1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def PPCTLSRegOperand : AsmOperandClass {
43 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
44 let RenderMethod = "addTLSRegOperands";
46 def tlsreg : Operand<i64> {
47 let EncoderMethod = "getTLSRegEncoding";
48 let ParserMatchClass = PPCTLSRegOperand;
50 def tlsgd : Operand<i64> {}
51 def tlscall : Operand<i64> {
52 let PrintMethod = "printTLSCall";
53 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
54 let EncoderMethod = "getTLSCallEncoding";
57 //===----------------------------------------------------------------------===//
58 // 64-bit transformation functions.
61 def SHL64 : SDNodeXForm<imm, [{
62 // Transformation function: 63 - imm
63 return getI32Imm(63 - N->getZExtValue());
66 def SRL64 : SDNodeXForm<imm, [{
67 // Transformation function: 64 - imm
68 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
71 def HI32_48 : SDNodeXForm<imm, [{
72 // Transformation function: shift the immediate value down into the low bits.
73 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
76 def HI48_64 : SDNodeXForm<imm, [{
77 // Transformation function: shift the immediate value down into the low bits.
78 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
82 //===----------------------------------------------------------------------===//
86 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
87 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
88 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
89 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
91 Requires<[In64BitMode]>;
92 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
93 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
95 Requires<[In64BitMode]>;
100 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
103 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
104 let Defs = [CTR8], Uses = [CTR8] in {
105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
111 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
113 "bdzlr", IIC_BrB, []>;
114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
115 "bdnzlr", IIC_BrB, []>;
121 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
122 // Convenient aliases for call instructions
124 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
125 "bl $func", IIC_BrB, []>; // See Pat patterns below.
127 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
128 "bl $func", IIC_BrB, []>;
130 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
131 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
133 let Uses = [RM], isCodeGenOnly = 1 in {
134 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
135 (outs), (ins calltarget:$func),
136 "bl $func\n\tnop", IIC_BrB, []>;
138 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
139 (outs), (ins tlscall:$func),
140 "bl $func\n\tnop", IIC_BrB, []>;
142 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
143 (outs), (ins abscalltarget:$func),
144 "bla $func\n\tnop", IIC_BrB,
145 [(PPCcall_nop (i64 imm:$func))]>;
147 let Uses = [CTR8, RM] in {
148 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
149 "bctrl", IIC_BrB, [(PPCbctrl)]>,
150 Requires<[In64BitMode]>;
152 let isCodeGenOnly = 1 in
153 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
154 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
156 Requires<[In64BitMode]>;
159 } // Interpretation64Bit
161 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
162 // previous definition must be marked as CodeGen only to prevent decoding
164 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
165 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
166 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
167 "bl $func", IIC_BrB, []>;
170 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
171 (BL8 tglobaladdr:$dst)>;
172 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
173 (BL8_NOP tglobaladdr:$dst)>;
175 def : Pat<(PPCcall (i64 texternalsym:$dst)),
176 (BL8 texternalsym:$dst)>;
177 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
178 (BL8_NOP texternalsym:$dst)>;
181 let usesCustomInserter = 1 in {
182 let Defs = [CR0] in {
183 def ATOMIC_LOAD_ADD_I64 : Pseudo<
184 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
185 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
186 def ATOMIC_LOAD_SUB_I64 : Pseudo<
187 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
188 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
189 def ATOMIC_LOAD_OR_I64 : Pseudo<
190 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
191 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
192 def ATOMIC_LOAD_XOR_I64 : Pseudo<
193 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
194 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
195 def ATOMIC_LOAD_AND_I64 : Pseudo<
196 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
197 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
198 def ATOMIC_LOAD_NAND_I64 : Pseudo<
199 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
200 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
202 def ATOMIC_CMP_SWAP_I64 : Pseudo<
203 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
204 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
206 def ATOMIC_SWAP_I64 : Pseudo<
207 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
208 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
212 // Instructions to support atomic operations
213 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
214 "ldarx $rD, $ptr", IIC_LdStLDARX,
215 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
218 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
219 "stdcx. $rS, $dst", IIC_LdStSTDCX,
220 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
223 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
224 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
225 def TCRETURNdi8 :Pseudo< (outs),
226 (ins calltarget:$dst, i32imm:$offset),
227 "#TC_RETURNd8 $dst $offset",
230 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
231 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
232 "#TC_RETURNa8 $func $offset",
233 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
235 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
236 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
237 "#TC_RETURNr8 $dst $offset",
240 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
241 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
242 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
244 Requires<[In64BitMode]>;
246 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
247 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
248 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
252 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
253 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
254 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
257 } // Interpretation64Bit
259 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
260 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
262 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
263 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
265 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
266 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
269 // 64-bit CR instructions
270 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
271 let neverHasSideEffects = 1 in {
272 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
273 "mtocrf $FXM, $ST", IIC_BrMCRX>,
274 PPC970_DGroup_First, PPC970_Unit_CRU;
276 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
277 "mtcrf $FXM, $rS", IIC_BrMCRX>,
278 PPC970_MicroCode, PPC970_Unit_CRU;
280 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
281 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
282 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
283 PPC970_DGroup_First, PPC970_Unit_CRU;
285 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
286 "mfcr $rT", IIC_SprMFCR>,
287 PPC970_MicroCode, PPC970_Unit_CRU;
288 } // neverHasSideEffects = 1
290 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
292 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
294 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
295 Requires<[In64BitMode]>;
296 let isTerminator = 1 in
297 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
298 "#EH_SJLJ_LONGJMP64",
299 [(PPCeh_sjlj_longjmp addr:$buf)]>,
300 Requires<[In64BitMode]>;
303 //===----------------------------------------------------------------------===//
304 // 64-bit SPR manipulation instrs.
306 let Uses = [CTR8] in {
307 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
308 "mfctr $rT", IIC_SprMFSPR>,
309 PPC970_DGroup_First, PPC970_Unit_FXU;
311 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
312 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
313 "mtctr $rS", IIC_SprMTSPR>,
314 PPC970_DGroup_First, PPC970_Unit_FXU;
316 let hasSideEffects = 1, Defs = [CTR8] in {
317 let Pattern = [(int_ppc_mtctr i64:$rS)] in
318 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
319 "mtctr $rS", IIC_SprMTSPR>,
320 PPC970_DGroup_First, PPC970_Unit_FXU;
323 let Pattern = [(set i64:$rT, readcyclecounter)] in
324 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
325 "mfspr $rT, 268", IIC_SprMFTB>,
326 PPC970_DGroup_First, PPC970_Unit_FXU;
327 // Note that encoding mftb using mfspr is now the preferred form,
328 // and has been since at least ISA v2.03. The mftb instruction has
329 // now been phased out. Using mfspr, however, is known not to work on
332 let Defs = [X1], Uses = [X1] in
333 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
335 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
337 let Defs = [LR8] in {
338 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
339 "mtlr $rS", IIC_SprMTSPR>,
340 PPC970_DGroup_First, PPC970_Unit_FXU;
342 let Uses = [LR8] in {
343 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
344 "mflr $rT", IIC_SprMFSPR>,
345 PPC970_DGroup_First, PPC970_Unit_FXU;
347 } // Interpretation64Bit
349 //===----------------------------------------------------------------------===//
350 // Fixed point instructions.
353 let PPC970_Unit = 1 in { // FXU Operations.
354 let Interpretation64Bit = 1 in {
355 let neverHasSideEffects = 1 in {
356 let isCodeGenOnly = 1 in {
358 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
359 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
360 "li $rD, $imm", IIC_IntSimple,
361 [(set i64:$rD, imm64SExt16:$imm)]>;
362 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
363 "lis $rD, $imm", IIC_IntSimple,
364 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
368 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
369 "nand", "$rA, $rS, $rB", IIC_IntSimple,
370 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
371 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
372 "and", "$rA, $rS, $rB", IIC_IntSimple,
373 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
374 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
375 "andc", "$rA, $rS, $rB", IIC_IntSimple,
376 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
377 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
378 "or", "$rA, $rS, $rB", IIC_IntSimple,
379 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
380 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
381 "nor", "$rA, $rS, $rB", IIC_IntSimple,
382 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
383 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
384 "orc", "$rA, $rS, $rB", IIC_IntSimple,
385 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
386 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
387 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
388 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
389 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
390 "xor", "$rA, $rS, $rB", IIC_IntSimple,
391 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
393 // Logical ops with immediate.
394 let Defs = [CR0] in {
395 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
396 "andi. $dst, $src1, $src2", IIC_IntGeneral,
397 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
399 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
400 "andis. $dst, $src1, $src2", IIC_IntGeneral,
401 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
404 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
405 "ori $dst, $src1, $src2", IIC_IntSimple,
406 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
407 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
408 "oris $dst, $src1, $src2", IIC_IntSimple,
409 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
410 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
411 "xori $dst, $src1, $src2", IIC_IntSimple,
412 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
413 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
414 "xoris $dst, $src1, $src2", IIC_IntSimple,
415 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
417 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
418 "add", "$rT, $rA, $rB", IIC_IntSimple,
419 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
420 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
421 // initial-exec thread-local storage model.
422 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
423 "add $rT, $rA, $rB", IIC_IntSimple,
424 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
426 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
427 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
428 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
429 PPC970_DGroup_Cracked;
430 let Defs = [CARRY] in
431 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
432 "addic $rD, $rA, $imm", IIC_IntGeneral,
433 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
434 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
435 "addi $rD, $rA, $imm", IIC_IntSimple,
436 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
437 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
438 "addis $rD, $rA, $imm", IIC_IntSimple,
439 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
441 let Defs = [CARRY] in {
442 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
443 "subfic $rD, $rA, $imm", IIC_IntGeneral,
444 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
445 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
446 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
447 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
448 PPC970_DGroup_Cracked;
450 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
451 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
452 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
453 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
454 "neg", "$rT, $rA", IIC_IntSimple,
455 [(set i64:$rT, (ineg i64:$rA))]>;
456 let Uses = [CARRY] in {
457 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
458 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
459 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
460 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
461 "addme", "$rT, $rA", IIC_IntGeneral,
462 [(set i64:$rT, (adde i64:$rA, -1))]>;
463 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
464 "addze", "$rT, $rA", IIC_IntGeneral,
465 [(set i64:$rT, (adde i64:$rA, 0))]>;
466 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
467 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
468 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
469 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
470 "subfme", "$rT, $rA", IIC_IntGeneral,
471 [(set i64:$rT, (sube -1, i64:$rA))]>;
472 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
473 "subfze", "$rT, $rA", IIC_IntGeneral,
474 [(set i64:$rT, (sube 0, i64:$rA))]>;
478 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
479 // previous definition must be marked as CodeGen only to prevent decoding
481 let isAsmParserOnly = 1 in
482 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
483 "add $rT, $rA, $rB", IIC_IntSimple, []>;
485 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
486 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
487 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
488 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
489 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
490 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
492 } // Interpretation64Bit
494 let isCompare = 1, neverHasSideEffects = 1 in {
495 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
496 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
497 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
498 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
499 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
500 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
501 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
502 "cmpldi $dst, $src1, $src2",
503 IIC_IntCompare>, isPPC64;
506 let neverHasSideEffects = 1 in {
507 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
508 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
509 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
510 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
511 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
512 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
513 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
514 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
515 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
517 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
518 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
519 "extsb", "$rA, $rS", IIC_IntSimple,
520 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
521 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
522 "extsh", "$rA, $rS", IIC_IntSimple,
523 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
524 } // Interpretation64Bit
527 let isCodeGenOnly = 1 in {
528 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
529 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
530 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
531 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
532 } // isCodeGenOnly for fast-isel
534 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
535 "extsw", "$rA, $rS", IIC_IntSimple,
536 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
537 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
538 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
539 "extsw", "$rA, $rS", IIC_IntSimple,
540 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
542 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
543 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
544 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
545 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
546 "cntlzd", "$rA, $rS", IIC_IntGeneral,
547 [(set i64:$rA, (ctlz i64:$rS))]>;
548 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
549 "popcntd $rA, $rS", IIC_IntGeneral,
550 [(set i64:$rA, (ctpop i64:$rS))]>;
552 // popcntw also does a population count on the high 32 bits (storing the
553 // results in the high 32-bits of the output). We'll ignore that here (which is
554 // safe because we never separately use the high part of the 64-bit registers).
555 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
556 "popcntw $rA, $rS", IIC_IntGeneral,
557 [(set i32:$rA, (ctpop i32:$rS))]>;
559 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
560 "divd", "$rT, $rA, $rB", IIC_IntDivD,
561 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
562 PPC970_DGroup_First, PPC970_DGroup_Cracked;
563 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
564 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
565 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
566 PPC970_DGroup_First, PPC970_DGroup_Cracked;
567 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
568 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
569 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
570 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
571 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
572 "mulli $rD, $rA, $imm", IIC_IntMulLI,
573 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
576 let neverHasSideEffects = 1 in {
577 let isCommutable = 1 in {
578 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
579 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
580 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
581 []>, isPPC64, RegConstraint<"$rSi = $rA">,
585 // Rotate instructions.
586 defm RLDCL : MDSForm_1r<30, 8,
587 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
588 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
590 defm RLDCR : MDSForm_1r<30, 9,
591 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
592 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
594 defm RLDICL : MDForm_1r<30, 0,
595 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
596 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
599 let isCodeGenOnly = 1 in
600 def RLDICL_32_64 : MDForm_1<30, 0,
602 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
603 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
606 defm RLDICR : MDForm_1r<30, 1,
607 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
608 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
610 defm RLDIC : MDForm_1r<30, 2,
611 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
612 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
615 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
616 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
617 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
618 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
622 def ISEL8 : AForm_4<31, 15,
623 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
624 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
626 } // Interpretation64Bit
627 } // neverHasSideEffects = 1
628 } // End FXU Operations.
631 //===----------------------------------------------------------------------===//
632 // Load/Store instructions.
636 // Sign extending loads.
637 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
638 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
639 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
640 "lha $rD, $src", IIC_LdStLHA,
641 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
642 PPC970_DGroup_Cracked;
643 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
644 "lwa $rD, $src", IIC_LdStLWA,
646 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
647 PPC970_DGroup_Cracked;
648 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
649 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
650 "lhax $rD, $src", IIC_LdStLHA,
651 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
652 PPC970_DGroup_Cracked;
653 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
654 "lwax $rD, $src", IIC_LdStLHA,
655 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
656 PPC970_DGroup_Cracked;
658 let isCodeGenOnly = 1, mayLoad = 1 in {
659 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
660 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
661 PPC970_DGroup_Cracked;
662 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
663 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
664 PPC970_DGroup_Cracked;
665 } // end fast-isel isCodeGenOnly
668 let mayLoad = 1, neverHasSideEffects = 1 in {
669 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
670 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
672 "lhau $rD, $addr", IIC_LdStLHAU,
673 []>, RegConstraint<"$addr.reg = $ea_result">,
674 NoEncode<"$ea_result">;
677 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
678 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
680 "lhaux $rD, $addr", IIC_LdStLHAUX,
681 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
682 NoEncode<"$ea_result">;
683 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
685 "lwaux $rD, $addr", IIC_LdStLHAUX,
686 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
687 NoEncode<"$ea_result">, isPPC64;
691 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
692 // Zero extending loads.
693 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
694 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
695 "lbz $rD, $src", IIC_LdStLoad,
696 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
697 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
698 "lhz $rD, $src", IIC_LdStLoad,
699 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
700 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
701 "lwz $rD, $src", IIC_LdStLoad,
702 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
704 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
705 "lbzx $rD, $src", IIC_LdStLoad,
706 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
707 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
708 "lhzx $rD, $src", IIC_LdStLoad,
709 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
710 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
711 "lwzx $rD, $src", IIC_LdStLoad,
712 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
716 let mayLoad = 1, neverHasSideEffects = 1 in {
717 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
718 "lbzu $rD, $addr", IIC_LdStLoadUpd,
719 []>, RegConstraint<"$addr.reg = $ea_result">,
720 NoEncode<"$ea_result">;
721 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
722 "lhzu $rD, $addr", IIC_LdStLoadUpd,
723 []>, RegConstraint<"$addr.reg = $ea_result">,
724 NoEncode<"$ea_result">;
725 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
726 "lwzu $rD, $addr", IIC_LdStLoadUpd,
727 []>, RegConstraint<"$addr.reg = $ea_result">,
728 NoEncode<"$ea_result">;
730 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
732 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
733 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
734 NoEncode<"$ea_result">;
735 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
737 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
738 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
739 NoEncode<"$ea_result">;
740 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
742 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
743 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
744 NoEncode<"$ea_result">;
747 } // Interpretation64Bit
750 // Full 8-byte loads.
751 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
752 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
753 "ld $rD, $src", IIC_LdStLD,
754 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
755 // The following three definitions are selected for small code model only.
756 // Otherwise, we need to create two instructions to form a 32-bit offset,
757 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
758 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
761 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
762 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
765 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
766 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
769 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
771 let hasSideEffects = 1, isCodeGenOnly = 1 in {
772 let RST = 2, DS = 2 in
773 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
774 "ld 2, 8($reg)", IIC_LdStLD,
775 [(PPCload_toc i64:$reg)]>, isPPC64;
777 let RST = 2, DS = 10, RA = 1 in
778 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
779 "ld 2, 40(1)", IIC_LdStLD,
780 [(PPCtoc_restore)]>, isPPC64;
782 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
783 "ldx $rD, $src", IIC_LdStLD,
784 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
785 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
786 "ldbrx $rD, $src", IIC_LdStLoad,
787 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
789 let mayLoad = 1, neverHasSideEffects = 1 in {
790 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
791 "ldu $rD, $addr", IIC_LdStLDU,
792 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
793 NoEncode<"$ea_result">;
795 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
797 "ldux $rD, $addr", IIC_LdStLDUX,
798 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
799 NoEncode<"$ea_result">, isPPC64;
803 def : Pat<(PPCload ixaddr:$src),
805 def : Pat<(PPCload xaddr:$src),
808 // Support for medium and large code model.
809 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
812 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
814 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
817 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
818 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
821 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
823 // Support for thread-local storage.
824 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
827 (PPCaddisGotTprelHA i64:$reg,
828 tglobaltlsaddr:$disp))]>,
830 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
833 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
835 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
836 (ADD8TLS $in, tglobaltlsaddr:$g)>;
837 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
840 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
842 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
845 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
847 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
850 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
852 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
855 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
857 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
860 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
862 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
865 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
867 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
870 (PPCaddisDtprelHA i64:$reg,
871 tglobaltlsaddr:$disp))]>,
873 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
876 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
879 let PPC970_Unit = 2 in {
880 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
881 // Truncating stores.
882 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
883 "stb $rS, $src", IIC_LdStStore,
884 [(truncstorei8 i64:$rS, iaddr:$src)]>;
885 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
886 "sth $rS, $src", IIC_LdStStore,
887 [(truncstorei16 i64:$rS, iaddr:$src)]>;
888 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
889 "stw $rS, $src", IIC_LdStStore,
890 [(truncstorei32 i64:$rS, iaddr:$src)]>;
891 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
892 "stbx $rS, $dst", IIC_LdStStore,
893 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
894 PPC970_DGroup_Cracked;
895 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
896 "sthx $rS, $dst", IIC_LdStStore,
897 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
898 PPC970_DGroup_Cracked;
899 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
900 "stwx $rS, $dst", IIC_LdStStore,
901 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
902 PPC970_DGroup_Cracked;
903 } // Interpretation64Bit
905 // Normal 8-byte stores.
906 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
907 "std $rS, $dst", IIC_LdStSTD,
908 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
909 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
910 "stdx $rS, $dst", IIC_LdStSTD,
911 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
912 PPC970_DGroup_Cracked;
913 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
914 "stdbrx $rS, $dst", IIC_LdStStore,
915 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
916 PPC970_DGroup_Cracked;
919 // Stores with Update (pre-inc).
920 let PPC970_Unit = 2, mayStore = 1 in {
921 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
922 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
923 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
924 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
925 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
926 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
927 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
928 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
929 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
930 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
932 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
933 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
934 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
935 PPC970_DGroup_Cracked;
936 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
937 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
938 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
939 PPC970_DGroup_Cracked;
940 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
941 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
942 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
943 PPC970_DGroup_Cracked;
944 } // Interpretation64Bit
946 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
947 "stdu $rS, $dst", IIC_LdStSTDU, []>,
948 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
951 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
952 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
953 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
954 PPC970_DGroup_Cracked, isPPC64;
957 // Patterns to match the pre-inc stores. We can't put the patterns on
958 // the instruction definitions directly as ISel wants the address base
959 // and offset to be separate operands, not a single complex operand.
960 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
961 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
962 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
963 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
964 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
965 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
966 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
967 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
969 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
970 (STBUX8 $rS, $ptrreg, $ptroff)>;
971 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
972 (STHUX8 $rS, $ptrreg, $ptroff)>;
973 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
974 (STWUX8 $rS, $ptrreg, $ptroff)>;
975 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
976 (STDUX $rS, $ptrreg, $ptroff)>;
979 //===----------------------------------------------------------------------===//
980 // Floating point instructions.
984 let PPC970_Unit = 3, neverHasSideEffects = 1,
985 Uses = [RM] in { // FPU Operations.
986 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
987 "fcfid", "$frD, $frB", IIC_FPGeneral,
988 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
989 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
990 "fctid", "$frD, $frB", IIC_FPGeneral,
992 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
993 "fctidz", "$frD, $frB", IIC_FPGeneral,
994 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
996 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
997 "fcfidu", "$frD, $frB", IIC_FPGeneral,
998 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
999 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
1000 "fcfids", "$frD, $frB", IIC_FPGeneral,
1001 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
1002 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
1003 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1004 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1005 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1006 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1007 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1008 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1009 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1010 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1014 //===----------------------------------------------------------------------===//
1015 // Instruction Patterns
1018 // Extensions and truncates to/from 32-bit regs.
1019 def : Pat<(i64 (zext i32:$in)),
1020 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1022 def : Pat<(i64 (anyext i32:$in)),
1023 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1024 def : Pat<(i32 (trunc i64:$in)),
1025 (EXTRACT_SUBREG $in, sub_32)>;
1027 // Extending loads with i64 targets.
1028 def : Pat<(zextloadi1 iaddr:$src),
1030 def : Pat<(zextloadi1 xaddr:$src),
1031 (LBZX8 xaddr:$src)>;
1032 def : Pat<(extloadi1 iaddr:$src),
1034 def : Pat<(extloadi1 xaddr:$src),
1035 (LBZX8 xaddr:$src)>;
1036 def : Pat<(extloadi8 iaddr:$src),
1038 def : Pat<(extloadi8 xaddr:$src),
1039 (LBZX8 xaddr:$src)>;
1040 def : Pat<(extloadi16 iaddr:$src),
1042 def : Pat<(extloadi16 xaddr:$src),
1043 (LHZX8 xaddr:$src)>;
1044 def : Pat<(extloadi32 iaddr:$src),
1046 def : Pat<(extloadi32 xaddr:$src),
1047 (LWZX8 xaddr:$src)>;
1049 // Standard shifts. These are represented separately from the real shifts above
1050 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1052 def : Pat<(sra i64:$rS, i32:$rB),
1054 def : Pat<(srl i64:$rS, i32:$rB),
1056 def : Pat<(shl i64:$rS, i32:$rB),
1060 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1061 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1062 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1063 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1066 def : Pat<(rotl i64:$in, i32:$sh),
1067 (RLDCL $in, $sh, 0)>;
1068 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1069 (RLDICL $in, imm:$imm, 0)>;
1071 // Hi and Lo for Darwin Global Addresses.
1072 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1073 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1074 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1075 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1076 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1077 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1078 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1079 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1080 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1081 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1082 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1083 (ADDI8 $in, tglobaltlsaddr:$g)>;
1084 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1085 (ADDIS8 $in, tglobaladdr:$g)>;
1086 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1087 (ADDIS8 $in, tconstpool:$g)>;
1088 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1089 (ADDIS8 $in, tjumptable:$g)>;
1090 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1091 (ADDIS8 $in, tblockaddress:$g)>;
1093 // Patterns to match r+r indexed loads and stores for
1094 // addresses without at least 4-byte alignment.
1095 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1096 (LWAX xoaddr:$src)>;
1097 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1099 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1100 (STDX $rS, xoaddr:$dst)>;