1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
32 def tocentry : Operand<iPTR> {
33 let MIOperandInfo = (ops i64imm:$imm);
35 def tlsreg : Operand<i64> {
36 let EncoderMethod = "getTLSRegEncoding";
38 def tlsgd : Operand<i64> {}
40 //===----------------------------------------------------------------------===//
41 // 64-bit transformation functions.
44 def SHL64 : SDNodeXForm<imm, [{
45 // Transformation function: 63 - imm
46 return getI32Imm(63 - N->getZExtValue());
49 def SRL64 : SDNodeXForm<imm, [{
50 // Transformation function: 64 - imm
51 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
54 def HI32_48 : SDNodeXForm<imm, [{
55 // Transformation function: shift the immediate value down into the low bits.
56 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
59 def HI48_64 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
65 //===----------------------------------------------------------------------===//
69 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
70 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in
71 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
72 Requires<[In64BitMode]>;
76 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
79 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
80 let Defs = [CTR8], Uses = [CTR8] in {
81 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
83 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
88 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
89 // Convenient aliases for call instructions
91 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
92 "bl $func", BrB, []>; // See Pat patterns below.
94 def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func),
95 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
97 let Uses = [RM], isCodeGenOnly = 1 in {
98 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
99 (outs), (ins calltarget:$func),
100 "bl $func\n\tnop", BrB, []>;
102 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24,
103 (outs), (ins calltarget:$func, tlsgd:$sym),
104 "bl $func($sym)\n\tnop", BrB, []>;
106 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24,
107 (outs), (ins calltarget:$func, tlsgd:$sym),
108 "bl $func($sym)\n\tnop", BrB, []>;
110 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
111 (outs), (ins aaddr:$func),
112 "bla $func\n\tnop", BrB,
113 [(PPCcall_nop (i64 imm:$func))]>;
115 let Uses = [CTR8, RM] in {
116 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
117 "bctrl", BrB, [(PPCbctrl)]>,
118 Requires<[In64BitMode]>;
124 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
125 (BL8 tglobaladdr:$dst)>;
126 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
127 (BL8_NOP tglobaladdr:$dst)>;
129 def : Pat<(PPCcall (i64 texternalsym:$dst)),
130 (BL8 texternalsym:$dst)>;
131 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
132 (BL8_NOP texternalsym:$dst)>;
135 let usesCustomInserter = 1 in {
136 let Defs = [CR0] in {
137 def ATOMIC_LOAD_ADD_I64 : Pseudo<
138 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
139 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
140 def ATOMIC_LOAD_SUB_I64 : Pseudo<
141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
142 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
143 def ATOMIC_LOAD_OR_I64 : Pseudo<
144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
145 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
146 def ATOMIC_LOAD_XOR_I64 : Pseudo<
147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
148 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
149 def ATOMIC_LOAD_AND_I64 : Pseudo<
150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
151 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
152 def ATOMIC_LOAD_NAND_I64 : Pseudo<
153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
154 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
156 def ATOMIC_CMP_SWAP_I64 : Pseudo<
157 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
158 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
160 def ATOMIC_SWAP_I64 : Pseudo<
161 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
162 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
166 // Instructions to support atomic operations
167 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
168 "ldarx $rD, $ptr", LdStLDARX,
169 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
172 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
173 "stdcx. $rS, $dst", LdStSTDCX,
174 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
178 def TCRETURNdi8 :Pseudo< (outs),
179 (ins calltarget:$dst, i32imm:$offset),
180 "#TC_RETURNd8 $dst $offset",
183 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
184 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
185 "#TC_RETURNa8 $func $offset",
186 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
188 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
189 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
190 "#TC_RETURNr8 $dst $offset",
193 let isCodeGenOnly = 1 in {
195 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
196 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
197 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
198 Requires<[In64BitMode]>;
201 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
202 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
203 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
208 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
209 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
210 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
216 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
217 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
219 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
220 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
222 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
223 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
226 // 64-bit CR instructions
227 let neverHasSideEffects = 1 in {
228 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
229 "mtcrf $FXM, $rS", BrMCRX>,
230 PPC970_MicroCode, PPC970_Unit_CRU;
232 let isCodeGenOnly = 1 in
233 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
234 "#MFCR8pseud", SprMFCR>,
235 PPC970_MicroCode, PPC970_Unit_CRU;
236 } // neverHasSideEffects = 1
238 // MFCR uses all CR registers, but marking that explicitly causes
239 // problems because some of them appear to be undefined. Because
240 // this form is used only in prologue code, just mark it as having
242 let /* Uses = [CR0, CR1, CR2, CR3, CR4, CR5, CR6] */ hasSideEffects = 1 in
243 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
244 "mfcr $rT", SprMFCR>,
245 PPC970_MicroCode, PPC970_Unit_CRU;
247 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
248 def EH_SjLj_SetJmp64 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
250 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
251 Requires<[In64BitMode]>;
252 let isTerminator = 1 in
253 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
254 "#EH_SJLJ_LONGJMP64",
255 [(PPCeh_sjlj_longjmp addr:$buf)]>,
256 Requires<[In64BitMode]>;
259 //===----------------------------------------------------------------------===//
260 // 64-bit SPR manipulation instrs.
262 let Uses = [CTR8] in {
263 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
264 "mfctr $rT", SprMFSPR>,
265 PPC970_DGroup_First, PPC970_Unit_FXU;
267 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
268 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
269 "mtctr $rS", SprMTSPR>,
270 PPC970_DGroup_First, PPC970_Unit_FXU;
273 let Pattern = [(set i64:$rT, readcyclecounter)] in
274 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
275 "mfspr $rT, 268", SprMFTB>,
276 PPC970_DGroup_First, PPC970_Unit_FXU;
277 // Note that encoding mftb using mfspr is now the preferred form,
278 // and has been since at least ISA v2.03. The mftb instruction has
279 // now been phased out. Using mfspr, however, is known not to work on
282 let Defs = [X1], Uses = [X1] in
283 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
285 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
287 let Defs = [LR8] in {
288 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
289 "mtlr $rS", SprMTSPR>,
290 PPC970_DGroup_First, PPC970_Unit_FXU;
292 let Uses = [LR8] in {
293 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
294 "mflr $rT", SprMFSPR>,
295 PPC970_DGroup_First, PPC970_Unit_FXU;
298 //===----------------------------------------------------------------------===//
299 // Fixed point instructions.
302 let PPC970_Unit = 1 in { // FXU Operations.
304 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
305 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
306 "li $rD, $imm", IntSimple,
307 [(set i64:$rD, immSExt16:$imm)]>;
308 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
309 "lis $rD, $imm", IntSimple,
310 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
314 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
315 "nand $rA, $rS, $rB", IntSimple,
316 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
317 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
318 "and $rA, $rS, $rB", IntSimple,
319 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
320 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
321 "andc $rA, $rS, $rB", IntSimple,
322 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
323 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
324 "or $rA, $rS, $rB", IntSimple,
325 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
326 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
327 "nor $rA, $rS, $rB", IntSimple,
328 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
329 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
330 "orc $rA, $rS, $rB", IntSimple,
331 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
332 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
333 "eqv $rA, $rS, $rB", IntSimple,
334 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
335 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
336 "xor $rA, $rS, $rB", IntSimple,
337 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
339 // Logical ops with immediate.
340 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
341 "andi. $dst, $src1, $src2", IntGeneral,
342 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
344 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
345 "andis. $dst, $src1, $src2", IntGeneral,
346 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
348 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
349 "ori $dst, $src1, $src2", IntSimple,
350 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
351 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
352 "oris $dst, $src1, $src2", IntSimple,
353 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
354 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
355 "xori $dst, $src1, $src2", IntSimple,
356 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
357 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
358 "xoris $dst, $src1, $src2", IntSimple,
359 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
361 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
362 "add $rT, $rA, $rB", IntSimple,
363 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
364 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
365 // initial-exec thread-local storage model.
366 let isCodeGenOnly = 1 in
367 def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB),
368 "add $rT, $rA, $rB@tls", IntSimple,
369 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
371 let Defs = [CARRY] in {
372 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
373 "addc $rT, $rA, $rB", IntGeneral,
374 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
375 PPC970_DGroup_Cracked;
376 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
377 "addic $rD, $rA, $imm", IntGeneral,
378 [(set i64:$rD, (addc i64:$rA, immSExt16:$imm))]>;
380 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolLo64:$imm),
381 "addi $rD, $rA, $imm", IntSimple,
382 [(set i64:$rD, (add i64:$rA, immSExt16:$imm))]>;
383 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolHi64:$imm),
384 "addis $rD, $rA, $imm", IntSimple,
385 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
387 let Defs = [CARRY] in {
388 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
389 "subfic $rD, $rA, $imm", IntGeneral,
390 [(set i64:$rD, (subc immSExt16:$imm, i64:$rA))]>;
391 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
392 "subfc $rT, $rA, $rB", IntGeneral,
393 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
394 PPC970_DGroup_Cracked;
396 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
397 "subf $rT, $rA, $rB", IntGeneral,
398 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
399 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
400 "neg $rT, $rA", IntSimple,
401 [(set i64:$rT, (ineg i64:$rA))]>;
402 let Uses = [CARRY], Defs = [CARRY] in {
403 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
404 "adde $rT, $rA, $rB", IntGeneral,
405 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
406 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
407 "addme $rT, $rA", IntGeneral,
408 [(set i64:$rT, (adde i64:$rA, -1))]>;
409 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
410 "addze $rT, $rA", IntGeneral,
411 [(set i64:$rT, (adde i64:$rA, 0))]>;
412 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
413 "subfe $rT, $rA, $rB", IntGeneral,
414 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
415 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
416 "subfme $rT, $rA", IntGeneral,
417 [(set i64:$rT, (sube -1, i64:$rA))]>;
418 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
419 "subfze $rT, $rA", IntGeneral,
420 [(set i64:$rT, (sube 0, i64:$rA))]>;
424 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
425 "mulhd $rT, $rA, $rB", IntMulHW,
426 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
427 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
428 "mulhdu $rT, $rA, $rB", IntMulHWU,
429 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
431 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
432 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
433 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
434 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
435 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
436 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
437 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
438 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
440 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
441 "sld $rA, $rS, $rB", IntRotateD,
442 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
443 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
444 "srd $rA, $rS, $rB", IntRotateD,
445 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
446 let Defs = [CARRY] in {
447 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
448 "srad $rA, $rS, $rB", IntRotateD,
449 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
452 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
453 "extsb $rA, $rS", IntSimple,
454 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
455 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
456 "extsh $rA, $rS", IntSimple,
457 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
459 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
460 "extsw $rA, $rS", IntSimple,
461 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
462 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
463 "extsw $rA, $rS", IntSimple,
464 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
466 let Defs = [CARRY] in {
467 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
468 "sradi $rA, $rS, $SH", IntRotateDI,
469 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
471 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
472 "cntlzd $rA, $rS", IntGeneral,
473 [(set i64:$rA, (ctlz i64:$rS))]>;
474 def POPCNTD : XForm_11<31, 506, (outs G8RC:$rA), (ins G8RC:$rS),
475 "popcntd $rA, $rS", IntGeneral,
476 [(set i64:$rA, (ctpop i64:$rS))]>;
478 // popcntw also does a population count on the high 32 bits (storing the
479 // results in the high 32-bits of the output). We'll ignore that here (which is
480 // safe because we never separately use the high part of the 64-bit registers).
481 def POPCNTW : XForm_11<31, 378, (outs GPRC:$rA), (ins GPRC:$rS),
482 "popcntw $rA, $rS", IntGeneral,
483 [(set i32:$rA, (ctpop i32:$rS))]>;
485 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
486 "divd $rT, $rA, $rB", IntDivD,
487 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
488 PPC970_DGroup_First, PPC970_DGroup_Cracked;
489 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
490 "divdu $rT, $rA, $rB", IntDivD,
491 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
492 PPC970_DGroup_First, PPC970_DGroup_Cracked;
493 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
494 "mulld $rT, $rA, $rB", IntMulHD,
495 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
498 let neverHasSideEffects = 1 in {
499 let isCommutable = 1 in {
500 def RLDIMI : MDForm_1<30, 3,
501 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
502 "rldimi $rA, $rS, $SH, $MB", IntRotateDI,
503 []>, isPPC64, RegConstraint<"$rSi = $rA">,
507 // Rotate instructions.
508 def RLDCL : MDForm_1<30, 0,
509 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
510 "rldcl $rA, $rS, $rB, $MBE", IntRotateD,
512 def RLDICL : MDForm_1<30, 0,
513 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
514 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
516 def RLDICR : MDForm_1<30, 1,
517 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
518 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI,
521 def RLWINM8 : MForm_2<21,
522 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
523 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
527 def ISEL8 : AForm_4<31, 15,
528 (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, CRBITRC:$cond),
529 "isel $rT, $rA, $rB, $cond", IntGeneral,
531 } // neverHasSideEffects = 1
532 } // End FXU Operations.
535 //===----------------------------------------------------------------------===//
536 // Load/Store instructions.
540 // Sign extending loads.
541 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
542 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
543 "lha $rD, $src", LdStLHA,
544 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
545 PPC970_DGroup_Cracked;
546 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
547 "lwa $rD, $src", LdStLWA,
549 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
550 PPC970_DGroup_Cracked;
551 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
552 "lhax $rD, $src", LdStLHA,
553 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
554 PPC970_DGroup_Cracked;
555 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
556 "lwax $rD, $src", LdStLHA,
557 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
558 PPC970_DGroup_Cracked;
561 let mayLoad = 1, neverHasSideEffects = 1 in {
562 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
564 "lhau $rD, $addr", LdStLHAU,
565 []>, RegConstraint<"$addr.reg = $ea_result">,
566 NoEncode<"$ea_result">;
569 def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
571 "lhaux $rD, $addr", LdStLHAU,
572 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
573 NoEncode<"$ea_result">;
574 def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
576 "lwaux $rD, $addr", LdStLHAU,
577 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
578 NoEncode<"$ea_result">, isPPC64;
582 // Zero extending loads.
583 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
584 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
585 "lbz $rD, $src", LdStLoad,
586 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
587 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
588 "lhz $rD, $src", LdStLoad,
589 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
590 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
591 "lwz $rD, $src", LdStLoad,
592 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
594 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
595 "lbzx $rD, $src", LdStLoad,
596 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
597 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
598 "lhzx $rD, $src", LdStLoad,
599 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
600 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
601 "lwzx $rD, $src", LdStLoad,
602 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
606 let mayLoad = 1, neverHasSideEffects = 1 in {
607 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
608 "lbzu $rD, $addr", LdStLoadUpd,
609 []>, RegConstraint<"$addr.reg = $ea_result">,
610 NoEncode<"$ea_result">;
611 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
612 "lhzu $rD, $addr", LdStLoadUpd,
613 []>, RegConstraint<"$addr.reg = $ea_result">,
614 NoEncode<"$ea_result">;
615 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
616 "lwzu $rD, $addr", LdStLoadUpd,
617 []>, RegConstraint<"$addr.reg = $ea_result">,
618 NoEncode<"$ea_result">;
620 def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
622 "lbzux $rD, $addr", LdStLoadUpd,
623 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
624 NoEncode<"$ea_result">;
625 def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
627 "lhzux $rD, $addr", LdStLoadUpd,
628 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
629 NoEncode<"$ea_result">;
630 def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
632 "lwzux $rD, $addr", LdStLoadUpd,
633 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
634 NoEncode<"$ea_result">;
639 // Full 8-byte loads.
640 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
641 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
642 "ld $rD, $src", LdStLD,
643 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
644 // The following three definitions are selected for small code model only.
645 // Otherwise, we need to create two instructions to form a 32-bit offset,
646 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
647 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
650 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
651 def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
654 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
655 def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
658 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
660 let hasSideEffects = 1, isCodeGenOnly = 1 in {
661 let RST = 2, DS = 2 in
662 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg),
663 "ld 2, 8($reg)", LdStLD,
664 [(PPCload_toc i64:$reg)]>, isPPC64;
666 let RST = 2, DS = 10, RA = 1 in
667 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
668 "ld 2, 40(1)", LdStLD,
669 [(PPCtoc_restore)]>, isPPC64;
671 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
672 "ldx $rD, $src", LdStLD,
673 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
674 def LDBRX : XForm_1<31, 532, (outs G8RC:$rD), (ins memrr:$src),
675 "ldbrx $rD, $src", LdStLoad,
676 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
678 let mayLoad = 1, neverHasSideEffects = 1 in {
679 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
680 "ldu $rD, $addr", LdStLDU,
681 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
682 NoEncode<"$ea_result">;
684 def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
686 "ldux $rD, $addr", LdStLDU,
687 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
688 NoEncode<"$ea_result">, isPPC64;
692 def : Pat<(PPCload ixaddr:$src),
694 def : Pat<(PPCload xaddr:$src),
697 // Support for medium and large code model.
698 def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, tocentry:$disp),
701 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
703 def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC_NOX0:$reg),
706 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
707 def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, tocentry:$disp),
710 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
712 // Support for thread-local storage.
713 def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
716 (PPCaddisGotTprelHA i64:$reg,
717 tglobaltlsaddr:$disp))]>,
719 def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC_NOX0:$reg),
722 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
724 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
725 (ADD8TLS $in, tglobaltlsaddr:$g)>;
726 def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
729 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
731 def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
734 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
736 def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
739 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
741 def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
744 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
746 def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
749 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
751 def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
754 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
756 def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
759 (PPCaddisDtprelHA i64:$reg,
760 tglobaltlsaddr:$disp))]>,
762 def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
765 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
768 let PPC970_Unit = 2 in {
769 // Truncating stores.
770 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
771 "stb $rS, $src", LdStStore,
772 [(truncstorei8 i64:$rS, iaddr:$src)]>;
773 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
774 "sth $rS, $src", LdStStore,
775 [(truncstorei16 i64:$rS, iaddr:$src)]>;
776 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
777 "stw $rS, $src", LdStStore,
778 [(truncstorei32 i64:$rS, iaddr:$src)]>;
779 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
780 "stbx $rS, $dst", LdStStore,
781 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
782 PPC970_DGroup_Cracked;
783 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
784 "sthx $rS, $dst", LdStStore,
785 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
786 PPC970_DGroup_Cracked;
787 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
788 "stwx $rS, $dst", LdStStore,
789 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
790 PPC970_DGroup_Cracked;
791 // Normal 8-byte stores.
792 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
793 "std $rS, $dst", LdStSTD,
794 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
795 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
796 "stdx $rS, $dst", LdStSTD,
797 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
798 PPC970_DGroup_Cracked;
799 def STDBRX: XForm_8<31, 660, (outs), (ins G8RC:$rS, memrr:$dst),
800 "stdbrx $rS, $dst", LdStStore,
801 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
802 PPC970_DGroup_Cracked;
805 // Stores with Update (pre-inc).
806 let PPC970_Unit = 2, mayStore = 1 in {
807 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
808 "stbu $rS, $dst", LdStStoreUpd, []>,
809 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
810 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
811 "sthu $rS, $dst", LdStStoreUpd, []>,
812 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
813 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
814 "stwu $rS, $dst", LdStStoreUpd, []>,
815 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
816 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst),
817 "stdu $rS, $dst", LdStSTDU, []>,
818 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
821 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
822 "stbux $rS, $dst", LdStStoreUpd, []>,
823 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
824 PPC970_DGroup_Cracked;
825 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
826 "sthux $rS, $dst", LdStStoreUpd, []>,
827 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
828 PPC970_DGroup_Cracked;
829 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
830 "stwux $rS, $dst", LdStStoreUpd, []>,
831 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
832 PPC970_DGroup_Cracked;
833 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
834 "stdux $rS, $dst", LdStSTDU, []>,
835 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
836 PPC970_DGroup_Cracked, isPPC64;
839 // Patterns to match the pre-inc stores. We can't put the patterns on
840 // the instruction definitions directly as ISel wants the address base
841 // and offset to be separate operands, not a single complex operand.
842 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
843 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
844 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
845 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
846 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
847 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
848 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
849 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
851 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
852 (STBUX8 $rS, $ptrreg, $ptroff)>;
853 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
854 (STHUX8 $rS, $ptrreg, $ptroff)>;
855 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
856 (STWUX8 $rS, $ptrreg, $ptroff)>;
857 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
858 (STDUX $rS, $ptrreg, $ptroff)>;
861 //===----------------------------------------------------------------------===//
862 // Floating point instructions.
866 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
867 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
868 "fcfid $frD, $frB", FPGeneral,
869 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
870 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
871 "fctidz $frD, $frB", FPGeneral,
872 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
874 def FCFIDU : XForm_26<63, 974, (outs F8RC:$frD), (ins F8RC:$frB),
875 "fcfidu $frD, $frB", FPGeneral,
876 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
877 def FCFIDS : XForm_26<59, 846, (outs F4RC:$frD), (ins F8RC:$frB),
878 "fcfids $frD, $frB", FPGeneral,
879 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
880 def FCFIDUS : XForm_26<59, 974, (outs F4RC:$frD), (ins F8RC:$frB),
881 "fcfidus $frD, $frB", FPGeneral,
882 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
883 def FCTIDUZ : XForm_26<63, 943, (outs F8RC:$frD), (ins F8RC:$frB),
884 "fctiduz $frD, $frB", FPGeneral,
885 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
886 def FCTIWUZ : XForm_26<63, 143, (outs F8RC:$frD), (ins F8RC:$frB),
887 "fctiwuz $frD, $frB", FPGeneral,
888 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
892 //===----------------------------------------------------------------------===//
893 // Instruction Patterns
896 // Extensions and truncates to/from 32-bit regs.
897 def : Pat<(i64 (zext i32:$in)),
898 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
900 def : Pat<(i64 (anyext i32:$in)),
901 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
902 def : Pat<(i32 (trunc i64:$in)),
903 (EXTRACT_SUBREG $in, sub_32)>;
905 // Extending loads with i64 targets.
906 def : Pat<(zextloadi1 iaddr:$src),
908 def : Pat<(zextloadi1 xaddr:$src),
910 def : Pat<(extloadi1 iaddr:$src),
912 def : Pat<(extloadi1 xaddr:$src),
914 def : Pat<(extloadi8 iaddr:$src),
916 def : Pat<(extloadi8 xaddr:$src),
918 def : Pat<(extloadi16 iaddr:$src),
920 def : Pat<(extloadi16 xaddr:$src),
922 def : Pat<(extloadi32 iaddr:$src),
924 def : Pat<(extloadi32 xaddr:$src),
927 // Standard shifts. These are represented separately from the real shifts above
928 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
930 def : Pat<(sra i64:$rS, i32:$rB),
932 def : Pat<(srl i64:$rS, i32:$rB),
934 def : Pat<(shl i64:$rS, i32:$rB),
938 def : Pat<(shl i64:$in, (i32 imm:$imm)),
939 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
940 def : Pat<(srl i64:$in, (i32 imm:$imm)),
941 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
944 def : Pat<(rotl i64:$in, i32:$sh),
945 (RLDCL $in, $sh, 0)>;
946 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
947 (RLDICL $in, imm:$imm, 0)>;
949 // Hi and Lo for Darwin Global Addresses.
950 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
951 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
952 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
953 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
954 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
955 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
956 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
957 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
958 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
959 (ADDIS8 $in, tglobaltlsaddr:$g)>;
960 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
961 (ADDI8 $in, tglobaltlsaddr:$g)>;
962 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
963 (ADDIS8 $in, tglobaladdr:$g)>;
964 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
965 (ADDIS8 $in, tconstpool:$g)>;
966 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
967 (ADDIS8 $in, tjumptable:$g)>;
968 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
969 (ADDIS8 $in, tblockaddress:$g)>;
971 // Patterns to match r+r indexed loads and stores for
972 // addresses without at least 4-byte alignment.
973 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
975 def : Pat<(i64 (unaligned4load xoaddr:$src)),
977 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
978 (STDX $rS, xoaddr:$dst)>;