1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
32 def tocentry : Operand<iPTR> {
33 let MIOperandInfo = (ops i64imm:$imm);
35 def tlsreg : Operand<i64> {
36 let EncoderMethod = "getTLSRegEncoding";
38 def tlsgd : Operand<i64> {}
40 //===----------------------------------------------------------------------===//
41 // 64-bit transformation functions.
44 def SHL64 : SDNodeXForm<imm, [{
45 // Transformation function: 63 - imm
46 return getI32Imm(63 - N->getZExtValue());
49 def SRL64 : SDNodeXForm<imm, [{
50 // Transformation function: 64 - imm
51 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
54 def HI32_48 : SDNodeXForm<imm, [{
55 // Transformation function: shift the immediate value down into the low bits.
56 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
59 def HI48_64 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
65 //===----------------------------------------------------------------------===//
69 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
70 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in
71 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
72 Requires<[In64BitMode]>;
76 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
79 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
80 let Defs = [CTR8], Uses = [CTR8] in {
81 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
83 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
88 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
89 // Convenient aliases for call instructions
91 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
92 "bl $func", BrB, []>; // See Pat patterns below.
94 def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func),
95 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
97 let Uses = [RM], isCodeGenOnly = 1 in {
98 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
99 (outs), (ins calltarget:$func),
100 "bl $func\n\tnop", BrB, []>;
102 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24,
103 (outs), (ins calltarget:$func, tlsgd:$sym),
104 "bl $func($sym)\n\tnop", BrB, []>;
106 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24,
107 (outs), (ins calltarget:$func, tlsgd:$sym),
108 "bl $func($sym)\n\tnop", BrB, []>;
110 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
111 (outs), (ins aaddr:$func),
112 "bla $func\n\tnop", BrB,
113 [(PPCcall_nop (i64 imm:$func))]>;
115 let Uses = [CTR8, RM] in {
116 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
117 "bctrl", BrB, [(PPCbctrl)]>,
118 Requires<[In64BitMode]>;
124 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
125 (BL8 tglobaladdr:$dst)>;
126 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
127 (BL8_NOP tglobaladdr:$dst)>;
129 def : Pat<(PPCcall (i64 texternalsym:$dst)),
130 (BL8 texternalsym:$dst)>;
131 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
132 (BL8_NOP texternalsym:$dst)>;
135 let usesCustomInserter = 1 in {
136 let Defs = [CR0] in {
137 def ATOMIC_LOAD_ADD_I64 : Pseudo<
138 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
139 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
140 def ATOMIC_LOAD_SUB_I64 : Pseudo<
141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
142 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
143 def ATOMIC_LOAD_OR_I64 : Pseudo<
144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
145 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
146 def ATOMIC_LOAD_XOR_I64 : Pseudo<
147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
148 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
149 def ATOMIC_LOAD_AND_I64 : Pseudo<
150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
151 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
152 def ATOMIC_LOAD_NAND_I64 : Pseudo<
153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
154 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
156 def ATOMIC_CMP_SWAP_I64 : Pseudo<
157 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
158 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
160 def ATOMIC_SWAP_I64 : Pseudo<
161 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
162 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
166 // Instructions to support atomic operations
167 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
168 "ldarx $rD, $ptr", LdStLDARX,
169 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
172 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
173 "stdcx. $rS, $dst", LdStSTDCX,
174 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
178 def TCRETURNdi8 :Pseudo< (outs),
179 (ins calltarget:$dst, i32imm:$offset),
180 "#TC_RETURNd8 $dst $offset",
183 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
184 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
185 "#TC_RETURNa8 $func $offset",
186 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
188 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
189 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
190 "#TC_RETURNr8 $dst $offset",
193 let isCodeGenOnly = 1 in {
195 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
196 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
197 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
198 Requires<[In64BitMode]>;
201 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
202 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
203 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
208 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
209 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
210 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
216 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
217 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
219 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
220 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
222 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
223 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
226 // 64-but CR instructions
227 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
228 "mtcrf $FXM, $rS", BrMCRX>,
229 PPC970_MicroCode, PPC970_Unit_CRU;
231 let isCodeGenOnly = 1 in
232 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
233 "#MFCR8pseud", SprMFCR>,
234 PPC970_MicroCode, PPC970_Unit_CRU;
236 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
237 "mfcr $rT", SprMFCR>,
238 PPC970_MicroCode, PPC970_Unit_CRU;
240 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
241 def EH_SjLj_SetJmp64 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
243 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
244 Requires<[In64BitMode]>;
245 let isTerminator = 1 in
246 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
247 "#EH_SJLJ_LONGJMP64",
248 [(PPCeh_sjlj_longjmp addr:$buf)]>,
249 Requires<[In64BitMode]>;
252 //===----------------------------------------------------------------------===//
253 // 64-bit SPR manipulation instrs.
255 let Uses = [CTR8] in {
256 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
257 "mfctr $rT", SprMFSPR>,
258 PPC970_DGroup_First, PPC970_Unit_FXU;
260 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
261 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
262 "mtctr $rS", SprMTSPR>,
263 PPC970_DGroup_First, PPC970_Unit_FXU;
266 let Pattern = [(set i64:$rT, readcyclecounter)] in
267 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
268 "mfspr $rT, 268", SprMFTB>,
269 PPC970_DGroup_First, PPC970_Unit_FXU;
270 // Note that encoding mftb using mfspr is now the preferred form,
271 // and has been since at least ISA v2.03. The mftb instruction has
272 // now been phased out. Using mfspr, however, is known not to work on
275 let Defs = [X1], Uses = [X1] in
276 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
278 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
280 let Defs = [LR8] in {
281 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
282 "mtlr $rS", SprMTSPR>,
283 PPC970_DGroup_First, PPC970_Unit_FXU;
285 let Uses = [LR8] in {
286 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
287 "mflr $rT", SprMFSPR>,
288 PPC970_DGroup_First, PPC970_Unit_FXU;
291 //===----------------------------------------------------------------------===//
292 // Fixed point instructions.
295 let PPC970_Unit = 1 in { // FXU Operations.
297 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
298 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
299 "li $rD, $imm", IntSimple,
300 [(set i64:$rD, immSExt16:$imm)]>;
301 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
302 "lis $rD, $imm", IntSimple,
303 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
307 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
308 "nand $rA, $rS, $rB", IntSimple,
309 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
310 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
311 "and $rA, $rS, $rB", IntSimple,
312 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
313 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
314 "andc $rA, $rS, $rB", IntSimple,
315 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
316 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
317 "or $rA, $rS, $rB", IntSimple,
318 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
319 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
320 "nor $rA, $rS, $rB", IntSimple,
321 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
322 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
323 "orc $rA, $rS, $rB", IntSimple,
324 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
325 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
326 "eqv $rA, $rS, $rB", IntSimple,
327 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
328 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
329 "xor $rA, $rS, $rB", IntSimple,
330 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
332 // Logical ops with immediate.
333 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
334 "andi. $dst, $src1, $src2", IntGeneral,
335 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
337 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
338 "andis. $dst, $src1, $src2", IntGeneral,
339 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
341 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
342 "ori $dst, $src1, $src2", IntSimple,
343 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
344 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
345 "oris $dst, $src1, $src2", IntSimple,
346 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
347 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
348 "xori $dst, $src1, $src2", IntSimple,
349 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
350 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
351 "xoris $dst, $src1, $src2", IntSimple,
352 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
354 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
355 "add $rT, $rA, $rB", IntSimple,
356 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
357 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
358 // initial-exec thread-local storage model.
359 let isCodeGenOnly = 1 in
360 def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB),
361 "add $rT, $rA, $rB@tls", IntSimple,
362 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
364 let Defs = [CARRY] in {
365 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
366 "addc $rT, $rA, $rB", IntGeneral,
367 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
368 PPC970_DGroup_Cracked;
369 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
370 "addic $rD, $rA, $imm", IntGeneral,
371 [(set i64:$rD, (addc i64:$rA, immSExt16:$imm))]>;
373 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolLo64:$imm),
374 "addi $rD, $rA, $imm", IntSimple,
375 [(set i64:$rD, (add i64:$rA, immSExt16:$imm))]>;
376 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolHi64:$imm),
377 "addis $rD, $rA, $imm", IntSimple,
378 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
380 let Defs = [CARRY] in {
381 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
382 "subfic $rD, $rA, $imm", IntGeneral,
383 [(set i64:$rD, (subc immSExt16:$imm, i64:$rA))]>;
384 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
385 "subfc $rT, $rA, $rB", IntGeneral,
386 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
387 PPC970_DGroup_Cracked;
389 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
390 "subf $rT, $rA, $rB", IntGeneral,
391 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
392 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
393 "neg $rT, $rA", IntSimple,
394 [(set i64:$rT, (ineg i64:$rA))]>;
395 let Uses = [CARRY], Defs = [CARRY] in {
396 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
397 "adde $rT, $rA, $rB", IntGeneral,
398 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
399 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
400 "addme $rT, $rA", IntGeneral,
401 [(set i64:$rT, (adde i64:$rA, -1))]>;
402 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
403 "addze $rT, $rA", IntGeneral,
404 [(set i64:$rT, (adde i64:$rA, 0))]>;
405 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
406 "subfe $rT, $rA, $rB", IntGeneral,
407 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
408 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
409 "subfme $rT, $rA", IntGeneral,
410 [(set i64:$rT, (sube -1, i64:$rA))]>;
411 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
412 "subfze $rT, $rA", IntGeneral,
413 [(set i64:$rT, (sube 0, i64:$rA))]>;
417 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
418 "mulhd $rT, $rA, $rB", IntMulHW,
419 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
420 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
421 "mulhdu $rT, $rA, $rB", IntMulHWU,
422 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
424 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
425 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
426 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
427 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
428 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
429 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
430 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
431 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
433 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
434 "sld $rA, $rS, $rB", IntRotateD,
435 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
436 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
437 "srd $rA, $rS, $rB", IntRotateD,
438 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
439 let Defs = [CARRY] in {
440 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
441 "srad $rA, $rS, $rB", IntRotateD,
442 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
445 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
446 "extsb $rA, $rS", IntSimple,
447 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
448 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
449 "extsh $rA, $rS", IntSimple,
450 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
452 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
453 "extsw $rA, $rS", IntSimple,
454 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
455 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
456 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
457 "extsw $rA, $rS", IntSimple,
458 [(set i32:$rA, (PPCextsw_32 i32:$rS))]>, isPPC64;
459 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
460 "extsw $rA, $rS", IntSimple,
461 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
463 let Defs = [CARRY] in {
464 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
465 "sradi $rA, $rS, $SH", IntRotateDI,
466 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
468 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
469 "cntlzd $rA, $rS", IntGeneral,
470 [(set i64:$rA, (ctlz i64:$rS))]>;
472 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
473 "divd $rT, $rA, $rB", IntDivD,
474 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
475 PPC970_DGroup_First, PPC970_DGroup_Cracked;
476 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
477 "divdu $rT, $rA, $rB", IntDivD,
478 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
479 PPC970_DGroup_First, PPC970_DGroup_Cracked;
480 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
481 "mulld $rT, $rA, $rB", IntMulHD,
482 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
485 let isCommutable = 1 in {
486 def RLDIMI : MDForm_1<30, 3,
487 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
488 "rldimi $rA, $rS, $SH, $MB", IntRotateDI,
489 []>, isPPC64, RegConstraint<"$rSi = $rA">,
493 // Rotate instructions.
494 def RLDCL : MDForm_1<30, 0,
495 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
496 "rldcl $rA, $rS, $rB, $MBE", IntRotateD,
498 def RLDICL : MDForm_1<30, 0,
499 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
500 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
502 def RLDICR : MDForm_1<30, 1,
503 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
504 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI,
507 def RLWINM8 : MForm_2<21,
508 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
509 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
512 def ISEL8 : AForm_4<31, 15,
513 (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, CRBITRC:$cond),
514 "isel $rT, $rA, $rB, $cond", IntGeneral,
516 } // End FXU Operations.
519 //===----------------------------------------------------------------------===//
520 // Load/Store instructions.
524 // Sign extending loads.
525 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
526 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
527 "lha $rD, $src", LdStLHA,
528 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
529 PPC970_DGroup_Cracked;
530 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
531 "lwa $rD, $src", LdStLWA,
533 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
534 PPC970_DGroup_Cracked;
535 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
536 "lhax $rD, $src", LdStLHA,
537 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
538 PPC970_DGroup_Cracked;
539 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
540 "lwax $rD, $src", LdStLHA,
541 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
542 PPC970_DGroup_Cracked;
546 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
548 "lhau $rD, $addr", LdStLHAU,
549 []>, RegConstraint<"$addr.reg = $ea_result">,
550 NoEncode<"$ea_result">;
553 def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
555 "lhaux $rD, $addr", LdStLHAU,
556 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
557 NoEncode<"$ea_result">;
558 def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
560 "lwaux $rD, $addr", LdStLHAU,
561 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
562 NoEncode<"$ea_result">, isPPC64;
566 // Zero extending loads.
567 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
568 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
569 "lbz $rD, $src", LdStLoad,
570 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
571 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
572 "lhz $rD, $src", LdStLoad,
573 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
574 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
575 "lwz $rD, $src", LdStLoad,
576 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
578 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
579 "lbzx $rD, $src", LdStLoad,
580 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
581 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
582 "lhzx $rD, $src", LdStLoad,
583 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
584 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
585 "lwzx $rD, $src", LdStLoad,
586 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
591 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
592 "lbzu $rD, $addr", LdStLoadUpd,
593 []>, RegConstraint<"$addr.reg = $ea_result">,
594 NoEncode<"$ea_result">;
595 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
596 "lhzu $rD, $addr", LdStLoadUpd,
597 []>, RegConstraint<"$addr.reg = $ea_result">,
598 NoEncode<"$ea_result">;
599 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
600 "lwzu $rD, $addr", LdStLoadUpd,
601 []>, RegConstraint<"$addr.reg = $ea_result">,
602 NoEncode<"$ea_result">;
604 def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
606 "lbzux $rD, $addr", LdStLoadUpd,
607 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
608 NoEncode<"$ea_result">;
609 def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
611 "lhzux $rD, $addr", LdStLoadUpd,
612 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
613 NoEncode<"$ea_result">;
614 def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
616 "lwzux $rD, $addr", LdStLoadUpd,
617 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
618 NoEncode<"$ea_result">;
623 // Full 8-byte loads.
624 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
625 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
626 "ld $rD, $src", LdStLD,
627 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
628 // The following three definitions are selected for small code model only.
629 // Otherwise, we need to create two instructions to form a 32-bit offset,
630 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
631 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
634 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
635 def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
638 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
639 def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
642 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
644 let hasSideEffects = 1, isCodeGenOnly = 1 in {
645 let RST = 2, DS = 2 in
646 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg),
647 "ld 2, 8($reg)", LdStLD,
648 [(PPCload_toc i64:$reg)]>, isPPC64;
650 let RST = 2, DS = 10, RA = 1 in
651 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
652 "ld 2, 40(1)", LdStLD,
653 [(PPCtoc_restore)]>, isPPC64;
655 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
656 "ldx $rD, $src", LdStLD,
657 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
660 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
661 "ldu $rD, $addr", LdStLDU,
662 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
663 NoEncode<"$ea_result">;
665 def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
667 "ldux $rD, $addr", LdStLDU,
668 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
669 NoEncode<"$ea_result">, isPPC64;
672 def : Pat<(PPCload ixaddr:$src),
674 def : Pat<(PPCload xaddr:$src),
677 // Support for medium and large code model.
678 def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, tocentry:$disp),
681 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
683 def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
686 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
687 def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, tocentry:$disp),
690 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
692 // Support for thread-local storage.
693 def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
696 (PPCaddisGotTprelHA i64:$reg,
697 tglobaltlsaddr:$disp))]>,
699 def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg),
702 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
704 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
705 (ADD8TLS $in, tglobaltlsaddr:$g)>;
706 def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
709 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
711 def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
714 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
716 def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
719 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
721 def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
724 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
726 def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
729 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
731 def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
734 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
736 def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
739 (PPCaddisDtprelHA i64:$reg,
740 tglobaltlsaddr:$disp))]>,
742 def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
745 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
748 let PPC970_Unit = 2 in {
749 // Truncating stores.
750 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
751 "stb $rS, $src", LdStStore,
752 [(truncstorei8 i64:$rS, iaddr:$src)]>;
753 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
754 "sth $rS, $src", LdStStore,
755 [(truncstorei16 i64:$rS, iaddr:$src)]>;
756 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
757 "stw $rS, $src", LdStStore,
758 [(truncstorei32 i64:$rS, iaddr:$src)]>;
759 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
760 "stbx $rS, $dst", LdStStore,
761 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
762 PPC970_DGroup_Cracked;
763 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
764 "sthx $rS, $dst", LdStStore,
765 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
766 PPC970_DGroup_Cracked;
767 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
768 "stwx $rS, $dst", LdStStore,
769 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
770 PPC970_DGroup_Cracked;
771 // Normal 8-byte stores.
772 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
773 "std $rS, $dst", LdStSTD,
774 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
775 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
776 "stdx $rS, $dst", LdStSTD,
777 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
778 PPC970_DGroup_Cracked;
779 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
780 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
781 "std $rT, $dst", LdStSTD,
782 [(PPCstd_32 i32:$rT, ixaddr:$dst)]>, isPPC64;
783 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
784 "stdx $rT, $dst", LdStSTD,
785 [(PPCstd_32 i32:$rT, xaddr:$dst)]>, isPPC64,
786 PPC970_DGroup_Cracked;
789 // Stores with Update (pre-inc).
790 let PPC970_Unit = 2, mayStore = 1 in {
791 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
792 "stbu $rS, $dst", LdStStoreUpd, []>,
793 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
794 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
795 "sthu $rS, $dst", LdStStoreUpd, []>,
796 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
797 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
798 "stwu $rS, $dst", LdStStoreUpd, []>,
799 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
800 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst),
801 "stdu $rS, $dst", LdStSTDU, []>,
802 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
805 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
806 "stbux $rS, $dst", LdStStoreUpd, []>,
807 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
808 PPC970_DGroup_Cracked;
809 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
810 "sthux $rS, $dst", LdStStoreUpd, []>,
811 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
812 PPC970_DGroup_Cracked;
813 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
814 "stwux $rS, $dst", LdStStoreUpd, []>,
815 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
816 PPC970_DGroup_Cracked;
817 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
818 "stdux $rS, $dst", LdStSTDU, []>,
819 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
820 PPC970_DGroup_Cracked, isPPC64;
823 // Patterns to match the pre-inc stores. We can't put the patterns on
824 // the instruction definitions directly as ISel wants the address base
825 // and offset to be separate operands, not a single complex operand.
826 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
827 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
828 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
829 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
830 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
831 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
832 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
833 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
835 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
836 (STBUX8 $rS, $ptrreg, $ptroff)>;
837 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
838 (STHUX8 $rS, $ptrreg, $ptroff)>;
839 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
840 (STWUX8 $rS, $ptrreg, $ptroff)>;
841 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
842 (STDUX $rS, $ptrreg, $ptroff)>;
845 //===----------------------------------------------------------------------===//
846 // Floating point instructions.
850 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
851 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
852 "fcfid $frD, $frB", FPGeneral,
853 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
854 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
855 "fctidz $frD, $frB", FPGeneral,
856 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
860 //===----------------------------------------------------------------------===//
861 // Instruction Patterns
864 // Extensions and truncates to/from 32-bit regs.
865 def : Pat<(i64 (zext i32:$in)),
866 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
868 def : Pat<(i64 (anyext i32:$in)),
869 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
870 def : Pat<(i32 (trunc i64:$in)),
871 (EXTRACT_SUBREG $in, sub_32)>;
873 // Extending loads with i64 targets.
874 def : Pat<(zextloadi1 iaddr:$src),
876 def : Pat<(zextloadi1 xaddr:$src),
878 def : Pat<(extloadi1 iaddr:$src),
880 def : Pat<(extloadi1 xaddr:$src),
882 def : Pat<(extloadi8 iaddr:$src),
884 def : Pat<(extloadi8 xaddr:$src),
886 def : Pat<(extloadi16 iaddr:$src),
888 def : Pat<(extloadi16 xaddr:$src),
890 def : Pat<(extloadi32 iaddr:$src),
892 def : Pat<(extloadi32 xaddr:$src),
895 // Standard shifts. These are represented separately from the real shifts above
896 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
898 def : Pat<(sra i64:$rS, i32:$rB),
900 def : Pat<(srl i64:$rS, i32:$rB),
902 def : Pat<(shl i64:$rS, i32:$rB),
906 def : Pat<(shl i64:$in, (i32 imm:$imm)),
907 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
908 def : Pat<(srl i64:$in, (i32 imm:$imm)),
909 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
912 def : Pat<(rotl i64:$in, i32:$sh),
913 (RLDCL $in, $sh, 0)>;
914 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
915 (RLDICL $in, imm:$imm, 0)>;
917 // Hi and Lo for Darwin Global Addresses.
918 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
919 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
920 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
921 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
922 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
923 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
924 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
925 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
926 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
927 (ADDIS8 $in, tglobaltlsaddr:$g)>;
928 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
929 (ADDI8 $in, tglobaltlsaddr:$g)>;
930 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
931 (ADDIS8 $in, tglobaladdr:$g)>;
932 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
933 (ADDIS8 $in, tconstpool:$g)>;
934 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
935 (ADDIS8 $in, tjumptable:$g)>;
936 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
937 (ADDIS8 $in, tblockaddress:$g)>;
939 // Patterns to match r+r indexed loads and stores for
940 // addresses without at least 4-byte alignment.
941 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
943 def : Pat<(i64 (unaligned4load xoaddr:$src)),
945 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
946 (STDX $rS, xoaddr:$dst)>;