1 //===-- PPC32ISelPattern.cpp - A pattern matching inst selector for PPC32 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC.
12 //===----------------------------------------------------------------------===//
15 #include "PowerPCInstrBuilder.h"
16 #include "PowerPCInstrInfo.h"
17 #include "PPC32RegisterInfo.h"
18 #include "llvm/Constants.h" // FIXME: REMOVE
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/Statistic.h"
35 //===----------------------------------------------------------------------===//
36 // PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
38 class PPC32TargetLowering : public TargetLowering {
39 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
40 int ReturnAddrIndex; // FrameIndex for return slot.
42 PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
43 // Set up the TargetLowering object.
45 // Set up the register classes.
46 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
47 addRegisterClass(MVT::f32, PPC32::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
50 computeRegisterProperties();
53 /// LowerArguments - This hook must be implemented to indicate how we should
54 /// lower the arguments for the specified function, into the specified DAG.
55 virtual std::vector<SDOperand>
56 LowerArguments(Function &F, SelectionDAG &DAG);
58 /// LowerCallTo - This hook lowers an abstract call to a function into an
60 virtual std::pair<SDOperand, SDOperand>
61 LowerCallTo(SDOperand Chain, const Type *RetTy, SDOperand Callee,
62 ArgListTy &Args, SelectionDAG &DAG);
64 virtual std::pair<SDOperand, SDOperand>
65 LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
67 virtual std::pair<SDOperand,SDOperand>
68 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
69 const Type *ArgTy, SelectionDAG &DAG);
71 virtual std::pair<SDOperand, SDOperand>
72 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
78 std::vector<SDOperand>
79 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
81 // add beautiful description of PPC stack frame format, or at least some docs
83 MachineFunction &MF = DAG.getMachineFunction();
84 MachineFrameInfo *MFI = MF.getFrameInfo();
85 MachineBasicBlock& BB = MF.front();
86 std::vector<SDOperand> ArgValues;
88 // Due to the rather complicated nature of the PowerPC ABI, rather than a
89 // fixed size array of physical args, for the sake of simplicity let the STL
90 // handle tracking them for us.
91 std::vector<unsigned> argVR, argPR, argOp;
92 unsigned ArgOffset = 24;
93 unsigned GPR_remaining = 8;
94 unsigned FPR_remaining = 13;
95 unsigned GPR_idx = 0, FPR_idx = 0;
96 static const unsigned GPR[] = {
97 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
98 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
100 static const unsigned FPR[] = {
101 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
102 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
105 // Add DAG nodes to load the arguments... On entry to a function on PPC,
106 // the arguments start at offset 24, although they are likely to be passed
108 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
109 SDOperand newroot, argt;
111 bool needsLoad = false;
112 MVT::ValueType ObjectVT = getValueType(I->getType());
115 default: assert(0 && "Unhandled argument type!");
121 if (GPR_remaining > 0) {
122 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
124 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
125 argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
126 if (ObjectVT != MVT::i32)
127 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
128 argVR.push_back(virtReg);
129 argPR.push_back(GPR[GPR_idx]);
130 argOp.push_back(PPC::OR);
135 case MVT::i64: ObjSize = 8;
136 if (GPR_remaining > 1) {
137 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
138 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
139 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
141 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32))-1;
142 // FIXME: is this correct?
143 argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
144 argt = DAG.getCopyFromReg(virtReg+1, MVT::i32, newroot);
145 // Push the arguments for emitting into BB later
146 argVR.push_back(virtReg); argVR.push_back(virtReg+1);
147 argPR.push_back(GPR[GPR_idx]); argPR.push_back(GPR[GPR_idx+1]);
148 argOp.push_back(PPC::OR); argOp.push_back(PPC::OR);
153 case MVT::f32: ObjSize = 4;
154 case MVT::f64: ObjSize = 8;
155 if (FPR_remaining > 0) {
156 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
158 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(ObjectVT));
159 argt = newroot = DAG.getCopyFromReg(virtReg, ObjectVT, DAG.getRoot());
160 argVR.push_back(virtReg);
161 argPR.push_back(FPR[FPR_idx]);
162 argOp.push_back(PPC::FMR);
171 // We need to load the argument to a virtual register if we determined above
172 // that we ran out of physical registers of the appropriate type
174 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
175 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
176 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
179 // Every 4 bytes of argument space consumes one of the GPRs available for
181 if (GPR_remaining > 0) {
182 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
183 GPR_remaining -= delta;
186 ArgOffset += ObjSize;
188 DAG.setRoot(newroot.getValue(1));
189 ArgValues.push_back(argt);
192 for (int i = 0, count = argVR.size(); i < count; ++i) {
193 if (argOp[i] == PPC::FMR)
194 BuildMI(&BB, argOp[i], 1, argVR[i]).addReg(argPR[i]);
196 BuildMI(&BB, argOp[i], 2, argVR[i]).addReg(argPR[i]).addReg(argPR[i]);
199 // If the function takes variable number of arguments, make a frame index for
200 // the start of the first vararg value... for expansion of llvm.va_start.
202 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
207 std::pair<SDOperand, SDOperand>
208 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
209 const Type *RetTy, SDOperand Callee,
210 ArgListTy &Args, SelectionDAG &DAG) {
214 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
215 DAG.getConstant(NumBytes, getPointerTy()));
216 std::vector<SDOperand> args_to_use;
217 for (unsigned i = 0, e = Args.size(); i != e; ++i)
219 switch (getValueType(Args[i].second)) {
220 default: assert(0 && "Unexpected ValueType for argument!");
224 // Promote the integer to 32 bits. If the input type is signed use a
225 // sign extend, otherwise use a zero extend.
226 if (Args[i].second->isSigned())
227 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
229 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
236 args_to_use.push_back(Args[i].first);
239 std::vector<MVT::ValueType> RetVals;
240 MVT::ValueType RetTyVT = getValueType(RetTy);
241 if (RetTyVT != MVT::isVoid)
242 RetVals.push_back(RetTyVT);
243 RetVals.push_back(MVT::Other);
245 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
246 Chain, Callee, args_to_use), 0);
247 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
248 Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
249 DAG.getConstant(NumBytes, getPointerTy()));
250 return std::make_pair(TheCall, Chain);
253 std::pair<SDOperand, SDOperand>
254 PPC32TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
255 //vastart just returns the address of the VarArgsFrameIndex slot.
256 return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
259 std::pair<SDOperand,SDOperand> PPC32TargetLowering::
260 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
261 const Type *ArgTy, SelectionDAG &DAG) {
266 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
267 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
274 //===--------------------------------------------------------------------===//
275 /// ISel - PPC32 specific code to select PPC32 machine instructions for
276 /// SelectionDAG operations.
277 //===--------------------------------------------------------------------===//
278 class ISel : public SelectionDAGISel {
281 PPC32TargetLowering PPC32Lowering;
283 /// ExprMap - As shared expressions are codegen'd, we keep track of which
284 /// vreg the value is produced in, so we only emit one copy of each compiled
286 std::map<SDOperand, unsigned> ExprMap;
289 ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM)
292 /// InstructionSelectBasicBlock - This callback is invoked by
293 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
294 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
296 // Codegen the basic block.
297 Select(DAG.getRoot());
299 // Clear state used for selection.
303 unsigned SelectExpr(SDOperand N);
304 unsigned SelectExprFP(SDOperand N, unsigned Result);
305 void Select(SDOperand N);
307 void SelectAddr(SDOperand N, unsigned& Reg, int& offset);
308 void SelectBranchCC(SDOperand N);
311 /// canUseAsImmediateForOpcode - This method returns a value indicating whether
312 /// the ConstantSDNode N can be used as an immediate to Opcode. The return
313 /// values are either 0, 1 or 2. 0 indicates that either N is not a
314 /// ConstantSDNode, or is not suitable for use by that opcode. A return value
315 /// of 1 indicates that the constant may be used in normal immediate form. A
316 /// return value of 2 indicates that the constant may be used in shifted
317 /// immediate form. If the return value is nonzero, the constant value is
320 static unsigned canUseAsImmediateForOpcode(SDOperand N, unsigned Opcode,
322 if (N.getOpcode() != ISD::Constant) return 0;
324 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
329 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
330 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
335 if (v >= 0 && v <= 65535) { Imm = v & 0xFFFF; return 1; }
336 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
343 //Check to see if the load is a constant offset from a base register
344 void ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
351 void ISel::SelectBranchCC(SDOperand N)
353 assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
354 MachineBasicBlock *Dest =
355 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
358 Select(N.getOperand(0)); //chain
359 SDOperand CC = N.getOperand(1);
361 //Giveup and do the stupid thing
362 unsigned Tmp1 = SelectExpr(CC);
363 BuildMI(BB, PPC::BNE, 2).addReg(Tmp1).addMBB(Dest);
367 unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
369 unsigned Tmp1, Tmp2, Tmp3;
371 SDNode *Node = N.Val;
372 MVT::ValueType DestType = N.getValueType();
373 unsigned opcode = N.getOpcode();
378 assert(0 && "Node not handled!\n");
384 assert (DestType == MVT::f32 &&
385 N.getOperand(0).getValueType() == MVT::f64 &&
386 "only f64 to f32 conversion supported here");
387 Tmp1 = SelectExpr(N.getOperand(0));
388 BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
392 assert (DestType == MVT::f64 &&
393 N.getOperand(0).getValueType() == MVT::f32 &&
394 "only f32 to f64 conversion supported here");
395 Tmp1 = SelectExpr(N.getOperand(0));
396 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
399 case ISD::CopyFromReg:
400 // FIXME: Handle copy from physregs!
401 // Just use the specified register as our input.
402 return dyn_cast<RegSDNode>(Node)->getReg();
408 case ISD::ConstantFP:
416 case ISD::MUL: Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
417 case ISD::ADD: Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS; break;
418 case ISD::SUB: Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS; break;
419 case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
422 Tmp1 = SelectExpr(N.getOperand(0));
423 Tmp2 = SelectExpr(N.getOperand(1));
424 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
427 case ISD::UINT_TO_FP:
428 case ISD::SINT_TO_FP:
431 assert(0 && "should not get here");
435 unsigned ISel::SelectExpr(SDOperand N) {
437 unsigned Tmp1, Tmp2, Tmp3;
439 unsigned opcode = N.getOpcode();
441 SDNode *Node = N.Val;
442 MVT::ValueType DestType = N.getValueType();
444 unsigned &Reg = ExprMap[N];
447 if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::ADD_PARTS &&
448 N.getOpcode() != ISD::SUB_PARTS)
449 Reg = Result = (N.getValueType() != MVT::Other) ?
450 MakeReg(N.getValueType()) : 1;
452 // If this is a call instruction, make sure to prepare ALL of the result
453 // values as well as the chain.
454 if (N.getOpcode() == ISD::CALL) {
455 if (Node->getNumValues() == 1)
456 Reg = Result = 1; // Void call, just a chain.
458 Result = MakeReg(Node->getValueType(0));
459 ExprMap[N.getValue(0)] = Result;
460 for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
461 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
462 ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
465 Result = MakeReg(Node->getValueType(0));
466 ExprMap[N.getValue(0)] = Result;
467 for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
468 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
472 if (DestType == MVT::f64 || DestType == MVT::f32)
473 return SelectExprFP(N, Result);
478 assert(0 && "Node not handled!\n");
480 case ISD::DYNAMIC_STACKALLOC:
481 // Generate both result values. FIXME: Need a better commment here?
483 ExprMap[N.getValue(1)] = 1;
485 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
487 // FIXME: We are currently ignoring the requested alignment for handling
488 // greater than the stack alignment. This will need to be revisited at some
489 // point. Align = N.getOperand(2);
490 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
491 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
492 std::cerr << "Cannot allocate stack object with greater alignment than"
493 << " the stack alignment yet!";
496 Select(N.getOperand(0));
497 Tmp1 = SelectExpr(N.getOperand(1));
498 // Subtract size from stack pointer, thereby allocating some space.
499 BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(Tmp1).addReg(PPC::R1);
500 // Put a pointer to the space into the result register by copying the SP
501 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R1).addReg(PPC::R1);
504 case ISD::ConstantPool:
507 case ISD::FrameIndex:
510 case ISD::GlobalAddress: {
511 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
512 unsigned Tmp1 = MakeReg(MVT::i32);
513 // FIXME: R1 is incorrect, we need the getGlobalBaseReg() functionality
514 // from the simple isel
515 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(PPC::R1).addGlobalAddress(GV);
516 if (GV->hasWeakLinkage() || GV->isExternal()) {
517 BuildMI(BB, PPC::LWZ, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
519 BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp1).addGlobalAddress(GV);
527 case ISD::SEXTLOAD: {
528 // Make sure we generate both values.
530 ExprMap[N.getValue(1)] = 1; // Generate the token
532 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
534 SDOperand Chain = N.getOperand(0);
535 SDOperand Address = N.getOperand(1);
538 switch (Node->getValueType(0)) {
539 default: assert(0 && "Cannot load this type!");
540 case MVT::i1: Opc = PPC::LBZ; Tmp3 = 0; break;
541 case MVT::i8: Opc = PPC::LBZ; Tmp3 = 1; break;
542 case MVT::i16: Opc = PPC::LHZ; Tmp3 = 0; break;
543 case MVT::i32: Opc = PPC::LWZ; Tmp3 = 0; break;
546 if(Address.getOpcode() == ISD::FrameIndex) {
547 BuildMI(BB, Opc, 2, Result)
548 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
552 SelectAddr(Address, Tmp1, offset);
553 BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
559 // Lower the chain for this call.
560 Select(N.getOperand(0));
561 ExprMap[N.getValue(Node->getNumValues()-1)] = 1;
563 // get the virtual reg for each argument
564 std::vector<unsigned> VRegs;
565 for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
566 VRegs.push_back(SelectExpr(N.getOperand(i)));
568 // The ABI specifies that the first 32 bytes of args may be passed in GPRs,
569 // and that 13 FPRs may also be used for passing any floating point args.
570 int GPR_remaining = 8, FPR_remaining = 13;
571 unsigned GPR_idx = 0, FPR_idx = 0;
572 static const unsigned GPR[] = {
573 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
574 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
576 static const unsigned FPR[] = {
577 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
578 PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
582 // move the vregs into the appropriate architected register or stack slot
583 for(int i = 0, e = VRegs.size(); i < e; ++i) {
584 unsigned OperandType = N.getOperand(i+2).getValueType();
585 switch(OperandType) {
588 N.getOperand(i).Val->dump();
589 std::cerr << "Type for " << i << " is: " <<
590 N.getOperand(i+2).getValueType() << "\n";
591 assert(0 && "Unknown value type for call");
596 if (GPR_remaining > 0)
597 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(VRegs[i])
602 if (FPR_remaining > 0) {
603 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(VRegs[i]);
608 // All arguments consume GPRs available for argument passing
609 if (GPR_remaining > 0) --GPR_remaining;
610 if (MVT::f64 == OperandType && GPR_remaining > 0) --GPR_remaining;
613 // Emit the correct call instruction based on the type of symbol called.
614 if (GlobalAddressSDNode *GASD =
615 dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
616 BuildMI(BB, PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(), true);
617 } else if (ExternalSymbolSDNode *ESSDN =
618 dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
619 BuildMI(BB, PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(), true);
621 Tmp1 = SelectExpr(N.getOperand(1));
622 BuildMI(BB, PPC::OR, 2, PPC::R12).addReg(Tmp1).addReg(Tmp1);
623 BuildMI(BB, PPC::MTCTR, 1).addReg(PPC::R12);
624 BuildMI(BB, PPC::CALLindirect, 3).addImm(20).addImm(0).addReg(PPC::R12);
627 switch (Node->getValueType(0)) {
628 default: assert(0 && "Unknown value type for call result!");
629 case MVT::Other: return 1;
634 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3);
635 if (Node->getValueType(1) == MVT::i32)
636 BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R4);
640 BuildMI(BB, PPC::FMR, 1, Result).addReg(PPC::F1);
643 return Result+N.ResNo;
646 case ISD::SIGN_EXTEND:
647 case ISD::SIGN_EXTEND_INREG:
648 Tmp1 = SelectExpr(N.getOperand(0));
649 BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
652 case ISD::ZERO_EXTEND_INREG:
653 Tmp1 = SelectExpr(N.getOperand(0));
654 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
657 assert(0 && "Zero Extend InReg not there yet");
659 case MVT::i16: Tmp2 = 16; break;
660 case MVT::i8: Tmp2 = 24; break;
661 case MVT::i1: Tmp2 = 31; break;
663 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(0).addImm(0)
664 .addImm(Tmp2).addImm(31);
667 case ISD::CopyFromReg:
669 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
670 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
671 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
675 Tmp1 = SelectExpr(N.getOperand(0));
676 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
677 Tmp2 = CN->getValue() & 0x1F;
678 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(Tmp2).addImm(0)
681 Tmp2 = SelectExpr(N.getOperand(1));
682 BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
687 Tmp1 = SelectExpr(N.getOperand(0));
688 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
689 Tmp2 = CN->getValue() & 0x1F;
690 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(32-Tmp2)
691 .addImm(Tmp2).addImm(31);
693 Tmp2 = SelectExpr(N.getOperand(1));
694 BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
699 Tmp1 = SelectExpr(N.getOperand(0));
700 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
701 Tmp2 = CN->getValue() & 0x1F;
702 BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
704 Tmp2 = SelectExpr(N.getOperand(1));
705 BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
710 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
711 Tmp1 = SelectExpr(N.getOperand(0));
712 switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
713 default: assert(0 && "unhandled result code");
714 case 0: // No immediate
715 Tmp2 = SelectExpr(N.getOperand(1));
716 BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
718 case 1: // Low immediate
719 BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
721 case 2: // Shifted immediate
722 BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp2);
730 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
731 Tmp1 = SelectExpr(N.getOperand(0));
732 switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
733 default: assert(0 && "unhandled result code");
734 case 0: // No immediate
735 Tmp2 = SelectExpr(N.getOperand(1));
737 case ISD::AND: Opc = PPC::AND; break;
738 case ISD::OR: Opc = PPC::OR; break;
739 case ISD::XOR: Opc = PPC::XOR; break;
741 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
743 case 1: // Low immediate
745 case ISD::AND: Opc = PPC::ANDIo; break;
746 case ISD::OR: Opc = PPC::ORI; break;
747 case ISD::XOR: Opc = PPC::XORI; break;
749 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
751 case 2: // Shifted immediate
753 case ISD::AND: Opc = PPC::ANDISo; break;
754 case ISD::OR: Opc = PPC::ORIS; break;
755 case ISD::XOR: Opc = PPC::XORIS; break;
757 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
763 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
764 Tmp1 = SelectExpr(N.getOperand(0));
765 Tmp2 = SelectExpr(N.getOperand(1));
766 BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
770 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
771 Tmp1 = SelectExpr(N.getOperand(0));
772 Tmp2 = SelectExpr(N.getOperand(1));
773 BuildMI(BB, PPC::MULLW, 2, Result).addReg(Tmp2).addReg(Tmp1);
784 case ISD::FP_TO_UINT:
785 case ISD::FP_TO_SINT:
795 switch (N.getValueType()) {
796 default: assert(0 && "Cannot use constants of this type!");
798 BuildMI(BB, PPC::LI, 1, Result)
799 .addSImm(!cast<ConstantSDNode>(N)->isNullValue());
803 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
804 if (v < 32768 && v >= -32768) {
805 BuildMI(BB, PPC::LI, 1, Result).addSImm(v);
807 Tmp1 = MakeReg(MVT::i32);
808 BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
809 BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(v & 0xFFFF);
819 void ISel::Select(SDOperand N) {
820 unsigned Tmp1, Tmp2, Opc;
821 unsigned opcode = N.getOpcode();
823 if (!ExprMap.insert(std::make_pair(N, 1)).second)
824 return; // Already selected.
826 SDNode *Node = N.Val;
828 switch (Node->getOpcode()) {
830 Node->dump(); std::cerr << "\n";
831 assert(0 && "Node not handled yet!");
832 case ISD::EntryToken: return; // Noop
833 case ISD::TokenFactor:
834 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
835 Select(Node->getOperand(i));
837 case ISD::ADJCALLSTACKDOWN:
838 case ISD::ADJCALLSTACKUP:
839 Select(N.getOperand(0));
840 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
841 Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? PPC::ADJCALLSTACKDOWN :
843 BuildMI(BB, Opc, 1).addImm(Tmp1);
846 MachineBasicBlock *Dest =
847 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
848 Select(N.getOperand(0));
849 BuildMI(BB, PPC::B, 1).addMBB(Dest);
856 Select(N.getOperand(0));
857 Tmp1 = SelectExpr(N.getOperand(1));
858 Tmp2 = cast<RegSDNode>(N)->getReg();
861 if (N.getOperand(1).getValueType() == MVT::f64 ||
862 N.getOperand(1).getValueType() == MVT::f32)
863 BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
865 BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
868 case ISD::ImplicitDef:
869 Select(N.getOperand(0));
870 BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
873 switch (N.getNumOperands()) {
875 assert(0 && "Unknown return instruction!");
877 assert(N.getOperand(1).getValueType() == MVT::i32 &&
878 N.getOperand(2).getValueType() == MVT::i32 &&
879 "Unknown two-register value!");
880 Select(N.getOperand(0));
881 Tmp1 = SelectExpr(N.getOperand(1));
882 Tmp2 = SelectExpr(N.getOperand(2));
883 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
884 BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp2).addReg(Tmp2);
887 Select(N.getOperand(0));
888 Tmp1 = SelectExpr(N.getOperand(1));
889 switch (N.getOperand(1).getValueType()) {
891 assert(0 && "Unknown return type!");
894 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(Tmp1);
897 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
901 Select(N.getOperand(0));
904 BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
906 case ISD::TRUNCSTORE:
909 SDOperand Chain = N.getOperand(0);
910 SDOperand Value = N.getOperand(1);
911 SDOperand Address = N.getOperand(2);
914 Tmp1 = SelectExpr(Value); //value
916 if (opcode == ISD::STORE) {
917 switch(Value.getValueType()) {
918 default: assert(0 && "unknown Type in store");
919 case MVT::i32: Opc = PPC::STW; break;
920 case MVT::f64: Opc = PPC::STFD; break;
921 case MVT::f32: Opc = PPC::STFS; break;
923 } else { //ISD::TRUNCSTORE
924 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
925 default: assert(0 && "unknown Type in store");
926 case MVT::i1: //FIXME: DAG does not promote this load
927 case MVT::i8: Opc = PPC::STB; break;
928 case MVT::i16: Opc = PPC::STH; break;
932 if (Address.getOpcode() == ISD::GlobalAddress)
934 BuildMI(BB, Opc, 2).addReg(Tmp1)
935 .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
937 else if(Address.getOpcode() == ISD::FrameIndex)
939 BuildMI(BB, Opc, 2).addReg(Tmp1)
940 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex());
945 SelectAddr(Address, Tmp2, offset);
946 BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
954 case ISD::CopyFromReg:
956 case ISD::DYNAMIC_STACKALLOC:
961 assert(0 && "Should not be reached!");
965 /// createPPC32PatternInstructionSelector - This pass converts an LLVM function
966 /// into a machine code representation using pattern matching and a machine
967 /// description file.
969 FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {