1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "PPCSubtarget.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to.
47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48 // three v4f32 operands and producing a v4f32 result.
51 /// VPERM - The PPC VPERM Instruction.
55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
56 /// address respectively. These nodes have two operands, the first of
57 /// which must be a TargetGlobalAddress, and the second of which must be a
58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
59 /// though these are usually folded into other nodes.
64 /// The following three target-specific nodes are used for calls through
65 /// function pointers in the 64-bit SVR4 ABI.
67 /// Restore the TOC from the TOC save area of the current stack frame.
68 /// This is basically a hard coded load instruction which additionally
69 /// takes/produces a flag.
72 /// Like a regular LOAD but additionally taking/producing a flag.
75 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
76 /// a hard coded load instruction.
79 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
80 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
81 /// compute an allocation on the stack.
84 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
85 /// at function entry, used for PIC code.
88 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
89 /// shift amounts. These nodes are generated by the multi-precision shift
93 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
97 /// CALL - A direct function call.
98 CALL_Darwin, CALL_SVR4,
100 /// NOP - Special NOP which follows 64-bit SVR4 calls.
103 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
104 /// MTCTR instruction.
107 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
108 /// BCTRL instruction.
109 BCTRL_Darwin, BCTRL_SVR4,
111 /// Return with a flag operand, matched by 'blr'
114 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
115 /// instructions. This copies the bits corresponding to the specified
116 /// CRREG into the resultant GPR. Bits corresponding to other CR regs
120 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
121 /// instructions. For lack of better number, we use the opcode number
122 /// encoding for the OPC field to identify the compare. For example, 838
126 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
127 /// altivec VCMP*o instructions. For lack of better number, we use the
128 /// opcode number encoding for the OPC field to identify the compare. For
129 /// example, 838 is VCMPGTSH.
132 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
133 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
134 /// condition register to branch on, OPC is the branch opcode to use (e.g.
135 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
136 /// an optional input flag argument.
139 // The following 5 instructions are used only as part of the
140 // long double-to-int conversion sequence.
142 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
146 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
149 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
152 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
153 /// rounding towards zero. It has flags added so it won't move past the
154 /// FPSCR-setting instructions.
157 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
160 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
161 /// reserve indexed. This is used to implement atomic operations.
164 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
165 /// indexed. This is used to implement atomic operations.
168 /// TC_RETURN - A tail call return.
170 /// operand #1 callee (register or absolute)
171 /// operand #2 stack adjustment
172 /// operand #3 optional in flag
175 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
176 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
178 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
179 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
180 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
184 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
185 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
186 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
192 /// Define some predicates that are used for node matching.
194 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
195 /// VPKUHUM instruction.
196 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
198 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
199 /// VPKUWUM instruction.
200 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
202 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
203 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
204 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
207 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
208 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
209 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
212 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
213 /// amount, otherwise return -1.
214 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
216 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
217 /// specifies a splat of a single element that is suitable for input to
218 /// VSPLTB/VSPLTH/VSPLTW.
219 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
221 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
223 bool isAllNegativeZeroVector(SDNode *N);
225 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
226 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
227 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
229 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
230 /// formed by using a vspltis[bhw] instruction of the specified element
231 /// size, return the constant being splatted. The ByteSize field indicates
232 /// the number of bytes of each element [124] -> [bhw].
233 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
236 class PPCTargetLowering : public TargetLowering {
237 const PPCSubtarget &PPCSubTarget;
240 explicit PPCTargetLowering(PPCTargetMachine &TM);
242 /// getTargetNodeName() - This method returns the name of a target specific
244 virtual const char *getTargetNodeName(unsigned Opcode) const;
246 /// getSetCCResultType - Return the ISD::SETCC ValueType
247 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
249 /// getPreIndexedAddressParts - returns true by value, base pointer and
250 /// offset pointer and addressing mode by reference if the node's address
251 /// can be legally represented as pre-indexed load / store address.
252 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
254 ISD::MemIndexedMode &AM,
255 SelectionDAG &DAG) const;
257 /// SelectAddressRegReg - Given the specified addressed, check to see if it
258 /// can be represented as an indexed [r+r] operation. Returns false if it
259 /// can be more efficiently represented with [r+imm].
260 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
261 SelectionDAG &DAG) const;
263 /// SelectAddressRegImm - Returns true if the address N can be represented
264 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
265 /// is not better represented as reg+reg.
266 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
267 SelectionDAG &DAG) const;
269 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
270 /// represented as an indexed [r+r] operation.
271 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
272 SelectionDAG &DAG) const;
274 /// SelectAddressRegImmShift - Returns true if the address N can be
275 /// represented by a base register plus a signed 14-bit displacement
276 /// [r+imm*4]. Suitable for use by STD and friends.
277 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
278 SelectionDAG &DAG) const;
281 /// LowerOperation - Provide custom lowering hooks for some operations.
283 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
285 /// ReplaceNodeResults - Replace the results of node with an illegal result
286 /// type with new values built out of custom code.
288 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
289 SelectionDAG &DAG) const;
291 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
293 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
297 const SelectionDAG &DAG,
298 unsigned Depth = 0) const;
300 virtual MachineBasicBlock *
301 EmitInstrWithCustomInserter(MachineInstr *MI,
302 MachineBasicBlock *MBB) const;
303 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
304 MachineBasicBlock *MBB, bool is64Bit,
305 unsigned BinOpcode) const;
306 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
307 MachineBasicBlock *MBB,
308 bool is8bit, unsigned Opcode) const;
310 ConstraintType getConstraintType(const std::string &Constraint) const;
311 std::pair<unsigned, const TargetRegisterClass*>
312 getRegForInlineAsmConstraint(const std::string &Constraint,
315 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
316 /// function arguments in the caller parameter area. This is the actual
317 /// alignment, not its logarithm.
318 unsigned getByValTypeAlignment(const Type *Ty) const;
320 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
321 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
322 /// true it means one of the asm constraint of the inline asm instruction
323 /// being processed is 'm'.
324 virtual void LowerAsmOperandForConstraint(SDValue Op,
325 char ConstraintLetter,
327 std::vector<SDValue> &Ops,
328 SelectionDAG &DAG) const;
330 /// isLegalAddressingMode - Return true if the addressing mode represented
331 /// by AM is legal for this target, for a load/store of the specified type.
332 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
334 /// isLegalAddressImmediate - Return true if the integer value can be used
335 /// as the offset of the target addressing mode for load / store of the
337 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
339 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
340 /// the offset of the target addressing mode.
341 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
343 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
345 /// getOptimalMemOpType - Returns the target specific optimal type for load
346 /// and store operations as a result of memset, memcpy, and memmove
347 /// lowering. If DstAlign is zero that means it's safe to destination
348 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
349 /// means there isn't a need to check it against alignment requirement,
350 /// probably because the source does not need to be loaded. If
351 /// 'NonScalarIntSafe' is true, that means it's safe to return a
352 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
353 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
354 /// constant so it does not need to be loaded.
355 /// It returns EVT::Other if the type should be determined using generic
356 /// target-independent logic.
358 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
359 bool NonScalarIntSafe, bool MemcpyStrSrc,
360 MachineFunction &MF) const;
362 /// getFunctionAlignment - Return the Log2 alignment of this function.
363 virtual unsigned getFunctionAlignment(const Function *F) const;
366 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
367 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
370 IsEligibleForTailCallOptimization(SDValue Callee,
371 CallingConv::ID CalleeCC,
373 const SmallVectorImpl<ISD::InputArg> &Ins,
374 SelectionDAG& DAG) const;
376 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
384 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
385 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
386 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
387 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
388 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
389 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
390 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
391 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
392 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
393 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
394 const PPCSubtarget &Subtarget) const;
395 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
396 const PPCSubtarget &Subtarget) const;
397 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
398 const PPCSubtarget &Subtarget) const;
399 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
400 const PPCSubtarget &Subtarget) const;
401 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
402 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
403 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
404 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
405 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
406 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
407 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
408 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
409 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
410 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
411 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
412 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
414 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
415 CallingConv::ID CallConv, bool isVarArg,
416 const SmallVectorImpl<ISD::InputArg> &Ins,
417 DebugLoc dl, SelectionDAG &DAG,
418 SmallVectorImpl<SDValue> &InVals) const;
419 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
422 SmallVector<std::pair<unsigned, SDValue>, 8>
424 SDValue InFlag, SDValue Chain,
426 int SPDiff, unsigned NumBytes,
427 const SmallVectorImpl<ISD::InputArg> &Ins,
428 SmallVectorImpl<SDValue> &InVals) const;
431 LowerFormalArguments(SDValue Chain,
432 CallingConv::ID CallConv, bool isVarArg,
433 const SmallVectorImpl<ISD::InputArg> &Ins,
434 DebugLoc dl, SelectionDAG &DAG,
435 SmallVectorImpl<SDValue> &InVals) const;
438 LowerCall(SDValue Chain, SDValue Callee,
439 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
440 const SmallVectorImpl<ISD::OutputArg> &Outs,
441 const SmallVectorImpl<ISD::InputArg> &Ins,
442 DebugLoc dl, SelectionDAG &DAG,
443 SmallVectorImpl<SDValue> &InVals) const;
446 LowerReturn(SDValue Chain,
447 CallingConv::ID CallConv, bool isVarArg,
448 const SmallVectorImpl<ISD::OutputArg> &Outs,
449 DebugLoc dl, SelectionDAG &DAG) const;
452 LowerFormalArguments_Darwin(SDValue Chain,
453 CallingConv::ID CallConv, bool isVarArg,
454 const SmallVectorImpl<ISD::InputArg> &Ins,
455 DebugLoc dl, SelectionDAG &DAG,
456 SmallVectorImpl<SDValue> &InVals) const;
458 LowerFormalArguments_SVR4(SDValue Chain,
459 CallingConv::ID CallConv, bool isVarArg,
460 const SmallVectorImpl<ISD::InputArg> &Ins,
461 DebugLoc dl, SelectionDAG &DAG,
462 SmallVectorImpl<SDValue> &InVals) const;
465 LowerCall_Darwin(SDValue Chain, SDValue Callee,
466 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
467 const SmallVectorImpl<ISD::OutputArg> &Outs,
468 const SmallVectorImpl<ISD::InputArg> &Ins,
469 DebugLoc dl, SelectionDAG &DAG,
470 SmallVectorImpl<SDValue> &InVals) const;
472 LowerCall_SVR4(SDValue Chain, SDValue Callee,
473 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
474 const SmallVectorImpl<ISD::OutputArg> &Outs,
475 const SmallVectorImpl<ISD::InputArg> &Ins,
476 DebugLoc dl, SelectionDAG &DAG,
477 SmallVectorImpl<SDValue> &InVals) const;
481 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H