1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
37 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
38 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
41 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
46 // Use _setjmp/_longjmp instead of setjmp/longjmp.
47 setUseUnderscoreSetJmp(true);
48 setUseUnderscoreLongJmp(true);
50 // Set up the register classes.
51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
56 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
57 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
74 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
75 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
76 // This is used in the ppcf128->int sequence. Note it has different semantics
77 // from FP_ROUND: that rounds to nearest, this rounds to zero.
78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
80 // PowerPC has no SREM/UREM instructions
81 setOperationAction(ISD::SREM, MVT::i32, Expand);
82 setOperationAction(ISD::UREM, MVT::i32, Expand);
83 setOperationAction(ISD::SREM, MVT::i64, Expand);
84 setOperationAction(ISD::UREM, MVT::i64, Expand);
86 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
87 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
88 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
89 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
90 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
91 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
92 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
93 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
94 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
96 // We don't support sin/cos/sqrt/fmod/pow
97 setOperationAction(ISD::FSIN , MVT::f64, Expand);
98 setOperationAction(ISD::FCOS , MVT::f64, Expand);
99 setOperationAction(ISD::FREM , MVT::f64, Expand);
100 setOperationAction(ISD::FPOW , MVT::f64, Expand);
101 setOperationAction(ISD::FSIN , MVT::f32, Expand);
102 setOperationAction(ISD::FCOS , MVT::f32, Expand);
103 setOperationAction(ISD::FREM , MVT::f32, Expand);
104 setOperationAction(ISD::FPOW , MVT::f32, Expand);
106 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
108 // If we're enabling GP optimizations, use hardware square root
109 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
110 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
111 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
114 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
115 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
117 // PowerPC does not have BSWAP, CTPOP or CTTZ
118 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
119 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
120 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
121 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
122 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
123 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
125 // PowerPC does not have ROTR
126 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
127 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
129 // PowerPC does not have Select
130 setOperationAction(ISD::SELECT, MVT::i32, Expand);
131 setOperationAction(ISD::SELECT, MVT::i64, Expand);
132 setOperationAction(ISD::SELECT, MVT::f32, Expand);
133 setOperationAction(ISD::SELECT, MVT::f64, Expand);
135 // PowerPC wants to turn select_cc of FP into fsel when possible.
136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
139 // PowerPC wants to optimize integer setcc a bit
140 setOperationAction(ISD::SETCC, MVT::i32, Custom);
142 // PowerPC does not have BRCOND which requires SetCC
143 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
145 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
147 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
148 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
150 // PowerPC does not have [U|S]INT_TO_FP
151 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
152 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
154 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
155 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
156 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
157 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
159 // We cannot sextinreg(i1). Expand to shifts.
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
162 // Support label based line numbers.
163 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
164 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
166 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
167 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
168 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
169 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
172 // We want to legalize GlobalAddress and ConstantPool nodes into the
173 // appropriate instructions to materialize the address.
174 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
175 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
176 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
177 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
178 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
179 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
180 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
181 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
183 // RET must be custom lowered, to meet ABI requirements.
184 setOperationAction(ISD::RET , MVT::Other, Custom);
187 setOperationAction(ISD::TRAP, MVT::Other, Legal);
189 // TRAMPOLINE is custom lowered.
190 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
192 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
193 setOperationAction(ISD::VASTART , MVT::Other, Custom);
195 // VAARG is custom lowered with ELF 32 ABI
196 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
197 setOperationAction(ISD::VAARG, MVT::Other, Custom);
199 setOperationAction(ISD::VAARG, MVT::Other, Expand);
201 // Use the default implementation.
202 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
203 setOperationAction(ISD::VAEND , MVT::Other, Expand);
204 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
205 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
209 // We want to custom lower some of our intrinsics.
210 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
212 // Comparisons that require checking two conditions.
213 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
214 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
215 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
216 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
217 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
218 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
219 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
220 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
221 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
222 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
223 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
224 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
226 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
227 // They also have instructions for converting between i64 and fp.
228 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
229 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
230 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
231 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
232 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
234 // FIXME: disable this lowered code. This generates 64-bit register values,
235 // and we don't model the fact that the top part is clobbered by calls. We
236 // need to flag these together so that the value isn't live across a call.
237 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
239 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
240 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
242 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
243 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
246 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
247 // 64-bit PowerPC implementations can support i64 types directly
248 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
249 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
250 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
251 // 64-bit PowerPC wants to expand i128 shifts itself.
252 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
253 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
254 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
256 // 32-bit PowerPC wants to expand i64 shifts itself.
257 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
258 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
259 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
262 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
263 // First set operation action for all vector types to expand. Then we
264 // will selectively turn on ones that can be effectively codegen'd.
265 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
266 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
267 MVT VT = (MVT::SimpleValueType)i;
269 // add/sub are legal for all supported vector VT's.
270 setOperationAction(ISD::ADD , VT, Legal);
271 setOperationAction(ISD::SUB , VT, Legal);
273 // We promote all shuffles to v16i8.
274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
275 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
277 // We promote all non-typed operations to v4i32.
278 setOperationAction(ISD::AND , VT, Promote);
279 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
280 setOperationAction(ISD::OR , VT, Promote);
281 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
282 setOperationAction(ISD::XOR , VT, Promote);
283 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
284 setOperationAction(ISD::LOAD , VT, Promote);
285 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
286 setOperationAction(ISD::SELECT, VT, Promote);
287 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
288 setOperationAction(ISD::STORE, VT, Promote);
289 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
291 // No other operations are legal.
292 setOperationAction(ISD::MUL , VT, Expand);
293 setOperationAction(ISD::SDIV, VT, Expand);
294 setOperationAction(ISD::SREM, VT, Expand);
295 setOperationAction(ISD::UDIV, VT, Expand);
296 setOperationAction(ISD::UREM, VT, Expand);
297 setOperationAction(ISD::FDIV, VT, Expand);
298 setOperationAction(ISD::FNEG, VT, Expand);
299 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
300 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
301 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
302 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
303 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
304 setOperationAction(ISD::UDIVREM, VT, Expand);
305 setOperationAction(ISD::SDIVREM, VT, Expand);
306 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
307 setOperationAction(ISD::FPOW, VT, Expand);
308 setOperationAction(ISD::CTPOP, VT, Expand);
309 setOperationAction(ISD::CTLZ, VT, Expand);
310 setOperationAction(ISD::CTTZ, VT, Expand);
313 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
314 // with merges, splats, etc.
315 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
317 setOperationAction(ISD::AND , MVT::v4i32, Legal);
318 setOperationAction(ISD::OR , MVT::v4i32, Legal);
319 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
320 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
321 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
322 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
324 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
325 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
326 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
327 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
329 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
330 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
331 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
332 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
334 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
335 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
337 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
338 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
339 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
340 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
343 setShiftAmountType(MVT::i32);
344 setBooleanContents(ZeroOrOneBooleanContent);
346 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
347 setStackPointerRegisterToSaveRestore(PPC::X1);
348 setExceptionPointerRegister(PPC::X3);
349 setExceptionSelectorRegister(PPC::X4);
351 setStackPointerRegisterToSaveRestore(PPC::R1);
352 setExceptionPointerRegister(PPC::R3);
353 setExceptionSelectorRegister(PPC::R4);
356 // We have target-specific dag combine patterns for the following nodes:
357 setTargetDAGCombine(ISD::SINT_TO_FP);
358 setTargetDAGCombine(ISD::STORE);
359 setTargetDAGCombine(ISD::BR_CC);
360 setTargetDAGCombine(ISD::BSWAP);
362 // Darwin long double math library functions have $LDBL128 appended.
363 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
364 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
365 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
366 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
367 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
368 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
369 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
370 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
371 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
372 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
373 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
376 computeRegisterProperties();
379 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
380 /// function arguments in the caller parameter area.
381 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
382 TargetMachine &TM = getTargetMachine();
383 // Darwin passes everything on 4 byte boundary.
384 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
390 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
393 case PPCISD::FSEL: return "PPCISD::FSEL";
394 case PPCISD::FCFID: return "PPCISD::FCFID";
395 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
396 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
397 case PPCISD::STFIWX: return "PPCISD::STFIWX";
398 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
399 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
400 case PPCISD::VPERM: return "PPCISD::VPERM";
401 case PPCISD::Hi: return "PPCISD::Hi";
402 case PPCISD::Lo: return "PPCISD::Lo";
403 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
404 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
405 case PPCISD::SRL: return "PPCISD::SRL";
406 case PPCISD::SRA: return "PPCISD::SRA";
407 case PPCISD::SHL: return "PPCISD::SHL";
408 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
409 case PPCISD::STD_32: return "PPCISD::STD_32";
410 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
411 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
412 case PPCISD::MTCTR: return "PPCISD::MTCTR";
413 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
414 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
415 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
416 case PPCISD::MFCR: return "PPCISD::MFCR";
417 case PPCISD::VCMP: return "PPCISD::VCMP";
418 case PPCISD::VCMPo: return "PPCISD::VCMPo";
419 case PPCISD::LBRX: return "PPCISD::LBRX";
420 case PPCISD::STBRX: return "PPCISD::STBRX";
421 case PPCISD::LARX: return "PPCISD::LARX";
422 case PPCISD::STCX: return "PPCISD::STCX";
423 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
424 case PPCISD::MFFS: return "PPCISD::MFFS";
425 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
426 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
427 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
428 case PPCISD::MTFSF: return "PPCISD::MTFSF";
429 case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
430 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
435 MVT PPCTargetLowering::getSetCCResultType(MVT VT) const {
440 //===----------------------------------------------------------------------===//
441 // Node matching predicates, for use by the tblgen matching code.
442 //===----------------------------------------------------------------------===//
444 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
445 static bool isFloatingPointZero(SDValue Op) {
446 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
447 return CFP->getValueAPF().isZero();
448 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
449 // Maybe this has already been legalized into the constant pool?
450 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
451 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
452 return CFP->getValueAPF().isZero();
457 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
458 /// true if Op is undef or if it matches the specified value.
459 static bool isConstantOrUndef(SDValue Op, unsigned Val) {
460 return Op.getOpcode() == ISD::UNDEF ||
461 cast<ConstantSDNode>(Op)->getZExtValue() == Val;
464 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
465 /// VPKUHUM instruction.
466 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
468 for (unsigned i = 0; i != 16; ++i)
469 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
472 for (unsigned i = 0; i != 8; ++i)
473 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
474 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
480 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
481 /// VPKUWUM instruction.
482 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
484 for (unsigned i = 0; i != 16; i += 2)
485 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
486 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
489 for (unsigned i = 0; i != 8; i += 2)
490 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
491 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
492 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
493 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
499 /// isVMerge - Common function, used to match vmrg* shuffles.
501 static bool isVMerge(SDNode *N, unsigned UnitSize,
502 unsigned LHSStart, unsigned RHSStart) {
503 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
504 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
505 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
506 "Unsupported merge size!");
508 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
509 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
510 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
511 LHSStart+j+i*UnitSize) ||
512 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
513 RHSStart+j+i*UnitSize))
519 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
520 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
521 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
523 return isVMerge(N, UnitSize, 8, 24);
524 return isVMerge(N, UnitSize, 8, 8);
527 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
528 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
529 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
531 return isVMerge(N, UnitSize, 0, 16);
532 return isVMerge(N, UnitSize, 0, 0);
536 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
537 /// amount, otherwise return -1.
538 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
539 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
540 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
541 // Find the first non-undef value in the shuffle mask.
543 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
546 if (i == 16) return -1; // all undef.
548 // Otherwise, check to see if the rest of the elements are consequtively
549 // numbered from this value.
550 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getZExtValue();
551 if (ShiftAmt < i) return -1;
555 // Check the rest of the elements to see if they are consequtive.
556 for (++i; i != 16; ++i)
557 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
560 // Check the rest of the elements to see if they are consequtive.
561 for (++i; i != 16; ++i)
562 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
569 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
570 /// specifies a splat of a single element that is suitable for input to
571 /// VSPLTB/VSPLTH/VSPLTW.
572 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
573 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
574 N->getNumOperands() == 16 &&
575 (EltSize == 1 || EltSize == 2 || EltSize == 4));
577 // This is a splat operation if each element of the permute is the same, and
578 // if the value doesn't reference the second vector.
579 unsigned ElementBase = 0;
580 SDValue Elt = N->getOperand(0);
581 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
582 ElementBase = EltV->getZExtValue();
584 return false; // FIXME: Handle UNDEF elements too!
586 if (cast<ConstantSDNode>(Elt)->getZExtValue() >= 16)
589 // Check that they are consequtive.
590 for (unsigned i = 1; i != EltSize; ++i) {
591 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
592 cast<ConstantSDNode>(N->getOperand(i))->getZExtValue() != i+ElementBase)
596 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
597 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
598 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
599 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
600 "Invalid VECTOR_SHUFFLE mask!");
601 for (unsigned j = 0; j != EltSize; ++j)
602 if (N->getOperand(i+j) != N->getOperand(j))
609 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
611 bool PPC::isAllNegativeZeroVector(SDNode *N) {
612 assert(N->getOpcode() == ISD::BUILD_VECTOR);
613 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
614 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
615 return CFP->getValueAPF().isNegZero();
619 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
620 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
621 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
622 assert(isSplatShuffleMask(N, EltSize));
623 return cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() / EltSize;
626 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
627 /// by using a vspltis[bhw] instruction of the specified element size, return
628 /// the constant being splatted. The ByteSize field indicates the number of
629 /// bytes of each element [124] -> [bhw].
630 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
633 // If ByteSize of the splat is bigger than the element size of the
634 // build_vector, then we have a case where we are checking for a splat where
635 // multiple elements of the buildvector are folded together into a single
636 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
637 unsigned EltSize = 16/N->getNumOperands();
638 if (EltSize < ByteSize) {
639 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
640 SDValue UniquedVals[4];
641 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
643 // See if all of the elements in the buildvector agree across.
644 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
645 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
646 // If the element isn't a constant, bail fully out.
647 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
650 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
651 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
652 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
653 return SDValue(); // no match.
656 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
657 // either constant or undef values that are identical for each chunk. See
658 // if these chunks can form into a larger vspltis*.
660 // Check to see if all of the leading entries are either 0 or -1. If
661 // neither, then this won't fit into the immediate field.
662 bool LeadingZero = true;
663 bool LeadingOnes = true;
664 for (unsigned i = 0; i != Multiple-1; ++i) {
665 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
667 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
668 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
670 // Finally, check the least significant entry.
672 if (UniquedVals[Multiple-1].getNode() == 0)
673 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
674 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
676 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
679 if (UniquedVals[Multiple-1].getNode() == 0)
680 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
681 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
682 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
683 return DAG.getTargetConstant(Val, MVT::i32);
689 // Check to see if this buildvec has a single non-undef value in its elements.
690 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
691 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
692 if (OpVal.getNode() == 0)
693 OpVal = N->getOperand(i);
694 else if (OpVal != N->getOperand(i))
698 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
700 unsigned ValSizeInBytes = 0;
702 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
703 Value = CN->getZExtValue();
704 ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8;
705 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
706 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
707 Value = FloatToBits(CN->getValueAPF().convertToFloat());
711 // If the splat value is larger than the element value, then we can never do
712 // this splat. The only case that we could fit the replicated bits into our
713 // immediate field for would be zero, and we prefer to use vxor for it.
714 if (ValSizeInBytes < ByteSize) return SDValue();
716 // If the element value is larger than the splat value, cut it in half and
717 // check to see if the two halves are equal. Continue doing this until we
718 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
719 while (ValSizeInBytes > ByteSize) {
720 ValSizeInBytes >>= 1;
722 // If the top half equals the bottom half, we're still ok.
723 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
724 (Value & ((1 << (8*ValSizeInBytes))-1)))
728 // Properly sign extend the value.
729 int ShAmt = (4-ByteSize)*8;
730 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
732 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
733 if (MaskVal == 0) return SDValue();
735 // Finally, if this value fits in a 5 bit sext field, return it
736 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
737 return DAG.getTargetConstant(MaskVal, MVT::i32);
741 //===----------------------------------------------------------------------===//
742 // Addressing Mode Selection
743 //===----------------------------------------------------------------------===//
745 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
746 /// or 64-bit immediate, and if the value can be accurately represented as a
747 /// sign extension from a 16-bit value. If so, this returns true and the
749 static bool isIntS16Immediate(SDNode *N, short &Imm) {
750 if (N->getOpcode() != ISD::Constant)
753 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
754 if (N->getValueType(0) == MVT::i32)
755 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
757 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
759 static bool isIntS16Immediate(SDValue Op, short &Imm) {
760 return isIntS16Immediate(Op.getNode(), Imm);
764 /// SelectAddressRegReg - Given the specified addressed, check to see if it
765 /// can be represented as an indexed [r+r] operation. Returns false if it
766 /// can be more efficiently represented with [r+imm].
767 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
769 SelectionDAG &DAG) const {
771 if (N.getOpcode() == ISD::ADD) {
772 if (isIntS16Immediate(N.getOperand(1), imm))
774 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
777 Base = N.getOperand(0);
778 Index = N.getOperand(1);
780 } else if (N.getOpcode() == ISD::OR) {
781 if (isIntS16Immediate(N.getOperand(1), imm))
782 return false; // r+i can fold it if we can.
784 // If this is an or of disjoint bitfields, we can codegen this as an add
785 // (for better address arithmetic) if the LHS and RHS of the OR are provably
787 APInt LHSKnownZero, LHSKnownOne;
788 APInt RHSKnownZero, RHSKnownOne;
789 DAG.ComputeMaskedBits(N.getOperand(0),
790 APInt::getAllOnesValue(N.getOperand(0)
791 .getValueSizeInBits()),
792 LHSKnownZero, LHSKnownOne);
794 if (LHSKnownZero.getBoolValue()) {
795 DAG.ComputeMaskedBits(N.getOperand(1),
796 APInt::getAllOnesValue(N.getOperand(1)
797 .getValueSizeInBits()),
798 RHSKnownZero, RHSKnownOne);
799 // If all of the bits are known zero on the LHS or RHS, the add won't
801 if (~(LHSKnownZero | RHSKnownZero) == 0) {
802 Base = N.getOperand(0);
803 Index = N.getOperand(1);
812 /// Returns true if the address N can be represented by a base register plus
813 /// a signed 16-bit displacement [r+imm], and if it is not better
814 /// represented as reg+reg.
815 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
817 SelectionDAG &DAG) const {
818 // FIXME dl should come from parent load or store, not from address
819 DebugLoc dl = N.getDebugLoc();
820 // If this can be more profitably realized as r+r, fail.
821 if (SelectAddressRegReg(N, Disp, Base, DAG))
824 if (N.getOpcode() == ISD::ADD) {
826 if (isIntS16Immediate(N.getOperand(1), imm)) {
827 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
828 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
829 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
831 Base = N.getOperand(0);
833 return true; // [r+i]
834 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
835 // Match LOAD (ADD (X, Lo(G))).
836 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
837 && "Cannot handle constant offsets yet!");
838 Disp = N.getOperand(1).getOperand(0); // The global address.
839 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
840 Disp.getOpcode() == ISD::TargetConstantPool ||
841 Disp.getOpcode() == ISD::TargetJumpTable);
842 Base = N.getOperand(0);
843 return true; // [&g+r]
845 } else if (N.getOpcode() == ISD::OR) {
847 if (isIntS16Immediate(N.getOperand(1), imm)) {
848 // If this is an or of disjoint bitfields, we can codegen this as an add
849 // (for better address arithmetic) if the LHS and RHS of the OR are
850 // provably disjoint.
851 APInt LHSKnownZero, LHSKnownOne;
852 DAG.ComputeMaskedBits(N.getOperand(0),
853 APInt::getAllOnesValue(N.getOperand(0)
854 .getValueSizeInBits()),
855 LHSKnownZero, LHSKnownOne);
857 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
858 // If all of the bits are known zero on the LHS or RHS, the add won't
860 Base = N.getOperand(0);
861 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
865 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
866 // Loading from a constant address.
868 // If this address fits entirely in a 16-bit sext immediate field, codegen
871 if (isIntS16Immediate(CN, Imm)) {
872 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
873 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
877 // Handle 32-bit sext immediates with LIS + addr mode.
878 if (CN->getValueType(0) == MVT::i32 ||
879 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
880 int Addr = (int)CN->getZExtValue();
882 // Otherwise, break this down into an LIS + disp.
883 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
885 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
886 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
887 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
892 Disp = DAG.getTargetConstant(0, getPointerTy());
893 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
894 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
897 return true; // [r+0]
900 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
901 /// represented as an indexed [r+r] operation.
902 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
904 SelectionDAG &DAG) const {
905 // Check to see if we can easily represent this as an [r+r] address. This
906 // will fail if it thinks that the address is more profitably represented as
907 // reg+imm, e.g. where imm = 0.
908 if (SelectAddressRegReg(N, Base, Index, DAG))
911 // If the operand is an addition, always emit this as [r+r], since this is
912 // better (for code size, and execution, as the memop does the add for free)
913 // than emitting an explicit add.
914 if (N.getOpcode() == ISD::ADD) {
915 Base = N.getOperand(0);
916 Index = N.getOperand(1);
920 // Otherwise, do it the hard way, using R0 as the base register.
921 Base = DAG.getRegister(PPC::R0, N.getValueType());
926 /// SelectAddressRegImmShift - Returns true if the address N can be
927 /// represented by a base register plus a signed 14-bit displacement
928 /// [r+imm*4]. Suitable for use by STD and friends.
929 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
931 SelectionDAG &DAG) const {
932 // FIXME dl should come from the parent load or store, not the address
933 DebugLoc dl = N.getDebugLoc();
934 // If this can be more profitably realized as r+r, fail.
935 if (SelectAddressRegReg(N, Disp, Base, DAG))
938 if (N.getOpcode() == ISD::ADD) {
940 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
941 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
942 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
943 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
945 Base = N.getOperand(0);
947 return true; // [r+i]
948 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
949 // Match LOAD (ADD (X, Lo(G))).
950 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
951 && "Cannot handle constant offsets yet!");
952 Disp = N.getOperand(1).getOperand(0); // The global address.
953 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
954 Disp.getOpcode() == ISD::TargetConstantPool ||
955 Disp.getOpcode() == ISD::TargetJumpTable);
956 Base = N.getOperand(0);
957 return true; // [&g+r]
959 } else if (N.getOpcode() == ISD::OR) {
961 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
962 // If this is an or of disjoint bitfields, we can codegen this as an add
963 // (for better address arithmetic) if the LHS and RHS of the OR are
964 // provably disjoint.
965 APInt LHSKnownZero, LHSKnownOne;
966 DAG.ComputeMaskedBits(N.getOperand(0),
967 APInt::getAllOnesValue(N.getOperand(0)
968 .getValueSizeInBits()),
969 LHSKnownZero, LHSKnownOne);
970 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
971 // If all of the bits are known zero on the LHS or RHS, the add won't
973 Base = N.getOperand(0);
974 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
978 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
979 // Loading from a constant address. Verify low two bits are clear.
980 if ((CN->getZExtValue() & 3) == 0) {
981 // If this address fits entirely in a 14-bit sext immediate field, codegen
984 if (isIntS16Immediate(CN, Imm)) {
985 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
986 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
990 // Fold the low-part of 32-bit absolute addresses into addr mode.
991 if (CN->getValueType(0) == MVT::i32 ||
992 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
993 int Addr = (int)CN->getZExtValue();
995 // Otherwise, break this down into an LIS + disp.
996 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
997 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
998 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
999 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0);
1005 Disp = DAG.getTargetConstant(0, getPointerTy());
1006 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1007 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1010 return true; // [r+0]
1014 /// getPreIndexedAddressParts - returns true by value, base pointer and
1015 /// offset pointer and addressing mode by reference if the node's address
1016 /// can be legally represented as pre-indexed load / store address.
1017 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1019 ISD::MemIndexedMode &AM,
1020 SelectionDAG &DAG) const {
1021 // Disabled by default for now.
1022 if (!EnablePPCPreinc) return false;
1026 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1027 Ptr = LD->getBasePtr();
1028 VT = LD->getMemoryVT();
1030 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1032 Ptr = ST->getBasePtr();
1033 VT = ST->getMemoryVT();
1037 // PowerPC doesn't have preinc load/store instructions for vectors.
1041 // TODO: Check reg+reg first.
1043 // LDU/STU use reg+imm*4, others use reg+imm.
1044 if (VT != MVT::i64) {
1046 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1050 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1054 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1055 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1056 // sext i32 to i64 when addr mode is r+i.
1057 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1058 LD->getExtensionType() == ISD::SEXTLOAD &&
1059 isa<ConstantSDNode>(Offset))
1067 //===----------------------------------------------------------------------===//
1068 // LowerOperation implementation
1069 //===----------------------------------------------------------------------===//
1071 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1072 SelectionDAG &DAG) {
1073 MVT PtrVT = Op.getValueType();
1074 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1075 Constant *C = CP->getConstVal();
1076 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1077 SDValue Zero = DAG.getConstant(0, PtrVT);
1079 const TargetMachine &TM = DAG.getTarget();
1081 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1082 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1084 // If this is a non-darwin platform, we don't support non-static relo models
1086 if (TM.getRelocationModel() == Reloc::Static ||
1087 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1088 // Generate non-pic code that has direct accesses to the constant pool.
1089 // The address of the global is just (hi(&g)+lo(&g)).
1090 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1093 if (TM.getRelocationModel() == Reloc::PIC_) {
1094 // With PIC, the first instruction is actually "GR+hi(&G)".
1095 Hi = DAG.getNode(ISD::ADD, PtrVT,
1096 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1099 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1103 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1104 MVT PtrVT = Op.getValueType();
1105 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1106 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1107 SDValue Zero = DAG.getConstant(0, PtrVT);
1109 const TargetMachine &TM = DAG.getTarget();
1111 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1112 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1114 // If this is a non-darwin platform, we don't support non-static relo models
1116 if (TM.getRelocationModel() == Reloc::Static ||
1117 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1118 // Generate non-pic code that has direct accesses to the constant pool.
1119 // The address of the global is just (hi(&g)+lo(&g)).
1120 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1123 if (TM.getRelocationModel() == Reloc::PIC_) {
1124 // With PIC, the first instruction is actually "GR+hi(&G)".
1125 Hi = DAG.getNode(ISD::ADD, PtrVT,
1126 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1129 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1133 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1134 SelectionDAG &DAG) {
1135 assert(0 && "TLS not implemented for PPC.");
1136 return SDValue(); // Not reached
1139 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1140 SelectionDAG &DAG) {
1141 MVT PtrVT = Op.getValueType();
1142 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1143 GlobalValue *GV = GSDN->getGlobal();
1144 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1145 SDValue Zero = DAG.getConstant(0, PtrVT);
1146 DebugLoc dl = GSDN->getDebugLoc();
1148 const TargetMachine &TM = DAG.getTarget();
1150 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1151 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1153 // If this is a non-darwin platform, we don't support non-static relo models
1155 if (TM.getRelocationModel() == Reloc::Static ||
1156 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1157 // Generate non-pic code that has direct accesses to globals.
1158 // The address of the global is just (hi(&g)+lo(&g)).
1159 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1162 if (TM.getRelocationModel() == Reloc::PIC_) {
1163 // With PIC, the first instruction is actually "GR+hi(&G)".
1164 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1165 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1168 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1170 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1173 // If the global is weak or external, we have to go through the lazy
1175 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
1178 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1179 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1180 DebugLoc dl = Op.getNode()->getDebugLoc();
1182 // If we're comparing for equality to zero, expose the fact that this is
1183 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1184 // fold the new nodes.
1185 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1186 if (C->isNullValue() && CC == ISD::SETEQ) {
1187 MVT VT = Op.getOperand(0).getValueType();
1188 SDValue Zext = Op.getOperand(0);
1189 if (VT.bitsLT(MVT::i32)) {
1191 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1193 unsigned Log2b = Log2_32(VT.getSizeInBits());
1194 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1195 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1196 DAG.getConstant(Log2b, MVT::i32));
1197 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1199 // Leave comparisons against 0 and -1 alone for now, since they're usually
1200 // optimized. FIXME: revisit this when we can custom lower all setcc
1202 if (C->isAllOnesValue() || C->isNullValue())
1206 // If we have an integer seteq/setne, turn it into a compare against zero
1207 // by xor'ing the rhs with the lhs, which is faster than setting a
1208 // condition register, reading it back out, and masking the correct bit. The
1209 // normal approach here uses sub to do this instead of xor. Using xor exposes
1210 // the result to other bit-twiddling opportunities.
1211 MVT LHSVT = Op.getOperand(0).getValueType();
1212 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1213 MVT VT = Op.getValueType();
1214 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1216 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1221 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1222 int VarArgsFrameIndex,
1223 int VarArgsStackOffset,
1224 unsigned VarArgsNumGPR,
1225 unsigned VarArgsNumFPR,
1226 const PPCSubtarget &Subtarget) {
1228 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1229 return SDValue(); // Not reached
1232 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1233 SDValue Chain = Op.getOperand(0);
1234 SDValue Trmp = Op.getOperand(1); // trampoline
1235 SDValue FPtr = Op.getOperand(2); // nested function
1236 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1237 DebugLoc dl = Op.getNode()->getDebugLoc();
1239 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1240 bool isPPC64 = (PtrVT == MVT::i64);
1241 const Type *IntPtrTy =
1242 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType();
1244 TargetLowering::ArgListTy Args;
1245 TargetLowering::ArgListEntry Entry;
1247 Entry.Ty = IntPtrTy;
1248 Entry.Node = Trmp; Args.push_back(Entry);
1250 // TrampSize == (isPPC64 ? 48 : 40);
1251 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1252 isPPC64 ? MVT::i64 : MVT::i32);
1253 Args.push_back(Entry);
1255 Entry.Node = FPtr; Args.push_back(Entry);
1256 Entry.Node = Nest; Args.push_back(Entry);
1258 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1259 std::pair<SDValue, SDValue> CallResult =
1260 LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false,
1261 false, false, CallingConv::C, false,
1262 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1266 { CallResult.first, CallResult.second };
1268 return DAG.getMergeValues(Ops, 2, dl);
1271 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1272 int VarArgsFrameIndex,
1273 int VarArgsStackOffset,
1274 unsigned VarArgsNumGPR,
1275 unsigned VarArgsNumFPR,
1276 const PPCSubtarget &Subtarget) {
1277 DebugLoc dl = Op.getNode()->getDebugLoc();
1279 if (Subtarget.isMachoABI()) {
1280 // vastart just stores the address of the VarArgsFrameIndex slot into the
1281 // memory location argument.
1282 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1283 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1284 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1285 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1288 // For ELF 32 ABI we follow the layout of the va_list struct.
1289 // We suppose the given va_list is already allocated.
1292 // char gpr; /* index into the array of 8 GPRs
1293 // * stored in the register save area
1294 // * gpr=0 corresponds to r3,
1295 // * gpr=1 to r4, etc.
1297 // char fpr; /* index into the array of 8 FPRs
1298 // * stored in the register save area
1299 // * fpr=0 corresponds to f1,
1300 // * fpr=1 to f2, etc.
1302 // char *overflow_arg_area;
1303 // /* location on stack that holds
1304 // * the next overflow argument
1306 // char *reg_save_area;
1307 // /* where r3:r10 and f1:f8 (if saved)
1313 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1314 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1317 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1319 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1320 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1322 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1323 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1325 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1326 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1328 uint64_t FPROffset = 1;
1329 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1331 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1333 // Store first byte : number of int regs
1334 SDValue firstStore = DAG.getStore(Op.getOperand(0), dl, ArgGPR,
1335 Op.getOperand(1), SV, 0);
1336 uint64_t nextOffset = FPROffset;
1337 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1340 // Store second byte : number of float regs
1341 SDValue secondStore =
1342 DAG.getStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset);
1343 nextOffset += StackOffset;
1344 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1346 // Store second word : arguments given on stack
1347 SDValue thirdStore =
1348 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
1349 nextOffset += FrameOffset;
1350 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1352 // Store third word : arguments given in registers
1353 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset);
1357 #include "PPCGenCallingConv.inc"
1359 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1360 /// depending on which subtarget is selected.
1361 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1362 if (Subtarget.isMachoABI()) {
1363 static const unsigned FPR[] = {
1364 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1365 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1371 static const unsigned FPR[] = {
1372 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1378 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1380 static unsigned CalculateStackSlotSize(SDValue Arg, ISD::ArgFlagsTy Flags,
1381 bool isVarArg, unsigned PtrByteSize) {
1382 MVT ArgVT = Arg.getValueType();
1383 unsigned ArgSize =ArgVT.getSizeInBits()/8;
1384 if (Flags.isByVal())
1385 ArgSize = Flags.getByValSize();
1386 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1392 PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1394 int &VarArgsFrameIndex,
1395 int &VarArgsStackOffset,
1396 unsigned &VarArgsNumGPR,
1397 unsigned &VarArgsNumFPR,
1398 const PPCSubtarget &Subtarget) {
1399 // TODO: add description of PPC stack frame format, or at least some docs.
1401 MachineFunction &MF = DAG.getMachineFunction();
1402 MachineFrameInfo *MFI = MF.getFrameInfo();
1403 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1404 SmallVector<SDValue, 8> ArgValues;
1405 SDValue Root = Op.getOperand(0);
1406 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1407 DebugLoc dl = Op.getNode()->getDebugLoc();
1409 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1410 bool isPPC64 = PtrVT == MVT::i64;
1411 bool isMachoABI = Subtarget.isMachoABI();
1412 bool isELF32_ABI = Subtarget.isELF32_ABI();
1413 // Potential tail calls could cause overwriting of argument stack slots.
1414 unsigned CC = MF.getFunction()->getCallingConv();
1415 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1416 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1418 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1419 // Area that is at least reserved in caller of this function.
1420 unsigned MinReservedArea = ArgOffset;
1422 static const unsigned GPR_32[] = { // 32-bit registers.
1423 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1424 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1426 static const unsigned GPR_64[] = { // 64-bit registers.
1427 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1428 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1431 static const unsigned *FPR = GetFPR(Subtarget);
1433 static const unsigned VR[] = {
1434 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1435 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1438 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1439 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1440 const unsigned Num_VR_Regs = array_lengthof( VR);
1442 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1444 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1446 // In 32-bit non-varargs functions, the stack space for vectors is after the
1447 // stack space for non-vectors. We do not use this space unless we have
1448 // too many vectors to fit in registers, something that only occurs in
1449 // constructed examples:), but we have to walk the arglist to figure
1450 // that out...for the pathological case, compute VecArgOffset as the
1451 // start of the vector parameter area. Computing VecArgOffset is the
1452 // entire point of the following loop.
1453 // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying
1454 // to handle Elf here.
1455 unsigned VecArgOffset = ArgOffset;
1456 if (!isVarArg && !isPPC64) {
1457 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e;
1459 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1460 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1461 ISD::ArgFlagsTy Flags =
1462 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1464 if (Flags.isByVal()) {
1465 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1466 ObjSize = Flags.getByValSize();
1468 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1469 VecArgOffset += ArgSize;
1473 switch(ObjectVT.getSimpleVT()) {
1474 default: assert(0 && "Unhandled argument type!");
1477 VecArgOffset += isPPC64 ? 8 : 4;
1479 case MVT::i64: // PPC64
1487 // Nothing to do, we're only looking at Nonvector args here.
1492 // We've found where the vector parameter area in memory is. Skip the
1493 // first 12 parameters; these don't use that memory.
1494 VecArgOffset = ((VecArgOffset+15)/16)*16;
1495 VecArgOffset += 12*16;
1497 // Add DAG nodes to load the arguments or copy them out of registers. On
1498 // entry to a function on PPC, the arguments start after the linkage area,
1499 // although the first ones are often in registers.
1501 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1502 // represented with two words (long long or double) must be copied to an
1503 // even GPR_idx value or to an even ArgOffset value.
1505 SmallVector<SDValue, 8> MemOps;
1506 unsigned nAltivecParamsAtEnd = 0;
1507 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1;
1508 ArgNo != e; ++ArgNo) {
1510 bool needsLoad = false;
1511 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1512 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1513 unsigned ArgSize = ObjSize;
1514 ISD::ArgFlagsTy Flags =
1515 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1516 // See if next argument requires stack alignment in ELF
1517 bool Align = Flags.isSplit();
1519 unsigned CurArgOffset = ArgOffset;
1521 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1522 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1523 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1524 if (isVarArg || isPPC64) {
1525 MinReservedArea = ((MinReservedArea+15)/16)*16;
1526 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1530 } else nAltivecParamsAtEnd++;
1532 // Calculate min reserved area.
1533 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1538 // FIXME alignment for ELF may not be right
1539 // FIXME the codegen can be much improved in some cases.
1540 // We do not have to keep everything in memory.
1541 if (Flags.isByVal()) {
1542 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1543 ObjSize = Flags.getByValSize();
1544 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1545 // Double word align in ELF
1546 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1547 // Objects of size 1 and 2 are right justified, everything else is
1548 // left justified. This means the memory address is adjusted forwards.
1549 if (ObjSize==1 || ObjSize==2) {
1550 CurArgOffset = CurArgOffset + (4 - ObjSize);
1552 // The value of the object is its address.
1553 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1554 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1555 ArgValues.push_back(FIN);
1556 if (ObjSize==1 || ObjSize==2) {
1557 if (GPR_idx != Num_GPR_Regs) {
1558 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1559 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1560 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1561 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1562 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1563 MemOps.push_back(Store);
1565 if (isMachoABI) ArgOffset += PtrByteSize;
1567 ArgOffset += PtrByteSize;
1571 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1572 // Store whatever pieces of the object are in registers
1573 // to memory. ArgVal will be address of the beginning of
1575 if (GPR_idx != Num_GPR_Regs) {
1576 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1577 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1578 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1579 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1580 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1581 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1582 MemOps.push_back(Store);
1584 if (isMachoABI) ArgOffset += PtrByteSize;
1586 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1593 switch (ObjectVT.getSimpleVT()) {
1594 default: assert(0 && "Unhandled argument type!");
1597 // Double word align in ELF
1598 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1600 if (GPR_idx != Num_GPR_Regs) {
1601 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1602 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1603 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1607 ArgSize = PtrByteSize;
1609 // Stack align in ELF
1610 if (needsLoad && Align && isELF32_ABI)
1611 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1612 // All int arguments reserve stack space in Macho ABI.
1613 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1617 case MVT::i64: // PPC64
1618 if (GPR_idx != Num_GPR_Regs) {
1619 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1620 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1621 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1623 if (ObjectVT == MVT::i32) {
1624 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1625 // value to MVT::i64 and then truncate to the correct register size.
1627 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1628 DAG.getValueType(ObjectVT));
1629 else if (Flags.isZExt())
1630 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1631 DAG.getValueType(ObjectVT));
1633 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1639 ArgSize = PtrByteSize;
1641 // All int arguments reserve stack space in Macho ABI.
1642 if (isMachoABI || needsLoad) ArgOffset += 8;
1647 // Every 4 bytes of argument space consumes one of the GPRs available for
1648 // argument passing.
1649 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1651 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1654 if (FPR_idx != Num_FPR_Regs) {
1656 if (ObjectVT == MVT::f32)
1657 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1659 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1660 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1661 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1667 // Stack align in ELF
1668 if (needsLoad && Align && isELF32_ABI)
1669 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1670 // All FP arguments reserve stack space in Macho ABI.
1671 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1677 // Note that vector arguments in registers don't reserve stack space,
1678 // except in varargs functions.
1679 if (VR_idx != Num_VR_Regs) {
1680 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1681 RegInfo.addLiveIn(VR[VR_idx], VReg);
1682 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1684 while ((ArgOffset % 16) != 0) {
1685 ArgOffset += PtrByteSize;
1686 if (GPR_idx != Num_GPR_Regs)
1690 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1694 if (!isVarArg && !isPPC64) {
1695 // Vectors go after all the nonvectors.
1696 CurArgOffset = VecArgOffset;
1699 // Vectors are aligned.
1700 ArgOffset = ((ArgOffset+15)/16)*16;
1701 CurArgOffset = ArgOffset;
1709 // We need to load the argument to a virtual register if we determined above
1710 // that we ran out of physical registers of the appropriate type.
1712 int FI = MFI->CreateFixedObject(ObjSize,
1713 CurArgOffset + (ArgSize - ObjSize),
1715 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1716 ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
1719 ArgValues.push_back(ArgVal);
1722 // Set the size that is at least reserved in caller of this function. Tail
1723 // call optimized function's reserved stack space needs to be aligned so that
1724 // taking the difference between two stack areas will result in an aligned
1726 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1727 // Add the Altivec parameters at the end, if needed.
1728 if (nAltivecParamsAtEnd) {
1729 MinReservedArea = ((MinReservedArea+15)/16)*16;
1730 MinReservedArea += 16*nAltivecParamsAtEnd;
1733 std::max(MinReservedArea,
1734 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1735 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1736 getStackAlignment();
1737 unsigned AlignMask = TargetAlign-1;
1738 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1739 FI->setMinReservedArea(MinReservedArea);
1741 // If the function takes variable number of arguments, make a frame index for
1742 // the start of the first vararg value... for expansion of llvm.va_start.
1747 VarArgsNumGPR = GPR_idx;
1748 VarArgsNumFPR = FPR_idx;
1750 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1752 depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 +
1753 Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 +
1754 PtrVT.getSizeInBits()/8);
1756 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1763 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1765 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1767 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1768 // stored to the VarArgsFrameIndex on the stack.
1770 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1771 SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1772 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
1773 MemOps.push_back(Store);
1774 // Increment the address by four for the next argument to store
1775 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1776 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1780 // If this function is vararg, store any remaining integer argument regs
1781 // to their spots on the stack so that they may be loaded by deferencing the
1782 // result of va_next.
1783 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1786 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1788 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1790 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1791 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1792 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1793 MemOps.push_back(Store);
1794 // Increment the address by four for the next argument to store
1795 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1796 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1799 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1802 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1803 SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1804 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
1805 MemOps.push_back(Store);
1806 // Increment the address by eight for the next argument to store
1807 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1809 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1812 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1814 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1816 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1817 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64);
1818 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1819 MemOps.push_back(Store);
1820 // Increment the address by eight for the next argument to store
1821 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1823 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1828 if (!MemOps.empty())
1829 Root = DAG.getNode(ISD::TokenFactor, dl,
1830 MVT::Other, &MemOps[0], MemOps.size());
1832 ArgValues.push_back(Root);
1834 // Return the new list of results.
1835 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1836 &ArgValues[0], ArgValues.size());
1839 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
1842 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
1847 CallSDNode *TheCall,
1848 unsigned &nAltivecParamsAtEnd) {
1849 // Count how many bytes are to be pushed on the stack, including the linkage
1850 // area, and parameter passing area. We start with 24/48 bytes, which is
1851 // prereserved space for [SP][CR][LR][3 x unused].
1852 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1853 unsigned NumOps = TheCall->getNumArgs();
1854 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1856 // Add up all the space actually used.
1857 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
1858 // they all go in registers, but we must reserve stack space for them for
1859 // possible use by the caller. In varargs or 64-bit calls, parameters are
1860 // assigned stack space in order, with padding so Altivec parameters are
1862 nAltivecParamsAtEnd = 0;
1863 for (unsigned i = 0; i != NumOps; ++i) {
1864 SDValue Arg = TheCall->getArg(i);
1865 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1866 MVT ArgVT = Arg.getValueType();
1867 // Varargs Altivec parameters are padded to a 16 byte boundary.
1868 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
1869 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
1870 if (!isVarArg && !isPPC64) {
1871 // Non-varargs Altivec parameters go after all the non-Altivec
1872 // parameters; handle those later so we know how much padding we need.
1873 nAltivecParamsAtEnd++;
1876 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
1877 NumBytes = ((NumBytes+15)/16)*16;
1879 NumBytes += CalculateStackSlotSize(Arg, Flags, isVarArg, PtrByteSize);
1882 // Allow for Altivec parameters at the end, if needed.
1883 if (nAltivecParamsAtEnd) {
1884 NumBytes = ((NumBytes+15)/16)*16;
1885 NumBytes += 16*nAltivecParamsAtEnd;
1888 // The prolog code of the callee may store up to 8 GPR argument registers to
1889 // the stack, allowing va_start to index over them in memory if its varargs.
1890 // Because we cannot tell if this is needed on the caller side, we have to
1891 // conservatively assume that it is needed. As such, make sure we have at
1892 // least enough stack space for the caller to store the 8 GPRs.
1893 NumBytes = std::max(NumBytes,
1894 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1896 // Tail call needs the stack to be aligned.
1897 if (CC==CallingConv::Fast && PerformTailCallOpt) {
1898 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1899 getStackAlignment();
1900 unsigned AlignMask = TargetAlign-1;
1901 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
1907 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
1908 /// adjusted to accomodate the arguments for the tailcall.
1909 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
1910 unsigned ParamSize) {
1912 if (!IsTailCall) return 0;
1914 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
1915 unsigned CallerMinReservedArea = FI->getMinReservedArea();
1916 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
1917 // Remember only if the new adjustement is bigger.
1918 if (SPDiff < FI->getTailCallSPDelta())
1919 FI->setTailCallSPDelta(SPDiff);
1924 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1925 /// following the call is a return. A function is eligible if caller/callee
1926 /// calling conventions match, currently only fastcc supports tail calls, and
1927 /// the function CALL is immediatly followed by a RET.
1929 PPCTargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1931 SelectionDAG& DAG) const {
1932 // Variable argument functions are not supported.
1933 if (!PerformTailCallOpt || TheCall->isVarArg())
1936 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1937 MachineFunction &MF = DAG.getMachineFunction();
1938 unsigned CallerCC = MF.getFunction()->getCallingConv();
1939 unsigned CalleeCC = TheCall->getCallingConv();
1940 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1941 // Functions containing by val parameters are not supported.
1942 for (unsigned i = 0; i != TheCall->getNumArgs(); i++) {
1943 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1944 if (Flags.isByVal()) return false;
1947 SDValue Callee = TheCall->getCallee();
1948 // Non PIC/GOT tail calls are supported.
1949 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1952 // At the moment we can only do local tail calls (in same module, hidden
1953 // or protected) if we are generating PIC.
1954 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1955 return G->getGlobal()->hasHiddenVisibility()
1956 || G->getGlobal()->hasProtectedVisibility();
1963 /// isCallCompatibleAddress - Return the immediate to use if the specified
1964 /// 32-bit value is representable in the immediate field of a BxA instruction.
1965 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
1966 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1969 int Addr = C->getZExtValue();
1970 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1971 (Addr << 6 >> 6) != Addr)
1972 return 0; // Top 6 bits have to be sext of immediate.
1974 return DAG.getConstant((int)C->getZExtValue() >> 2,
1975 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
1980 struct TailCallArgumentInfo {
1985 TailCallArgumentInfo() : FrameIdx(0) {}
1990 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
1992 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
1994 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
1995 SmallVector<SDValue, 8> &MemOpChains,
1997 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
1998 SDValue Arg = TailCallArgs[i].Arg;
1999 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2000 int FI = TailCallArgs[i].FrameIdx;
2001 // Store relative to framepointer.
2002 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2003 PseudoSourceValue::getFixedStack(FI),
2008 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2009 /// the appropriate stack slot for the tail call optimized function call.
2010 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2011 MachineFunction &MF,
2020 // Calculate the new stack slot for the return address.
2021 int SlotSize = isPPC64 ? 8 : 4;
2022 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2024 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2026 int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
2028 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
2030 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2031 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2032 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2033 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
2034 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2035 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2036 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
2041 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2042 /// the position of the argument.
2044 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2045 SDValue Arg, int SPDiff, unsigned ArgOffset,
2046 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2047 int Offset = ArgOffset + SPDiff;
2048 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2049 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
2050 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2051 SDValue FIN = DAG.getFrameIndex(FI, VT);
2052 TailCallArgumentInfo Info;
2054 Info.FrameIdxOp = FIN;
2056 TailCallArguments.push_back(Info);
2059 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2060 /// stack slot. Returns the chain as result and the loaded frame pointers in
2061 /// LROpOut/FPOpout. Used when tail calling.
2062 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2069 // Load the LR and FP stack slot for later adjusting.
2070 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2071 LROpOut = getReturnAddrFrameIndex(DAG);
2072 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
2073 Chain = SDValue(LROpOut.getNode(), 1);
2074 FPOpOut = getFramePointerFrameIndex(DAG);
2075 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
2076 Chain = SDValue(FPOpOut.getNode(), 1);
2081 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2082 /// by "Src" to address "Dst" of size "Size". Alignment information is
2083 /// specified by the specific parameter attribute. The copy will be passed as
2084 /// a byval function parameter.
2085 /// Sometimes what we are copying is the end of a larger object, the part that
2086 /// does not fit in registers.
2088 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2089 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2090 unsigned Size, DebugLoc dl) {
2091 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
2092 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2093 false, NULL, 0, NULL, 0);
2096 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2099 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2100 SDValue Arg, SDValue PtrOff, int SPDiff,
2101 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2102 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2103 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2105 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2110 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2112 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2113 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2114 DAG.getConstant(ArgOffset, PtrVT));
2116 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
2117 // Calculate and remember argument location.
2118 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2122 SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
2123 const PPCSubtarget &Subtarget,
2124 TargetMachine &TM) {
2125 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
2126 SDValue Chain = TheCall->getChain();
2127 bool isVarArg = TheCall->isVarArg();
2128 unsigned CC = TheCall->getCallingConv();
2129 bool isTailCall = TheCall->isTailCall()
2130 && CC == CallingConv::Fast && PerformTailCallOpt;
2131 SDValue Callee = TheCall->getCallee();
2132 unsigned NumOps = TheCall->getNumArgs();
2133 DebugLoc dl = TheCall->getDebugLoc();
2135 bool isMachoABI = Subtarget.isMachoABI();
2136 bool isELF32_ABI = Subtarget.isELF32_ABI();
2138 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2139 bool isPPC64 = PtrVT == MVT::i64;
2140 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2142 MachineFunction &MF = DAG.getMachineFunction();
2144 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
2145 // SelectExpr to use to put the arguments in the appropriate registers.
2146 std::vector<SDValue> args_to_use;
2148 // Mark this function as potentially containing a function that contains a
2149 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2150 // and restoring the callers stack pointer in this functions epilog. This is
2151 // done because by tail calling the called function might overwrite the value
2152 // in this function's (MF) stack pointer stack slot 0(SP).
2153 if (PerformTailCallOpt && CC==CallingConv::Fast)
2154 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2156 unsigned nAltivecParamsAtEnd = 0;
2158 // Count how many bytes are to be pushed on the stack, including the linkage
2159 // area, and parameter passing area. We start with 24/48 bytes, which is
2160 // prereserved space for [SP][CR][LR][3 x unused].
2162 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC,
2163 TheCall, nAltivecParamsAtEnd);
2165 // Calculate by how many bytes the stack has to be adjusted in case of tail
2166 // call optimization.
2167 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2169 // Adjust the stack pointer for the new arguments...
2170 // These operations are automatically eliminated by the prolog/epilog pass
2171 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2172 SDValue CallSeqStart = Chain;
2174 // Load the return address and frame pointer so it can be move somewhere else
2177 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
2179 // Set up a copy of the stack pointer for use loading and storing any
2180 // arguments that may not fit in the registers available for argument
2184 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2186 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2188 // Figure out which arguments are going to go in registers, and which in
2189 // memory. Also, if this is a vararg function, floating point operations
2190 // must be stored to our stack, and loaded into integer regs as well, if
2191 // any integer regs are available for argument passing.
2192 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
2193 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2195 static const unsigned GPR_32[] = { // 32-bit registers.
2196 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2197 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2199 static const unsigned GPR_64[] = { // 64-bit registers.
2200 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2201 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2203 static const unsigned *FPR = GetFPR(Subtarget);
2205 static const unsigned VR[] = {
2206 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2207 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2209 const unsigned NumGPRs = array_lengthof(GPR_32);
2210 const unsigned NumFPRs = isMachoABI ? 13 : 8;
2211 const unsigned NumVRs = array_lengthof( VR);
2213 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2215 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
2216 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2218 SmallVector<SDValue, 8> MemOpChains;
2219 for (unsigned i = 0; i != NumOps; ++i) {
2221 SDValue Arg = TheCall->getArg(i);
2222 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2223 // See if next argument requires stack alignment in ELF
2224 bool Align = Flags.isSplit();
2226 // PtrOff will be used to store the current argument to the stack if a
2227 // register cannot be found for it.
2230 // Stack align in ELF 32
2231 if (isELF32_ABI && Align)
2232 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
2233 StackPtr.getValueType());
2235 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2237 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
2239 // On PPC64, promote integers to 64-bit values.
2240 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2241 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2242 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2243 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
2246 // FIXME Elf untested, what are alignment rules?
2247 // FIXME memcpy is used way more than necessary. Correctness first.
2248 if (Flags.isByVal()) {
2249 unsigned Size = Flags.getByValSize();
2250 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2251 if (Size==1 || Size==2) {
2252 // Very small objects are passed right-justified.
2253 // Everything else is passed left-justified.
2254 MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2255 if (GPR_idx != NumGPRs) {
2256 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
2258 MemOpChains.push_back(Load.getValue(1));
2259 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2261 ArgOffset += PtrByteSize;
2263 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2264 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
2265 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2266 CallSeqStart.getNode()->getOperand(0),
2267 Flags, DAG, Size, dl);
2268 // This must go outside the CALLSEQ_START..END.
2269 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2270 CallSeqStart.getNode()->getOperand(1));
2271 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2272 NewCallSeqStart.getNode());
2273 Chain = CallSeqStart = NewCallSeqStart;
2274 ArgOffset += PtrByteSize;
2278 // Copy entire object into memory. There are cases where gcc-generated
2279 // code assumes it is there, even if it could be put entirely into
2280 // registers. (This is not what the doc says.)
2281 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2282 CallSeqStart.getNode()->getOperand(0),
2283 Flags, DAG, Size, dl);
2284 // This must go outside the CALLSEQ_START..END.
2285 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2286 CallSeqStart.getNode()->getOperand(1));
2287 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2288 Chain = CallSeqStart = NewCallSeqStart;
2289 // And copy the pieces of it that fit into registers.
2290 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2291 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
2292 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2293 if (GPR_idx != NumGPRs) {
2294 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
2295 MemOpChains.push_back(Load.getValue(1));
2296 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2298 ArgOffset += PtrByteSize;
2300 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2307 switch (Arg.getValueType().getSimpleVT()) {
2308 default: assert(0 && "Unexpected ValueType for argument!");
2311 // Double word align in ELF
2312 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2313 if (GPR_idx != NumGPRs) {
2314 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2316 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2317 isPPC64, isTailCall, false, MemOpChains,
2318 TailCallArguments, dl);
2321 if (inMem || isMachoABI) {
2322 // Stack align in ELF
2323 if (isELF32_ABI && Align)
2324 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2326 ArgOffset += PtrByteSize;
2331 if (FPR_idx != NumFPRs) {
2332 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
2335 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2336 MemOpChains.push_back(Store);
2338 // Float varargs are always shadowed in available integer registers
2339 if (GPR_idx != NumGPRs) {
2340 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2341 MemOpChains.push_back(Load.getValue(1));
2342 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2345 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
2346 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
2347 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
2348 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2349 MemOpChains.push_back(Load.getValue(1));
2350 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2354 // If we have any FPRs remaining, we may also have GPRs remaining.
2355 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2358 if (GPR_idx != NumGPRs)
2360 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
2361 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
2366 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2367 isPPC64, isTailCall, false, MemOpChains,
2368 TailCallArguments, dl);
2371 if (inMem || isMachoABI) {
2372 // Stack align in ELF
2373 if (isELF32_ABI && Align)
2374 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2378 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
2386 // These go aligned on the stack, or in the corresponding R registers
2387 // when within range. The Darwin PPC ABI doc claims they also go in
2388 // V registers; in fact gcc does this only for arguments that are
2389 // prototyped, not for those that match the ... We do it for all
2390 // arguments, seems to work.
2391 while (ArgOffset % 16 !=0) {
2392 ArgOffset += PtrByteSize;
2393 if (GPR_idx != NumGPRs)
2396 // We could elide this store in the case where the object fits
2397 // entirely in R registers. Maybe later.
2398 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2399 DAG.getConstant(ArgOffset, PtrVT));
2400 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2401 MemOpChains.push_back(Store);
2402 if (VR_idx != NumVRs) {
2403 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
2404 MemOpChains.push_back(Load.getValue(1));
2405 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
2408 for (unsigned i=0; i<16; i+=PtrByteSize) {
2409 if (GPR_idx == NumGPRs)
2411 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
2412 DAG.getConstant(i, PtrVT));
2413 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
2414 MemOpChains.push_back(Load.getValue(1));
2415 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2420 // Non-varargs Altivec params generally go in registers, but have
2421 // stack space allocated at the end.
2422 if (VR_idx != NumVRs) {
2423 // Doesn't have GPR space allocated.
2424 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
2425 } else if (nAltivecParamsAtEnd==0) {
2426 // We are emitting Altivec params in order.
2427 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2428 isPPC64, isTailCall, true, MemOpChains,
2429 TailCallArguments, dl);
2435 // If all Altivec parameters fit in registers, as they usually do,
2436 // they get stack space following the non-Altivec parameters. We
2437 // don't track this here because nobody below needs it.
2438 // If there are more Altivec parameters than fit in registers emit
2440 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
2442 // Offset is aligned; skip 1st 12 params which go in V registers.
2443 ArgOffset = ((ArgOffset+15)/16)*16;
2445 for (unsigned i = 0; i != NumOps; ++i) {
2446 SDValue Arg = TheCall->getArg(i);
2447 MVT ArgType = Arg.getValueType();
2448 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
2449 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
2452 // We are emitting Altivec params in order.
2453 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2454 isPPC64, isTailCall, true, MemOpChains,
2455 TailCallArguments, dl);
2462 if (!MemOpChains.empty())
2463 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2464 &MemOpChains[0], MemOpChains.size());
2466 // Build a sequence of copy-to-reg nodes chained together with token chain
2467 // and flag operands which copy the outgoing args into the appropriate regs.
2469 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2470 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2471 RegsToPass[i].second, InFlag);
2472 InFlag = Chain.getValue(1);
2475 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
2476 if (isVarArg && isELF32_ABI) {
2477 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
2478 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2479 InFlag = Chain.getValue(1);
2482 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2483 // might overwrite each other in case of tail call optimization.
2485 SmallVector<SDValue, 8> MemOpChains2;
2486 // Do not flag preceeding copytoreg stuff together with the following stuff.
2488 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2490 if (!MemOpChains2.empty())
2491 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2492 &MemOpChains2[0], MemOpChains2.size());
2494 // Store the return address to the appropriate stack slot.
2495 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2496 isPPC64, isMachoABI, dl);
2499 // Emit callseq_end just before tailcall node.
2501 SmallVector<SDValue, 8> CallSeqOps;
2502 SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2503 CallSeqOps.push_back(Chain);
2504 CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes, true));
2505 CallSeqOps.push_back(DAG.getIntPtrConstant(0, true));
2506 if (InFlag.getNode())
2507 CallSeqOps.push_back(InFlag);
2508 Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
2510 InFlag = Chain.getValue(1);
2513 std::vector<MVT> NodeTys;
2514 NodeTys.push_back(MVT::Other); // Returns a chain
2515 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2517 SmallVector<SDValue, 8> Ops;
2518 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
2520 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2521 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2522 // node so that legalize doesn't hack it.
2523 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2524 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2525 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2526 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2527 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2528 // If this is an absolute destination address, use the munged value.
2529 Callee = SDValue(Dest, 0);
2531 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2532 // to do the call, we can't use PPCISD::CALL.
2533 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2534 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2535 2 + (InFlag.getNode() != 0));
2536 InFlag = Chain.getValue(1);
2538 // Copy the callee address into R12/X12 on darwin.
2540 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
2541 Chain = DAG.getCopyToReg(Chain, dl, Reg, Callee, InFlag);
2542 InFlag = Chain.getValue(1);
2546 NodeTys.push_back(MVT::Other);
2547 NodeTys.push_back(MVT::Flag);
2548 Ops.push_back(Chain);
2549 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
2551 // Add CTR register as callee so a bctr can be emitted later.
2553 Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
2556 // If this is a direct call, pass the chain and the callee.
2557 if (Callee.getNode()) {
2558 Ops.push_back(Chain);
2559 Ops.push_back(Callee);
2561 // If this is a tail call add stack pointer delta.
2563 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2565 // Add argument registers to the end of the list so that they are known live
2567 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2568 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2569 RegsToPass[i].second.getValueType()));
2571 // When performing tail call optimization the callee pops its arguments off
2572 // the stack. Account for this here so these bytes can be pushed back on in
2573 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2574 int BytesCalleePops =
2575 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2577 if (InFlag.getNode())
2578 Ops.push_back(InFlag);
2582 assert(InFlag.getNode() &&
2583 "Flag must be set. Depend on flag being set in LowerRET");
2584 Chain = DAG.getNode(PPCISD::TAILCALL, dl,
2585 TheCall->getVTList(), &Ops[0], Ops.size());
2586 return SDValue(Chain.getNode(), Op.getResNo());
2589 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2590 InFlag = Chain.getValue(1);
2592 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2593 DAG.getIntPtrConstant(BytesCalleePops, true),
2595 if (TheCall->getValueType(0) != MVT::Other)
2596 InFlag = Chain.getValue(1);
2598 SmallVector<SDValue, 16> ResultVals;
2599 SmallVector<CCValAssign, 16> RVLocs;
2600 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
2601 CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
2602 CCInfo.AnalyzeCallResult(TheCall, RetCC_PPC);
2604 // Copy all of the result registers out of their specified physreg.
2605 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2606 CCValAssign &VA = RVLocs[i];
2607 MVT VT = VA.getValVT();
2608 assert(VA.isRegLoc() && "Can only return in registers!");
2609 Chain = DAG.getCopyFromReg(Chain, dl,
2610 VA.getLocReg(), VT, InFlag).getValue(1);
2611 ResultVals.push_back(Chain.getValue(0));
2612 InFlag = Chain.getValue(2);
2615 // If the function returns void, just return the chain.
2619 // Otherwise, merge everything together with a MERGE_VALUES node.
2620 ResultVals.push_back(Chain);
2621 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
2622 &ResultVals[0], ResultVals.size());
2623 return Res.getValue(Op.getResNo());
2626 SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
2627 TargetMachine &TM) {
2628 SmallVector<CCValAssign, 16> RVLocs;
2629 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
2630 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
2631 DebugLoc dl = Op.getDebugLoc();
2632 CCState CCInfo(CC, isVarArg, TM, RVLocs);
2633 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
2635 // If this is the first return lowered for this function, add the regs to the
2636 // liveout set for the function.
2637 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2638 for (unsigned i = 0; i != RVLocs.size(); ++i)
2639 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2642 SDValue Chain = Op.getOperand(0);
2644 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
2645 if (Chain.getOpcode() == PPCISD::TAILCALL) {
2646 SDValue TailCall = Chain;
2647 SDValue TargetAddress = TailCall.getOperand(1);
2648 SDValue StackAdjustment = TailCall.getOperand(2);
2650 assert(((TargetAddress.getOpcode() == ISD::Register &&
2651 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
2652 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
2653 TargetAddress.getOpcode() == ISD::TargetGlobalAddress ||
2654 isa<ConstantSDNode>(TargetAddress)) &&
2655 "Expecting an global address, external symbol, absolute value or register");
2657 assert(StackAdjustment.getOpcode() == ISD::Constant &&
2658 "Expecting a const value");
2660 SmallVector<SDValue,8> Operands;
2661 Operands.push_back(Chain.getOperand(0));
2662 Operands.push_back(TargetAddress);
2663 Operands.push_back(StackAdjustment);
2664 // Copy registers used by the call. Last operand is a flag so it is not
2666 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
2667 Operands.push_back(Chain.getOperand(i));
2669 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Operands[0],
2675 // Copy the result values into the output registers.
2676 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2677 CCValAssign &VA = RVLocs[i];
2678 assert(VA.isRegLoc() && "Can only return in registers!");
2679 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2680 Op.getOperand(i*2+1), Flag);
2681 Flag = Chain.getValue(1);
2685 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
2687 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
2690 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
2691 const PPCSubtarget &Subtarget) {
2692 // When we pop the dynamic allocation we need to restore the SP link.
2693 DebugLoc dl = Op.getNode()->getDebugLoc();
2695 // Get the corect type for pointers.
2696 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2698 // Construct the stack pointer operand.
2699 bool IsPPC64 = Subtarget.isPPC64();
2700 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2701 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
2703 // Get the operands for the STACKRESTORE.
2704 SDValue Chain = Op.getOperand(0);
2705 SDValue SaveSP = Op.getOperand(1);
2707 // Load the old link SP.
2708 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
2710 // Restore the stack pointer.
2711 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
2713 // Store the old link SP.
2714 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
2720 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
2721 MachineFunction &MF = DAG.getMachineFunction();
2722 bool IsPPC64 = PPCSubTarget.isPPC64();
2723 bool isMachoABI = PPCSubTarget.isMachoABI();
2724 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2726 // Get current frame pointer save index. The users of this index will be
2727 // primarily DYNALLOC instructions.
2728 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2729 int RASI = FI->getReturnAddrSaveIndex();
2731 // If the frame pointer save index hasn't been defined yet.
2733 // Find out what the fix offset of the frame pointer save area.
2734 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI);
2735 // Allocate the frame index for frame pointer save area.
2736 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
2738 FI->setReturnAddrSaveIndex(RASI);
2740 return DAG.getFrameIndex(RASI, PtrVT);
2744 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
2745 MachineFunction &MF = DAG.getMachineFunction();
2746 bool IsPPC64 = PPCSubTarget.isPPC64();
2747 bool isMachoABI = PPCSubTarget.isMachoABI();
2748 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2750 // Get current frame pointer save index. The users of this index will be
2751 // primarily DYNALLOC instructions.
2752 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2753 int FPSI = FI->getFramePointerSaveIndex();
2755 // If the frame pointer save index hasn't been defined yet.
2757 // Find out what the fix offset of the frame pointer save area.
2758 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2760 // Allocate the frame index for frame pointer save area.
2761 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
2763 FI->setFramePointerSaveIndex(FPSI);
2765 return DAG.getFrameIndex(FPSI, PtrVT);
2768 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
2770 const PPCSubtarget &Subtarget) {
2772 SDValue Chain = Op.getOperand(0);
2773 SDValue Size = Op.getOperand(1);
2775 // Get the corect type for pointers.
2776 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2778 SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT,
2779 DAG.getConstant(0, PtrVT), Size);
2780 // Construct a node for the frame pointer save index.
2781 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
2782 // Build a DYNALLOC node.
2783 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
2784 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2785 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2788 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2790 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
2791 // Not FP? Not a fsel.
2792 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
2793 !Op.getOperand(2).getValueType().isFloatingPoint())
2796 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2798 // Cannot handle SETEQ/SETNE.
2799 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDValue();
2801 MVT ResVT = Op.getValueType();
2802 MVT CmpVT = Op.getOperand(0).getValueType();
2803 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2804 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
2806 // If the RHS of the comparison is a 0.0, we don't need to do the
2807 // subtraction at all.
2808 if (isFloatingPointZero(RHS))
2810 default: break; // SETUO etc aren't handled by fsel.
2813 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2816 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2817 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2818 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2821 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2824 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2825 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2826 return DAG.getNode(PPCISD::FSEL, ResVT,
2827 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2832 default: break; // SETUO etc aren't handled by fsel.
2835 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2836 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2837 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2838 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2841 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2842 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2843 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2844 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2847 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2848 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2849 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2850 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2853 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2854 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2855 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2856 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2861 // FIXME: Split this code up when LegalizeDAGTypes lands.
2862 SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2864 assert(Op.getOperand(0).getValueType().isFloatingPoint());
2865 SDValue Src = Op.getOperand(0);
2866 if (Src.getValueType() == MVT::f32)
2867 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
2870 switch (Op.getValueType().getSimpleVT()) {
2871 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2873 Tmp = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Src);
2876 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
2880 // Convert the FP value to an int value through memory.
2881 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
2883 // Emit a store to the stack slot.
2884 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
2886 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2888 if (Op.getValueType() == MVT::i32)
2889 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
2890 DAG.getConstant(4, FIPtr.getValueType()));
2891 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
2894 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2895 DebugLoc dl = Op.getNode()->getDebugLoc();
2896 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
2897 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
2900 if (Op.getOperand(0).getValueType() == MVT::i64) {
2901 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
2902 MVT::f64, Op.getOperand(0));
2903 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
2904 if (Op.getValueType() == MVT::f32)
2905 FP = DAG.getNode(ISD::FP_ROUND, dl,
2906 MVT::f32, FP, DAG.getIntPtrConstant(0));
2910 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2911 "Unhandled SINT_TO_FP type in custom expander!");
2912 // Since we only generate this in 64-bit mode, we can take advantage of
2913 // 64-bit registers. In particular, sign extend the input value into the
2914 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2915 // then lfd it and fcfid it.
2916 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2917 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2918 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2919 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2921 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
2924 // STD the extended value into the stack slot.
2925 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
2926 MachineMemOperand::MOStore, 0, 8, 8);
2927 SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other,
2928 DAG.getEntryNode(), Ext64, FIdx,
2929 DAG.getMemOperand(MO));
2930 // Load the value as a double.
2931 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
2933 // FCFID it and return it.
2934 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
2935 if (Op.getValueType() == MVT::f32)
2936 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
2940 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
2941 DebugLoc dl = Op.getNode()->getDebugLoc();
2943 The rounding mode is in bits 30:31 of FPSR, and has the following
2950 FLT_ROUNDS, on the other hand, expects the following:
2957 To perform the conversion, we do:
2958 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2961 MachineFunction &MF = DAG.getMachineFunction();
2962 MVT VT = Op.getValueType();
2963 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2964 std::vector<MVT> NodeTys;
2965 SDValue MFFSreg, InFlag;
2967 // Save FP Control Word to register
2968 NodeTys.push_back(MVT::f64); // return register
2969 NodeTys.push_back(MVT::Flag); // unused in this context
2970 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
2972 // Save FP register to stack slot
2973 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2974 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2975 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
2976 StackSlot, NULL, 0);
2978 // Load FP Control Word from low 32 bits of stack slot.
2979 SDValue Four = DAG.getConstant(4, PtrVT);
2980 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
2981 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
2983 // Transform as necessary
2985 DAG.getNode(ISD::AND, dl, MVT::i32,
2986 CWD, DAG.getConstant(3, MVT::i32));
2988 DAG.getNode(ISD::SRL, dl, MVT::i32,
2989 DAG.getNode(ISD::AND, dl, MVT::i32,
2990 DAG.getNode(ISD::XOR, dl, MVT::i32,
2991 CWD, DAG.getConstant(3, MVT::i32)),
2992 DAG.getConstant(3, MVT::i32)),
2993 DAG.getConstant(1, MVT::i32));
2996 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
2998 return DAG.getNode((VT.getSizeInBits() < 16 ?
2999 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3002 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
3003 MVT VT = Op.getValueType();
3004 unsigned BitWidth = VT.getSizeInBits();
3005 DebugLoc dl = Op.getDebugLoc();
3006 assert(Op.getNumOperands() == 3 &&
3007 VT == Op.getOperand(1).getValueType() &&
3010 // Expand into a bunch of logical ops. Note that these ops
3011 // depend on the PPC behavior for oversized shift amounts.
3012 SDValue Lo = Op.getOperand(0);
3013 SDValue Hi = Op.getOperand(1);
3014 SDValue Amt = Op.getOperand(2);
3015 MVT AmtVT = Amt.getValueType();
3017 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3018 DAG.getConstant(BitWidth, AmtVT), Amt);
3019 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3020 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3021 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3022 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3023 DAG.getConstant(-BitWidth, AmtVT));
3024 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3025 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3026 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3027 SDValue OutOps[] = { OutLo, OutHi };
3028 return DAG.getMergeValues(OutOps, 2, dl);
3031 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3032 MVT VT = Op.getValueType();
3033 DebugLoc dl = Op.getDebugLoc();
3034 unsigned BitWidth = VT.getSizeInBits();
3035 assert(Op.getNumOperands() == 3 &&
3036 VT == Op.getOperand(1).getValueType() &&
3039 // Expand into a bunch of logical ops. Note that these ops
3040 // depend on the PPC behavior for oversized shift amounts.
3041 SDValue Lo = Op.getOperand(0);
3042 SDValue Hi = Op.getOperand(1);
3043 SDValue Amt = Op.getOperand(2);
3044 MVT AmtVT = Amt.getValueType();
3046 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3047 DAG.getConstant(BitWidth, AmtVT), Amt);
3048 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3049 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3050 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3051 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3052 DAG.getConstant(-BitWidth, AmtVT));
3053 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3054 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3055 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3056 SDValue OutOps[] = { OutLo, OutHi };
3057 return DAG.getMergeValues(OutOps, 2, dl);
3060 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3061 DebugLoc dl = Op.getNode()->getDebugLoc();
3062 MVT VT = Op.getValueType();
3063 unsigned BitWidth = VT.getSizeInBits();
3064 assert(Op.getNumOperands() == 3 &&
3065 VT == Op.getOperand(1).getValueType() &&
3068 // Expand into a bunch of logical ops, followed by a select_cc.
3069 SDValue Lo = Op.getOperand(0);
3070 SDValue Hi = Op.getOperand(1);
3071 SDValue Amt = Op.getOperand(2);
3072 MVT AmtVT = Amt.getValueType();
3074 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3075 DAG.getConstant(BitWidth, AmtVT), Amt);
3076 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3077 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3078 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3079 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3080 DAG.getConstant(-BitWidth, AmtVT));
3081 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3082 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3083 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3084 Tmp4, Tmp6, ISD::SETLE);
3085 SDValue OutOps[] = { OutLo, OutHi };
3086 return DAG.getMergeValues(OutOps, 2, dl);
3089 //===----------------------------------------------------------------------===//
3090 // Vector related lowering.
3093 // If this is a vector of constants or undefs, get the bits. A bit in
3094 // UndefBits is set if the corresponding element of the vector is an
3095 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3096 // zero. Return true if this is not an array of constants, false if it is.
3098 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
3099 uint64_t UndefBits[2]) {
3100 // Start with zero'd results.
3101 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
3103 unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
3104 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3105 SDValue OpVal = BV->getOperand(i);
3107 unsigned PartNo = i >= e/2; // In the upper 128 bits?
3108 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
3110 uint64_t EltBits = 0;
3111 if (OpVal.getOpcode() == ISD::UNDEF) {
3112 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
3113 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
3115 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
3116 EltBits = CN->getZExtValue() & (~0U >> (32-EltBitSize));
3117 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
3118 assert(CN->getValueType(0) == MVT::f32 &&
3119 "Only one legal FP vector type!");
3120 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
3122 // Nonconstant element.
3126 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
3129 //printf("%llx %llx %llx %llx\n",
3130 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
3134 // If this is a splat (repetition) of a value across the whole vector, return
3135 // the smallest size that splats it. For example, "0x01010101010101..." is a
3136 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3137 // SplatSize = 1 byte.
3138 static bool isConstantSplat(const uint64_t Bits128[2],
3139 const uint64_t Undef128[2],
3140 unsigned &SplatBits, unsigned &SplatUndef,
3141 unsigned &SplatSize) {
3143 // Don't let undefs prevent splats from matching. See if the top 64-bits are
3144 // the same as the lower 64-bits, ignoring undefs.
3145 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
3146 return false; // Can't be a splat if two pieces don't match.
3148 uint64_t Bits64 = Bits128[0] | Bits128[1];
3149 uint64_t Undef64 = Undef128[0] & Undef128[1];
3151 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
3153 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
3154 return false; // Can't be a splat if two pieces don't match.
3156 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
3157 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
3159 // If the top 16-bits are different than the lower 16-bits, ignoring
3160 // undefs, we have an i32 splat.
3161 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
3163 SplatUndef = Undef32;
3168 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
3169 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
3171 // If the top 8-bits are different than the lower 8-bits, ignoring
3172 // undefs, we have an i16 splat.
3173 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
3175 SplatUndef = Undef16;
3180 // Otherwise, we have an 8-bit splat.
3181 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
3182 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
3187 /// BuildSplatI - Build a canonical splati of Val with an element size of
3188 /// SplatSize. Cast the result to VT.
3189 static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT,
3190 SelectionDAG &DAG, DebugLoc dl) {
3191 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3193 static const MVT VTys[] = { // canonical VT to use for each size.
3194 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3197 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3199 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3203 MVT CanonicalVT = VTys[SplatSize-1];
3205 // Build a canonical splat for this value.
3206 SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
3207 SmallVector<SDValue, 8> Ops;
3208 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3209 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3210 &Ops[0], Ops.size());
3211 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3214 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3215 /// specified intrinsic ID.
3216 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3217 SelectionDAG &DAG, DebugLoc dl,
3218 MVT DestVT = MVT::Other) {
3219 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3220 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3221 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3224 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3225 /// specified intrinsic ID.
3226 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3227 SDValue Op2, SelectionDAG &DAG,
3228 DebugLoc dl, MVT DestVT = MVT::Other) {
3229 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3230 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3231 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3235 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3236 /// amount. The result has the specified value type.
3237 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3238 MVT VT, SelectionDAG &DAG, DebugLoc dl) {
3239 // Force LHS/RHS to be the right type.
3240 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3241 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3244 for (unsigned i = 0; i != 16; ++i)
3245 Ops[i] = DAG.getConstant(i+Amt, MVT::i8);
3246 SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, LHS, RHS,
3247 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops,16));
3248 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3251 // If this is a case we can't handle, return null and let the default
3252 // expansion code take care of it. If we CAN select this case, and if it
3253 // selects to a single instruction, return Op. Otherwise, if we can codegen
3254 // this case more efficiently than a constant pool load, lower it to the
3255 // sequence of ops that should be used.
3256 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3257 SelectionDAG &DAG) {
3258 // If this is a vector of constants or undefs, get the bits. A bit in
3259 // UndefBits is set if the corresponding element of the vector is an
3260 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3262 uint64_t VectorBits[2];
3263 uint64_t UndefBits[2];
3264 DebugLoc dl = Op.getDebugLoc();
3265 if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits))
3266 return SDValue(); // Not a constant vector.
3268 // If this is a splat (repetition) of a value across the whole vector, return
3269 // the smallest size that splats it. For example, "0x01010101010101..." is a
3270 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3271 // SplatSize = 1 byte.
3272 unsigned SplatBits, SplatUndef, SplatSize;
3273 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
3274 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
3276 // First, handle single instruction cases.
3279 if (SplatBits == 0) {
3280 // Canonicalize all zero vectors to be v4i32.
3281 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3282 SDValue Z = DAG.getConstant(0, MVT::i32);
3283 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3284 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3289 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3290 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
3291 if (SextVal >= -16 && SextVal <= 15)
3292 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3295 // Two instruction sequences.
3297 // If this value is in the range [-32,30] and is even, use:
3298 // tmp = VSPLTI[bhw], result = add tmp, tmp
3299 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3300 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3301 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3302 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3305 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3306 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3308 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3309 // Make -1 and vspltisw -1:
3310 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3312 // Make the VSLW intrinsic, computing 0x8000_0000.
3313 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3316 // xor by OnesV to invert it.
3317 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3318 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3321 // Check to see if this is a wide variety of vsplti*, binop self cases.
3322 unsigned SplatBitSize = SplatSize*8;
3323 static const signed char SplatCsts[] = {
3324 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3325 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3328 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3329 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3330 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3331 int i = SplatCsts[idx];
3333 // Figure out what shift amount will be used by altivec if shifted by i in
3335 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3337 // vsplti + shl self.
3338 if (SextVal == (i << (int)TypeShiftAmt)) {
3339 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3340 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3341 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3342 Intrinsic::ppc_altivec_vslw
3344 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3345 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3348 // vsplti + srl self.
3349 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3350 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3351 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3352 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3353 Intrinsic::ppc_altivec_vsrw
3355 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3356 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3359 // vsplti + sra self.
3360 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3361 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3362 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3363 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3364 Intrinsic::ppc_altivec_vsraw
3366 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3367 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3370 // vsplti + rol self.
3371 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3372 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3373 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3374 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3375 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3376 Intrinsic::ppc_altivec_vrlw
3378 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3379 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3382 // t = vsplti c, result = vsldoi t, t, 1
3383 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3384 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3385 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3387 // t = vsplti c, result = vsldoi t, t, 2
3388 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3389 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3390 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3392 // t = vsplti c, result = vsldoi t, t, 3
3393 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3394 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3395 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3399 // Three instruction sequences.
3401 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3402 if (SextVal >= 0 && SextVal <= 31) {
3403 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3404 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3405 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3406 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3408 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3409 if (SextVal >= -31 && SextVal <= 0) {
3410 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3411 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3412 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3413 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3420 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3421 /// the specified operations to build the shuffle.
3422 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3423 SDValue RHS, SelectionDAG &DAG,
3425 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3426 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3427 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3430 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3442 if (OpNum == OP_COPY) {
3443 if (LHSID == (1*9+2)*9+3) return LHS;
3444 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3448 SDValue OpLHS, OpRHS;
3449 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3450 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3452 unsigned ShufIdxs[16];
3454 default: assert(0 && "Unknown i32 permute!");
3456 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3457 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3458 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3459 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3462 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3463 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3464 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3465 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3468 for (unsigned i = 0; i != 16; ++i)
3469 ShufIdxs[i] = (i&3)+0;
3472 for (unsigned i = 0; i != 16; ++i)
3473 ShufIdxs[i] = (i&3)+4;
3476 for (unsigned i = 0; i != 16; ++i)
3477 ShufIdxs[i] = (i&3)+8;
3480 for (unsigned i = 0; i != 16; ++i)
3481 ShufIdxs[i] = (i&3)+12;
3484 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
3486 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
3488 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
3491 for (unsigned i = 0; i != 16; ++i)
3492 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
3494 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, OpLHS.getValueType(),
3496 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
3499 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3500 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3501 /// return the code it can be lowered into. Worst case, it can always be
3502 /// lowered into a vperm.
3503 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
3504 SelectionDAG &DAG) {
3505 DebugLoc dl = Op.getDebugLoc();
3506 SDValue V1 = Op.getOperand(0);
3507 SDValue V2 = Op.getOperand(1);
3508 SDValue PermMask = Op.getOperand(2);
3510 // Cases that are handled by instructions that take permute immediates
3511 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3512 // selected by the instruction selector.
3513 if (V2.getOpcode() == ISD::UNDEF) {
3514 if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) ||
3515 PPC::isSplatShuffleMask(PermMask.getNode(), 2) ||
3516 PPC::isSplatShuffleMask(PermMask.getNode(), 4) ||
3517 PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) ||
3518 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) ||
3519 PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 ||
3520 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) ||
3521 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) ||
3522 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) ||
3523 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) ||
3524 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) ||
3525 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) {
3530 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3531 // and produce a fixed permutation. If any of these match, do not lower to
3533 if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) ||
3534 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) ||
3535 PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 ||
3536 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) ||
3537 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) ||
3538 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) ||
3539 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) ||
3540 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) ||
3541 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false))
3544 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3545 // perfect shuffle table to emit an optimal matching sequence.
3546 unsigned PFIndexes[4];
3547 bool isFourElementShuffle = true;
3548 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3549 unsigned EltNo = 8; // Start out undef.
3550 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3551 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
3552 continue; // Undef, ignore it.
3554 unsigned ByteSource =
3555 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getZExtValue();
3556 if ((ByteSource & 3) != j) {
3557 isFourElementShuffle = false;
3562 EltNo = ByteSource/4;
3563 } else if (EltNo != ByteSource/4) {
3564 isFourElementShuffle = false;
3568 PFIndexes[i] = EltNo;
3571 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3572 // perfect shuffle vector to determine if it is cost effective to do this as
3573 // discrete instructions, or whether we should use a vperm.
3574 if (isFourElementShuffle) {
3575 // Compute the index in the perfect shuffle table.
3576 unsigned PFTableIndex =
3577 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3579 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3580 unsigned Cost = (PFEntry >> 30);
3582 // Determining when to avoid vperm is tricky. Many things affect the cost
3583 // of vperm, particularly how many times the perm mask needs to be computed.
3584 // For example, if the perm mask can be hoisted out of a loop or is already
3585 // used (perhaps because there are multiple permutes with the same shuffle
3586 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3587 // the loop requires an extra register.
3589 // As a compromise, we only emit discrete instructions if the shuffle can be
3590 // generated in 3 or fewer operations. When we have loop information
3591 // available, if this block is within a loop, we should avoid using vperm
3592 // for 3-operation perms and use a constant pool load instead.
3594 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3597 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3598 // vector that will get spilled to the constant pool.
3599 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3601 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3602 // that it is in input element units, not in bytes. Convert now.
3603 MVT EltVT = V1.getValueType().getVectorElementType();
3604 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
3606 SmallVector<SDValue, 16> ResultMask;
3607 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
3609 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
3612 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
3614 for (unsigned j = 0; j != BytesPerElement; ++j)
3615 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3619 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
3620 &ResultMask[0], ResultMask.size());
3621 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
3624 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3625 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3626 /// information about the intrinsic.
3627 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
3629 unsigned IntrinsicID =
3630 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
3633 switch (IntrinsicID) {
3634 default: return false;
3635 // Comparison predicates.
3636 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3637 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3638 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3639 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3640 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3641 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3642 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3643 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3644 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3645 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3646 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3647 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3648 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3650 // Normal Comparisons.
3651 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3652 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3653 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3654 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3655 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3656 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3657 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3658 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3659 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3660 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
3661 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
3662 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
3663 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3668 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3669 /// lower, do it, otherwise return null.
3670 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3671 SelectionDAG &DAG) {
3672 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3673 // opcode number of the comparison.
3674 DebugLoc dl = Op.getDebugLoc();
3677 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3678 return SDValue(); // Don't custom lower most intrinsics.
3680 // If this is a non-dot comparison, make the VCMP node and we are done.
3682 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
3683 Op.getOperand(1), Op.getOperand(2),
3684 DAG.getConstant(CompareOpc, MVT::i32));
3685 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
3688 // Create the PPCISD altivec 'dot' comparison node.
3690 Op.getOperand(2), // LHS
3691 Op.getOperand(3), // RHS
3692 DAG.getConstant(CompareOpc, MVT::i32)
3694 std::vector<MVT> VTs;
3695 VTs.push_back(Op.getOperand(2).getValueType());
3696 VTs.push_back(MVT::Flag);
3697 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
3699 // Now that we have the comparison, emit a copy from the CR to a GPR.
3700 // This is flagged to the above dot comparison.
3701 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
3702 DAG.getRegister(PPC::CR6, MVT::i32),
3703 CompNode.getValue(1));
3705 // Unpack the result based on how the target uses it.
3706 unsigned BitNo; // Bit # of CR6.
3707 bool InvertBit; // Invert result?
3708 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
3709 default: // Can't happen, don't crash on invalid number though.
3710 case 0: // Return the value of the EQ bit of CR6.
3711 BitNo = 0; InvertBit = false;
3713 case 1: // Return the inverted value of the EQ bit of CR6.
3714 BitNo = 0; InvertBit = true;
3716 case 2: // Return the value of the LT bit of CR6.
3717 BitNo = 2; InvertBit = false;
3719 case 3: // Return the inverted value of the LT bit of CR6.
3720 BitNo = 2; InvertBit = true;
3724 // Shift the bit into the low position.
3725 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
3726 DAG.getConstant(8-(3-BitNo), MVT::i32));
3728 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
3729 DAG.getConstant(1, MVT::i32));
3731 // If we are supposed to, toggle the bit.
3733 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
3734 DAG.getConstant(1, MVT::i32));
3738 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
3739 SelectionDAG &DAG) {
3740 DebugLoc dl = Op.getNode()->getDebugLoc();
3741 // Create a stack slot that is 16-byte aligned.
3742 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3743 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3744 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3745 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3747 // Store the input value into Value#0 of the stack slot.
3748 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
3749 Op.getOperand(0), FIdx, NULL, 0);
3751 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0);
3754 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
3755 DebugLoc dl = Op.getDebugLoc();
3756 if (Op.getValueType() == MVT::v4i32) {
3757 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3759 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
3760 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
3762 SDValue RHSSwap = // = vrlw RHS, 16
3763 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
3765 // Shrinkify inputs to v8i16.
3766 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
3767 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
3768 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
3770 // Low parts multiplied together, generating 32-bit results (we ignore the
3772 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3773 LHS, RHS, DAG, dl, MVT::v4i32);
3775 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3776 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
3777 // Shift the high parts up 16 bits.
3778 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
3780 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
3781 } else if (Op.getValueType() == MVT::v8i16) {
3782 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3784 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
3786 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3787 LHS, RHS, Zero, DAG, dl);
3788 } else if (Op.getValueType() == MVT::v16i8) {
3789 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3791 // Multiply the even 8-bit parts, producing 16-bit sums.
3792 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3793 LHS, RHS, DAG, dl, MVT::v8i16);
3794 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
3796 // Multiply the odd 8-bit parts, producing 16-bit sums.
3797 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3798 LHS, RHS, DAG, dl, MVT::v8i16);
3799 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
3801 // Merge the results together.
3803 for (unsigned i = 0; i != 8; ++i) {
3804 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3805 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3807 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, EvenParts, OddParts,
3808 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
3810 assert(0 && "Unknown mul to lower!");
3815 /// LowerOperation - Provide custom lowering hooks for some operations.
3817 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
3818 switch (Op.getOpcode()) {
3819 default: assert(0 && "Wasn't expecting to be able to lower this!");
3820 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3821 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3822 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3823 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3824 case ISD::SETCC: return LowerSETCC(Op, DAG);
3825 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
3827 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3828 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3831 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3832 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3834 case ISD::FORMAL_ARGUMENTS:
3835 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3836 VarArgsStackOffset, VarArgsNumGPR,
3837 VarArgsNumFPR, PPCSubTarget);
3839 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget,
3840 getTargetMachine());
3841 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3842 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3843 case ISD::DYNAMIC_STACKALLOC:
3844 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3846 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3847 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG,
3849 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3850 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3852 // Lower 64-bit shifts.
3853 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3854 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3855 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3857 // Vector-related lowering.
3858 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3859 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3860 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3861 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3862 case ISD::MUL: return LowerMUL(Op, DAG);
3864 // Frame & Return address.
3865 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3866 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3871 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
3872 SmallVectorImpl<SDValue>&Results,
3873 SelectionDAG &DAG) {
3874 DebugLoc dl = N->getDebugLoc();
3875 switch (N->getOpcode()) {
3877 assert(false && "Do not know how to custom type legalize this operation!");
3879 case ISD::FP_ROUND_INREG: {
3880 assert(N->getValueType(0) == MVT::ppcf128);
3881 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
3882 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
3883 MVT::f64, N->getOperand(0),
3884 DAG.getIntPtrConstant(0));
3885 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
3886 MVT::f64, N->getOperand(0),
3887 DAG.getIntPtrConstant(1));
3889 // This sequence changes FPSCR to do round-to-zero, adds the two halves
3890 // of the long double, and puts FPSCR back the way it was. We do not
3891 // actually model FPSCR.
3892 std::vector<MVT> NodeTys;
3893 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
3895 NodeTys.push_back(MVT::f64); // Return register
3896 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
3897 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3898 MFFSreg = Result.getValue(0);
3899 InFlag = Result.getValue(1);
3902 NodeTys.push_back(MVT::Flag); // Returns a flag
3903 Ops[0] = DAG.getConstant(31, MVT::i32);
3905 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
3906 InFlag = Result.getValue(0);
3909 NodeTys.push_back(MVT::Flag); // Returns a flag
3910 Ops[0] = DAG.getConstant(30, MVT::i32);
3912 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
3913 InFlag = Result.getValue(0);
3916 NodeTys.push_back(MVT::f64); // result of add
3917 NodeTys.push_back(MVT::Flag); // Returns a flag
3921 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
3922 FPreg = Result.getValue(0);
3923 InFlag = Result.getValue(1);
3926 NodeTys.push_back(MVT::f64);
3927 Ops[0] = DAG.getConstant(1, MVT::i32);
3931 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
3932 FPreg = Result.getValue(0);
3934 // We know the low half is about to be thrown away, so just use something
3936 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
3940 case ISD::FP_TO_SINT:
3941 Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG, dl));
3947 //===----------------------------------------------------------------------===//
3948 // Other Lowering Code
3949 //===----------------------------------------------------------------------===//
3952 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3953 bool is64bit, unsigned BinOpcode) {
3954 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3955 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3957 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3958 MachineFunction *F = BB->getParent();
3959 MachineFunction::iterator It = BB;
3962 unsigned dest = MI->getOperand(0).getReg();
3963 unsigned ptrA = MI->getOperand(1).getReg();
3964 unsigned ptrB = MI->getOperand(2).getReg();
3965 unsigned incr = MI->getOperand(3).getReg();
3967 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
3968 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
3969 F->insert(It, loopMBB);
3970 F->insert(It, exitMBB);
3971 exitMBB->transferSuccessors(BB);
3973 MachineRegisterInfo &RegInfo = F->getRegInfo();
3974 unsigned TmpReg = (!BinOpcode) ? incr :
3975 RegInfo.createVirtualRegister(
3976 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
3977 (const TargetRegisterClass *) &PPC::GPRCRegClass);
3981 // fallthrough --> loopMBB
3982 BB->addSuccessor(loopMBB);
3985 // l[wd]arx dest, ptr
3986 // add r0, dest, incr
3987 // st[wd]cx. r0, ptr
3989 // fallthrough --> exitMBB
3991 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
3992 .addReg(ptrA).addReg(ptrB);
3994 BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
3995 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
3996 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
3997 BuildMI(BB, TII->get(PPC::BCC))
3998 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
3999 BB->addSuccessor(loopMBB);
4000 BB->addSuccessor(exitMBB);
4009 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4010 MachineBasicBlock *BB,
4011 bool is8bit, // operation
4012 unsigned BinOpcode) {
4013 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4014 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4015 // In 64 bit mode we have to use 64 bits for addresses, even though the
4016 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4017 // registers without caring whether they're 32 or 64, but here we're
4018 // doing actual arithmetic on the addresses.
4019 bool is64bit = PPCSubTarget.isPPC64();
4021 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4022 MachineFunction *F = BB->getParent();
4023 MachineFunction::iterator It = BB;
4026 unsigned dest = MI->getOperand(0).getReg();
4027 unsigned ptrA = MI->getOperand(1).getReg();
4028 unsigned ptrB = MI->getOperand(2).getReg();
4029 unsigned incr = MI->getOperand(3).getReg();
4031 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4032 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4033 F->insert(It, loopMBB);
4034 F->insert(It, exitMBB);
4035 exitMBB->transferSuccessors(BB);
4037 MachineRegisterInfo &RegInfo = F->getRegInfo();
4038 const TargetRegisterClass *RC =
4039 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4040 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4041 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4042 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4043 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4044 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4045 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4046 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4047 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4048 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4049 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4050 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4051 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4053 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4057 // fallthrough --> loopMBB
4058 BB->addSuccessor(loopMBB);
4060 // The 4-byte load must be aligned, while a char or short may be
4061 // anywhere in the word. Hence all this nasty bookkeeping code.
4062 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4063 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4064 // xori shift, shift1, 24 [16]
4065 // rlwinm ptr, ptr1, 0, 0, 29
4066 // slw incr2, incr, shift
4067 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4068 // slw mask, mask2, shift
4070 // lwarx tmpDest, ptr
4071 // add tmp, tmpDest, incr2
4072 // andc tmp2, tmpDest, mask
4073 // and tmp3, tmp, mask
4074 // or tmp4, tmp3, tmp2
4077 // fallthrough --> exitMBB
4078 // srw dest, tmpDest, shift
4080 if (ptrA!=PPC::R0) {
4081 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4082 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4083 .addReg(ptrA).addReg(ptrB);
4087 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4088 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4089 BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4090 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4092 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
4093 .addReg(Ptr1Reg).addImm(0).addImm(61);
4095 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
4096 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4097 BuildMI(BB, TII->get(PPC::SLW), Incr2Reg)
4098 .addReg(incr).addReg(ShiftReg);
4100 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
4102 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
4103 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
4105 BuildMI(BB, TII->get(PPC::SLW), MaskReg)
4106 .addReg(Mask2Reg).addReg(ShiftReg);
4109 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
4110 .addReg(PPC::R0).addReg(PtrReg);
4112 BuildMI(BB, TII->get(BinOpcode), TmpReg)
4113 .addReg(Incr2Reg).addReg(TmpDestReg);
4114 BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4115 .addReg(TmpDestReg).addReg(MaskReg);
4116 BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4117 .addReg(TmpReg).addReg(MaskReg);
4118 BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4119 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4120 BuildMI(BB, TII->get(PPC::STWCX))
4121 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4122 BuildMI(BB, TII->get(PPC::BCC))
4123 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4124 BB->addSuccessor(loopMBB);
4125 BB->addSuccessor(exitMBB);
4130 BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4135 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4136 MachineBasicBlock *BB) {
4137 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4139 // To "insert" these instructions we actually have to insert their
4140 // control-flow patterns.
4141 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4142 MachineFunction::iterator It = BB;
4145 MachineFunction *F = BB->getParent();
4147 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4148 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4149 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4150 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4151 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4153 // The incoming instruction knows the destination vreg to set, the
4154 // condition code register to branch on, the true/false values to
4155 // select between, and a branch opcode to use.
4160 // cmpTY ccX, r1, r2
4162 // fallthrough --> copy0MBB
4163 MachineBasicBlock *thisMBB = BB;
4164 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4165 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4166 unsigned SelectPred = MI->getOperand(4).getImm();
4167 BuildMI(BB, TII->get(PPC::BCC))
4168 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4169 F->insert(It, copy0MBB);
4170 F->insert(It, sinkMBB);
4171 // Update machine-CFG edges by transferring all successors of the current
4172 // block to the new block which will contain the Phi node for the select.
4173 sinkMBB->transferSuccessors(BB);
4174 // Next, add the true and fallthrough blocks as its successors.
4175 BB->addSuccessor(copy0MBB);
4176 BB->addSuccessor(sinkMBB);
4179 // %FalseValue = ...
4180 // # fallthrough to sinkMBB
4183 // Update machine-CFG edges
4184 BB->addSuccessor(sinkMBB);
4187 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4190 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4191 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4192 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4194 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4195 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4196 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4197 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4198 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4199 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4200 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4201 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4203 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4204 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4205 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4206 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4207 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4208 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4209 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4210 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4212 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4213 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4214 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4215 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4216 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4217 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4218 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4219 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4221 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4222 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4223 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4224 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4225 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4226 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4227 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4228 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4230 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4231 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4232 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4233 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4234 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4235 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4236 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4237 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4239 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4240 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4241 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4242 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4243 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4244 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4245 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4246 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4248 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4249 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4250 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4251 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4252 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4253 BB = EmitAtomicBinary(MI, BB, false, 0);
4254 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4255 BB = EmitAtomicBinary(MI, BB, true, 0);
4257 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4258 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4259 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4261 unsigned dest = MI->getOperand(0).getReg();
4262 unsigned ptrA = MI->getOperand(1).getReg();
4263 unsigned ptrB = MI->getOperand(2).getReg();
4264 unsigned oldval = MI->getOperand(3).getReg();
4265 unsigned newval = MI->getOperand(4).getReg();
4267 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4268 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4269 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4270 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4271 F->insert(It, loop1MBB);
4272 F->insert(It, loop2MBB);
4273 F->insert(It, midMBB);
4274 F->insert(It, exitMBB);
4275 exitMBB->transferSuccessors(BB);
4279 // fallthrough --> loopMBB
4280 BB->addSuccessor(loop1MBB);
4283 // l[wd]arx dest, ptr
4284 // cmp[wd] dest, oldval
4287 // st[wd]cx. newval, ptr
4291 // st[wd]cx. dest, ptr
4294 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4295 .addReg(ptrA).addReg(ptrB);
4296 BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4297 .addReg(oldval).addReg(dest);
4298 BuildMI(BB, TII->get(PPC::BCC))
4299 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4300 BB->addSuccessor(loop2MBB);
4301 BB->addSuccessor(midMBB);
4304 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4305 .addReg(newval).addReg(ptrA).addReg(ptrB);
4306 BuildMI(BB, TII->get(PPC::BCC))
4307 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4308 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
4309 BB->addSuccessor(loop1MBB);
4310 BB->addSuccessor(exitMBB);
4313 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4314 .addReg(dest).addReg(ptrA).addReg(ptrB);
4315 BB->addSuccessor(exitMBB);
4320 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4321 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4322 // We must use 64-bit registers for addresses when targeting 64-bit,
4323 // since we're actually doing arithmetic on them. Other registers
4325 bool is64bit = PPCSubTarget.isPPC64();
4326 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4328 unsigned dest = MI->getOperand(0).getReg();
4329 unsigned ptrA = MI->getOperand(1).getReg();
4330 unsigned ptrB = MI->getOperand(2).getReg();
4331 unsigned oldval = MI->getOperand(3).getReg();
4332 unsigned newval = MI->getOperand(4).getReg();
4334 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4335 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4336 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4337 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4338 F->insert(It, loop1MBB);
4339 F->insert(It, loop2MBB);
4340 F->insert(It, midMBB);
4341 F->insert(It, exitMBB);
4342 exitMBB->transferSuccessors(BB);
4344 MachineRegisterInfo &RegInfo = F->getRegInfo();
4345 const TargetRegisterClass *RC =
4346 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4347 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4348 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4349 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4350 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4351 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4352 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4353 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4354 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4355 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4356 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4357 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4358 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4359 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4360 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4362 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4365 // fallthrough --> loopMBB
4366 BB->addSuccessor(loop1MBB);
4368 // The 4-byte load must be aligned, while a char or short may be
4369 // anywhere in the word. Hence all this nasty bookkeeping code.
4370 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4371 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4372 // xori shift, shift1, 24 [16]
4373 // rlwinm ptr, ptr1, 0, 0, 29
4374 // slw newval2, newval, shift
4375 // slw oldval2, oldval,shift
4376 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4377 // slw mask, mask2, shift
4378 // and newval3, newval2, mask
4379 // and oldval3, oldval2, mask
4381 // lwarx tmpDest, ptr
4382 // and tmp, tmpDest, mask
4383 // cmpw tmp, oldval3
4386 // andc tmp2, tmpDest, mask
4387 // or tmp4, tmp2, newval3
4392 // stwcx. tmpDest, ptr
4394 // srw dest, tmpDest, shift
4395 if (ptrA!=PPC::R0) {
4396 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4397 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4398 .addReg(ptrA).addReg(ptrB);
4402 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4403 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4404 BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4405 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4407 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
4408 .addReg(Ptr1Reg).addImm(0).addImm(61);
4410 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
4411 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4412 BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg)
4413 .addReg(newval).addReg(ShiftReg);
4414 BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg)
4415 .addReg(oldval).addReg(ShiftReg);
4417 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
4419 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
4420 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
4422 BuildMI(BB, TII->get(PPC::SLW), MaskReg)
4423 .addReg(Mask2Reg).addReg(ShiftReg);
4424 BuildMI(BB, TII->get(PPC::AND), NewVal3Reg)
4425 .addReg(NewVal2Reg).addReg(MaskReg);
4426 BuildMI(BB, TII->get(PPC::AND), OldVal3Reg)
4427 .addReg(OldVal2Reg).addReg(MaskReg);
4430 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
4431 .addReg(PPC::R0).addReg(PtrReg);
4432 BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg);
4433 BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0)
4434 .addReg(TmpReg).addReg(OldVal3Reg);
4435 BuildMI(BB, TII->get(PPC::BCC))
4436 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4437 BB->addSuccessor(loop2MBB);
4438 BB->addSuccessor(midMBB);
4441 BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg);
4442 BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg);
4443 BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4444 .addReg(PPC::R0).addReg(PtrReg);
4445 BuildMI(BB, TII->get(PPC::BCC))
4446 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4447 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
4448 BB->addSuccessor(loop1MBB);
4449 BB->addSuccessor(exitMBB);
4452 BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4453 .addReg(PPC::R0).addReg(PtrReg);
4454 BB->addSuccessor(exitMBB);
4459 BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4461 assert(0 && "Unexpected instr type to insert");
4464 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4468 //===----------------------------------------------------------------------===//
4469 // Target Optimization Hooks
4470 //===----------------------------------------------------------------------===//
4472 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4473 DAGCombinerInfo &DCI) const {
4474 TargetMachine &TM = getTargetMachine();
4475 SelectionDAG &DAG = DCI.DAG;
4476 DebugLoc dl = N->getDebugLoc();
4477 switch (N->getOpcode()) {
4480 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4481 if (C->getZExtValue() == 0) // 0 << V -> 0.
4482 return N->getOperand(0);
4486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4487 if (C->getZExtValue() == 0) // 0 >>u V -> 0.
4488 return N->getOperand(0);
4492 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4493 if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
4494 C->isAllOnesValue()) // -1 >>s V -> -1.
4495 return N->getOperand(0);
4499 case ISD::SINT_TO_FP:
4500 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4501 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4502 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4503 // We allow the src/dst to be either f32/f64, but the intermediate
4504 // type must be i64.
4505 if (N->getOperand(0).getValueType() == MVT::i64 &&
4506 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4507 SDValue Val = N->getOperand(0).getOperand(0);
4508 if (Val.getValueType() == MVT::f32) {
4509 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4510 DCI.AddToWorklist(Val.getNode());
4513 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
4514 DCI.AddToWorklist(Val.getNode());
4515 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
4516 DCI.AddToWorklist(Val.getNode());
4517 if (N->getValueType(0) == MVT::f32) {
4518 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
4519 DAG.getIntPtrConstant(0));
4520 DCI.AddToWorklist(Val.getNode());
4523 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4524 // If the intermediate type is i32, we can avoid the load/store here
4531 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4532 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4533 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4534 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4535 N->getOperand(1).getValueType() == MVT::i32 &&
4536 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4537 SDValue Val = N->getOperand(1).getOperand(0);
4538 if (Val.getValueType() == MVT::f32) {
4539 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4540 DCI.AddToWorklist(Val.getNode());
4542 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
4543 DCI.AddToWorklist(Val.getNode());
4545 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
4546 N->getOperand(2), N->getOperand(3));
4547 DCI.AddToWorklist(Val.getNode());
4551 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4552 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
4553 N->getOperand(1).getNode()->hasOneUse() &&
4554 (N->getOperand(1).getValueType() == MVT::i32 ||
4555 N->getOperand(1).getValueType() == MVT::i16)) {
4556 SDValue BSwapOp = N->getOperand(1).getOperand(0);
4557 // Do an any-extend to 32-bits if this is a half-word input.
4558 if (BSwapOp.getValueType() == MVT::i16)
4559 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
4561 return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0),
4562 BSwapOp, N->getOperand(2), N->getOperand(3),
4563 DAG.getValueType(N->getOperand(1).getValueType()));
4567 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4568 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
4569 N->getOperand(0).hasOneUse() &&
4570 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4571 SDValue Load = N->getOperand(0);
4572 LoadSDNode *LD = cast<LoadSDNode>(Load);
4573 // Create the byte-swapping load.
4574 std::vector<MVT> VTs;
4575 VTs.push_back(MVT::i32);
4576 VTs.push_back(MVT::Other);
4577 SDValue MO = DAG.getMemOperand(LD->getMemOperand());
4579 LD->getChain(), // Chain
4580 LD->getBasePtr(), // Ptr
4582 DAG.getValueType(N->getValueType(0)) // VT
4584 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4);
4586 // If this is an i16 load, insert the truncate.
4587 SDValue ResVal = BSLoad;
4588 if (N->getValueType(0) == MVT::i16)
4589 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
4591 // First, combine the bswap away. This makes the value produced by the
4593 DCI.CombineTo(N, ResVal);
4595 // Next, combine the load away, we give it a bogus result value but a real
4596 // chain result. The result value is dead because the bswap is dead.
4597 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
4599 // Return N so it doesn't get rechecked!
4600 return SDValue(N, 0);
4604 case PPCISD::VCMP: {
4605 // If a VCMPo node already exists with exactly the same operands as this
4606 // node, use its result instead of this node (VCMPo computes both a CR6 and
4607 // a normal output).
4609 if (!N->getOperand(0).hasOneUse() &&
4610 !N->getOperand(1).hasOneUse() &&
4611 !N->getOperand(2).hasOneUse()) {
4613 // Scan all of the users of the LHS, looking for VCMPo's that match.
4614 SDNode *VCMPoNode = 0;
4616 SDNode *LHSN = N->getOperand(0).getNode();
4617 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
4619 if (UI->getOpcode() == PPCISD::VCMPo &&
4620 UI->getOperand(1) == N->getOperand(1) &&
4621 UI->getOperand(2) == N->getOperand(2) &&
4622 UI->getOperand(0) == N->getOperand(0)) {
4627 // If there is no VCMPo node, or if the flag value has a single use, don't
4629 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
4632 // Look at the (necessarily single) use of the flag value. If it has a
4633 // chain, this transformation is more complex. Note that multiple things
4634 // could use the value result, which we should ignore.
4635 SDNode *FlagUser = 0;
4636 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
4637 FlagUser == 0; ++UI) {
4638 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
4640 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
4641 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
4648 // If the user is a MFCR instruction, we know this is safe. Otherwise we
4649 // give up for right now.
4650 if (FlagUser->getOpcode() == PPCISD::MFCR)
4651 return SDValue(VCMPoNode, 0);
4656 // If this is a branch on an altivec predicate comparison, lower this so
4657 // that we don't have to do a MFCR: instead, branch directly on CR6. This
4658 // lowering is done pre-legalize, because the legalizer lowers the predicate
4659 // compare down to code that is difficult to reassemble.
4660 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
4661 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
4665 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
4666 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
4667 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
4668 assert(isDot && "Can't compare against a vector result!");
4670 // If this is a comparison against something other than 0/1, then we know
4671 // that the condition is never/always true.
4672 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
4673 if (Val != 0 && Val != 1) {
4674 if (CC == ISD::SETEQ) // Cond never true, remove branch.
4675 return N->getOperand(0);
4676 // Always !=, turn it into an unconditional branch.
4677 return DAG.getNode(ISD::BR, dl, MVT::Other,
4678 N->getOperand(0), N->getOperand(4));
4681 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
4683 // Create the PPCISD altivec 'dot' comparison node.
4684 std::vector<MVT> VTs;
4686 LHS.getOperand(2), // LHS of compare
4687 LHS.getOperand(3), // RHS of compare
4688 DAG.getConstant(CompareOpc, MVT::i32)
4690 VTs.push_back(LHS.getOperand(2).getValueType());
4691 VTs.push_back(MVT::Flag);
4692 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4694 // Unpack the result based on how the target uses it.
4695 PPC::Predicate CompOpc;
4696 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
4697 default: // Can't happen, don't crash on invalid number though.
4698 case 0: // Branch on the value of the EQ bit of CR6.
4699 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
4701 case 1: // Branch on the inverted value of the EQ bit of CR6.
4702 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
4704 case 2: // Branch on the value of the LT bit of CR6.
4705 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
4707 case 3: // Branch on the inverted value of the LT bit of CR6.
4708 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
4712 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
4713 DAG.getConstant(CompOpc, MVT::i32),
4714 DAG.getRegister(PPC::CR6, MVT::i32),
4715 N->getOperand(4), CompNode.getValue(1));
4724 //===----------------------------------------------------------------------===//
4725 // Inline Assembly Support
4726 //===----------------------------------------------------------------------===//
4728 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4732 const SelectionDAG &DAG,
4733 unsigned Depth) const {
4734 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4735 switch (Op.getOpcode()) {
4737 case PPCISD::LBRX: {
4738 // lhbrx is known to have the top bits cleared out.
4739 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
4740 KnownZero = 0xFFFF0000;
4743 case ISD::INTRINSIC_WO_CHAIN: {
4744 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
4746 case Intrinsic::ppc_altivec_vcmpbfp_p:
4747 case Intrinsic::ppc_altivec_vcmpeqfp_p:
4748 case Intrinsic::ppc_altivec_vcmpequb_p:
4749 case Intrinsic::ppc_altivec_vcmpequh_p:
4750 case Intrinsic::ppc_altivec_vcmpequw_p:
4751 case Intrinsic::ppc_altivec_vcmpgefp_p:
4752 case Intrinsic::ppc_altivec_vcmpgtfp_p:
4753 case Intrinsic::ppc_altivec_vcmpgtsb_p:
4754 case Intrinsic::ppc_altivec_vcmpgtsh_p:
4755 case Intrinsic::ppc_altivec_vcmpgtsw_p:
4756 case Intrinsic::ppc_altivec_vcmpgtub_p:
4757 case Intrinsic::ppc_altivec_vcmpgtuh_p:
4758 case Intrinsic::ppc_altivec_vcmpgtuw_p:
4759 KnownZero = ~1U; // All bits but the low one are known to be zero.
4767 /// getConstraintType - Given a constraint, return the type of
4768 /// constraint it is for this target.
4769 PPCTargetLowering::ConstraintType
4770 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
4771 if (Constraint.size() == 1) {
4772 switch (Constraint[0]) {
4779 return C_RegisterClass;
4782 return TargetLowering::getConstraintType(Constraint);
4785 std::pair<unsigned, const TargetRegisterClass*>
4786 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4788 if (Constraint.size() == 1) {
4789 // GCC RS6000 Constraint Letters
4790 switch (Constraint[0]) {
4793 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
4794 return std::make_pair(0U, PPC::G8RCRegisterClass);
4795 return std::make_pair(0U, PPC::GPRCRegisterClass);
4798 return std::make_pair(0U, PPC::F4RCRegisterClass);
4799 else if (VT == MVT::f64)
4800 return std::make_pair(0U, PPC::F8RCRegisterClass);
4803 return std::make_pair(0U, PPC::VRRCRegisterClass);
4805 return std::make_pair(0U, PPC::CRRCRegisterClass);
4809 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4813 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4814 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
4815 /// it means one of the asm constraint of the inline asm instruction being
4816 /// processed is 'm'.
4817 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
4819 std::vector<SDValue>&Ops,
4820 SelectionDAG &DAG) const {
4821 SDValue Result(0,0);
4832 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
4833 if (!CST) return; // Must be an immediate to match.
4834 unsigned Value = CST->getZExtValue();
4836 default: assert(0 && "Unknown constraint letter!");
4837 case 'I': // "I" is a signed 16-bit constant.
4838 if ((short)Value == (int)Value)
4839 Result = DAG.getTargetConstant(Value, Op.getValueType());
4841 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
4842 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
4843 if ((short)Value == 0)
4844 Result = DAG.getTargetConstant(Value, Op.getValueType());
4846 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
4847 if ((Value >> 16) == 0)
4848 Result = DAG.getTargetConstant(Value, Op.getValueType());
4850 case 'M': // "M" is a constant that is greater than 31.
4852 Result = DAG.getTargetConstant(Value, Op.getValueType());
4854 case 'N': // "N" is a positive constant that is an exact power of two.
4855 if ((int)Value > 0 && isPowerOf2_32(Value))
4856 Result = DAG.getTargetConstant(Value, Op.getValueType());
4858 case 'O': // "O" is the constant zero.
4860 Result = DAG.getTargetConstant(Value, Op.getValueType());
4862 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
4863 if ((short)-Value == (int)-Value)
4864 Result = DAG.getTargetConstant(Value, Op.getValueType());
4871 if (Result.getNode()) {
4872 Ops.push_back(Result);
4876 // Handle standard constraint letters.
4877 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
4880 // isLegalAddressingMode - Return true if the addressing mode represented
4881 // by AM is legal for this target, for a load/store of the specified type.
4882 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4883 const Type *Ty) const {
4884 // FIXME: PPC does not allow r+i addressing modes for vectors!
4886 // PPC allows a sign-extended 16-bit immediate field.
4887 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
4890 // No global is ever allowed as a base.
4894 // PPC only support r+r,
4896 case 0: // "r+i" or just "i", depending on HasBaseReg.
4899 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
4901 // Otherwise we have r+r or r+i.
4904 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
4906 // Allow 2*r as r+r.
4909 // No other scales are supported.
4916 /// isLegalAddressImmediate - Return true if the integer value can be used
4917 /// as the offset of the target addressing mode for load / store of the
4919 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
4920 // PPC allows a sign-extended 16-bit immediate field.
4921 return (V > -(1 << 16) && V < (1 << 16)-1);
4924 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
4928 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
4929 DebugLoc dl = Op.getNode()->getDebugLoc();
4930 // Depths > 0 not supported yet!
4931 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
4934 MachineFunction &MF = DAG.getMachineFunction();
4935 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4937 // Just load the return address off the stack.
4938 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
4940 // Make sure the function really does not optimize away the store of the RA
4942 FuncInfo->setLRStoreRequired();
4943 return DAG.getLoad(getPointerTy(), dl,
4944 DAG.getEntryNode(), RetAddrFI, NULL, 0);
4947 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
4948 DebugLoc dl = Op.getDebugLoc();
4949 // Depths > 0 not supported yet!
4950 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
4953 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4954 bool isPPC64 = PtrVT == MVT::i64;
4956 MachineFunction &MF = DAG.getMachineFunction();
4957 MachineFrameInfo *MFI = MF.getFrameInfo();
4958 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
4959 && MFI->getStackSize();
4962 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
4965 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
4970 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4971 // The PowerPC target isn't yet aware of offsets.