1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
37 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
38 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
41 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
46 // Use _setjmp/_longjmp instead of setjmp/longjmp.
47 setUseUnderscoreSetJmp(true);
48 setUseUnderscoreLongJmp(true);
50 // Set up the register classes.
51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
56 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
57 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
74 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
75 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
76 // This is used in the ppcf128->int sequence. Note it has different semantics
77 // from FP_ROUND: that rounds to nearest, this rounds to zero.
78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
80 // PowerPC has no SREM/UREM instructions
81 setOperationAction(ISD::SREM, MVT::i32, Expand);
82 setOperationAction(ISD::UREM, MVT::i32, Expand);
83 setOperationAction(ISD::SREM, MVT::i64, Expand);
84 setOperationAction(ISD::UREM, MVT::i64, Expand);
86 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
87 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
88 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
89 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
90 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
91 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
92 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
93 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
94 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
96 // We don't support sin/cos/sqrt/fmod/pow
97 setOperationAction(ISD::FSIN , MVT::f64, Expand);
98 setOperationAction(ISD::FCOS , MVT::f64, Expand);
99 setOperationAction(ISD::FREM , MVT::f64, Expand);
100 setOperationAction(ISD::FPOW , MVT::f64, Expand);
101 setOperationAction(ISD::FSIN , MVT::f32, Expand);
102 setOperationAction(ISD::FCOS , MVT::f32, Expand);
103 setOperationAction(ISD::FREM , MVT::f32, Expand);
104 setOperationAction(ISD::FPOW , MVT::f32, Expand);
106 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
108 // If we're enabling GP optimizations, use hardware square root
109 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
110 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
111 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
114 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
115 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
117 // PowerPC does not have BSWAP, CTPOP or CTTZ
118 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
119 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
120 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
121 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
122 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
123 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
125 // PowerPC does not have ROTR
126 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
127 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
129 // PowerPC does not have Select
130 setOperationAction(ISD::SELECT, MVT::i32, Expand);
131 setOperationAction(ISD::SELECT, MVT::i64, Expand);
132 setOperationAction(ISD::SELECT, MVT::f32, Expand);
133 setOperationAction(ISD::SELECT, MVT::f64, Expand);
135 // PowerPC wants to turn select_cc of FP into fsel when possible.
136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
139 // PowerPC wants to optimize integer setcc a bit
140 setOperationAction(ISD::SETCC, MVT::i32, Custom);
142 // PowerPC does not have BRCOND which requires SetCC
143 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
145 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
147 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
148 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
150 // PowerPC does not have [U|S]INT_TO_FP
151 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
152 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
154 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
155 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
156 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
157 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
159 // We cannot sextinreg(i1). Expand to shifts.
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
162 // Support label based line numbers.
163 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
164 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
166 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
167 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
168 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
169 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
172 // We want to legalize GlobalAddress and ConstantPool nodes into the
173 // appropriate instructions to materialize the address.
174 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
175 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
176 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
177 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
178 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
179 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
180 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
181 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
183 // RET must be custom lowered, to meet ABI requirements.
184 setOperationAction(ISD::RET , MVT::Other, Custom);
187 setOperationAction(ISD::TRAP, MVT::Other, Legal);
189 // TRAMPOLINE is custom lowered.
190 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
192 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
193 setOperationAction(ISD::VASTART , MVT::Other, Custom);
195 // VAARG is custom lowered with ELF 32 ABI
196 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
197 setOperationAction(ISD::VAARG, MVT::Other, Custom);
199 setOperationAction(ISD::VAARG, MVT::Other, Expand);
201 // Use the default implementation.
202 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
203 setOperationAction(ISD::VAEND , MVT::Other, Expand);
204 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
205 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
209 // We want to custom lower some of our intrinsics.
210 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
212 // Comparisons that require checking two conditions.
213 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
214 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
215 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
216 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
217 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
218 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
219 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
220 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
221 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
222 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
223 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
224 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
226 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
227 // They also have instructions for converting between i64 and fp.
228 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
229 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
230 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
231 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
232 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
234 // FIXME: disable this lowered code. This generates 64-bit register values,
235 // and we don't model the fact that the top part is clobbered by calls. We
236 // need to flag these together so that the value isn't live across a call.
237 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
239 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
240 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
242 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
243 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
246 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
247 // 64-bit PowerPC implementations can support i64 types directly
248 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
249 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
250 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
251 // 64-bit PowerPC wants to expand i128 shifts itself.
252 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
253 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
254 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
256 // 32-bit PowerPC wants to expand i64 shifts itself.
257 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
258 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
259 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
262 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
263 // First set operation action for all vector types to expand. Then we
264 // will selectively turn on ones that can be effectively codegen'd.
265 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
266 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
267 MVT VT = (MVT::SimpleValueType)i;
269 // add/sub are legal for all supported vector VT's.
270 setOperationAction(ISD::ADD , VT, Legal);
271 setOperationAction(ISD::SUB , VT, Legal);
273 // We promote all shuffles to v16i8.
274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
275 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
277 // We promote all non-typed operations to v4i32.
278 setOperationAction(ISD::AND , VT, Promote);
279 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
280 setOperationAction(ISD::OR , VT, Promote);
281 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
282 setOperationAction(ISD::XOR , VT, Promote);
283 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
284 setOperationAction(ISD::LOAD , VT, Promote);
285 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
286 setOperationAction(ISD::SELECT, VT, Promote);
287 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
288 setOperationAction(ISD::STORE, VT, Promote);
289 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
291 // No other operations are legal.
292 setOperationAction(ISD::MUL , VT, Expand);
293 setOperationAction(ISD::SDIV, VT, Expand);
294 setOperationAction(ISD::SREM, VT, Expand);
295 setOperationAction(ISD::UDIV, VT, Expand);
296 setOperationAction(ISD::UREM, VT, Expand);
297 setOperationAction(ISD::FDIV, VT, Expand);
298 setOperationAction(ISD::FNEG, VT, Expand);
299 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
300 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
301 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
302 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
303 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
304 setOperationAction(ISD::UDIVREM, VT, Expand);
305 setOperationAction(ISD::SDIVREM, VT, Expand);
306 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
307 setOperationAction(ISD::FPOW, VT, Expand);
308 setOperationAction(ISD::CTPOP, VT, Expand);
309 setOperationAction(ISD::CTLZ, VT, Expand);
310 setOperationAction(ISD::CTTZ, VT, Expand);
313 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
314 // with merges, splats, etc.
315 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
317 setOperationAction(ISD::AND , MVT::v4i32, Legal);
318 setOperationAction(ISD::OR , MVT::v4i32, Legal);
319 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
320 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
321 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
322 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
324 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
325 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
326 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
327 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
329 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
330 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
331 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
332 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
334 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
335 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
337 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
338 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
339 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
340 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
343 setShiftAmountType(MVT::i32);
344 setBooleanContents(ZeroOrOneBooleanContent);
346 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
347 setStackPointerRegisterToSaveRestore(PPC::X1);
348 setExceptionPointerRegister(PPC::X3);
349 setExceptionSelectorRegister(PPC::X4);
351 setStackPointerRegisterToSaveRestore(PPC::R1);
352 setExceptionPointerRegister(PPC::R3);
353 setExceptionSelectorRegister(PPC::R4);
356 // We have target-specific dag combine patterns for the following nodes:
357 setTargetDAGCombine(ISD::SINT_TO_FP);
358 setTargetDAGCombine(ISD::STORE);
359 setTargetDAGCombine(ISD::BR_CC);
360 setTargetDAGCombine(ISD::BSWAP);
362 // Darwin long double math library functions have $LDBL128 appended.
363 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
364 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
365 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
366 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
367 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
368 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
369 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
370 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
371 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
372 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
373 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
376 computeRegisterProperties();
379 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
380 /// function arguments in the caller parameter area.
381 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
382 TargetMachine &TM = getTargetMachine();
383 // Darwin passes everything on 4 byte boundary.
384 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
390 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
393 case PPCISD::FSEL: return "PPCISD::FSEL";
394 case PPCISD::FCFID: return "PPCISD::FCFID";
395 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
396 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
397 case PPCISD::STFIWX: return "PPCISD::STFIWX";
398 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
399 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
400 case PPCISD::VPERM: return "PPCISD::VPERM";
401 case PPCISD::Hi: return "PPCISD::Hi";
402 case PPCISD::Lo: return "PPCISD::Lo";
403 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
404 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
405 case PPCISD::SRL: return "PPCISD::SRL";
406 case PPCISD::SRA: return "PPCISD::SRA";
407 case PPCISD::SHL: return "PPCISD::SHL";
408 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
409 case PPCISD::STD_32: return "PPCISD::STD_32";
410 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
411 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
412 case PPCISD::MTCTR: return "PPCISD::MTCTR";
413 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
414 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
415 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
416 case PPCISD::MFCR: return "PPCISD::MFCR";
417 case PPCISD::VCMP: return "PPCISD::VCMP";
418 case PPCISD::VCMPo: return "PPCISD::VCMPo";
419 case PPCISD::LBRX: return "PPCISD::LBRX";
420 case PPCISD::STBRX: return "PPCISD::STBRX";
421 case PPCISD::LARX: return "PPCISD::LARX";
422 case PPCISD::STCX: return "PPCISD::STCX";
423 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
424 case PPCISD::MFFS: return "PPCISD::MFFS";
425 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
426 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
427 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
428 case PPCISD::MTFSF: return "PPCISD::MTFSF";
429 case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
430 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
435 MVT PPCTargetLowering::getSetCCResultType(MVT VT) const {
440 //===----------------------------------------------------------------------===//
441 // Node matching predicates, for use by the tblgen matching code.
442 //===----------------------------------------------------------------------===//
444 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
445 static bool isFloatingPointZero(SDValue Op) {
446 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
447 return CFP->getValueAPF().isZero();
448 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
449 // Maybe this has already been legalized into the constant pool?
450 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
451 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
452 return CFP->getValueAPF().isZero();
457 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
458 /// true if Op is undef or if it matches the specified value.
459 static bool isConstantOrUndef(SDValue Op, unsigned Val) {
460 return Op.getOpcode() == ISD::UNDEF ||
461 cast<ConstantSDNode>(Op)->getZExtValue() == Val;
464 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
465 /// VPKUHUM instruction.
466 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
468 for (unsigned i = 0; i != 16; ++i)
469 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
472 for (unsigned i = 0; i != 8; ++i)
473 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
474 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
480 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
481 /// VPKUWUM instruction.
482 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
484 for (unsigned i = 0; i != 16; i += 2)
485 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
486 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
489 for (unsigned i = 0; i != 8; i += 2)
490 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
491 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
492 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
493 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
499 /// isVMerge - Common function, used to match vmrg* shuffles.
501 static bool isVMerge(SDNode *N, unsigned UnitSize,
502 unsigned LHSStart, unsigned RHSStart) {
503 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
504 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
505 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
506 "Unsupported merge size!");
508 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
509 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
510 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
511 LHSStart+j+i*UnitSize) ||
512 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
513 RHSStart+j+i*UnitSize))
519 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
520 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
521 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
523 return isVMerge(N, UnitSize, 8, 24);
524 return isVMerge(N, UnitSize, 8, 8);
527 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
528 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
529 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
531 return isVMerge(N, UnitSize, 0, 16);
532 return isVMerge(N, UnitSize, 0, 0);
536 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
537 /// amount, otherwise return -1.
538 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
539 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
540 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
541 // Find the first non-undef value in the shuffle mask.
543 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
546 if (i == 16) return -1; // all undef.
548 // Otherwise, check to see if the rest of the elements are consequtively
549 // numbered from this value.
550 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getZExtValue();
551 if (ShiftAmt < i) return -1;
555 // Check the rest of the elements to see if they are consequtive.
556 for (++i; i != 16; ++i)
557 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
560 // Check the rest of the elements to see if they are consequtive.
561 for (++i; i != 16; ++i)
562 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
569 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
570 /// specifies a splat of a single element that is suitable for input to
571 /// VSPLTB/VSPLTH/VSPLTW.
572 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
573 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
574 N->getNumOperands() == 16 &&
575 (EltSize == 1 || EltSize == 2 || EltSize == 4));
577 // This is a splat operation if each element of the permute is the same, and
578 // if the value doesn't reference the second vector.
579 unsigned ElementBase = 0;
580 SDValue Elt = N->getOperand(0);
581 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
582 ElementBase = EltV->getZExtValue();
584 return false; // FIXME: Handle UNDEF elements too!
586 if (cast<ConstantSDNode>(Elt)->getZExtValue() >= 16)
589 // Check that they are consequtive.
590 for (unsigned i = 1; i != EltSize; ++i) {
591 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
592 cast<ConstantSDNode>(N->getOperand(i))->getZExtValue() != i+ElementBase)
596 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
597 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
598 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
599 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
600 "Invalid VECTOR_SHUFFLE mask!");
601 for (unsigned j = 0; j != EltSize; ++j)
602 if (N->getOperand(i+j) != N->getOperand(j))
609 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
611 bool PPC::isAllNegativeZeroVector(SDNode *N) {
612 assert(N->getOpcode() == ISD::BUILD_VECTOR);
613 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
614 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
615 return CFP->getValueAPF().isNegZero();
619 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
620 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
621 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
622 assert(isSplatShuffleMask(N, EltSize));
623 return cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() / EltSize;
626 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
627 /// by using a vspltis[bhw] instruction of the specified element size, return
628 /// the constant being splatted. The ByteSize field indicates the number of
629 /// bytes of each element [124] -> [bhw].
630 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
633 // If ByteSize of the splat is bigger than the element size of the
634 // build_vector, then we have a case where we are checking for a splat where
635 // multiple elements of the buildvector are folded together into a single
636 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
637 unsigned EltSize = 16/N->getNumOperands();
638 if (EltSize < ByteSize) {
639 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
640 SDValue UniquedVals[4];
641 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
643 // See if all of the elements in the buildvector agree across.
644 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
645 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
646 // If the element isn't a constant, bail fully out.
647 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
650 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
651 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
652 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
653 return SDValue(); // no match.
656 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
657 // either constant or undef values that are identical for each chunk. See
658 // if these chunks can form into a larger vspltis*.
660 // Check to see if all of the leading entries are either 0 or -1. If
661 // neither, then this won't fit into the immediate field.
662 bool LeadingZero = true;
663 bool LeadingOnes = true;
664 for (unsigned i = 0; i != Multiple-1; ++i) {
665 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
667 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
668 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
670 // Finally, check the least significant entry.
672 if (UniquedVals[Multiple-1].getNode() == 0)
673 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
674 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
676 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
679 if (UniquedVals[Multiple-1].getNode() == 0)
680 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
681 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
682 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
683 return DAG.getTargetConstant(Val, MVT::i32);
689 // Check to see if this buildvec has a single non-undef value in its elements.
690 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
691 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
692 if (OpVal.getNode() == 0)
693 OpVal = N->getOperand(i);
694 else if (OpVal != N->getOperand(i))
698 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
700 unsigned ValSizeInBytes = 0;
702 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
703 Value = CN->getZExtValue();
704 ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8;
705 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
706 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
707 Value = FloatToBits(CN->getValueAPF().convertToFloat());
711 // If the splat value is larger than the element value, then we can never do
712 // this splat. The only case that we could fit the replicated bits into our
713 // immediate field for would be zero, and we prefer to use vxor for it.
714 if (ValSizeInBytes < ByteSize) return SDValue();
716 // If the element value is larger than the splat value, cut it in half and
717 // check to see if the two halves are equal. Continue doing this until we
718 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
719 while (ValSizeInBytes > ByteSize) {
720 ValSizeInBytes >>= 1;
722 // If the top half equals the bottom half, we're still ok.
723 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
724 (Value & ((1 << (8*ValSizeInBytes))-1)))
728 // Properly sign extend the value.
729 int ShAmt = (4-ByteSize)*8;
730 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
732 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
733 if (MaskVal == 0) return SDValue();
735 // Finally, if this value fits in a 5 bit sext field, return it
736 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
737 return DAG.getTargetConstant(MaskVal, MVT::i32);
741 //===----------------------------------------------------------------------===//
742 // Addressing Mode Selection
743 //===----------------------------------------------------------------------===//
745 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
746 /// or 64-bit immediate, and if the value can be accurately represented as a
747 /// sign extension from a 16-bit value. If so, this returns true and the
749 static bool isIntS16Immediate(SDNode *N, short &Imm) {
750 if (N->getOpcode() != ISD::Constant)
753 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
754 if (N->getValueType(0) == MVT::i32)
755 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
757 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
759 static bool isIntS16Immediate(SDValue Op, short &Imm) {
760 return isIntS16Immediate(Op.getNode(), Imm);
764 /// SelectAddressRegReg - Given the specified addressed, check to see if it
765 /// can be represented as an indexed [r+r] operation. Returns false if it
766 /// can be more efficiently represented with [r+imm].
767 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
769 SelectionDAG &DAG) const {
771 if (N.getOpcode() == ISD::ADD) {
772 if (isIntS16Immediate(N.getOperand(1), imm))
774 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
777 Base = N.getOperand(0);
778 Index = N.getOperand(1);
780 } else if (N.getOpcode() == ISD::OR) {
781 if (isIntS16Immediate(N.getOperand(1), imm))
782 return false; // r+i can fold it if we can.
784 // If this is an or of disjoint bitfields, we can codegen this as an add
785 // (for better address arithmetic) if the LHS and RHS of the OR are provably
787 APInt LHSKnownZero, LHSKnownOne;
788 APInt RHSKnownZero, RHSKnownOne;
789 DAG.ComputeMaskedBits(N.getOperand(0),
790 APInt::getAllOnesValue(N.getOperand(0)
791 .getValueSizeInBits()),
792 LHSKnownZero, LHSKnownOne);
794 if (LHSKnownZero.getBoolValue()) {
795 DAG.ComputeMaskedBits(N.getOperand(1),
796 APInt::getAllOnesValue(N.getOperand(1)
797 .getValueSizeInBits()),
798 RHSKnownZero, RHSKnownOne);
799 // If all of the bits are known zero on the LHS or RHS, the add won't
801 if (~(LHSKnownZero | RHSKnownZero) == 0) {
802 Base = N.getOperand(0);
803 Index = N.getOperand(1);
812 /// Returns true if the address N can be represented by a base register plus
813 /// a signed 16-bit displacement [r+imm], and if it is not better
814 /// represented as reg+reg.
815 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
817 SelectionDAG &DAG) const {
818 // FIXME dl should come from parent load or store, not from address
819 DebugLoc dl = N.getDebugLoc();
820 // If this can be more profitably realized as r+r, fail.
821 if (SelectAddressRegReg(N, Disp, Base, DAG))
824 if (N.getOpcode() == ISD::ADD) {
826 if (isIntS16Immediate(N.getOperand(1), imm)) {
827 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
828 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
829 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
831 Base = N.getOperand(0);
833 return true; // [r+i]
834 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
835 // Match LOAD (ADD (X, Lo(G))).
836 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
837 && "Cannot handle constant offsets yet!");
838 Disp = N.getOperand(1).getOperand(0); // The global address.
839 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
840 Disp.getOpcode() == ISD::TargetConstantPool ||
841 Disp.getOpcode() == ISD::TargetJumpTable);
842 Base = N.getOperand(0);
843 return true; // [&g+r]
845 } else if (N.getOpcode() == ISD::OR) {
847 if (isIntS16Immediate(N.getOperand(1), imm)) {
848 // If this is an or of disjoint bitfields, we can codegen this as an add
849 // (for better address arithmetic) if the LHS and RHS of the OR are
850 // provably disjoint.
851 APInt LHSKnownZero, LHSKnownOne;
852 DAG.ComputeMaskedBits(N.getOperand(0),
853 APInt::getAllOnesValue(N.getOperand(0)
854 .getValueSizeInBits()),
855 LHSKnownZero, LHSKnownOne);
857 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
858 // If all of the bits are known zero on the LHS or RHS, the add won't
860 Base = N.getOperand(0);
861 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
865 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
866 // Loading from a constant address.
868 // If this address fits entirely in a 16-bit sext immediate field, codegen
871 if (isIntS16Immediate(CN, Imm)) {
872 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
873 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
877 // Handle 32-bit sext immediates with LIS + addr mode.
878 if (CN->getValueType(0) == MVT::i32 ||
879 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
880 int Addr = (int)CN->getZExtValue();
882 // Otherwise, break this down into an LIS + disp.
883 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
885 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
886 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
887 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
892 Disp = DAG.getTargetConstant(0, getPointerTy());
893 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
894 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
897 return true; // [r+0]
900 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
901 /// represented as an indexed [r+r] operation.
902 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
904 SelectionDAG &DAG) const {
905 // Check to see if we can easily represent this as an [r+r] address. This
906 // will fail if it thinks that the address is more profitably represented as
907 // reg+imm, e.g. where imm = 0.
908 if (SelectAddressRegReg(N, Base, Index, DAG))
911 // If the operand is an addition, always emit this as [r+r], since this is
912 // better (for code size, and execution, as the memop does the add for free)
913 // than emitting an explicit add.
914 if (N.getOpcode() == ISD::ADD) {
915 Base = N.getOperand(0);
916 Index = N.getOperand(1);
920 // Otherwise, do it the hard way, using R0 as the base register.
921 Base = DAG.getRegister(PPC::R0, N.getValueType());
926 /// SelectAddressRegImmShift - Returns true if the address N can be
927 /// represented by a base register plus a signed 14-bit displacement
928 /// [r+imm*4]. Suitable for use by STD and friends.
929 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
931 SelectionDAG &DAG) const {
932 // FIXME dl should come from the parent load or store, not the address
933 DebugLoc dl = N.getDebugLoc();
934 // If this can be more profitably realized as r+r, fail.
935 if (SelectAddressRegReg(N, Disp, Base, DAG))
938 if (N.getOpcode() == ISD::ADD) {
940 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
941 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
942 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
943 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
945 Base = N.getOperand(0);
947 return true; // [r+i]
948 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
949 // Match LOAD (ADD (X, Lo(G))).
950 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
951 && "Cannot handle constant offsets yet!");
952 Disp = N.getOperand(1).getOperand(0); // The global address.
953 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
954 Disp.getOpcode() == ISD::TargetConstantPool ||
955 Disp.getOpcode() == ISD::TargetJumpTable);
956 Base = N.getOperand(0);
957 return true; // [&g+r]
959 } else if (N.getOpcode() == ISD::OR) {
961 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
962 // If this is an or of disjoint bitfields, we can codegen this as an add
963 // (for better address arithmetic) if the LHS and RHS of the OR are
964 // provably disjoint.
965 APInt LHSKnownZero, LHSKnownOne;
966 DAG.ComputeMaskedBits(N.getOperand(0),
967 APInt::getAllOnesValue(N.getOperand(0)
968 .getValueSizeInBits()),
969 LHSKnownZero, LHSKnownOne);
970 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
971 // If all of the bits are known zero on the LHS or RHS, the add won't
973 Base = N.getOperand(0);
974 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
978 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
979 // Loading from a constant address. Verify low two bits are clear.
980 if ((CN->getZExtValue() & 3) == 0) {
981 // If this address fits entirely in a 14-bit sext immediate field, codegen
984 if (isIntS16Immediate(CN, Imm)) {
985 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
986 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
990 // Fold the low-part of 32-bit absolute addresses into addr mode.
991 if (CN->getValueType(0) == MVT::i32 ||
992 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
993 int Addr = (int)CN->getZExtValue();
995 // Otherwise, break this down into an LIS + disp.
996 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
997 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
998 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
999 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0);
1005 Disp = DAG.getTargetConstant(0, getPointerTy());
1006 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1007 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1010 return true; // [r+0]
1014 /// getPreIndexedAddressParts - returns true by value, base pointer and
1015 /// offset pointer and addressing mode by reference if the node's address
1016 /// can be legally represented as pre-indexed load / store address.
1017 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1019 ISD::MemIndexedMode &AM,
1020 SelectionDAG &DAG) const {
1021 // Disabled by default for now.
1022 if (!EnablePPCPreinc) return false;
1026 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1027 Ptr = LD->getBasePtr();
1028 VT = LD->getMemoryVT();
1030 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1032 Ptr = ST->getBasePtr();
1033 VT = ST->getMemoryVT();
1037 // PowerPC doesn't have preinc load/store instructions for vectors.
1041 // TODO: Check reg+reg first.
1043 // LDU/STU use reg+imm*4, others use reg+imm.
1044 if (VT != MVT::i64) {
1046 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1050 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1054 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1055 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1056 // sext i32 to i64 when addr mode is r+i.
1057 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1058 LD->getExtensionType() == ISD::SEXTLOAD &&
1059 isa<ConstantSDNode>(Offset))
1067 //===----------------------------------------------------------------------===//
1068 // LowerOperation implementation
1069 //===----------------------------------------------------------------------===//
1071 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1072 SelectionDAG &DAG) {
1073 MVT PtrVT = Op.getValueType();
1074 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1075 Constant *C = CP->getConstVal();
1076 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1077 SDValue Zero = DAG.getConstant(0, PtrVT);
1078 // FIXME there isn't really any debug info here
1079 DebugLoc dl = Op.getDebugLoc();
1081 const TargetMachine &TM = DAG.getTarget();
1083 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
1084 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
1086 // If this is a non-darwin platform, we don't support non-static relo models
1088 if (TM.getRelocationModel() == Reloc::Static ||
1089 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1090 // Generate non-pic code that has direct accesses to the constant pool.
1091 // The address of the global is just (hi(&g)+lo(&g)).
1092 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1095 if (TM.getRelocationModel() == Reloc::PIC_) {
1096 // With PIC, the first instruction is actually "GR+hi(&G)".
1097 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1098 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1101 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1105 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1106 MVT PtrVT = Op.getValueType();
1107 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1108 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1109 SDValue Zero = DAG.getConstant(0, PtrVT);
1110 // FIXME there isn't really any debug loc here
1111 DebugLoc dl = Op.getDebugLoc();
1113 const TargetMachine &TM = DAG.getTarget();
1115 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
1116 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
1118 // If this is a non-darwin platform, we don't support non-static relo models
1120 if (TM.getRelocationModel() == Reloc::Static ||
1121 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1122 // Generate non-pic code that has direct accesses to the constant pool.
1123 // The address of the global is just (hi(&g)+lo(&g)).
1124 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1127 if (TM.getRelocationModel() == Reloc::PIC_) {
1128 // With PIC, the first instruction is actually "GR+hi(&G)".
1129 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1130 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1133 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1137 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1138 SelectionDAG &DAG) {
1139 assert(0 && "TLS not implemented for PPC.");
1140 return SDValue(); // Not reached
1143 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1144 SelectionDAG &DAG) {
1145 MVT PtrVT = Op.getValueType();
1146 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1147 GlobalValue *GV = GSDN->getGlobal();
1148 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1149 SDValue Zero = DAG.getConstant(0, PtrVT);
1150 // FIXME there isn't really any debug info here
1151 DebugLoc dl = GSDN->getDebugLoc();
1153 const TargetMachine &TM = DAG.getTarget();
1155 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1156 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1158 // If this is a non-darwin platform, we don't support non-static relo models
1160 if (TM.getRelocationModel() == Reloc::Static ||
1161 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1162 // Generate non-pic code that has direct accesses to globals.
1163 // The address of the global is just (hi(&g)+lo(&g)).
1164 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1167 if (TM.getRelocationModel() == Reloc::PIC_) {
1168 // With PIC, the first instruction is actually "GR+hi(&G)".
1169 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1170 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1173 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1175 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1178 // If the global is weak or external, we have to go through the lazy
1180 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
1183 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1184 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1185 DebugLoc dl = Op.getNode()->getDebugLoc();
1187 // If we're comparing for equality to zero, expose the fact that this is
1188 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1189 // fold the new nodes.
1190 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1191 if (C->isNullValue() && CC == ISD::SETEQ) {
1192 MVT VT = Op.getOperand(0).getValueType();
1193 SDValue Zext = Op.getOperand(0);
1194 if (VT.bitsLT(MVT::i32)) {
1196 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1198 unsigned Log2b = Log2_32(VT.getSizeInBits());
1199 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1200 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1201 DAG.getConstant(Log2b, MVT::i32));
1202 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1204 // Leave comparisons against 0 and -1 alone for now, since they're usually
1205 // optimized. FIXME: revisit this when we can custom lower all setcc
1207 if (C->isAllOnesValue() || C->isNullValue())
1211 // If we have an integer seteq/setne, turn it into a compare against zero
1212 // by xor'ing the rhs with the lhs, which is faster than setting a
1213 // condition register, reading it back out, and masking the correct bit. The
1214 // normal approach here uses sub to do this instead of xor. Using xor exposes
1215 // the result to other bit-twiddling opportunities.
1216 MVT LHSVT = Op.getOperand(0).getValueType();
1217 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1218 MVT VT = Op.getValueType();
1219 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1221 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1226 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1227 int VarArgsFrameIndex,
1228 int VarArgsStackOffset,
1229 unsigned VarArgsNumGPR,
1230 unsigned VarArgsNumFPR,
1231 const PPCSubtarget &Subtarget) {
1233 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1234 return SDValue(); // Not reached
1237 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1238 SDValue Chain = Op.getOperand(0);
1239 SDValue Trmp = Op.getOperand(1); // trampoline
1240 SDValue FPtr = Op.getOperand(2); // nested function
1241 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1242 DebugLoc dl = Op.getNode()->getDebugLoc();
1244 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1245 bool isPPC64 = (PtrVT == MVT::i64);
1246 const Type *IntPtrTy =
1247 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType();
1249 TargetLowering::ArgListTy Args;
1250 TargetLowering::ArgListEntry Entry;
1252 Entry.Ty = IntPtrTy;
1253 Entry.Node = Trmp; Args.push_back(Entry);
1255 // TrampSize == (isPPC64 ? 48 : 40);
1256 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1257 isPPC64 ? MVT::i64 : MVT::i32);
1258 Args.push_back(Entry);
1260 Entry.Node = FPtr; Args.push_back(Entry);
1261 Entry.Node = Nest; Args.push_back(Entry);
1263 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1264 std::pair<SDValue, SDValue> CallResult =
1265 LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false,
1266 false, false, CallingConv::C, false,
1267 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1271 { CallResult.first, CallResult.second };
1273 return DAG.getMergeValues(Ops, 2, dl);
1276 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1277 int VarArgsFrameIndex,
1278 int VarArgsStackOffset,
1279 unsigned VarArgsNumGPR,
1280 unsigned VarArgsNumFPR,
1281 const PPCSubtarget &Subtarget) {
1282 DebugLoc dl = Op.getNode()->getDebugLoc();
1284 if (Subtarget.isMachoABI()) {
1285 // vastart just stores the address of the VarArgsFrameIndex slot into the
1286 // memory location argument.
1287 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1288 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1289 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1290 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1293 // For ELF 32 ABI we follow the layout of the va_list struct.
1294 // We suppose the given va_list is already allocated.
1297 // char gpr; /* index into the array of 8 GPRs
1298 // * stored in the register save area
1299 // * gpr=0 corresponds to r3,
1300 // * gpr=1 to r4, etc.
1302 // char fpr; /* index into the array of 8 FPRs
1303 // * stored in the register save area
1304 // * fpr=0 corresponds to f1,
1305 // * fpr=1 to f2, etc.
1307 // char *overflow_arg_area;
1308 // /* location on stack that holds
1309 // * the next overflow argument
1311 // char *reg_save_area;
1312 // /* where r3:r10 and f1:f8 (if saved)
1318 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1319 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1322 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1324 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1325 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1327 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1328 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1330 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1331 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1333 uint64_t FPROffset = 1;
1334 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1336 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1338 // Store first byte : number of int regs
1339 SDValue firstStore = DAG.getStore(Op.getOperand(0), dl, ArgGPR,
1340 Op.getOperand(1), SV, 0);
1341 uint64_t nextOffset = FPROffset;
1342 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1345 // Store second byte : number of float regs
1346 SDValue secondStore =
1347 DAG.getStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset);
1348 nextOffset += StackOffset;
1349 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1351 // Store second word : arguments given on stack
1352 SDValue thirdStore =
1353 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
1354 nextOffset += FrameOffset;
1355 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1357 // Store third word : arguments given in registers
1358 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset);
1362 #include "PPCGenCallingConv.inc"
1364 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1365 /// depending on which subtarget is selected.
1366 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1367 if (Subtarget.isMachoABI()) {
1368 static const unsigned FPR[] = {
1369 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1370 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1376 static const unsigned FPR[] = {
1377 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1383 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1385 static unsigned CalculateStackSlotSize(SDValue Arg, ISD::ArgFlagsTy Flags,
1386 bool isVarArg, unsigned PtrByteSize) {
1387 MVT ArgVT = Arg.getValueType();
1388 unsigned ArgSize =ArgVT.getSizeInBits()/8;
1389 if (Flags.isByVal())
1390 ArgSize = Flags.getByValSize();
1391 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1397 PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1399 int &VarArgsFrameIndex,
1400 int &VarArgsStackOffset,
1401 unsigned &VarArgsNumGPR,
1402 unsigned &VarArgsNumFPR,
1403 const PPCSubtarget &Subtarget) {
1404 // TODO: add description of PPC stack frame format, or at least some docs.
1406 MachineFunction &MF = DAG.getMachineFunction();
1407 MachineFrameInfo *MFI = MF.getFrameInfo();
1408 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1409 SmallVector<SDValue, 8> ArgValues;
1410 SDValue Root = Op.getOperand(0);
1411 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1412 DebugLoc dl = Op.getNode()->getDebugLoc();
1414 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1415 bool isPPC64 = PtrVT == MVT::i64;
1416 bool isMachoABI = Subtarget.isMachoABI();
1417 bool isELF32_ABI = Subtarget.isELF32_ABI();
1418 // Potential tail calls could cause overwriting of argument stack slots.
1419 unsigned CC = MF.getFunction()->getCallingConv();
1420 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1421 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1423 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1424 // Area that is at least reserved in caller of this function.
1425 unsigned MinReservedArea = ArgOffset;
1427 static const unsigned GPR_32[] = { // 32-bit registers.
1428 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1429 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1431 static const unsigned GPR_64[] = { // 64-bit registers.
1432 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1433 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1436 static const unsigned *FPR = GetFPR(Subtarget);
1438 static const unsigned VR[] = {
1439 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1440 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1443 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1444 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1445 const unsigned Num_VR_Regs = array_lengthof( VR);
1447 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1449 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1451 // In 32-bit non-varargs functions, the stack space for vectors is after the
1452 // stack space for non-vectors. We do not use this space unless we have
1453 // too many vectors to fit in registers, something that only occurs in
1454 // constructed examples:), but we have to walk the arglist to figure
1455 // that out...for the pathological case, compute VecArgOffset as the
1456 // start of the vector parameter area. Computing VecArgOffset is the
1457 // entire point of the following loop.
1458 // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying
1459 // to handle Elf here.
1460 unsigned VecArgOffset = ArgOffset;
1461 if (!isVarArg && !isPPC64) {
1462 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e;
1464 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1465 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1466 ISD::ArgFlagsTy Flags =
1467 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1469 if (Flags.isByVal()) {
1470 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1471 ObjSize = Flags.getByValSize();
1473 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1474 VecArgOffset += ArgSize;
1478 switch(ObjectVT.getSimpleVT()) {
1479 default: assert(0 && "Unhandled argument type!");
1482 VecArgOffset += isPPC64 ? 8 : 4;
1484 case MVT::i64: // PPC64
1492 // Nothing to do, we're only looking at Nonvector args here.
1497 // We've found where the vector parameter area in memory is. Skip the
1498 // first 12 parameters; these don't use that memory.
1499 VecArgOffset = ((VecArgOffset+15)/16)*16;
1500 VecArgOffset += 12*16;
1502 // Add DAG nodes to load the arguments or copy them out of registers. On
1503 // entry to a function on PPC, the arguments start after the linkage area,
1504 // although the first ones are often in registers.
1506 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1507 // represented with two words (long long or double) must be copied to an
1508 // even GPR_idx value or to an even ArgOffset value.
1510 SmallVector<SDValue, 8> MemOps;
1511 unsigned nAltivecParamsAtEnd = 0;
1512 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1;
1513 ArgNo != e; ++ArgNo) {
1515 bool needsLoad = false;
1516 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1517 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1518 unsigned ArgSize = ObjSize;
1519 ISD::ArgFlagsTy Flags =
1520 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1521 // See if next argument requires stack alignment in ELF
1522 bool Align = Flags.isSplit();
1524 unsigned CurArgOffset = ArgOffset;
1526 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1527 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1528 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1529 if (isVarArg || isPPC64) {
1530 MinReservedArea = ((MinReservedArea+15)/16)*16;
1531 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1535 } else nAltivecParamsAtEnd++;
1537 // Calculate min reserved area.
1538 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1543 // FIXME alignment for ELF may not be right
1544 // FIXME the codegen can be much improved in some cases.
1545 // We do not have to keep everything in memory.
1546 if (Flags.isByVal()) {
1547 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1548 ObjSize = Flags.getByValSize();
1549 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1550 // Double word align in ELF
1551 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1552 // Objects of size 1 and 2 are right justified, everything else is
1553 // left justified. This means the memory address is adjusted forwards.
1554 if (ObjSize==1 || ObjSize==2) {
1555 CurArgOffset = CurArgOffset + (4 - ObjSize);
1557 // The value of the object is its address.
1558 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1559 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1560 ArgValues.push_back(FIN);
1561 if (ObjSize==1 || ObjSize==2) {
1562 if (GPR_idx != Num_GPR_Regs) {
1563 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1564 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1565 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1566 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1567 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1568 MemOps.push_back(Store);
1570 if (isMachoABI) ArgOffset += PtrByteSize;
1572 ArgOffset += PtrByteSize;
1576 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1577 // Store whatever pieces of the object are in registers
1578 // to memory. ArgVal will be address of the beginning of
1580 if (GPR_idx != Num_GPR_Regs) {
1581 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1582 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1583 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1584 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1585 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1586 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1587 MemOps.push_back(Store);
1589 if (isMachoABI) ArgOffset += PtrByteSize;
1591 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1598 switch (ObjectVT.getSimpleVT()) {
1599 default: assert(0 && "Unhandled argument type!");
1602 // Double word align in ELF
1603 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1605 if (GPR_idx != Num_GPR_Regs) {
1606 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1607 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1608 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1612 ArgSize = PtrByteSize;
1614 // Stack align in ELF
1615 if (needsLoad && Align && isELF32_ABI)
1616 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1617 // All int arguments reserve stack space in Macho ABI.
1618 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1622 case MVT::i64: // PPC64
1623 if (GPR_idx != Num_GPR_Regs) {
1624 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1625 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1626 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1628 if (ObjectVT == MVT::i32) {
1629 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1630 // value to MVT::i64 and then truncate to the correct register size.
1632 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1633 DAG.getValueType(ObjectVT));
1634 else if (Flags.isZExt())
1635 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1636 DAG.getValueType(ObjectVT));
1638 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1644 ArgSize = PtrByteSize;
1646 // All int arguments reserve stack space in Macho ABI.
1647 if (isMachoABI || needsLoad) ArgOffset += 8;
1652 // Every 4 bytes of argument space consumes one of the GPRs available for
1653 // argument passing.
1654 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1656 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1659 if (FPR_idx != Num_FPR_Regs) {
1661 if (ObjectVT == MVT::f32)
1662 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1664 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1665 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1666 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1672 // Stack align in ELF
1673 if (needsLoad && Align && isELF32_ABI)
1674 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1675 // All FP arguments reserve stack space in Macho ABI.
1676 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1682 // Note that vector arguments in registers don't reserve stack space,
1683 // except in varargs functions.
1684 if (VR_idx != Num_VR_Regs) {
1685 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1686 RegInfo.addLiveIn(VR[VR_idx], VReg);
1687 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1689 while ((ArgOffset % 16) != 0) {
1690 ArgOffset += PtrByteSize;
1691 if (GPR_idx != Num_GPR_Regs)
1695 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1699 if (!isVarArg && !isPPC64) {
1700 // Vectors go after all the nonvectors.
1701 CurArgOffset = VecArgOffset;
1704 // Vectors are aligned.
1705 ArgOffset = ((ArgOffset+15)/16)*16;
1706 CurArgOffset = ArgOffset;
1714 // We need to load the argument to a virtual register if we determined above
1715 // that we ran out of physical registers of the appropriate type.
1717 int FI = MFI->CreateFixedObject(ObjSize,
1718 CurArgOffset + (ArgSize - ObjSize),
1720 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1721 ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
1724 ArgValues.push_back(ArgVal);
1727 // Set the size that is at least reserved in caller of this function. Tail
1728 // call optimized function's reserved stack space needs to be aligned so that
1729 // taking the difference between two stack areas will result in an aligned
1731 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1732 // Add the Altivec parameters at the end, if needed.
1733 if (nAltivecParamsAtEnd) {
1734 MinReservedArea = ((MinReservedArea+15)/16)*16;
1735 MinReservedArea += 16*nAltivecParamsAtEnd;
1738 std::max(MinReservedArea,
1739 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1740 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1741 getStackAlignment();
1742 unsigned AlignMask = TargetAlign-1;
1743 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1744 FI->setMinReservedArea(MinReservedArea);
1746 // If the function takes variable number of arguments, make a frame index for
1747 // the start of the first vararg value... for expansion of llvm.va_start.
1752 VarArgsNumGPR = GPR_idx;
1753 VarArgsNumFPR = FPR_idx;
1755 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1757 depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 +
1758 Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 +
1759 PtrVT.getSizeInBits()/8);
1761 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1768 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1770 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1772 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1773 // stored to the VarArgsFrameIndex on the stack.
1775 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1776 SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1777 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
1778 MemOps.push_back(Store);
1779 // Increment the address by four for the next argument to store
1780 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1781 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1785 // If this function is vararg, store any remaining integer argument regs
1786 // to their spots on the stack so that they may be loaded by deferencing the
1787 // result of va_next.
1788 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1791 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1793 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1795 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1796 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1797 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1798 MemOps.push_back(Store);
1799 // Increment the address by four for the next argument to store
1800 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1801 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1804 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1807 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1808 SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1809 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
1810 MemOps.push_back(Store);
1811 // Increment the address by eight for the next argument to store
1812 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1814 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1817 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1819 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1821 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1822 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64);
1823 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1824 MemOps.push_back(Store);
1825 // Increment the address by eight for the next argument to store
1826 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1828 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1833 if (!MemOps.empty())
1834 Root = DAG.getNode(ISD::TokenFactor, dl,
1835 MVT::Other, &MemOps[0], MemOps.size());
1837 ArgValues.push_back(Root);
1839 // Return the new list of results.
1840 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1841 &ArgValues[0], ArgValues.size());
1844 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
1847 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
1852 CallSDNode *TheCall,
1853 unsigned &nAltivecParamsAtEnd) {
1854 // Count how many bytes are to be pushed on the stack, including the linkage
1855 // area, and parameter passing area. We start with 24/48 bytes, which is
1856 // prereserved space for [SP][CR][LR][3 x unused].
1857 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1858 unsigned NumOps = TheCall->getNumArgs();
1859 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1861 // Add up all the space actually used.
1862 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
1863 // they all go in registers, but we must reserve stack space for them for
1864 // possible use by the caller. In varargs or 64-bit calls, parameters are
1865 // assigned stack space in order, with padding so Altivec parameters are
1867 nAltivecParamsAtEnd = 0;
1868 for (unsigned i = 0; i != NumOps; ++i) {
1869 SDValue Arg = TheCall->getArg(i);
1870 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1871 MVT ArgVT = Arg.getValueType();
1872 // Varargs Altivec parameters are padded to a 16 byte boundary.
1873 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
1874 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
1875 if (!isVarArg && !isPPC64) {
1876 // Non-varargs Altivec parameters go after all the non-Altivec
1877 // parameters; handle those later so we know how much padding we need.
1878 nAltivecParamsAtEnd++;
1881 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
1882 NumBytes = ((NumBytes+15)/16)*16;
1884 NumBytes += CalculateStackSlotSize(Arg, Flags, isVarArg, PtrByteSize);
1887 // Allow for Altivec parameters at the end, if needed.
1888 if (nAltivecParamsAtEnd) {
1889 NumBytes = ((NumBytes+15)/16)*16;
1890 NumBytes += 16*nAltivecParamsAtEnd;
1893 // The prolog code of the callee may store up to 8 GPR argument registers to
1894 // the stack, allowing va_start to index over them in memory if its varargs.
1895 // Because we cannot tell if this is needed on the caller side, we have to
1896 // conservatively assume that it is needed. As such, make sure we have at
1897 // least enough stack space for the caller to store the 8 GPRs.
1898 NumBytes = std::max(NumBytes,
1899 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1901 // Tail call needs the stack to be aligned.
1902 if (CC==CallingConv::Fast && PerformTailCallOpt) {
1903 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1904 getStackAlignment();
1905 unsigned AlignMask = TargetAlign-1;
1906 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
1912 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
1913 /// adjusted to accomodate the arguments for the tailcall.
1914 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
1915 unsigned ParamSize) {
1917 if (!IsTailCall) return 0;
1919 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
1920 unsigned CallerMinReservedArea = FI->getMinReservedArea();
1921 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
1922 // Remember only if the new adjustement is bigger.
1923 if (SPDiff < FI->getTailCallSPDelta())
1924 FI->setTailCallSPDelta(SPDiff);
1929 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1930 /// following the call is a return. A function is eligible if caller/callee
1931 /// calling conventions match, currently only fastcc supports tail calls, and
1932 /// the function CALL is immediatly followed by a RET.
1934 PPCTargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1936 SelectionDAG& DAG) const {
1937 // Variable argument functions are not supported.
1938 if (!PerformTailCallOpt || TheCall->isVarArg())
1941 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1942 MachineFunction &MF = DAG.getMachineFunction();
1943 unsigned CallerCC = MF.getFunction()->getCallingConv();
1944 unsigned CalleeCC = TheCall->getCallingConv();
1945 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1946 // Functions containing by val parameters are not supported.
1947 for (unsigned i = 0; i != TheCall->getNumArgs(); i++) {
1948 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1949 if (Flags.isByVal()) return false;
1952 SDValue Callee = TheCall->getCallee();
1953 // Non PIC/GOT tail calls are supported.
1954 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1957 // At the moment we can only do local tail calls (in same module, hidden
1958 // or protected) if we are generating PIC.
1959 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1960 return G->getGlobal()->hasHiddenVisibility()
1961 || G->getGlobal()->hasProtectedVisibility();
1968 /// isCallCompatibleAddress - Return the immediate to use if the specified
1969 /// 32-bit value is representable in the immediate field of a BxA instruction.
1970 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
1971 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1974 int Addr = C->getZExtValue();
1975 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1976 (Addr << 6 >> 6) != Addr)
1977 return 0; // Top 6 bits have to be sext of immediate.
1979 return DAG.getConstant((int)C->getZExtValue() >> 2,
1980 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
1985 struct TailCallArgumentInfo {
1990 TailCallArgumentInfo() : FrameIdx(0) {}
1995 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
1997 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
1999 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2000 SmallVector<SDValue, 8> &MemOpChains,
2002 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2003 SDValue Arg = TailCallArgs[i].Arg;
2004 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2005 int FI = TailCallArgs[i].FrameIdx;
2006 // Store relative to framepointer.
2007 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2008 PseudoSourceValue::getFixedStack(FI),
2013 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2014 /// the appropriate stack slot for the tail call optimized function call.
2015 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2016 MachineFunction &MF,
2025 // Calculate the new stack slot for the return address.
2026 int SlotSize = isPPC64 ? 8 : 4;
2027 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2029 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2031 int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
2033 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
2035 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2036 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2037 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2038 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
2039 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2040 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2041 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
2046 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2047 /// the position of the argument.
2049 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2050 SDValue Arg, int SPDiff, unsigned ArgOffset,
2051 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2052 int Offset = ArgOffset + SPDiff;
2053 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2054 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
2055 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2056 SDValue FIN = DAG.getFrameIndex(FI, VT);
2057 TailCallArgumentInfo Info;
2059 Info.FrameIdxOp = FIN;
2061 TailCallArguments.push_back(Info);
2064 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2065 /// stack slot. Returns the chain as result and the loaded frame pointers in
2066 /// LROpOut/FPOpout. Used when tail calling.
2067 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2074 // Load the LR and FP stack slot for later adjusting.
2075 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2076 LROpOut = getReturnAddrFrameIndex(DAG);
2077 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
2078 Chain = SDValue(LROpOut.getNode(), 1);
2079 FPOpOut = getFramePointerFrameIndex(DAG);
2080 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
2081 Chain = SDValue(FPOpOut.getNode(), 1);
2086 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2087 /// by "Src" to address "Dst" of size "Size". Alignment information is
2088 /// specified by the specific parameter attribute. The copy will be passed as
2089 /// a byval function parameter.
2090 /// Sometimes what we are copying is the end of a larger object, the part that
2091 /// does not fit in registers.
2093 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2094 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2095 unsigned Size, DebugLoc dl) {
2096 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
2097 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2098 false, NULL, 0, NULL, 0);
2101 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2104 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2105 SDValue Arg, SDValue PtrOff, int SPDiff,
2106 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2107 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2108 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2110 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2115 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2117 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2118 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2119 DAG.getConstant(ArgOffset, PtrVT));
2121 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
2122 // Calculate and remember argument location.
2123 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2127 SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
2128 const PPCSubtarget &Subtarget,
2129 TargetMachine &TM) {
2130 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
2131 SDValue Chain = TheCall->getChain();
2132 bool isVarArg = TheCall->isVarArg();
2133 unsigned CC = TheCall->getCallingConv();
2134 bool isTailCall = TheCall->isTailCall()
2135 && CC == CallingConv::Fast && PerformTailCallOpt;
2136 SDValue Callee = TheCall->getCallee();
2137 unsigned NumOps = TheCall->getNumArgs();
2138 DebugLoc dl = TheCall->getDebugLoc();
2140 bool isMachoABI = Subtarget.isMachoABI();
2141 bool isELF32_ABI = Subtarget.isELF32_ABI();
2143 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2144 bool isPPC64 = PtrVT == MVT::i64;
2145 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2147 MachineFunction &MF = DAG.getMachineFunction();
2149 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
2150 // SelectExpr to use to put the arguments in the appropriate registers.
2151 std::vector<SDValue> args_to_use;
2153 // Mark this function as potentially containing a function that contains a
2154 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2155 // and restoring the callers stack pointer in this functions epilog. This is
2156 // done because by tail calling the called function might overwrite the value
2157 // in this function's (MF) stack pointer stack slot 0(SP).
2158 if (PerformTailCallOpt && CC==CallingConv::Fast)
2159 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2161 unsigned nAltivecParamsAtEnd = 0;
2163 // Count how many bytes are to be pushed on the stack, including the linkage
2164 // area, and parameter passing area. We start with 24/48 bytes, which is
2165 // prereserved space for [SP][CR][LR][3 x unused].
2167 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC,
2168 TheCall, nAltivecParamsAtEnd);
2170 // Calculate by how many bytes the stack has to be adjusted in case of tail
2171 // call optimization.
2172 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2174 // Adjust the stack pointer for the new arguments...
2175 // These operations are automatically eliminated by the prolog/epilog pass
2176 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2177 SDValue CallSeqStart = Chain;
2179 // Load the return address and frame pointer so it can be move somewhere else
2182 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
2184 // Set up a copy of the stack pointer for use loading and storing any
2185 // arguments that may not fit in the registers available for argument
2189 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2191 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2193 // Figure out which arguments are going to go in registers, and which in
2194 // memory. Also, if this is a vararg function, floating point operations
2195 // must be stored to our stack, and loaded into integer regs as well, if
2196 // any integer regs are available for argument passing.
2197 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
2198 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2200 static const unsigned GPR_32[] = { // 32-bit registers.
2201 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2202 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2204 static const unsigned GPR_64[] = { // 64-bit registers.
2205 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2206 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2208 static const unsigned *FPR = GetFPR(Subtarget);
2210 static const unsigned VR[] = {
2211 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2212 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2214 const unsigned NumGPRs = array_lengthof(GPR_32);
2215 const unsigned NumFPRs = isMachoABI ? 13 : 8;
2216 const unsigned NumVRs = array_lengthof( VR);
2218 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2220 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
2221 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2223 SmallVector<SDValue, 8> MemOpChains;
2224 for (unsigned i = 0; i != NumOps; ++i) {
2226 SDValue Arg = TheCall->getArg(i);
2227 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2228 // See if next argument requires stack alignment in ELF
2229 bool Align = Flags.isSplit();
2231 // PtrOff will be used to store the current argument to the stack if a
2232 // register cannot be found for it.
2235 // Stack align in ELF 32
2236 if (isELF32_ABI && Align)
2237 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
2238 StackPtr.getValueType());
2240 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2242 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
2244 // On PPC64, promote integers to 64-bit values.
2245 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2246 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2247 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2248 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
2251 // FIXME Elf untested, what are alignment rules?
2252 // FIXME memcpy is used way more than necessary. Correctness first.
2253 if (Flags.isByVal()) {
2254 unsigned Size = Flags.getByValSize();
2255 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2256 if (Size==1 || Size==2) {
2257 // Very small objects are passed right-justified.
2258 // Everything else is passed left-justified.
2259 MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2260 if (GPR_idx != NumGPRs) {
2261 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
2263 MemOpChains.push_back(Load.getValue(1));
2264 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2266 ArgOffset += PtrByteSize;
2268 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2269 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
2270 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2271 CallSeqStart.getNode()->getOperand(0),
2272 Flags, DAG, Size, dl);
2273 // This must go outside the CALLSEQ_START..END.
2274 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2275 CallSeqStart.getNode()->getOperand(1));
2276 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2277 NewCallSeqStart.getNode());
2278 Chain = CallSeqStart = NewCallSeqStart;
2279 ArgOffset += PtrByteSize;
2283 // Copy entire object into memory. There are cases where gcc-generated
2284 // code assumes it is there, even if it could be put entirely into
2285 // registers. (This is not what the doc says.)
2286 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2287 CallSeqStart.getNode()->getOperand(0),
2288 Flags, DAG, Size, dl);
2289 // This must go outside the CALLSEQ_START..END.
2290 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2291 CallSeqStart.getNode()->getOperand(1));
2292 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2293 Chain = CallSeqStart = NewCallSeqStart;
2294 // And copy the pieces of it that fit into registers.
2295 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2296 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
2297 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2298 if (GPR_idx != NumGPRs) {
2299 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
2300 MemOpChains.push_back(Load.getValue(1));
2301 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2303 ArgOffset += PtrByteSize;
2305 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2312 switch (Arg.getValueType().getSimpleVT()) {
2313 default: assert(0 && "Unexpected ValueType for argument!");
2316 // Double word align in ELF
2317 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2318 if (GPR_idx != NumGPRs) {
2319 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2321 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2322 isPPC64, isTailCall, false, MemOpChains,
2323 TailCallArguments, dl);
2326 if (inMem || isMachoABI) {
2327 // Stack align in ELF
2328 if (isELF32_ABI && Align)
2329 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2331 ArgOffset += PtrByteSize;
2336 if (FPR_idx != NumFPRs) {
2337 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
2340 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2341 MemOpChains.push_back(Store);
2343 // Float varargs are always shadowed in available integer registers
2344 if (GPR_idx != NumGPRs) {
2345 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2346 MemOpChains.push_back(Load.getValue(1));
2347 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2350 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
2351 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
2352 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
2353 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2354 MemOpChains.push_back(Load.getValue(1));
2355 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2359 // If we have any FPRs remaining, we may also have GPRs remaining.
2360 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2363 if (GPR_idx != NumGPRs)
2365 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
2366 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
2371 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2372 isPPC64, isTailCall, false, MemOpChains,
2373 TailCallArguments, dl);
2376 if (inMem || isMachoABI) {
2377 // Stack align in ELF
2378 if (isELF32_ABI && Align)
2379 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2383 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
2391 // These go aligned on the stack, or in the corresponding R registers
2392 // when within range. The Darwin PPC ABI doc claims they also go in
2393 // V registers; in fact gcc does this only for arguments that are
2394 // prototyped, not for those that match the ... We do it for all
2395 // arguments, seems to work.
2396 while (ArgOffset % 16 !=0) {
2397 ArgOffset += PtrByteSize;
2398 if (GPR_idx != NumGPRs)
2401 // We could elide this store in the case where the object fits
2402 // entirely in R registers. Maybe later.
2403 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2404 DAG.getConstant(ArgOffset, PtrVT));
2405 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2406 MemOpChains.push_back(Store);
2407 if (VR_idx != NumVRs) {
2408 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
2409 MemOpChains.push_back(Load.getValue(1));
2410 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
2413 for (unsigned i=0; i<16; i+=PtrByteSize) {
2414 if (GPR_idx == NumGPRs)
2416 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
2417 DAG.getConstant(i, PtrVT));
2418 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
2419 MemOpChains.push_back(Load.getValue(1));
2420 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2425 // Non-varargs Altivec params generally go in registers, but have
2426 // stack space allocated at the end.
2427 if (VR_idx != NumVRs) {
2428 // Doesn't have GPR space allocated.
2429 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
2430 } else if (nAltivecParamsAtEnd==0) {
2431 // We are emitting Altivec params in order.
2432 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2433 isPPC64, isTailCall, true, MemOpChains,
2434 TailCallArguments, dl);
2440 // If all Altivec parameters fit in registers, as they usually do,
2441 // they get stack space following the non-Altivec parameters. We
2442 // don't track this here because nobody below needs it.
2443 // If there are more Altivec parameters than fit in registers emit
2445 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
2447 // Offset is aligned; skip 1st 12 params which go in V registers.
2448 ArgOffset = ((ArgOffset+15)/16)*16;
2450 for (unsigned i = 0; i != NumOps; ++i) {
2451 SDValue Arg = TheCall->getArg(i);
2452 MVT ArgType = Arg.getValueType();
2453 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
2454 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
2457 // We are emitting Altivec params in order.
2458 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2459 isPPC64, isTailCall, true, MemOpChains,
2460 TailCallArguments, dl);
2467 if (!MemOpChains.empty())
2468 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2469 &MemOpChains[0], MemOpChains.size());
2471 // Build a sequence of copy-to-reg nodes chained together with token chain
2472 // and flag operands which copy the outgoing args into the appropriate regs.
2474 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2475 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2476 RegsToPass[i].second, InFlag);
2477 InFlag = Chain.getValue(1);
2480 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
2481 if (isVarArg && isELF32_ABI) {
2482 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
2483 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2484 InFlag = Chain.getValue(1);
2487 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2488 // might overwrite each other in case of tail call optimization.
2490 SmallVector<SDValue, 8> MemOpChains2;
2491 // Do not flag preceeding copytoreg stuff together with the following stuff.
2493 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2495 if (!MemOpChains2.empty())
2496 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2497 &MemOpChains2[0], MemOpChains2.size());
2499 // Store the return address to the appropriate stack slot.
2500 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2501 isPPC64, isMachoABI, dl);
2504 // Emit callseq_end just before tailcall node.
2506 SmallVector<SDValue, 8> CallSeqOps;
2507 SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2508 CallSeqOps.push_back(Chain);
2509 CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes, true));
2510 CallSeqOps.push_back(DAG.getIntPtrConstant(0, true));
2511 if (InFlag.getNode())
2512 CallSeqOps.push_back(InFlag);
2513 Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
2515 InFlag = Chain.getValue(1);
2518 std::vector<MVT> NodeTys;
2519 NodeTys.push_back(MVT::Other); // Returns a chain
2520 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2522 SmallVector<SDValue, 8> Ops;
2523 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
2525 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2526 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2527 // node so that legalize doesn't hack it.
2528 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2529 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2530 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2531 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2532 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2533 // If this is an absolute destination address, use the munged value.
2534 Callee = SDValue(Dest, 0);
2536 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2537 // to do the call, we can't use PPCISD::CALL.
2538 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2539 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2540 2 + (InFlag.getNode() != 0));
2541 InFlag = Chain.getValue(1);
2543 // Copy the callee address into R12/X12 on darwin.
2545 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
2546 Chain = DAG.getCopyToReg(Chain, dl, Reg, Callee, InFlag);
2547 InFlag = Chain.getValue(1);
2551 NodeTys.push_back(MVT::Other);
2552 NodeTys.push_back(MVT::Flag);
2553 Ops.push_back(Chain);
2554 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
2556 // Add CTR register as callee so a bctr can be emitted later.
2558 Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
2561 // If this is a direct call, pass the chain and the callee.
2562 if (Callee.getNode()) {
2563 Ops.push_back(Chain);
2564 Ops.push_back(Callee);
2566 // If this is a tail call add stack pointer delta.
2568 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2570 // Add argument registers to the end of the list so that they are known live
2572 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2573 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2574 RegsToPass[i].second.getValueType()));
2576 // When performing tail call optimization the callee pops its arguments off
2577 // the stack. Account for this here so these bytes can be pushed back on in
2578 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2579 int BytesCalleePops =
2580 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2582 if (InFlag.getNode())
2583 Ops.push_back(InFlag);
2587 assert(InFlag.getNode() &&
2588 "Flag must be set. Depend on flag being set in LowerRET");
2589 Chain = DAG.getNode(PPCISD::TAILCALL, dl,
2590 TheCall->getVTList(), &Ops[0], Ops.size());
2591 return SDValue(Chain.getNode(), Op.getResNo());
2594 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2595 InFlag = Chain.getValue(1);
2597 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2598 DAG.getIntPtrConstant(BytesCalleePops, true),
2600 if (TheCall->getValueType(0) != MVT::Other)
2601 InFlag = Chain.getValue(1);
2603 SmallVector<SDValue, 16> ResultVals;
2604 SmallVector<CCValAssign, 16> RVLocs;
2605 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
2606 CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
2607 CCInfo.AnalyzeCallResult(TheCall, RetCC_PPC);
2609 // Copy all of the result registers out of their specified physreg.
2610 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2611 CCValAssign &VA = RVLocs[i];
2612 MVT VT = VA.getValVT();
2613 assert(VA.isRegLoc() && "Can only return in registers!");
2614 Chain = DAG.getCopyFromReg(Chain, dl,
2615 VA.getLocReg(), VT, InFlag).getValue(1);
2616 ResultVals.push_back(Chain.getValue(0));
2617 InFlag = Chain.getValue(2);
2620 // If the function returns void, just return the chain.
2624 // Otherwise, merge everything together with a MERGE_VALUES node.
2625 ResultVals.push_back(Chain);
2626 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
2627 &ResultVals[0], ResultVals.size());
2628 return Res.getValue(Op.getResNo());
2631 SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
2632 TargetMachine &TM) {
2633 SmallVector<CCValAssign, 16> RVLocs;
2634 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
2635 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
2636 DebugLoc dl = Op.getDebugLoc();
2637 CCState CCInfo(CC, isVarArg, TM, RVLocs);
2638 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
2640 // If this is the first return lowered for this function, add the regs to the
2641 // liveout set for the function.
2642 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2643 for (unsigned i = 0; i != RVLocs.size(); ++i)
2644 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2647 SDValue Chain = Op.getOperand(0);
2649 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
2650 if (Chain.getOpcode() == PPCISD::TAILCALL) {
2651 SDValue TailCall = Chain;
2652 SDValue TargetAddress = TailCall.getOperand(1);
2653 SDValue StackAdjustment = TailCall.getOperand(2);
2655 assert(((TargetAddress.getOpcode() == ISD::Register &&
2656 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
2657 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
2658 TargetAddress.getOpcode() == ISD::TargetGlobalAddress ||
2659 isa<ConstantSDNode>(TargetAddress)) &&
2660 "Expecting an global address, external symbol, absolute value or register");
2662 assert(StackAdjustment.getOpcode() == ISD::Constant &&
2663 "Expecting a const value");
2665 SmallVector<SDValue,8> Operands;
2666 Operands.push_back(Chain.getOperand(0));
2667 Operands.push_back(TargetAddress);
2668 Operands.push_back(StackAdjustment);
2669 // Copy registers used by the call. Last operand is a flag so it is not
2671 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
2672 Operands.push_back(Chain.getOperand(i));
2674 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Operands[0],
2680 // Copy the result values into the output registers.
2681 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2682 CCValAssign &VA = RVLocs[i];
2683 assert(VA.isRegLoc() && "Can only return in registers!");
2684 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2685 Op.getOperand(i*2+1), Flag);
2686 Flag = Chain.getValue(1);
2690 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
2692 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
2695 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
2696 const PPCSubtarget &Subtarget) {
2697 // When we pop the dynamic allocation we need to restore the SP link.
2698 DebugLoc dl = Op.getNode()->getDebugLoc();
2700 // Get the corect type for pointers.
2701 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2703 // Construct the stack pointer operand.
2704 bool IsPPC64 = Subtarget.isPPC64();
2705 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2706 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
2708 // Get the operands for the STACKRESTORE.
2709 SDValue Chain = Op.getOperand(0);
2710 SDValue SaveSP = Op.getOperand(1);
2712 // Load the old link SP.
2713 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
2715 // Restore the stack pointer.
2716 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
2718 // Store the old link SP.
2719 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
2725 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
2726 MachineFunction &MF = DAG.getMachineFunction();
2727 bool IsPPC64 = PPCSubTarget.isPPC64();
2728 bool isMachoABI = PPCSubTarget.isMachoABI();
2729 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2731 // Get current frame pointer save index. The users of this index will be
2732 // primarily DYNALLOC instructions.
2733 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2734 int RASI = FI->getReturnAddrSaveIndex();
2736 // If the frame pointer save index hasn't been defined yet.
2738 // Find out what the fix offset of the frame pointer save area.
2739 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI);
2740 // Allocate the frame index for frame pointer save area.
2741 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
2743 FI->setReturnAddrSaveIndex(RASI);
2745 return DAG.getFrameIndex(RASI, PtrVT);
2749 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
2750 MachineFunction &MF = DAG.getMachineFunction();
2751 bool IsPPC64 = PPCSubTarget.isPPC64();
2752 bool isMachoABI = PPCSubTarget.isMachoABI();
2753 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2755 // Get current frame pointer save index. The users of this index will be
2756 // primarily DYNALLOC instructions.
2757 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2758 int FPSI = FI->getFramePointerSaveIndex();
2760 // If the frame pointer save index hasn't been defined yet.
2762 // Find out what the fix offset of the frame pointer save area.
2763 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2765 // Allocate the frame index for frame pointer save area.
2766 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
2768 FI->setFramePointerSaveIndex(FPSI);
2770 return DAG.getFrameIndex(FPSI, PtrVT);
2773 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
2775 const PPCSubtarget &Subtarget) {
2777 SDValue Chain = Op.getOperand(0);
2778 SDValue Size = Op.getOperand(1);
2779 DebugLoc dl = Op.getDebugLoc();
2781 // Get the corect type for pointers.
2782 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2784 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
2785 DAG.getConstant(0, PtrVT), Size);
2786 // Construct a node for the frame pointer save index.
2787 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
2788 // Build a DYNALLOC node.
2789 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
2790 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2791 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
2794 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2796 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
2797 // Not FP? Not a fsel.
2798 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
2799 !Op.getOperand(2).getValueType().isFloatingPoint())
2802 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2804 // Cannot handle SETEQ/SETNE.
2805 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDValue();
2807 MVT ResVT = Op.getValueType();
2808 MVT CmpVT = Op.getOperand(0).getValueType();
2809 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2810 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
2811 DebugLoc dl = Op.getDebugLoc();
2813 // If the RHS of the comparison is a 0.0, we don't need to do the
2814 // subtraction at all.
2815 if (isFloatingPointZero(RHS))
2817 default: break; // SETUO etc aren't handled by fsel.
2820 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2823 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2824 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
2825 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
2828 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2831 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2832 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
2833 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
2834 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
2839 default: break; // SETUO etc aren't handled by fsel.
2842 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
2843 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2844 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
2845 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
2848 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
2849 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2850 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
2851 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
2854 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
2855 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2856 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
2857 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
2860 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
2861 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2862 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
2863 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
2868 // FIXME: Split this code up when LegalizeDAGTypes lands.
2869 SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2871 assert(Op.getOperand(0).getValueType().isFloatingPoint());
2872 SDValue Src = Op.getOperand(0);
2873 if (Src.getValueType() == MVT::f32)
2874 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
2877 switch (Op.getValueType().getSimpleVT()) {
2878 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2880 Tmp = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Src);
2883 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
2887 // Convert the FP value to an int value through memory.
2888 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
2890 // Emit a store to the stack slot.
2891 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
2893 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2895 if (Op.getValueType() == MVT::i32)
2896 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
2897 DAG.getConstant(4, FIPtr.getValueType()));
2898 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
2901 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2902 DebugLoc dl = Op.getNode()->getDebugLoc();
2903 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
2904 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
2907 if (Op.getOperand(0).getValueType() == MVT::i64) {
2908 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
2909 MVT::f64, Op.getOperand(0));
2910 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
2911 if (Op.getValueType() == MVT::f32)
2912 FP = DAG.getNode(ISD::FP_ROUND, dl,
2913 MVT::f32, FP, DAG.getIntPtrConstant(0));
2917 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2918 "Unhandled SINT_TO_FP type in custom expander!");
2919 // Since we only generate this in 64-bit mode, we can take advantage of
2920 // 64-bit registers. In particular, sign extend the input value into the
2921 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2922 // then lfd it and fcfid it.
2923 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2924 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2925 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2926 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2928 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
2931 // STD the extended value into the stack slot.
2932 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
2933 MachineMemOperand::MOStore, 0, 8, 8);
2934 SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other,
2935 DAG.getEntryNode(), Ext64, FIdx,
2936 DAG.getMemOperand(MO));
2937 // Load the value as a double.
2938 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
2940 // FCFID it and return it.
2941 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
2942 if (Op.getValueType() == MVT::f32)
2943 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
2947 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
2948 DebugLoc dl = Op.getNode()->getDebugLoc();
2950 The rounding mode is in bits 30:31 of FPSR, and has the following
2957 FLT_ROUNDS, on the other hand, expects the following:
2964 To perform the conversion, we do:
2965 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2968 MachineFunction &MF = DAG.getMachineFunction();
2969 MVT VT = Op.getValueType();
2970 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2971 std::vector<MVT> NodeTys;
2972 SDValue MFFSreg, InFlag;
2974 // Save FP Control Word to register
2975 NodeTys.push_back(MVT::f64); // return register
2976 NodeTys.push_back(MVT::Flag); // unused in this context
2977 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
2979 // Save FP register to stack slot
2980 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2981 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2982 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
2983 StackSlot, NULL, 0);
2985 // Load FP Control Word from low 32 bits of stack slot.
2986 SDValue Four = DAG.getConstant(4, PtrVT);
2987 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
2988 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
2990 // Transform as necessary
2992 DAG.getNode(ISD::AND, dl, MVT::i32,
2993 CWD, DAG.getConstant(3, MVT::i32));
2995 DAG.getNode(ISD::SRL, dl, MVT::i32,
2996 DAG.getNode(ISD::AND, dl, MVT::i32,
2997 DAG.getNode(ISD::XOR, dl, MVT::i32,
2998 CWD, DAG.getConstant(3, MVT::i32)),
2999 DAG.getConstant(3, MVT::i32)),
3000 DAG.getConstant(1, MVT::i32));
3003 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3005 return DAG.getNode((VT.getSizeInBits() < 16 ?
3006 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3009 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
3010 MVT VT = Op.getValueType();
3011 unsigned BitWidth = VT.getSizeInBits();
3012 DebugLoc dl = Op.getDebugLoc();
3013 assert(Op.getNumOperands() == 3 &&
3014 VT == Op.getOperand(1).getValueType() &&
3017 // Expand into a bunch of logical ops. Note that these ops
3018 // depend on the PPC behavior for oversized shift amounts.
3019 SDValue Lo = Op.getOperand(0);
3020 SDValue Hi = Op.getOperand(1);
3021 SDValue Amt = Op.getOperand(2);
3022 MVT AmtVT = Amt.getValueType();
3024 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3025 DAG.getConstant(BitWidth, AmtVT), Amt);
3026 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3027 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3028 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3029 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3030 DAG.getConstant(-BitWidth, AmtVT));
3031 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3032 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3033 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3034 SDValue OutOps[] = { OutLo, OutHi };
3035 return DAG.getMergeValues(OutOps, 2, dl);
3038 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3039 MVT VT = Op.getValueType();
3040 DebugLoc dl = Op.getDebugLoc();
3041 unsigned BitWidth = VT.getSizeInBits();
3042 assert(Op.getNumOperands() == 3 &&
3043 VT == Op.getOperand(1).getValueType() &&
3046 // Expand into a bunch of logical ops. Note that these ops
3047 // depend on the PPC behavior for oversized shift amounts.
3048 SDValue Lo = Op.getOperand(0);
3049 SDValue Hi = Op.getOperand(1);
3050 SDValue Amt = Op.getOperand(2);
3051 MVT AmtVT = Amt.getValueType();
3053 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3054 DAG.getConstant(BitWidth, AmtVT), Amt);
3055 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3056 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3057 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3058 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3059 DAG.getConstant(-BitWidth, AmtVT));
3060 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3061 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3062 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3063 SDValue OutOps[] = { OutLo, OutHi };
3064 return DAG.getMergeValues(OutOps, 2, dl);
3067 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3068 DebugLoc dl = Op.getNode()->getDebugLoc();
3069 MVT VT = Op.getValueType();
3070 unsigned BitWidth = VT.getSizeInBits();
3071 assert(Op.getNumOperands() == 3 &&
3072 VT == Op.getOperand(1).getValueType() &&
3075 // Expand into a bunch of logical ops, followed by a select_cc.
3076 SDValue Lo = Op.getOperand(0);
3077 SDValue Hi = Op.getOperand(1);
3078 SDValue Amt = Op.getOperand(2);
3079 MVT AmtVT = Amt.getValueType();
3081 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3082 DAG.getConstant(BitWidth, AmtVT), Amt);
3083 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3084 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3085 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3086 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3087 DAG.getConstant(-BitWidth, AmtVT));
3088 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3089 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3090 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3091 Tmp4, Tmp6, ISD::SETLE);
3092 SDValue OutOps[] = { OutLo, OutHi };
3093 return DAG.getMergeValues(OutOps, 2, dl);
3096 //===----------------------------------------------------------------------===//
3097 // Vector related lowering.
3100 // If this is a vector of constants or undefs, get the bits. A bit in
3101 // UndefBits is set if the corresponding element of the vector is an
3102 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3103 // zero. Return true if this is not an array of constants, false if it is.
3105 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
3106 uint64_t UndefBits[2]) {
3107 // Start with zero'd results.
3108 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
3110 unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
3111 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3112 SDValue OpVal = BV->getOperand(i);
3114 unsigned PartNo = i >= e/2; // In the upper 128 bits?
3115 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
3117 uint64_t EltBits = 0;
3118 if (OpVal.getOpcode() == ISD::UNDEF) {
3119 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
3120 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
3122 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
3123 EltBits = CN->getZExtValue() & (~0U >> (32-EltBitSize));
3124 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
3125 assert(CN->getValueType(0) == MVT::f32 &&
3126 "Only one legal FP vector type!");
3127 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
3129 // Nonconstant element.
3133 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
3136 //printf("%llx %llx %llx %llx\n",
3137 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
3141 // If this is a splat (repetition) of a value across the whole vector, return
3142 // the smallest size that splats it. For example, "0x01010101010101..." is a
3143 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3144 // SplatSize = 1 byte.
3145 static bool isConstantSplat(const uint64_t Bits128[2],
3146 const uint64_t Undef128[2],
3147 unsigned &SplatBits, unsigned &SplatUndef,
3148 unsigned &SplatSize) {
3150 // Don't let undefs prevent splats from matching. See if the top 64-bits are
3151 // the same as the lower 64-bits, ignoring undefs.
3152 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
3153 return false; // Can't be a splat if two pieces don't match.
3155 uint64_t Bits64 = Bits128[0] | Bits128[1];
3156 uint64_t Undef64 = Undef128[0] & Undef128[1];
3158 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
3160 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
3161 return false; // Can't be a splat if two pieces don't match.
3163 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
3164 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
3166 // If the top 16-bits are different than the lower 16-bits, ignoring
3167 // undefs, we have an i32 splat.
3168 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
3170 SplatUndef = Undef32;
3175 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
3176 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
3178 // If the top 8-bits are different than the lower 8-bits, ignoring
3179 // undefs, we have an i16 splat.
3180 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
3182 SplatUndef = Undef16;
3187 // Otherwise, we have an 8-bit splat.
3188 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
3189 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
3194 /// BuildSplatI - Build a canonical splati of Val with an element size of
3195 /// SplatSize. Cast the result to VT.
3196 static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT,
3197 SelectionDAG &DAG, DebugLoc dl) {
3198 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3200 static const MVT VTys[] = { // canonical VT to use for each size.
3201 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3204 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3206 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3210 MVT CanonicalVT = VTys[SplatSize-1];
3212 // Build a canonical splat for this value.
3213 SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
3214 SmallVector<SDValue, 8> Ops;
3215 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3216 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3217 &Ops[0], Ops.size());
3218 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3221 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3222 /// specified intrinsic ID.
3223 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3224 SelectionDAG &DAG, DebugLoc dl,
3225 MVT DestVT = MVT::Other) {
3226 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3227 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3228 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3231 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3232 /// specified intrinsic ID.
3233 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3234 SDValue Op2, SelectionDAG &DAG,
3235 DebugLoc dl, MVT DestVT = MVT::Other) {
3236 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3237 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3238 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3242 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3243 /// amount. The result has the specified value type.
3244 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3245 MVT VT, SelectionDAG &DAG, DebugLoc dl) {
3246 // Force LHS/RHS to be the right type.
3247 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3248 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3251 for (unsigned i = 0; i != 16; ++i)
3252 Ops[i] = DAG.getConstant(i+Amt, MVT::i8);
3253 SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, LHS, RHS,
3254 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops,16));
3255 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3258 // If this is a case we can't handle, return null and let the default
3259 // expansion code take care of it. If we CAN select this case, and if it
3260 // selects to a single instruction, return Op. Otherwise, if we can codegen
3261 // this case more efficiently than a constant pool load, lower it to the
3262 // sequence of ops that should be used.
3263 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3264 SelectionDAG &DAG) {
3265 // If this is a vector of constants or undefs, get the bits. A bit in
3266 // UndefBits is set if the corresponding element of the vector is an
3267 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3269 uint64_t VectorBits[2];
3270 uint64_t UndefBits[2];
3271 DebugLoc dl = Op.getDebugLoc();
3272 if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits))
3273 return SDValue(); // Not a constant vector.
3275 // If this is a splat (repetition) of a value across the whole vector, return
3276 // the smallest size that splats it. For example, "0x01010101010101..." is a
3277 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3278 // SplatSize = 1 byte.
3279 unsigned SplatBits, SplatUndef, SplatSize;
3280 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
3281 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
3283 // First, handle single instruction cases.
3286 if (SplatBits == 0) {
3287 // Canonicalize all zero vectors to be v4i32.
3288 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3289 SDValue Z = DAG.getConstant(0, MVT::i32);
3290 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3291 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3296 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3297 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
3298 if (SextVal >= -16 && SextVal <= 15)
3299 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3302 // Two instruction sequences.
3304 // If this value is in the range [-32,30] and is even, use:
3305 // tmp = VSPLTI[bhw], result = add tmp, tmp
3306 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3307 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3308 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3309 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3312 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3313 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3315 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3316 // Make -1 and vspltisw -1:
3317 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3319 // Make the VSLW intrinsic, computing 0x8000_0000.
3320 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3323 // xor by OnesV to invert it.
3324 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3325 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3328 // Check to see if this is a wide variety of vsplti*, binop self cases.
3329 unsigned SplatBitSize = SplatSize*8;
3330 static const signed char SplatCsts[] = {
3331 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3332 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3335 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3336 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3337 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3338 int i = SplatCsts[idx];
3340 // Figure out what shift amount will be used by altivec if shifted by i in
3342 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3344 // vsplti + shl self.
3345 if (SextVal == (i << (int)TypeShiftAmt)) {
3346 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3347 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3348 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3349 Intrinsic::ppc_altivec_vslw
3351 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3352 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3355 // vsplti + srl self.
3356 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3357 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3358 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3359 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3360 Intrinsic::ppc_altivec_vsrw
3362 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3363 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3366 // vsplti + sra self.
3367 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3368 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3369 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3370 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3371 Intrinsic::ppc_altivec_vsraw
3373 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3374 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3377 // vsplti + rol self.
3378 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3379 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3380 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3381 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3382 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3383 Intrinsic::ppc_altivec_vrlw
3385 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3386 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3389 // t = vsplti c, result = vsldoi t, t, 1
3390 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3391 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3392 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3394 // t = vsplti c, result = vsldoi t, t, 2
3395 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3396 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3397 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3399 // t = vsplti c, result = vsldoi t, t, 3
3400 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3401 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3402 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3406 // Three instruction sequences.
3408 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3409 if (SextVal >= 0 && SextVal <= 31) {
3410 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3411 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3412 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3413 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3415 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3416 if (SextVal >= -31 && SextVal <= 0) {
3417 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3418 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3419 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3420 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3427 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3428 /// the specified operations to build the shuffle.
3429 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3430 SDValue RHS, SelectionDAG &DAG,
3432 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3433 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3434 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3437 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3449 if (OpNum == OP_COPY) {
3450 if (LHSID == (1*9+2)*9+3) return LHS;
3451 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3455 SDValue OpLHS, OpRHS;
3456 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3457 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3459 unsigned ShufIdxs[16];
3461 default: assert(0 && "Unknown i32 permute!");
3463 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3464 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3465 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3466 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3469 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3470 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3471 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3472 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3475 for (unsigned i = 0; i != 16; ++i)
3476 ShufIdxs[i] = (i&3)+0;
3479 for (unsigned i = 0; i != 16; ++i)
3480 ShufIdxs[i] = (i&3)+4;
3483 for (unsigned i = 0; i != 16; ++i)
3484 ShufIdxs[i] = (i&3)+8;
3487 for (unsigned i = 0; i != 16; ++i)
3488 ShufIdxs[i] = (i&3)+12;
3491 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
3493 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
3495 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
3498 for (unsigned i = 0; i != 16; ++i)
3499 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
3501 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, OpLHS.getValueType(),
3503 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
3506 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3507 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3508 /// return the code it can be lowered into. Worst case, it can always be
3509 /// lowered into a vperm.
3510 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
3511 SelectionDAG &DAG) {
3512 DebugLoc dl = Op.getDebugLoc();
3513 SDValue V1 = Op.getOperand(0);
3514 SDValue V2 = Op.getOperand(1);
3515 SDValue PermMask = Op.getOperand(2);
3517 // Cases that are handled by instructions that take permute immediates
3518 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3519 // selected by the instruction selector.
3520 if (V2.getOpcode() == ISD::UNDEF) {
3521 if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) ||
3522 PPC::isSplatShuffleMask(PermMask.getNode(), 2) ||
3523 PPC::isSplatShuffleMask(PermMask.getNode(), 4) ||
3524 PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) ||
3525 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) ||
3526 PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 ||
3527 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) ||
3528 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) ||
3529 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) ||
3530 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) ||
3531 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) ||
3532 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) {
3537 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3538 // and produce a fixed permutation. If any of these match, do not lower to
3540 if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) ||
3541 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) ||
3542 PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 ||
3543 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) ||
3544 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) ||
3545 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) ||
3546 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) ||
3547 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) ||
3548 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false))
3551 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3552 // perfect shuffle table to emit an optimal matching sequence.
3553 unsigned PFIndexes[4];
3554 bool isFourElementShuffle = true;
3555 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3556 unsigned EltNo = 8; // Start out undef.
3557 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3558 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
3559 continue; // Undef, ignore it.
3561 unsigned ByteSource =
3562 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getZExtValue();
3563 if ((ByteSource & 3) != j) {
3564 isFourElementShuffle = false;
3569 EltNo = ByteSource/4;
3570 } else if (EltNo != ByteSource/4) {
3571 isFourElementShuffle = false;
3575 PFIndexes[i] = EltNo;
3578 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3579 // perfect shuffle vector to determine if it is cost effective to do this as
3580 // discrete instructions, or whether we should use a vperm.
3581 if (isFourElementShuffle) {
3582 // Compute the index in the perfect shuffle table.
3583 unsigned PFTableIndex =
3584 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3586 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3587 unsigned Cost = (PFEntry >> 30);
3589 // Determining when to avoid vperm is tricky. Many things affect the cost
3590 // of vperm, particularly how many times the perm mask needs to be computed.
3591 // For example, if the perm mask can be hoisted out of a loop or is already
3592 // used (perhaps because there are multiple permutes with the same shuffle
3593 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3594 // the loop requires an extra register.
3596 // As a compromise, we only emit discrete instructions if the shuffle can be
3597 // generated in 3 or fewer operations. When we have loop information
3598 // available, if this block is within a loop, we should avoid using vperm
3599 // for 3-operation perms and use a constant pool load instead.
3601 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3604 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3605 // vector that will get spilled to the constant pool.
3606 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3608 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3609 // that it is in input element units, not in bytes. Convert now.
3610 MVT EltVT = V1.getValueType().getVectorElementType();
3611 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
3613 SmallVector<SDValue, 16> ResultMask;
3614 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
3616 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
3619 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
3621 for (unsigned j = 0; j != BytesPerElement; ++j)
3622 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3626 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
3627 &ResultMask[0], ResultMask.size());
3628 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
3631 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3632 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3633 /// information about the intrinsic.
3634 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
3636 unsigned IntrinsicID =
3637 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
3640 switch (IntrinsicID) {
3641 default: return false;
3642 // Comparison predicates.
3643 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3644 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3645 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3646 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3647 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3648 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3649 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3650 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3651 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3652 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3653 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3654 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3655 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3657 // Normal Comparisons.
3658 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3659 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3660 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3661 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3662 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3663 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3664 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3665 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3666 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3667 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
3668 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
3669 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
3670 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3675 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3676 /// lower, do it, otherwise return null.
3677 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3678 SelectionDAG &DAG) {
3679 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3680 // opcode number of the comparison.
3681 DebugLoc dl = Op.getDebugLoc();
3684 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3685 return SDValue(); // Don't custom lower most intrinsics.
3687 // If this is a non-dot comparison, make the VCMP node and we are done.
3689 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
3690 Op.getOperand(1), Op.getOperand(2),
3691 DAG.getConstant(CompareOpc, MVT::i32));
3692 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
3695 // Create the PPCISD altivec 'dot' comparison node.
3697 Op.getOperand(2), // LHS
3698 Op.getOperand(3), // RHS
3699 DAG.getConstant(CompareOpc, MVT::i32)
3701 std::vector<MVT> VTs;
3702 VTs.push_back(Op.getOperand(2).getValueType());
3703 VTs.push_back(MVT::Flag);
3704 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
3706 // Now that we have the comparison, emit a copy from the CR to a GPR.
3707 // This is flagged to the above dot comparison.
3708 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
3709 DAG.getRegister(PPC::CR6, MVT::i32),
3710 CompNode.getValue(1));
3712 // Unpack the result based on how the target uses it.
3713 unsigned BitNo; // Bit # of CR6.
3714 bool InvertBit; // Invert result?
3715 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
3716 default: // Can't happen, don't crash on invalid number though.
3717 case 0: // Return the value of the EQ bit of CR6.
3718 BitNo = 0; InvertBit = false;
3720 case 1: // Return the inverted value of the EQ bit of CR6.
3721 BitNo = 0; InvertBit = true;
3723 case 2: // Return the value of the LT bit of CR6.
3724 BitNo = 2; InvertBit = false;
3726 case 3: // Return the inverted value of the LT bit of CR6.
3727 BitNo = 2; InvertBit = true;
3731 // Shift the bit into the low position.
3732 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
3733 DAG.getConstant(8-(3-BitNo), MVT::i32));
3735 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
3736 DAG.getConstant(1, MVT::i32));
3738 // If we are supposed to, toggle the bit.
3740 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
3741 DAG.getConstant(1, MVT::i32));
3745 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
3746 SelectionDAG &DAG) {
3747 DebugLoc dl = Op.getNode()->getDebugLoc();
3748 // Create a stack slot that is 16-byte aligned.
3749 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3750 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3751 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3752 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3754 // Store the input value into Value#0 of the stack slot.
3755 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
3756 Op.getOperand(0), FIdx, NULL, 0);
3758 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0);
3761 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
3762 DebugLoc dl = Op.getDebugLoc();
3763 if (Op.getValueType() == MVT::v4i32) {
3764 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3766 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
3767 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
3769 SDValue RHSSwap = // = vrlw RHS, 16
3770 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
3772 // Shrinkify inputs to v8i16.
3773 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
3774 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
3775 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
3777 // Low parts multiplied together, generating 32-bit results (we ignore the
3779 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3780 LHS, RHS, DAG, dl, MVT::v4i32);
3782 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3783 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
3784 // Shift the high parts up 16 bits.
3785 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
3787 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
3788 } else if (Op.getValueType() == MVT::v8i16) {
3789 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3791 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
3793 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3794 LHS, RHS, Zero, DAG, dl);
3795 } else if (Op.getValueType() == MVT::v16i8) {
3796 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3798 // Multiply the even 8-bit parts, producing 16-bit sums.
3799 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3800 LHS, RHS, DAG, dl, MVT::v8i16);
3801 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
3803 // Multiply the odd 8-bit parts, producing 16-bit sums.
3804 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3805 LHS, RHS, DAG, dl, MVT::v8i16);
3806 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
3808 // Merge the results together.
3810 for (unsigned i = 0; i != 8; ++i) {
3811 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3812 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3814 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, EvenParts, OddParts,
3815 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
3817 assert(0 && "Unknown mul to lower!");
3822 /// LowerOperation - Provide custom lowering hooks for some operations.
3824 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
3825 switch (Op.getOpcode()) {
3826 default: assert(0 && "Wasn't expecting to be able to lower this!");
3827 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3828 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3829 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3830 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3831 case ISD::SETCC: return LowerSETCC(Op, DAG);
3832 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
3834 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3835 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3838 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3839 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3841 case ISD::FORMAL_ARGUMENTS:
3842 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3843 VarArgsStackOffset, VarArgsNumGPR,
3844 VarArgsNumFPR, PPCSubTarget);
3846 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget,
3847 getTargetMachine());
3848 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3849 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3850 case ISD::DYNAMIC_STACKALLOC:
3851 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3853 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3854 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG,
3856 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3857 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3859 // Lower 64-bit shifts.
3860 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3861 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3862 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3864 // Vector-related lowering.
3865 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3866 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3867 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3868 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3869 case ISD::MUL: return LowerMUL(Op, DAG);
3871 // Frame & Return address.
3872 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3873 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3878 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
3879 SmallVectorImpl<SDValue>&Results,
3880 SelectionDAG &DAG) {
3881 DebugLoc dl = N->getDebugLoc();
3882 switch (N->getOpcode()) {
3884 assert(false && "Do not know how to custom type legalize this operation!");
3886 case ISD::FP_ROUND_INREG: {
3887 assert(N->getValueType(0) == MVT::ppcf128);
3888 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
3889 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
3890 MVT::f64, N->getOperand(0),
3891 DAG.getIntPtrConstant(0));
3892 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
3893 MVT::f64, N->getOperand(0),
3894 DAG.getIntPtrConstant(1));
3896 // This sequence changes FPSCR to do round-to-zero, adds the two halves
3897 // of the long double, and puts FPSCR back the way it was. We do not
3898 // actually model FPSCR.
3899 std::vector<MVT> NodeTys;
3900 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
3902 NodeTys.push_back(MVT::f64); // Return register
3903 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
3904 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3905 MFFSreg = Result.getValue(0);
3906 InFlag = Result.getValue(1);
3909 NodeTys.push_back(MVT::Flag); // Returns a flag
3910 Ops[0] = DAG.getConstant(31, MVT::i32);
3912 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
3913 InFlag = Result.getValue(0);
3916 NodeTys.push_back(MVT::Flag); // Returns a flag
3917 Ops[0] = DAG.getConstant(30, MVT::i32);
3919 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
3920 InFlag = Result.getValue(0);
3923 NodeTys.push_back(MVT::f64); // result of add
3924 NodeTys.push_back(MVT::Flag); // Returns a flag
3928 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
3929 FPreg = Result.getValue(0);
3930 InFlag = Result.getValue(1);
3933 NodeTys.push_back(MVT::f64);
3934 Ops[0] = DAG.getConstant(1, MVT::i32);
3938 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
3939 FPreg = Result.getValue(0);
3941 // We know the low half is about to be thrown away, so just use something
3943 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
3947 case ISD::FP_TO_SINT:
3948 Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG, dl));
3954 //===----------------------------------------------------------------------===//
3955 // Other Lowering Code
3956 //===----------------------------------------------------------------------===//
3959 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3960 bool is64bit, unsigned BinOpcode) {
3961 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3962 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3964 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3965 MachineFunction *F = BB->getParent();
3966 MachineFunction::iterator It = BB;
3969 unsigned dest = MI->getOperand(0).getReg();
3970 unsigned ptrA = MI->getOperand(1).getReg();
3971 unsigned ptrB = MI->getOperand(2).getReg();
3972 unsigned incr = MI->getOperand(3).getReg();
3974 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
3975 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
3976 F->insert(It, loopMBB);
3977 F->insert(It, exitMBB);
3978 exitMBB->transferSuccessors(BB);
3980 MachineRegisterInfo &RegInfo = F->getRegInfo();
3981 unsigned TmpReg = (!BinOpcode) ? incr :
3982 RegInfo.createVirtualRegister(
3983 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
3984 (const TargetRegisterClass *) &PPC::GPRCRegClass);
3988 // fallthrough --> loopMBB
3989 BB->addSuccessor(loopMBB);
3992 // l[wd]arx dest, ptr
3993 // add r0, dest, incr
3994 // st[wd]cx. r0, ptr
3996 // fallthrough --> exitMBB
3998 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
3999 .addReg(ptrA).addReg(ptrB);
4001 BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4002 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4003 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4004 BuildMI(BB, TII->get(PPC::BCC))
4005 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4006 BB->addSuccessor(loopMBB);
4007 BB->addSuccessor(exitMBB);
4016 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4017 MachineBasicBlock *BB,
4018 bool is8bit, // operation
4019 unsigned BinOpcode) {
4020 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4021 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4022 // In 64 bit mode we have to use 64 bits for addresses, even though the
4023 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4024 // registers without caring whether they're 32 or 64, but here we're
4025 // doing actual arithmetic on the addresses.
4026 bool is64bit = PPCSubTarget.isPPC64();
4028 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4029 MachineFunction *F = BB->getParent();
4030 MachineFunction::iterator It = BB;
4033 unsigned dest = MI->getOperand(0).getReg();
4034 unsigned ptrA = MI->getOperand(1).getReg();
4035 unsigned ptrB = MI->getOperand(2).getReg();
4036 unsigned incr = MI->getOperand(3).getReg();
4038 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4039 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4040 F->insert(It, loopMBB);
4041 F->insert(It, exitMBB);
4042 exitMBB->transferSuccessors(BB);
4044 MachineRegisterInfo &RegInfo = F->getRegInfo();
4045 const TargetRegisterClass *RC =
4046 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4047 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4048 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4049 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4050 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4051 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4052 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4053 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4054 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4055 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4056 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4057 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4058 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4060 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4064 // fallthrough --> loopMBB
4065 BB->addSuccessor(loopMBB);
4067 // The 4-byte load must be aligned, while a char or short may be
4068 // anywhere in the word. Hence all this nasty bookkeeping code.
4069 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4070 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4071 // xori shift, shift1, 24 [16]
4072 // rlwinm ptr, ptr1, 0, 0, 29
4073 // slw incr2, incr, shift
4074 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4075 // slw mask, mask2, shift
4077 // lwarx tmpDest, ptr
4078 // add tmp, tmpDest, incr2
4079 // andc tmp2, tmpDest, mask
4080 // and tmp3, tmp, mask
4081 // or tmp4, tmp3, tmp2
4084 // fallthrough --> exitMBB
4085 // srw dest, tmpDest, shift
4087 if (ptrA!=PPC::R0) {
4088 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4089 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4090 .addReg(ptrA).addReg(ptrB);
4094 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4095 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4096 BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4097 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4099 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
4100 .addReg(Ptr1Reg).addImm(0).addImm(61);
4102 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
4103 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4104 BuildMI(BB, TII->get(PPC::SLW), Incr2Reg)
4105 .addReg(incr).addReg(ShiftReg);
4107 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
4109 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
4110 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
4112 BuildMI(BB, TII->get(PPC::SLW), MaskReg)
4113 .addReg(Mask2Reg).addReg(ShiftReg);
4116 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
4117 .addReg(PPC::R0).addReg(PtrReg);
4119 BuildMI(BB, TII->get(BinOpcode), TmpReg)
4120 .addReg(Incr2Reg).addReg(TmpDestReg);
4121 BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4122 .addReg(TmpDestReg).addReg(MaskReg);
4123 BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4124 .addReg(TmpReg).addReg(MaskReg);
4125 BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4126 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4127 BuildMI(BB, TII->get(PPC::STWCX))
4128 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4129 BuildMI(BB, TII->get(PPC::BCC))
4130 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4131 BB->addSuccessor(loopMBB);
4132 BB->addSuccessor(exitMBB);
4137 BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4142 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4143 MachineBasicBlock *BB) {
4144 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4146 // To "insert" these instructions we actually have to insert their
4147 // control-flow patterns.
4148 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4149 MachineFunction::iterator It = BB;
4152 MachineFunction *F = BB->getParent();
4154 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4155 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4156 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4157 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4158 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4160 // The incoming instruction knows the destination vreg to set, the
4161 // condition code register to branch on, the true/false values to
4162 // select between, and a branch opcode to use.
4167 // cmpTY ccX, r1, r2
4169 // fallthrough --> copy0MBB
4170 MachineBasicBlock *thisMBB = BB;
4171 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4172 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4173 unsigned SelectPred = MI->getOperand(4).getImm();
4174 BuildMI(BB, TII->get(PPC::BCC))
4175 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4176 F->insert(It, copy0MBB);
4177 F->insert(It, sinkMBB);
4178 // Update machine-CFG edges by transferring all successors of the current
4179 // block to the new block which will contain the Phi node for the select.
4180 sinkMBB->transferSuccessors(BB);
4181 // Next, add the true and fallthrough blocks as its successors.
4182 BB->addSuccessor(copy0MBB);
4183 BB->addSuccessor(sinkMBB);
4186 // %FalseValue = ...
4187 // # fallthrough to sinkMBB
4190 // Update machine-CFG edges
4191 BB->addSuccessor(sinkMBB);
4194 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4197 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4198 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4199 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4201 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4202 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4203 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4204 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4205 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4206 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4207 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4208 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4210 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4211 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4212 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4213 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4214 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4215 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4216 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4217 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4219 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4220 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4221 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4222 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4223 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4224 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4225 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4226 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4228 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4229 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4230 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4231 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4232 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4233 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4234 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4235 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4237 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4238 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4239 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4240 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4241 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4242 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4243 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4244 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4246 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4247 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4248 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4249 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4250 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4251 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4252 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4253 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4255 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4256 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4257 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4258 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4259 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4260 BB = EmitAtomicBinary(MI, BB, false, 0);
4261 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4262 BB = EmitAtomicBinary(MI, BB, true, 0);
4264 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4265 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4266 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4268 unsigned dest = MI->getOperand(0).getReg();
4269 unsigned ptrA = MI->getOperand(1).getReg();
4270 unsigned ptrB = MI->getOperand(2).getReg();
4271 unsigned oldval = MI->getOperand(3).getReg();
4272 unsigned newval = MI->getOperand(4).getReg();
4274 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4275 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4276 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4277 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4278 F->insert(It, loop1MBB);
4279 F->insert(It, loop2MBB);
4280 F->insert(It, midMBB);
4281 F->insert(It, exitMBB);
4282 exitMBB->transferSuccessors(BB);
4286 // fallthrough --> loopMBB
4287 BB->addSuccessor(loop1MBB);
4290 // l[wd]arx dest, ptr
4291 // cmp[wd] dest, oldval
4294 // st[wd]cx. newval, ptr
4298 // st[wd]cx. dest, ptr
4301 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4302 .addReg(ptrA).addReg(ptrB);
4303 BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4304 .addReg(oldval).addReg(dest);
4305 BuildMI(BB, TII->get(PPC::BCC))
4306 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4307 BB->addSuccessor(loop2MBB);
4308 BB->addSuccessor(midMBB);
4311 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4312 .addReg(newval).addReg(ptrA).addReg(ptrB);
4313 BuildMI(BB, TII->get(PPC::BCC))
4314 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4315 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
4316 BB->addSuccessor(loop1MBB);
4317 BB->addSuccessor(exitMBB);
4320 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4321 .addReg(dest).addReg(ptrA).addReg(ptrB);
4322 BB->addSuccessor(exitMBB);
4327 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4328 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4329 // We must use 64-bit registers for addresses when targeting 64-bit,
4330 // since we're actually doing arithmetic on them. Other registers
4332 bool is64bit = PPCSubTarget.isPPC64();
4333 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4335 unsigned dest = MI->getOperand(0).getReg();
4336 unsigned ptrA = MI->getOperand(1).getReg();
4337 unsigned ptrB = MI->getOperand(2).getReg();
4338 unsigned oldval = MI->getOperand(3).getReg();
4339 unsigned newval = MI->getOperand(4).getReg();
4341 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4342 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4343 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4344 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4345 F->insert(It, loop1MBB);
4346 F->insert(It, loop2MBB);
4347 F->insert(It, midMBB);
4348 F->insert(It, exitMBB);
4349 exitMBB->transferSuccessors(BB);
4351 MachineRegisterInfo &RegInfo = F->getRegInfo();
4352 const TargetRegisterClass *RC =
4353 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4354 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4355 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4356 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4357 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4358 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4359 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4360 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4361 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4362 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4363 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4364 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4365 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4366 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4367 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4369 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4372 // fallthrough --> loopMBB
4373 BB->addSuccessor(loop1MBB);
4375 // The 4-byte load must be aligned, while a char or short may be
4376 // anywhere in the word. Hence all this nasty bookkeeping code.
4377 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4378 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4379 // xori shift, shift1, 24 [16]
4380 // rlwinm ptr, ptr1, 0, 0, 29
4381 // slw newval2, newval, shift
4382 // slw oldval2, oldval,shift
4383 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4384 // slw mask, mask2, shift
4385 // and newval3, newval2, mask
4386 // and oldval3, oldval2, mask
4388 // lwarx tmpDest, ptr
4389 // and tmp, tmpDest, mask
4390 // cmpw tmp, oldval3
4393 // andc tmp2, tmpDest, mask
4394 // or tmp4, tmp2, newval3
4399 // stwcx. tmpDest, ptr
4401 // srw dest, tmpDest, shift
4402 if (ptrA!=PPC::R0) {
4403 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4404 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4405 .addReg(ptrA).addReg(ptrB);
4409 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4410 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4411 BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4412 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4414 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
4415 .addReg(Ptr1Reg).addImm(0).addImm(61);
4417 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
4418 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4419 BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg)
4420 .addReg(newval).addReg(ShiftReg);
4421 BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg)
4422 .addReg(oldval).addReg(ShiftReg);
4424 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
4426 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
4427 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
4429 BuildMI(BB, TII->get(PPC::SLW), MaskReg)
4430 .addReg(Mask2Reg).addReg(ShiftReg);
4431 BuildMI(BB, TII->get(PPC::AND), NewVal3Reg)
4432 .addReg(NewVal2Reg).addReg(MaskReg);
4433 BuildMI(BB, TII->get(PPC::AND), OldVal3Reg)
4434 .addReg(OldVal2Reg).addReg(MaskReg);
4437 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
4438 .addReg(PPC::R0).addReg(PtrReg);
4439 BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg);
4440 BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0)
4441 .addReg(TmpReg).addReg(OldVal3Reg);
4442 BuildMI(BB, TII->get(PPC::BCC))
4443 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4444 BB->addSuccessor(loop2MBB);
4445 BB->addSuccessor(midMBB);
4448 BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg);
4449 BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg);
4450 BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4451 .addReg(PPC::R0).addReg(PtrReg);
4452 BuildMI(BB, TII->get(PPC::BCC))
4453 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4454 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
4455 BB->addSuccessor(loop1MBB);
4456 BB->addSuccessor(exitMBB);
4459 BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4460 .addReg(PPC::R0).addReg(PtrReg);
4461 BB->addSuccessor(exitMBB);
4466 BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4468 assert(0 && "Unexpected instr type to insert");
4471 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4475 //===----------------------------------------------------------------------===//
4476 // Target Optimization Hooks
4477 //===----------------------------------------------------------------------===//
4479 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4480 DAGCombinerInfo &DCI) const {
4481 TargetMachine &TM = getTargetMachine();
4482 SelectionDAG &DAG = DCI.DAG;
4483 DebugLoc dl = N->getDebugLoc();
4484 switch (N->getOpcode()) {
4487 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4488 if (C->getZExtValue() == 0) // 0 << V -> 0.
4489 return N->getOperand(0);
4493 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4494 if (C->getZExtValue() == 0) // 0 >>u V -> 0.
4495 return N->getOperand(0);
4499 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4500 if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
4501 C->isAllOnesValue()) // -1 >>s V -> -1.
4502 return N->getOperand(0);
4506 case ISD::SINT_TO_FP:
4507 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4508 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4509 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4510 // We allow the src/dst to be either f32/f64, but the intermediate
4511 // type must be i64.
4512 if (N->getOperand(0).getValueType() == MVT::i64 &&
4513 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4514 SDValue Val = N->getOperand(0).getOperand(0);
4515 if (Val.getValueType() == MVT::f32) {
4516 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4517 DCI.AddToWorklist(Val.getNode());
4520 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
4521 DCI.AddToWorklist(Val.getNode());
4522 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
4523 DCI.AddToWorklist(Val.getNode());
4524 if (N->getValueType(0) == MVT::f32) {
4525 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
4526 DAG.getIntPtrConstant(0));
4527 DCI.AddToWorklist(Val.getNode());
4530 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4531 // If the intermediate type is i32, we can avoid the load/store here
4538 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4539 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4540 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4541 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4542 N->getOperand(1).getValueType() == MVT::i32 &&
4543 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4544 SDValue Val = N->getOperand(1).getOperand(0);
4545 if (Val.getValueType() == MVT::f32) {
4546 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4547 DCI.AddToWorklist(Val.getNode());
4549 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
4550 DCI.AddToWorklist(Val.getNode());
4552 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
4553 N->getOperand(2), N->getOperand(3));
4554 DCI.AddToWorklist(Val.getNode());
4558 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4559 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
4560 N->getOperand(1).getNode()->hasOneUse() &&
4561 (N->getOperand(1).getValueType() == MVT::i32 ||
4562 N->getOperand(1).getValueType() == MVT::i16)) {
4563 SDValue BSwapOp = N->getOperand(1).getOperand(0);
4564 // Do an any-extend to 32-bits if this is a half-word input.
4565 if (BSwapOp.getValueType() == MVT::i16)
4566 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
4568 return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0),
4569 BSwapOp, N->getOperand(2), N->getOperand(3),
4570 DAG.getValueType(N->getOperand(1).getValueType()));
4574 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4575 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
4576 N->getOperand(0).hasOneUse() &&
4577 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4578 SDValue Load = N->getOperand(0);
4579 LoadSDNode *LD = cast<LoadSDNode>(Load);
4580 // Create the byte-swapping load.
4581 std::vector<MVT> VTs;
4582 VTs.push_back(MVT::i32);
4583 VTs.push_back(MVT::Other);
4584 SDValue MO = DAG.getMemOperand(LD->getMemOperand());
4586 LD->getChain(), // Chain
4587 LD->getBasePtr(), // Ptr
4589 DAG.getValueType(N->getValueType(0)) // VT
4591 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4);
4593 // If this is an i16 load, insert the truncate.
4594 SDValue ResVal = BSLoad;
4595 if (N->getValueType(0) == MVT::i16)
4596 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
4598 // First, combine the bswap away. This makes the value produced by the
4600 DCI.CombineTo(N, ResVal);
4602 // Next, combine the load away, we give it a bogus result value but a real
4603 // chain result. The result value is dead because the bswap is dead.
4604 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
4606 // Return N so it doesn't get rechecked!
4607 return SDValue(N, 0);
4611 case PPCISD::VCMP: {
4612 // If a VCMPo node already exists with exactly the same operands as this
4613 // node, use its result instead of this node (VCMPo computes both a CR6 and
4614 // a normal output).
4616 if (!N->getOperand(0).hasOneUse() &&
4617 !N->getOperand(1).hasOneUse() &&
4618 !N->getOperand(2).hasOneUse()) {
4620 // Scan all of the users of the LHS, looking for VCMPo's that match.
4621 SDNode *VCMPoNode = 0;
4623 SDNode *LHSN = N->getOperand(0).getNode();
4624 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
4626 if (UI->getOpcode() == PPCISD::VCMPo &&
4627 UI->getOperand(1) == N->getOperand(1) &&
4628 UI->getOperand(2) == N->getOperand(2) &&
4629 UI->getOperand(0) == N->getOperand(0)) {
4634 // If there is no VCMPo node, or if the flag value has a single use, don't
4636 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
4639 // Look at the (necessarily single) use of the flag value. If it has a
4640 // chain, this transformation is more complex. Note that multiple things
4641 // could use the value result, which we should ignore.
4642 SDNode *FlagUser = 0;
4643 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
4644 FlagUser == 0; ++UI) {
4645 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
4647 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
4648 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
4655 // If the user is a MFCR instruction, we know this is safe. Otherwise we
4656 // give up for right now.
4657 if (FlagUser->getOpcode() == PPCISD::MFCR)
4658 return SDValue(VCMPoNode, 0);
4663 // If this is a branch on an altivec predicate comparison, lower this so
4664 // that we don't have to do a MFCR: instead, branch directly on CR6. This
4665 // lowering is done pre-legalize, because the legalizer lowers the predicate
4666 // compare down to code that is difficult to reassemble.
4667 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
4668 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
4672 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
4673 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
4674 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
4675 assert(isDot && "Can't compare against a vector result!");
4677 // If this is a comparison against something other than 0/1, then we know
4678 // that the condition is never/always true.
4679 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
4680 if (Val != 0 && Val != 1) {
4681 if (CC == ISD::SETEQ) // Cond never true, remove branch.
4682 return N->getOperand(0);
4683 // Always !=, turn it into an unconditional branch.
4684 return DAG.getNode(ISD::BR, dl, MVT::Other,
4685 N->getOperand(0), N->getOperand(4));
4688 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
4690 // Create the PPCISD altivec 'dot' comparison node.
4691 std::vector<MVT> VTs;
4693 LHS.getOperand(2), // LHS of compare
4694 LHS.getOperand(3), // RHS of compare
4695 DAG.getConstant(CompareOpc, MVT::i32)
4697 VTs.push_back(LHS.getOperand(2).getValueType());
4698 VTs.push_back(MVT::Flag);
4699 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4701 // Unpack the result based on how the target uses it.
4702 PPC::Predicate CompOpc;
4703 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
4704 default: // Can't happen, don't crash on invalid number though.
4705 case 0: // Branch on the value of the EQ bit of CR6.
4706 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
4708 case 1: // Branch on the inverted value of the EQ bit of CR6.
4709 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
4711 case 2: // Branch on the value of the LT bit of CR6.
4712 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
4714 case 3: // Branch on the inverted value of the LT bit of CR6.
4715 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
4719 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
4720 DAG.getConstant(CompOpc, MVT::i32),
4721 DAG.getRegister(PPC::CR6, MVT::i32),
4722 N->getOperand(4), CompNode.getValue(1));
4731 //===----------------------------------------------------------------------===//
4732 // Inline Assembly Support
4733 //===----------------------------------------------------------------------===//
4735 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4739 const SelectionDAG &DAG,
4740 unsigned Depth) const {
4741 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4742 switch (Op.getOpcode()) {
4744 case PPCISD::LBRX: {
4745 // lhbrx is known to have the top bits cleared out.
4746 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
4747 KnownZero = 0xFFFF0000;
4750 case ISD::INTRINSIC_WO_CHAIN: {
4751 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
4753 case Intrinsic::ppc_altivec_vcmpbfp_p:
4754 case Intrinsic::ppc_altivec_vcmpeqfp_p:
4755 case Intrinsic::ppc_altivec_vcmpequb_p:
4756 case Intrinsic::ppc_altivec_vcmpequh_p:
4757 case Intrinsic::ppc_altivec_vcmpequw_p:
4758 case Intrinsic::ppc_altivec_vcmpgefp_p:
4759 case Intrinsic::ppc_altivec_vcmpgtfp_p:
4760 case Intrinsic::ppc_altivec_vcmpgtsb_p:
4761 case Intrinsic::ppc_altivec_vcmpgtsh_p:
4762 case Intrinsic::ppc_altivec_vcmpgtsw_p:
4763 case Intrinsic::ppc_altivec_vcmpgtub_p:
4764 case Intrinsic::ppc_altivec_vcmpgtuh_p:
4765 case Intrinsic::ppc_altivec_vcmpgtuw_p:
4766 KnownZero = ~1U; // All bits but the low one are known to be zero.
4774 /// getConstraintType - Given a constraint, return the type of
4775 /// constraint it is for this target.
4776 PPCTargetLowering::ConstraintType
4777 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
4778 if (Constraint.size() == 1) {
4779 switch (Constraint[0]) {
4786 return C_RegisterClass;
4789 return TargetLowering::getConstraintType(Constraint);
4792 std::pair<unsigned, const TargetRegisterClass*>
4793 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4795 if (Constraint.size() == 1) {
4796 // GCC RS6000 Constraint Letters
4797 switch (Constraint[0]) {
4800 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
4801 return std::make_pair(0U, PPC::G8RCRegisterClass);
4802 return std::make_pair(0U, PPC::GPRCRegisterClass);
4805 return std::make_pair(0U, PPC::F4RCRegisterClass);
4806 else if (VT == MVT::f64)
4807 return std::make_pair(0U, PPC::F8RCRegisterClass);
4810 return std::make_pair(0U, PPC::VRRCRegisterClass);
4812 return std::make_pair(0U, PPC::CRRCRegisterClass);
4816 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4820 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4821 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
4822 /// it means one of the asm constraint of the inline asm instruction being
4823 /// processed is 'm'.
4824 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
4826 std::vector<SDValue>&Ops,
4827 SelectionDAG &DAG) const {
4828 SDValue Result(0,0);
4839 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
4840 if (!CST) return; // Must be an immediate to match.
4841 unsigned Value = CST->getZExtValue();
4843 default: assert(0 && "Unknown constraint letter!");
4844 case 'I': // "I" is a signed 16-bit constant.
4845 if ((short)Value == (int)Value)
4846 Result = DAG.getTargetConstant(Value, Op.getValueType());
4848 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
4849 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
4850 if ((short)Value == 0)
4851 Result = DAG.getTargetConstant(Value, Op.getValueType());
4853 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
4854 if ((Value >> 16) == 0)
4855 Result = DAG.getTargetConstant(Value, Op.getValueType());
4857 case 'M': // "M" is a constant that is greater than 31.
4859 Result = DAG.getTargetConstant(Value, Op.getValueType());
4861 case 'N': // "N" is a positive constant that is an exact power of two.
4862 if ((int)Value > 0 && isPowerOf2_32(Value))
4863 Result = DAG.getTargetConstant(Value, Op.getValueType());
4865 case 'O': // "O" is the constant zero.
4867 Result = DAG.getTargetConstant(Value, Op.getValueType());
4869 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
4870 if ((short)-Value == (int)-Value)
4871 Result = DAG.getTargetConstant(Value, Op.getValueType());
4878 if (Result.getNode()) {
4879 Ops.push_back(Result);
4883 // Handle standard constraint letters.
4884 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
4887 // isLegalAddressingMode - Return true if the addressing mode represented
4888 // by AM is legal for this target, for a load/store of the specified type.
4889 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4890 const Type *Ty) const {
4891 // FIXME: PPC does not allow r+i addressing modes for vectors!
4893 // PPC allows a sign-extended 16-bit immediate field.
4894 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
4897 // No global is ever allowed as a base.
4901 // PPC only support r+r,
4903 case 0: // "r+i" or just "i", depending on HasBaseReg.
4906 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
4908 // Otherwise we have r+r or r+i.
4911 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
4913 // Allow 2*r as r+r.
4916 // No other scales are supported.
4923 /// isLegalAddressImmediate - Return true if the integer value can be used
4924 /// as the offset of the target addressing mode for load / store of the
4926 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
4927 // PPC allows a sign-extended 16-bit immediate field.
4928 return (V > -(1 << 16) && V < (1 << 16)-1);
4931 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
4935 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
4936 DebugLoc dl = Op.getNode()->getDebugLoc();
4937 // Depths > 0 not supported yet!
4938 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
4941 MachineFunction &MF = DAG.getMachineFunction();
4942 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4944 // Just load the return address off the stack.
4945 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
4947 // Make sure the function really does not optimize away the store of the RA
4949 FuncInfo->setLRStoreRequired();
4950 return DAG.getLoad(getPointerTy(), dl,
4951 DAG.getEntryNode(), RetAddrFI, NULL, 0);
4954 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
4955 DebugLoc dl = Op.getDebugLoc();
4956 // Depths > 0 not supported yet!
4957 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
4960 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4961 bool isPPC64 = PtrVT == MVT::i64;
4963 MachineFunction &MF = DAG.getMachineFunction();
4964 MachineFrameInfo *MFI = MF.getFrameInfo();
4965 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
4966 && MFI->getStackSize();
4969 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
4972 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
4977 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4978 // The PowerPC target isn't yet aware of offsets.