1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/ParameterAttributes.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
38 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
39 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
42 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
43 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
47 // Use _setjmp/_longjmp instead of setjmp/longjmp.
48 setUseUnderscoreSetJmp(true);
49 setUseUnderscoreLongJmp(true);
51 // Set up the register classes.
52 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
53 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
54 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
56 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
57 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
58 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
60 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
62 // PowerPC has pre-inc load and store's.
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
67 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
72 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
74 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
75 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
76 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
77 // This is used in the ppcf128->int sequence. Note it has different semantics
78 // from FP_ROUND: that rounds to nearest, this rounds to zero.
79 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
81 // PowerPC has no SREM/UREM instructions
82 setOperationAction(ISD::SREM, MVT::i32, Expand);
83 setOperationAction(ISD::UREM, MVT::i32, Expand);
84 setOperationAction(ISD::SREM, MVT::i64, Expand);
85 setOperationAction(ISD::UREM, MVT::i64, Expand);
87 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
88 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
89 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
90 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
91 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
92 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
93 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
94 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
95 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
97 // We don't support sin/cos/sqrt/fmod/pow
98 setOperationAction(ISD::FSIN , MVT::f64, Expand);
99 setOperationAction(ISD::FCOS , MVT::f64, Expand);
100 setOperationAction(ISD::FREM , MVT::f64, Expand);
101 setOperationAction(ISD::FPOW , MVT::f64, Expand);
102 setOperationAction(ISD::FSIN , MVT::f32, Expand);
103 setOperationAction(ISD::FCOS , MVT::f32, Expand);
104 setOperationAction(ISD::FREM , MVT::f32, Expand);
105 setOperationAction(ISD::FPOW , MVT::f32, Expand);
107 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
109 // If we're enabling GP optimizations, use hardware square root
110 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
111 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
112 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
115 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
116 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
118 // PowerPC does not have BSWAP, CTPOP or CTTZ
119 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
121 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
122 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
123 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
124 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
126 // PowerPC does not have ROTR
127 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
129 // PowerPC does not have Select
130 setOperationAction(ISD::SELECT, MVT::i32, Expand);
131 setOperationAction(ISD::SELECT, MVT::i64, Expand);
132 setOperationAction(ISD::SELECT, MVT::f32, Expand);
133 setOperationAction(ISD::SELECT, MVT::f64, Expand);
135 // PowerPC wants to turn select_cc of FP into fsel when possible.
136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
139 // PowerPC wants to optimize integer setcc a bit
140 setOperationAction(ISD::SETCC, MVT::i32, Custom);
142 // PowerPC does not have BRCOND which requires SetCC
143 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
145 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
147 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
148 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
150 // PowerPC does not have [U|S]INT_TO_FP
151 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
152 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
154 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
155 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
156 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
157 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
159 // We cannot sextinreg(i1). Expand to shifts.
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
162 // Support label based line numbers.
163 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
164 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
166 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
167 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
168 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
169 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
172 // We want to legalize GlobalAddress and ConstantPool nodes into the
173 // appropriate instructions to materialize the address.
174 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
175 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
176 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
177 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
178 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
179 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
180 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
181 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
183 // RET must be custom lowered, to meet ABI requirements.
184 setOperationAction(ISD::RET , MVT::Other, Custom);
187 setOperationAction(ISD::TRAP, MVT::Other, Legal);
189 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
190 setOperationAction(ISD::VASTART , MVT::Other, Custom);
192 // VAARG is custom lowered with ELF 32 ABI
193 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
194 setOperationAction(ISD::VAARG, MVT::Other, Custom);
196 setOperationAction(ISD::VAARG, MVT::Other, Expand);
198 // Use the default implementation.
199 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
200 setOperationAction(ISD::VAEND , MVT::Other, Expand);
201 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
202 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
203 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
204 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
206 // We want to custom lower some of our intrinsics.
207 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
209 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
210 // They also have instructions for converting between i64 and fp.
211 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
212 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
213 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
214 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
215 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
217 // FIXME: disable this lowered code. This generates 64-bit register values,
218 // and we don't model the fact that the top part is clobbered by calls. We
219 // need to flag these together so that the value isn't live across a call.
220 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
222 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
223 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
225 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
226 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
229 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
230 // 64-bit PowerPC implementations can support i64 types directly
231 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
232 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
233 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
234 // 64-bit PowerPC wants to expand i128 shifts itself.
235 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
236 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
237 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
239 // 32-bit PowerPC wants to expand i64 shifts itself.
240 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
241 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
242 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
245 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
246 // First set operation action for all vector types to expand. Then we
247 // will selectively turn on ones that can be effectively codegen'd.
248 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
249 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
250 MVT VT = (MVT::SimpleValueType)i;
252 // add/sub are legal for all supported vector VT's.
253 setOperationAction(ISD::ADD , VT, Legal);
254 setOperationAction(ISD::SUB , VT, Legal);
256 // We promote all shuffles to v16i8.
257 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
258 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
260 // We promote all non-typed operations to v4i32.
261 setOperationAction(ISD::AND , VT, Promote);
262 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
263 setOperationAction(ISD::OR , VT, Promote);
264 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
265 setOperationAction(ISD::XOR , VT, Promote);
266 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
267 setOperationAction(ISD::LOAD , VT, Promote);
268 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
269 setOperationAction(ISD::SELECT, VT, Promote);
270 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
271 setOperationAction(ISD::STORE, VT, Promote);
272 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
274 // No other operations are legal.
275 setOperationAction(ISD::MUL , VT, Expand);
276 setOperationAction(ISD::SDIV, VT, Expand);
277 setOperationAction(ISD::SREM, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::UREM, VT, Expand);
280 setOperationAction(ISD::FDIV, VT, Expand);
281 setOperationAction(ISD::FNEG, VT, Expand);
282 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
283 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
284 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
285 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
286 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
287 setOperationAction(ISD::UDIVREM, VT, Expand);
288 setOperationAction(ISD::SDIVREM, VT, Expand);
289 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
290 setOperationAction(ISD::FPOW, VT, Expand);
291 setOperationAction(ISD::CTPOP, VT, Expand);
292 setOperationAction(ISD::CTLZ, VT, Expand);
293 setOperationAction(ISD::CTTZ, VT, Expand);
296 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
297 // with merges, splats, etc.
298 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
300 setOperationAction(ISD::AND , MVT::v4i32, Legal);
301 setOperationAction(ISD::OR , MVT::v4i32, Legal);
302 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
303 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
304 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
305 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
307 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
308 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
309 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
310 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
312 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
313 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
314 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
315 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
317 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
318 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
320 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
321 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
322 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
323 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
326 setShiftAmountType(MVT::i32);
327 setSetCCResultContents(ZeroOrOneSetCCResult);
329 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
330 setStackPointerRegisterToSaveRestore(PPC::X1);
331 setExceptionPointerRegister(PPC::X3);
332 setExceptionSelectorRegister(PPC::X4);
334 setStackPointerRegisterToSaveRestore(PPC::R1);
335 setExceptionPointerRegister(PPC::R3);
336 setExceptionSelectorRegister(PPC::R4);
339 // We have target-specific dag combine patterns for the following nodes:
340 setTargetDAGCombine(ISD::SINT_TO_FP);
341 setTargetDAGCombine(ISD::STORE);
342 setTargetDAGCombine(ISD::BR_CC);
343 setTargetDAGCombine(ISD::BSWAP);
345 // Darwin long double math library functions have $LDBL128 appended.
346 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
347 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
348 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
349 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
350 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
351 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
354 computeRegisterProperties();
357 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
358 /// function arguments in the caller parameter area.
359 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
360 TargetMachine &TM = getTargetMachine();
361 // Darwin passes everything on 4 byte boundary.
362 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
368 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
371 case PPCISD::FSEL: return "PPCISD::FSEL";
372 case PPCISD::FCFID: return "PPCISD::FCFID";
373 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
374 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
375 case PPCISD::STFIWX: return "PPCISD::STFIWX";
376 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
377 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
378 case PPCISD::VPERM: return "PPCISD::VPERM";
379 case PPCISD::Hi: return "PPCISD::Hi";
380 case PPCISD::Lo: return "PPCISD::Lo";
381 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
382 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
383 case PPCISD::SRL: return "PPCISD::SRL";
384 case PPCISD::SRA: return "PPCISD::SRA";
385 case PPCISD::SHL: return "PPCISD::SHL";
386 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
387 case PPCISD::STD_32: return "PPCISD::STD_32";
388 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
389 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
390 case PPCISD::MTCTR: return "PPCISD::MTCTR";
391 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
392 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
393 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
394 case PPCISD::MFCR: return "PPCISD::MFCR";
395 case PPCISD::VCMP: return "PPCISD::VCMP";
396 case PPCISD::VCMPo: return "PPCISD::VCMPo";
397 case PPCISD::LBRX: return "PPCISD::LBRX";
398 case PPCISD::STBRX: return "PPCISD::STBRX";
399 case PPCISD::LARX: return "PPCISD::LARX";
400 case PPCISD::STCX: return "PPCISD::STCX";
401 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
402 case PPCISD::MFFS: return "PPCISD::MFFS";
403 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
404 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
405 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
406 case PPCISD::MTFSF: return "PPCISD::MTFSF";
407 case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
408 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
413 MVT PPCTargetLowering::getSetCCResultType(const SDValue &) const {
418 //===----------------------------------------------------------------------===//
419 // Node matching predicates, for use by the tblgen matching code.
420 //===----------------------------------------------------------------------===//
422 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
423 static bool isFloatingPointZero(SDValue Op) {
424 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
425 return CFP->getValueAPF().isZero();
426 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
427 // Maybe this has already been legalized into the constant pool?
428 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
429 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
430 return CFP->getValueAPF().isZero();
435 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
436 /// true if Op is undef or if it matches the specified value.
437 static bool isConstantOrUndef(SDValue Op, unsigned Val) {
438 return Op.getOpcode() == ISD::UNDEF ||
439 cast<ConstantSDNode>(Op)->getValue() == Val;
442 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
443 /// VPKUHUM instruction.
444 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
446 for (unsigned i = 0; i != 16; ++i)
447 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
450 for (unsigned i = 0; i != 8; ++i)
451 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
452 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
458 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
459 /// VPKUWUM instruction.
460 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
462 for (unsigned i = 0; i != 16; i += 2)
463 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
464 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
467 for (unsigned i = 0; i != 8; i += 2)
468 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
469 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
470 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
471 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
477 /// isVMerge - Common function, used to match vmrg* shuffles.
479 static bool isVMerge(SDNode *N, unsigned UnitSize,
480 unsigned LHSStart, unsigned RHSStart) {
481 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
482 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
483 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
484 "Unsupported merge size!");
486 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
487 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
488 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
489 LHSStart+j+i*UnitSize) ||
490 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
491 RHSStart+j+i*UnitSize))
497 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
498 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
499 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
501 return isVMerge(N, UnitSize, 8, 24);
502 return isVMerge(N, UnitSize, 8, 8);
505 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
506 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
507 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
509 return isVMerge(N, UnitSize, 0, 16);
510 return isVMerge(N, UnitSize, 0, 0);
514 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
515 /// amount, otherwise return -1.
516 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
517 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
518 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
519 // Find the first non-undef value in the shuffle mask.
521 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
524 if (i == 16) return -1; // all undef.
526 // Otherwise, check to see if the rest of the elements are consequtively
527 // numbered from this value.
528 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
529 if (ShiftAmt < i) return -1;
533 // Check the rest of the elements to see if they are consequtive.
534 for (++i; i != 16; ++i)
535 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
538 // Check the rest of the elements to see if they are consequtive.
539 for (++i; i != 16; ++i)
540 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
547 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
548 /// specifies a splat of a single element that is suitable for input to
549 /// VSPLTB/VSPLTH/VSPLTW.
550 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
551 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
552 N->getNumOperands() == 16 &&
553 (EltSize == 1 || EltSize == 2 || EltSize == 4));
555 // This is a splat operation if each element of the permute is the same, and
556 // if the value doesn't reference the second vector.
557 unsigned ElementBase = 0;
558 SDValue Elt = N->getOperand(0);
559 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
560 ElementBase = EltV->getValue();
562 return false; // FIXME: Handle UNDEF elements too!
564 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
567 // Check that they are consequtive.
568 for (unsigned i = 1; i != EltSize; ++i) {
569 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
570 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
574 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
575 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
576 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
577 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
578 "Invalid VECTOR_SHUFFLE mask!");
579 for (unsigned j = 0; j != EltSize; ++j)
580 if (N->getOperand(i+j) != N->getOperand(j))
587 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
589 bool PPC::isAllNegativeZeroVector(SDNode *N) {
590 assert(N->getOpcode() == ISD::BUILD_VECTOR);
591 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
592 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
593 return CFP->getValueAPF().isNegZero();
597 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
598 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
599 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
600 assert(isSplatShuffleMask(N, EltSize));
601 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
604 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
605 /// by using a vspltis[bhw] instruction of the specified element size, return
606 /// the constant being splatted. The ByteSize field indicates the number of
607 /// bytes of each element [124] -> [bhw].
608 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
611 // If ByteSize of the splat is bigger than the element size of the
612 // build_vector, then we have a case where we are checking for a splat where
613 // multiple elements of the buildvector are folded together into a single
614 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
615 unsigned EltSize = 16/N->getNumOperands();
616 if (EltSize < ByteSize) {
617 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
618 SDValue UniquedVals[4];
619 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
621 // See if all of the elements in the buildvector agree across.
622 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
623 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
624 // If the element isn't a constant, bail fully out.
625 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
628 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
629 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
630 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
631 return SDValue(); // no match.
634 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
635 // either constant or undef values that are identical for each chunk. See
636 // if these chunks can form into a larger vspltis*.
638 // Check to see if all of the leading entries are either 0 or -1. If
639 // neither, then this won't fit into the immediate field.
640 bool LeadingZero = true;
641 bool LeadingOnes = true;
642 for (unsigned i = 0; i != Multiple-1; ++i) {
643 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
645 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
646 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
648 // Finally, check the least significant entry.
650 if (UniquedVals[Multiple-1].getNode() == 0)
651 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
652 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
654 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
657 if (UniquedVals[Multiple-1].getNode() == 0)
658 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
659 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
660 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
661 return DAG.getTargetConstant(Val, MVT::i32);
667 // Check to see if this buildvec has a single non-undef value in its elements.
668 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
669 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
670 if (OpVal.getNode() == 0)
671 OpVal = N->getOperand(i);
672 else if (OpVal != N->getOperand(i))
676 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
678 unsigned ValSizeInBytes = 0;
680 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
681 Value = CN->getValue();
682 ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8;
683 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
684 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
685 Value = FloatToBits(CN->getValueAPF().convertToFloat());
689 // If the splat value is larger than the element value, then we can never do
690 // this splat. The only case that we could fit the replicated bits into our
691 // immediate field for would be zero, and we prefer to use vxor for it.
692 if (ValSizeInBytes < ByteSize) return SDValue();
694 // If the element value is larger than the splat value, cut it in half and
695 // check to see if the two halves are equal. Continue doing this until we
696 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
697 while (ValSizeInBytes > ByteSize) {
698 ValSizeInBytes >>= 1;
700 // If the top half equals the bottom half, we're still ok.
701 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
702 (Value & ((1 << (8*ValSizeInBytes))-1)))
706 // Properly sign extend the value.
707 int ShAmt = (4-ByteSize)*8;
708 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
710 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
711 if (MaskVal == 0) return SDValue();
713 // Finally, if this value fits in a 5 bit sext field, return it
714 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
715 return DAG.getTargetConstant(MaskVal, MVT::i32);
719 //===----------------------------------------------------------------------===//
720 // Addressing Mode Selection
721 //===----------------------------------------------------------------------===//
723 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
724 /// or 64-bit immediate, and if the value can be accurately represented as a
725 /// sign extension from a 16-bit value. If so, this returns true and the
727 static bool isIntS16Immediate(SDNode *N, short &Imm) {
728 if (N->getOpcode() != ISD::Constant)
731 Imm = (short)cast<ConstantSDNode>(N)->getValue();
732 if (N->getValueType(0) == MVT::i32)
733 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
735 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
737 static bool isIntS16Immediate(SDValue Op, short &Imm) {
738 return isIntS16Immediate(Op.getNode(), Imm);
742 /// SelectAddressRegReg - Given the specified addressed, check to see if it
743 /// can be represented as an indexed [r+r] operation. Returns false if it
744 /// can be more efficiently represented with [r+imm].
745 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
749 if (N.getOpcode() == ISD::ADD) {
750 if (isIntS16Immediate(N.getOperand(1), imm))
752 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
755 Base = N.getOperand(0);
756 Index = N.getOperand(1);
758 } else if (N.getOpcode() == ISD::OR) {
759 if (isIntS16Immediate(N.getOperand(1), imm))
760 return false; // r+i can fold it if we can.
762 // If this is an or of disjoint bitfields, we can codegen this as an add
763 // (for better address arithmetic) if the LHS and RHS of the OR are provably
765 APInt LHSKnownZero, LHSKnownOne;
766 APInt RHSKnownZero, RHSKnownOne;
767 DAG.ComputeMaskedBits(N.getOperand(0),
768 APInt::getAllOnesValue(N.getOperand(0)
769 .getValueSizeInBits()),
770 LHSKnownZero, LHSKnownOne);
772 if (LHSKnownZero.getBoolValue()) {
773 DAG.ComputeMaskedBits(N.getOperand(1),
774 APInt::getAllOnesValue(N.getOperand(1)
775 .getValueSizeInBits()),
776 RHSKnownZero, RHSKnownOne);
777 // If all of the bits are known zero on the LHS or RHS, the add won't
779 if (~(LHSKnownZero | RHSKnownZero) == 0) {
780 Base = N.getOperand(0);
781 Index = N.getOperand(1);
790 /// Returns true if the address N can be represented by a base register plus
791 /// a signed 16-bit displacement [r+imm], and if it is not better
792 /// represented as reg+reg.
793 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
794 SDValue &Base, SelectionDAG &DAG){
795 // If this can be more profitably realized as r+r, fail.
796 if (SelectAddressRegReg(N, Disp, Base, DAG))
799 if (N.getOpcode() == ISD::ADD) {
801 if (isIntS16Immediate(N.getOperand(1), imm)) {
802 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
803 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
804 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
806 Base = N.getOperand(0);
808 return true; // [r+i]
809 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
810 // Match LOAD (ADD (X, Lo(G))).
811 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
812 && "Cannot handle constant offsets yet!");
813 Disp = N.getOperand(1).getOperand(0); // The global address.
814 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
815 Disp.getOpcode() == ISD::TargetConstantPool ||
816 Disp.getOpcode() == ISD::TargetJumpTable);
817 Base = N.getOperand(0);
818 return true; // [&g+r]
820 } else if (N.getOpcode() == ISD::OR) {
822 if (isIntS16Immediate(N.getOperand(1), imm)) {
823 // If this is an or of disjoint bitfields, we can codegen this as an add
824 // (for better address arithmetic) if the LHS and RHS of the OR are
825 // provably disjoint.
826 APInt LHSKnownZero, LHSKnownOne;
827 DAG.ComputeMaskedBits(N.getOperand(0),
828 APInt::getAllOnesValue(N.getOperand(0)
829 .getValueSizeInBits()),
830 LHSKnownZero, LHSKnownOne);
832 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
833 // If all of the bits are known zero on the LHS or RHS, the add won't
835 Base = N.getOperand(0);
836 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
840 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
841 // Loading from a constant address.
843 // If this address fits entirely in a 16-bit sext immediate field, codegen
846 if (isIntS16Immediate(CN, Imm)) {
847 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
848 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
852 // Handle 32-bit sext immediates with LIS + addr mode.
853 if (CN->getValueType(0) == MVT::i32 ||
854 (int64_t)CN->getValue() == (int)CN->getValue()) {
855 int Addr = (int)CN->getValue();
857 // Otherwise, break this down into an LIS + disp.
858 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
860 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
861 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
862 Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
867 Disp = DAG.getTargetConstant(0, getPointerTy());
868 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
869 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
872 return true; // [r+0]
875 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
876 /// represented as an indexed [r+r] operation.
877 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
880 // Check to see if we can easily represent this as an [r+r] address. This
881 // will fail if it thinks that the address is more profitably represented as
882 // reg+imm, e.g. where imm = 0.
883 if (SelectAddressRegReg(N, Base, Index, DAG))
886 // If the operand is an addition, always emit this as [r+r], since this is
887 // better (for code size, and execution, as the memop does the add for free)
888 // than emitting an explicit add.
889 if (N.getOpcode() == ISD::ADD) {
890 Base = N.getOperand(0);
891 Index = N.getOperand(1);
895 // Otherwise, do it the hard way, using R0 as the base register.
896 Base = DAG.getRegister(PPC::R0, N.getValueType());
901 /// SelectAddressRegImmShift - Returns true if the address N can be
902 /// represented by a base register plus a signed 14-bit displacement
903 /// [r+imm*4]. Suitable for use by STD and friends.
904 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
907 // If this can be more profitably realized as r+r, fail.
908 if (SelectAddressRegReg(N, Disp, Base, DAG))
911 if (N.getOpcode() == ISD::ADD) {
913 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
914 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
915 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
916 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
918 Base = N.getOperand(0);
920 return true; // [r+i]
921 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
922 // Match LOAD (ADD (X, Lo(G))).
923 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
924 && "Cannot handle constant offsets yet!");
925 Disp = N.getOperand(1).getOperand(0); // The global address.
926 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
927 Disp.getOpcode() == ISD::TargetConstantPool ||
928 Disp.getOpcode() == ISD::TargetJumpTable);
929 Base = N.getOperand(0);
930 return true; // [&g+r]
932 } else if (N.getOpcode() == ISD::OR) {
934 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
935 // If this is an or of disjoint bitfields, we can codegen this as an add
936 // (for better address arithmetic) if the LHS and RHS of the OR are
937 // provably disjoint.
938 APInt LHSKnownZero, LHSKnownOne;
939 DAG.ComputeMaskedBits(N.getOperand(0),
940 APInt::getAllOnesValue(N.getOperand(0)
941 .getValueSizeInBits()),
942 LHSKnownZero, LHSKnownOne);
943 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
944 // If all of the bits are known zero on the LHS or RHS, the add won't
946 Base = N.getOperand(0);
947 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
951 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
952 // Loading from a constant address. Verify low two bits are clear.
953 if ((CN->getValue() & 3) == 0) {
954 // If this address fits entirely in a 14-bit sext immediate field, codegen
957 if (isIntS16Immediate(CN, Imm)) {
958 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
959 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
963 // Fold the low-part of 32-bit absolute addresses into addr mode.
964 if (CN->getValueType(0) == MVT::i32 ||
965 (int64_t)CN->getValue() == (int)CN->getValue()) {
966 int Addr = (int)CN->getValue();
968 // Otherwise, break this down into an LIS + disp.
969 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
971 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
972 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
973 Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
979 Disp = DAG.getTargetConstant(0, getPointerTy());
980 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
981 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
984 return true; // [r+0]
988 /// getPreIndexedAddressParts - returns true by value, base pointer and
989 /// offset pointer and addressing mode by reference if the node's address
990 /// can be legally represented as pre-indexed load / store address.
991 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
993 ISD::MemIndexedMode &AM,
995 // Disabled by default for now.
996 if (!EnablePPCPreinc) return false;
1000 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1001 Ptr = LD->getBasePtr();
1002 VT = LD->getMemoryVT();
1004 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1006 Ptr = ST->getBasePtr();
1007 VT = ST->getMemoryVT();
1011 // PowerPC doesn't have preinc load/store instructions for vectors.
1015 // TODO: Check reg+reg first.
1017 // LDU/STU use reg+imm*4, others use reg+imm.
1018 if (VT != MVT::i64) {
1020 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1024 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1028 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1029 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1030 // sext i32 to i64 when addr mode is r+i.
1031 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1032 LD->getExtensionType() == ISD::SEXTLOAD &&
1033 isa<ConstantSDNode>(Offset))
1041 //===----------------------------------------------------------------------===//
1042 // LowerOperation implementation
1043 //===----------------------------------------------------------------------===//
1045 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1046 SelectionDAG &DAG) {
1047 MVT PtrVT = Op.getValueType();
1048 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1049 Constant *C = CP->getConstVal();
1050 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1051 SDValue Zero = DAG.getConstant(0, PtrVT);
1053 const TargetMachine &TM = DAG.getTarget();
1055 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1056 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1058 // If this is a non-darwin platform, we don't support non-static relo models
1060 if (TM.getRelocationModel() == Reloc::Static ||
1061 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1062 // Generate non-pic code that has direct accesses to the constant pool.
1063 // The address of the global is just (hi(&g)+lo(&g)).
1064 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1067 if (TM.getRelocationModel() == Reloc::PIC_) {
1068 // With PIC, the first instruction is actually "GR+hi(&G)".
1069 Hi = DAG.getNode(ISD::ADD, PtrVT,
1070 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1073 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1077 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1078 MVT PtrVT = Op.getValueType();
1079 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1080 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1081 SDValue Zero = DAG.getConstant(0, PtrVT);
1083 const TargetMachine &TM = DAG.getTarget();
1085 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1086 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1088 // If this is a non-darwin platform, we don't support non-static relo models
1090 if (TM.getRelocationModel() == Reloc::Static ||
1091 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1092 // Generate non-pic code that has direct accesses to the constant pool.
1093 // The address of the global is just (hi(&g)+lo(&g)).
1094 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1097 if (TM.getRelocationModel() == Reloc::PIC_) {
1098 // With PIC, the first instruction is actually "GR+hi(&G)".
1099 Hi = DAG.getNode(ISD::ADD, PtrVT,
1100 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1103 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1107 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1108 SelectionDAG &DAG) {
1109 assert(0 && "TLS not implemented for PPC.");
1110 return SDValue(); // Not reached
1113 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1114 SelectionDAG &DAG) {
1115 MVT PtrVT = Op.getValueType();
1116 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1117 GlobalValue *GV = GSDN->getGlobal();
1118 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1119 // If it's a debug information descriptor, don't mess with it.
1120 if (DAG.isVerifiedDebugInfoDesc(Op))
1122 SDValue Zero = DAG.getConstant(0, PtrVT);
1124 const TargetMachine &TM = DAG.getTarget();
1126 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1127 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1129 // If this is a non-darwin platform, we don't support non-static relo models
1131 if (TM.getRelocationModel() == Reloc::Static ||
1132 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1133 // Generate non-pic code that has direct accesses to globals.
1134 // The address of the global is just (hi(&g)+lo(&g)).
1135 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1138 if (TM.getRelocationModel() == Reloc::PIC_) {
1139 // With PIC, the first instruction is actually "GR+hi(&G)".
1140 Hi = DAG.getNode(ISD::ADD, PtrVT,
1141 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1144 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1146 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1149 // If the global is weak or external, we have to go through the lazy
1151 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1154 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1155 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1157 // If we're comparing for equality to zero, expose the fact that this is
1158 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1159 // fold the new nodes.
1160 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1161 if (C->isNullValue() && CC == ISD::SETEQ) {
1162 MVT VT = Op.getOperand(0).getValueType();
1163 SDValue Zext = Op.getOperand(0);
1164 if (VT.bitsLT(MVT::i32)) {
1166 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1168 unsigned Log2b = Log2_32(VT.getSizeInBits());
1169 SDValue Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1170 SDValue Scc = DAG.getNode(ISD::SRL, VT, Clz,
1171 DAG.getConstant(Log2b, MVT::i32));
1172 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1174 // Leave comparisons against 0 and -1 alone for now, since they're usually
1175 // optimized. FIXME: revisit this when we can custom lower all setcc
1177 if (C->isAllOnesValue() || C->isNullValue())
1181 // If we have an integer seteq/setne, turn it into a compare against zero
1182 // by xor'ing the rhs with the lhs, which is faster than setting a
1183 // condition register, reading it back out, and masking the correct bit. The
1184 // normal approach here uses sub to do this instead of xor. Using xor exposes
1185 // the result to other bit-twiddling opportunities.
1186 MVT LHSVT = Op.getOperand(0).getValueType();
1187 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1188 MVT VT = Op.getValueType();
1189 SDValue Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1191 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1196 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1197 int VarArgsFrameIndex,
1198 int VarArgsStackOffset,
1199 unsigned VarArgsNumGPR,
1200 unsigned VarArgsNumFPR,
1201 const PPCSubtarget &Subtarget) {
1203 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1204 return SDValue(); // Not reached
1207 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1208 int VarArgsFrameIndex,
1209 int VarArgsStackOffset,
1210 unsigned VarArgsNumGPR,
1211 unsigned VarArgsNumFPR,
1212 const PPCSubtarget &Subtarget) {
1214 if (Subtarget.isMachoABI()) {
1215 // vastart just stores the address of the VarArgsFrameIndex slot into the
1216 // memory location argument.
1217 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1218 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1219 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1220 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
1223 // For ELF 32 ABI we follow the layout of the va_list struct.
1224 // We suppose the given va_list is already allocated.
1227 // char gpr; /* index into the array of 8 GPRs
1228 // * stored in the register save area
1229 // * gpr=0 corresponds to r3,
1230 // * gpr=1 to r4, etc.
1232 // char fpr; /* index into the array of 8 FPRs
1233 // * stored in the register save area
1234 // * fpr=0 corresponds to f1,
1235 // * fpr=1 to f2, etc.
1237 // char *overflow_arg_area;
1238 // /* location on stack that holds
1239 // * the next overflow argument
1241 // char *reg_save_area;
1242 // /* where r3:r10 and f1:f8 (if saved)
1248 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1249 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1252 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1254 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1255 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1257 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1258 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1260 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1261 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1263 uint64_t FPROffset = 1;
1264 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1266 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1268 // Store first byte : number of int regs
1269 SDValue firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1270 Op.getOperand(1), SV, 0);
1271 uint64_t nextOffset = FPROffset;
1272 SDValue nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1275 // Store second byte : number of float regs
1276 SDValue secondStore =
1277 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1278 nextOffset += StackOffset;
1279 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1281 // Store second word : arguments given on stack
1282 SDValue thirdStore =
1283 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1284 nextOffset += FrameOffset;
1285 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1287 // Store third word : arguments given in registers
1288 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
1292 #include "PPCGenCallingConv.inc"
1294 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1295 /// depending on which subtarget is selected.
1296 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1297 if (Subtarget.isMachoABI()) {
1298 static const unsigned FPR[] = {
1299 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1300 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1306 static const unsigned FPR[] = {
1307 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1313 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1315 static unsigned CalculateStackSlotSize(SDValue Arg, SDValue Flag,
1316 bool isVarArg, unsigned PtrByteSize) {
1317 MVT ArgVT = Arg.getValueType();
1318 ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Flag)->getArgFlags();
1319 unsigned ArgSize =ArgVT.getSizeInBits()/8;
1320 if (Flags.isByVal())
1321 ArgSize = Flags.getByValSize();
1322 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1328 PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1330 int &VarArgsFrameIndex,
1331 int &VarArgsStackOffset,
1332 unsigned &VarArgsNumGPR,
1333 unsigned &VarArgsNumFPR,
1334 const PPCSubtarget &Subtarget) {
1335 // TODO: add description of PPC stack frame format, or at least some docs.
1337 MachineFunction &MF = DAG.getMachineFunction();
1338 MachineFrameInfo *MFI = MF.getFrameInfo();
1339 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1340 SmallVector<SDValue, 8> ArgValues;
1341 SDValue Root = Op.getOperand(0);
1342 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1344 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1345 bool isPPC64 = PtrVT == MVT::i64;
1346 bool isMachoABI = Subtarget.isMachoABI();
1347 bool isELF32_ABI = Subtarget.isELF32_ABI();
1348 // Potential tail calls could cause overwriting of argument stack slots.
1349 unsigned CC = MF.getFunction()->getCallingConv();
1350 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1351 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1353 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1354 // Area that is at least reserved in caller of this function.
1355 unsigned MinReservedArea = ArgOffset;
1357 static const unsigned GPR_32[] = { // 32-bit registers.
1358 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1359 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1361 static const unsigned GPR_64[] = { // 64-bit registers.
1362 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1363 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1366 static const unsigned *FPR = GetFPR(Subtarget);
1368 static const unsigned VR[] = {
1369 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1370 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1373 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1374 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1375 const unsigned Num_VR_Regs = array_lengthof( VR);
1377 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1379 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1381 // In 32-bit non-varargs functions, the stack space for vectors is after the
1382 // stack space for non-vectors. We do not use this space unless we have
1383 // too many vectors to fit in registers, something that only occurs in
1384 // constructed examples:), but we have to walk the arglist to figure
1385 // that out...for the pathological case, compute VecArgOffset as the
1386 // start of the vector parameter area. Computing VecArgOffset is the
1387 // entire point of the following loop.
1388 // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying
1389 // to handle Elf here.
1390 unsigned VecArgOffset = ArgOffset;
1391 if (!isVarArg && !isPPC64) {
1392 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e;
1394 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1395 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1396 ISD::ArgFlagsTy Flags =
1397 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1399 if (Flags.isByVal()) {
1400 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1401 ObjSize = Flags.getByValSize();
1403 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1404 VecArgOffset += ArgSize;
1408 switch(ObjectVT.getSimpleVT()) {
1409 default: assert(0 && "Unhandled argument type!");
1412 VecArgOffset += isPPC64 ? 8 : 4;
1414 case MVT::i64: // PPC64
1422 // Nothing to do, we're only looking at Nonvector args here.
1427 // We've found where the vector parameter area in memory is. Skip the
1428 // first 12 parameters; these don't use that memory.
1429 VecArgOffset = ((VecArgOffset+15)/16)*16;
1430 VecArgOffset += 12*16;
1432 // Add DAG nodes to load the arguments or copy them out of registers. On
1433 // entry to a function on PPC, the arguments start after the linkage area,
1434 // although the first ones are often in registers.
1436 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1437 // represented with two words (long long or double) must be copied to an
1438 // even GPR_idx value or to an even ArgOffset value.
1440 SmallVector<SDValue, 8> MemOps;
1441 unsigned nAltivecParamsAtEnd = 0;
1442 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
1444 bool needsLoad = false;
1445 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1446 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1447 unsigned ArgSize = ObjSize;
1448 ISD::ArgFlagsTy Flags =
1449 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1450 // See if next argument requires stack alignment in ELF
1451 bool Align = Flags.isSplit();
1453 unsigned CurArgOffset = ArgOffset;
1455 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1456 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1457 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1458 if (isVarArg || isPPC64) {
1459 MinReservedArea = ((MinReservedArea+15)/16)*16;
1460 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1461 Op.getOperand(ArgNo+3),
1464 } else nAltivecParamsAtEnd++;
1466 // Calculate min reserved area.
1467 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1468 Op.getOperand(ArgNo+3),
1472 // FIXME alignment for ELF may not be right
1473 // FIXME the codegen can be much improved in some cases.
1474 // We do not have to keep everything in memory.
1475 if (Flags.isByVal()) {
1476 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1477 ObjSize = Flags.getByValSize();
1478 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1479 // Double word align in ELF
1480 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1481 // Objects of size 1 and 2 are right justified, everything else is
1482 // left justified. This means the memory address is adjusted forwards.
1483 if (ObjSize==1 || ObjSize==2) {
1484 CurArgOffset = CurArgOffset + (4 - ObjSize);
1486 // The value of the object is its address.
1487 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1488 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1489 ArgValues.push_back(FIN);
1490 if (ObjSize==1 || ObjSize==2) {
1491 if (GPR_idx != Num_GPR_Regs) {
1492 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1493 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1494 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1495 SDValue Store = DAG.getTruncStore(Val.getValue(1), Val, FIN,
1496 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1497 MemOps.push_back(Store);
1499 if (isMachoABI) ArgOffset += PtrByteSize;
1501 ArgOffset += PtrByteSize;
1505 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1506 // Store whatever pieces of the object are in registers
1507 // to memory. ArgVal will be address of the beginning of
1509 if (GPR_idx != Num_GPR_Regs) {
1510 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1511 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1512 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1513 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1514 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1515 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1516 MemOps.push_back(Store);
1518 if (isMachoABI) ArgOffset += PtrByteSize;
1520 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1527 switch (ObjectVT.getSimpleVT()) {
1528 default: assert(0 && "Unhandled argument type!");
1531 // Double word align in ELF
1532 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1534 if (GPR_idx != Num_GPR_Regs) {
1535 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1536 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1537 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1541 ArgSize = PtrByteSize;
1543 // Stack align in ELF
1544 if (needsLoad && Align && isELF32_ABI)
1545 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1546 // All int arguments reserve stack space in Macho ABI.
1547 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1551 case MVT::i64: // PPC64
1552 if (GPR_idx != Num_GPR_Regs) {
1553 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1554 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1555 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1557 if (ObjectVT == MVT::i32) {
1558 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1559 // value to MVT::i64 and then truncate to the correct register size.
1561 ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
1562 DAG.getValueType(ObjectVT));
1563 else if (Flags.isZExt())
1564 ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
1565 DAG.getValueType(ObjectVT));
1567 ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
1573 ArgSize = PtrByteSize;
1575 // All int arguments reserve stack space in Macho ABI.
1576 if (isMachoABI || needsLoad) ArgOffset += 8;
1581 // Every 4 bytes of argument space consumes one of the GPRs available for
1582 // argument passing.
1583 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1585 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1588 if (FPR_idx != Num_FPR_Regs) {
1590 if (ObjectVT == MVT::f32)
1591 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1593 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1594 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1595 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1601 // Stack align in ELF
1602 if (needsLoad && Align && isELF32_ABI)
1603 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1604 // All FP arguments reserve stack space in Macho ABI.
1605 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1611 // Note that vector arguments in registers don't reserve stack space,
1612 // except in varargs functions.
1613 if (VR_idx != Num_VR_Regs) {
1614 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1615 RegInfo.addLiveIn(VR[VR_idx], VReg);
1616 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1618 while ((ArgOffset % 16) != 0) {
1619 ArgOffset += PtrByteSize;
1620 if (GPR_idx != Num_GPR_Regs)
1624 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1628 if (!isVarArg && !isPPC64) {
1629 // Vectors go after all the nonvectors.
1630 CurArgOffset = VecArgOffset;
1633 // Vectors are aligned.
1634 ArgOffset = ((ArgOffset+15)/16)*16;
1635 CurArgOffset = ArgOffset;
1643 // We need to load the argument to a virtual register if we determined above
1644 // that we ran out of physical registers of the appropriate type.
1646 int FI = MFI->CreateFixedObject(ObjSize,
1647 CurArgOffset + (ArgSize - ObjSize),
1649 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1650 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1653 ArgValues.push_back(ArgVal);
1656 // Set the size that is at least reserved in caller of this function. Tail
1657 // call optimized function's reserved stack space needs to be aligned so that
1658 // taking the difference between two stack areas will result in an aligned
1660 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1661 // Add the Altivec parameters at the end, if needed.
1662 if (nAltivecParamsAtEnd) {
1663 MinReservedArea = ((MinReservedArea+15)/16)*16;
1664 MinReservedArea += 16*nAltivecParamsAtEnd;
1667 std::max(MinReservedArea,
1668 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1669 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1670 getStackAlignment();
1671 unsigned AlignMask = TargetAlign-1;
1672 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1673 FI->setMinReservedArea(MinReservedArea);
1675 // If the function takes variable number of arguments, make a frame index for
1676 // the start of the first vararg value... for expansion of llvm.va_start.
1681 VarArgsNumGPR = GPR_idx;
1682 VarArgsNumFPR = FPR_idx;
1684 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1686 depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 +
1687 Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 +
1688 PtrVT.getSizeInBits()/8);
1690 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1697 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1699 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1701 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1702 // stored to the VarArgsFrameIndex on the stack.
1704 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1705 SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1706 SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1707 MemOps.push_back(Store);
1708 // Increment the address by four for the next argument to store
1709 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1710 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1714 // If this function is vararg, store any remaining integer argument regs
1715 // to their spots on the stack so that they may be loaded by deferencing the
1716 // result of va_next.
1717 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1720 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1722 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1724 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1725 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1726 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1727 MemOps.push_back(Store);
1728 // Increment the address by four for the next argument to store
1729 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1730 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1733 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1736 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1737 SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1738 SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1739 MemOps.push_back(Store);
1740 // Increment the address by eight for the next argument to store
1741 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1743 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1746 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1748 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1750 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1751 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1752 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1753 MemOps.push_back(Store);
1754 // Increment the address by eight for the next argument to store
1755 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1757 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1762 if (!MemOps.empty())
1763 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1765 ArgValues.push_back(Root);
1767 // Return the new list of results.
1768 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
1772 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
1775 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
1781 unsigned &nAltivecParamsAtEnd) {
1782 // Count how many bytes are to be pushed on the stack, including the linkage
1783 // area, and parameter passing area. We start with 24/48 bytes, which is
1784 // prereserved space for [SP][CR][LR][3 x unused].
1785 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1786 unsigned NumOps = (Call.getNumOperands() - 5) / 2;
1787 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1789 // Add up all the space actually used.
1790 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
1791 // they all go in registers, but we must reserve stack space for them for
1792 // possible use by the caller. In varargs or 64-bit calls, parameters are
1793 // assigned stack space in order, with padding so Altivec parameters are
1795 nAltivecParamsAtEnd = 0;
1796 for (unsigned i = 0; i != NumOps; ++i) {
1797 SDValue Arg = Call.getOperand(5+2*i);
1798 SDValue Flag = Call.getOperand(5+2*i+1);
1799 MVT ArgVT = Arg.getValueType();
1800 // Varargs Altivec parameters are padded to a 16 byte boundary.
1801 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
1802 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
1803 if (!isVarArg && !isPPC64) {
1804 // Non-varargs Altivec parameters go after all the non-Altivec
1805 // parameters; handle those later so we know how much padding we need.
1806 nAltivecParamsAtEnd++;
1809 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
1810 NumBytes = ((NumBytes+15)/16)*16;
1812 NumBytes += CalculateStackSlotSize(Arg, Flag, isVarArg, PtrByteSize);
1815 // Allow for Altivec parameters at the end, if needed.
1816 if (nAltivecParamsAtEnd) {
1817 NumBytes = ((NumBytes+15)/16)*16;
1818 NumBytes += 16*nAltivecParamsAtEnd;
1821 // The prolog code of the callee may store up to 8 GPR argument registers to
1822 // the stack, allowing va_start to index over them in memory if its varargs.
1823 // Because we cannot tell if this is needed on the caller side, we have to
1824 // conservatively assume that it is needed. As such, make sure we have at
1825 // least enough stack space for the caller to store the 8 GPRs.
1826 NumBytes = std::max(NumBytes,
1827 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1829 // Tail call needs the stack to be aligned.
1830 if (CC==CallingConv::Fast && PerformTailCallOpt) {
1831 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1832 getStackAlignment();
1833 unsigned AlignMask = TargetAlign-1;
1834 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
1840 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
1841 /// adjusted to accomodate the arguments for the tailcall.
1842 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
1843 unsigned ParamSize) {
1845 if (!IsTailCall) return 0;
1847 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
1848 unsigned CallerMinReservedArea = FI->getMinReservedArea();
1849 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
1850 // Remember only if the new adjustement is bigger.
1851 if (SPDiff < FI->getTailCallSPDelta())
1852 FI->setTailCallSPDelta(SPDiff);
1857 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1858 /// following the call is a return. A function is eligible if caller/callee
1859 /// calling conventions match, currently only fastcc supports tail calls, and
1860 /// the function CALL is immediatly followed by a RET.
1862 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
1864 SelectionDAG& DAG) const {
1865 // Variable argument functions are not supported.
1866 if (!PerformTailCallOpt ||
1867 cast<ConstantSDNode>(Call.getOperand(2))->getValue() != 0) return false;
1869 if (CheckTailCallReturnConstraints(Call, Ret)) {
1870 MachineFunction &MF = DAG.getMachineFunction();
1871 unsigned CallerCC = MF.getFunction()->getCallingConv();
1872 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1873 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1874 // Functions containing by val parameters are not supported.
1875 for (unsigned i = 0; i != ((Call.getNumOperands()-5)/2); i++) {
1876 ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Call.getOperand(5+2*i+1))
1878 if (Flags.isByVal()) return false;
1881 SDValue Callee = Call.getOperand(4);
1882 // Non PIC/GOT tail calls are supported.
1883 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1886 // At the moment we can only do local tail calls (in same module, hidden
1887 // or protected) if we are generating PIC.
1888 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1889 return G->getGlobal()->hasHiddenVisibility()
1890 || G->getGlobal()->hasProtectedVisibility();
1897 /// isCallCompatibleAddress - Return the immediate to use if the specified
1898 /// 32-bit value is representable in the immediate field of a BxA instruction.
1899 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
1900 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1903 int Addr = C->getValue();
1904 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1905 (Addr << 6 >> 6) != Addr)
1906 return 0; // Top 6 bits have to be sext of immediate.
1908 return DAG.getConstant((int)C->getValue() >> 2,
1909 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
1914 struct TailCallArgumentInfo {
1919 TailCallArgumentInfo() : FrameIdx(0) {}
1924 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
1926 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
1928 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
1929 SmallVector<SDValue, 8> &MemOpChains) {
1930 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
1931 SDValue Arg = TailCallArgs[i].Arg;
1932 SDValue FIN = TailCallArgs[i].FrameIdxOp;
1933 int FI = TailCallArgs[i].FrameIdx;
1934 // Store relative to framepointer.
1935 MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN,
1936 PseudoSourceValue::getFixedStack(FI),
1941 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
1942 /// the appropriate stack slot for the tail call optimized function call.
1943 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
1944 MachineFunction &MF,
1952 // Calculate the new stack slot for the return address.
1953 int SlotSize = isPPC64 ? 8 : 4;
1954 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
1956 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
1958 int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
1960 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
1962 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
1963 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
1964 Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx,
1965 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
1966 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
1967 Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx,
1968 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
1973 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
1974 /// the position of the argument.
1976 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
1977 SDValue Arg, int SPDiff, unsigned ArgOffset,
1978 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
1979 int Offset = ArgOffset + SPDiff;
1980 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
1981 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1982 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
1983 SDValue FIN = DAG.getFrameIndex(FI, VT);
1984 TailCallArgumentInfo Info;
1986 Info.FrameIdxOp = FIN;
1988 TailCallArguments.push_back(Info);
1991 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
1992 /// stack slot. Returns the chain as result and the loaded frame pointers in
1993 /// LROpOut/FPOpout. Used when tail calling.
1994 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2000 // Load the LR and FP stack slot for later adjusting.
2001 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2002 LROpOut = getReturnAddrFrameIndex(DAG);
2003 LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
2004 Chain = SDValue(LROpOut.getNode(), 1);
2005 FPOpOut = getFramePointerFrameIndex(DAG);
2006 FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0);
2007 Chain = SDValue(FPOpOut.getNode(), 1);
2012 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2013 /// by "Src" to address "Dst" of size "Size". Alignment information is
2014 /// specified by the specific parameter attribute. The copy will be passed as
2015 /// a byval function parameter.
2016 /// Sometimes what we are copying is the end of a larger object, the part that
2017 /// does not fit in registers.
2019 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2020 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2022 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
2023 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false,
2027 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2030 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2031 SDValue Arg, SDValue PtrOff, int SPDiff,
2032 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2033 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2034 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2035 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2040 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2042 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2043 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
2044 DAG.getConstant(ArgOffset, PtrVT));
2046 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
2047 // Calculate and remember argument location.
2048 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2052 SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
2053 const PPCSubtarget &Subtarget,
2054 TargetMachine &TM) {
2055 SDValue Chain = Op.getOperand(0);
2056 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
2057 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2058 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 &&
2059 CC == CallingConv::Fast && PerformTailCallOpt;
2060 SDValue Callee = Op.getOperand(4);
2061 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
2063 bool isMachoABI = Subtarget.isMachoABI();
2064 bool isELF32_ABI = Subtarget.isELF32_ABI();
2066 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2067 bool isPPC64 = PtrVT == MVT::i64;
2068 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2070 MachineFunction &MF = DAG.getMachineFunction();
2072 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
2073 // SelectExpr to use to put the arguments in the appropriate registers.
2074 std::vector<SDValue> args_to_use;
2076 // Mark this function as potentially containing a function that contains a
2077 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2078 // and restoring the callers stack pointer in this functions epilog. This is
2079 // done because by tail calling the called function might overwrite the value
2080 // in this function's (MF) stack pointer stack slot 0(SP).
2081 if (PerformTailCallOpt && CC==CallingConv::Fast)
2082 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2084 unsigned nAltivecParamsAtEnd = 0;
2086 // Count how many bytes are to be pushed on the stack, including the linkage
2087 // area, and parameter passing area. We start with 24/48 bytes, which is
2088 // prereserved space for [SP][CR][LR][3 x unused].
2090 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC,
2091 Op, nAltivecParamsAtEnd);
2093 // Calculate by how many bytes the stack has to be adjusted in case of tail
2094 // call optimization.
2095 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2097 // Adjust the stack pointer for the new arguments...
2098 // These operations are automatically eliminated by the prolog/epilog pass
2099 Chain = DAG.getCALLSEQ_START(Chain,
2100 DAG.getConstant(NumBytes, PtrVT));
2101 SDValue CallSeqStart = Chain;
2103 // Load the return address and frame pointer so it can be move somewhere else
2106 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp);
2108 // Set up a copy of the stack pointer for use loading and storing any
2109 // arguments that may not fit in the registers available for argument
2113 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2115 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2117 // Figure out which arguments are going to go in registers, and which in
2118 // memory. Also, if this is a vararg function, floating point operations
2119 // must be stored to our stack, and loaded into integer regs as well, if
2120 // any integer regs are available for argument passing.
2121 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
2122 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2124 static const unsigned GPR_32[] = { // 32-bit registers.
2125 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2126 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2128 static const unsigned GPR_64[] = { // 64-bit registers.
2129 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2130 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2132 static const unsigned *FPR = GetFPR(Subtarget);
2134 static const unsigned VR[] = {
2135 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2136 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2138 const unsigned NumGPRs = array_lengthof(GPR_32);
2139 const unsigned NumFPRs = isMachoABI ? 13 : 8;
2140 const unsigned NumVRs = array_lengthof( VR);
2142 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2144 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
2145 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2147 SmallVector<SDValue, 8> MemOpChains;
2148 for (unsigned i = 0; i != NumOps; ++i) {
2150 SDValue Arg = Op.getOperand(5+2*i);
2151 ISD::ArgFlagsTy Flags =
2152 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
2153 // See if next argument requires stack alignment in ELF
2154 bool Align = Flags.isSplit();
2156 // PtrOff will be used to store the current argument to the stack if a
2157 // register cannot be found for it.
2160 // Stack align in ELF 32
2161 if (isELF32_ABI && Align)
2162 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
2163 StackPtr.getValueType());
2165 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2167 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
2169 // On PPC64, promote integers to 64-bit values.
2170 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2171 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2172 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2173 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
2176 // FIXME Elf untested, what are alignment rules?
2177 // FIXME memcpy is used way more than necessary. Correctness first.
2178 if (Flags.isByVal()) {
2179 unsigned Size = Flags.getByValSize();
2180 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2181 if (Size==1 || Size==2) {
2182 // Very small objects are passed right-justified.
2183 // Everything else is passed left-justified.
2184 MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2185 if (GPR_idx != NumGPRs) {
2186 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
2188 MemOpChains.push_back(Load.getValue(1));
2189 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2191 ArgOffset += PtrByteSize;
2193 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2194 SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
2195 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2196 CallSeqStart.getNode()->getOperand(0),
2198 // This must go outside the CALLSEQ_START..END.
2199 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2200 CallSeqStart.getNode()->getOperand(1));
2201 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2202 Chain = CallSeqStart = NewCallSeqStart;
2203 ArgOffset += PtrByteSize;
2207 // Copy entire object into memory. There are cases where gcc-generated
2208 // code assumes it is there, even if it could be put entirely into
2209 // registers. (This is not what the doc says.)
2210 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2211 CallSeqStart.getNode()->getOperand(0),
2213 // This must go outside the CALLSEQ_START..END.
2214 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2215 CallSeqStart.getNode()->getOperand(1));
2216 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2217 Chain = CallSeqStart = NewCallSeqStart;
2218 // And copy the pieces of it that fit into registers.
2219 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2220 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
2221 SDValue AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
2222 if (GPR_idx != NumGPRs) {
2223 SDValue Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
2224 MemOpChains.push_back(Load.getValue(1));
2225 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2227 ArgOffset += PtrByteSize;
2229 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2236 switch (Arg.getValueType().getSimpleVT()) {
2237 default: assert(0 && "Unexpected ValueType for argument!");
2240 // Double word align in ELF
2241 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2242 if (GPR_idx != NumGPRs) {
2243 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2245 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2246 isPPC64, isTailCall, false, MemOpChains,
2250 if (inMem || isMachoABI) {
2251 // Stack align in ELF
2252 if (isELF32_ABI && Align)
2253 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2255 ArgOffset += PtrByteSize;
2260 if (FPR_idx != NumFPRs) {
2261 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
2264 SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
2265 MemOpChains.push_back(Store);
2267 // Float varargs are always shadowed in available integer registers
2268 if (GPR_idx != NumGPRs) {
2269 SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
2270 MemOpChains.push_back(Load.getValue(1));
2271 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2274 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
2275 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
2276 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
2277 SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
2278 MemOpChains.push_back(Load.getValue(1));
2279 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2283 // If we have any FPRs remaining, we may also have GPRs remaining.
2284 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2287 if (GPR_idx != NumGPRs)
2289 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
2290 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
2295 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2296 isPPC64, isTailCall, false, MemOpChains,
2300 if (inMem || isMachoABI) {
2301 // Stack align in ELF
2302 if (isELF32_ABI && Align)
2303 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2307 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
2315 // These go aligned on the stack, or in the corresponding R registers
2316 // when within range. The Darwin PPC ABI doc claims they also go in
2317 // V registers; in fact gcc does this only for arguments that are
2318 // prototyped, not for those that match the ... We do it for all
2319 // arguments, seems to work.
2320 while (ArgOffset % 16 !=0) {
2321 ArgOffset += PtrByteSize;
2322 if (GPR_idx != NumGPRs)
2325 // We could elide this store in the case where the object fits
2326 // entirely in R registers. Maybe later.
2327 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
2328 DAG.getConstant(ArgOffset, PtrVT));
2329 SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
2330 MemOpChains.push_back(Store);
2331 if (VR_idx != NumVRs) {
2332 SDValue Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0);
2333 MemOpChains.push_back(Load.getValue(1));
2334 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
2337 for (unsigned i=0; i<16; i+=PtrByteSize) {
2338 if (GPR_idx == NumGPRs)
2340 SDValue Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
2341 DAG.getConstant(i, PtrVT));
2342 SDValue Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0);
2343 MemOpChains.push_back(Load.getValue(1));
2344 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2349 // Non-varargs Altivec params generally go in registers, but have
2350 // stack space allocated at the end.
2351 if (VR_idx != NumVRs) {
2352 // Doesn't have GPR space allocated.
2353 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
2354 } else if (nAltivecParamsAtEnd==0) {
2355 // We are emitting Altivec params in order.
2356 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2357 isPPC64, isTailCall, true, MemOpChains,
2364 // If all Altivec parameters fit in registers, as they usually do,
2365 // they get stack space following the non-Altivec parameters. We
2366 // don't track this here because nobody below needs it.
2367 // If there are more Altivec parameters than fit in registers emit
2369 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
2371 // Offset is aligned; skip 1st 12 params which go in V registers.
2372 ArgOffset = ((ArgOffset+15)/16)*16;
2374 for (unsigned i = 0; i != NumOps; ++i) {
2375 SDValue Arg = Op.getOperand(5+2*i);
2376 MVT ArgType = Arg.getValueType();
2377 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
2378 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
2381 // We are emitting Altivec params in order.
2382 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2383 isPPC64, isTailCall, true, MemOpChains,
2391 if (!MemOpChains.empty())
2392 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2393 &MemOpChains[0], MemOpChains.size());
2395 // Build a sequence of copy-to-reg nodes chained together with token chain
2396 // and flag operands which copy the outgoing args into the appropriate regs.
2398 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2399 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
2401 InFlag = Chain.getValue(1);
2404 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
2405 if (isVarArg && isELF32_ABI) {
2406 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
2407 Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag);
2408 InFlag = Chain.getValue(1);
2411 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2412 // might overwrite each other in case of tail call optimization.
2414 SmallVector<SDValue, 8> MemOpChains2;
2415 // Do not flag preceeding copytoreg stuff together with the following stuff.
2417 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2419 if (!MemOpChains2.empty())
2420 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2421 &MemOpChains2[0], MemOpChains2.size());
2423 // Store the return address to the appropriate stack slot.
2424 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2425 isPPC64, isMachoABI);
2428 // Emit callseq_end just before tailcall node.
2430 SmallVector<SDValue, 8> CallSeqOps;
2431 SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2432 CallSeqOps.push_back(Chain);
2433 CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes));
2434 CallSeqOps.push_back(DAG.getIntPtrConstant(0));
2435 if (InFlag.getNode())
2436 CallSeqOps.push_back(InFlag);
2437 Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
2439 InFlag = Chain.getValue(1);
2442 std::vector<MVT> NodeTys;
2443 NodeTys.push_back(MVT::Other); // Returns a chain
2444 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2446 SmallVector<SDValue, 8> Ops;
2447 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
2449 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2450 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2451 // node so that legalize doesn't hack it.
2452 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2453 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2454 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2455 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2456 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2457 // If this is an absolute destination address, use the munged value.
2458 Callee = SDValue(Dest, 0);
2460 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2461 // to do the call, we can't use PPCISD::CALL.
2462 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2463 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.getNode()!=0));
2464 InFlag = Chain.getValue(1);
2466 // Copy the callee address into R12/X12 on darwin.
2468 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
2469 Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag);
2470 InFlag = Chain.getValue(1);
2474 NodeTys.push_back(MVT::Other);
2475 NodeTys.push_back(MVT::Flag);
2476 Ops.push_back(Chain);
2477 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
2479 // Add CTR register as callee so a bctr can be emitted later.
2481 Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
2484 // If this is a direct call, pass the chain and the callee.
2485 if (Callee.getNode()) {
2486 Ops.push_back(Chain);
2487 Ops.push_back(Callee);
2489 // If this is a tail call add stack pointer delta.
2491 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2493 // Add argument registers to the end of the list so that they are known live
2495 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2496 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2497 RegsToPass[i].second.getValueType()));
2499 // When performing tail call optimization the callee pops its arguments off
2500 // the stack. Account for this here so these bytes can be pushed back on in
2501 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2502 int BytesCalleePops =
2503 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2505 if (InFlag.getNode())
2506 Ops.push_back(InFlag);
2510 assert(InFlag.getNode() &&
2511 "Flag must be set. Depend on flag being set in LowerRET");
2512 Chain = DAG.getNode(PPCISD::TAILCALL,
2513 Op.getNode()->getVTList(), &Ops[0], Ops.size());
2514 return SDValue(Chain.getNode(), Op.getResNo());
2517 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
2518 InFlag = Chain.getValue(1);
2520 Chain = DAG.getCALLSEQ_END(Chain,
2521 DAG.getConstant(NumBytes, PtrVT),
2522 DAG.getConstant(BytesCalleePops, PtrVT),
2524 if (Op.getNode()->getValueType(0) != MVT::Other)
2525 InFlag = Chain.getValue(1);
2527 SmallVector<SDValue, 16> ResultVals;
2528 SmallVector<CCValAssign, 16> RVLocs;
2529 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
2530 CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
2531 CCInfo.AnalyzeCallResult(Op.getNode(), RetCC_PPC);
2533 // Copy all of the result registers out of their specified physreg.
2534 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2535 CCValAssign &VA = RVLocs[i];
2536 MVT VT = VA.getValVT();
2537 assert(VA.isRegLoc() && "Can only return in registers!");
2538 Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1);
2539 ResultVals.push_back(Chain.getValue(0));
2540 InFlag = Chain.getValue(2);
2543 // If the function returns void, just return the chain.
2547 // Otherwise, merge everything together with a MERGE_VALUES node.
2548 ResultVals.push_back(Chain);
2549 SDValue Res = DAG.getMergeValues(Op.getNode()->getVTList(), &ResultVals[0],
2551 return Res.getValue(Op.getResNo());
2554 SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
2555 TargetMachine &TM) {
2556 SmallVector<CCValAssign, 16> RVLocs;
2557 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
2558 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
2559 CCState CCInfo(CC, isVarArg, TM, RVLocs);
2560 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
2562 // If this is the first return lowered for this function, add the regs to the
2563 // liveout set for the function.
2564 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2565 for (unsigned i = 0; i != RVLocs.size(); ++i)
2566 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2569 SDValue Chain = Op.getOperand(0);
2571 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
2572 if (Chain.getOpcode() == PPCISD::TAILCALL) {
2573 SDValue TailCall = Chain;
2574 SDValue TargetAddress = TailCall.getOperand(1);
2575 SDValue StackAdjustment = TailCall.getOperand(2);
2577 assert(((TargetAddress.getOpcode() == ISD::Register &&
2578 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
2579 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
2580 TargetAddress.getOpcode() == ISD::TargetGlobalAddress ||
2581 isa<ConstantSDNode>(TargetAddress)) &&
2582 "Expecting an global address, external symbol, absolute value or register");
2584 assert(StackAdjustment.getOpcode() == ISD::Constant &&
2585 "Expecting a const value");
2587 SmallVector<SDValue,8> Operands;
2588 Operands.push_back(Chain.getOperand(0));
2589 Operands.push_back(TargetAddress);
2590 Operands.push_back(StackAdjustment);
2591 // Copy registers used by the call. Last operand is a flag so it is not
2593 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
2594 Operands.push_back(Chain.getOperand(i));
2596 return DAG.getNode(PPCISD::TC_RETURN, MVT::Other, &Operands[0],
2602 // Copy the result values into the output registers.
2603 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2604 CCValAssign &VA = RVLocs[i];
2605 assert(VA.isRegLoc() && "Can only return in registers!");
2606 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
2607 Flag = Chain.getValue(1);
2611 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
2613 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
2616 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
2617 const PPCSubtarget &Subtarget) {
2618 // When we pop the dynamic allocation we need to restore the SP link.
2620 // Get the corect type for pointers.
2621 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2623 // Construct the stack pointer operand.
2624 bool IsPPC64 = Subtarget.isPPC64();
2625 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2626 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
2628 // Get the operands for the STACKRESTORE.
2629 SDValue Chain = Op.getOperand(0);
2630 SDValue SaveSP = Op.getOperand(1);
2632 // Load the old link SP.
2633 SDValue LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
2635 // Restore the stack pointer.
2636 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
2638 // Store the old link SP.
2639 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
2645 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
2646 MachineFunction &MF = DAG.getMachineFunction();
2647 bool IsPPC64 = PPCSubTarget.isPPC64();
2648 bool isMachoABI = PPCSubTarget.isMachoABI();
2649 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2651 // Get current frame pointer save index. The users of this index will be
2652 // primarily DYNALLOC instructions.
2653 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2654 int RASI = FI->getReturnAddrSaveIndex();
2656 // If the frame pointer save index hasn't been defined yet.
2658 // Find out what the fix offset of the frame pointer save area.
2659 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI);
2660 // Allocate the frame index for frame pointer save area.
2661 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
2663 FI->setReturnAddrSaveIndex(RASI);
2665 return DAG.getFrameIndex(RASI, PtrVT);
2669 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
2670 MachineFunction &MF = DAG.getMachineFunction();
2671 bool IsPPC64 = PPCSubTarget.isPPC64();
2672 bool isMachoABI = PPCSubTarget.isMachoABI();
2673 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2675 // Get current frame pointer save index. The users of this index will be
2676 // primarily DYNALLOC instructions.
2677 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2678 int FPSI = FI->getFramePointerSaveIndex();
2680 // If the frame pointer save index hasn't been defined yet.
2682 // Find out what the fix offset of the frame pointer save area.
2683 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2685 // Allocate the frame index for frame pointer save area.
2686 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
2688 FI->setFramePointerSaveIndex(FPSI);
2690 return DAG.getFrameIndex(FPSI, PtrVT);
2693 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
2695 const PPCSubtarget &Subtarget) {
2697 SDValue Chain = Op.getOperand(0);
2698 SDValue Size = Op.getOperand(1);
2700 // Get the corect type for pointers.
2701 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2703 SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT,
2704 DAG.getConstant(0, PtrVT), Size);
2705 // Construct a node for the frame pointer save index.
2706 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
2707 // Build a DYNALLOC node.
2708 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
2709 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2710 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2713 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2715 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
2716 // Not FP? Not a fsel.
2717 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
2718 !Op.getOperand(2).getValueType().isFloatingPoint())
2721 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2723 // Cannot handle SETEQ/SETNE.
2724 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDValue();
2726 MVT ResVT = Op.getValueType();
2727 MVT CmpVT = Op.getOperand(0).getValueType();
2728 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2729 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
2731 // If the RHS of the comparison is a 0.0, we don't need to do the
2732 // subtraction at all.
2733 if (isFloatingPointZero(RHS))
2735 default: break; // SETUO etc aren't handled by fsel.
2738 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2741 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2742 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2743 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2746 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2749 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2750 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2751 return DAG.getNode(PPCISD::FSEL, ResVT,
2752 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2757 default: break; // SETUO etc aren't handled by fsel.
2760 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2761 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2762 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2763 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2766 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2767 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2768 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2769 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2772 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2773 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2774 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2775 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2778 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2779 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2780 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2781 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2786 // FIXME: Split this code up when LegalizeDAGTypes lands.
2787 SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
2788 assert(Op.getOperand(0).getValueType().isFloatingPoint());
2789 SDValue Src = Op.getOperand(0);
2790 if (Src.getValueType() == MVT::f32)
2791 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2794 switch (Op.getValueType().getSimpleVT()) {
2795 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2797 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2800 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2804 // Convert the FP value to an int value through memory.
2805 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
2807 // Emit a store to the stack slot.
2808 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2810 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2812 if (Op.getValueType() == MVT::i32)
2813 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2814 DAG.getConstant(4, FIPtr.getValueType()));
2815 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
2818 SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op,
2819 SelectionDAG &DAG) {
2820 assert(Op.getValueType() == MVT::ppcf128);
2821 SDNode *Node = Op.getNode();
2822 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
2823 assert(Node->getOperand(0).getNode()->getOpcode() == ISD::BUILD_PAIR);
2824 SDValue Lo = Node->getOperand(0).getNode()->getOperand(0);
2825 SDValue Hi = Node->getOperand(0).getNode()->getOperand(1);
2827 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2828 // of the long double, and puts FPSCR back the way it was. We do not
2829 // actually model FPSCR.
2830 std::vector<MVT> NodeTys;
2831 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
2833 NodeTys.push_back(MVT::f64); // Return register
2834 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2835 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2836 MFFSreg = Result.getValue(0);
2837 InFlag = Result.getValue(1);
2840 NodeTys.push_back(MVT::Flag); // Returns a flag
2841 Ops[0] = DAG.getConstant(31, MVT::i32);
2843 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2844 InFlag = Result.getValue(0);
2847 NodeTys.push_back(MVT::Flag); // Returns a flag
2848 Ops[0] = DAG.getConstant(30, MVT::i32);
2850 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2851 InFlag = Result.getValue(0);
2854 NodeTys.push_back(MVT::f64); // result of add
2855 NodeTys.push_back(MVT::Flag); // Returns a flag
2859 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2860 FPreg = Result.getValue(0);
2861 InFlag = Result.getValue(1);
2864 NodeTys.push_back(MVT::f64);
2865 Ops[0] = DAG.getConstant(1, MVT::i32);
2869 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
2870 FPreg = Result.getValue(0);
2872 // We know the low half is about to be thrown away, so just use something
2874 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
2877 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2878 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
2879 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
2882 if (Op.getOperand(0).getValueType() == MVT::i64) {
2883 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2884 SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2885 if (Op.getValueType() == MVT::f32)
2886 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2890 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2891 "Unhandled SINT_TO_FP type in custom expander!");
2892 // Since we only generate this in 64-bit mode, we can take advantage of
2893 // 64-bit registers. In particular, sign extend the input value into the
2894 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2895 // then lfd it and fcfid it.
2896 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2897 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2898 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2899 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2901 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2904 // STD the extended value into the stack slot.
2905 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
2906 MachineMemOperand::MOStore, 0, 8, 8);
2907 SDValue Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2908 DAG.getEntryNode(), Ext64, FIdx,
2909 DAG.getMemOperand(MO));
2910 // Load the value as a double.
2911 SDValue Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2913 // FCFID it and return it.
2914 SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2915 if (Op.getValueType() == MVT::f32)
2916 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2920 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
2922 The rounding mode is in bits 30:31 of FPSR, and has the following
2929 FLT_ROUNDS, on the other hand, expects the following:
2936 To perform the conversion, we do:
2937 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2940 MachineFunction &MF = DAG.getMachineFunction();
2941 MVT VT = Op.getValueType();
2942 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2943 std::vector<MVT> NodeTys;
2944 SDValue MFFSreg, InFlag;
2946 // Save FP Control Word to register
2947 NodeTys.push_back(MVT::f64); // return register
2948 NodeTys.push_back(MVT::Flag); // unused in this context
2949 SDValue Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2951 // Save FP register to stack slot
2952 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2953 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2954 SDValue Store = DAG.getStore(DAG.getEntryNode(), Chain,
2955 StackSlot, NULL, 0);
2957 // Load FP Control Word from low 32 bits of stack slot.
2958 SDValue Four = DAG.getConstant(4, PtrVT);
2959 SDValue Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
2960 SDValue CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
2962 // Transform as necessary
2964 DAG.getNode(ISD::AND, MVT::i32,
2965 CWD, DAG.getConstant(3, MVT::i32));
2967 DAG.getNode(ISD::SRL, MVT::i32,
2968 DAG.getNode(ISD::AND, MVT::i32,
2969 DAG.getNode(ISD::XOR, MVT::i32,
2970 CWD, DAG.getConstant(3, MVT::i32)),
2971 DAG.getConstant(3, MVT::i32)),
2972 DAG.getConstant(1, MVT::i8));
2975 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
2977 return DAG.getNode((VT.getSizeInBits() < 16 ?
2978 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
2981 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
2982 MVT VT = Op.getValueType();
2983 unsigned BitWidth = VT.getSizeInBits();
2984 assert(Op.getNumOperands() == 3 &&
2985 VT == Op.getOperand(1).getValueType() &&
2988 // Expand into a bunch of logical ops. Note that these ops
2989 // depend on the PPC behavior for oversized shift amounts.
2990 SDValue Lo = Op.getOperand(0);
2991 SDValue Hi = Op.getOperand(1);
2992 SDValue Amt = Op.getOperand(2);
2993 MVT AmtVT = Amt.getValueType();
2995 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2996 DAG.getConstant(BitWidth, AmtVT), Amt);
2997 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
2998 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
2999 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3000 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3001 DAG.getConstant(-BitWidth, AmtVT));
3002 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
3003 SDValue OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
3004 SDValue OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
3005 SDValue OutOps[] = { OutLo, OutHi };
3006 return DAG.getMergeValues(OutOps, 2);
3009 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3010 MVT VT = Op.getValueType();
3011 unsigned BitWidth = VT.getSizeInBits();
3012 assert(Op.getNumOperands() == 3 &&
3013 VT == Op.getOperand(1).getValueType() &&
3016 // Expand into a bunch of logical ops. Note that these ops
3017 // depend on the PPC behavior for oversized shift amounts.
3018 SDValue Lo = Op.getOperand(0);
3019 SDValue Hi = Op.getOperand(1);
3020 SDValue Amt = Op.getOperand(2);
3021 MVT AmtVT = Amt.getValueType();
3023 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
3024 DAG.getConstant(BitWidth, AmtVT), Amt);
3025 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
3026 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
3027 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3028 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3029 DAG.getConstant(-BitWidth, AmtVT));
3030 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
3031 SDValue OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
3032 SDValue OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
3033 SDValue OutOps[] = { OutLo, OutHi };
3034 return DAG.getMergeValues(OutOps, 2);
3037 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3038 MVT VT = Op.getValueType();
3039 unsigned BitWidth = VT.getSizeInBits();
3040 assert(Op.getNumOperands() == 3 &&
3041 VT == Op.getOperand(1).getValueType() &&
3044 // Expand into a bunch of logical ops, followed by a select_cc.
3045 SDValue Lo = Op.getOperand(0);
3046 SDValue Hi = Op.getOperand(1);
3047 SDValue Amt = Op.getOperand(2);
3048 MVT AmtVT = Amt.getValueType();
3050 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
3051 DAG.getConstant(BitWidth, AmtVT), Amt);
3052 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
3053 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
3054 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3055 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3056 DAG.getConstant(-BitWidth, AmtVT));
3057 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
3058 SDValue OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
3059 SDValue OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
3060 Tmp4, Tmp6, ISD::SETLE);
3061 SDValue OutOps[] = { OutLo, OutHi };
3062 return DAG.getMergeValues(OutOps, 2);
3065 //===----------------------------------------------------------------------===//
3066 // Vector related lowering.
3069 // If this is a vector of constants or undefs, get the bits. A bit in
3070 // UndefBits is set if the corresponding element of the vector is an
3071 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3072 // zero. Return true if this is not an array of constants, false if it is.
3074 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
3075 uint64_t UndefBits[2]) {
3076 // Start with zero'd results.
3077 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
3079 unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
3080 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3081 SDValue OpVal = BV->getOperand(i);
3083 unsigned PartNo = i >= e/2; // In the upper 128 bits?
3084 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
3086 uint64_t EltBits = 0;
3087 if (OpVal.getOpcode() == ISD::UNDEF) {
3088 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
3089 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
3091 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
3092 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
3093 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
3094 assert(CN->getValueType(0) == MVT::f32 &&
3095 "Only one legal FP vector type!");
3096 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
3098 // Nonconstant element.
3102 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
3105 //printf("%llx %llx %llx %llx\n",
3106 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
3110 // If this is a splat (repetition) of a value across the whole vector, return
3111 // the smallest size that splats it. For example, "0x01010101010101..." is a
3112 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3113 // SplatSize = 1 byte.
3114 static bool isConstantSplat(const uint64_t Bits128[2],
3115 const uint64_t Undef128[2],
3116 unsigned &SplatBits, unsigned &SplatUndef,
3117 unsigned &SplatSize) {
3119 // Don't let undefs prevent splats from matching. See if the top 64-bits are
3120 // the same as the lower 64-bits, ignoring undefs.
3121 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
3122 return false; // Can't be a splat if two pieces don't match.
3124 uint64_t Bits64 = Bits128[0] | Bits128[1];
3125 uint64_t Undef64 = Undef128[0] & Undef128[1];
3127 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
3129 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
3130 return false; // Can't be a splat if two pieces don't match.
3132 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
3133 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
3135 // If the top 16-bits are different than the lower 16-bits, ignoring
3136 // undefs, we have an i32 splat.
3137 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
3139 SplatUndef = Undef32;
3144 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
3145 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
3147 // If the top 8-bits are different than the lower 8-bits, ignoring
3148 // undefs, we have an i16 splat.
3149 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
3151 SplatUndef = Undef16;
3156 // Otherwise, we have an 8-bit splat.
3157 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
3158 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
3163 /// BuildSplatI - Build a canonical splati of Val with an element size of
3164 /// SplatSize. Cast the result to VT.
3165 static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT,
3166 SelectionDAG &DAG) {
3167 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3169 static const MVT VTys[] = { // canonical VT to use for each size.
3170 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3173 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3175 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3179 MVT CanonicalVT = VTys[SplatSize-1];
3181 // Build a canonical splat for this value.
3182 SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
3183 SmallVector<SDValue, 8> Ops;
3184 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3185 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
3186 &Ops[0], Ops.size());
3187 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
3190 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3191 /// specified intrinsic ID.
3192 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3194 MVT DestVT = MVT::Other) {
3195 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3196 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
3197 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3200 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3201 /// specified intrinsic ID.
3202 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3203 SDValue Op2, SelectionDAG &DAG,
3204 MVT DestVT = MVT::Other) {
3205 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3206 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
3207 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3211 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3212 /// amount. The result has the specified value type.
3213 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3214 MVT VT, SelectionDAG &DAG) {
3215 // Force LHS/RHS to be the right type.
3216 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
3217 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
3220 for (unsigned i = 0; i != 16; ++i)
3221 Ops[i] = DAG.getConstant(i+Amt, MVT::i8);
3222 SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
3223 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
3224 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
3227 // If this is a case we can't handle, return null and let the default
3228 // expansion code take care of it. If we CAN select this case, and if it
3229 // selects to a single instruction, return Op. Otherwise, if we can codegen
3230 // this case more efficiently than a constant pool load, lower it to the
3231 // sequence of ops that should be used.
3232 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3233 SelectionDAG &DAG) {
3234 // If this is a vector of constants or undefs, get the bits. A bit in
3235 // UndefBits is set if the corresponding element of the vector is an
3236 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3238 uint64_t VectorBits[2];
3239 uint64_t UndefBits[2];
3240 if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits))
3241 return SDValue(); // Not a constant vector.
3243 // If this is a splat (repetition) of a value across the whole vector, return
3244 // the smallest size that splats it. For example, "0x01010101010101..." is a
3245 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3246 // SplatSize = 1 byte.
3247 unsigned SplatBits, SplatUndef, SplatSize;
3248 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
3249 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
3251 // First, handle single instruction cases.
3254 if (SplatBits == 0) {
3255 // Canonicalize all zero vectors to be v4i32.
3256 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3257 SDValue Z = DAG.getConstant(0, MVT::i32);
3258 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
3259 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
3264 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3265 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
3266 if (SextVal >= -16 && SextVal <= 15)
3267 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
3270 // Two instruction sequences.
3272 // If this value is in the range [-32,30] and is even, use:
3273 // tmp = VSPLTI[bhw], result = add tmp, tmp
3274 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3275 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG);
3276 Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res);
3277 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3280 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3281 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3283 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3284 // Make -1 and vspltisw -1:
3285 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
3287 // Make the VSLW intrinsic, computing 0x8000_0000.
3288 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3291 // xor by OnesV to invert it.
3292 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
3293 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3296 // Check to see if this is a wide variety of vsplti*, binop self cases.
3297 unsigned SplatBitSize = SplatSize*8;
3298 static const signed char SplatCsts[] = {
3299 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3300 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3303 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3304 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3305 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3306 int i = SplatCsts[idx];
3308 // Figure out what shift amount will be used by altivec if shifted by i in
3310 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3312 // vsplti + shl self.
3313 if (SextVal == (i << (int)TypeShiftAmt)) {
3314 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3315 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3316 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3317 Intrinsic::ppc_altivec_vslw
3319 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3320 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3323 // vsplti + srl self.
3324 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3325 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3326 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3327 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3328 Intrinsic::ppc_altivec_vsrw
3330 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3331 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3334 // vsplti + sra self.
3335 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3336 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3337 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3338 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3339 Intrinsic::ppc_altivec_vsraw
3341 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3342 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3345 // vsplti + rol self.
3346 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3347 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3348 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3349 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3350 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3351 Intrinsic::ppc_altivec_vrlw
3353 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3354 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3357 // t = vsplti c, result = vsldoi t, t, 1
3358 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3359 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3360 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
3362 // t = vsplti c, result = vsldoi t, t, 2
3363 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3364 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3365 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
3367 // t = vsplti c, result = vsldoi t, t, 3
3368 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3369 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3370 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
3374 // Three instruction sequences.
3376 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3377 if (SextVal >= 0 && SextVal <= 31) {
3378 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
3379 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
3380 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
3381 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
3383 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3384 if (SextVal >= -31 && SextVal <= 0) {
3385 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
3386 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
3387 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
3388 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
3395 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3396 /// the specified operations to build the shuffle.
3397 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3398 SDValue RHS, SelectionDAG &DAG) {
3399 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3400 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3401 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3404 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3416 if (OpNum == OP_COPY) {
3417 if (LHSID == (1*9+2)*9+3) return LHS;
3418 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3422 SDValue OpLHS, OpRHS;
3423 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
3424 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
3426 unsigned ShufIdxs[16];
3428 default: assert(0 && "Unknown i32 permute!");
3430 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3431 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3432 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3433 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3436 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3437 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3438 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3439 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3442 for (unsigned i = 0; i != 16; ++i)
3443 ShufIdxs[i] = (i&3)+0;
3446 for (unsigned i = 0; i != 16; ++i)
3447 ShufIdxs[i] = (i&3)+4;
3450 for (unsigned i = 0; i != 16; ++i)
3451 ShufIdxs[i] = (i&3)+8;
3454 for (unsigned i = 0; i != 16; ++i)
3455 ShufIdxs[i] = (i&3)+12;
3458 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
3460 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
3462 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
3465 for (unsigned i = 0; i != 16; ++i)
3466 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
3468 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
3469 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3472 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3473 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3474 /// return the code it can be lowered into. Worst case, it can always be
3475 /// lowered into a vperm.
3476 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
3477 SelectionDAG &DAG) {
3478 SDValue V1 = Op.getOperand(0);
3479 SDValue V2 = Op.getOperand(1);
3480 SDValue PermMask = Op.getOperand(2);
3482 // Cases that are handled by instructions that take permute immediates
3483 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3484 // selected by the instruction selector.
3485 if (V2.getOpcode() == ISD::UNDEF) {
3486 if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) ||
3487 PPC::isSplatShuffleMask(PermMask.getNode(), 2) ||
3488 PPC::isSplatShuffleMask(PermMask.getNode(), 4) ||
3489 PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) ||
3490 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) ||
3491 PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 ||
3492 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) ||
3493 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) ||
3494 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) ||
3495 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) ||
3496 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) ||
3497 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) {
3502 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3503 // and produce a fixed permutation. If any of these match, do not lower to
3505 if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) ||
3506 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) ||
3507 PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 ||
3508 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) ||
3509 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) ||
3510 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) ||
3511 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) ||
3512 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) ||
3513 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false))
3516 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3517 // perfect shuffle table to emit an optimal matching sequence.
3518 unsigned PFIndexes[4];
3519 bool isFourElementShuffle = true;
3520 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3521 unsigned EltNo = 8; // Start out undef.
3522 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3523 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
3524 continue; // Undef, ignore it.
3526 unsigned ByteSource =
3527 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
3528 if ((ByteSource & 3) != j) {
3529 isFourElementShuffle = false;
3534 EltNo = ByteSource/4;
3535 } else if (EltNo != ByteSource/4) {
3536 isFourElementShuffle = false;
3540 PFIndexes[i] = EltNo;
3543 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3544 // perfect shuffle vector to determine if it is cost effective to do this as
3545 // discrete instructions, or whether we should use a vperm.
3546 if (isFourElementShuffle) {
3547 // Compute the index in the perfect shuffle table.
3548 unsigned PFTableIndex =
3549 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3551 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3552 unsigned Cost = (PFEntry >> 30);
3554 // Determining when to avoid vperm is tricky. Many things affect the cost
3555 // of vperm, particularly how many times the perm mask needs to be computed.
3556 // For example, if the perm mask can be hoisted out of a loop or is already
3557 // used (perhaps because there are multiple permutes with the same shuffle
3558 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3559 // the loop requires an extra register.
3561 // As a compromise, we only emit discrete instructions if the shuffle can be
3562 // generated in 3 or fewer operations. When we have loop information
3563 // available, if this block is within a loop, we should avoid using vperm
3564 // for 3-operation perms and use a constant pool load instead.
3566 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
3569 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3570 // vector that will get spilled to the constant pool.
3571 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3573 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3574 // that it is in input element units, not in bytes. Convert now.
3575 MVT EltVT = V1.getValueType().getVectorElementType();
3576 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
3578 SmallVector<SDValue, 16> ResultMask;
3579 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
3581 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
3584 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
3586 for (unsigned j = 0; j != BytesPerElement; ++j)
3587 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3591 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
3592 &ResultMask[0], ResultMask.size());
3593 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
3596 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3597 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3598 /// information about the intrinsic.
3599 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
3601 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
3604 switch (IntrinsicID) {
3605 default: return false;
3606 // Comparison predicates.
3607 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3608 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3609 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3610 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3611 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3612 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3613 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3614 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3615 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3616 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3617 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3618 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3619 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3621 // Normal Comparisons.
3622 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3623 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3624 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3625 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3626 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3627 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3628 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3629 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3630 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3631 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
3632 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
3633 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
3634 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3639 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3640 /// lower, do it, otherwise return null.
3641 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3642 SelectionDAG &DAG) {
3643 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3644 // opcode number of the comparison.
3647 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3648 return SDValue(); // Don't custom lower most intrinsics.
3650 // If this is a non-dot comparison, make the VCMP node and we are done.
3652 SDValue Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
3653 Op.getOperand(1), Op.getOperand(2),
3654 DAG.getConstant(CompareOpc, MVT::i32));
3655 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
3658 // Create the PPCISD altivec 'dot' comparison node.
3660 Op.getOperand(2), // LHS
3661 Op.getOperand(3), // RHS
3662 DAG.getConstant(CompareOpc, MVT::i32)
3664 std::vector<MVT> VTs;
3665 VTs.push_back(Op.getOperand(2).getValueType());
3666 VTs.push_back(MVT::Flag);
3667 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3669 // Now that we have the comparison, emit a copy from the CR to a GPR.
3670 // This is flagged to the above dot comparison.
3671 SDValue Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
3672 DAG.getRegister(PPC::CR6, MVT::i32),
3673 CompNode.getValue(1));
3675 // Unpack the result based on how the target uses it.
3676 unsigned BitNo; // Bit # of CR6.
3677 bool InvertBit; // Invert result?
3678 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
3679 default: // Can't happen, don't crash on invalid number though.
3680 case 0: // Return the value of the EQ bit of CR6.
3681 BitNo = 0; InvertBit = false;
3683 case 1: // Return the inverted value of the EQ bit of CR6.
3684 BitNo = 0; InvertBit = true;
3686 case 2: // Return the value of the LT bit of CR6.
3687 BitNo = 2; InvertBit = false;
3689 case 3: // Return the inverted value of the LT bit of CR6.
3690 BitNo = 2; InvertBit = true;
3694 // Shift the bit into the low position.
3695 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
3696 DAG.getConstant(8-(3-BitNo), MVT::i32));
3698 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
3699 DAG.getConstant(1, MVT::i32));
3701 // If we are supposed to, toggle the bit.
3703 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
3704 DAG.getConstant(1, MVT::i32));
3708 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
3709 SelectionDAG &DAG) {
3710 // Create a stack slot that is 16-byte aligned.
3711 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3712 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3713 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3714 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3716 // Store the input value into Value#0 of the stack slot.
3717 SDValue Store = DAG.getStore(DAG.getEntryNode(),
3718 Op.getOperand(0), FIdx, NULL, 0);
3720 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
3723 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
3724 if (Op.getValueType() == MVT::v4i32) {
3725 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3727 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3728 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3730 SDValue RHSSwap = // = vrlw RHS, 16
3731 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3733 // Shrinkify inputs to v8i16.
3734 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3735 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3736 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3738 // Low parts multiplied together, generating 32-bit results (we ignore the
3740 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3741 LHS, RHS, DAG, MVT::v4i32);
3743 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3744 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3745 // Shift the high parts up 16 bits.
3746 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3747 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3748 } else if (Op.getValueType() == MVT::v8i16) {
3749 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3751 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
3753 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3754 LHS, RHS, Zero, DAG);
3755 } else if (Op.getValueType() == MVT::v16i8) {
3756 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3758 // Multiply the even 8-bit parts, producing 16-bit sums.
3759 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3760 LHS, RHS, DAG, MVT::v8i16);
3761 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3763 // Multiply the odd 8-bit parts, producing 16-bit sums.
3764 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3765 LHS, RHS, DAG, MVT::v8i16);
3766 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3768 // Merge the results together.
3770 for (unsigned i = 0; i != 8; ++i) {
3771 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3772 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3774 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
3775 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3777 assert(0 && "Unknown mul to lower!");
3782 /// LowerOperation - Provide custom lowering hooks for some operations.
3784 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
3785 switch (Op.getOpcode()) {
3786 default: assert(0 && "Wasn't expecting to be able to lower this!");
3787 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3788 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3789 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3790 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3791 case ISD::SETCC: return LowerSETCC(Op, DAG);
3793 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3794 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3797 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3798 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3800 case ISD::FORMAL_ARGUMENTS:
3801 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3802 VarArgsStackOffset, VarArgsNumGPR,
3803 VarArgsNumFPR, PPCSubTarget);
3805 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget,
3806 getTargetMachine());
3807 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3808 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3809 case ISD::DYNAMIC_STACKALLOC:
3810 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3812 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3813 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3814 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3815 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
3816 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3818 // Lower 64-bit shifts.
3819 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3820 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3821 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3823 // Vector-related lowering.
3824 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3825 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3826 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3827 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3828 case ISD::MUL: return LowerMUL(Op, DAG);
3830 // Frame & Return address.
3831 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3832 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3837 SDNode *PPCTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
3838 switch (N->getOpcode()) {
3839 default: assert(0 && "Wasn't expecting to be able to lower this!");
3840 case ISD::FP_TO_SINT: {
3841 SDValue Res = LowerFP_TO_SINT(SDValue(N, 0), DAG);
3842 // Use MERGE_VALUES to drop the chain result value and get a node with one
3843 // result. This requires turning off getMergeValues simplification, since
3844 // otherwise it will give us Res back.
3845 return DAG.getMergeValues(&Res, 1, false).getNode();
3851 //===----------------------------------------------------------------------===//
3852 // Other Lowering Code
3853 //===----------------------------------------------------------------------===//
3856 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3857 bool is64bit, unsigned BinOpcode) {
3858 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3859 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3861 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3862 MachineFunction *F = BB->getParent();
3863 MachineFunction::iterator It = BB;
3866 unsigned dest = MI->getOperand(0).getReg();
3867 unsigned ptrA = MI->getOperand(1).getReg();
3868 unsigned ptrB = MI->getOperand(2).getReg();
3869 unsigned incr = MI->getOperand(3).getReg();
3871 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
3872 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
3873 F->insert(It, loopMBB);
3874 F->insert(It, exitMBB);
3875 exitMBB->transferSuccessors(BB);
3877 MachineRegisterInfo &RegInfo = F->getRegInfo();
3878 unsigned TmpReg = (!BinOpcode) ? incr :
3879 RegInfo.createVirtualRegister(
3880 is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
3881 (const TargetRegisterClass *) &PPC::G8RCRegClass);
3885 // fallthrough --> loopMBB
3886 BB->addSuccessor(loopMBB);
3889 // l[wd]arx dest, ptr
3890 // add r0, dest, incr
3891 // st[wd]cx. r0, ptr
3893 // fallthrough --> exitMBB
3895 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
3896 .addReg(ptrA).addReg(ptrB);
3898 BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
3899 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
3900 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
3901 BuildMI(BB, TII->get(PPC::BCC))
3902 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
3903 BB->addSuccessor(loopMBB);
3904 BB->addSuccessor(exitMBB);
3913 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
3914 MachineBasicBlock *BB,
3915 bool is8bit, // operation
3916 unsigned BinOpcode) {
3917 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3918 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3919 // In 64 bit mode we have to use 64 bits for addresses, even though the
3920 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
3921 // registers without caring whether they're 32 or 64, but here we're
3922 // doing actual arithmetic on the addresses.
3923 bool is64bit = PPCSubTarget.isPPC64();
3925 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3926 MachineFunction *F = BB->getParent();
3927 MachineFunction::iterator It = BB;
3930 unsigned dest = MI->getOperand(0).getReg();
3931 unsigned ptrA = MI->getOperand(1).getReg();
3932 unsigned ptrB = MI->getOperand(2).getReg();
3933 unsigned incr = MI->getOperand(3).getReg();
3935 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
3936 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
3937 F->insert(It, loopMBB);
3938 F->insert(It, exitMBB);
3939 exitMBB->transferSuccessors(BB);
3941 MachineRegisterInfo &RegInfo = F->getRegInfo();
3942 const TargetRegisterClass *RC =
3943 is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
3944 (const TargetRegisterClass *) &PPC::G8RCRegClass;
3945 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
3946 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
3947 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
3948 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
3949 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
3950 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
3951 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
3952 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
3953 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
3954 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
3955 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
3957 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
3961 // fallthrough --> loopMBB
3962 BB->addSuccessor(loopMBB);
3964 // The 4-byte load must be aligned, while a char or short may be
3965 // anywhere in the word. Hence all this nasty bookkeeping code.
3966 // add ptr1, ptrA, ptrB [copy if ptrA==0]
3967 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
3968 // xor shift, shift1, 24 [16]
3969 // rlwinm ptr, ptr1, 0, 0, 29
3970 // slw incr2, incr, shift
3971 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
3972 // slw mask, mask2, shift
3974 // lwarx tmpDest, ptr
3975 // add tmp, tmpDest, incr2
3976 // andc tmp2, tmpDest, mask
3977 // and tmp3, tmp, mask
3978 // or tmp4, tmp3, tmp2
3981 // fallthrough --> exitMBB
3982 // srw dest, tmpDest, shift
3984 if (ptrA!=PPC::R0) {
3985 Ptr1Reg = RegInfo.createVirtualRegister(RC);
3986 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
3987 .addReg(ptrA).addReg(ptrB);
3991 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
3992 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
3993 BuildMI(BB, TII->get(is64bit ? PPC::XOR8 : PPC::XOR), ShiftReg)
3994 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
3996 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
3997 .addReg(Ptr1Reg).addImm(0).addImm(61);
3999 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
4000 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4001 BuildMI(BB, TII->get(PPC::SLW), Incr2Reg)
4002 .addReg(incr).addReg(ShiftReg);
4004 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
4006 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
4007 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
4009 BuildMI(BB, TII->get(PPC::SLW), MaskReg)
4010 .addReg(Mask2Reg).addReg(ShiftReg);
4013 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
4014 .addReg(PPC::R0).addReg(PtrReg);
4016 BuildMI(BB, TII->get(BinOpcode), TmpReg)
4017 .addReg(Incr2Reg).addReg(TmpDestReg);
4018 BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4019 .addReg(TmpDestReg).addReg(MaskReg);
4020 BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4021 .addReg(TmpReg).addReg(MaskReg);
4022 BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4023 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4024 BuildMI(BB, TII->get(PPC::STWCX))
4025 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4026 BuildMI(BB, TII->get(PPC::BCC))
4027 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4028 BB->addSuccessor(loopMBB);
4029 BB->addSuccessor(exitMBB);
4034 BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4039 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4040 MachineBasicBlock *BB) {
4041 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4043 // To "insert" these instructions we actually have to insert their
4044 // control-flow patterns.
4045 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4046 MachineFunction::iterator It = BB;
4049 MachineFunction *F = BB->getParent();
4051 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4052 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4053 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4054 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4055 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4057 // The incoming instruction knows the destination vreg to set, the
4058 // condition code register to branch on, the true/false values to
4059 // select between, and a branch opcode to use.
4064 // cmpTY ccX, r1, r2
4066 // fallthrough --> copy0MBB
4067 MachineBasicBlock *thisMBB = BB;
4068 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4069 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4070 unsigned SelectPred = MI->getOperand(4).getImm();
4071 BuildMI(BB, TII->get(PPC::BCC))
4072 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4073 F->insert(It, copy0MBB);
4074 F->insert(It, sinkMBB);
4075 // Update machine-CFG edges by transferring all successors of the current
4076 // block to the new block which will contain the Phi node for the select.
4077 sinkMBB->transferSuccessors(BB);
4078 // Next, add the true and fallthrough blocks as its successors.
4079 BB->addSuccessor(copy0MBB);
4080 BB->addSuccessor(sinkMBB);
4083 // %FalseValue = ...
4084 // # fallthrough to sinkMBB
4087 // Update machine-CFG edges
4088 BB->addSuccessor(sinkMBB);
4091 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4094 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4095 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4096 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4098 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4099 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4100 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4101 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4102 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4103 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4104 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4105 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4107 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4108 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4109 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4110 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4111 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4112 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4113 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4114 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4116 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4117 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4118 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4119 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4120 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4121 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4122 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4123 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4125 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4126 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4127 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4128 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4129 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4130 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4131 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4132 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4134 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4135 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
4136 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4137 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
4138 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4139 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
4140 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4141 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
4143 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4144 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4145 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4146 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4147 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4148 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4149 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4150 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4152 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4153 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4154 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4155 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4156 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4157 BB = EmitAtomicBinary(MI, BB, false, 0);
4158 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4159 BB = EmitAtomicBinary(MI, BB, true, 0);
4161 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4162 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4163 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4165 unsigned dest = MI->getOperand(0).getReg();
4166 unsigned ptrA = MI->getOperand(1).getReg();
4167 unsigned ptrB = MI->getOperand(2).getReg();
4168 unsigned oldval = MI->getOperand(3).getReg();
4169 unsigned newval = MI->getOperand(4).getReg();
4171 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4172 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4173 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4174 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4175 F->insert(It, loop1MBB);
4176 F->insert(It, loop2MBB);
4177 F->insert(It, midMBB);
4178 F->insert(It, exitMBB);
4179 exitMBB->transferSuccessors(BB);
4183 // fallthrough --> loopMBB
4184 BB->addSuccessor(loop1MBB);
4187 // l[wd]arx dest, ptr
4188 // cmp[wd] dest, oldval
4191 // st[wd]cx. newval, ptr
4195 // st[wd]cx. dest, ptr
4198 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4199 .addReg(ptrA).addReg(ptrB);
4200 BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4201 .addReg(oldval).addReg(dest);
4202 BuildMI(BB, TII->get(PPC::BCC))
4203 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4204 BB->addSuccessor(loop2MBB);
4205 BB->addSuccessor(midMBB);
4208 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4209 .addReg(newval).addReg(ptrA).addReg(ptrB);
4210 BuildMI(BB, TII->get(PPC::BCC))
4211 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4212 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
4213 BB->addSuccessor(loop1MBB);
4214 BB->addSuccessor(exitMBB);
4217 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4218 .addReg(dest).addReg(ptrA).addReg(ptrB);
4219 BB->addSuccessor(exitMBB);
4224 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4225 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4226 // We must use 64-bit registers for addresses when targeting 64-bit,
4227 // since we're actually doing arithmetic on them. Other registers
4229 bool is64bit = PPCSubTarget.isPPC64();
4230 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4232 unsigned dest = MI->getOperand(0).getReg();
4233 unsigned ptrA = MI->getOperand(1).getReg();
4234 unsigned ptrB = MI->getOperand(2).getReg();
4235 unsigned oldval = MI->getOperand(3).getReg();
4236 unsigned newval = MI->getOperand(4).getReg();
4238 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4239 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4240 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4241 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4242 F->insert(It, loop1MBB);
4243 F->insert(It, loop2MBB);
4244 F->insert(It, midMBB);
4245 F->insert(It, exitMBB);
4246 exitMBB->transferSuccessors(BB);
4248 MachineRegisterInfo &RegInfo = F->getRegInfo();
4249 const TargetRegisterClass *RC =
4250 is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
4251 (const TargetRegisterClass *) &PPC::G8RCRegClass;
4252 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4253 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4254 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4255 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4256 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4257 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4258 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4259 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4260 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4261 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4262 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4263 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4264 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4266 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4269 // fallthrough --> loopMBB
4270 BB->addSuccessor(loop1MBB);
4272 // The 4-byte load must be aligned, while a char or short may be
4273 // anywhere in the word. Hence all this nasty bookkeeping code.
4274 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4275 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4276 // xor shift, shift1, 24 [16]
4277 // rlwinm ptr, ptr1, 0, 0, 29
4278 // slw newval2, newval, shift
4279 // slw oldval2, oldval,shift
4280 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4281 // slw mask, mask2, shift
4282 // and newval3, newval2, mask
4283 // and oldval3, oldval2, mask
4285 // lwarx tmpDest, ptr
4286 // and tmp, tmpDest, mask
4287 // cmpw tmp, oldval3
4290 // andc tmp2, tmpDest, mask
4291 // or tmp4, tmp2, newval3
4296 // stwcx. tmpDest, ptr
4298 // srw dest, tmpDest, shift
4299 if (ptrA!=PPC::R0) {
4300 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4301 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4302 .addReg(ptrA).addReg(ptrB);
4306 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4307 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4308 BuildMI(BB, TII->get(is64bit ? PPC::XOR8 : PPC::XOR), ShiftReg)
4309 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4311 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
4312 .addReg(Ptr1Reg).addImm(0).addImm(61);
4314 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
4315 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4316 BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg)
4317 .addReg(newval).addReg(ShiftReg);
4318 BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg)
4319 .addReg(oldval).addReg(ShiftReg);
4321 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
4323 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
4324 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
4326 BuildMI(BB, TII->get(PPC::SLW), MaskReg)
4327 .addReg(Mask2Reg).addReg(ShiftReg);
4328 BuildMI(BB, TII->get(PPC::AND), NewVal3Reg)
4329 .addReg(NewVal2Reg).addReg(MaskReg);
4330 BuildMI(BB, TII->get(PPC::AND), OldVal3Reg)
4331 .addReg(OldVal2Reg).addReg(MaskReg);
4334 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
4335 .addReg(PPC::R0).addReg(PtrReg);
4336 BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg);
4337 BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0)
4338 .addReg(TmpReg).addReg(OldVal3Reg);
4339 BuildMI(BB, TII->get(PPC::BCC))
4340 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4341 BB->addSuccessor(loop2MBB);
4342 BB->addSuccessor(midMBB);
4345 BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg);
4346 BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg);
4347 BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4348 .addReg(PPC::R0).addReg(PtrReg);
4349 BuildMI(BB, TII->get(PPC::BCC))
4350 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4351 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
4352 BB->addSuccessor(loop1MBB);
4353 BB->addSuccessor(exitMBB);
4356 BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4357 .addReg(PPC::R0).addReg(PtrReg);
4358 BB->addSuccessor(exitMBB);
4363 BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4365 assert(0 && "Unexpected instr type to insert");
4368 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4372 //===----------------------------------------------------------------------===//
4373 // Target Optimization Hooks
4374 //===----------------------------------------------------------------------===//
4376 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4377 DAGCombinerInfo &DCI) const {
4378 TargetMachine &TM = getTargetMachine();
4379 SelectionDAG &DAG = DCI.DAG;
4380 switch (N->getOpcode()) {
4383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4384 if (C->getValue() == 0) // 0 << V -> 0.
4385 return N->getOperand(0);
4389 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4390 if (C->getValue() == 0) // 0 >>u V -> 0.
4391 return N->getOperand(0);
4395 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4396 if (C->getValue() == 0 || // 0 >>s V -> 0.
4397 C->isAllOnesValue()) // -1 >>s V -> -1.
4398 return N->getOperand(0);
4402 case ISD::SINT_TO_FP:
4403 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4404 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4405 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4406 // We allow the src/dst to be either f32/f64, but the intermediate
4407 // type must be i64.
4408 if (N->getOperand(0).getValueType() == MVT::i64 &&
4409 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4410 SDValue Val = N->getOperand(0).getOperand(0);
4411 if (Val.getValueType() == MVT::f32) {
4412 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
4413 DCI.AddToWorklist(Val.getNode());
4416 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
4417 DCI.AddToWorklist(Val.getNode());
4418 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
4419 DCI.AddToWorklist(Val.getNode());
4420 if (N->getValueType(0) == MVT::f32) {
4421 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
4422 DAG.getIntPtrConstant(0));
4423 DCI.AddToWorklist(Val.getNode());
4426 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4427 // If the intermediate type is i32, we can avoid the load/store here
4434 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4435 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4436 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4437 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4438 N->getOperand(1).getValueType() == MVT::i32 &&
4439 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4440 SDValue Val = N->getOperand(1).getOperand(0);
4441 if (Val.getValueType() == MVT::f32) {
4442 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
4443 DCI.AddToWorklist(Val.getNode());
4445 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
4446 DCI.AddToWorklist(Val.getNode());
4448 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
4449 N->getOperand(2), N->getOperand(3));
4450 DCI.AddToWorklist(Val.getNode());
4454 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4455 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
4456 N->getOperand(1).getNode()->hasOneUse() &&
4457 (N->getOperand(1).getValueType() == MVT::i32 ||
4458 N->getOperand(1).getValueType() == MVT::i16)) {
4459 SDValue BSwapOp = N->getOperand(1).getOperand(0);
4460 // Do an any-extend to 32-bits if this is a half-word input.
4461 if (BSwapOp.getValueType() == MVT::i16)
4462 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
4464 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
4465 N->getOperand(2), N->getOperand(3),
4466 DAG.getValueType(N->getOperand(1).getValueType()));
4470 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4471 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
4472 N->getOperand(0).hasOneUse() &&
4473 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4474 SDValue Load = N->getOperand(0);
4475 LoadSDNode *LD = cast<LoadSDNode>(Load);
4476 // Create the byte-swapping load.
4477 std::vector<MVT> VTs;
4478 VTs.push_back(MVT::i32);
4479 VTs.push_back(MVT::Other);
4480 SDValue MO = DAG.getMemOperand(LD->getMemOperand());
4482 LD->getChain(), // Chain
4483 LD->getBasePtr(), // Ptr
4485 DAG.getValueType(N->getValueType(0)) // VT
4487 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
4489 // If this is an i16 load, insert the truncate.
4490 SDValue ResVal = BSLoad;
4491 if (N->getValueType(0) == MVT::i16)
4492 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
4494 // First, combine the bswap away. This makes the value produced by the
4496 DCI.CombineTo(N, ResVal);
4498 // Next, combine the load away, we give it a bogus result value but a real
4499 // chain result. The result value is dead because the bswap is dead.
4500 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
4502 // Return N so it doesn't get rechecked!
4503 return SDValue(N, 0);
4507 case PPCISD::VCMP: {
4508 // If a VCMPo node already exists with exactly the same operands as this
4509 // node, use its result instead of this node (VCMPo computes both a CR6 and
4510 // a normal output).
4512 if (!N->getOperand(0).hasOneUse() &&
4513 !N->getOperand(1).hasOneUse() &&
4514 !N->getOperand(2).hasOneUse()) {
4516 // Scan all of the users of the LHS, looking for VCMPo's that match.
4517 SDNode *VCMPoNode = 0;
4519 SDNode *LHSN = N->getOperand(0).getNode();
4520 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
4522 if (UI->getOpcode() == PPCISD::VCMPo &&
4523 UI->getOperand(1) == N->getOperand(1) &&
4524 UI->getOperand(2) == N->getOperand(2) &&
4525 UI->getOperand(0) == N->getOperand(0)) {
4530 // If there is no VCMPo node, or if the flag value has a single use, don't
4532 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
4535 // Look at the (necessarily single) use of the flag value. If it has a
4536 // chain, this transformation is more complex. Note that multiple things
4537 // could use the value result, which we should ignore.
4538 SDNode *FlagUser = 0;
4539 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
4540 FlagUser == 0; ++UI) {
4541 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
4543 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
4544 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
4551 // If the user is a MFCR instruction, we know this is safe. Otherwise we
4552 // give up for right now.
4553 if (FlagUser->getOpcode() == PPCISD::MFCR)
4554 return SDValue(VCMPoNode, 0);
4559 // If this is a branch on an altivec predicate comparison, lower this so
4560 // that we don't have to do a MFCR: instead, branch directly on CR6. This
4561 // lowering is done pre-legalize, because the legalizer lowers the predicate
4562 // compare down to code that is difficult to reassemble.
4563 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
4564 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
4568 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
4569 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
4570 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
4571 assert(isDot && "Can't compare against a vector result!");
4573 // If this is a comparison against something other than 0/1, then we know
4574 // that the condition is never/always true.
4575 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
4576 if (Val != 0 && Val != 1) {
4577 if (CC == ISD::SETEQ) // Cond never true, remove branch.
4578 return N->getOperand(0);
4579 // Always !=, turn it into an unconditional branch.
4580 return DAG.getNode(ISD::BR, MVT::Other,
4581 N->getOperand(0), N->getOperand(4));
4584 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
4586 // Create the PPCISD altivec 'dot' comparison node.
4587 std::vector<MVT> VTs;
4589 LHS.getOperand(2), // LHS of compare
4590 LHS.getOperand(3), // RHS of compare
4591 DAG.getConstant(CompareOpc, MVT::i32)
4593 VTs.push_back(LHS.getOperand(2).getValueType());
4594 VTs.push_back(MVT::Flag);
4595 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
4597 // Unpack the result based on how the target uses it.
4598 PPC::Predicate CompOpc;
4599 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
4600 default: // Can't happen, don't crash on invalid number though.
4601 case 0: // Branch on the value of the EQ bit of CR6.
4602 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
4604 case 1: // Branch on the inverted value of the EQ bit of CR6.
4605 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
4607 case 2: // Branch on the value of the LT bit of CR6.
4608 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
4610 case 3: // Branch on the inverted value of the LT bit of CR6.
4611 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
4615 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
4616 DAG.getConstant(CompOpc, MVT::i32),
4617 DAG.getRegister(PPC::CR6, MVT::i32),
4618 N->getOperand(4), CompNode.getValue(1));
4627 //===----------------------------------------------------------------------===//
4628 // Inline Assembly Support
4629 //===----------------------------------------------------------------------===//
4631 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4635 const SelectionDAG &DAG,
4636 unsigned Depth) const {
4637 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4638 switch (Op.getOpcode()) {
4640 case PPCISD::LBRX: {
4641 // lhbrx is known to have the top bits cleared out.
4642 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
4643 KnownZero = 0xFFFF0000;
4646 case ISD::INTRINSIC_WO_CHAIN: {
4647 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
4649 case Intrinsic::ppc_altivec_vcmpbfp_p:
4650 case Intrinsic::ppc_altivec_vcmpeqfp_p:
4651 case Intrinsic::ppc_altivec_vcmpequb_p:
4652 case Intrinsic::ppc_altivec_vcmpequh_p:
4653 case Intrinsic::ppc_altivec_vcmpequw_p:
4654 case Intrinsic::ppc_altivec_vcmpgefp_p:
4655 case Intrinsic::ppc_altivec_vcmpgtfp_p:
4656 case Intrinsic::ppc_altivec_vcmpgtsb_p:
4657 case Intrinsic::ppc_altivec_vcmpgtsh_p:
4658 case Intrinsic::ppc_altivec_vcmpgtsw_p:
4659 case Intrinsic::ppc_altivec_vcmpgtub_p:
4660 case Intrinsic::ppc_altivec_vcmpgtuh_p:
4661 case Intrinsic::ppc_altivec_vcmpgtuw_p:
4662 KnownZero = ~1U; // All bits but the low one are known to be zero.
4670 /// getConstraintType - Given a constraint, return the type of
4671 /// constraint it is for this target.
4672 PPCTargetLowering::ConstraintType
4673 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
4674 if (Constraint.size() == 1) {
4675 switch (Constraint[0]) {
4682 return C_RegisterClass;
4685 return TargetLowering::getConstraintType(Constraint);
4688 std::pair<unsigned, const TargetRegisterClass*>
4689 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4691 if (Constraint.size() == 1) {
4692 // GCC RS6000 Constraint Letters
4693 switch (Constraint[0]) {
4696 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
4697 return std::make_pair(0U, PPC::G8RCRegisterClass);
4698 return std::make_pair(0U, PPC::GPRCRegisterClass);
4701 return std::make_pair(0U, PPC::F4RCRegisterClass);
4702 else if (VT == MVT::f64)
4703 return std::make_pair(0U, PPC::F8RCRegisterClass);
4706 return std::make_pair(0U, PPC::VRRCRegisterClass);
4708 return std::make_pair(0U, PPC::CRRCRegisterClass);
4712 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4716 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4717 /// vector. If it is invalid, don't add anything to Ops.
4718 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
4719 std::vector<SDValue>&Ops,
4720 SelectionDAG &DAG) const {
4721 SDValue Result(0,0);
4732 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
4733 if (!CST) return; // Must be an immediate to match.
4734 unsigned Value = CST->getValue();
4736 default: assert(0 && "Unknown constraint letter!");
4737 case 'I': // "I" is a signed 16-bit constant.
4738 if ((short)Value == (int)Value)
4739 Result = DAG.getTargetConstant(Value, Op.getValueType());
4741 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
4742 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
4743 if ((short)Value == 0)
4744 Result = DAG.getTargetConstant(Value, Op.getValueType());
4746 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
4747 if ((Value >> 16) == 0)
4748 Result = DAG.getTargetConstant(Value, Op.getValueType());
4750 case 'M': // "M" is a constant that is greater than 31.
4752 Result = DAG.getTargetConstant(Value, Op.getValueType());
4754 case 'N': // "N" is a positive constant that is an exact power of two.
4755 if ((int)Value > 0 && isPowerOf2_32(Value))
4756 Result = DAG.getTargetConstant(Value, Op.getValueType());
4758 case 'O': // "O" is the constant zero.
4760 Result = DAG.getTargetConstant(Value, Op.getValueType());
4762 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
4763 if ((short)-Value == (int)-Value)
4764 Result = DAG.getTargetConstant(Value, Op.getValueType());
4771 if (Result.getNode()) {
4772 Ops.push_back(Result);
4776 // Handle standard constraint letters.
4777 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
4780 // isLegalAddressingMode - Return true if the addressing mode represented
4781 // by AM is legal for this target, for a load/store of the specified type.
4782 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4783 const Type *Ty) const {
4784 // FIXME: PPC does not allow r+i addressing modes for vectors!
4786 // PPC allows a sign-extended 16-bit immediate field.
4787 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
4790 // No global is ever allowed as a base.
4794 // PPC only support r+r,
4796 case 0: // "r+i" or just "i", depending on HasBaseReg.
4799 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
4801 // Otherwise we have r+r or r+i.
4804 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
4806 // Allow 2*r as r+r.
4809 // No other scales are supported.
4816 /// isLegalAddressImmediate - Return true if the integer value can be used
4817 /// as the offset of the target addressing mode for load / store of the
4819 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
4820 // PPC allows a sign-extended 16-bit immediate field.
4821 return (V > -(1 << 16) && V < (1 << 16)-1);
4824 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
4828 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
4829 // Depths > 0 not supported yet!
4830 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4833 MachineFunction &MF = DAG.getMachineFunction();
4834 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4836 // Just load the return address off the stack.
4837 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
4839 // Make sure the function really does not optimize away the store of the RA
4841 FuncInfo->setLRStoreRequired();
4842 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4845 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
4846 // Depths > 0 not supported yet!
4847 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4850 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4851 bool isPPC64 = PtrVT == MVT::i64;
4853 MachineFunction &MF = DAG.getMachineFunction();
4854 MachineFrameInfo *MFI = MF.getFrameInfo();
4855 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
4856 && MFI->getStackSize();
4859 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
4862 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,