1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Support/CommandLine.h"
36 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
37 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
40 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
41 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
45 // Use _setjmp/_longjmp instead of setjmp/longjmp.
46 setUseUnderscoreSetJmp(true);
47 setUseUnderscoreLongJmp(true);
49 // Set up the register classes.
50 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
51 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
52 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
56 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
60 // PowerPC has pre-inc load and store's.
61 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
66 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
72 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
73 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
75 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
76 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
77 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
78 // This is used in the ppcf128->int sequence. Note it has different semantics
79 // from FP_ROUND: that rounds to nearest, this rounds to zero.
80 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
82 // PowerPC has no intrinsics for these particular operations
83 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
84 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
85 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
87 // PowerPC has no SREM/UREM instructions
88 setOperationAction(ISD::SREM, MVT::i32, Expand);
89 setOperationAction(ISD::UREM, MVT::i32, Expand);
90 setOperationAction(ISD::SREM, MVT::i64, Expand);
91 setOperationAction(ISD::UREM, MVT::i64, Expand);
93 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
94 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
95 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
96 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
97 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
98 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
99 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
100 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
101 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
103 // We don't support sin/cos/sqrt/fmod/pow
104 setOperationAction(ISD::FSIN , MVT::f64, Expand);
105 setOperationAction(ISD::FCOS , MVT::f64, Expand);
106 setOperationAction(ISD::FREM , MVT::f64, Expand);
107 setOperationAction(ISD::FPOW , MVT::f64, Expand);
108 setOperationAction(ISD::FSIN , MVT::f32, Expand);
109 setOperationAction(ISD::FCOS , MVT::f32, Expand);
110 setOperationAction(ISD::FREM , MVT::f32, Expand);
111 setOperationAction(ISD::FPOW , MVT::f32, Expand);
113 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
115 // If we're enabling GP optimizations, use hardware square root
116 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
117 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
118 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
121 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
122 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
124 // PowerPC does not have BSWAP, CTPOP or CTTZ
125 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
126 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
127 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
128 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
129 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
130 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
132 // PowerPC does not have ROTR
133 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
135 // PowerPC does not have Select
136 setOperationAction(ISD::SELECT, MVT::i32, Expand);
137 setOperationAction(ISD::SELECT, MVT::i64, Expand);
138 setOperationAction(ISD::SELECT, MVT::f32, Expand);
139 setOperationAction(ISD::SELECT, MVT::f64, Expand);
141 // PowerPC wants to turn select_cc of FP into fsel when possible.
142 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
145 // PowerPC wants to optimize integer setcc a bit
146 setOperationAction(ISD::SETCC, MVT::i32, Custom);
148 // PowerPC does not have BRCOND which requires SetCC
149 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
151 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
153 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
154 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
156 // PowerPC does not have [U|S]INT_TO_FP
157 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
158 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
160 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
161 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
162 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
163 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
165 // We cannot sextinreg(i1). Expand to shifts.
166 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
168 // Support label based line numbers.
169 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
170 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
172 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
173 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
174 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
175 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
178 // We want to legalize GlobalAddress and ConstantPool nodes into the
179 // appropriate instructions to materialize the address.
180 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
181 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
182 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
183 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
184 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
185 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
186 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
187 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
189 // RET must be custom lowered, to meet ABI requirements
190 setOperationAction(ISD::RET , MVT::Other, Custom);
192 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
193 setOperationAction(ISD::VASTART , MVT::Other, Custom);
195 // VAARG is custom lowered with ELF 32 ABI
196 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
197 setOperationAction(ISD::VAARG, MVT::Other, Custom);
199 setOperationAction(ISD::VAARG, MVT::Other, Expand);
201 // Use the default implementation.
202 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
203 setOperationAction(ISD::VAEND , MVT::Other, Expand);
204 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
205 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
209 // We want to custom lower some of our intrinsics.
210 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
212 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
213 // They also have instructions for converting between i64 and fp.
214 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
215 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
216 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
217 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
218 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
220 // FIXME: disable this lowered code. This generates 64-bit register values,
221 // and we don't model the fact that the top part is clobbered by calls. We
222 // need to flag these together so that the value isn't live across a call.
223 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
225 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
226 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
228 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
229 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
232 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
233 // 64-bit PowerPC implementations can support i64 types directly
234 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
235 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
236 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
238 // 32-bit PowerPC wants to expand i64 shifts itself.
239 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
240 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
241 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
244 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
245 // First set operation action for all vector types to expand. Then we
246 // will selectively turn on ones that can be effectively codegen'd.
247 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
248 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
249 // add/sub are legal for all supported vector VT's.
250 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
251 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
253 // We promote all shuffles to v16i8.
254 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
255 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
257 // We promote all non-typed operations to v4i32.
258 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
259 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
260 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
261 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
262 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
263 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
264 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
265 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
266 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
267 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
268 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
269 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
271 // No other operations are legal.
272 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
273 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
274 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
275 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
276 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
277 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
278 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
279 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
280 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
281 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
282 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
283 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
284 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
285 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
286 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
287 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
288 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
289 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
290 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
293 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
294 // with merges, splats, etc.
295 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
297 setOperationAction(ISD::AND , MVT::v4i32, Legal);
298 setOperationAction(ISD::OR , MVT::v4i32, Legal);
299 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
300 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
301 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
302 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
304 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
305 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
306 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
307 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
309 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
310 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
311 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
312 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
314 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
315 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
317 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
318 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
319 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
320 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
323 setSetCCResultType(MVT::i32);
324 setShiftAmountType(MVT::i32);
325 setSetCCResultContents(ZeroOrOneSetCCResult);
327 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
328 setStackPointerRegisterToSaveRestore(PPC::X1);
329 setExceptionPointerRegister(PPC::X3);
330 setExceptionSelectorRegister(PPC::X4);
332 setStackPointerRegisterToSaveRestore(PPC::R1);
333 setExceptionPointerRegister(PPC::R3);
334 setExceptionSelectorRegister(PPC::R4);
337 // We have target-specific dag combine patterns for the following nodes:
338 setTargetDAGCombine(ISD::SINT_TO_FP);
339 setTargetDAGCombine(ISD::STORE);
340 setTargetDAGCombine(ISD::BR_CC);
341 setTargetDAGCombine(ISD::BSWAP);
343 // Darwin long double math library functions have $LDBL128 appended.
344 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
345 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
346 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
347 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
348 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
349 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
352 computeRegisterProperties();
355 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
358 case PPCISD::FSEL: return "PPCISD::FSEL";
359 case PPCISD::FCFID: return "PPCISD::FCFID";
360 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
361 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
362 case PPCISD::STFIWX: return "PPCISD::STFIWX";
363 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
364 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
365 case PPCISD::VPERM: return "PPCISD::VPERM";
366 case PPCISD::Hi: return "PPCISD::Hi";
367 case PPCISD::Lo: return "PPCISD::Lo";
368 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
369 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
370 case PPCISD::SRL: return "PPCISD::SRL";
371 case PPCISD::SRA: return "PPCISD::SRA";
372 case PPCISD::SHL: return "PPCISD::SHL";
373 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
374 case PPCISD::STD_32: return "PPCISD::STD_32";
375 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
376 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
377 case PPCISD::MTCTR: return "PPCISD::MTCTR";
378 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
379 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
380 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
381 case PPCISD::MFCR: return "PPCISD::MFCR";
382 case PPCISD::VCMP: return "PPCISD::VCMP";
383 case PPCISD::VCMPo: return "PPCISD::VCMPo";
384 case PPCISD::LBRX: return "PPCISD::LBRX";
385 case PPCISD::STBRX: return "PPCISD::STBRX";
386 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
387 case PPCISD::MFFS: return "PPCISD::MFFS";
388 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
389 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
390 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
391 case PPCISD::MTFSF: return "PPCISD::MTFSF";
395 //===----------------------------------------------------------------------===//
396 // Node matching predicates, for use by the tblgen matching code.
397 //===----------------------------------------------------------------------===//
399 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
400 static bool isFloatingPointZero(SDOperand Op) {
401 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
402 return CFP->getValueAPF().isZero();
403 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
404 // Maybe this has already been legalized into the constant pool?
405 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
406 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
407 return CFP->getValueAPF().isZero();
412 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
413 /// true if Op is undef or if it matches the specified value.
414 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
415 return Op.getOpcode() == ISD::UNDEF ||
416 cast<ConstantSDNode>(Op)->getValue() == Val;
419 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
420 /// VPKUHUM instruction.
421 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
423 for (unsigned i = 0; i != 16; ++i)
424 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
427 for (unsigned i = 0; i != 8; ++i)
428 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
429 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
435 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
436 /// VPKUWUM instruction.
437 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
439 for (unsigned i = 0; i != 16; i += 2)
440 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
441 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
444 for (unsigned i = 0; i != 8; i += 2)
445 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
446 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
447 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
448 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
454 /// isVMerge - Common function, used to match vmrg* shuffles.
456 static bool isVMerge(SDNode *N, unsigned UnitSize,
457 unsigned LHSStart, unsigned RHSStart) {
458 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
459 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
460 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
461 "Unsupported merge size!");
463 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
464 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
465 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
466 LHSStart+j+i*UnitSize) ||
467 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
468 RHSStart+j+i*UnitSize))
474 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
475 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
476 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
478 return isVMerge(N, UnitSize, 8, 24);
479 return isVMerge(N, UnitSize, 8, 8);
482 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
483 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
484 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
486 return isVMerge(N, UnitSize, 0, 16);
487 return isVMerge(N, UnitSize, 0, 0);
491 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
492 /// amount, otherwise return -1.
493 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
494 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
495 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
496 // Find the first non-undef value in the shuffle mask.
498 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
501 if (i == 16) return -1; // all undef.
503 // Otherwise, check to see if the rest of the elements are consequtively
504 // numbered from this value.
505 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
506 if (ShiftAmt < i) return -1;
510 // Check the rest of the elements to see if they are consequtive.
511 for (++i; i != 16; ++i)
512 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
515 // Check the rest of the elements to see if they are consequtive.
516 for (++i; i != 16; ++i)
517 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
524 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
525 /// specifies a splat of a single element that is suitable for input to
526 /// VSPLTB/VSPLTH/VSPLTW.
527 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
528 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
529 N->getNumOperands() == 16 &&
530 (EltSize == 1 || EltSize == 2 || EltSize == 4));
532 // This is a splat operation if each element of the permute is the same, and
533 // if the value doesn't reference the second vector.
534 unsigned ElementBase = 0;
535 SDOperand Elt = N->getOperand(0);
536 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
537 ElementBase = EltV->getValue();
539 return false; // FIXME: Handle UNDEF elements too!
541 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
544 // Check that they are consequtive.
545 for (unsigned i = 1; i != EltSize; ++i) {
546 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
547 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
551 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
552 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
553 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
554 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
555 "Invalid VECTOR_SHUFFLE mask!");
556 for (unsigned j = 0; j != EltSize; ++j)
557 if (N->getOperand(i+j) != N->getOperand(j))
564 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
566 bool PPC::isAllNegativeZeroVector(SDNode *N) {
567 assert(N->getOpcode() == ISD::BUILD_VECTOR);
568 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
569 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
570 return CFP->getValueAPF().isNegZero();
574 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
575 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
576 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
577 assert(isSplatShuffleMask(N, EltSize));
578 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
581 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
582 /// by using a vspltis[bhw] instruction of the specified element size, return
583 /// the constant being splatted. The ByteSize field indicates the number of
584 /// bytes of each element [124] -> [bhw].
585 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
586 SDOperand OpVal(0, 0);
588 // If ByteSize of the splat is bigger than the element size of the
589 // build_vector, then we have a case where we are checking for a splat where
590 // multiple elements of the buildvector are folded together into a single
591 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
592 unsigned EltSize = 16/N->getNumOperands();
593 if (EltSize < ByteSize) {
594 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
595 SDOperand UniquedVals[4];
596 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
598 // See if all of the elements in the buildvector agree across.
599 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
600 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
601 // If the element isn't a constant, bail fully out.
602 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
605 if (UniquedVals[i&(Multiple-1)].Val == 0)
606 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
607 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
608 return SDOperand(); // no match.
611 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
612 // either constant or undef values that are identical for each chunk. See
613 // if these chunks can form into a larger vspltis*.
615 // Check to see if all of the leading entries are either 0 or -1. If
616 // neither, then this won't fit into the immediate field.
617 bool LeadingZero = true;
618 bool LeadingOnes = true;
619 for (unsigned i = 0; i != Multiple-1; ++i) {
620 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
622 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
623 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
625 // Finally, check the least significant entry.
627 if (UniquedVals[Multiple-1].Val == 0)
628 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
629 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
631 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
634 if (UniquedVals[Multiple-1].Val == 0)
635 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
636 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
637 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
638 return DAG.getTargetConstant(Val, MVT::i32);
644 // Check to see if this buildvec has a single non-undef value in its elements.
645 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
646 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
648 OpVal = N->getOperand(i);
649 else if (OpVal != N->getOperand(i))
653 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
655 unsigned ValSizeInBytes = 0;
657 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
658 Value = CN->getValue();
659 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
660 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
661 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
662 Value = FloatToBits(CN->getValueAPF().convertToFloat());
666 // If the splat value is larger than the element value, then we can never do
667 // this splat. The only case that we could fit the replicated bits into our
668 // immediate field for would be zero, and we prefer to use vxor for it.
669 if (ValSizeInBytes < ByteSize) return SDOperand();
671 // If the element value is larger than the splat value, cut it in half and
672 // check to see if the two halves are equal. Continue doing this until we
673 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
674 while (ValSizeInBytes > ByteSize) {
675 ValSizeInBytes >>= 1;
677 // If the top half equals the bottom half, we're still ok.
678 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
679 (Value & ((1 << (8*ValSizeInBytes))-1)))
683 // Properly sign extend the value.
684 int ShAmt = (4-ByteSize)*8;
685 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
687 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
688 if (MaskVal == 0) return SDOperand();
690 // Finally, if this value fits in a 5 bit sext field, return it
691 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
692 return DAG.getTargetConstant(MaskVal, MVT::i32);
696 //===----------------------------------------------------------------------===//
697 // Addressing Mode Selection
698 //===----------------------------------------------------------------------===//
700 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
701 /// or 64-bit immediate, and if the value can be accurately represented as a
702 /// sign extension from a 16-bit value. If so, this returns true and the
704 static bool isIntS16Immediate(SDNode *N, short &Imm) {
705 if (N->getOpcode() != ISD::Constant)
708 Imm = (short)cast<ConstantSDNode>(N)->getValue();
709 if (N->getValueType(0) == MVT::i32)
710 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
712 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
714 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
715 return isIntS16Immediate(Op.Val, Imm);
719 /// SelectAddressRegReg - Given the specified addressed, check to see if it
720 /// can be represented as an indexed [r+r] operation. Returns false if it
721 /// can be more efficiently represented with [r+imm].
722 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
726 if (N.getOpcode() == ISD::ADD) {
727 if (isIntS16Immediate(N.getOperand(1), imm))
729 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
732 Base = N.getOperand(0);
733 Index = N.getOperand(1);
735 } else if (N.getOpcode() == ISD::OR) {
736 if (isIntS16Immediate(N.getOperand(1), imm))
737 return false; // r+i can fold it if we can.
739 // If this is an or of disjoint bitfields, we can codegen this as an add
740 // (for better address arithmetic) if the LHS and RHS of the OR are provably
742 uint64_t LHSKnownZero, LHSKnownOne;
743 uint64_t RHSKnownZero, RHSKnownOne;
744 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
747 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
748 // If all of the bits are known zero on the LHS or RHS, the add won't
750 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
751 Base = N.getOperand(0);
752 Index = N.getOperand(1);
761 /// Returns true if the address N can be represented by a base register plus
762 /// a signed 16-bit displacement [r+imm], and if it is not better
763 /// represented as reg+reg.
764 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
765 SDOperand &Base, SelectionDAG &DAG){
766 // If this can be more profitably realized as r+r, fail.
767 if (SelectAddressRegReg(N, Disp, Base, DAG))
770 if (N.getOpcode() == ISD::ADD) {
772 if (isIntS16Immediate(N.getOperand(1), imm)) {
773 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
774 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
775 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
777 Base = N.getOperand(0);
779 return true; // [r+i]
780 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
781 // Match LOAD (ADD (X, Lo(G))).
782 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
783 && "Cannot handle constant offsets yet!");
784 Disp = N.getOperand(1).getOperand(0); // The global address.
785 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
786 Disp.getOpcode() == ISD::TargetConstantPool ||
787 Disp.getOpcode() == ISD::TargetJumpTable);
788 Base = N.getOperand(0);
789 return true; // [&g+r]
791 } else if (N.getOpcode() == ISD::OR) {
793 if (isIntS16Immediate(N.getOperand(1), imm)) {
794 // If this is an or of disjoint bitfields, we can codegen this as an add
795 // (for better address arithmetic) if the LHS and RHS of the OR are
796 // provably disjoint.
797 uint64_t LHSKnownZero, LHSKnownOne;
798 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
799 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
800 // If all of the bits are known zero on the LHS or RHS, the add won't
802 Base = N.getOperand(0);
803 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
807 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
808 // Loading from a constant address.
810 // If this address fits entirely in a 16-bit sext immediate field, codegen
813 if (isIntS16Immediate(CN, Imm)) {
814 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
815 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
819 // Handle 32-bit sext immediates with LIS + addr mode.
820 if (CN->getValueType(0) == MVT::i32 ||
821 (int64_t)CN->getValue() == (int)CN->getValue()) {
822 int Addr = (int)CN->getValue();
824 // Otherwise, break this down into an LIS + disp.
825 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
827 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
828 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
829 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
834 Disp = DAG.getTargetConstant(0, getPointerTy());
835 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
836 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
839 return true; // [r+0]
842 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
843 /// represented as an indexed [r+r] operation.
844 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
847 // Check to see if we can easily represent this as an [r+r] address. This
848 // will fail if it thinks that the address is more profitably represented as
849 // reg+imm, e.g. where imm = 0.
850 if (SelectAddressRegReg(N, Base, Index, DAG))
853 // If the operand is an addition, always emit this as [r+r], since this is
854 // better (for code size, and execution, as the memop does the add for free)
855 // than emitting an explicit add.
856 if (N.getOpcode() == ISD::ADD) {
857 Base = N.getOperand(0);
858 Index = N.getOperand(1);
862 // Otherwise, do it the hard way, using R0 as the base register.
863 Base = DAG.getRegister(PPC::R0, N.getValueType());
868 /// SelectAddressRegImmShift - Returns true if the address N can be
869 /// represented by a base register plus a signed 14-bit displacement
870 /// [r+imm*4]. Suitable for use by STD and friends.
871 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
874 // If this can be more profitably realized as r+r, fail.
875 if (SelectAddressRegReg(N, Disp, Base, DAG))
878 if (N.getOpcode() == ISD::ADD) {
880 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
881 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
882 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
883 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
885 Base = N.getOperand(0);
887 return true; // [r+i]
888 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
889 // Match LOAD (ADD (X, Lo(G))).
890 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
891 && "Cannot handle constant offsets yet!");
892 Disp = N.getOperand(1).getOperand(0); // The global address.
893 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
894 Disp.getOpcode() == ISD::TargetConstantPool ||
895 Disp.getOpcode() == ISD::TargetJumpTable);
896 Base = N.getOperand(0);
897 return true; // [&g+r]
899 } else if (N.getOpcode() == ISD::OR) {
901 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
902 // If this is an or of disjoint bitfields, we can codegen this as an add
903 // (for better address arithmetic) if the LHS and RHS of the OR are
904 // provably disjoint.
905 uint64_t LHSKnownZero, LHSKnownOne;
906 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
907 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
908 // If all of the bits are known zero on the LHS or RHS, the add won't
910 Base = N.getOperand(0);
911 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
915 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
916 // Loading from a constant address. Verify low two bits are clear.
917 if ((CN->getValue() & 3) == 0) {
918 // If this address fits entirely in a 14-bit sext immediate field, codegen
921 if (isIntS16Immediate(CN, Imm)) {
922 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
923 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
927 // Fold the low-part of 32-bit absolute addresses into addr mode.
928 if (CN->getValueType(0) == MVT::i32 ||
929 (int64_t)CN->getValue() == (int)CN->getValue()) {
930 int Addr = (int)CN->getValue();
932 // Otherwise, break this down into an LIS + disp.
933 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
935 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
936 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
937 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
943 Disp = DAG.getTargetConstant(0, getPointerTy());
944 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
945 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
948 return true; // [r+0]
952 /// getPreIndexedAddressParts - returns true by value, base pointer and
953 /// offset pointer and addressing mode by reference if the node's address
954 /// can be legally represented as pre-indexed load / store address.
955 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
957 ISD::MemIndexedMode &AM,
959 // Disabled by default for now.
960 if (!EnablePPCPreinc) return false;
964 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
965 Ptr = LD->getBasePtr();
966 VT = LD->getMemoryVT();
968 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
970 Ptr = ST->getBasePtr();
971 VT = ST->getMemoryVT();
975 // PowerPC doesn't have preinc load/store instructions for vectors.
976 if (MVT::isVector(VT))
979 // TODO: Check reg+reg first.
981 // LDU/STU use reg+imm*4, others use reg+imm.
982 if (VT != MVT::i64) {
984 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
988 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
992 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
993 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
994 // sext i32 to i64 when addr mode is r+i.
995 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
996 LD->getExtensionType() == ISD::SEXTLOAD &&
997 isa<ConstantSDNode>(Offset))
1005 //===----------------------------------------------------------------------===//
1006 // LowerOperation implementation
1007 //===----------------------------------------------------------------------===//
1009 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
1010 MVT::ValueType PtrVT = Op.getValueType();
1011 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1012 Constant *C = CP->getConstVal();
1013 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1014 SDOperand Zero = DAG.getConstant(0, PtrVT);
1016 const TargetMachine &TM = DAG.getTarget();
1018 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1019 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1021 // If this is a non-darwin platform, we don't support non-static relo models
1023 if (TM.getRelocationModel() == Reloc::Static ||
1024 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1025 // Generate non-pic code that has direct accesses to the constant pool.
1026 // The address of the global is just (hi(&g)+lo(&g)).
1027 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1030 if (TM.getRelocationModel() == Reloc::PIC_) {
1031 // With PIC, the first instruction is actually "GR+hi(&G)".
1032 Hi = DAG.getNode(ISD::ADD, PtrVT,
1033 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1036 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1040 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1041 MVT::ValueType PtrVT = Op.getValueType();
1042 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1043 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1044 SDOperand Zero = DAG.getConstant(0, PtrVT);
1046 const TargetMachine &TM = DAG.getTarget();
1048 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1049 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1051 // If this is a non-darwin platform, we don't support non-static relo models
1053 if (TM.getRelocationModel() == Reloc::Static ||
1054 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1055 // Generate non-pic code that has direct accesses to the constant pool.
1056 // The address of the global is just (hi(&g)+lo(&g)).
1057 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1060 if (TM.getRelocationModel() == Reloc::PIC_) {
1061 // With PIC, the first instruction is actually "GR+hi(&G)".
1062 Hi = DAG.getNode(ISD::ADD, PtrVT,
1063 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1066 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1070 static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
1071 assert(0 && "TLS not implemented for PPC.");
1074 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
1075 MVT::ValueType PtrVT = Op.getValueType();
1076 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1077 GlobalValue *GV = GSDN->getGlobal();
1078 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1079 // If it's a debug information descriptor, don't mess with it.
1080 if (DAG.isVerifiedDebugInfoDesc(Op))
1082 SDOperand Zero = DAG.getConstant(0, PtrVT);
1084 const TargetMachine &TM = DAG.getTarget();
1086 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1087 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1089 // If this is a non-darwin platform, we don't support non-static relo models
1091 if (TM.getRelocationModel() == Reloc::Static ||
1092 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1093 // Generate non-pic code that has direct accesses to globals.
1094 // The address of the global is just (hi(&g)+lo(&g)).
1095 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1098 if (TM.getRelocationModel() == Reloc::PIC_) {
1099 // With PIC, the first instruction is actually "GR+hi(&G)".
1100 Hi = DAG.getNode(ISD::ADD, PtrVT,
1101 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1104 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1106 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1109 // If the global is weak or external, we have to go through the lazy
1111 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1114 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1115 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1117 // If we're comparing for equality to zero, expose the fact that this is
1118 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1119 // fold the new nodes.
1120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1121 if (C->isNullValue() && CC == ISD::SETEQ) {
1122 MVT::ValueType VT = Op.getOperand(0).getValueType();
1123 SDOperand Zext = Op.getOperand(0);
1124 if (VT < MVT::i32) {
1126 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1128 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1129 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1130 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1131 DAG.getConstant(Log2b, MVT::i32));
1132 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1134 // Leave comparisons against 0 and -1 alone for now, since they're usually
1135 // optimized. FIXME: revisit this when we can custom lower all setcc
1137 if (C->isAllOnesValue() || C->isNullValue())
1141 // If we have an integer seteq/setne, turn it into a compare against zero
1142 // by xor'ing the rhs with the lhs, which is faster than setting a
1143 // condition register, reading it back out, and masking the correct bit. The
1144 // normal approach here uses sub to do this instead of xor. Using xor exposes
1145 // the result to other bit-twiddling opportunities.
1146 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1147 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1148 MVT::ValueType VT = Op.getValueType();
1149 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1151 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1156 static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1157 int VarArgsFrameIndex,
1158 int VarArgsStackOffset,
1159 unsigned VarArgsNumGPR,
1160 unsigned VarArgsNumFPR,
1161 const PPCSubtarget &Subtarget) {
1163 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1166 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1167 int VarArgsFrameIndex,
1168 int VarArgsStackOffset,
1169 unsigned VarArgsNumGPR,
1170 unsigned VarArgsNumFPR,
1171 const PPCSubtarget &Subtarget) {
1173 if (Subtarget.isMachoABI()) {
1174 // vastart just stores the address of the VarArgsFrameIndex slot into the
1175 // memory location argument.
1176 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1177 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1178 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1179 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
1183 // For ELF 32 ABI we follow the layout of the va_list struct.
1184 // We suppose the given va_list is already allocated.
1187 // char gpr; /* index into the array of 8 GPRs
1188 // * stored in the register save area
1189 // * gpr=0 corresponds to r3,
1190 // * gpr=1 to r4, etc.
1192 // char fpr; /* index into the array of 8 FPRs
1193 // * stored in the register save area
1194 // * fpr=0 corresponds to f1,
1195 // * fpr=1 to f2, etc.
1197 // char *overflow_arg_area;
1198 // /* location on stack that holds
1199 // * the next overflow argument
1201 // char *reg_save_area;
1202 // /* where r3:r10 and f1:f8 (if saved)
1208 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1209 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1212 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1214 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1215 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1217 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8,
1219 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1,
1221 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT);
1223 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1225 // Store first byte : number of int regs
1226 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1227 Op.getOperand(1), SV->getValue(),
1229 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1232 // Store second byte : number of float regs
1233 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr,
1234 SV->getValue(), SV->getOffset());
1235 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1237 // Store second word : arguments given on stack
1238 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr,
1239 SV->getValue(), SV->getOffset());
1240 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1242 // Store third word : arguments given in registers
1243 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(),
1248 #include "PPCGenCallingConv.inc"
1250 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1251 /// depending on which subtarget is selected.
1252 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1253 if (Subtarget.isMachoABI()) {
1254 static const unsigned FPR[] = {
1255 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1256 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1262 static const unsigned FPR[] = {
1263 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1269 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1270 int &VarArgsFrameIndex,
1271 int &VarArgsStackOffset,
1272 unsigned &VarArgsNumGPR,
1273 unsigned &VarArgsNumFPR,
1274 const PPCSubtarget &Subtarget) {
1275 // TODO: add description of PPC stack frame format, or at least some docs.
1277 MachineFunction &MF = DAG.getMachineFunction();
1278 MachineFrameInfo *MFI = MF.getFrameInfo();
1279 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1280 SmallVector<SDOperand, 8> ArgValues;
1281 SDOperand Root = Op.getOperand(0);
1283 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1284 bool isPPC64 = PtrVT == MVT::i64;
1285 bool isMachoABI = Subtarget.isMachoABI();
1286 bool isELF32_ABI = Subtarget.isELF32_ABI();
1287 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1289 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1291 static const unsigned GPR_32[] = { // 32-bit registers.
1292 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1293 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1295 static const unsigned GPR_64[] = { // 64-bit registers.
1296 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1297 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1300 static const unsigned *FPR = GetFPR(Subtarget);
1302 static const unsigned VR[] = {
1303 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1304 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1307 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1308 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1309 const unsigned Num_VR_Regs = array_lengthof( VR);
1311 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1313 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1315 // Add DAG nodes to load the arguments or copy them out of registers. On
1316 // entry to a function on PPC, the arguments start after the linkage area,
1317 // although the first ones are often in registers.
1319 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1320 // represented with two words (long long or double) must be copied to an
1321 // even GPR_idx value or to an even ArgOffset value.
1323 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1325 bool needsLoad = false;
1326 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1327 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1328 unsigned ArgSize = ObjSize;
1329 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1330 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1331 // See if next argument requires stack alignment in ELF
1332 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1333 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1334 (!(Flags & AlignFlag)));
1336 unsigned CurArgOffset = ArgOffset;
1338 default: assert(0 && "Unhandled argument type!");
1340 // Double word align in ELF
1341 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1342 if (GPR_idx != Num_GPR_Regs) {
1343 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1344 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1345 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1349 ArgSize = PtrByteSize;
1351 // Stack align in ELF
1352 if (needsLoad && Expand && isELF32_ABI)
1353 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1354 // All int arguments reserve stack space in Macho ABI.
1355 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1358 case MVT::i64: // PPC64
1359 if (GPR_idx != Num_GPR_Regs) {
1360 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1361 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1362 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1367 // All int arguments reserve stack space in Macho ABI.
1368 if (isMachoABI || needsLoad) ArgOffset += 8;
1373 // Every 4 bytes of argument space consumes one of the GPRs available for
1374 // argument passing.
1375 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1377 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1380 if (FPR_idx != Num_FPR_Regs) {
1382 if (ObjectVT == MVT::f32)
1383 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1385 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1386 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1387 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1393 // Stack align in ELF
1394 if (needsLoad && Expand && isELF32_ABI)
1395 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1396 // All FP arguments reserve stack space in Macho ABI.
1397 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1403 // Note that vector arguments in registers don't reserve stack space.
1404 if (VR_idx != Num_VR_Regs) {
1405 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1406 RegInfo.addLiveIn(VR[VR_idx], VReg);
1407 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1410 // This should be simple, but requires getting 16-byte aligned stack
1412 assert(0 && "Loading VR argument not implemented yet!");
1418 // We need to load the argument to a virtual register if we determined above
1419 // that we ran out of physical registers of the appropriate type
1421 // If the argument is actually used, emit a load from the right stack
1423 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1424 int FI = MFI->CreateFixedObject(ObjSize,
1425 CurArgOffset + (ArgSize - ObjSize));
1426 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1427 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1429 // Don't emit a dead load.
1430 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1434 ArgValues.push_back(ArgVal);
1437 // If the function takes variable number of arguments, make a frame index for
1438 // the start of the first vararg value... for expansion of llvm.va_start.
1439 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1444 VarArgsNumGPR = GPR_idx;
1445 VarArgsNumFPR = FPR_idx;
1447 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1449 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1450 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1451 MVT::getSizeInBits(PtrVT)/8);
1453 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1460 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1462 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1464 SmallVector<SDOperand, 8> MemOps;
1466 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1467 // stored to the VarArgsFrameIndex on the stack.
1469 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1470 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1471 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1472 MemOps.push_back(Store);
1473 // Increment the address by four for the next argument to store
1474 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1475 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1479 // If this function is vararg, store any remaining integer argument regs
1480 // to their spots on the stack so that they may be loaded by deferencing the
1481 // result of va_next.
1482 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1485 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1487 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1489 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1490 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1491 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1492 MemOps.push_back(Store);
1493 // Increment the address by four for the next argument to store
1494 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1495 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1498 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1501 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1502 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1503 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1504 MemOps.push_back(Store);
1505 // Increment the address by eight for the next argument to store
1506 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1508 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1511 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1513 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1515 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1516 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1517 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1518 MemOps.push_back(Store);
1519 // Increment the address by eight for the next argument to store
1520 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1522 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1526 if (!MemOps.empty())
1527 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1530 ArgValues.push_back(Root);
1532 // Return the new list of results.
1533 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1534 Op.Val->value_end());
1535 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1538 /// isCallCompatibleAddress - Return the immediate to use if the specified
1539 /// 32-bit value is representable in the immediate field of a BxA instruction.
1540 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1541 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1544 int Addr = C->getValue();
1545 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1546 (Addr << 6 >> 6) != Addr)
1547 return 0; // Top 6 bits have to be sext of immediate.
1549 return DAG.getConstant((int)C->getValue() >> 2,
1550 DAG.getTargetLoweringInfo().getPointerTy()).Val;
1554 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
1555 const PPCSubtarget &Subtarget) {
1556 SDOperand Chain = Op.getOperand(0);
1557 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1558 SDOperand Callee = Op.getOperand(4);
1559 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1561 bool isMachoABI = Subtarget.isMachoABI();
1562 bool isELF32_ABI = Subtarget.isELF32_ABI();
1564 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1565 bool isPPC64 = PtrVT == MVT::i64;
1566 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1568 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1569 // SelectExpr to use to put the arguments in the appropriate registers.
1570 std::vector<SDOperand> args_to_use;
1572 // Count how many bytes are to be pushed on the stack, including the linkage
1573 // area, and parameter passing area. We start with 24/48 bytes, which is
1574 // prereserved space for [SP][CR][LR][3 x unused].
1575 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1577 // Add up all the space actually used.
1578 for (unsigned i = 0; i != NumOps; ++i) {
1579 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1580 ArgSize = std::max(ArgSize, PtrByteSize);
1581 NumBytes += ArgSize;
1584 // The prolog code of the callee may store up to 8 GPR argument registers to
1585 // the stack, allowing va_start to index over them in memory if its varargs.
1586 // Because we cannot tell if this is needed on the caller side, we have to
1587 // conservatively assume that it is needed. As such, make sure we have at
1588 // least enough stack space for the caller to store the 8 GPRs.
1589 NumBytes = std::max(NumBytes,
1590 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1592 // Adjust the stack pointer for the new arguments...
1593 // These operations are automatically eliminated by the prolog/epilog pass
1594 Chain = DAG.getCALLSEQ_START(Chain,
1595 DAG.getConstant(NumBytes, PtrVT));
1597 // Set up a copy of the stack pointer for use loading and storing any
1598 // arguments that may not fit in the registers available for argument
1602 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1604 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1606 // Figure out which arguments are going to go in registers, and which in
1607 // memory. Also, if this is a vararg function, floating point operations
1608 // must be stored to our stack, and loaded into integer regs as well, if
1609 // any integer regs are available for argument passing.
1610 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1611 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1613 static const unsigned GPR_32[] = { // 32-bit registers.
1614 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1615 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1617 static const unsigned GPR_64[] = { // 64-bit registers.
1618 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1619 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1621 static const unsigned *FPR = GetFPR(Subtarget);
1623 static const unsigned VR[] = {
1624 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1625 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1627 const unsigned NumGPRs = array_lengthof(GPR_32);
1628 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1629 const unsigned NumVRs = array_lengthof( VR);
1631 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1633 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1634 SmallVector<SDOperand, 8> MemOpChains;
1635 for (unsigned i = 0; i != NumOps; ++i) {
1637 SDOperand Arg = Op.getOperand(5+2*i);
1638 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1639 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1640 // See if next argument requires stack alignment in ELF
1641 unsigned next = 5+2*(i+1)+1;
1642 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1643 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1644 (!(Flags & AlignFlag)));
1646 // PtrOff will be used to store the current argument to the stack if a
1647 // register cannot be found for it.
1650 // Stack align in ELF 32
1651 if (isELF32_ABI && Expand)
1652 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1653 StackPtr.getValueType());
1655 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1657 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1659 // On PPC64, promote integers to 64-bit values.
1660 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1661 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1663 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1666 switch (Arg.getValueType()) {
1667 default: assert(0 && "Unexpected ValueType for argument!");
1670 // Double word align in ELF
1671 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1672 if (GPR_idx != NumGPRs) {
1673 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1675 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1678 if (inMem || isMachoABI) {
1679 // Stack align in ELF
1680 if (isELF32_ABI && Expand)
1681 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1683 ArgOffset += PtrByteSize;
1689 // Float varargs need to be promoted to double.
1690 if (Arg.getValueType() == MVT::f32)
1691 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1694 if (FPR_idx != NumFPRs) {
1695 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1698 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1699 MemOpChains.push_back(Store);
1701 // Float varargs are always shadowed in available integer registers
1702 if (GPR_idx != NumGPRs) {
1703 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1704 MemOpChains.push_back(Load.getValue(1));
1705 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1708 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1709 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1710 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1711 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1712 MemOpChains.push_back(Load.getValue(1));
1713 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1717 // If we have any FPRs remaining, we may also have GPRs remaining.
1718 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1721 if (GPR_idx != NumGPRs)
1723 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1724 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1729 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1732 if (inMem || isMachoABI) {
1733 // Stack align in ELF
1734 if (isELF32_ABI && Expand)
1735 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1739 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1746 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1747 assert(VR_idx != NumVRs &&
1748 "Don't support passing more than 12 vector args yet!");
1749 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1753 if (!MemOpChains.empty())
1754 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1755 &MemOpChains[0], MemOpChains.size());
1757 // Build a sequence of copy-to-reg nodes chained together with token chain
1758 // and flag operands which copy the outgoing args into the appropriate regs.
1760 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1761 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1763 InFlag = Chain.getValue(1);
1766 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1767 if (isVarArg && isELF32_ABI) {
1768 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1769 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1770 InFlag = Chain.getValue(1);
1773 std::vector<MVT::ValueType> NodeTys;
1774 NodeTys.push_back(MVT::Other); // Returns a chain
1775 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1777 SmallVector<SDOperand, 8> Ops;
1778 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1780 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1781 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1782 // node so that legalize doesn't hack it.
1783 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1784 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1785 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1786 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1787 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1788 // If this is an absolute destination address, use the munged value.
1789 Callee = SDOperand(Dest, 0);
1791 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1792 // to do the call, we can't use PPCISD::CALL.
1793 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1794 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1795 InFlag = Chain.getValue(1);
1797 // Copy the callee address into R12 on darwin.
1799 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1800 InFlag = Chain.getValue(1);
1804 NodeTys.push_back(MVT::Other);
1805 NodeTys.push_back(MVT::Flag);
1806 Ops.push_back(Chain);
1807 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1811 // If this is a direct call, pass the chain and the callee.
1813 Ops.push_back(Chain);
1814 Ops.push_back(Callee);
1817 // Add argument registers to the end of the list so that they are known live
1819 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1820 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1821 RegsToPass[i].second.getValueType()));
1824 Ops.push_back(InFlag);
1825 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1826 InFlag = Chain.getValue(1);
1828 Chain = DAG.getCALLSEQ_END(Chain,
1829 DAG.getConstant(NumBytes, PtrVT),
1830 DAG.getConstant(0, PtrVT),
1832 if (Op.Val->getValueType(0) != MVT::Other)
1833 InFlag = Chain.getValue(1);
1835 SDOperand ResultVals[3];
1836 unsigned NumResults = 0;
1839 // If the call has results, copy the values out of the ret val registers.
1840 switch (Op.Val->getValueType(0)) {
1841 default: assert(0 && "Unexpected ret value!");
1842 case MVT::Other: break;
1844 if (Op.Val->getValueType(1) == MVT::i32) {
1845 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1846 ResultVals[0] = Chain.getValue(0);
1847 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
1848 Chain.getValue(2)).getValue(1);
1849 ResultVals[1] = Chain.getValue(0);
1851 NodeTys.push_back(MVT::i32);
1853 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1854 ResultVals[0] = Chain.getValue(0);
1857 NodeTys.push_back(MVT::i32);
1860 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1861 ResultVals[0] = Chain.getValue(0);
1863 NodeTys.push_back(MVT::i64);
1866 if (Op.Val->getValueType(1) == MVT::f64) {
1867 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1);
1868 ResultVals[0] = Chain.getValue(0);
1869 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64,
1870 Chain.getValue(2)).getValue(1);
1871 ResultVals[1] = Chain.getValue(0);
1873 NodeTys.push_back(MVT::f64);
1874 NodeTys.push_back(MVT::f64);
1877 // else fall through
1879 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1880 InFlag).getValue(1);
1881 ResultVals[0] = Chain.getValue(0);
1883 NodeTys.push_back(Op.Val->getValueType(0));
1889 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1890 InFlag).getValue(1);
1891 ResultVals[0] = Chain.getValue(0);
1893 NodeTys.push_back(Op.Val->getValueType(0));
1897 NodeTys.push_back(MVT::Other);
1899 // If the function returns void, just return the chain.
1900 if (NumResults == 0)
1903 // Otherwise, merge everything together with a MERGE_VALUES node.
1904 ResultVals[NumResults++] = Chain;
1905 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1906 ResultVals, NumResults);
1907 return Res.getValue(Op.ResNo);
1910 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1911 SmallVector<CCValAssign, 16> RVLocs;
1912 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1913 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1914 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1915 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1917 // If this is the first return lowered for this function, add the regs to the
1918 // liveout set for the function.
1919 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1920 for (unsigned i = 0; i != RVLocs.size(); ++i)
1921 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1924 SDOperand Chain = Op.getOperand(0);
1927 // Copy the result values into the output registers.
1928 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1929 CCValAssign &VA = RVLocs[i];
1930 assert(VA.isRegLoc() && "Can only return in registers!");
1931 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1932 Flag = Chain.getValue(1);
1936 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
1938 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
1941 static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
1942 const PPCSubtarget &Subtarget) {
1943 // When we pop the dynamic allocation we need to restore the SP link.
1945 // Get the corect type for pointers.
1946 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1948 // Construct the stack pointer operand.
1949 bool IsPPC64 = Subtarget.isPPC64();
1950 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
1951 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
1953 // Get the operands for the STACKRESTORE.
1954 SDOperand Chain = Op.getOperand(0);
1955 SDOperand SaveSP = Op.getOperand(1);
1957 // Load the old link SP.
1958 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
1960 // Restore the stack pointer.
1961 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
1963 // Store the old link SP.
1964 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
1967 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1968 const PPCSubtarget &Subtarget) {
1969 MachineFunction &MF = DAG.getMachineFunction();
1970 bool IsPPC64 = Subtarget.isPPC64();
1971 bool isMachoABI = Subtarget.isMachoABI();
1973 // Get current frame pointer save index. The users of this index will be
1974 // primarily DYNALLOC instructions.
1975 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1976 int FPSI = FI->getFramePointerSaveIndex();
1978 // If the frame pointer save index hasn't been defined yet.
1980 // Find out what the fix offset of the frame pointer save area.
1981 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
1983 // Allocate the frame index for frame pointer save area.
1984 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
1986 FI->setFramePointerSaveIndex(FPSI);
1990 SDOperand Chain = Op.getOperand(0);
1991 SDOperand Size = Op.getOperand(1);
1993 // Get the corect type for pointers.
1994 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1996 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
1997 DAG.getConstant(0, PtrVT), Size);
1998 // Construct a node for the frame pointer save index.
1999 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
2000 // Build a DYNALLOC node.
2001 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
2002 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2003 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2007 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2009 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
2010 // Not FP? Not a fsel.
2011 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
2012 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
2015 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2017 // Cannot handle SETEQ/SETNE.
2018 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
2020 MVT::ValueType ResVT = Op.getValueType();
2021 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
2022 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2023 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
2025 // If the RHS of the comparison is a 0.0, we don't need to do the
2026 // subtraction at all.
2027 if (isFloatingPointZero(RHS))
2029 default: break; // SETUO etc aren't handled by fsel.
2033 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2037 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2038 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2039 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2043 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2047 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2048 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2049 return DAG.getNode(PPCISD::FSEL, ResVT,
2050 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2055 default: break; // SETUO etc aren't handled by fsel.
2059 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2060 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2061 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2062 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2066 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2067 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2068 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2069 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2073 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2074 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2075 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2076 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2080 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2081 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2082 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2083 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2088 // FIXME: Split this code up when LegalizeDAGTypes lands.
2089 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2090 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2091 SDOperand Src = Op.getOperand(0);
2092 if (Src.getValueType() == MVT::f32)
2093 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2096 switch (Op.getValueType()) {
2097 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2099 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2102 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2106 // Convert the FP value to an int value through memory.
2107 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
2109 // Emit a store to the stack slot.
2110 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2112 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2114 if (Op.getValueType() == MVT::i32)
2115 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2116 DAG.getConstant(4, FIPtr.getValueType()));
2117 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
2120 static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) {
2121 assert(Op.getValueType() == MVT::ppcf128);
2122 SDNode *Node = Op.Val;
2123 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
2124 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
2125 SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
2126 SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
2128 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2129 // of the long double, and puts FPSCR back the way it was. We do not
2130 // actually model FPSCR.
2131 std::vector<MVT::ValueType> NodeTys;
2132 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
2134 NodeTys.push_back(MVT::f64); // Return register
2135 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2136 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2137 MFFSreg = Result.getValue(0);
2138 InFlag = Result.getValue(1);
2141 NodeTys.push_back(MVT::Flag); // Returns a flag
2142 Ops[0] = DAG.getConstant(31, MVT::i32);
2144 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2145 InFlag = Result.getValue(0);
2148 NodeTys.push_back(MVT::Flag); // Returns a flag
2149 Ops[0] = DAG.getConstant(30, MVT::i32);
2151 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2152 InFlag = Result.getValue(0);
2155 NodeTys.push_back(MVT::f64); // result of add
2156 NodeTys.push_back(MVT::Flag); // Returns a flag
2160 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2161 FPreg = Result.getValue(0);
2162 InFlag = Result.getValue(1);
2165 NodeTys.push_back(MVT::f64);
2166 Ops[0] = DAG.getConstant(1, MVT::i32);
2170 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
2171 FPreg = Result.getValue(0);
2173 // We know the low half is about to be thrown away, so just use something
2175 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
2178 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2179 if (Op.getOperand(0).getValueType() == MVT::i64) {
2180 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2181 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2182 if (Op.getValueType() == MVT::f32)
2183 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2187 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2188 "Unhandled SINT_TO_FP type in custom expander!");
2189 // Since we only generate this in 64-bit mode, we can take advantage of
2190 // 64-bit registers. In particular, sign extend the input value into the
2191 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2192 // then lfd it and fcfid it.
2193 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2194 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2195 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2196 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2198 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2201 // STD the extended value into the stack slot.
2202 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2203 DAG.getEntryNode(), Ext64, FIdx,
2204 DAG.getSrcValue(NULL));
2205 // Load the value as a double.
2206 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2208 // FCFID it and return it.
2209 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2210 if (Op.getValueType() == MVT::f32)
2211 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2215 static SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
2217 The rounding mode is in bits 30:31 of FPSR, and has the following
2224 FLT_ROUNDS, on the other hand, expects the following:
2231 To perform the conversion, we do:
2232 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2235 MachineFunction &MF = DAG.getMachineFunction();
2236 MVT::ValueType VT = Op.getValueType();
2237 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2238 std::vector<MVT::ValueType> NodeTys;
2239 SDOperand MFFSreg, InFlag;
2241 // Save FP Control Word to register
2242 NodeTys.push_back(MVT::f64); // return register
2243 NodeTys.push_back(MVT::Flag); // unused in this context
2244 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2246 // Save FP register to stack slot
2247 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2248 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2249 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
2250 StackSlot, NULL, 0);
2252 // Load FP Control Word from low 32 bits of stack slot.
2253 SDOperand Four = DAG.getConstant(4, PtrVT);
2254 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
2255 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
2257 // Transform as necessary
2259 DAG.getNode(ISD::AND, MVT::i32,
2260 CWD, DAG.getConstant(3, MVT::i32));
2262 DAG.getNode(ISD::SRL, MVT::i32,
2263 DAG.getNode(ISD::AND, MVT::i32,
2264 DAG.getNode(ISD::XOR, MVT::i32,
2265 CWD, DAG.getConstant(3, MVT::i32)),
2266 DAG.getConstant(3, MVT::i32)),
2267 DAG.getConstant(1, MVT::i8));
2270 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
2272 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
2273 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
2276 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2277 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2278 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2280 // Expand into a bunch of logical ops. Note that these ops
2281 // depend on the PPC behavior for oversized shift amounts.
2282 SDOperand Lo = Op.getOperand(0);
2283 SDOperand Hi = Op.getOperand(1);
2284 SDOperand Amt = Op.getOperand(2);
2286 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2287 DAG.getConstant(32, MVT::i32), Amt);
2288 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2289 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2290 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2291 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2292 DAG.getConstant(-32U, MVT::i32));
2293 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2294 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2295 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2296 SDOperand OutOps[] = { OutLo, OutHi };
2297 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2301 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2302 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2303 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2305 // Otherwise, expand into a bunch of logical ops. Note that these ops
2306 // depend on the PPC behavior for oversized shift amounts.
2307 SDOperand Lo = Op.getOperand(0);
2308 SDOperand Hi = Op.getOperand(1);
2309 SDOperand Amt = Op.getOperand(2);
2311 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2312 DAG.getConstant(32, MVT::i32), Amt);
2313 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2314 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2315 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2316 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2317 DAG.getConstant(-32U, MVT::i32));
2318 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2319 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2320 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2321 SDOperand OutOps[] = { OutLo, OutHi };
2322 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2326 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2327 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2328 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2330 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2331 SDOperand Lo = Op.getOperand(0);
2332 SDOperand Hi = Op.getOperand(1);
2333 SDOperand Amt = Op.getOperand(2);
2335 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2336 DAG.getConstant(32, MVT::i32), Amt);
2337 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2338 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2339 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2340 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2341 DAG.getConstant(-32U, MVT::i32));
2342 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2343 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2344 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2345 Tmp4, Tmp6, ISD::SETLE);
2346 SDOperand OutOps[] = { OutLo, OutHi };
2347 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2351 //===----------------------------------------------------------------------===//
2352 // Vector related lowering.
2355 // If this is a vector of constants or undefs, get the bits. A bit in
2356 // UndefBits is set if the corresponding element of the vector is an
2357 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2358 // zero. Return true if this is not an array of constants, false if it is.
2360 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2361 uint64_t UndefBits[2]) {
2362 // Start with zero'd results.
2363 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2365 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2366 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2367 SDOperand OpVal = BV->getOperand(i);
2369 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2370 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2372 uint64_t EltBits = 0;
2373 if (OpVal.getOpcode() == ISD::UNDEF) {
2374 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2375 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2377 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2378 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2379 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2380 assert(CN->getValueType(0) == MVT::f32 &&
2381 "Only one legal FP vector type!");
2382 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
2384 // Nonconstant element.
2388 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2391 //printf("%llx %llx %llx %llx\n",
2392 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2396 // If this is a splat (repetition) of a value across the whole vector, return
2397 // the smallest size that splats it. For example, "0x01010101010101..." is a
2398 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2399 // SplatSize = 1 byte.
2400 static bool isConstantSplat(const uint64_t Bits128[2],
2401 const uint64_t Undef128[2],
2402 unsigned &SplatBits, unsigned &SplatUndef,
2403 unsigned &SplatSize) {
2405 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2406 // the same as the lower 64-bits, ignoring undefs.
2407 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2408 return false; // Can't be a splat if two pieces don't match.
2410 uint64_t Bits64 = Bits128[0] | Bits128[1];
2411 uint64_t Undef64 = Undef128[0] & Undef128[1];
2413 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2415 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2416 return false; // Can't be a splat if two pieces don't match.
2418 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2419 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2421 // If the top 16-bits are different than the lower 16-bits, ignoring
2422 // undefs, we have an i32 splat.
2423 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2425 SplatUndef = Undef32;
2430 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2431 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2433 // If the top 8-bits are different than the lower 8-bits, ignoring
2434 // undefs, we have an i16 splat.
2435 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2437 SplatUndef = Undef16;
2442 // Otherwise, we have an 8-bit splat.
2443 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2444 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2449 /// BuildSplatI - Build a canonical splati of Val with an element size of
2450 /// SplatSize. Cast the result to VT.
2451 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2452 SelectionDAG &DAG) {
2453 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2455 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2456 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2459 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2461 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2465 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2467 // Build a canonical splat for this value.
2468 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2469 SmallVector<SDOperand, 8> Ops;
2470 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2471 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2472 &Ops[0], Ops.size());
2473 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2476 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2477 /// specified intrinsic ID.
2478 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2480 MVT::ValueType DestVT = MVT::Other) {
2481 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2482 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2483 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2486 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2487 /// specified intrinsic ID.
2488 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2489 SDOperand Op2, SelectionDAG &DAG,
2490 MVT::ValueType DestVT = MVT::Other) {
2491 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2492 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2493 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2497 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2498 /// amount. The result has the specified value type.
2499 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2500 MVT::ValueType VT, SelectionDAG &DAG) {
2501 // Force LHS/RHS to be the right type.
2502 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2503 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2506 for (unsigned i = 0; i != 16; ++i)
2507 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2508 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2509 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2510 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2513 // If this is a case we can't handle, return null and let the default
2514 // expansion code take care of it. If we CAN select this case, and if it
2515 // selects to a single instruction, return Op. Otherwise, if we can codegen
2516 // this case more efficiently than a constant pool load, lower it to the
2517 // sequence of ops that should be used.
2518 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2519 // If this is a vector of constants or undefs, get the bits. A bit in
2520 // UndefBits is set if the corresponding element of the vector is an
2521 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2523 uint64_t VectorBits[2];
2524 uint64_t UndefBits[2];
2525 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2526 return SDOperand(); // Not a constant vector.
2528 // If this is a splat (repetition) of a value across the whole vector, return
2529 // the smallest size that splats it. For example, "0x01010101010101..." is a
2530 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2531 // SplatSize = 1 byte.
2532 unsigned SplatBits, SplatUndef, SplatSize;
2533 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2534 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2536 // First, handle single instruction cases.
2539 if (SplatBits == 0) {
2540 // Canonicalize all zero vectors to be v4i32.
2541 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2542 SDOperand Z = DAG.getConstant(0, MVT::i32);
2543 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2544 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2549 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2550 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2551 if (SextVal >= -16 && SextVal <= 15)
2552 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2555 // Two instruction sequences.
2557 // If this value is in the range [-32,30] and is even, use:
2558 // tmp = VSPLTI[bhw], result = add tmp, tmp
2559 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2560 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2561 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2564 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2565 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2567 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2568 // Make -1 and vspltisw -1:
2569 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2571 // Make the VSLW intrinsic, computing 0x8000_0000.
2572 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2575 // xor by OnesV to invert it.
2576 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2577 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2580 // Check to see if this is a wide variety of vsplti*, binop self cases.
2581 unsigned SplatBitSize = SplatSize*8;
2582 static const signed char SplatCsts[] = {
2583 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2584 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2587 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
2588 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2589 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2590 int i = SplatCsts[idx];
2592 // Figure out what shift amount will be used by altivec if shifted by i in
2594 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2596 // vsplti + shl self.
2597 if (SextVal == (i << (int)TypeShiftAmt)) {
2598 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2599 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2600 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2601 Intrinsic::ppc_altivec_vslw
2603 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2604 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2607 // vsplti + srl self.
2608 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2609 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2610 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2611 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2612 Intrinsic::ppc_altivec_vsrw
2614 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2615 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2618 // vsplti + sra self.
2619 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2620 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2621 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2622 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2623 Intrinsic::ppc_altivec_vsraw
2625 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2626 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2629 // vsplti + rol self.
2630 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2631 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2632 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2633 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2634 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2635 Intrinsic::ppc_altivec_vrlw
2637 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2638 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2641 // t = vsplti c, result = vsldoi t, t, 1
2642 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2643 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2644 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2646 // t = vsplti c, result = vsldoi t, t, 2
2647 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2648 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2649 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2651 // t = vsplti c, result = vsldoi t, t, 3
2652 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2653 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2654 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2658 // Three instruction sequences.
2660 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2661 if (SextVal >= 0 && SextVal <= 31) {
2662 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2663 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2664 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
2665 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2667 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2668 if (SextVal >= -31 && SextVal <= 0) {
2669 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2670 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2671 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
2672 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2679 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2680 /// the specified operations to build the shuffle.
2681 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2682 SDOperand RHS, SelectionDAG &DAG) {
2683 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2684 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2685 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2688 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2700 if (OpNum == OP_COPY) {
2701 if (LHSID == (1*9+2)*9+3) return LHS;
2702 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2706 SDOperand OpLHS, OpRHS;
2707 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2708 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2710 unsigned ShufIdxs[16];
2712 default: assert(0 && "Unknown i32 permute!");
2714 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2715 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2716 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2717 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2720 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2721 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2722 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2723 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2726 for (unsigned i = 0; i != 16; ++i)
2727 ShufIdxs[i] = (i&3)+0;
2730 for (unsigned i = 0; i != 16; ++i)
2731 ShufIdxs[i] = (i&3)+4;
2734 for (unsigned i = 0; i != 16; ++i)
2735 ShufIdxs[i] = (i&3)+8;
2738 for (unsigned i = 0; i != 16; ++i)
2739 ShufIdxs[i] = (i&3)+12;
2742 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2744 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2746 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2749 for (unsigned i = 0; i != 16; ++i)
2750 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2752 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2753 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2756 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2757 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2758 /// return the code it can be lowered into. Worst case, it can always be
2759 /// lowered into a vperm.
2760 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2761 SDOperand V1 = Op.getOperand(0);
2762 SDOperand V2 = Op.getOperand(1);
2763 SDOperand PermMask = Op.getOperand(2);
2765 // Cases that are handled by instructions that take permute immediates
2766 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2767 // selected by the instruction selector.
2768 if (V2.getOpcode() == ISD::UNDEF) {
2769 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2770 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2771 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2772 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2773 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2774 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2775 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2776 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2777 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2778 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2779 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2780 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2785 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2786 // and produce a fixed permutation. If any of these match, do not lower to
2788 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2789 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2790 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2791 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2792 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2793 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2794 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2795 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2796 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2799 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2800 // perfect shuffle table to emit an optimal matching sequence.
2801 unsigned PFIndexes[4];
2802 bool isFourElementShuffle = true;
2803 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2804 unsigned EltNo = 8; // Start out undef.
2805 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2806 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2807 continue; // Undef, ignore it.
2809 unsigned ByteSource =
2810 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2811 if ((ByteSource & 3) != j) {
2812 isFourElementShuffle = false;
2817 EltNo = ByteSource/4;
2818 } else if (EltNo != ByteSource/4) {
2819 isFourElementShuffle = false;
2823 PFIndexes[i] = EltNo;
2826 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2827 // perfect shuffle vector to determine if it is cost effective to do this as
2828 // discrete instructions, or whether we should use a vperm.
2829 if (isFourElementShuffle) {
2830 // Compute the index in the perfect shuffle table.
2831 unsigned PFTableIndex =
2832 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2834 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2835 unsigned Cost = (PFEntry >> 30);
2837 // Determining when to avoid vperm is tricky. Many things affect the cost
2838 // of vperm, particularly how many times the perm mask needs to be computed.
2839 // For example, if the perm mask can be hoisted out of a loop or is already
2840 // used (perhaps because there are multiple permutes with the same shuffle
2841 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2842 // the loop requires an extra register.
2844 // As a compromise, we only emit discrete instructions if the shuffle can be
2845 // generated in 3 or fewer operations. When we have loop information
2846 // available, if this block is within a loop, we should avoid using vperm
2847 // for 3-operation perms and use a constant pool load instead.
2849 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2852 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2853 // vector that will get spilled to the constant pool.
2854 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2856 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2857 // that it is in input element units, not in bytes. Convert now.
2858 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
2859 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2861 SmallVector<SDOperand, 16> ResultMask;
2862 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2864 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2867 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2869 for (unsigned j = 0; j != BytesPerElement; ++j)
2870 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2874 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2875 &ResultMask[0], ResultMask.size());
2876 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2879 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2880 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2881 /// information about the intrinsic.
2882 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2884 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2887 switch (IntrinsicID) {
2888 default: return false;
2889 // Comparison predicates.
2890 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2891 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2892 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2893 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2894 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2895 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2896 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2897 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2898 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2899 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2900 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2901 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2902 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2904 // Normal Comparisons.
2905 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2906 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2907 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2908 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2909 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2910 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2911 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2912 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2913 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2914 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2915 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2916 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2917 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2922 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2923 /// lower, do it, otherwise return null.
2924 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2925 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2926 // opcode number of the comparison.
2929 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2930 return SDOperand(); // Don't custom lower most intrinsics.
2932 // If this is a non-dot comparison, make the VCMP node and we are done.
2934 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2935 Op.getOperand(1), Op.getOperand(2),
2936 DAG.getConstant(CompareOpc, MVT::i32));
2937 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2940 // Create the PPCISD altivec 'dot' comparison node.
2942 Op.getOperand(2), // LHS
2943 Op.getOperand(3), // RHS
2944 DAG.getConstant(CompareOpc, MVT::i32)
2946 std::vector<MVT::ValueType> VTs;
2947 VTs.push_back(Op.getOperand(2).getValueType());
2948 VTs.push_back(MVT::Flag);
2949 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2951 // Now that we have the comparison, emit a copy from the CR to a GPR.
2952 // This is flagged to the above dot comparison.
2953 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2954 DAG.getRegister(PPC::CR6, MVT::i32),
2955 CompNode.getValue(1));
2957 // Unpack the result based on how the target uses it.
2958 unsigned BitNo; // Bit # of CR6.
2959 bool InvertBit; // Invert result?
2960 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2961 default: // Can't happen, don't crash on invalid number though.
2962 case 0: // Return the value of the EQ bit of CR6.
2963 BitNo = 0; InvertBit = false;
2965 case 1: // Return the inverted value of the EQ bit of CR6.
2966 BitNo = 0; InvertBit = true;
2968 case 2: // Return the value of the LT bit of CR6.
2969 BitNo = 2; InvertBit = false;
2971 case 3: // Return the inverted value of the LT bit of CR6.
2972 BitNo = 2; InvertBit = true;
2976 // Shift the bit into the low position.
2977 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2978 DAG.getConstant(8-(3-BitNo), MVT::i32));
2980 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2981 DAG.getConstant(1, MVT::i32));
2983 // If we are supposed to, toggle the bit.
2985 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2986 DAG.getConstant(1, MVT::i32));
2990 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2991 // Create a stack slot that is 16-byte aligned.
2992 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2993 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2994 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2995 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2997 // Store the input value into Value#0 of the stack slot.
2998 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2999 Op.getOperand(0), FIdx, NULL, 0);
3001 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
3004 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
3005 if (Op.getValueType() == MVT::v4i32) {
3006 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3008 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3009 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3011 SDOperand RHSSwap = // = vrlw RHS, 16
3012 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3014 // Shrinkify inputs to v8i16.
3015 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3016 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3017 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3019 // Low parts multiplied together, generating 32-bit results (we ignore the
3021 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3022 LHS, RHS, DAG, MVT::v4i32);
3024 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3025 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3026 // Shift the high parts up 16 bits.
3027 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3028 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3029 } else if (Op.getValueType() == MVT::v8i16) {
3030 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3032 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
3034 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3035 LHS, RHS, Zero, DAG);
3036 } else if (Op.getValueType() == MVT::v16i8) {
3037 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3039 // Multiply the even 8-bit parts, producing 16-bit sums.
3040 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3041 LHS, RHS, DAG, MVT::v8i16);
3042 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3044 // Multiply the odd 8-bit parts, producing 16-bit sums.
3045 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3046 LHS, RHS, DAG, MVT::v8i16);
3047 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3049 // Merge the results together.
3051 for (unsigned i = 0; i != 8; ++i) {
3052 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3053 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3055 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
3056 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3058 assert(0 && "Unknown mul to lower!");
3063 /// LowerOperation - Provide custom lowering hooks for some operations.
3065 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3066 switch (Op.getOpcode()) {
3067 default: assert(0 && "Wasn't expecting to be able to lower this!");
3068 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3069 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3070 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3071 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3072 case ISD::SETCC: return LowerSETCC(Op, DAG);
3074 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3075 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3078 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3079 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3081 case ISD::FORMAL_ARGUMENTS:
3082 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3083 VarArgsStackOffset, VarArgsNumGPR,
3084 VarArgsNumFPR, PPCSubTarget);
3086 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
3087 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3088 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3089 case ISD::DYNAMIC_STACKALLOC:
3090 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3092 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3093 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3094 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3095 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
3096 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3098 // Lower 64-bit shifts.
3099 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3100 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3101 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3103 // Vector-related lowering.
3104 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3105 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3106 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3107 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3108 case ISD::MUL: return LowerMUL(Op, DAG);
3110 // Frame & Return address.
3111 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3112 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3117 SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
3118 switch (N->getOpcode()) {
3119 default: assert(0 && "Wasn't expecting to be able to lower this!");
3120 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val;
3125 //===----------------------------------------------------------------------===//
3126 // Other Lowering Code
3127 //===----------------------------------------------------------------------===//
3130 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3131 MachineBasicBlock *BB) {
3132 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3133 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
3134 MI->getOpcode() == PPC::SELECT_CC_I8 ||
3135 MI->getOpcode() == PPC::SELECT_CC_F4 ||
3136 MI->getOpcode() == PPC::SELECT_CC_F8 ||
3137 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
3138 "Unexpected instr type to insert");
3140 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3141 // control-flow pattern. The incoming instruction knows the destination vreg
3142 // to set, the condition code register to branch on, the true/false values to
3143 // select between, and a branch opcode to use.
3144 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3145 ilist<MachineBasicBlock>::iterator It = BB;
3151 // cmpTY ccX, r1, r2
3153 // fallthrough --> copy0MBB
3154 MachineBasicBlock *thisMBB = BB;
3155 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
3156 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
3157 unsigned SelectPred = MI->getOperand(4).getImm();
3158 BuildMI(BB, TII->get(PPC::BCC))
3159 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
3160 MachineFunction *F = BB->getParent();
3161 F->getBasicBlockList().insert(It, copy0MBB);
3162 F->getBasicBlockList().insert(It, sinkMBB);
3163 // Update machine-CFG edges by first adding all successors of the current
3164 // block to the new block which will contain the Phi node for the select.
3165 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
3166 e = BB->succ_end(); i != e; ++i)
3167 sinkMBB->addSuccessor(*i);
3168 // Next, remove all successors of the current block, and add the true
3169 // and fallthrough blocks as its successors.
3170 while(!BB->succ_empty())
3171 BB->removeSuccessor(BB->succ_begin());
3172 BB->addSuccessor(copy0MBB);
3173 BB->addSuccessor(sinkMBB);
3176 // %FalseValue = ...
3177 // # fallthrough to sinkMBB
3180 // Update machine-CFG edges
3181 BB->addSuccessor(sinkMBB);
3184 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3187 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
3188 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
3189 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3191 delete MI; // The pseudo instruction is gone now.
3195 //===----------------------------------------------------------------------===//
3196 // Target Optimization Hooks
3197 //===----------------------------------------------------------------------===//
3199 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3200 DAGCombinerInfo &DCI) const {
3201 TargetMachine &TM = getTargetMachine();
3202 SelectionDAG &DAG = DCI.DAG;
3203 switch (N->getOpcode()) {
3206 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3207 if (C->getValue() == 0) // 0 << V -> 0.
3208 return N->getOperand(0);
3212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3213 if (C->getValue() == 0) // 0 >>u V -> 0.
3214 return N->getOperand(0);
3218 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3219 if (C->getValue() == 0 || // 0 >>s V -> 0.
3220 C->isAllOnesValue()) // -1 >>s V -> -1.
3221 return N->getOperand(0);
3225 case ISD::SINT_TO_FP:
3226 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3227 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3228 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3229 // We allow the src/dst to be either f32/f64, but the intermediate
3230 // type must be i64.
3231 if (N->getOperand(0).getValueType() == MVT::i64 &&
3232 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
3233 SDOperand Val = N->getOperand(0).getOperand(0);
3234 if (Val.getValueType() == MVT::f32) {
3235 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3236 DCI.AddToWorklist(Val.Val);
3239 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3240 DCI.AddToWorklist(Val.Val);
3241 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3242 DCI.AddToWorklist(Val.Val);
3243 if (N->getValueType(0) == MVT::f32) {
3244 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
3245 DAG.getIntPtrConstant(0));
3246 DCI.AddToWorklist(Val.Val);
3249 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3250 // If the intermediate type is i32, we can avoid the load/store here
3257 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3258 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3259 !cast<StoreSDNode>(N)->isTruncatingStore() &&
3260 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3261 N->getOperand(1).getValueType() == MVT::i32 &&
3262 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
3263 SDOperand Val = N->getOperand(1).getOperand(0);
3264 if (Val.getValueType() == MVT::f32) {
3265 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3266 DCI.AddToWorklist(Val.Val);
3268 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3269 DCI.AddToWorklist(Val.Val);
3271 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3272 N->getOperand(2), N->getOperand(3));
3273 DCI.AddToWorklist(Val.Val);
3277 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3278 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3279 N->getOperand(1).Val->hasOneUse() &&
3280 (N->getOperand(1).getValueType() == MVT::i32 ||
3281 N->getOperand(1).getValueType() == MVT::i16)) {
3282 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3283 // Do an any-extend to 32-bits if this is a half-word input.
3284 if (BSwapOp.getValueType() == MVT::i16)
3285 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3287 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3288 N->getOperand(2), N->getOperand(3),
3289 DAG.getValueType(N->getOperand(1).getValueType()));
3293 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3294 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3295 N->getOperand(0).hasOneUse() &&
3296 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3297 SDOperand Load = N->getOperand(0);
3298 LoadSDNode *LD = cast<LoadSDNode>(Load);
3299 // Create the byte-swapping load.
3300 std::vector<MVT::ValueType> VTs;
3301 VTs.push_back(MVT::i32);
3302 VTs.push_back(MVT::Other);
3303 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
3305 LD->getChain(), // Chain
3306 LD->getBasePtr(), // Ptr
3308 DAG.getValueType(N->getValueType(0)) // VT
3310 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3312 // If this is an i16 load, insert the truncate.
3313 SDOperand ResVal = BSLoad;
3314 if (N->getValueType(0) == MVT::i16)
3315 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3317 // First, combine the bswap away. This makes the value produced by the
3319 DCI.CombineTo(N, ResVal);
3321 // Next, combine the load away, we give it a bogus result value but a real
3322 // chain result. The result value is dead because the bswap is dead.
3323 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3325 // Return N so it doesn't get rechecked!
3326 return SDOperand(N, 0);
3330 case PPCISD::VCMP: {
3331 // If a VCMPo node already exists with exactly the same operands as this
3332 // node, use its result instead of this node (VCMPo computes both a CR6 and
3333 // a normal output).
3335 if (!N->getOperand(0).hasOneUse() &&
3336 !N->getOperand(1).hasOneUse() &&
3337 !N->getOperand(2).hasOneUse()) {
3339 // Scan all of the users of the LHS, looking for VCMPo's that match.
3340 SDNode *VCMPoNode = 0;
3342 SDNode *LHSN = N->getOperand(0).Val;
3343 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3345 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3346 (*UI)->getOperand(1) == N->getOperand(1) &&
3347 (*UI)->getOperand(2) == N->getOperand(2) &&
3348 (*UI)->getOperand(0) == N->getOperand(0)) {
3353 // If there is no VCMPo node, or if the flag value has a single use, don't
3355 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3358 // Look at the (necessarily single) use of the flag value. If it has a
3359 // chain, this transformation is more complex. Note that multiple things
3360 // could use the value result, which we should ignore.
3361 SDNode *FlagUser = 0;
3362 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3363 FlagUser == 0; ++UI) {
3364 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3366 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3367 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3374 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3375 // give up for right now.
3376 if (FlagUser->getOpcode() == PPCISD::MFCR)
3377 return SDOperand(VCMPoNode, 0);
3382 // If this is a branch on an altivec predicate comparison, lower this so
3383 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3384 // lowering is done pre-legalize, because the legalizer lowers the predicate
3385 // compare down to code that is difficult to reassemble.
3386 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3387 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3391 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3392 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3393 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3394 assert(isDot && "Can't compare against a vector result!");
3396 // If this is a comparison against something other than 0/1, then we know
3397 // that the condition is never/always true.
3398 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3399 if (Val != 0 && Val != 1) {
3400 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3401 return N->getOperand(0);
3402 // Always !=, turn it into an unconditional branch.
3403 return DAG.getNode(ISD::BR, MVT::Other,
3404 N->getOperand(0), N->getOperand(4));
3407 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3409 // Create the PPCISD altivec 'dot' comparison node.
3410 std::vector<MVT::ValueType> VTs;
3412 LHS.getOperand(2), // LHS of compare
3413 LHS.getOperand(3), // RHS of compare
3414 DAG.getConstant(CompareOpc, MVT::i32)
3416 VTs.push_back(LHS.getOperand(2).getValueType());
3417 VTs.push_back(MVT::Flag);
3418 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3420 // Unpack the result based on how the target uses it.
3421 PPC::Predicate CompOpc;
3422 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3423 default: // Can't happen, don't crash on invalid number though.
3424 case 0: // Branch on the value of the EQ bit of CR6.
3425 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3427 case 1: // Branch on the inverted value of the EQ bit of CR6.
3428 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3430 case 2: // Branch on the value of the LT bit of CR6.
3431 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3433 case 3: // Branch on the inverted value of the LT bit of CR6.
3434 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3438 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3439 DAG.getConstant(CompOpc, MVT::i32),
3440 DAG.getRegister(PPC::CR6, MVT::i32),
3441 N->getOperand(4), CompNode.getValue(1));
3450 //===----------------------------------------------------------------------===//
3451 // Inline Assembly Support
3452 //===----------------------------------------------------------------------===//
3454 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3456 uint64_t &KnownZero,
3458 const SelectionDAG &DAG,
3459 unsigned Depth) const {
3462 switch (Op.getOpcode()) {
3464 case PPCISD::LBRX: {
3465 // lhbrx is known to have the top bits cleared out.
3466 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3467 KnownZero = 0xFFFF0000;
3470 case ISD::INTRINSIC_WO_CHAIN: {
3471 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3473 case Intrinsic::ppc_altivec_vcmpbfp_p:
3474 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3475 case Intrinsic::ppc_altivec_vcmpequb_p:
3476 case Intrinsic::ppc_altivec_vcmpequh_p:
3477 case Intrinsic::ppc_altivec_vcmpequw_p:
3478 case Intrinsic::ppc_altivec_vcmpgefp_p:
3479 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3480 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3481 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3482 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3483 case Intrinsic::ppc_altivec_vcmpgtub_p:
3484 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3485 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3486 KnownZero = ~1U; // All bits but the low one are known to be zero.
3494 /// getConstraintType - Given a constraint, return the type of
3495 /// constraint it is for this target.
3496 PPCTargetLowering::ConstraintType
3497 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3498 if (Constraint.size() == 1) {
3499 switch (Constraint[0]) {
3506 return C_RegisterClass;
3509 return TargetLowering::getConstraintType(Constraint);
3512 std::pair<unsigned, const TargetRegisterClass*>
3513 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3514 MVT::ValueType VT) const {
3515 if (Constraint.size() == 1) {
3516 // GCC RS6000 Constraint Letters
3517 switch (Constraint[0]) {
3520 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3521 return std::make_pair(0U, PPC::G8RCRegisterClass);
3522 return std::make_pair(0U, PPC::GPRCRegisterClass);
3525 return std::make_pair(0U, PPC::F4RCRegisterClass);
3526 else if (VT == MVT::f64)
3527 return std::make_pair(0U, PPC::F8RCRegisterClass);
3530 return std::make_pair(0U, PPC::VRRCRegisterClass);
3532 return std::make_pair(0U, PPC::CRRCRegisterClass);
3536 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3540 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3541 /// vector. If it is invalid, don't add anything to Ops.
3542 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3543 std::vector<SDOperand>&Ops,
3544 SelectionDAG &DAG) {
3545 SDOperand Result(0,0);
3556 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3557 if (!CST) return; // Must be an immediate to match.
3558 unsigned Value = CST->getValue();
3560 default: assert(0 && "Unknown constraint letter!");
3561 case 'I': // "I" is a signed 16-bit constant.
3562 if ((short)Value == (int)Value)
3563 Result = DAG.getTargetConstant(Value, Op.getValueType());
3565 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3566 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3567 if ((short)Value == 0)
3568 Result = DAG.getTargetConstant(Value, Op.getValueType());
3570 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3571 if ((Value >> 16) == 0)
3572 Result = DAG.getTargetConstant(Value, Op.getValueType());
3574 case 'M': // "M" is a constant that is greater than 31.
3576 Result = DAG.getTargetConstant(Value, Op.getValueType());
3578 case 'N': // "N" is a positive constant that is an exact power of two.
3579 if ((int)Value > 0 && isPowerOf2_32(Value))
3580 Result = DAG.getTargetConstant(Value, Op.getValueType());
3582 case 'O': // "O" is the constant zero.
3584 Result = DAG.getTargetConstant(Value, Op.getValueType());
3586 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3587 if ((short)-Value == (int)-Value)
3588 Result = DAG.getTargetConstant(Value, Op.getValueType());
3596 Ops.push_back(Result);
3600 // Handle standard constraint letters.
3601 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
3604 // isLegalAddressingMode - Return true if the addressing mode represented
3605 // by AM is legal for this target, for a load/store of the specified type.
3606 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3607 const Type *Ty) const {
3608 // FIXME: PPC does not allow r+i addressing modes for vectors!
3610 // PPC allows a sign-extended 16-bit immediate field.
3611 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3614 // No global is ever allowed as a base.
3618 // PPC only support r+r,
3620 case 0: // "r+i" or just "i", depending on HasBaseReg.
3623 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3625 // Otherwise we have r+r or r+i.
3628 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3630 // Allow 2*r as r+r.
3633 // No other scales are supported.
3640 /// isLegalAddressImmediate - Return true if the integer value can be used
3641 /// as the offset of the target addressing mode for load / store of the
3643 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3644 // PPC allows a sign-extended 16-bit immediate field.
3645 return (V > -(1 << 16) && V < (1 << 16)-1);
3648 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3652 SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
3653 // Depths > 0 not supported yet!
3654 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3657 MachineFunction &MF = DAG.getMachineFunction();
3658 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3659 int RAIdx = FuncInfo->getReturnAddrSaveIndex();
3661 bool isPPC64 = PPCSubTarget.isPPC64();
3663 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI());
3665 // Set up a frame object for the return address.
3666 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset);
3668 // Remember it for next time.
3669 FuncInfo->setReturnAddrSaveIndex(RAIdx);
3671 // Make sure the function really does not optimize away the store of the RA
3673 FuncInfo->setLRStoreRequired();
3676 // Just load the return address off the stack.
3677 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy());
3678 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
3681 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
3682 // Depths > 0 not supported yet!
3683 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3686 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3687 bool isPPC64 = PtrVT == MVT::i64;
3689 MachineFunction &MF = DAG.getMachineFunction();
3690 MachineFrameInfo *MFI = MF.getFrameInfo();
3691 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3692 && MFI->getStackSize();
3695 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3698 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,