1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 setStackPointerRegisterToSaveRestore(PPC::X1);
631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
634 setStackPointerRegisterToSaveRestore(PPC::R1);
635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
641 setTargetDAGCombine(ISD::LOAD);
642 setTargetDAGCombine(ISD::STORE);
643 setTargetDAGCombine(ISD::BR_CC);
644 if (Subtarget.useCRBits())
645 setTargetDAGCombine(ISD::BRCOND);
646 setTargetDAGCombine(ISD::BSWAP);
647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
653 if (Subtarget.useCRBits()) {
654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
665 // Darwin long double math library functions have $LDBL128 appended.
666 if (Subtarget.isDarwin()) {
667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
681 if (Subtarget.useCRBits())
682 setHasMultipleConditionRegisters();
684 setMinFunctionAlignment(2);
685 if (Subtarget.isDarwin())
686 setPrefFunctionAlignment(4);
688 if (isPPC64 && Subtarget.isJITCodeModel())
689 // Temporary workaround for the inability of PPC64 JIT to handle jump
691 setSupportJumpTables(false);
693 setInsertFencesForAtomic(true);
695 if (Subtarget.enableMachineScheduler())
696 setSchedulingPreference(Sched::Source);
698 setSchedulingPreference(Sched::Hybrid);
700 computeRegisterProperties();
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
704 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
713 setPrefFunctionAlignment(4);
717 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718 /// the desired ByVal argument alignment.
719 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
739 if (MaxAlign == MaxMaxAlign)
745 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746 /// function arguments in the caller parameter area.
747 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
748 // Darwin passes everything on 4 byte boundary.
749 if (Subtarget.isDarwin())
752 // 16byte and wider vectors are passed on 16byte boundary.
753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
754 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
756 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 default: return nullptr;
763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
776 case PPCISD::LOAD: return "PPCISD::LOAD";
777 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
778 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
779 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
780 case PPCISD::SRL: return "PPCISD::SRL";
781 case PPCISD::SRA: return "PPCISD::SRA";
782 case PPCISD::SHL: return "PPCISD::SHL";
783 case PPCISD::CALL: return "PPCISD::CALL";
784 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
785 case PPCISD::MTCTR: return "PPCISD::MTCTR";
786 case PPCISD::BCTRL: return "PPCISD::BCTRL";
787 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
788 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
789 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
790 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
791 case PPCISD::VCMP: return "PPCISD::VCMP";
792 case PPCISD::VCMPo: return "PPCISD::VCMPo";
793 case PPCISD::LBRX: return "PPCISD::LBRX";
794 case PPCISD::STBRX: return "PPCISD::STBRX";
795 case PPCISD::LARX: return "PPCISD::LARX";
796 case PPCISD::STCX: return "PPCISD::STCX";
797 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
798 case PPCISD::BDNZ: return "PPCISD::BDNZ";
799 case PPCISD::BDZ: return "PPCISD::BDZ";
800 case PPCISD::MFFS: return "PPCISD::MFFS";
801 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
802 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
803 case PPCISD::CR6SET: return "PPCISD::CR6SET";
804 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
805 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
806 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
807 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
808 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
809 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
810 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
811 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
812 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
813 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
814 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
815 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
816 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
817 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
818 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
819 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
820 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
821 case PPCISD::SC: return "PPCISD::SC";
825 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
827 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
828 return VT.changeVectorElementTypeToInteger();
831 //===----------------------------------------------------------------------===//
832 // Node matching predicates, for use by the tblgen matching code.
833 //===----------------------------------------------------------------------===//
835 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
836 static bool isFloatingPointZero(SDValue Op) {
837 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
838 return CFP->getValueAPF().isZero();
839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
840 // Maybe this has already been legalized into the constant pool?
841 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
842 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
843 return CFP->getValueAPF().isZero();
848 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
849 /// true if Op is undef or if it matches the specified value.
850 static bool isConstantOrUndef(int Op, int Val) {
851 return Op < 0 || Op == Val;
854 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
855 /// VPKUHUM instruction.
856 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
858 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
860 for (unsigned i = 0; i != 16; ++i)
861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
864 for (unsigned i = 0; i != 8; ++i)
865 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
866 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
872 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUWUM instruction.
874 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
877 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
885 for (unsigned i = 0; i != 16; i += 2)
886 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
887 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
890 for (unsigned i = 0; i != 8; i += 2)
891 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
892 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
893 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
900 /// isVMerge - Common function, used to match vmrg* shuffles.
902 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
903 unsigned LHSStart, unsigned RHSStart) {
904 if (N->getValueType(0) != MVT::v16i8)
906 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
907 "Unsupported merge size!");
909 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
910 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
911 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
912 LHSStart+j+i*UnitSize) ||
913 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
914 RHSStart+j+i*UnitSize))
920 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
921 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
922 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
923 bool isUnary, SelectionDAG &DAG) {
924 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
926 return isVMerge(N, UnitSize, 0, 16);
927 return isVMerge(N, UnitSize, 0, 0);
930 return isVMerge(N, UnitSize, 8, 24);
931 return isVMerge(N, UnitSize, 8, 8);
935 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
936 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
937 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
938 bool isUnary, SelectionDAG &DAG) {
939 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
941 return isVMerge(N, UnitSize, 8, 24);
942 return isVMerge(N, UnitSize, 8, 8);
945 return isVMerge(N, UnitSize, 0, 16);
946 return isVMerge(N, UnitSize, 0, 0);
951 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
952 /// amount, otherwise return -1.
953 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
954 if (N->getValueType(0) != MVT::v16i8)
957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
959 // Find the first non-undef value in the shuffle mask.
961 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
964 if (i == 16) return -1; // all undef.
966 // Otherwise, check to see if the rest of the elements are consecutively
967 // numbered from this value.
968 unsigned ShiftAmt = SVOp->getMaskElt(i);
969 if (ShiftAmt < i) return -1;
971 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
976 // Check the rest of the elements to see if they are consecutive.
977 for (++i; i != 16; ++i)
978 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
981 // Check the rest of the elements to see if they are consecutive.
982 for (++i; i != 16; ++i)
983 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
987 } else { // Big Endian
992 // Check the rest of the elements to see if they are consecutive.
993 for (++i; i != 16; ++i)
994 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
997 // Check the rest of the elements to see if they are consecutive.
998 for (++i; i != 16; ++i)
999 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1006 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1007 /// specifies a splat of a single element that is suitable for input to
1008 /// VSPLTB/VSPLTH/VSPLTW.
1009 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1010 assert(N->getValueType(0) == MVT::v16i8 &&
1011 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1013 // This is a splat operation if each element of the permute is the same, and
1014 // if the value doesn't reference the second vector.
1015 unsigned ElementBase = N->getMaskElt(0);
1017 // FIXME: Handle UNDEF elements too!
1018 if (ElementBase >= 16)
1021 // Check that the indices are consecutive, in the case of a multi-byte element
1022 // splatted with a v16i8 mask.
1023 for (unsigned i = 1; i != EltSize; ++i)
1024 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1027 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1028 if (N->getMaskElt(i) < 0) continue;
1029 for (unsigned j = 0; j != EltSize; ++j)
1030 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1036 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1038 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1039 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1041 APInt APVal, APUndef;
1045 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1047 return CFP->getValueAPF().isNegZero();
1052 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1053 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1054 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1055 SelectionDAG &DAG) {
1056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1057 assert(isSplatShuffleMask(SVOp, EltSize));
1058 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1059 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1061 return SVOp->getMaskElt(0) / EltSize;
1064 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1065 /// by using a vspltis[bhw] instruction of the specified element size, return
1066 /// the constant being splatted. The ByteSize field indicates the number of
1067 /// bytes of each element [124] -> [bhw].
1068 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1069 SDValue OpVal(nullptr, 0);
1071 // If ByteSize of the splat is bigger than the element size of the
1072 // build_vector, then we have a case where we are checking for a splat where
1073 // multiple elements of the buildvector are folded together into a single
1074 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1075 unsigned EltSize = 16/N->getNumOperands();
1076 if (EltSize < ByteSize) {
1077 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1078 SDValue UniquedVals[4];
1079 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1081 // See if all of the elements in the buildvector agree across.
1082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1083 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1084 // If the element isn't a constant, bail fully out.
1085 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1088 if (!UniquedVals[i&(Multiple-1)].getNode())
1089 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1090 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1091 return SDValue(); // no match.
1094 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1095 // either constant or undef values that are identical for each chunk. See
1096 // if these chunks can form into a larger vspltis*.
1098 // Check to see if all of the leading entries are either 0 or -1. If
1099 // neither, then this won't fit into the immediate field.
1100 bool LeadingZero = true;
1101 bool LeadingOnes = true;
1102 for (unsigned i = 0; i != Multiple-1; ++i) {
1103 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1105 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1106 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1108 // Finally, check the least significant entry.
1110 if (!UniquedVals[Multiple-1].getNode())
1111 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1112 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1114 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1117 if (!UniquedVals[Multiple-1].getNode())
1118 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1119 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1120 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1121 return DAG.getTargetConstant(Val, MVT::i32);
1127 // Check to see if this buildvec has a single non-undef value in its elements.
1128 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1129 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1130 if (!OpVal.getNode())
1131 OpVal = N->getOperand(i);
1132 else if (OpVal != N->getOperand(i))
1136 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1138 unsigned ValSizeInBytes = EltSize;
1140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1141 Value = CN->getZExtValue();
1142 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1143 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1144 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1147 // If the splat value is larger than the element value, then we can never do
1148 // this splat. The only case that we could fit the replicated bits into our
1149 // immediate field for would be zero, and we prefer to use vxor for it.
1150 if (ValSizeInBytes < ByteSize) return SDValue();
1152 // If the element value is larger than the splat value, cut it in half and
1153 // check to see if the two halves are equal. Continue doing this until we
1154 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1155 while (ValSizeInBytes > ByteSize) {
1156 ValSizeInBytes >>= 1;
1158 // If the top half equals the bottom half, we're still ok.
1159 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1160 (Value & ((1 << (8*ValSizeInBytes))-1)))
1164 // Properly sign extend the value.
1165 int MaskVal = SignExtend32(Value, ByteSize * 8);
1167 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1168 if (MaskVal == 0) return SDValue();
1170 // Finally, if this value fits in a 5 bit sext field, return it
1171 if (SignExtend32<5>(MaskVal) == MaskVal)
1172 return DAG.getTargetConstant(MaskVal, MVT::i32);
1176 //===----------------------------------------------------------------------===//
1177 // Addressing Mode Selection
1178 //===----------------------------------------------------------------------===//
1180 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1181 /// or 64-bit immediate, and if the value can be accurately represented as a
1182 /// sign extension from a 16-bit value. If so, this returns true and the
1184 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1185 if (!isa<ConstantSDNode>(N))
1188 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1189 if (N->getValueType(0) == MVT::i32)
1190 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1192 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1194 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1195 return isIntS16Immediate(Op.getNode(), Imm);
1199 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1200 /// can be represented as an indexed [r+r] operation. Returns false if it
1201 /// can be more efficiently represented with [r+imm].
1202 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1204 SelectionDAG &DAG) const {
1206 if (N.getOpcode() == ISD::ADD) {
1207 if (isIntS16Immediate(N.getOperand(1), imm))
1208 return false; // r+i
1209 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1210 return false; // r+i
1212 Base = N.getOperand(0);
1213 Index = N.getOperand(1);
1215 } else if (N.getOpcode() == ISD::OR) {
1216 if (isIntS16Immediate(N.getOperand(1), imm))
1217 return false; // r+i can fold it if we can.
1219 // If this is an or of disjoint bitfields, we can codegen this as an add
1220 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1222 APInt LHSKnownZero, LHSKnownOne;
1223 APInt RHSKnownZero, RHSKnownOne;
1224 DAG.computeKnownBits(N.getOperand(0),
1225 LHSKnownZero, LHSKnownOne);
1227 if (LHSKnownZero.getBoolValue()) {
1228 DAG.computeKnownBits(N.getOperand(1),
1229 RHSKnownZero, RHSKnownOne);
1230 // If all of the bits are known zero on the LHS or RHS, the add won't
1232 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1233 Base = N.getOperand(0);
1234 Index = N.getOperand(1);
1243 // If we happen to be doing an i64 load or store into a stack slot that has
1244 // less than a 4-byte alignment, then the frame-index elimination may need to
1245 // use an indexed load or store instruction (because the offset may not be a
1246 // multiple of 4). The extra register needed to hold the offset comes from the
1247 // register scavenger, and it is possible that the scavenger will need to use
1248 // an emergency spill slot. As a result, we need to make sure that a spill slot
1249 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1251 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1252 // FIXME: This does not handle the LWA case.
1256 // NOTE: We'll exclude negative FIs here, which come from argument
1257 // lowering, because there are no known test cases triggering this problem
1258 // using packed structures (or similar). We can remove this exclusion if
1259 // we find such a test case. The reason why this is so test-case driven is
1260 // because this entire 'fixup' is only to prevent crashes (from the
1261 // register scavenger) on not-really-valid inputs. For example, if we have:
1263 // %b = bitcast i1* %a to i64*
1264 // store i64* a, i64 b
1265 // then the store should really be marked as 'align 1', but is not. If it
1266 // were marked as 'align 1' then the indexed form would have been
1267 // instruction-selected initially, and the problem this 'fixup' is preventing
1268 // won't happen regardless.
1272 MachineFunction &MF = DAG.getMachineFunction();
1273 MachineFrameInfo *MFI = MF.getFrameInfo();
1275 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1279 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1280 FuncInfo->setHasNonRISpills();
1283 /// Returns true if the address N can be represented by a base register plus
1284 /// a signed 16-bit displacement [r+imm], and if it is not better
1285 /// represented as reg+reg. If Aligned is true, only accept displacements
1286 /// suitable for STD and friends, i.e. multiples of 4.
1287 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1290 bool Aligned) const {
1291 // FIXME dl should come from parent load or store, not from address
1293 // If this can be more profitably realized as r+r, fail.
1294 if (SelectAddressRegReg(N, Disp, Base, DAG))
1297 if (N.getOpcode() == ISD::ADD) {
1299 if (isIntS16Immediate(N.getOperand(1), imm) &&
1300 (!Aligned || (imm & 3) == 0)) {
1301 Disp = DAG.getTargetConstant(imm, N.getValueType());
1302 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1303 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1304 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1306 Base = N.getOperand(0);
1308 return true; // [r+i]
1309 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1310 // Match LOAD (ADD (X, Lo(G))).
1311 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1312 && "Cannot handle constant offsets yet!");
1313 Disp = N.getOperand(1).getOperand(0); // The global address.
1314 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1315 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1316 Disp.getOpcode() == ISD::TargetConstantPool ||
1317 Disp.getOpcode() == ISD::TargetJumpTable);
1318 Base = N.getOperand(0);
1319 return true; // [&g+r]
1321 } else if (N.getOpcode() == ISD::OR) {
1323 if (isIntS16Immediate(N.getOperand(1), imm) &&
1324 (!Aligned || (imm & 3) == 0)) {
1325 // If this is an or of disjoint bitfields, we can codegen this as an add
1326 // (for better address arithmetic) if the LHS and RHS of the OR are
1327 // provably disjoint.
1328 APInt LHSKnownZero, LHSKnownOne;
1329 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1331 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1332 // If all of the bits are known zero on the LHS or RHS, the add won't
1334 if (FrameIndexSDNode *FI =
1335 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1336 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1337 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1339 Base = N.getOperand(0);
1341 Disp = DAG.getTargetConstant(imm, N.getValueType());
1345 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1346 // Loading from a constant address.
1348 // If this address fits entirely in a 16-bit sext immediate field, codegen
1351 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1352 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1353 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1354 CN->getValueType(0));
1358 // Handle 32-bit sext immediates with LIS + addr mode.
1359 if ((CN->getValueType(0) == MVT::i32 ||
1360 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1361 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1362 int Addr = (int)CN->getZExtValue();
1364 // Otherwise, break this down into an LIS + disp.
1365 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1367 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1368 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1369 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1374 Disp = DAG.getTargetConstant(0, getPointerTy());
1375 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1376 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1377 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1380 return true; // [r+0]
1383 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1384 /// represented as an indexed [r+r] operation.
1385 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1387 SelectionDAG &DAG) const {
1388 // Check to see if we can easily represent this as an [r+r] address. This
1389 // will fail if it thinks that the address is more profitably represented as
1390 // reg+imm, e.g. where imm = 0.
1391 if (SelectAddressRegReg(N, Base, Index, DAG))
1394 // If the operand is an addition, always emit this as [r+r], since this is
1395 // better (for code size, and execution, as the memop does the add for free)
1396 // than emitting an explicit add.
1397 if (N.getOpcode() == ISD::ADD) {
1398 Base = N.getOperand(0);
1399 Index = N.getOperand(1);
1403 // Otherwise, do it the hard way, using R0 as the base register.
1404 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1410 /// getPreIndexedAddressParts - returns true by value, base pointer and
1411 /// offset pointer and addressing mode by reference if the node's address
1412 /// can be legally represented as pre-indexed load / store address.
1413 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1415 ISD::MemIndexedMode &AM,
1416 SelectionDAG &DAG) const {
1417 if (DisablePPCPreinc) return false;
1423 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1424 Ptr = LD->getBasePtr();
1425 VT = LD->getMemoryVT();
1426 Alignment = LD->getAlignment();
1427 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1428 Ptr = ST->getBasePtr();
1429 VT = ST->getMemoryVT();
1430 Alignment = ST->getAlignment();
1435 // PowerPC doesn't have preinc load/store instructions for vectors.
1439 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1441 // Common code will reject creating a pre-inc form if the base pointer
1442 // is a frame index, or if N is a store and the base pointer is either
1443 // the same as or a predecessor of the value being stored. Check for
1444 // those situations here, and try with swapped Base/Offset instead.
1447 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1450 SDValue Val = cast<StoreSDNode>(N)->getValue();
1451 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1456 std::swap(Base, Offset);
1462 // LDU/STU can only handle immediates that are a multiple of 4.
1463 if (VT != MVT::i64) {
1464 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1467 // LDU/STU need an address with at least 4-byte alignment.
1471 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1475 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1476 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1477 // sext i32 to i64 when addr mode is r+i.
1478 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1479 LD->getExtensionType() == ISD::SEXTLOAD &&
1480 isa<ConstantSDNode>(Offset))
1488 //===----------------------------------------------------------------------===//
1489 // LowerOperation implementation
1490 //===----------------------------------------------------------------------===//
1492 /// GetLabelAccessInfo - Return true if we should reference labels using a
1493 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1494 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1495 unsigned &LoOpFlags,
1496 const GlobalValue *GV = nullptr) {
1497 HiOpFlags = PPCII::MO_HA;
1498 LoOpFlags = PPCII::MO_LO;
1500 // Don't use the pic base if not in PIC relocation model.
1501 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1504 HiOpFlags |= PPCII::MO_PIC_FLAG;
1505 LoOpFlags |= PPCII::MO_PIC_FLAG;
1508 // If this is a reference to a global value that requires a non-lazy-ptr, make
1509 // sure that instruction lowering adds it.
1510 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1511 HiOpFlags |= PPCII::MO_NLP_FLAG;
1512 LoOpFlags |= PPCII::MO_NLP_FLAG;
1514 if (GV->hasHiddenVisibility()) {
1515 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1516 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1523 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1524 SelectionDAG &DAG) {
1525 EVT PtrVT = HiPart.getValueType();
1526 SDValue Zero = DAG.getConstant(0, PtrVT);
1529 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1530 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1532 // With PIC, the first instruction is actually "GR+hi(&G)".
1534 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1535 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1537 // Generate non-pic code that has direct accesses to the constant pool.
1538 // The address of the global is just (hi(&g)+lo(&g)).
1539 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1542 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1543 SelectionDAG &DAG) const {
1544 EVT PtrVT = Op.getValueType();
1545 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1546 const Constant *C = CP->getConstVal();
1548 // 64-bit SVR4 ABI code is always position-independent.
1549 // The actual address of the GlobalValue is stored in the TOC.
1550 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1551 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1552 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1553 DAG.getRegister(PPC::X2, MVT::i64));
1556 unsigned MOHiFlag, MOLoFlag;
1557 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1559 if (isPIC && Subtarget.isSVR4ABI()) {
1560 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1561 PPCII::MO_PIC_FLAG);
1563 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1564 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1568 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1570 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1571 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1574 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1575 EVT PtrVT = Op.getValueType();
1576 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1578 // 64-bit SVR4 ABI code is always position-independent.
1579 // The actual address of the GlobalValue is stored in the TOC.
1580 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1581 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1582 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1583 DAG.getRegister(PPC::X2, MVT::i64));
1586 unsigned MOHiFlag, MOLoFlag;
1587 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1589 if (isPIC && Subtarget.isSVR4ABI()) {
1590 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1591 PPCII::MO_PIC_FLAG);
1593 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1594 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1597 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1598 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1599 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1602 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1603 SelectionDAG &DAG) const {
1604 EVT PtrVT = Op.getValueType();
1606 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1608 unsigned MOHiFlag, MOLoFlag;
1609 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1610 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1611 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1612 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1615 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1616 SelectionDAG &DAG) const {
1618 // FIXME: TLS addresses currently use medium model code sequences,
1619 // which is the most useful form. Eventually support for small and
1620 // large models could be added if users need it, at the cost of
1621 // additional complexity.
1622 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1624 const GlobalValue *GV = GA->getGlobal();
1625 EVT PtrVT = getPointerTy();
1626 bool is64bit = Subtarget.isPPC64();
1628 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1630 if (Model == TLSModel::LocalExec) {
1631 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1632 PPCII::MO_TPREL_HA);
1633 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1634 PPCII::MO_TPREL_LO);
1635 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1636 is64bit ? MVT::i64 : MVT::i32);
1637 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1638 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1641 if (Model == TLSModel::InitialExec) {
1642 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1643 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1647 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1648 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1649 PtrVT, GOTReg, TGA);
1651 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1652 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1653 PtrVT, TGA, GOTPtr);
1654 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1657 if (Model == TLSModel::GeneralDynamic) {
1658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1659 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1660 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1662 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1665 // We need a chain node, and don't have one handy. The underlying
1666 // call has no side effects, so using the function entry node
1668 SDValue Chain = DAG.getEntryNode();
1669 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1670 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1671 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1672 PtrVT, ParmReg, TGA);
1673 // The return value from GET_TLS_ADDR really is in X3 already, but
1674 // some hacks are needed here to tie everything together. The extra
1675 // copies dissolve during subsequent transforms.
1676 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1677 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1680 if (Model == TLSModel::LocalDynamic) {
1681 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1682 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1683 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1685 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1688 // We need a chain node, and don't have one handy. The underlying
1689 // call has no side effects, so using the function entry node
1691 SDValue Chain = DAG.getEntryNode();
1692 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1693 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1694 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1695 PtrVT, ParmReg, TGA);
1696 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1697 // some hacks are needed here to tie everything together. The extra
1698 // copies dissolve during subsequent transforms.
1699 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1700 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1701 Chain, ParmReg, TGA);
1702 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1705 llvm_unreachable("Unknown TLS model!");
1708 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1709 SelectionDAG &DAG) const {
1710 EVT PtrVT = Op.getValueType();
1711 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1713 const GlobalValue *GV = GSDN->getGlobal();
1715 // 64-bit SVR4 ABI code is always position-independent.
1716 // The actual address of the GlobalValue is stored in the TOC.
1717 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1718 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1719 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1720 DAG.getRegister(PPC::X2, MVT::i64));
1723 unsigned MOHiFlag, MOLoFlag;
1724 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1726 if (isPIC && Subtarget.isSVR4ABI()) {
1727 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1729 PPCII::MO_PIC_FLAG);
1730 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1731 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1735 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1737 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1739 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1741 // If the global reference is actually to a non-lazy-pointer, we have to do an
1742 // extra load to get the address of the global.
1743 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1744 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1745 false, false, false, 0);
1749 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1750 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1753 if (Op.getValueType() == MVT::v2i64) {
1754 // When the operands themselves are v2i64 values, we need to do something
1755 // special because VSX has no underlying comparison operations for these.
1756 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1757 // Equality can be handled by casting to the legal type for Altivec
1758 // comparisons, everything else needs to be expanded.
1759 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1760 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1761 DAG.getSetCC(dl, MVT::v4i32,
1762 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1763 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1770 // We handle most of these in the usual way.
1774 // If we're comparing for equality to zero, expose the fact that this is
1775 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1776 // fold the new nodes.
1777 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1778 if (C->isNullValue() && CC == ISD::SETEQ) {
1779 EVT VT = Op.getOperand(0).getValueType();
1780 SDValue Zext = Op.getOperand(0);
1781 if (VT.bitsLT(MVT::i32)) {
1783 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1785 unsigned Log2b = Log2_32(VT.getSizeInBits());
1786 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1787 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1788 DAG.getConstant(Log2b, MVT::i32));
1789 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1791 // Leave comparisons against 0 and -1 alone for now, since they're usually
1792 // optimized. FIXME: revisit this when we can custom lower all setcc
1794 if (C->isAllOnesValue() || C->isNullValue())
1798 // If we have an integer seteq/setne, turn it into a compare against zero
1799 // by xor'ing the rhs with the lhs, which is faster than setting a
1800 // condition register, reading it back out, and masking the correct bit. The
1801 // normal approach here uses sub to do this instead of xor. Using xor exposes
1802 // the result to other bit-twiddling opportunities.
1803 EVT LHSVT = Op.getOperand(0).getValueType();
1804 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1805 EVT VT = Op.getValueType();
1806 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1808 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1813 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1814 const PPCSubtarget &Subtarget) const {
1815 SDNode *Node = Op.getNode();
1816 EVT VT = Node->getValueType(0);
1817 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1818 SDValue InChain = Node->getOperand(0);
1819 SDValue VAListPtr = Node->getOperand(1);
1820 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1823 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1826 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1827 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1829 InChain = GprIndex.getValue(1);
1831 if (VT == MVT::i64) {
1832 // Check if GprIndex is even
1833 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1834 DAG.getConstant(1, MVT::i32));
1835 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1836 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1837 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1838 DAG.getConstant(1, MVT::i32));
1839 // Align GprIndex to be even if it isn't
1840 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1844 // fpr index is 1 byte after gpr
1845 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1846 DAG.getConstant(1, MVT::i32));
1849 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1850 FprPtr, MachinePointerInfo(SV), MVT::i8,
1852 InChain = FprIndex.getValue(1);
1854 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1855 DAG.getConstant(8, MVT::i32));
1857 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1858 DAG.getConstant(4, MVT::i32));
1861 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1862 MachinePointerInfo(), false, false,
1864 InChain = OverflowArea.getValue(1);
1866 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1867 MachinePointerInfo(), false, false,
1869 InChain = RegSaveArea.getValue(1);
1871 // select overflow_area if index > 8
1872 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1873 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1875 // adjustment constant gpr_index * 4/8
1876 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1877 VT.isInteger() ? GprIndex : FprIndex,
1878 DAG.getConstant(VT.isInteger() ? 4 : 8,
1881 // OurReg = RegSaveArea + RegConstant
1882 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1885 // Floating types are 32 bytes into RegSaveArea
1886 if (VT.isFloatingPoint())
1887 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1888 DAG.getConstant(32, MVT::i32));
1890 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1891 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1892 VT.isInteger() ? GprIndex : FprIndex,
1893 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1896 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1897 VT.isInteger() ? VAListPtr : FprPtr,
1898 MachinePointerInfo(SV),
1899 MVT::i8, false, false, 0);
1901 // determine if we should load from reg_save_area or overflow_area
1902 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1904 // increase overflow_area by 4/8 if gpr/fpr > 8
1905 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1906 DAG.getConstant(VT.isInteger() ? 4 : 8,
1909 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1912 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1914 MachinePointerInfo(),
1915 MVT::i32, false, false, 0);
1917 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1918 false, false, false, 0);
1921 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1922 const PPCSubtarget &Subtarget) const {
1923 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1925 // We have to copy the entire va_list struct:
1926 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1927 return DAG.getMemcpy(Op.getOperand(0), Op,
1928 Op.getOperand(1), Op.getOperand(2),
1929 DAG.getConstant(12, MVT::i32), 8, false, true,
1930 MachinePointerInfo(), MachinePointerInfo());
1933 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1934 SelectionDAG &DAG) const {
1935 return Op.getOperand(0);
1938 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1939 SelectionDAG &DAG) const {
1940 SDValue Chain = Op.getOperand(0);
1941 SDValue Trmp = Op.getOperand(1); // trampoline
1942 SDValue FPtr = Op.getOperand(2); // nested function
1943 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1946 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1947 bool isPPC64 = (PtrVT == MVT::i64);
1949 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1952 TargetLowering::ArgListTy Args;
1953 TargetLowering::ArgListEntry Entry;
1955 Entry.Ty = IntPtrTy;
1956 Entry.Node = Trmp; Args.push_back(Entry);
1958 // TrampSize == (isPPC64 ? 48 : 40);
1959 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1960 isPPC64 ? MVT::i64 : MVT::i32);
1961 Args.push_back(Entry);
1963 Entry.Node = FPtr; Args.push_back(Entry);
1964 Entry.Node = Nest; Args.push_back(Entry);
1966 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1967 TargetLowering::CallLoweringInfo CLI(DAG);
1968 CLI.setDebugLoc(dl).setChain(Chain)
1969 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1970 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1971 std::move(Args), 0);
1973 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1974 return CallResult.second;
1977 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1978 const PPCSubtarget &Subtarget) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1984 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1985 // vastart just stores the address of the VarArgsFrameIndex slot into the
1986 // memory location argument.
1987 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1988 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1989 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1990 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1991 MachinePointerInfo(SV),
1995 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1996 // We suppose the given va_list is already allocated.
1999 // char gpr; /* index into the array of 8 GPRs
2000 // * stored in the register save area
2001 // * gpr=0 corresponds to r3,
2002 // * gpr=1 to r4, etc.
2004 // char fpr; /* index into the array of 8 FPRs
2005 // * stored in the register save area
2006 // * fpr=0 corresponds to f1,
2007 // * fpr=1 to f2, etc.
2009 // char *overflow_arg_area;
2010 // /* location on stack that holds
2011 // * the next overflow argument
2013 // char *reg_save_area;
2014 // /* where r3:r10 and f1:f8 (if saved)
2020 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2021 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2024 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2026 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2028 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2031 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2032 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2034 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2035 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2037 uint64_t FPROffset = 1;
2038 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2040 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2042 // Store first byte : number of int regs
2043 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2045 MachinePointerInfo(SV),
2046 MVT::i8, false, false, 0);
2047 uint64_t nextOffset = FPROffset;
2048 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2051 // Store second byte : number of float regs
2052 SDValue secondStore =
2053 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2054 MachinePointerInfo(SV, nextOffset), MVT::i8,
2056 nextOffset += StackOffset;
2057 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2059 // Store second word : arguments given on stack
2060 SDValue thirdStore =
2061 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2062 MachinePointerInfo(SV, nextOffset),
2064 nextOffset += FrameOffset;
2065 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2067 // Store third word : arguments given in registers
2068 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2069 MachinePointerInfo(SV, nextOffset),
2074 #include "PPCGenCallingConv.inc"
2076 // Function whose sole purpose is to kill compiler warnings
2077 // stemming from unused functions included from PPCGenCallingConv.inc.
2078 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2079 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2082 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2083 CCValAssign::LocInfo &LocInfo,
2084 ISD::ArgFlagsTy &ArgFlags,
2089 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2091 CCValAssign::LocInfo &LocInfo,
2092 ISD::ArgFlagsTy &ArgFlags,
2094 static const MCPhysReg ArgRegs[] = {
2095 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2096 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2098 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2100 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2102 // Skip one register if the first unallocated register has an even register
2103 // number and there are still argument registers available which have not been
2104 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2105 // need to skip a register if RegNum is odd.
2106 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2107 State.AllocateReg(ArgRegs[RegNum]);
2110 // Always return false here, as this function only makes sure that the first
2111 // unallocated register has an odd register number and does not actually
2112 // allocate a register for the current argument.
2116 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2118 CCValAssign::LocInfo &LocInfo,
2119 ISD::ArgFlagsTy &ArgFlags,
2121 static const MCPhysReg ArgRegs[] = {
2122 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2126 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2128 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2130 // If there is only one Floating-point register left we need to put both f64
2131 // values of a split ppc_fp128 value on the stack.
2132 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2133 State.AllocateReg(ArgRegs[RegNum]);
2136 // Always return false here, as this function only makes sure that the two f64
2137 // values a ppc_fp128 value is split into are both passed in registers or both
2138 // passed on the stack and does not actually allocate a register for the
2139 // current argument.
2143 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2145 static const MCPhysReg *GetFPR() {
2146 static const MCPhysReg FPR[] = {
2147 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2148 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2154 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2156 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2157 unsigned PtrByteSize) {
2158 unsigned ArgSize = ArgVT.getStoreSize();
2159 if (Flags.isByVal())
2160 ArgSize = Flags.getByValSize();
2162 // Round up to multiples of the pointer size, except for array members,
2163 // which are always packed.
2164 if (!Flags.isInConsecutiveRegs())
2165 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2170 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2172 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2173 ISD::ArgFlagsTy Flags,
2174 unsigned PtrByteSize) {
2175 unsigned Align = PtrByteSize;
2177 // Altivec parameters are padded to a 16 byte boundary.
2178 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2179 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2180 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2183 // ByVal parameters are aligned as requested.
2184 if (Flags.isByVal()) {
2185 unsigned BVAlign = Flags.getByValAlign();
2186 if (BVAlign > PtrByteSize) {
2187 if (BVAlign % PtrByteSize != 0)
2189 "ByVal alignment is not a multiple of the pointer size");
2195 // Array members are always packed to their original alignment.
2196 if (Flags.isInConsecutiveRegs()) {
2197 // If the array member was split into multiple registers, the first
2198 // needs to be aligned to the size of the full type. (Except for
2199 // ppcf128, which is only aligned as its f64 components.)
2200 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2201 Align = OrigVT.getStoreSize();
2203 Align = ArgVT.getStoreSize();
2209 /// CalculateStackSlotUsed - Return whether this argument will use its
2210 /// stack slot (instead of being passed in registers). ArgOffset,
2211 /// AvailableFPRs, and AvailableVRs must hold the current argument
2212 /// position, and will be updated to account for this argument.
2213 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2214 ISD::ArgFlagsTy Flags,
2215 unsigned PtrByteSize,
2216 unsigned LinkageSize,
2217 unsigned ParamAreaSize,
2218 unsigned &ArgOffset,
2219 unsigned &AvailableFPRs,
2220 unsigned &AvailableVRs) {
2221 bool UseMemory = false;
2223 // Respect alignment of argument on the stack.
2225 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2226 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2227 // If there's no space left in the argument save area, we must
2228 // use memory (this check also catches zero-sized arguments).
2229 if (ArgOffset >= LinkageSize + ParamAreaSize)
2232 // Allocate argument on the stack.
2233 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2234 if (Flags.isInConsecutiveRegsLast())
2235 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2236 // If we overran the argument save area, we must use memory
2237 // (this check catches arguments passed partially in memory)
2238 if (ArgOffset > LinkageSize + ParamAreaSize)
2241 // However, if the argument is actually passed in an FPR or a VR,
2242 // we don't use memory after all.
2243 if (!Flags.isByVal()) {
2244 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2245 if (AvailableFPRs > 0) {
2249 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2250 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2251 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2252 if (AvailableVRs > 0) {
2261 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2262 /// ensure minimum alignment required for target.
2263 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2264 unsigned NumBytes) {
2265 unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment();
2266 unsigned AlignMask = TargetAlign - 1;
2267 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2272 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2273 CallingConv::ID CallConv, bool isVarArg,
2274 const SmallVectorImpl<ISD::InputArg>
2276 SDLoc dl, SelectionDAG &DAG,
2277 SmallVectorImpl<SDValue> &InVals)
2279 if (Subtarget.isSVR4ABI()) {
2280 if (Subtarget.isPPC64())
2281 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2284 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2287 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2293 PPCTargetLowering::LowerFormalArguments_32SVR4(
2295 CallingConv::ID CallConv, bool isVarArg,
2296 const SmallVectorImpl<ISD::InputArg>
2298 SDLoc dl, SelectionDAG &DAG,
2299 SmallVectorImpl<SDValue> &InVals) const {
2301 // 32-bit SVR4 ABI Stack Frame Layout:
2302 // +-----------------------------------+
2303 // +--> | Back chain |
2304 // | +-----------------------------------+
2305 // | | Floating-point register save area |
2306 // | +-----------------------------------+
2307 // | | General register save area |
2308 // | +-----------------------------------+
2309 // | | CR save word |
2310 // | +-----------------------------------+
2311 // | | VRSAVE save word |
2312 // | +-----------------------------------+
2313 // | | Alignment padding |
2314 // | +-----------------------------------+
2315 // | | Vector register save area |
2316 // | +-----------------------------------+
2317 // | | Local variable space |
2318 // | +-----------------------------------+
2319 // | | Parameter list area |
2320 // | +-----------------------------------+
2321 // | | LR save word |
2322 // | +-----------------------------------+
2323 // SP--> +--- | Back chain |
2324 // +-----------------------------------+
2327 // System V Application Binary Interface PowerPC Processor Supplement
2328 // AltiVec Technology Programming Interface Manual
2330 MachineFunction &MF = DAG.getMachineFunction();
2331 MachineFrameInfo *MFI = MF.getFrameInfo();
2332 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2334 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2335 // Potential tail calls could cause overwriting of argument stack slots.
2336 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2337 (CallConv == CallingConv::Fast));
2338 unsigned PtrByteSize = 4;
2340 // Assign locations to all of the incoming arguments.
2341 SmallVector<CCValAssign, 16> ArgLocs;
2342 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2343 getTargetMachine(), ArgLocs, *DAG.getContext());
2345 // Reserve space for the linkage area on the stack.
2346 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2347 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2349 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2351 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2352 CCValAssign &VA = ArgLocs[i];
2354 // Arguments stored in registers.
2355 if (VA.isRegLoc()) {
2356 const TargetRegisterClass *RC;
2357 EVT ValVT = VA.getValVT();
2359 switch (ValVT.getSimpleVT().SimpleTy) {
2361 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2364 RC = &PPC::GPRCRegClass;
2367 RC = &PPC::F4RCRegClass;
2370 if (Subtarget.hasVSX())
2371 RC = &PPC::VSFRCRegClass;
2373 RC = &PPC::F8RCRegClass;
2379 RC = &PPC::VRRCRegClass;
2383 RC = &PPC::VSHRCRegClass;
2387 // Transform the arguments stored in physical registers into virtual ones.
2388 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2389 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2390 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2392 if (ValVT == MVT::i1)
2393 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2395 InVals.push_back(ArgValue);
2397 // Argument stored in memory.
2398 assert(VA.isMemLoc());
2400 unsigned ArgSize = VA.getLocVT().getStoreSize();
2401 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2404 // Create load nodes to retrieve arguments from the stack.
2405 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2406 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2407 MachinePointerInfo(),
2408 false, false, false, 0));
2412 // Assign locations to all of the incoming aggregate by value arguments.
2413 // Aggregates passed by value are stored in the local variable space of the
2414 // caller's stack frame, right above the parameter list area.
2415 SmallVector<CCValAssign, 16> ByValArgLocs;
2416 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2417 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2419 // Reserve stack space for the allocations in CCInfo.
2420 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2422 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2424 // Area that is at least reserved in the caller of this function.
2425 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2426 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2428 // Set the size that is at least reserved in caller of this function. Tail
2429 // call optimized function's reserved stack space needs to be aligned so that
2430 // taking the difference between two stack areas will result in an aligned
2432 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2433 FuncInfo->setMinReservedArea(MinReservedArea);
2435 SmallVector<SDValue, 8> MemOps;
2437 // If the function takes variable number of arguments, make a frame index for
2438 // the start of the first vararg value... for expansion of llvm.va_start.
2440 static const MCPhysReg GPArgRegs[] = {
2441 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2442 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2444 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2446 static const MCPhysReg FPArgRegs[] = {
2447 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2450 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2452 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2454 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2457 // Make room for NumGPArgRegs and NumFPArgRegs.
2458 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2459 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2461 FuncInfo->setVarArgsStackOffset(
2462 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2463 CCInfo.getNextStackOffset(), true));
2465 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2466 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2468 // The fixed integer arguments of a variadic function are stored to the
2469 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2470 // the result of va_next.
2471 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2472 // Get an existing live-in vreg, or add a new one.
2473 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2475 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2477 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2478 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2479 MachinePointerInfo(), false, false, 0);
2480 MemOps.push_back(Store);
2481 // Increment the address by four for the next argument to store
2482 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2483 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2486 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2488 // The double arguments are stored to the VarArgsFrameIndex
2490 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2491 // Get an existing live-in vreg, or add a new one.
2492 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2494 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2496 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2497 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2498 MachinePointerInfo(), false, false, 0);
2499 MemOps.push_back(Store);
2500 // Increment the address by eight for the next argument to store
2501 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2503 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2507 if (!MemOps.empty())
2508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2513 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2514 // value to MVT::i64 and then truncate to the correct register size.
2516 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2517 SelectionDAG &DAG, SDValue ArgVal,
2520 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2521 DAG.getValueType(ObjectVT));
2522 else if (Flags.isZExt())
2523 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2524 DAG.getValueType(ObjectVT));
2526 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2530 PPCTargetLowering::LowerFormalArguments_64SVR4(
2532 CallingConv::ID CallConv, bool isVarArg,
2533 const SmallVectorImpl<ISD::InputArg>
2535 SDLoc dl, SelectionDAG &DAG,
2536 SmallVectorImpl<SDValue> &InVals) const {
2537 // TODO: add description of PPC stack frame format, or at least some docs.
2539 bool isELFv2ABI = Subtarget.isELFv2ABI();
2540 bool isLittleEndian = Subtarget.isLittleEndian();
2541 MachineFunction &MF = DAG.getMachineFunction();
2542 MachineFrameInfo *MFI = MF.getFrameInfo();
2543 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2545 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2546 // Potential tail calls could cause overwriting of argument stack slots.
2547 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2548 (CallConv == CallingConv::Fast));
2549 unsigned PtrByteSize = 8;
2551 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2554 static const MCPhysReg GPR[] = {
2555 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2556 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2559 static const MCPhysReg *FPR = GetFPR();
2561 static const MCPhysReg VR[] = {
2562 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2563 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2565 static const MCPhysReg VSRH[] = {
2566 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2567 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2570 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2571 const unsigned Num_FPR_Regs = 13;
2572 const unsigned Num_VR_Regs = array_lengthof(VR);
2574 // Do a first pass over the arguments to determine whether the ABI
2575 // guarantees that our caller has allocated the parameter save area
2576 // on its stack frame. In the ELFv1 ABI, this is always the case;
2577 // in the ELFv2 ABI, it is true if this is a vararg function or if
2578 // any parameter is located in a stack slot.
2580 bool HasParameterArea = !isELFv2ABI || isVarArg;
2581 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2582 unsigned NumBytes = LinkageSize;
2583 unsigned AvailableFPRs = Num_FPR_Regs;
2584 unsigned AvailableVRs = Num_VR_Regs;
2585 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2586 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2587 PtrByteSize, LinkageSize, ParamAreaSize,
2588 NumBytes, AvailableFPRs, AvailableVRs))
2589 HasParameterArea = true;
2591 // Add DAG nodes to load the arguments or copy them out of registers. On
2592 // entry to a function on PPC, the arguments start after the linkage area,
2593 // although the first ones are often in registers.
2595 unsigned ArgOffset = LinkageSize;
2596 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2597 SmallVector<SDValue, 8> MemOps;
2598 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2599 unsigned CurArgIdx = 0;
2600 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2602 bool needsLoad = false;
2603 EVT ObjectVT = Ins[ArgNo].VT;
2604 EVT OrigVT = Ins[ArgNo].ArgVT;
2605 unsigned ObjSize = ObjectVT.getStoreSize();
2606 unsigned ArgSize = ObjSize;
2607 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2608 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2609 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2611 /* Respect alignment of argument on the stack. */
2613 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2614 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2615 unsigned CurArgOffset = ArgOffset;
2617 /* Compute GPR index associated with argument offset. */
2618 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2619 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2621 // FIXME the codegen can be much improved in some cases.
2622 // We do not have to keep everything in memory.
2623 if (Flags.isByVal()) {
2624 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2625 ObjSize = Flags.getByValSize();
2626 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2627 // Empty aggregate parameters do not take up registers. Examples:
2631 // etc. However, we have to provide a place-holder in InVals, so
2632 // pretend we have an 8-byte item at the current address for that
2635 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2636 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2637 InVals.push_back(FIN);
2641 // Create a stack object covering all stack doublewords occupied
2642 // by the argument. If the argument is (fully or partially) on
2643 // the stack, or if the argument is fully in registers but the
2644 // caller has allocated the parameter save anyway, we can refer
2645 // directly to the caller's stack frame. Otherwise, create a
2646 // local copy in our own frame.
2648 if (HasParameterArea ||
2649 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2650 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, true);
2652 FI = MFI->CreateStackObject(ArgSize, Align, false);
2653 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2655 // Handle aggregates smaller than 8 bytes.
2656 if (ObjSize < PtrByteSize) {
2657 // The value of the object is its address, which differs from the
2658 // address of the enclosing doubleword on big-endian systems.
2660 if (!isLittleEndian) {
2661 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2662 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2664 InVals.push_back(Arg);
2666 if (GPR_idx != Num_GPR_Regs) {
2667 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2668 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2671 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2672 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2673 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2674 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2675 MachinePointerInfo(FuncArg),
2676 ObjType, false, false, 0);
2678 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2679 // store the whole register as-is to the parameter save area
2681 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2682 MachinePointerInfo(FuncArg),
2686 MemOps.push_back(Store);
2688 // Whether we copied from a register or not, advance the offset
2689 // into the parameter save area by a full doubleword.
2690 ArgOffset += PtrByteSize;
2694 // The value of the object is its address, which is the address of
2695 // its first stack doubleword.
2696 InVals.push_back(FIN);
2698 // Store whatever pieces of the object are in registers to memory.
2699 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2700 if (GPR_idx == Num_GPR_Regs)
2703 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2704 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2707 SDValue Off = DAG.getConstant(j, PtrVT);
2708 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2710 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2711 MachinePointerInfo(FuncArg, j),
2713 MemOps.push_back(Store);
2716 ArgOffset += ArgSize;
2720 switch (ObjectVT.getSimpleVT().SimpleTy) {
2721 default: llvm_unreachable("Unhandled argument type!");
2725 // These can be scalar arguments or elements of an integer array type
2726 // passed directly. Clang may use those instead of "byval" aggregate
2727 // types to avoid forcing arguments to memory unnecessarily.
2728 if (GPR_idx != Num_GPR_Regs) {
2729 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2730 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2732 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2733 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2734 // value to MVT::i64 and then truncate to the correct register size.
2735 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2738 ArgSize = PtrByteSize;
2745 // These can be scalar arguments or elements of a float array type
2746 // passed directly. The latter are used to implement ELFv2 homogenous
2747 // float aggregates.
2748 if (FPR_idx != Num_FPR_Regs) {
2751 if (ObjectVT == MVT::f32)
2752 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2754 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2755 &PPC::VSFRCRegClass :
2756 &PPC::F8RCRegClass);
2758 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2760 } else if (GPR_idx != Num_GPR_Regs) {
2761 // This can only ever happen in the presence of f32 array types,
2762 // since otherwise we never run out of FPRs before running out
2764 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2765 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2767 if (ObjectVT == MVT::f32) {
2768 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2769 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2770 DAG.getConstant(32, MVT::i32));
2771 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2774 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2779 // When passing an array of floats, the array occupies consecutive
2780 // space in the argument area; only round up to the next doubleword
2781 // at the end of the array. Otherwise, each float takes 8 bytes.
2782 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2783 ArgOffset += ArgSize;
2784 if (Flags.isInConsecutiveRegsLast())
2785 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2793 // These can be scalar arguments or elements of a vector array type
2794 // passed directly. The latter are used to implement ELFv2 homogenous
2795 // vector aggregates.
2796 if (VR_idx != Num_VR_Regs) {
2797 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2798 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2799 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2800 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2809 // We need to load the argument to a virtual register if we determined
2810 // above that we ran out of physical registers of the appropriate type.
2812 if (ObjSize < ArgSize && !isLittleEndian)
2813 CurArgOffset += ArgSize - ObjSize;
2814 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2815 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2816 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2817 false, false, false, 0);
2820 InVals.push_back(ArgVal);
2823 // Area that is at least reserved in the caller of this function.
2824 unsigned MinReservedArea;
2825 if (HasParameterArea)
2826 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2828 MinReservedArea = LinkageSize;
2830 // Set the size that is at least reserved in caller of this function. Tail
2831 // call optimized functions' reserved stack space needs to be aligned so that
2832 // taking the difference between two stack areas will result in an aligned
2834 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2835 FuncInfo->setMinReservedArea(MinReservedArea);
2837 // If the function takes variable number of arguments, make a frame index for
2838 // the start of the first vararg value... for expansion of llvm.va_start.
2840 int Depth = ArgOffset;
2842 FuncInfo->setVarArgsFrameIndex(
2843 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2844 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2846 // If this function is vararg, store any remaining integer argument regs
2847 // to their spots on the stack so that they may be loaded by deferencing the
2848 // result of va_next.
2849 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2850 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2851 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2852 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2853 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2854 MachinePointerInfo(), false, false, 0);
2855 MemOps.push_back(Store);
2856 // Increment the address by four for the next argument to store
2857 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2858 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2862 if (!MemOps.empty())
2863 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2869 PPCTargetLowering::LowerFormalArguments_Darwin(
2871 CallingConv::ID CallConv, bool isVarArg,
2872 const SmallVectorImpl<ISD::InputArg>
2874 SDLoc dl, SelectionDAG &DAG,
2875 SmallVectorImpl<SDValue> &InVals) const {
2876 // TODO: add description of PPC stack frame format, or at least some docs.
2878 MachineFunction &MF = DAG.getMachineFunction();
2879 MachineFrameInfo *MFI = MF.getFrameInfo();
2880 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2882 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2883 bool isPPC64 = PtrVT == MVT::i64;
2884 // Potential tail calls could cause overwriting of argument stack slots.
2885 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2886 (CallConv == CallingConv::Fast));
2887 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2889 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2891 unsigned ArgOffset = LinkageSize;
2892 // Area that is at least reserved in caller of this function.
2893 unsigned MinReservedArea = ArgOffset;
2895 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2896 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2897 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2899 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2900 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2901 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2904 static const MCPhysReg *FPR = GetFPR();
2906 static const MCPhysReg VR[] = {
2907 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2908 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2911 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2912 const unsigned Num_FPR_Regs = 13;
2913 const unsigned Num_VR_Regs = array_lengthof( VR);
2915 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2917 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2919 // In 32-bit non-varargs functions, the stack space for vectors is after the
2920 // stack space for non-vectors. We do not use this space unless we have
2921 // too many vectors to fit in registers, something that only occurs in
2922 // constructed examples:), but we have to walk the arglist to figure
2923 // that out...for the pathological case, compute VecArgOffset as the
2924 // start of the vector parameter area. Computing VecArgOffset is the
2925 // entire point of the following loop.
2926 unsigned VecArgOffset = ArgOffset;
2927 if (!isVarArg && !isPPC64) {
2928 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2930 EVT ObjectVT = Ins[ArgNo].VT;
2931 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2933 if (Flags.isByVal()) {
2934 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2935 unsigned ObjSize = Flags.getByValSize();
2937 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2938 VecArgOffset += ArgSize;
2942 switch(ObjectVT.getSimpleVT().SimpleTy) {
2943 default: llvm_unreachable("Unhandled argument type!");
2949 case MVT::i64: // PPC64
2951 // FIXME: We are guaranteed to be !isPPC64 at this point.
2952 // Does MVT::i64 apply?
2959 // Nothing to do, we're only looking at Nonvector args here.
2964 // We've found where the vector parameter area in memory is. Skip the
2965 // first 12 parameters; these don't use that memory.
2966 VecArgOffset = ((VecArgOffset+15)/16)*16;
2967 VecArgOffset += 12*16;
2969 // Add DAG nodes to load the arguments or copy them out of registers. On
2970 // entry to a function on PPC, the arguments start after the linkage area,
2971 // although the first ones are often in registers.
2973 SmallVector<SDValue, 8> MemOps;
2974 unsigned nAltivecParamsAtEnd = 0;
2975 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2976 unsigned CurArgIdx = 0;
2977 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2979 bool needsLoad = false;
2980 EVT ObjectVT = Ins[ArgNo].VT;
2981 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2982 unsigned ArgSize = ObjSize;
2983 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2984 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2985 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2987 unsigned CurArgOffset = ArgOffset;
2989 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2990 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2991 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2992 if (isVarArg || isPPC64) {
2993 MinReservedArea = ((MinReservedArea+15)/16)*16;
2994 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2997 } else nAltivecParamsAtEnd++;
2999 // Calculate min reserved area.
3000 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3004 // FIXME the codegen can be much improved in some cases.
3005 // We do not have to keep everything in memory.
3006 if (Flags.isByVal()) {
3007 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3008 ObjSize = Flags.getByValSize();
3009 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3010 // Objects of size 1 and 2 are right justified, everything else is
3011 // left justified. This means the memory address is adjusted forwards.
3012 if (ObjSize==1 || ObjSize==2) {
3013 CurArgOffset = CurArgOffset + (4 - ObjSize);
3015 // The value of the object is its address.
3016 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
3017 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3018 InVals.push_back(FIN);
3019 if (ObjSize==1 || ObjSize==2) {
3020 if (GPR_idx != Num_GPR_Regs) {
3023 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3025 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3026 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3027 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3028 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3029 MachinePointerInfo(FuncArg),
3030 ObjType, false, false, 0);
3031 MemOps.push_back(Store);
3035 ArgOffset += PtrByteSize;
3039 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3040 // Store whatever pieces of the object are in registers
3041 // to memory. ArgOffset will be the address of the beginning
3043 if (GPR_idx != Num_GPR_Regs) {
3046 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3048 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3049 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3050 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3051 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3052 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3053 MachinePointerInfo(FuncArg, j),
3055 MemOps.push_back(Store);
3057 ArgOffset += PtrByteSize;
3059 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3066 switch (ObjectVT.getSimpleVT().SimpleTy) {
3067 default: llvm_unreachable("Unhandled argument type!");
3071 if (GPR_idx != Num_GPR_Regs) {
3072 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3073 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3075 if (ObjectVT == MVT::i1)
3076 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3081 ArgSize = PtrByteSize;
3083 // All int arguments reserve stack space in the Darwin ABI.
3084 ArgOffset += PtrByteSize;
3088 case MVT::i64: // PPC64
3089 if (GPR_idx != Num_GPR_Regs) {
3090 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3091 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3093 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3094 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3095 // value to MVT::i64 and then truncate to the correct register size.
3096 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3101 ArgSize = PtrByteSize;
3103 // All int arguments reserve stack space in the Darwin ABI.
3109 // Every 4 bytes of argument space consumes one of the GPRs available for
3110 // argument passing.
3111 if (GPR_idx != Num_GPR_Regs) {
3113 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3116 if (FPR_idx != Num_FPR_Regs) {
3119 if (ObjectVT == MVT::f32)
3120 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3122 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3124 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3130 // All FP arguments reserve stack space in the Darwin ABI.
3131 ArgOffset += isPPC64 ? 8 : ObjSize;
3137 // Note that vector arguments in registers don't reserve stack space,
3138 // except in varargs functions.
3139 if (VR_idx != Num_VR_Regs) {
3140 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3141 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3143 while ((ArgOffset % 16) != 0) {
3144 ArgOffset += PtrByteSize;
3145 if (GPR_idx != Num_GPR_Regs)
3149 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3153 if (!isVarArg && !isPPC64) {
3154 // Vectors go after all the nonvectors.
3155 CurArgOffset = VecArgOffset;
3158 // Vectors are aligned.
3159 ArgOffset = ((ArgOffset+15)/16)*16;
3160 CurArgOffset = ArgOffset;
3168 // We need to load the argument to a virtual register if we determined above
3169 // that we ran out of physical registers of the appropriate type.
3171 int FI = MFI->CreateFixedObject(ObjSize,
3172 CurArgOffset + (ArgSize - ObjSize),
3174 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3175 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3176 false, false, false, 0);
3179 InVals.push_back(ArgVal);
3182 // Allow for Altivec parameters at the end, if needed.
3183 if (nAltivecParamsAtEnd) {
3184 MinReservedArea = ((MinReservedArea+15)/16)*16;
3185 MinReservedArea += 16*nAltivecParamsAtEnd;
3188 // Area that is at least reserved in the caller of this function.
3189 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3191 // Set the size that is at least reserved in caller of this function. Tail
3192 // call optimized functions' reserved stack space needs to be aligned so that
3193 // taking the difference between two stack areas will result in an aligned
3195 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3196 FuncInfo->setMinReservedArea(MinReservedArea);
3198 // If the function takes variable number of arguments, make a frame index for
3199 // the start of the first vararg value... for expansion of llvm.va_start.
3201 int Depth = ArgOffset;
3203 FuncInfo->setVarArgsFrameIndex(
3204 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3206 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3208 // If this function is vararg, store any remaining integer argument regs
3209 // to their spots on the stack so that they may be loaded by deferencing the
3210 // result of va_next.
3211 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3215 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3217 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3219 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3220 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3221 MachinePointerInfo(), false, false, 0);
3222 MemOps.push_back(Store);
3223 // Increment the address by four for the next argument to store
3224 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3225 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3229 if (!MemOps.empty())
3230 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3235 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3236 /// adjusted to accommodate the arguments for the tailcall.
3237 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3238 unsigned ParamSize) {
3240 if (!isTailCall) return 0;
3242 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3243 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3244 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3245 // Remember only if the new adjustement is bigger.
3246 if (SPDiff < FI->getTailCallSPDelta())
3247 FI->setTailCallSPDelta(SPDiff);
3252 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3253 /// for tail call optimization. Targets which want to do tail call
3254 /// optimization should implement this function.
3256 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3257 CallingConv::ID CalleeCC,
3259 const SmallVectorImpl<ISD::InputArg> &Ins,
3260 SelectionDAG& DAG) const {
3261 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3264 // Variable argument functions are not supported.
3268 MachineFunction &MF = DAG.getMachineFunction();
3269 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3270 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3271 // Functions containing by val parameters are not supported.
3272 for (unsigned i = 0; i != Ins.size(); i++) {
3273 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3274 if (Flags.isByVal()) return false;
3277 // Non-PIC/GOT tail calls are supported.
3278 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3281 // At the moment we can only do local tail calls (in same module, hidden
3282 // or protected) if we are generating PIC.
3283 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3284 return G->getGlobal()->hasHiddenVisibility()
3285 || G->getGlobal()->hasProtectedVisibility();
3291 /// isCallCompatibleAddress - Return the immediate to use if the specified
3292 /// 32-bit value is representable in the immediate field of a BxA instruction.
3293 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3294 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3295 if (!C) return nullptr;
3297 int Addr = C->getZExtValue();
3298 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3299 SignExtend32<26>(Addr) != Addr)
3300 return nullptr; // Top 6 bits have to be sext of immediate.
3302 return DAG.getConstant((int)C->getZExtValue() >> 2,
3303 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3308 struct TailCallArgumentInfo {
3313 TailCallArgumentInfo() : FrameIdx(0) {}
3318 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3320 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3322 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3323 SmallVectorImpl<SDValue> &MemOpChains,
3325 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3326 SDValue Arg = TailCallArgs[i].Arg;
3327 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3328 int FI = TailCallArgs[i].FrameIdx;
3329 // Store relative to framepointer.
3330 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3331 MachinePointerInfo::getFixedStack(FI),
3336 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3337 /// the appropriate stack slot for the tail call optimized function call.
3338 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3339 MachineFunction &MF,
3348 // Calculate the new stack slot for the return address.
3349 int SlotSize = isPPC64 ? 8 : 4;
3350 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3352 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3353 NewRetAddrLoc, true);
3354 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3355 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3356 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3357 MachinePointerInfo::getFixedStack(NewRetAddr),
3360 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3361 // slot as the FP is never overwritten.
3364 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3365 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3367 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3368 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3369 MachinePointerInfo::getFixedStack(NewFPIdx),
3376 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3377 /// the position of the argument.
3379 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3380 SDValue Arg, int SPDiff, unsigned ArgOffset,
3381 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3382 int Offset = ArgOffset + SPDiff;
3383 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3384 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3385 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3386 SDValue FIN = DAG.getFrameIndex(FI, VT);
3387 TailCallArgumentInfo Info;
3389 Info.FrameIdxOp = FIN;
3391 TailCallArguments.push_back(Info);
3394 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3395 /// stack slot. Returns the chain as result and the loaded frame pointers in
3396 /// LROpOut/FPOpout. Used when tail calling.
3397 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3405 // Load the LR and FP stack slot for later adjusting.
3406 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3407 LROpOut = getReturnAddrFrameIndex(DAG);
3408 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3409 false, false, false, 0);
3410 Chain = SDValue(LROpOut.getNode(), 1);
3412 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3413 // slot as the FP is never overwritten.
3415 FPOpOut = getFramePointerFrameIndex(DAG);
3416 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3417 false, false, false, 0);
3418 Chain = SDValue(FPOpOut.getNode(), 1);
3424 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3425 /// by "Src" to address "Dst" of size "Size". Alignment information is
3426 /// specified by the specific parameter attribute. The copy will be passed as
3427 /// a byval function parameter.
3428 /// Sometimes what we are copying is the end of a larger object, the part that
3429 /// does not fit in registers.
3431 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3432 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3434 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3435 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3436 false, false, MachinePointerInfo(),
3437 MachinePointerInfo());
3440 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3443 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3444 SDValue Arg, SDValue PtrOff, int SPDiff,
3445 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3446 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3447 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3449 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3454 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3456 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3457 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3458 DAG.getConstant(ArgOffset, PtrVT));
3460 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3461 MachinePointerInfo(), false, false, 0));
3462 // Calculate and remember argument location.
3463 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3468 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3469 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3470 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3471 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3472 MachineFunction &MF = DAG.getMachineFunction();
3474 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3475 // might overwrite each other in case of tail call optimization.
3476 SmallVector<SDValue, 8> MemOpChains2;
3477 // Do not flag preceding copytoreg stuff together with the following stuff.
3479 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3481 if (!MemOpChains2.empty())
3482 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3484 // Store the return address to the appropriate stack slot.
3485 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3486 isPPC64, isDarwinABI, dl);
3488 // Emit callseq_end just before tailcall node.
3489 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3490 DAG.getIntPtrConstant(0, true), InFlag, dl);
3491 InFlag = Chain.getValue(1);
3495 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3496 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3497 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3498 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3499 const PPCSubtarget &Subtarget) {
3501 bool isPPC64 = Subtarget.isPPC64();
3502 bool isSVR4ABI = Subtarget.isSVR4ABI();
3503 bool isELFv2ABI = Subtarget.isELFv2ABI();
3505 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3506 NodeTys.push_back(MVT::Other); // Returns a chain
3507 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3509 unsigned CallOpc = PPCISD::CALL;
3511 bool needIndirectCall = true;
3512 if (!isSVR4ABI || !isPPC64)
3513 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3514 // If this is an absolute destination address, use the munged value.
3515 Callee = SDValue(Dest, 0);
3516 needIndirectCall = false;
3519 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3520 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3521 // Use indirect calls for ALL functions calls in JIT mode, since the
3522 // far-call stubs may be outside relocation limits for a BL instruction.
3523 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3524 unsigned OpFlags = 0;
3525 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3526 (Subtarget.getTargetTriple().isMacOSX() &&
3527 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3528 (G->getGlobal()->isDeclaration() ||
3529 G->getGlobal()->isWeakForLinker())) ||
3530 (Subtarget.isTargetELF() && !isPPC64 &&
3531 !G->getGlobal()->hasLocalLinkage() &&
3532 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3533 // PC-relative references to external symbols should go through $stub,
3534 // unless we're building with the leopard linker or later, which
3535 // automatically synthesizes these stubs.
3536 OpFlags = PPCII::MO_PLT_OR_STUB;
3539 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3540 // every direct call is) turn it into a TargetGlobalAddress /
3541 // TargetExternalSymbol node so that legalize doesn't hack it.
3542 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3543 Callee.getValueType(),
3545 needIndirectCall = false;
3549 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3550 unsigned char OpFlags = 0;
3552 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3553 (Subtarget.getTargetTriple().isMacOSX() &&
3554 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3555 (Subtarget.isTargetELF() && !isPPC64 &&
3556 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3557 // PC-relative references to external symbols should go through $stub,
3558 // unless we're building with the leopard linker or later, which
3559 // automatically synthesizes these stubs.
3560 OpFlags = PPCII::MO_PLT_OR_STUB;
3563 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3565 needIndirectCall = false;
3568 if (needIndirectCall) {
3569 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3570 // to do the call, we can't use PPCISD::CALL.
3571 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3573 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3574 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3575 // entry point, but to the function descriptor (the function entry point
3576 // address is part of the function descriptor though).
3577 // The function descriptor is a three doubleword structure with the
3578 // following fields: function entry point, TOC base address and
3579 // environment pointer.
3580 // Thus for a call through a function pointer, the following actions need
3582 // 1. Save the TOC of the caller in the TOC save area of its stack
3583 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3584 // 2. Load the address of the function entry point from the function
3586 // 3. Load the TOC of the callee from the function descriptor into r2.
3587 // 4. Load the environment pointer from the function descriptor into
3589 // 5. Branch to the function entry point address.
3590 // 6. On return of the callee, the TOC of the caller needs to be
3591 // restored (this is done in FinishCall()).
3593 // All those operations are flagged together to ensure that no other
3594 // operations can be scheduled in between. E.g. without flagging the
3595 // operations together, a TOC access in the caller could be scheduled
3596 // between the load of the callee TOC and the branch to the callee, which
3597 // results in the TOC access going through the TOC of the callee instead
3598 // of going through the TOC of the caller, which leads to incorrect code.
3600 // Load the address of the function entry point from the function
3602 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3603 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3604 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3605 Chain = LoadFuncPtr.getValue(1);
3606 InFlag = LoadFuncPtr.getValue(2);
3608 // Load environment pointer into r11.
3609 // Offset of the environment pointer within the function descriptor.
3610 SDValue PtrOff = DAG.getIntPtrConstant(16);
3612 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3613 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3615 Chain = LoadEnvPtr.getValue(1);
3616 InFlag = LoadEnvPtr.getValue(2);
3618 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3620 Chain = EnvVal.getValue(0);
3621 InFlag = EnvVal.getValue(1);
3623 // Load TOC of the callee into r2. We are using a target-specific load
3624 // with r2 hard coded, because the result of a target-independent load
3625 // would never go directly into r2, since r2 is a reserved register (which
3626 // prevents the register allocator from allocating it), resulting in an
3627 // additional register being allocated and an unnecessary move instruction
3629 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3630 SDValue TOCOff = DAG.getIntPtrConstant(8);
3631 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3632 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3634 Chain = LoadTOCPtr.getValue(0);
3635 InFlag = LoadTOCPtr.getValue(1);
3637 MTCTROps[0] = Chain;
3638 MTCTROps[1] = LoadFuncPtr;
3639 MTCTROps[2] = InFlag;
3642 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3643 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3644 InFlag = Chain.getValue(1);
3647 NodeTys.push_back(MVT::Other);
3648 NodeTys.push_back(MVT::Glue);
3649 Ops.push_back(Chain);
3650 CallOpc = PPCISD::BCTRL;
3651 Callee.setNode(nullptr);
3652 // Add use of X11 (holding environment pointer)
3653 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3654 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3655 // Add CTR register as callee so a bctr can be emitted later.
3657 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3660 // If this is a direct call, pass the chain and the callee.
3661 if (Callee.getNode()) {
3662 Ops.push_back(Chain);
3663 Ops.push_back(Callee);
3665 // If this is a tail call add stack pointer delta.
3667 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3669 // Add argument registers to the end of the list so that they are known live
3671 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3672 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3673 RegsToPass[i].second.getValueType()));
3675 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3676 if (Callee.getNode() && isELFv2ABI)
3677 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3683 bool isLocalCall(const SDValue &Callee)
3685 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3686 return !G->getGlobal()->isDeclaration() &&
3687 !G->getGlobal()->isWeakForLinker();
3692 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3693 CallingConv::ID CallConv, bool isVarArg,
3694 const SmallVectorImpl<ISD::InputArg> &Ins,
3695 SDLoc dl, SelectionDAG &DAG,
3696 SmallVectorImpl<SDValue> &InVals) const {
3698 SmallVector<CCValAssign, 16> RVLocs;
3699 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3700 getTargetMachine(), RVLocs, *DAG.getContext());
3701 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3703 // Copy all of the result registers out of their specified physreg.
3704 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3705 CCValAssign &VA = RVLocs[i];
3706 assert(VA.isRegLoc() && "Can only return in registers!");
3708 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3709 VA.getLocReg(), VA.getLocVT(), InFlag);
3710 Chain = Val.getValue(1);
3711 InFlag = Val.getValue(2);
3713 switch (VA.getLocInfo()) {
3714 default: llvm_unreachable("Unknown loc info!");
3715 case CCValAssign::Full: break;
3716 case CCValAssign::AExt:
3717 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3719 case CCValAssign::ZExt:
3720 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3721 DAG.getValueType(VA.getValVT()));
3722 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3724 case CCValAssign::SExt:
3725 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3726 DAG.getValueType(VA.getValVT()));
3727 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3731 InVals.push_back(Val);
3738 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3739 bool isTailCall, bool isVarArg,
3741 SmallVector<std::pair<unsigned, SDValue>, 8>
3743 SDValue InFlag, SDValue Chain,
3745 int SPDiff, unsigned NumBytes,
3746 const SmallVectorImpl<ISD::InputArg> &Ins,
3747 SmallVectorImpl<SDValue> &InVals) const {
3749 bool isELFv2ABI = Subtarget.isELFv2ABI();
3750 std::vector<EVT> NodeTys;
3751 SmallVector<SDValue, 8> Ops;
3752 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3753 isTailCall, RegsToPass, Ops, NodeTys,
3756 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3757 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3758 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3760 // When performing tail call optimization the callee pops its arguments off
3761 // the stack. Account for this here so these bytes can be pushed back on in
3762 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3763 int BytesCalleePops =
3764 (CallConv == CallingConv::Fast &&
3765 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3767 // Add a register mask operand representing the call-preserved registers.
3768 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3769 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3770 assert(Mask && "Missing call preserved mask for calling convention");
3771 Ops.push_back(DAG.getRegisterMask(Mask));
3773 if (InFlag.getNode())
3774 Ops.push_back(InFlag);
3778 assert(((Callee.getOpcode() == ISD::Register &&
3779 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3780 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3781 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3782 isa<ConstantSDNode>(Callee)) &&
3783 "Expecting an global address, external symbol, absolute value or register");
3785 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3788 // Add a NOP immediately after the branch instruction when using the 64-bit
3789 // SVR4 ABI. At link time, if caller and callee are in a different module and
3790 // thus have a different TOC, the call will be replaced with a call to a stub
3791 // function which saves the current TOC, loads the TOC of the callee and
3792 // branches to the callee. The NOP will be replaced with a load instruction
3793 // which restores the TOC of the caller from the TOC save slot of the current
3794 // stack frame. If caller and callee belong to the same module (and have the
3795 // same TOC), the NOP will remain unchanged.
3797 bool needsTOCRestore = false;
3798 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3799 if (CallOpc == PPCISD::BCTRL) {
3800 // This is a call through a function pointer.
3801 // Restore the caller TOC from the save area into R2.
3802 // See PrepareCall() for more information about calls through function
3803 // pointers in the 64-bit SVR4 ABI.
3804 // We are using a target-specific load with r2 hard coded, because the
3805 // result of a target-independent load would never go directly into r2,
3806 // since r2 is a reserved register (which prevents the register allocator
3807 // from allocating it), resulting in an additional register being
3808 // allocated and an unnecessary move instruction being generated.
3809 needsTOCRestore = true;
3810 } else if ((CallOpc == PPCISD::CALL) &&
3811 (!isLocalCall(Callee) ||
3812 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3813 // Otherwise insert NOP for non-local calls.
3814 CallOpc = PPCISD::CALL_NOP;
3818 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3819 InFlag = Chain.getValue(1);
3821 if (needsTOCRestore) {
3822 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3823 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3824 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3825 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3826 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3827 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3828 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3829 InFlag = Chain.getValue(1);
3832 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3833 DAG.getIntPtrConstant(BytesCalleePops, true),
3836 InFlag = Chain.getValue(1);
3838 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3839 Ins, dl, DAG, InVals);
3843 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3844 SmallVectorImpl<SDValue> &InVals) const {
3845 SelectionDAG &DAG = CLI.DAG;
3847 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3848 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3849 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3850 SDValue Chain = CLI.Chain;
3851 SDValue Callee = CLI.Callee;
3852 bool &isTailCall = CLI.IsTailCall;
3853 CallingConv::ID CallConv = CLI.CallConv;
3854 bool isVarArg = CLI.IsVarArg;
3857 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3860 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3861 report_fatal_error("failed to perform tail call elimination on a call "
3862 "site marked musttail");
3864 if (Subtarget.isSVR4ABI()) {
3865 if (Subtarget.isPPC64())
3866 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3867 isTailCall, Outs, OutVals, Ins,
3870 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3871 isTailCall, Outs, OutVals, Ins,
3875 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3876 isTailCall, Outs, OutVals, Ins,
3881 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3882 CallingConv::ID CallConv, bool isVarArg,
3884 const SmallVectorImpl<ISD::OutputArg> &Outs,
3885 const SmallVectorImpl<SDValue> &OutVals,
3886 const SmallVectorImpl<ISD::InputArg> &Ins,
3887 SDLoc dl, SelectionDAG &DAG,
3888 SmallVectorImpl<SDValue> &InVals) const {
3889 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3890 // of the 32-bit SVR4 ABI stack frame layout.
3892 assert((CallConv == CallingConv::C ||
3893 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3895 unsigned PtrByteSize = 4;
3897 MachineFunction &MF = DAG.getMachineFunction();
3899 // Mark this function as potentially containing a function that contains a
3900 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3901 // and restoring the callers stack pointer in this functions epilog. This is
3902 // done because by tail calling the called function might overwrite the value
3903 // in this function's (MF) stack pointer stack slot 0(SP).
3904 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3905 CallConv == CallingConv::Fast)
3906 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3908 // Count how many bytes are to be pushed on the stack, including the linkage
3909 // area, parameter list area and the part of the local variable space which
3910 // contains copies of aggregates which are passed by value.
3912 // Assign locations to all of the outgoing arguments.
3913 SmallVector<CCValAssign, 16> ArgLocs;
3914 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3915 getTargetMachine(), ArgLocs, *DAG.getContext());
3917 // Reserve space for the linkage area on the stack.
3918 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3922 // Handle fixed and variable vector arguments differently.
3923 // Fixed vector arguments go into registers as long as registers are
3924 // available. Variable vector arguments always go into memory.
3925 unsigned NumArgs = Outs.size();
3927 for (unsigned i = 0; i != NumArgs; ++i) {
3928 MVT ArgVT = Outs[i].VT;
3929 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3932 if (Outs[i].IsFixed) {
3933 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3936 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3942 errs() << "Call operand #" << i << " has unhandled type "
3943 << EVT(ArgVT).getEVTString() << "\n";
3945 llvm_unreachable(nullptr);
3949 // All arguments are treated the same.
3950 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3953 // Assign locations to all of the outgoing aggregate by value arguments.
3954 SmallVector<CCValAssign, 16> ByValArgLocs;
3955 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3956 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3958 // Reserve stack space for the allocations in CCInfo.
3959 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3961 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3963 // Size of the linkage area, parameter list area and the part of the local
3964 // space variable where copies of aggregates which are passed by value are
3966 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3968 // Calculate by how many bytes the stack has to be adjusted in case of tail
3969 // call optimization.
3970 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3972 // Adjust the stack pointer for the new arguments...
3973 // These operations are automatically eliminated by the prolog/epilog pass
3974 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3976 SDValue CallSeqStart = Chain;
3978 // Load the return address and frame pointer so it can be moved somewhere else
3981 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3984 // Set up a copy of the stack pointer for use loading and storing any
3985 // arguments that may not fit in the registers available for argument
3987 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3989 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3990 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3991 SmallVector<SDValue, 8> MemOpChains;
3993 bool seenFloatArg = false;
3994 // Walk the register/memloc assignments, inserting copies/loads.
3995 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3998 CCValAssign &VA = ArgLocs[i];
3999 SDValue Arg = OutVals[i];
4000 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4002 if (Flags.isByVal()) {
4003 // Argument is an aggregate which is passed by value, thus we need to
4004 // create a copy of it in the local variable space of the current stack
4005 // frame (which is the stack frame of the caller) and pass the address of
4006 // this copy to the callee.
4007 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4008 CCValAssign &ByValVA = ByValArgLocs[j++];
4009 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4011 // Memory reserved in the local variable space of the callers stack frame.
4012 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4014 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4015 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4017 // Create a copy of the argument in the local area of the current
4019 SDValue MemcpyCall =
4020 CreateCopyOfByValArgument(Arg, PtrOff,
4021 CallSeqStart.getNode()->getOperand(0),
4024 // This must go outside the CALLSEQ_START..END.
4025 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4026 CallSeqStart.getNode()->getOperand(1),
4028 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4029 NewCallSeqStart.getNode());
4030 Chain = CallSeqStart = NewCallSeqStart;
4032 // Pass the address of the aggregate copy on the stack either in a
4033 // physical register or in the parameter list area of the current stack
4034 // frame to the callee.
4038 if (VA.isRegLoc()) {
4039 if (Arg.getValueType() == MVT::i1)
4040 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4042 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4043 // Put argument in a physical register.
4044 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4046 // Put argument in the parameter list area of the current stack frame.
4047 assert(VA.isMemLoc());
4048 unsigned LocMemOffset = VA.getLocMemOffset();
4051 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4052 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4054 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4055 MachinePointerInfo(),
4058 // Calculate and remember argument location.
4059 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4065 if (!MemOpChains.empty())
4066 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4068 // Build a sequence of copy-to-reg nodes chained together with token chain
4069 // and flag operands which copy the outgoing args into the appropriate regs.
4071 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4072 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4073 RegsToPass[i].second, InFlag);
4074 InFlag = Chain.getValue(1);
4077 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4080 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4081 SDValue Ops[] = { Chain, InFlag };
4083 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4084 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4086 InFlag = Chain.getValue(1);
4090 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4091 false, TailCallArguments);
4093 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4094 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4098 // Copy an argument into memory, being careful to do this outside the
4099 // call sequence for the call to which the argument belongs.
4101 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4102 SDValue CallSeqStart,
4103 ISD::ArgFlagsTy Flags,
4106 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4107 CallSeqStart.getNode()->getOperand(0),
4109 // The MEMCPY must go outside the CALLSEQ_START..END.
4110 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4111 CallSeqStart.getNode()->getOperand(1),
4113 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4114 NewCallSeqStart.getNode());
4115 return NewCallSeqStart;
4119 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4120 CallingConv::ID CallConv, bool isVarArg,
4122 const SmallVectorImpl<ISD::OutputArg> &Outs,
4123 const SmallVectorImpl<SDValue> &OutVals,
4124 const SmallVectorImpl<ISD::InputArg> &Ins,
4125 SDLoc dl, SelectionDAG &DAG,
4126 SmallVectorImpl<SDValue> &InVals) const {
4128 bool isELFv2ABI = Subtarget.isELFv2ABI();
4129 bool isLittleEndian = Subtarget.isLittleEndian();
4130 unsigned NumOps = Outs.size();
4132 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4133 unsigned PtrByteSize = 8;
4135 MachineFunction &MF = DAG.getMachineFunction();
4137 // Mark this function as potentially containing a function that contains a
4138 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4139 // and restoring the callers stack pointer in this functions epilog. This is
4140 // done because by tail calling the called function might overwrite the value
4141 // in this function's (MF) stack pointer stack slot 0(SP).
4142 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4143 CallConv == CallingConv::Fast)
4144 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4146 // Count how many bytes are to be pushed on the stack, including the linkage
4147 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4148 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4149 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4150 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4152 unsigned NumBytes = LinkageSize;
4154 // Add up all the space actually used.
4155 for (unsigned i = 0; i != NumOps; ++i) {
4156 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4157 EVT ArgVT = Outs[i].VT;
4158 EVT OrigVT = Outs[i].ArgVT;
4160 /* Respect alignment of argument on the stack. */
4162 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4163 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4165 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4166 if (Flags.isInConsecutiveRegsLast())
4167 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4170 unsigned NumBytesActuallyUsed = NumBytes;
4172 // The prolog code of the callee may store up to 8 GPR argument registers to
4173 // the stack, allowing va_start to index over them in memory if its varargs.
4174 // Because we cannot tell if this is needed on the caller side, we have to
4175 // conservatively assume that it is needed. As such, make sure we have at
4176 // least enough stack space for the caller to store the 8 GPRs.
4177 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4178 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4180 // Tail call needs the stack to be aligned.
4181 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4182 CallConv == CallingConv::Fast)
4183 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4185 // Calculate by how many bytes the stack has to be adjusted in case of tail
4186 // call optimization.
4187 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4189 // To protect arguments on the stack from being clobbered in a tail call,
4190 // force all the loads to happen before doing any other lowering.
4192 Chain = DAG.getStackArgumentTokenFactor(Chain);
4194 // Adjust the stack pointer for the new arguments...
4195 // These operations are automatically eliminated by the prolog/epilog pass
4196 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4198 SDValue CallSeqStart = Chain;
4200 // Load the return address and frame pointer so it can be move somewhere else
4203 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4206 // Set up a copy of the stack pointer for use loading and storing any
4207 // arguments that may not fit in the registers available for argument
4209 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4211 // Figure out which arguments are going to go in registers, and which in
4212 // memory. Also, if this is a vararg function, floating point operations
4213 // must be stored to our stack, and loaded into integer regs as well, if
4214 // any integer regs are available for argument passing.
4215 unsigned ArgOffset = LinkageSize;
4216 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4218 static const MCPhysReg GPR[] = {
4219 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4220 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4222 static const MCPhysReg *FPR = GetFPR();
4224 static const MCPhysReg VR[] = {
4225 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4226 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4228 static const MCPhysReg VSRH[] = {
4229 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4230 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4233 const unsigned NumGPRs = array_lengthof(GPR);
4234 const unsigned NumFPRs = 13;
4235 const unsigned NumVRs = array_lengthof(VR);
4237 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4238 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4240 SmallVector<SDValue, 8> MemOpChains;
4241 for (unsigned i = 0; i != NumOps; ++i) {
4242 SDValue Arg = OutVals[i];
4243 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4244 EVT ArgVT = Outs[i].VT;
4245 EVT OrigVT = Outs[i].ArgVT;
4247 /* Respect alignment of argument on the stack. */
4249 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4250 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4252 /* Compute GPR index associated with argument offset. */
4253 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4254 GPR_idx = std::min(GPR_idx, NumGPRs);
4256 // PtrOff will be used to store the current argument to the stack if a
4257 // register cannot be found for it.
4260 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4262 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4264 // Promote integers to 64-bit values.
4265 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4266 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4267 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4268 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4271 // FIXME memcpy is used way more than necessary. Correctness first.
4272 // Note: "by value" is code for passing a structure by value, not
4274 if (Flags.isByVal()) {
4275 // Note: Size includes alignment padding, so
4276 // struct x { short a; char b; }
4277 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4278 // These are the proper values we need for right-justifying the
4279 // aggregate in a parameter register.
4280 unsigned Size = Flags.getByValSize();
4282 // An empty aggregate parameter takes up no storage and no
4287 // All aggregates smaller than 8 bytes must be passed right-justified.
4288 if (Size==1 || Size==2 || Size==4) {
4289 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4290 if (GPR_idx != NumGPRs) {
4291 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4292 MachinePointerInfo(), VT,
4294 MemOpChains.push_back(Load.getValue(1));
4295 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4297 ArgOffset += PtrByteSize;
4302 if (GPR_idx == NumGPRs && Size < 8) {
4303 SDValue AddPtr = PtrOff;
4304 if (!isLittleEndian) {
4305 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4306 PtrOff.getValueType());
4307 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4309 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4312 ArgOffset += PtrByteSize;
4315 // Copy entire object into memory. There are cases where gcc-generated
4316 // code assumes it is there, even if it could be put entirely into
4317 // registers. (This is not what the doc says.)
4319 // FIXME: The above statement is likely due to a misunderstanding of the
4320 // documents. All arguments must be copied into the parameter area BY
4321 // THE CALLEE in the event that the callee takes the address of any
4322 // formal argument. That has not yet been implemented. However, it is
4323 // reasonable to use the stack area as a staging area for the register
4326 // Skip this for small aggregates, as we will use the same slot for a
4327 // right-justified copy, below.
4329 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4333 // When a register is available, pass a small aggregate right-justified.
4334 if (Size < 8 && GPR_idx != NumGPRs) {
4335 // The easiest way to get this right-justified in a register
4336 // is to copy the structure into the rightmost portion of a
4337 // local variable slot, then load the whole slot into the
4339 // FIXME: The memcpy seems to produce pretty awful code for
4340 // small aggregates, particularly for packed ones.
4341 // FIXME: It would be preferable to use the slot in the
4342 // parameter save area instead of a new local variable.
4343 SDValue AddPtr = PtrOff;
4344 if (!isLittleEndian) {
4345 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4346 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4348 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4352 // Load the slot into the register.
4353 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4354 MachinePointerInfo(),
4355 false, false, false, 0);
4356 MemOpChains.push_back(Load.getValue(1));
4357 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4359 // Done with this argument.
4360 ArgOffset += PtrByteSize;
4364 // For aggregates larger than PtrByteSize, copy the pieces of the
4365 // object that fit into registers from the parameter save area.
4366 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4367 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4368 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4369 if (GPR_idx != NumGPRs) {
4370 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4371 MachinePointerInfo(),
4372 false, false, false, 0);
4373 MemOpChains.push_back(Load.getValue(1));
4374 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4375 ArgOffset += PtrByteSize;
4377 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4384 switch (Arg.getSimpleValueType().SimpleTy) {
4385 default: llvm_unreachable("Unexpected ValueType for argument!");
4389 // These can be scalar arguments or elements of an integer array type
4390 // passed directly. Clang may use those instead of "byval" aggregate
4391 // types to avoid forcing arguments to memory unnecessarily.
4392 if (GPR_idx != NumGPRs) {
4393 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4395 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4396 true, isTailCall, false, MemOpChains,
4397 TailCallArguments, dl);
4399 ArgOffset += PtrByteSize;
4403 // These can be scalar arguments or elements of a float array type
4404 // passed directly. The latter are used to implement ELFv2 homogenous
4405 // float aggregates.
4407 // Named arguments go into FPRs first, and once they overflow, the
4408 // remaining arguments go into GPRs and then the parameter save area.
4409 // Unnamed arguments for vararg functions always go to GPRs and
4410 // then the parameter save area. For now, put all arguments to vararg
4411 // routines always in both locations (FPR *and* GPR or stack slot).
4412 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4414 // First load the argument into the next available FPR.
4415 if (FPR_idx != NumFPRs)
4416 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4418 // Next, load the argument into GPR or stack slot if needed.
4419 if (!NeedGPROrStack)
4421 else if (GPR_idx != NumGPRs) {
4422 // In the non-vararg case, this can only ever happen in the
4423 // presence of f32 array types, since otherwise we never run
4424 // out of FPRs before running out of GPRs.
4427 // Double values are always passed in a single GPR.
4428 if (Arg.getValueType() != MVT::f32) {
4429 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4431 // Non-array float values are extended and passed in a GPR.
4432 } else if (!Flags.isInConsecutiveRegs()) {
4433 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4434 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4436 // If we have an array of floats, we collect every odd element
4437 // together with its predecessor into one GPR.
4438 } else if (ArgOffset % PtrByteSize != 0) {
4440 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4441 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4442 if (!isLittleEndian)
4444 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4446 // The final element, if even, goes into the first half of a GPR.
4447 } else if (Flags.isInConsecutiveRegsLast()) {
4448 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4449 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4450 if (!isLittleEndian)
4451 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4452 DAG.getConstant(32, MVT::i32));
4454 // Non-final even elements are skipped; they will be handled
4455 // together the with subsequent argument on the next go-around.
4459 if (ArgVal.getNode())
4460 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4462 // Single-precision floating-point values are mapped to the
4463 // second (rightmost) word of the stack doubleword.
4464 if (Arg.getValueType() == MVT::f32 &&
4465 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4466 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4467 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4470 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4471 true, isTailCall, false, MemOpChains,
4472 TailCallArguments, dl);
4474 // When passing an array of floats, the array occupies consecutive
4475 // space in the argument area; only round up to the next doubleword
4476 // at the end of the array. Otherwise, each float takes 8 bytes.
4477 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4478 Flags.isInConsecutiveRegs()) ? 4 : 8;
4479 if (Flags.isInConsecutiveRegsLast())
4480 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4489 // These can be scalar arguments or elements of a vector array type
4490 // passed directly. The latter are used to implement ELFv2 homogenous
4491 // vector aggregates.
4493 // For a varargs call, named arguments go into VRs or on the stack as
4494 // usual; unnamed arguments always go to the stack or the corresponding
4495 // GPRs when within range. For now, we always put the value in both
4496 // locations (or even all three).
4498 // We could elide this store in the case where the object fits
4499 // entirely in R registers. Maybe later.
4500 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4501 MachinePointerInfo(), false, false, 0);
4502 MemOpChains.push_back(Store);
4503 if (VR_idx != NumVRs) {
4504 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4505 MachinePointerInfo(),
4506 false, false, false, 0);
4507 MemOpChains.push_back(Load.getValue(1));
4509 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4510 Arg.getSimpleValueType() == MVT::v2i64) ?
4511 VSRH[VR_idx] : VR[VR_idx];
4514 RegsToPass.push_back(std::make_pair(VReg, Load));
4517 for (unsigned i=0; i<16; i+=PtrByteSize) {
4518 if (GPR_idx == NumGPRs)
4520 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4521 DAG.getConstant(i, PtrVT));
4522 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4523 false, false, false, 0);
4524 MemOpChains.push_back(Load.getValue(1));
4525 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4530 // Non-varargs Altivec params go into VRs or on the stack.
4531 if (VR_idx != NumVRs) {
4532 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4533 Arg.getSimpleValueType() == MVT::v2i64) ?
4534 VSRH[VR_idx] : VR[VR_idx];
4537 RegsToPass.push_back(std::make_pair(VReg, Arg));
4539 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4540 true, isTailCall, true, MemOpChains,
4541 TailCallArguments, dl);
4548 assert(NumBytesActuallyUsed == ArgOffset);
4549 (void)NumBytesActuallyUsed;
4551 if (!MemOpChains.empty())
4552 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4554 // Check if this is an indirect call (MTCTR/BCTRL).
4555 // See PrepareCall() for more information about calls through function
4556 // pointers in the 64-bit SVR4 ABI.
4558 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4559 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4560 // Load r2 into a virtual register and store it to the TOC save area.
4561 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4562 // TOC save area offset.
4563 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4564 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4565 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4566 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4568 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4569 // This does not mean the MTCTR instruction must use R12; it's easier
4570 // to model this as an extra parameter, so do that.
4572 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4575 // Build a sequence of copy-to-reg nodes chained together with token chain
4576 // and flag operands which copy the outgoing args into the appropriate regs.
4578 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4579 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4580 RegsToPass[i].second, InFlag);
4581 InFlag = Chain.getValue(1);
4585 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4586 FPOp, true, TailCallArguments);
4588 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4589 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4594 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4595 CallingConv::ID CallConv, bool isVarArg,
4597 const SmallVectorImpl<ISD::OutputArg> &Outs,
4598 const SmallVectorImpl<SDValue> &OutVals,
4599 const SmallVectorImpl<ISD::InputArg> &Ins,
4600 SDLoc dl, SelectionDAG &DAG,
4601 SmallVectorImpl<SDValue> &InVals) const {
4603 unsigned NumOps = Outs.size();
4605 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4606 bool isPPC64 = PtrVT == MVT::i64;
4607 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4609 MachineFunction &MF = DAG.getMachineFunction();
4611 // Mark this function as potentially containing a function that contains a
4612 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4613 // and restoring the callers stack pointer in this functions epilog. This is
4614 // done because by tail calling the called function might overwrite the value
4615 // in this function's (MF) stack pointer stack slot 0(SP).
4616 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4617 CallConv == CallingConv::Fast)
4618 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4620 // Count how many bytes are to be pushed on the stack, including the linkage
4621 // area, and parameter passing area. We start with 24/48 bytes, which is
4622 // prereserved space for [SP][CR][LR][3 x unused].
4623 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4625 unsigned NumBytes = LinkageSize;
4627 // Add up all the space actually used.
4628 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4629 // they all go in registers, but we must reserve stack space for them for
4630 // possible use by the caller. In varargs or 64-bit calls, parameters are
4631 // assigned stack space in order, with padding so Altivec parameters are
4633 unsigned nAltivecParamsAtEnd = 0;
4634 for (unsigned i = 0; i != NumOps; ++i) {
4635 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4636 EVT ArgVT = Outs[i].VT;
4637 // Varargs Altivec parameters are padded to a 16 byte boundary.
4638 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4639 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4640 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4641 if (!isVarArg && !isPPC64) {
4642 // Non-varargs Altivec parameters go after all the non-Altivec
4643 // parameters; handle those later so we know how much padding we need.
4644 nAltivecParamsAtEnd++;
4647 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4648 NumBytes = ((NumBytes+15)/16)*16;
4650 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4653 // Allow for Altivec parameters at the end, if needed.
4654 if (nAltivecParamsAtEnd) {
4655 NumBytes = ((NumBytes+15)/16)*16;
4656 NumBytes += 16*nAltivecParamsAtEnd;
4659 // The prolog code of the callee may store up to 8 GPR argument registers to
4660 // the stack, allowing va_start to index over them in memory if its varargs.
4661 // Because we cannot tell if this is needed on the caller side, we have to
4662 // conservatively assume that it is needed. As such, make sure we have at
4663 // least enough stack space for the caller to store the 8 GPRs.
4664 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4666 // Tail call needs the stack to be aligned.
4667 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4668 CallConv == CallingConv::Fast)
4669 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4671 // Calculate by how many bytes the stack has to be adjusted in case of tail
4672 // call optimization.
4673 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4675 // To protect arguments on the stack from being clobbered in a tail call,
4676 // force all the loads to happen before doing any other lowering.
4678 Chain = DAG.getStackArgumentTokenFactor(Chain);
4680 // Adjust the stack pointer for the new arguments...
4681 // These operations are automatically eliminated by the prolog/epilog pass
4682 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4684 SDValue CallSeqStart = Chain;
4686 // Load the return address and frame pointer so it can be move somewhere else
4689 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4692 // Set up a copy of the stack pointer for use loading and storing any
4693 // arguments that may not fit in the registers available for argument
4697 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4699 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4701 // Figure out which arguments are going to go in registers, and which in
4702 // memory. Also, if this is a vararg function, floating point operations
4703 // must be stored to our stack, and loaded into integer regs as well, if
4704 // any integer regs are available for argument passing.
4705 unsigned ArgOffset = LinkageSize;
4706 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4708 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4709 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4710 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4712 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4713 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4714 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4716 static const MCPhysReg *FPR = GetFPR();
4718 static const MCPhysReg VR[] = {
4719 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4720 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4722 const unsigned NumGPRs = array_lengthof(GPR_32);
4723 const unsigned NumFPRs = 13;
4724 const unsigned NumVRs = array_lengthof(VR);
4726 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4728 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4729 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4731 SmallVector<SDValue, 8> MemOpChains;
4732 for (unsigned i = 0; i != NumOps; ++i) {
4733 SDValue Arg = OutVals[i];
4734 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4736 // PtrOff will be used to store the current argument to the stack if a
4737 // register cannot be found for it.
4740 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4742 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4744 // On PPC64, promote integers to 64-bit values.
4745 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4746 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4747 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4748 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4751 // FIXME memcpy is used way more than necessary. Correctness first.
4752 // Note: "by value" is code for passing a structure by value, not
4754 if (Flags.isByVal()) {
4755 unsigned Size = Flags.getByValSize();
4756 // Very small objects are passed right-justified. Everything else is
4757 // passed left-justified.
4758 if (Size==1 || Size==2) {
4759 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4760 if (GPR_idx != NumGPRs) {
4761 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4762 MachinePointerInfo(), VT,
4764 MemOpChains.push_back(Load.getValue(1));
4765 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4767 ArgOffset += PtrByteSize;
4769 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4770 PtrOff.getValueType());
4771 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4772 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4775 ArgOffset += PtrByteSize;
4779 // Copy entire object into memory. There are cases where gcc-generated
4780 // code assumes it is there, even if it could be put entirely into
4781 // registers. (This is not what the doc says.)
4782 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4786 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4787 // copy the pieces of the object that fit into registers from the
4788 // parameter save area.
4789 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4790 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4791 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4792 if (GPR_idx != NumGPRs) {
4793 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4794 MachinePointerInfo(),
4795 false, false, false, 0);
4796 MemOpChains.push_back(Load.getValue(1));
4797 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4798 ArgOffset += PtrByteSize;
4800 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4807 switch (Arg.getSimpleValueType().SimpleTy) {
4808 default: llvm_unreachable("Unexpected ValueType for argument!");
4812 if (GPR_idx != NumGPRs) {
4813 if (Arg.getValueType() == MVT::i1)
4814 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4816 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4818 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4819 isPPC64, isTailCall, false, MemOpChains,
4820 TailCallArguments, dl);
4822 ArgOffset += PtrByteSize;
4826 if (FPR_idx != NumFPRs) {
4827 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4830 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4831 MachinePointerInfo(), false, false, 0);
4832 MemOpChains.push_back(Store);
4834 // Float varargs are always shadowed in available integer registers
4835 if (GPR_idx != NumGPRs) {
4836 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4837 MachinePointerInfo(), false, false,
4839 MemOpChains.push_back(Load.getValue(1));
4840 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4842 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4843 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4844 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4845 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4846 MachinePointerInfo(),
4847 false, false, false, 0);
4848 MemOpChains.push_back(Load.getValue(1));
4849 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4852 // If we have any FPRs remaining, we may also have GPRs remaining.
4853 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4855 if (GPR_idx != NumGPRs)
4857 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4858 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4862 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4863 isPPC64, isTailCall, false, MemOpChains,
4864 TailCallArguments, dl);
4868 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4875 // These go aligned on the stack, or in the corresponding R registers
4876 // when within range. The Darwin PPC ABI doc claims they also go in
4877 // V registers; in fact gcc does this only for arguments that are
4878 // prototyped, not for those that match the ... We do it for all
4879 // arguments, seems to work.
4880 while (ArgOffset % 16 !=0) {
4881 ArgOffset += PtrByteSize;
4882 if (GPR_idx != NumGPRs)
4885 // We could elide this store in the case where the object fits
4886 // entirely in R registers. Maybe later.
4887 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4888 DAG.getConstant(ArgOffset, PtrVT));
4889 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4890 MachinePointerInfo(), false, false, 0);
4891 MemOpChains.push_back(Store);
4892 if (VR_idx != NumVRs) {
4893 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4894 MachinePointerInfo(),
4895 false, false, false, 0);
4896 MemOpChains.push_back(Load.getValue(1));
4897 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4900 for (unsigned i=0; i<16; i+=PtrByteSize) {
4901 if (GPR_idx == NumGPRs)
4903 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4904 DAG.getConstant(i, PtrVT));
4905 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4906 false, false, false, 0);
4907 MemOpChains.push_back(Load.getValue(1));
4908 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4913 // Non-varargs Altivec params generally go in registers, but have
4914 // stack space allocated at the end.
4915 if (VR_idx != NumVRs) {
4916 // Doesn't have GPR space allocated.
4917 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4918 } else if (nAltivecParamsAtEnd==0) {
4919 // We are emitting Altivec params in order.
4920 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4921 isPPC64, isTailCall, true, MemOpChains,
4922 TailCallArguments, dl);
4928 // If all Altivec parameters fit in registers, as they usually do,
4929 // they get stack space following the non-Altivec parameters. We
4930 // don't track this here because nobody below needs it.
4931 // If there are more Altivec parameters than fit in registers emit
4933 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4935 // Offset is aligned; skip 1st 12 params which go in V registers.
4936 ArgOffset = ((ArgOffset+15)/16)*16;
4938 for (unsigned i = 0; i != NumOps; ++i) {
4939 SDValue Arg = OutVals[i];
4940 EVT ArgType = Outs[i].VT;
4941 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4942 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4945 // We are emitting Altivec params in order.
4946 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4947 isPPC64, isTailCall, true, MemOpChains,
4948 TailCallArguments, dl);
4955 if (!MemOpChains.empty())
4956 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4958 // On Darwin, R12 must contain the address of an indirect callee. This does
4959 // not mean the MTCTR instruction must use R12; it's easier to model this as
4960 // an extra parameter, so do that.
4962 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4963 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4964 !isBLACompatibleAddress(Callee, DAG))
4965 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4966 PPC::R12), Callee));
4968 // Build a sequence of copy-to-reg nodes chained together with token chain
4969 // and flag operands which copy the outgoing args into the appropriate regs.
4971 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4972 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4973 RegsToPass[i].second, InFlag);
4974 InFlag = Chain.getValue(1);
4978 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4979 FPOp, true, TailCallArguments);
4981 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4982 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4987 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4988 MachineFunction &MF, bool isVarArg,
4989 const SmallVectorImpl<ISD::OutputArg> &Outs,
4990 LLVMContext &Context) const {
4991 SmallVector<CCValAssign, 16> RVLocs;
4992 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4994 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4998 PPCTargetLowering::LowerReturn(SDValue Chain,
4999 CallingConv::ID CallConv, bool isVarArg,
5000 const SmallVectorImpl<ISD::OutputArg> &Outs,
5001 const SmallVectorImpl<SDValue> &OutVals,
5002 SDLoc dl, SelectionDAG &DAG) const {
5004 SmallVector<CCValAssign, 16> RVLocs;
5005 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
5006 getTargetMachine(), RVLocs, *DAG.getContext());
5007 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5010 SmallVector<SDValue, 4> RetOps(1, Chain);
5012 // Copy the result values into the output registers.
5013 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5014 CCValAssign &VA = RVLocs[i];
5015 assert(VA.isRegLoc() && "Can only return in registers!");
5017 SDValue Arg = OutVals[i];
5019 switch (VA.getLocInfo()) {
5020 default: llvm_unreachable("Unknown loc info!");
5021 case CCValAssign::Full: break;
5022 case CCValAssign::AExt:
5023 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5025 case CCValAssign::ZExt:
5026 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5028 case CCValAssign::SExt:
5029 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5033 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5034 Flag = Chain.getValue(1);
5035 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5038 RetOps[0] = Chain; // Update chain.
5040 // Add the flag if we have it.
5042 RetOps.push_back(Flag);
5044 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5047 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5048 const PPCSubtarget &Subtarget) const {
5049 // When we pop the dynamic allocation we need to restore the SP link.
5052 // Get the corect type for pointers.
5053 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5055 // Construct the stack pointer operand.
5056 bool isPPC64 = Subtarget.isPPC64();
5057 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5058 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5060 // Get the operands for the STACKRESTORE.
5061 SDValue Chain = Op.getOperand(0);
5062 SDValue SaveSP = Op.getOperand(1);
5064 // Load the old link SP.
5065 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5066 MachinePointerInfo(),
5067 false, false, false, 0);
5069 // Restore the stack pointer.
5070 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5072 // Store the old link SP.
5073 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5080 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5081 MachineFunction &MF = DAG.getMachineFunction();
5082 bool isPPC64 = Subtarget.isPPC64();
5083 bool isDarwinABI = Subtarget.isDarwinABI();
5084 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5086 // Get current frame pointer save index. The users of this index will be
5087 // primarily DYNALLOC instructions.
5088 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5089 int RASI = FI->getReturnAddrSaveIndex();
5091 // If the frame pointer save index hasn't been defined yet.
5093 // Find out what the fix offset of the frame pointer save area.
5094 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5095 // Allocate the frame index for frame pointer save area.
5096 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5098 FI->setReturnAddrSaveIndex(RASI);
5100 return DAG.getFrameIndex(RASI, PtrVT);
5104 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5105 MachineFunction &MF = DAG.getMachineFunction();
5106 bool isPPC64 = Subtarget.isPPC64();
5107 bool isDarwinABI = Subtarget.isDarwinABI();
5108 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5110 // Get current frame pointer save index. The users of this index will be
5111 // primarily DYNALLOC instructions.
5112 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5113 int FPSI = FI->getFramePointerSaveIndex();
5115 // If the frame pointer save index hasn't been defined yet.
5117 // Find out what the fix offset of the frame pointer save area.
5118 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5121 // Allocate the frame index for frame pointer save area.
5122 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5124 FI->setFramePointerSaveIndex(FPSI);
5126 return DAG.getFrameIndex(FPSI, PtrVT);
5129 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5131 const PPCSubtarget &Subtarget) const {
5133 SDValue Chain = Op.getOperand(0);
5134 SDValue Size = Op.getOperand(1);
5137 // Get the corect type for pointers.
5138 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5140 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5141 DAG.getConstant(0, PtrVT), Size);
5142 // Construct a node for the frame pointer save index.
5143 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5144 // Build a DYNALLOC node.
5145 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5146 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5147 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5150 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5151 SelectionDAG &DAG) const {
5153 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5154 DAG.getVTList(MVT::i32, MVT::Other),
5155 Op.getOperand(0), Op.getOperand(1));
5158 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5159 SelectionDAG &DAG) const {
5161 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5162 Op.getOperand(0), Op.getOperand(1));
5165 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5166 assert(Op.getValueType() == MVT::i1 &&
5167 "Custom lowering only for i1 loads");
5169 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5172 LoadSDNode *LD = cast<LoadSDNode>(Op);
5174 SDValue Chain = LD->getChain();
5175 SDValue BasePtr = LD->getBasePtr();
5176 MachineMemOperand *MMO = LD->getMemOperand();
5178 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5179 BasePtr, MVT::i8, MMO);
5180 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5182 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5183 return DAG.getMergeValues(Ops, dl);
5186 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5187 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5188 "Custom lowering only for i1 stores");
5190 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5193 StoreSDNode *ST = cast<StoreSDNode>(Op);
5195 SDValue Chain = ST->getChain();
5196 SDValue BasePtr = ST->getBasePtr();
5197 SDValue Value = ST->getValue();
5198 MachineMemOperand *MMO = ST->getMemOperand();
5200 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5201 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5204 // FIXME: Remove this once the ANDI glue bug is fixed:
5205 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5206 assert(Op.getValueType() == MVT::i1 &&
5207 "Custom lowering only for i1 results");
5210 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5214 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5216 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5217 // Not FP? Not a fsel.
5218 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5219 !Op.getOperand(2).getValueType().isFloatingPoint())
5222 // We might be able to do better than this under some circumstances, but in
5223 // general, fsel-based lowering of select is a finite-math-only optimization.
5224 // For more information, see section F.3 of the 2.06 ISA specification.
5225 if (!DAG.getTarget().Options.NoInfsFPMath ||
5226 !DAG.getTarget().Options.NoNaNsFPMath)
5229 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5231 EVT ResVT = Op.getValueType();
5232 EVT CmpVT = Op.getOperand(0).getValueType();
5233 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5234 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5237 // If the RHS of the comparison is a 0.0, we don't need to do the
5238 // subtraction at all.
5240 if (isFloatingPointZero(RHS))
5242 default: break; // SETUO etc aren't handled by fsel.
5246 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5247 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5248 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5249 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5250 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5251 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5252 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5255 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5258 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5259 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5260 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5263 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5266 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5267 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5268 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5269 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5274 default: break; // SETUO etc aren't handled by fsel.
5278 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5279 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5280 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5281 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5282 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5283 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5284 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5285 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5288 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5289 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5290 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5291 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5294 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5295 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5296 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5297 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5300 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5301 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5302 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5303 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5306 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5307 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5308 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5309 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5314 // FIXME: Split this code up when LegalizeDAGTypes lands.
5315 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5317 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5318 SDValue Src = Op.getOperand(0);
5319 if (Src.getValueType() == MVT::f32)
5320 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5323 switch (Op.getSimpleValueType().SimpleTy) {
5324 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5326 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5327 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5332 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5333 "i64 FP_TO_UINT is supported only with FPCVT");
5334 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5340 // Convert the FP value to an int value through memory.
5341 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5342 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5343 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5344 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5345 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5347 // Emit a store to the stack slot.
5350 MachineFunction &MF = DAG.getMachineFunction();
5351 MachineMemOperand *MMO =
5352 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5353 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5354 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5355 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5357 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5358 MPI, false, false, 0);
5360 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5362 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5363 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5364 DAG.getConstant(4, FIPtr.getValueType()));
5365 MPI = MachinePointerInfo();
5368 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5369 false, false, false, 0);
5372 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5373 SelectionDAG &DAG) const {
5375 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5376 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5379 if (Op.getOperand(0).getValueType() == MVT::i1)
5380 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5381 DAG.getConstantFP(1.0, Op.getValueType()),
5382 DAG.getConstantFP(0.0, Op.getValueType()));
5384 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5385 "UINT_TO_FP is supported only with FPCVT");
5387 // If we have FCFIDS, then use it when converting to single-precision.
5388 // Otherwise, convert to double-precision and then round.
5389 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5390 (Op.getOpcode() == ISD::UINT_TO_FP ?
5391 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5392 (Op.getOpcode() == ISD::UINT_TO_FP ?
5393 PPCISD::FCFIDU : PPCISD::FCFID);
5394 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5395 MVT::f32 : MVT::f64;
5397 if (Op.getOperand(0).getValueType() == MVT::i64) {
5398 SDValue SINT = Op.getOperand(0);
5399 // When converting to single-precision, we actually need to convert
5400 // to double-precision first and then round to single-precision.
5401 // To avoid double-rounding effects during that operation, we have
5402 // to prepare the input operand. Bits that might be truncated when
5403 // converting to double-precision are replaced by a bit that won't
5404 // be lost at this stage, but is below the single-precision rounding
5407 // However, if -enable-unsafe-fp-math is in effect, accept double
5408 // rounding to avoid the extra overhead.
5409 if (Op.getValueType() == MVT::f32 &&
5410 !Subtarget.hasFPCVT() &&
5411 !DAG.getTarget().Options.UnsafeFPMath) {
5413 // Twiddle input to make sure the low 11 bits are zero. (If this
5414 // is the case, we are guaranteed the value will fit into the 53 bit
5415 // mantissa of an IEEE double-precision value without rounding.)
5416 // If any of those low 11 bits were not zero originally, make sure
5417 // bit 12 (value 2048) is set instead, so that the final rounding
5418 // to single-precision gets the correct result.
5419 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5420 SINT, DAG.getConstant(2047, MVT::i64));
5421 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5422 Round, DAG.getConstant(2047, MVT::i64));
5423 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5424 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5425 Round, DAG.getConstant(-2048, MVT::i64));
5427 // However, we cannot use that value unconditionally: if the magnitude
5428 // of the input value is small, the bit-twiddling we did above might
5429 // end up visibly changing the output. Fortunately, in that case, we
5430 // don't need to twiddle bits since the original input will convert
5431 // exactly to double-precision floating-point already. Therefore,
5432 // construct a conditional to use the original value if the top 11
5433 // bits are all sign-bit copies, and use the rounded value computed
5435 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5436 SINT, DAG.getConstant(53, MVT::i32));
5437 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5438 Cond, DAG.getConstant(1, MVT::i64));
5439 Cond = DAG.getSetCC(dl, MVT::i32,
5440 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5442 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5445 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5446 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5448 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5449 FP = DAG.getNode(ISD::FP_ROUND, dl,
5450 MVT::f32, FP, DAG.getIntPtrConstant(0));
5454 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5455 "Unhandled INT_TO_FP type in custom expander!");
5456 // Since we only generate this in 64-bit mode, we can take advantage of
5457 // 64-bit registers. In particular, sign extend the input value into the
5458 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5459 // then lfd it and fcfid it.
5460 MachineFunction &MF = DAG.getMachineFunction();
5461 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5462 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5465 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5466 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5467 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5469 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5470 MachinePointerInfo::getFixedStack(FrameIdx),
5473 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5474 "Expected an i32 store");
5475 MachineMemOperand *MMO =
5476 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5477 MachineMemOperand::MOLoad, 4, 4);
5478 SDValue Ops[] = { Store, FIdx };
5479 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5480 PPCISD::LFIWZX : PPCISD::LFIWAX,
5481 dl, DAG.getVTList(MVT::f64, MVT::Other),
5482 Ops, MVT::i32, MMO);
5484 assert(Subtarget.isPPC64() &&
5485 "i32->FP without LFIWAX supported only on PPC64");
5487 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5488 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5490 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5493 // STD the extended value into the stack slot.
5494 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5495 MachinePointerInfo::getFixedStack(FrameIdx),
5498 // Load the value as a double.
5499 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5500 MachinePointerInfo::getFixedStack(FrameIdx),
5501 false, false, false, 0);
5504 // FCFID it and return it.
5505 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5506 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5507 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5511 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5512 SelectionDAG &DAG) const {
5515 The rounding mode is in bits 30:31 of FPSR, and has the following
5522 FLT_ROUNDS, on the other hand, expects the following:
5529 To perform the conversion, we do:
5530 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5533 MachineFunction &MF = DAG.getMachineFunction();
5534 EVT VT = Op.getValueType();
5535 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5537 // Save FP Control Word to register
5539 MVT::f64, // return register
5540 MVT::Glue // unused in this context
5542 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5544 // Save FP register to stack slot
5545 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5546 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5547 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5548 StackSlot, MachinePointerInfo(), false, false,0);
5550 // Load FP Control Word from low 32 bits of stack slot.
5551 SDValue Four = DAG.getConstant(4, PtrVT);
5552 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5553 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5554 false, false, false, 0);
5556 // Transform as necessary
5558 DAG.getNode(ISD::AND, dl, MVT::i32,
5559 CWD, DAG.getConstant(3, MVT::i32));
5561 DAG.getNode(ISD::SRL, dl, MVT::i32,
5562 DAG.getNode(ISD::AND, dl, MVT::i32,
5563 DAG.getNode(ISD::XOR, dl, MVT::i32,
5564 CWD, DAG.getConstant(3, MVT::i32)),
5565 DAG.getConstant(3, MVT::i32)),
5566 DAG.getConstant(1, MVT::i32));
5569 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5571 return DAG.getNode((VT.getSizeInBits() < 16 ?
5572 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5575 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5576 EVT VT = Op.getValueType();
5577 unsigned BitWidth = VT.getSizeInBits();
5579 assert(Op.getNumOperands() == 3 &&
5580 VT == Op.getOperand(1).getValueType() &&
5583 // Expand into a bunch of logical ops. Note that these ops
5584 // depend on the PPC behavior for oversized shift amounts.
5585 SDValue Lo = Op.getOperand(0);
5586 SDValue Hi = Op.getOperand(1);
5587 SDValue Amt = Op.getOperand(2);
5588 EVT AmtVT = Amt.getValueType();
5590 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5591 DAG.getConstant(BitWidth, AmtVT), Amt);
5592 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5593 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5594 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5595 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5596 DAG.getConstant(-BitWidth, AmtVT));
5597 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5598 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5599 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5600 SDValue OutOps[] = { OutLo, OutHi };
5601 return DAG.getMergeValues(OutOps, dl);
5604 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5605 EVT VT = Op.getValueType();
5607 unsigned BitWidth = VT.getSizeInBits();
5608 assert(Op.getNumOperands() == 3 &&
5609 VT == Op.getOperand(1).getValueType() &&
5612 // Expand into a bunch of logical ops. Note that these ops
5613 // depend on the PPC behavior for oversized shift amounts.
5614 SDValue Lo = Op.getOperand(0);
5615 SDValue Hi = Op.getOperand(1);
5616 SDValue Amt = Op.getOperand(2);
5617 EVT AmtVT = Amt.getValueType();
5619 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5620 DAG.getConstant(BitWidth, AmtVT), Amt);
5621 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5622 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5623 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5624 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5625 DAG.getConstant(-BitWidth, AmtVT));
5626 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5627 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5628 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5629 SDValue OutOps[] = { OutLo, OutHi };
5630 return DAG.getMergeValues(OutOps, dl);
5633 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5635 EVT VT = Op.getValueType();
5636 unsigned BitWidth = VT.getSizeInBits();
5637 assert(Op.getNumOperands() == 3 &&
5638 VT == Op.getOperand(1).getValueType() &&
5641 // Expand into a bunch of logical ops, followed by a select_cc.
5642 SDValue Lo = Op.getOperand(0);
5643 SDValue Hi = Op.getOperand(1);
5644 SDValue Amt = Op.getOperand(2);
5645 EVT AmtVT = Amt.getValueType();
5647 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5648 DAG.getConstant(BitWidth, AmtVT), Amt);
5649 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5650 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5651 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5652 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5653 DAG.getConstant(-BitWidth, AmtVT));
5654 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5655 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5656 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5657 Tmp4, Tmp6, ISD::SETLE);
5658 SDValue OutOps[] = { OutLo, OutHi };
5659 return DAG.getMergeValues(OutOps, dl);
5662 //===----------------------------------------------------------------------===//
5663 // Vector related lowering.
5666 /// BuildSplatI - Build a canonical splati of Val with an element size of
5667 /// SplatSize. Cast the result to VT.
5668 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5669 SelectionDAG &DAG, SDLoc dl) {
5670 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5672 static const EVT VTys[] = { // canonical VT to use for each size.
5673 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5676 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5678 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5682 EVT CanonicalVT = VTys[SplatSize-1];
5684 // Build a canonical splat for this value.
5685 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5686 SmallVector<SDValue, 8> Ops;
5687 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5688 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5689 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5692 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5693 /// specified intrinsic ID.
5694 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5695 SelectionDAG &DAG, SDLoc dl,
5696 EVT DestVT = MVT::Other) {
5697 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5698 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5699 DAG.getConstant(IID, MVT::i32), Op);
5702 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5703 /// specified intrinsic ID.
5704 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5705 SelectionDAG &DAG, SDLoc dl,
5706 EVT DestVT = MVT::Other) {
5707 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5708 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5709 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5712 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5713 /// specified intrinsic ID.
5714 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5715 SDValue Op2, SelectionDAG &DAG,
5716 SDLoc dl, EVT DestVT = MVT::Other) {
5717 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5718 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5719 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5723 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5724 /// amount. The result has the specified value type.
5725 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5726 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5727 // Force LHS/RHS to be the right type.
5728 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5729 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5732 for (unsigned i = 0; i != 16; ++i)
5734 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5735 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5738 // If this is a case we can't handle, return null and let the default
5739 // expansion code take care of it. If we CAN select this case, and if it
5740 // selects to a single instruction, return Op. Otherwise, if we can codegen
5741 // this case more efficiently than a constant pool load, lower it to the
5742 // sequence of ops that should be used.
5743 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5744 SelectionDAG &DAG) const {
5746 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5747 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5749 // Check if this is a splat of a constant value.
5750 APInt APSplatBits, APSplatUndef;
5751 unsigned SplatBitSize;
5753 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5754 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5757 unsigned SplatBits = APSplatBits.getZExtValue();
5758 unsigned SplatUndef = APSplatUndef.getZExtValue();
5759 unsigned SplatSize = SplatBitSize / 8;
5761 // First, handle single instruction cases.
5764 if (SplatBits == 0) {
5765 // Canonicalize all zero vectors to be v4i32.
5766 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5767 SDValue Z = DAG.getConstant(0, MVT::i32);
5768 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5769 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5774 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5775 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5777 if (SextVal >= -16 && SextVal <= 15)
5778 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5781 // Two instruction sequences.
5783 // If this value is in the range [-32,30] and is even, use:
5784 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5785 // If this value is in the range [17,31] and is odd, use:
5786 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5787 // If this value is in the range [-31,-17] and is odd, use:
5788 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5789 // Note the last two are three-instruction sequences.
5790 if (SextVal >= -32 && SextVal <= 31) {
5791 // To avoid having these optimizations undone by constant folding,
5792 // we convert to a pseudo that will be expanded later into one of
5794 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5795 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5796 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5797 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5798 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5799 if (VT == Op.getValueType())
5802 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5805 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5806 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5808 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5809 // Make -1 and vspltisw -1:
5810 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5812 // Make the VSLW intrinsic, computing 0x8000_0000.
5813 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5816 // xor by OnesV to invert it.
5817 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5818 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5821 // The remaining cases assume either big endian element order or
5822 // a splat-size that equates to the element size of the vector
5823 // to be built. An example that doesn't work for little endian is
5824 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5825 // and a vector element size of 16 bits. The code below will
5826 // produce the vector in big endian element order, which for little
5827 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5829 // For now, just avoid these optimizations in that case.
5830 // FIXME: Develop correct optimizations for LE with mismatched
5831 // splat and element sizes.
5833 if (Subtarget.isLittleEndian() &&
5834 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5837 // Check to see if this is a wide variety of vsplti*, binop self cases.
5838 static const signed char SplatCsts[] = {
5839 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5840 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5843 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5844 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5845 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5846 int i = SplatCsts[idx];
5848 // Figure out what shift amount will be used by altivec if shifted by i in
5850 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5852 // vsplti + shl self.
5853 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5854 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5855 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5856 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5857 Intrinsic::ppc_altivec_vslw
5859 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5860 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5863 // vsplti + srl self.
5864 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5865 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5866 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5867 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5868 Intrinsic::ppc_altivec_vsrw
5870 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5871 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5874 // vsplti + sra self.
5875 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5876 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5877 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5878 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5879 Intrinsic::ppc_altivec_vsraw
5881 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5882 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5885 // vsplti + rol self.
5886 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5887 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5888 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5889 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5890 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5891 Intrinsic::ppc_altivec_vrlw
5893 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5894 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5897 // t = vsplti c, result = vsldoi t, t, 1
5898 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5899 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5900 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5902 // t = vsplti c, result = vsldoi t, t, 2
5903 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5904 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5905 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5907 // t = vsplti c, result = vsldoi t, t, 3
5908 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5909 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5910 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5917 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5918 /// the specified operations to build the shuffle.
5919 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5920 SDValue RHS, SelectionDAG &DAG,
5922 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5923 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5924 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5927 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5939 if (OpNum == OP_COPY) {
5940 if (LHSID == (1*9+2)*9+3) return LHS;
5941 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5945 SDValue OpLHS, OpRHS;
5946 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5947 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5951 default: llvm_unreachable("Unknown i32 permute!");
5953 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5954 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5955 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5956 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5959 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5960 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5961 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5962 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5965 for (unsigned i = 0; i != 16; ++i)
5966 ShufIdxs[i] = (i&3)+0;
5969 for (unsigned i = 0; i != 16; ++i)
5970 ShufIdxs[i] = (i&3)+4;
5973 for (unsigned i = 0; i != 16; ++i)
5974 ShufIdxs[i] = (i&3)+8;
5977 for (unsigned i = 0; i != 16; ++i)
5978 ShufIdxs[i] = (i&3)+12;
5981 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5983 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5985 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5987 EVT VT = OpLHS.getValueType();
5988 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5989 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5990 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5991 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5994 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5995 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5996 /// return the code it can be lowered into. Worst case, it can always be
5997 /// lowered into a vperm.
5998 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5999 SelectionDAG &DAG) const {
6001 SDValue V1 = Op.getOperand(0);
6002 SDValue V2 = Op.getOperand(1);
6003 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6004 EVT VT = Op.getValueType();
6005 bool isLittleEndian = Subtarget.isLittleEndian();
6007 // Cases that are handled by instructions that take permute immediates
6008 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6009 // selected by the instruction selector.
6010 if (V2.getOpcode() == ISD::UNDEF) {
6011 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6012 PPC::isSplatShuffleMask(SVOp, 2) ||
6013 PPC::isSplatShuffleMask(SVOp, 4) ||
6014 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
6015 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
6016 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
6017 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
6018 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
6019 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
6020 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
6021 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
6022 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
6027 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6028 // and produce a fixed permutation. If any of these match, do not lower to
6030 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
6031 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
6032 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
6033 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
6034 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
6035 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
6036 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
6037 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
6038 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
6041 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6042 // perfect shuffle table to emit an optimal matching sequence.
6043 ArrayRef<int> PermMask = SVOp->getMask();
6045 unsigned PFIndexes[4];
6046 bool isFourElementShuffle = true;
6047 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6048 unsigned EltNo = 8; // Start out undef.
6049 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6050 if (PermMask[i*4+j] < 0)
6051 continue; // Undef, ignore it.
6053 unsigned ByteSource = PermMask[i*4+j];
6054 if ((ByteSource & 3) != j) {
6055 isFourElementShuffle = false;
6060 EltNo = ByteSource/4;
6061 } else if (EltNo != ByteSource/4) {
6062 isFourElementShuffle = false;
6066 PFIndexes[i] = EltNo;
6069 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6070 // perfect shuffle vector to determine if it is cost effective to do this as
6071 // discrete instructions, or whether we should use a vperm.
6072 // For now, we skip this for little endian until such time as we have a
6073 // little-endian perfect shuffle table.
6074 if (isFourElementShuffle && !isLittleEndian) {
6075 // Compute the index in the perfect shuffle table.
6076 unsigned PFTableIndex =
6077 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6079 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6080 unsigned Cost = (PFEntry >> 30);
6082 // Determining when to avoid vperm is tricky. Many things affect the cost
6083 // of vperm, particularly how many times the perm mask needs to be computed.
6084 // For example, if the perm mask can be hoisted out of a loop or is already
6085 // used (perhaps because there are multiple permutes with the same shuffle
6086 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6087 // the loop requires an extra register.
6089 // As a compromise, we only emit discrete instructions if the shuffle can be
6090 // generated in 3 or fewer operations. When we have loop information
6091 // available, if this block is within a loop, we should avoid using vperm
6092 // for 3-operation perms and use a constant pool load instead.
6094 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6097 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6098 // vector that will get spilled to the constant pool.
6099 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6101 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6102 // that it is in input element units, not in bytes. Convert now.
6104 // For little endian, the order of the input vectors is reversed, and
6105 // the permutation mask is complemented with respect to 31. This is
6106 // necessary to produce proper semantics with the big-endian-biased vperm
6108 EVT EltVT = V1.getValueType().getVectorElementType();
6109 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6111 SmallVector<SDValue, 16> ResultMask;
6112 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6113 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6115 for (unsigned j = 0; j != BytesPerElement; ++j)
6117 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6120 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6124 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6127 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6130 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6134 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6135 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6136 /// information about the intrinsic.
6137 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6139 unsigned IntrinsicID =
6140 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6143 switch (IntrinsicID) {
6144 default: return false;
6145 // Comparison predicates.
6146 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6147 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6148 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6149 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6150 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6151 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6152 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6153 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6154 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6155 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6156 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6157 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6158 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6160 // Normal Comparisons.
6161 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6162 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6163 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6164 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6165 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6166 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6167 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6168 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6169 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6170 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6171 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6172 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6173 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6178 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6179 /// lower, do it, otherwise return null.
6180 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6181 SelectionDAG &DAG) const {
6182 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6183 // opcode number of the comparison.
6187 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6188 return SDValue(); // Don't custom lower most intrinsics.
6190 // If this is a non-dot comparison, make the VCMP node and we are done.
6192 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6193 Op.getOperand(1), Op.getOperand(2),
6194 DAG.getConstant(CompareOpc, MVT::i32));
6195 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6198 // Create the PPCISD altivec 'dot' comparison node.
6200 Op.getOperand(2), // LHS
6201 Op.getOperand(3), // RHS
6202 DAG.getConstant(CompareOpc, MVT::i32)
6204 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6205 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6207 // Now that we have the comparison, emit a copy from the CR to a GPR.
6208 // This is flagged to the above dot comparison.
6209 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6210 DAG.getRegister(PPC::CR6, MVT::i32),
6211 CompNode.getValue(1));
6213 // Unpack the result based on how the target uses it.
6214 unsigned BitNo; // Bit # of CR6.
6215 bool InvertBit; // Invert result?
6216 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6217 default: // Can't happen, don't crash on invalid number though.
6218 case 0: // Return the value of the EQ bit of CR6.
6219 BitNo = 0; InvertBit = false;
6221 case 1: // Return the inverted value of the EQ bit of CR6.
6222 BitNo = 0; InvertBit = true;
6224 case 2: // Return the value of the LT bit of CR6.
6225 BitNo = 2; InvertBit = false;
6227 case 3: // Return the inverted value of the LT bit of CR6.
6228 BitNo = 2; InvertBit = true;
6232 // Shift the bit into the low position.
6233 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6234 DAG.getConstant(8-(3-BitNo), MVT::i32));
6236 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6237 DAG.getConstant(1, MVT::i32));
6239 // If we are supposed to, toggle the bit.
6241 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6242 DAG.getConstant(1, MVT::i32));
6246 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6247 SelectionDAG &DAG) const {
6249 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6250 // instructions), but for smaller types, we need to first extend up to v2i32
6251 // before doing going farther.
6252 if (Op.getValueType() == MVT::v2i64) {
6253 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6254 if (ExtVT != MVT::v2i32) {
6255 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6256 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6257 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6258 ExtVT.getVectorElementType(), 4)));
6259 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6260 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6261 DAG.getValueType(MVT::v2i32));
6270 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6271 SelectionDAG &DAG) const {
6273 // Create a stack slot that is 16-byte aligned.
6274 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6275 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6276 EVT PtrVT = getPointerTy();
6277 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6279 // Store the input value into Value#0 of the stack slot.
6280 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6281 Op.getOperand(0), FIdx, MachinePointerInfo(),
6284 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6285 false, false, false, 0);
6288 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6290 if (Op.getValueType() == MVT::v4i32) {
6291 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6293 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6294 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6296 SDValue RHSSwap = // = vrlw RHS, 16
6297 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6299 // Shrinkify inputs to v8i16.
6300 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6301 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6302 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6304 // Low parts multiplied together, generating 32-bit results (we ignore the
6306 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6307 LHS, RHS, DAG, dl, MVT::v4i32);
6309 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6310 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6311 // Shift the high parts up 16 bits.
6312 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6314 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6315 } else if (Op.getValueType() == MVT::v8i16) {
6316 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6318 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6320 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6321 LHS, RHS, Zero, DAG, dl);
6322 } else if (Op.getValueType() == MVT::v16i8) {
6323 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6324 bool isLittleEndian = Subtarget.isLittleEndian();
6326 // Multiply the even 8-bit parts, producing 16-bit sums.
6327 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6328 LHS, RHS, DAG, dl, MVT::v8i16);
6329 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6331 // Multiply the odd 8-bit parts, producing 16-bit sums.
6332 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6333 LHS, RHS, DAG, dl, MVT::v8i16);
6334 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6336 // Merge the results together. Because vmuleub and vmuloub are
6337 // instructions with a big-endian bias, we must reverse the
6338 // element numbering and reverse the meaning of "odd" and "even"
6339 // when generating little endian code.
6341 for (unsigned i = 0; i != 8; ++i) {
6342 if (isLittleEndian) {
6344 Ops[i*2+1] = 2*i+16;
6347 Ops[i*2+1] = 2*i+1+16;
6351 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6353 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6355 llvm_unreachable("Unknown mul to lower!");
6359 /// LowerOperation - Provide custom lowering hooks for some operations.
6361 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6362 switch (Op.getOpcode()) {
6363 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6364 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6365 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6366 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6367 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6368 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6369 case ISD::SETCC: return LowerSETCC(Op, DAG);
6370 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6371 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6373 return LowerVASTART(Op, DAG, Subtarget);
6376 return LowerVAARG(Op, DAG, Subtarget);
6379 return LowerVACOPY(Op, DAG, Subtarget);
6381 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6382 case ISD::DYNAMIC_STACKALLOC:
6383 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6385 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6386 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6388 case ISD::LOAD: return LowerLOAD(Op, DAG);
6389 case ISD::STORE: return LowerSTORE(Op, DAG);
6390 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6391 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6392 case ISD::FP_TO_UINT:
6393 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6395 case ISD::UINT_TO_FP:
6396 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6397 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6399 // Lower 64-bit shifts.
6400 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6401 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6402 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6404 // Vector-related lowering.
6405 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6406 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6407 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6408 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6409 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6410 case ISD::MUL: return LowerMUL(Op, DAG);
6412 // For counter-based loop handling.
6413 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6415 // Frame & Return address.
6416 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6417 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6421 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6422 SmallVectorImpl<SDValue>&Results,
6423 SelectionDAG &DAG) const {
6424 const TargetMachine &TM = getTargetMachine();
6426 switch (N->getOpcode()) {
6428 llvm_unreachable("Do not know how to custom type legalize this operation!");
6429 case ISD::INTRINSIC_W_CHAIN: {
6430 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6431 Intrinsic::ppc_is_decremented_ctr_nonzero)
6434 assert(N->getValueType(0) == MVT::i1 &&
6435 "Unexpected result type for CTR decrement intrinsic");
6436 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6437 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6438 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6441 Results.push_back(NewInt);
6442 Results.push_back(NewInt.getValue(1));
6446 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6447 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6450 EVT VT = N->getValueType(0);
6452 if (VT == MVT::i64) {
6453 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6455 Results.push_back(NewNode);
6456 Results.push_back(NewNode.getValue(1));
6460 case ISD::FP_ROUND_INREG: {
6461 assert(N->getValueType(0) == MVT::ppcf128);
6462 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6463 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6464 MVT::f64, N->getOperand(0),
6465 DAG.getIntPtrConstant(0));
6466 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6467 MVT::f64, N->getOperand(0),
6468 DAG.getIntPtrConstant(1));
6470 // Add the two halves of the long double in round-to-zero mode.
6471 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6473 // We know the low half is about to be thrown away, so just use something
6475 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6479 case ISD::FP_TO_SINT:
6480 // LowerFP_TO_INT() can only handle f32 and f64.
6481 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6483 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6489 //===----------------------------------------------------------------------===//
6490 // Other Lowering Code
6491 //===----------------------------------------------------------------------===//
6494 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6495 bool is64bit, unsigned BinOpcode) const {
6496 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6497 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6499 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6500 MachineFunction *F = BB->getParent();
6501 MachineFunction::iterator It = BB;
6504 unsigned dest = MI->getOperand(0).getReg();
6505 unsigned ptrA = MI->getOperand(1).getReg();
6506 unsigned ptrB = MI->getOperand(2).getReg();
6507 unsigned incr = MI->getOperand(3).getReg();
6508 DebugLoc dl = MI->getDebugLoc();
6510 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6511 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6512 F->insert(It, loopMBB);
6513 F->insert(It, exitMBB);
6514 exitMBB->splice(exitMBB->begin(), BB,
6515 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6516 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6518 MachineRegisterInfo &RegInfo = F->getRegInfo();
6519 unsigned TmpReg = (!BinOpcode) ? incr :
6520 RegInfo.createVirtualRegister(
6521 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6522 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6526 // fallthrough --> loopMBB
6527 BB->addSuccessor(loopMBB);
6530 // l[wd]arx dest, ptr
6531 // add r0, dest, incr
6532 // st[wd]cx. r0, ptr
6534 // fallthrough --> exitMBB
6536 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6537 .addReg(ptrA).addReg(ptrB);
6539 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6540 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6541 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6542 BuildMI(BB, dl, TII->get(PPC::BCC))
6543 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6544 BB->addSuccessor(loopMBB);
6545 BB->addSuccessor(exitMBB);
6554 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6555 MachineBasicBlock *BB,
6556 bool is8bit, // operation
6557 unsigned BinOpcode) const {
6558 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6559 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6560 // In 64 bit mode we have to use 64 bits for addresses, even though the
6561 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6562 // registers without caring whether they're 32 or 64, but here we're
6563 // doing actual arithmetic on the addresses.
6564 bool is64bit = Subtarget.isPPC64();
6565 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6567 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6568 MachineFunction *F = BB->getParent();
6569 MachineFunction::iterator It = BB;
6572 unsigned dest = MI->getOperand(0).getReg();
6573 unsigned ptrA = MI->getOperand(1).getReg();
6574 unsigned ptrB = MI->getOperand(2).getReg();
6575 unsigned incr = MI->getOperand(3).getReg();
6576 DebugLoc dl = MI->getDebugLoc();
6578 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6579 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6580 F->insert(It, loopMBB);
6581 F->insert(It, exitMBB);
6582 exitMBB->splice(exitMBB->begin(), BB,
6583 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6584 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6586 MachineRegisterInfo &RegInfo = F->getRegInfo();
6587 const TargetRegisterClass *RC =
6588 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6589 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6590 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6591 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6592 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6593 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6594 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6595 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6596 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6597 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6598 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6599 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6600 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6602 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6606 // fallthrough --> loopMBB
6607 BB->addSuccessor(loopMBB);
6609 // The 4-byte load must be aligned, while a char or short may be
6610 // anywhere in the word. Hence all this nasty bookkeeping code.
6611 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6612 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6613 // xori shift, shift1, 24 [16]
6614 // rlwinm ptr, ptr1, 0, 0, 29
6615 // slw incr2, incr, shift
6616 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6617 // slw mask, mask2, shift
6619 // lwarx tmpDest, ptr
6620 // add tmp, tmpDest, incr2
6621 // andc tmp2, tmpDest, mask
6622 // and tmp3, tmp, mask
6623 // or tmp4, tmp3, tmp2
6626 // fallthrough --> exitMBB
6627 // srw dest, tmpDest, shift
6628 if (ptrA != ZeroReg) {
6629 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6630 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6631 .addReg(ptrA).addReg(ptrB);
6635 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6636 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6637 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6638 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6640 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6641 .addReg(Ptr1Reg).addImm(0).addImm(61);
6643 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6644 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6645 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6646 .addReg(incr).addReg(ShiftReg);
6648 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6650 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6651 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6653 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6654 .addReg(Mask2Reg).addReg(ShiftReg);
6657 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6658 .addReg(ZeroReg).addReg(PtrReg);
6660 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6661 .addReg(Incr2Reg).addReg(TmpDestReg);
6662 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6663 .addReg(TmpDestReg).addReg(MaskReg);
6664 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6665 .addReg(TmpReg).addReg(MaskReg);
6666 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6667 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6668 BuildMI(BB, dl, TII->get(PPC::STWCX))
6669 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6670 BuildMI(BB, dl, TII->get(PPC::BCC))
6671 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6672 BB->addSuccessor(loopMBB);
6673 BB->addSuccessor(exitMBB);
6678 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6683 llvm::MachineBasicBlock*
6684 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6685 MachineBasicBlock *MBB) const {
6686 DebugLoc DL = MI->getDebugLoc();
6687 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6689 MachineFunction *MF = MBB->getParent();
6690 MachineRegisterInfo &MRI = MF->getRegInfo();
6692 const BasicBlock *BB = MBB->getBasicBlock();
6693 MachineFunction::iterator I = MBB;
6697 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6698 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6700 unsigned DstReg = MI->getOperand(0).getReg();
6701 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6702 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6703 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6704 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6706 MVT PVT = getPointerTy();
6707 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6708 "Invalid Pointer Size!");
6709 // For v = setjmp(buf), we generate
6712 // SjLjSetup mainMBB
6718 // buf[LabelOffset] = LR
6722 // v = phi(main, restore)
6725 MachineBasicBlock *thisMBB = MBB;
6726 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6727 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6728 MF->insert(I, mainMBB);
6729 MF->insert(I, sinkMBB);
6731 MachineInstrBuilder MIB;
6733 // Transfer the remainder of BB and its successor edges to sinkMBB.
6734 sinkMBB->splice(sinkMBB->begin(), MBB,
6735 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6736 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6738 // Note that the structure of the jmp_buf used here is not compatible
6739 // with that used by libc, and is not designed to be. Specifically, it
6740 // stores only those 'reserved' registers that LLVM does not otherwise
6741 // understand how to spill. Also, by convention, by the time this
6742 // intrinsic is called, Clang has already stored the frame address in the
6743 // first slot of the buffer and stack address in the third. Following the
6744 // X86 target code, we'll store the jump address in the second slot. We also
6745 // need to save the TOC pointer (R2) to handle jumps between shared
6746 // libraries, and that will be stored in the fourth slot. The thread
6747 // identifier (R13) is not affected.
6750 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6751 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6752 const int64_t BPOffset = 4 * PVT.getStoreSize();
6754 // Prepare IP either in reg.
6755 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6756 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6757 unsigned BufReg = MI->getOperand(1).getReg();
6759 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6760 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6764 MIB.setMemRefs(MMOBegin, MMOEnd);
6767 // Naked functions never have a base pointer, and so we use r1. For all
6768 // other functions, this decision must be delayed until during PEI.
6770 if (MF->getFunction()->getAttributes().hasAttribute(
6771 AttributeSet::FunctionIndex, Attribute::Naked))
6772 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6774 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6776 MIB = BuildMI(*thisMBB, MI, DL,
6777 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6781 MIB.setMemRefs(MMOBegin, MMOEnd);
6784 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6785 const PPCRegisterInfo *TRI =
6786 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6787 MIB.addRegMask(TRI->getNoPreservedMask());
6789 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6791 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6793 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6795 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6796 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6800 MIB = BuildMI(mainMBB, DL,
6801 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6804 if (Subtarget.isPPC64()) {
6805 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6807 .addImm(LabelOffset)
6810 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6812 .addImm(LabelOffset)
6816 MIB.setMemRefs(MMOBegin, MMOEnd);
6818 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6819 mainMBB->addSuccessor(sinkMBB);
6822 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6823 TII->get(PPC::PHI), DstReg)
6824 .addReg(mainDstReg).addMBB(mainMBB)
6825 .addReg(restoreDstReg).addMBB(thisMBB);
6827 MI->eraseFromParent();
6832 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6833 MachineBasicBlock *MBB) const {
6834 DebugLoc DL = MI->getDebugLoc();
6835 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6837 MachineFunction *MF = MBB->getParent();
6838 MachineRegisterInfo &MRI = MF->getRegInfo();
6841 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6842 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6844 MVT PVT = getPointerTy();
6845 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6846 "Invalid Pointer Size!");
6848 const TargetRegisterClass *RC =
6849 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6850 unsigned Tmp = MRI.createVirtualRegister(RC);
6851 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6852 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6853 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6854 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6855 (Subtarget.isSVR4ABI() &&
6856 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6857 PPC::R29 : PPC::R30);
6859 MachineInstrBuilder MIB;
6861 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6862 const int64_t SPOffset = 2 * PVT.getStoreSize();
6863 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6864 const int64_t BPOffset = 4 * PVT.getStoreSize();
6866 unsigned BufReg = MI->getOperand(0).getReg();
6868 // Reload FP (the jumped-to function may not have had a
6869 // frame pointer, and if so, then its r31 will be restored
6871 if (PVT == MVT::i64) {
6872 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6876 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6880 MIB.setMemRefs(MMOBegin, MMOEnd);
6883 if (PVT == MVT::i64) {
6884 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6885 .addImm(LabelOffset)
6888 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6889 .addImm(LabelOffset)
6892 MIB.setMemRefs(MMOBegin, MMOEnd);
6895 if (PVT == MVT::i64) {
6896 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6900 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6904 MIB.setMemRefs(MMOBegin, MMOEnd);
6907 if (PVT == MVT::i64) {
6908 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6912 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6916 MIB.setMemRefs(MMOBegin, MMOEnd);
6919 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6920 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6924 MIB.setMemRefs(MMOBegin, MMOEnd);
6928 BuildMI(*MBB, MI, DL,
6929 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6930 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6932 MI->eraseFromParent();
6937 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6938 MachineBasicBlock *BB) const {
6939 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6940 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6941 return emitEHSjLjSetJmp(MI, BB);
6942 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6943 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6944 return emitEHSjLjLongJmp(MI, BB);
6947 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6949 // To "insert" these instructions we actually have to insert their
6950 // control-flow patterns.
6951 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6952 MachineFunction::iterator It = BB;
6955 MachineFunction *F = BB->getParent();
6957 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6958 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6959 MI->getOpcode() == PPC::SELECT_I4 ||
6960 MI->getOpcode() == PPC::SELECT_I8)) {
6961 SmallVector<MachineOperand, 2> Cond;
6962 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6963 MI->getOpcode() == PPC::SELECT_CC_I8)
6964 Cond.push_back(MI->getOperand(4));
6966 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6967 Cond.push_back(MI->getOperand(1));
6969 DebugLoc dl = MI->getDebugLoc();
6970 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6971 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6972 Cond, MI->getOperand(2).getReg(),
6973 MI->getOperand(3).getReg());
6974 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6975 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6976 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6977 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6978 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6979 MI->getOpcode() == PPC::SELECT_I4 ||
6980 MI->getOpcode() == PPC::SELECT_I8 ||
6981 MI->getOpcode() == PPC::SELECT_F4 ||
6982 MI->getOpcode() == PPC::SELECT_F8 ||
6983 MI->getOpcode() == PPC::SELECT_VRRC) {
6984 // The incoming instruction knows the destination vreg to set, the
6985 // condition code register to branch on, the true/false values to
6986 // select between, and a branch opcode to use.
6991 // cmpTY ccX, r1, r2
6993 // fallthrough --> copy0MBB
6994 MachineBasicBlock *thisMBB = BB;
6995 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6996 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6997 DebugLoc dl = MI->getDebugLoc();
6998 F->insert(It, copy0MBB);
6999 F->insert(It, sinkMBB);
7001 // Transfer the remainder of BB and its successor edges to sinkMBB.
7002 sinkMBB->splice(sinkMBB->begin(), BB,
7003 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7004 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7006 // Next, add the true and fallthrough blocks as its successors.
7007 BB->addSuccessor(copy0MBB);
7008 BB->addSuccessor(sinkMBB);
7010 if (MI->getOpcode() == PPC::SELECT_I4 ||
7011 MI->getOpcode() == PPC::SELECT_I8 ||
7012 MI->getOpcode() == PPC::SELECT_F4 ||
7013 MI->getOpcode() == PPC::SELECT_F8 ||
7014 MI->getOpcode() == PPC::SELECT_VRRC) {
7015 BuildMI(BB, dl, TII->get(PPC::BC))
7016 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7018 unsigned SelectPred = MI->getOperand(4).getImm();
7019 BuildMI(BB, dl, TII->get(PPC::BCC))
7020 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7024 // %FalseValue = ...
7025 // # fallthrough to sinkMBB
7028 // Update machine-CFG edges
7029 BB->addSuccessor(sinkMBB);
7032 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7035 BuildMI(*BB, BB->begin(), dl,
7036 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7037 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7038 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7040 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7041 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7042 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7043 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7044 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7045 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7046 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7047 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7049 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7050 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7051 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7052 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7053 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7054 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7055 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7056 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7058 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7059 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7060 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7061 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7062 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7063 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7064 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7065 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7067 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7068 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7069 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7070 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7071 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7072 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7073 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7074 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7076 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7077 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7078 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7079 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7080 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7081 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7082 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7083 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7085 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7086 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7087 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7088 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7089 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7090 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7091 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7092 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7094 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7095 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7096 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7097 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7098 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7099 BB = EmitAtomicBinary(MI, BB, false, 0);
7100 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7101 BB = EmitAtomicBinary(MI, BB, true, 0);
7103 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7104 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7105 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7107 unsigned dest = MI->getOperand(0).getReg();
7108 unsigned ptrA = MI->getOperand(1).getReg();
7109 unsigned ptrB = MI->getOperand(2).getReg();
7110 unsigned oldval = MI->getOperand(3).getReg();
7111 unsigned newval = MI->getOperand(4).getReg();
7112 DebugLoc dl = MI->getDebugLoc();
7114 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7115 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7116 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7117 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7118 F->insert(It, loop1MBB);
7119 F->insert(It, loop2MBB);
7120 F->insert(It, midMBB);
7121 F->insert(It, exitMBB);
7122 exitMBB->splice(exitMBB->begin(), BB,
7123 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7124 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7128 // fallthrough --> loopMBB
7129 BB->addSuccessor(loop1MBB);
7132 // l[wd]arx dest, ptr
7133 // cmp[wd] dest, oldval
7136 // st[wd]cx. newval, ptr
7140 // st[wd]cx. dest, ptr
7143 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7144 .addReg(ptrA).addReg(ptrB);
7145 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7146 .addReg(oldval).addReg(dest);
7147 BuildMI(BB, dl, TII->get(PPC::BCC))
7148 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7149 BB->addSuccessor(loop2MBB);
7150 BB->addSuccessor(midMBB);
7153 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7154 .addReg(newval).addReg(ptrA).addReg(ptrB);
7155 BuildMI(BB, dl, TII->get(PPC::BCC))
7156 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7157 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7158 BB->addSuccessor(loop1MBB);
7159 BB->addSuccessor(exitMBB);
7162 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7163 .addReg(dest).addReg(ptrA).addReg(ptrB);
7164 BB->addSuccessor(exitMBB);
7169 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7170 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7171 // We must use 64-bit registers for addresses when targeting 64-bit,
7172 // since we're actually doing arithmetic on them. Other registers
7174 bool is64bit = Subtarget.isPPC64();
7175 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7177 unsigned dest = MI->getOperand(0).getReg();
7178 unsigned ptrA = MI->getOperand(1).getReg();
7179 unsigned ptrB = MI->getOperand(2).getReg();
7180 unsigned oldval = MI->getOperand(3).getReg();
7181 unsigned newval = MI->getOperand(4).getReg();
7182 DebugLoc dl = MI->getDebugLoc();
7184 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7185 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7186 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7187 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7188 F->insert(It, loop1MBB);
7189 F->insert(It, loop2MBB);
7190 F->insert(It, midMBB);
7191 F->insert(It, exitMBB);
7192 exitMBB->splice(exitMBB->begin(), BB,
7193 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7194 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7196 MachineRegisterInfo &RegInfo = F->getRegInfo();
7197 const TargetRegisterClass *RC =
7198 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7199 (const TargetRegisterClass *) &PPC::GPRCRegClass;
7200 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7201 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7202 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7203 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7204 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7205 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7206 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7207 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7208 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7209 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7210 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7211 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7212 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7214 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7215 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7218 // fallthrough --> loopMBB
7219 BB->addSuccessor(loop1MBB);
7221 // The 4-byte load must be aligned, while a char or short may be
7222 // anywhere in the word. Hence all this nasty bookkeeping code.
7223 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7224 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7225 // xori shift, shift1, 24 [16]
7226 // rlwinm ptr, ptr1, 0, 0, 29
7227 // slw newval2, newval, shift
7228 // slw oldval2, oldval,shift
7229 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7230 // slw mask, mask2, shift
7231 // and newval3, newval2, mask
7232 // and oldval3, oldval2, mask
7234 // lwarx tmpDest, ptr
7235 // and tmp, tmpDest, mask
7236 // cmpw tmp, oldval3
7239 // andc tmp2, tmpDest, mask
7240 // or tmp4, tmp2, newval3
7245 // stwcx. tmpDest, ptr
7247 // srw dest, tmpDest, shift
7248 if (ptrA != ZeroReg) {
7249 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7250 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7251 .addReg(ptrA).addReg(ptrB);
7255 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7256 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7257 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7258 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7260 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7261 .addReg(Ptr1Reg).addImm(0).addImm(61);
7263 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7264 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7265 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7266 .addReg(newval).addReg(ShiftReg);
7267 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7268 .addReg(oldval).addReg(ShiftReg);
7270 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7272 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7273 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7274 .addReg(Mask3Reg).addImm(65535);
7276 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7277 .addReg(Mask2Reg).addReg(ShiftReg);
7278 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7279 .addReg(NewVal2Reg).addReg(MaskReg);
7280 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7281 .addReg(OldVal2Reg).addReg(MaskReg);
7284 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7285 .addReg(ZeroReg).addReg(PtrReg);
7286 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7287 .addReg(TmpDestReg).addReg(MaskReg);
7288 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7289 .addReg(TmpReg).addReg(OldVal3Reg);
7290 BuildMI(BB, dl, TII->get(PPC::BCC))
7291 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7292 BB->addSuccessor(loop2MBB);
7293 BB->addSuccessor(midMBB);
7296 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7297 .addReg(TmpDestReg).addReg(MaskReg);
7298 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7299 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7300 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7301 .addReg(ZeroReg).addReg(PtrReg);
7302 BuildMI(BB, dl, TII->get(PPC::BCC))
7303 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7304 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7305 BB->addSuccessor(loop1MBB);
7306 BB->addSuccessor(exitMBB);
7309 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7310 .addReg(ZeroReg).addReg(PtrReg);
7311 BB->addSuccessor(exitMBB);
7316 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7318 } else if (MI->getOpcode() == PPC::FADDrtz) {
7319 // This pseudo performs an FADD with rounding mode temporarily forced
7320 // to round-to-zero. We emit this via custom inserter since the FPSCR
7321 // is not modeled at the SelectionDAG level.
7322 unsigned Dest = MI->getOperand(0).getReg();
7323 unsigned Src1 = MI->getOperand(1).getReg();
7324 unsigned Src2 = MI->getOperand(2).getReg();
7325 DebugLoc dl = MI->getDebugLoc();
7327 MachineRegisterInfo &RegInfo = F->getRegInfo();
7328 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7330 // Save FPSCR value.
7331 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7333 // Set rounding mode to round-to-zero.
7334 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7335 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7337 // Perform addition.
7338 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7340 // Restore FPSCR value.
7341 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7342 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7343 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7344 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7345 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7346 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7347 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7348 PPC::ANDIo8 : PPC::ANDIo;
7349 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7350 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7352 MachineRegisterInfo &RegInfo = F->getRegInfo();
7353 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7354 &PPC::GPRCRegClass :
7355 &PPC::G8RCRegClass);
7357 DebugLoc dl = MI->getDebugLoc();
7358 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7359 .addReg(MI->getOperand(1).getReg()).addImm(1);
7360 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7361 MI->getOperand(0).getReg())
7362 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7364 llvm_unreachable("Unexpected instr type to insert");
7367 MI->eraseFromParent(); // The pseudo instruction is gone now.
7371 //===----------------------------------------------------------------------===//
7372 // Target Optimization Hooks
7373 //===----------------------------------------------------------------------===//
7375 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7376 DAGCombinerInfo &DCI) const {
7377 if (DCI.isAfterLegalizeVectorOps())
7380 EVT VT = Op.getValueType();
7382 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7383 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7384 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7385 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7387 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7388 // For the reciprocal, we need to find the zero of the function:
7389 // F(X) = A X - 1 [which has a zero at X = 1/A]
7391 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7392 // does not require additional intermediate precision]
7394 // Convergence is quadratic, so we essentially double the number of digits
7395 // correct after every iteration. The minimum architected relative
7396 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7397 // 23 digits and double has 52 digits.
7398 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7399 if (VT.getScalarType() == MVT::f64)
7402 SelectionDAG &DAG = DCI.DAG;
7406 DAG.getConstantFP(1.0, VT.getScalarType());
7407 if (VT.isVector()) {
7408 assert(VT.getVectorNumElements() == 4 &&
7409 "Unknown vector type");
7410 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7411 FPOne, FPOne, FPOne, FPOne);
7414 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7415 DCI.AddToWorklist(Est.getNode());
7417 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7418 for (int i = 0; i < Iterations; ++i) {
7419 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7420 DCI.AddToWorklist(NewEst.getNode());
7422 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7423 DCI.AddToWorklist(NewEst.getNode());
7425 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7426 DCI.AddToWorklist(NewEst.getNode());
7428 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7429 DCI.AddToWorklist(Est.getNode());
7438 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7439 DAGCombinerInfo &DCI) const {
7440 if (DCI.isAfterLegalizeVectorOps())
7443 EVT VT = Op.getValueType();
7445 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7446 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7447 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7448 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7450 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7451 // For the reciprocal sqrt, we need to find the zero of the function:
7452 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7454 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7455 // As a result, we precompute A/2 prior to the iteration loop.
7457 // Convergence is quadratic, so we essentially double the number of digits
7458 // correct after every iteration. The minimum architected relative
7459 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7460 // 23 digits and double has 52 digits.
7461 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7462 if (VT.getScalarType() == MVT::f64)
7465 SelectionDAG &DAG = DCI.DAG;
7468 SDValue FPThreeHalves =
7469 DAG.getConstantFP(1.5, VT.getScalarType());
7470 if (VT.isVector()) {
7471 assert(VT.getVectorNumElements() == 4 &&
7472 "Unknown vector type");
7473 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7474 FPThreeHalves, FPThreeHalves,
7475 FPThreeHalves, FPThreeHalves);
7478 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7479 DCI.AddToWorklist(Est.getNode());
7481 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7482 // this entire sequence requires only one FP constant.
7483 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7484 DCI.AddToWorklist(HalfArg.getNode());
7486 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7487 DCI.AddToWorklist(HalfArg.getNode());
7489 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7490 for (int i = 0; i < Iterations; ++i) {
7491 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7492 DCI.AddToWorklist(NewEst.getNode());
7494 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7495 DCI.AddToWorklist(NewEst.getNode());
7497 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7498 DCI.AddToWorklist(NewEst.getNode());
7500 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7501 DCI.AddToWorklist(Est.getNode());
7510 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7511 // not enforce equality of the chain operands.
7512 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7513 unsigned Bytes, int Dist,
7514 SelectionDAG &DAG) {
7515 EVT VT = LS->getMemoryVT();
7516 if (VT.getSizeInBits() / 8 != Bytes)
7519 SDValue Loc = LS->getBasePtr();
7520 SDValue BaseLoc = Base->getBasePtr();
7521 if (Loc.getOpcode() == ISD::FrameIndex) {
7522 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7524 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7525 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7526 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7527 int FS = MFI->getObjectSize(FI);
7528 int BFS = MFI->getObjectSize(BFI);
7529 if (FS != BFS || FS != (int)Bytes) return false;
7530 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7534 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7535 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7538 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7539 const GlobalValue *GV1 = nullptr;
7540 const GlobalValue *GV2 = nullptr;
7541 int64_t Offset1 = 0;
7542 int64_t Offset2 = 0;
7543 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7544 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7545 if (isGA1 && isGA2 && GV1 == GV2)
7546 return Offset1 == (Offset2 + Dist*Bytes);
7550 // Return true is there is a nearyby consecutive load to the one provided
7551 // (regardless of alignment). We search up and down the chain, looking though
7552 // token factors and other loads (but nothing else). As a result, a true
7553 // results indicates that it is safe to create a new consecutive load adjacent
7554 // to the load provided.
7555 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7556 SDValue Chain = LD->getChain();
7557 EVT VT = LD->getMemoryVT();
7559 SmallSet<SDNode *, 16> LoadRoots;
7560 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7561 SmallSet<SDNode *, 16> Visited;
7563 // First, search up the chain, branching to follow all token-factor operands.
7564 // If we find a consecutive load, then we're done, otherwise, record all
7565 // nodes just above the top-level loads and token factors.
7566 while (!Queue.empty()) {
7567 SDNode *ChainNext = Queue.pop_back_val();
7568 if (!Visited.insert(ChainNext))
7571 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7572 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7575 if (!Visited.count(ChainLD->getChain().getNode()))
7576 Queue.push_back(ChainLD->getChain().getNode());
7577 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7578 for (const SDUse &O : ChainNext->ops())
7579 if (!Visited.count(O.getNode()))
7580 Queue.push_back(O.getNode());
7582 LoadRoots.insert(ChainNext);
7585 // Second, search down the chain, starting from the top-level nodes recorded
7586 // in the first phase. These top-level nodes are the nodes just above all
7587 // loads and token factors. Starting with their uses, recursively look though
7588 // all loads (just the chain uses) and token factors to find a consecutive
7593 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7594 IE = LoadRoots.end(); I != IE; ++I) {
7595 Queue.push_back(*I);
7597 while (!Queue.empty()) {
7598 SDNode *LoadRoot = Queue.pop_back_val();
7599 if (!Visited.insert(LoadRoot))
7602 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7603 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7606 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7607 UE = LoadRoot->use_end(); UI != UE; ++UI)
7608 if (((isa<LoadSDNode>(*UI) &&
7609 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7610 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7611 Queue.push_back(*UI);
7618 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7619 DAGCombinerInfo &DCI) const {
7620 SelectionDAG &DAG = DCI.DAG;
7623 assert(Subtarget.useCRBits() &&
7624 "Expecting to be tracking CR bits");
7625 // If we're tracking CR bits, we need to be careful that we don't have:
7626 // trunc(binary-ops(zext(x), zext(y)))
7628 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7629 // such that we're unnecessarily moving things into GPRs when it would be
7630 // better to keep them in CR bits.
7632 // Note that trunc here can be an actual i1 trunc, or can be the effective
7633 // truncation that comes from a setcc or select_cc.
7634 if (N->getOpcode() == ISD::TRUNCATE &&
7635 N->getValueType(0) != MVT::i1)
7638 if (N->getOperand(0).getValueType() != MVT::i32 &&
7639 N->getOperand(0).getValueType() != MVT::i64)
7642 if (N->getOpcode() == ISD::SETCC ||
7643 N->getOpcode() == ISD::SELECT_CC) {
7644 // If we're looking at a comparison, then we need to make sure that the
7645 // high bits (all except for the first) don't matter the result.
7647 cast<CondCodeSDNode>(N->getOperand(
7648 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7649 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7651 if (ISD::isSignedIntSetCC(CC)) {
7652 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7653 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7655 } else if (ISD::isUnsignedIntSetCC(CC)) {
7656 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7657 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7658 !DAG.MaskedValueIsZero(N->getOperand(1),
7659 APInt::getHighBitsSet(OpBits, OpBits-1)))
7662 // This is neither a signed nor an unsigned comparison, just make sure
7663 // that the high bits are equal.
7664 APInt Op1Zero, Op1One;
7665 APInt Op2Zero, Op2One;
7666 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7667 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7669 // We don't really care about what is known about the first bit (if
7670 // anything), so clear it in all masks prior to comparing them.
7671 Op1Zero.clearBit(0); Op1One.clearBit(0);
7672 Op2Zero.clearBit(0); Op2One.clearBit(0);
7674 if (Op1Zero != Op2Zero || Op1One != Op2One)
7679 // We now know that the higher-order bits are irrelevant, we just need to
7680 // make sure that all of the intermediate operations are bit operations, and
7681 // all inputs are extensions.
7682 if (N->getOperand(0).getOpcode() != ISD::AND &&
7683 N->getOperand(0).getOpcode() != ISD::OR &&
7684 N->getOperand(0).getOpcode() != ISD::XOR &&
7685 N->getOperand(0).getOpcode() != ISD::SELECT &&
7686 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7687 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7688 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7689 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7690 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7693 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7694 N->getOperand(1).getOpcode() != ISD::AND &&
7695 N->getOperand(1).getOpcode() != ISD::OR &&
7696 N->getOperand(1).getOpcode() != ISD::XOR &&
7697 N->getOperand(1).getOpcode() != ISD::SELECT &&
7698 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7699 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7700 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7701 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7702 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7705 SmallVector<SDValue, 4> Inputs;
7706 SmallVector<SDValue, 8> BinOps, PromOps;
7707 SmallPtrSet<SDNode *, 16> Visited;
7709 for (unsigned i = 0; i < 2; ++i) {
7710 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7711 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7712 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7713 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7714 isa<ConstantSDNode>(N->getOperand(i)))
7715 Inputs.push_back(N->getOperand(i));
7717 BinOps.push_back(N->getOperand(i));
7719 if (N->getOpcode() == ISD::TRUNCATE)
7723 // Visit all inputs, collect all binary operations (and, or, xor and
7724 // select) that are all fed by extensions.
7725 while (!BinOps.empty()) {
7726 SDValue BinOp = BinOps.back();
7729 if (!Visited.insert(BinOp.getNode()))
7732 PromOps.push_back(BinOp);
7734 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7735 // The condition of the select is not promoted.
7736 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7738 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7741 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7742 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7743 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7744 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7745 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7746 Inputs.push_back(BinOp.getOperand(i));
7747 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7748 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7749 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7750 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7751 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7752 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7753 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7754 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7755 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7756 BinOps.push_back(BinOp.getOperand(i));
7758 // We have an input that is not an extension or another binary
7759 // operation; we'll abort this transformation.
7765 // Make sure that this is a self-contained cluster of operations (which
7766 // is not quite the same thing as saying that everything has only one
7768 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7769 if (isa<ConstantSDNode>(Inputs[i]))
7772 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7773 UE = Inputs[i].getNode()->use_end();
7776 if (User != N && !Visited.count(User))
7779 // Make sure that we're not going to promote the non-output-value
7780 // operand(s) or SELECT or SELECT_CC.
7781 // FIXME: Although we could sometimes handle this, and it does occur in
7782 // practice that one of the condition inputs to the select is also one of
7783 // the outputs, we currently can't deal with this.
7784 if (User->getOpcode() == ISD::SELECT) {
7785 if (User->getOperand(0) == Inputs[i])
7787 } else if (User->getOpcode() == ISD::SELECT_CC) {
7788 if (User->getOperand(0) == Inputs[i] ||
7789 User->getOperand(1) == Inputs[i])
7795 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7796 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7797 UE = PromOps[i].getNode()->use_end();
7800 if (User != N && !Visited.count(User))
7803 // Make sure that we're not going to promote the non-output-value
7804 // operand(s) or SELECT or SELECT_CC.
7805 // FIXME: Although we could sometimes handle this, and it does occur in
7806 // practice that one of the condition inputs to the select is also one of
7807 // the outputs, we currently can't deal with this.
7808 if (User->getOpcode() == ISD::SELECT) {
7809 if (User->getOperand(0) == PromOps[i])
7811 } else if (User->getOpcode() == ISD::SELECT_CC) {
7812 if (User->getOperand(0) == PromOps[i] ||
7813 User->getOperand(1) == PromOps[i])
7819 // Replace all inputs with the extension operand.
7820 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7821 // Constants may have users outside the cluster of to-be-promoted nodes,
7822 // and so we need to replace those as we do the promotions.
7823 if (isa<ConstantSDNode>(Inputs[i]))
7826 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7829 // Replace all operations (these are all the same, but have a different
7830 // (i1) return type). DAG.getNode will validate that the types of
7831 // a binary operator match, so go through the list in reverse so that
7832 // we've likely promoted both operands first. Any intermediate truncations or
7833 // extensions disappear.
7834 while (!PromOps.empty()) {
7835 SDValue PromOp = PromOps.back();
7838 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7839 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7840 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7841 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7842 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7843 PromOp.getOperand(0).getValueType() != MVT::i1) {
7844 // The operand is not yet ready (see comment below).
7845 PromOps.insert(PromOps.begin(), PromOp);
7849 SDValue RepValue = PromOp.getOperand(0);
7850 if (isa<ConstantSDNode>(RepValue))
7851 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7853 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7858 switch (PromOp.getOpcode()) {
7859 default: C = 0; break;
7860 case ISD::SELECT: C = 1; break;
7861 case ISD::SELECT_CC: C = 2; break;
7864 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7865 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7866 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7867 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7868 // The to-be-promoted operands of this node have not yet been
7869 // promoted (this should be rare because we're going through the
7870 // list backward, but if one of the operands has several users in
7871 // this cluster of to-be-promoted nodes, it is possible).
7872 PromOps.insert(PromOps.begin(), PromOp);
7876 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7877 PromOp.getNode()->op_end());
7879 // If there are any constant inputs, make sure they're replaced now.
7880 for (unsigned i = 0; i < 2; ++i)
7881 if (isa<ConstantSDNode>(Ops[C+i]))
7882 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7884 DAG.ReplaceAllUsesOfValueWith(PromOp,
7885 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7888 // Now we're left with the initial truncation itself.
7889 if (N->getOpcode() == ISD::TRUNCATE)
7890 return N->getOperand(0);
7892 // Otherwise, this is a comparison. The operands to be compared have just
7893 // changed type (to i1), but everything else is the same.
7894 return SDValue(N, 0);
7897 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7898 DAGCombinerInfo &DCI) const {
7899 SelectionDAG &DAG = DCI.DAG;
7902 // If we're tracking CR bits, we need to be careful that we don't have:
7903 // zext(binary-ops(trunc(x), trunc(y)))
7905 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7906 // such that we're unnecessarily moving things into CR bits that can more
7907 // efficiently stay in GPRs. Note that if we're not certain that the high
7908 // bits are set as required by the final extension, we still may need to do
7909 // some masking to get the proper behavior.
7911 // This same functionality is important on PPC64 when dealing with
7912 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7913 // the return values of functions. Because it is so similar, it is handled
7916 if (N->getValueType(0) != MVT::i32 &&
7917 N->getValueType(0) != MVT::i64)
7920 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7921 Subtarget.useCRBits()) ||
7922 (N->getOperand(0).getValueType() == MVT::i32 &&
7923 Subtarget.isPPC64())))
7926 if (N->getOperand(0).getOpcode() != ISD::AND &&
7927 N->getOperand(0).getOpcode() != ISD::OR &&
7928 N->getOperand(0).getOpcode() != ISD::XOR &&
7929 N->getOperand(0).getOpcode() != ISD::SELECT &&
7930 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7933 SmallVector<SDValue, 4> Inputs;
7934 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7935 SmallPtrSet<SDNode *, 16> Visited;
7937 // Visit all inputs, collect all binary operations (and, or, xor and
7938 // select) that are all fed by truncations.
7939 while (!BinOps.empty()) {
7940 SDValue BinOp = BinOps.back();
7943 if (!Visited.insert(BinOp.getNode()))
7946 PromOps.push_back(BinOp);
7948 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7949 // The condition of the select is not promoted.
7950 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7952 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7955 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7956 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7957 Inputs.push_back(BinOp.getOperand(i));
7958 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7959 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7960 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7961 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7962 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7963 BinOps.push_back(BinOp.getOperand(i));
7965 // We have an input that is not a truncation or another binary
7966 // operation; we'll abort this transformation.
7972 // Make sure that this is a self-contained cluster of operations (which
7973 // is not quite the same thing as saying that everything has only one
7975 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7976 if (isa<ConstantSDNode>(Inputs[i]))
7979 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7980 UE = Inputs[i].getNode()->use_end();
7983 if (User != N && !Visited.count(User))
7986 // Make sure that we're not going to promote the non-output-value
7987 // operand(s) or SELECT or SELECT_CC.
7988 // FIXME: Although we could sometimes handle this, and it does occur in
7989 // practice that one of the condition inputs to the select is also one of
7990 // the outputs, we currently can't deal with this.
7991 if (User->getOpcode() == ISD::SELECT) {
7992 if (User->getOperand(0) == Inputs[i])
7994 } else if (User->getOpcode() == ISD::SELECT_CC) {
7995 if (User->getOperand(0) == Inputs[i] ||
7996 User->getOperand(1) == Inputs[i])
8002 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8003 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8004 UE = PromOps[i].getNode()->use_end();
8007 if (User != N && !Visited.count(User))
8010 // Make sure that we're not going to promote the non-output-value
8011 // operand(s) or SELECT or SELECT_CC.
8012 // FIXME: Although we could sometimes handle this, and it does occur in
8013 // practice that one of the condition inputs to the select is also one of
8014 // the outputs, we currently can't deal with this.
8015 if (User->getOpcode() == ISD::SELECT) {
8016 if (User->getOperand(0) == PromOps[i])
8018 } else if (User->getOpcode() == ISD::SELECT_CC) {
8019 if (User->getOperand(0) == PromOps[i] ||
8020 User->getOperand(1) == PromOps[i])
8026 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8027 bool ReallyNeedsExt = false;
8028 if (N->getOpcode() != ISD::ANY_EXTEND) {
8029 // If all of the inputs are not already sign/zero extended, then
8030 // we'll still need to do that at the end.
8031 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8032 if (isa<ConstantSDNode>(Inputs[i]))
8036 Inputs[i].getOperand(0).getValueSizeInBits();
8037 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8039 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8040 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8041 APInt::getHighBitsSet(OpBits,
8042 OpBits-PromBits))) ||
8043 (N->getOpcode() == ISD::SIGN_EXTEND &&
8044 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8045 (OpBits-(PromBits-1)))) {
8046 ReallyNeedsExt = true;
8052 // Replace all inputs, either with the truncation operand, or a
8053 // truncation or extension to the final output type.
8054 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8055 // Constant inputs need to be replaced with the to-be-promoted nodes that
8056 // use them because they might have users outside of the cluster of
8058 if (isa<ConstantSDNode>(Inputs[i]))
8061 SDValue InSrc = Inputs[i].getOperand(0);
8062 if (Inputs[i].getValueType() == N->getValueType(0))
8063 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8064 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8065 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8066 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8067 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8068 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8069 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8071 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8072 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8075 // Replace all operations (these are all the same, but have a different
8076 // (promoted) return type). DAG.getNode will validate that the types of
8077 // a binary operator match, so go through the list in reverse so that
8078 // we've likely promoted both operands first.
8079 while (!PromOps.empty()) {
8080 SDValue PromOp = PromOps.back();
8084 switch (PromOp.getOpcode()) {
8085 default: C = 0; break;
8086 case ISD::SELECT: C = 1; break;
8087 case ISD::SELECT_CC: C = 2; break;
8090 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8091 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8092 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8093 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8094 // The to-be-promoted operands of this node have not yet been
8095 // promoted (this should be rare because we're going through the
8096 // list backward, but if one of the operands has several users in
8097 // this cluster of to-be-promoted nodes, it is possible).
8098 PromOps.insert(PromOps.begin(), PromOp);
8102 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8103 PromOp.getNode()->op_end());
8105 // If this node has constant inputs, then they'll need to be promoted here.
8106 for (unsigned i = 0; i < 2; ++i) {
8107 if (!isa<ConstantSDNode>(Ops[C+i]))
8109 if (Ops[C+i].getValueType() == N->getValueType(0))
8112 if (N->getOpcode() == ISD::SIGN_EXTEND)
8113 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8114 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8115 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8117 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8120 DAG.ReplaceAllUsesOfValueWith(PromOp,
8121 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8124 // Now we're left with the initial extension itself.
8125 if (!ReallyNeedsExt)
8126 return N->getOperand(0);
8128 // To zero extend, just mask off everything except for the first bit (in the
8130 if (N->getOpcode() == ISD::ZERO_EXTEND)
8131 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8132 DAG.getConstant(APInt::getLowBitsSet(
8133 N->getValueSizeInBits(0), PromBits),
8134 N->getValueType(0)));
8136 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8137 "Invalid extension type");
8138 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8140 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8141 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8142 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8143 N->getOperand(0), ShiftCst), ShiftCst);
8146 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8147 DAGCombinerInfo &DCI) const {
8148 const TargetMachine &TM = getTargetMachine();
8149 SelectionDAG &DAG = DCI.DAG;
8151 switch (N->getOpcode()) {
8154 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8155 if (C->isNullValue()) // 0 << V -> 0.
8156 return N->getOperand(0);
8160 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8161 if (C->isNullValue()) // 0 >>u V -> 0.
8162 return N->getOperand(0);
8166 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8167 if (C->isNullValue() || // 0 >>s V -> 0.
8168 C->isAllOnesValue()) // -1 >>s V -> -1.
8169 return N->getOperand(0);
8172 case ISD::SIGN_EXTEND:
8173 case ISD::ZERO_EXTEND:
8174 case ISD::ANY_EXTEND:
8175 return DAGCombineExtBoolTrunc(N, DCI);
8178 case ISD::SELECT_CC:
8179 return DAGCombineTruncBoolExt(N, DCI);
8181 assert(TM.Options.UnsafeFPMath &&
8182 "Reciprocal estimates require UnsafeFPMath");
8184 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
8186 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
8188 DCI.AddToWorklist(RV.getNode());
8189 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8190 N->getOperand(0), RV);
8192 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
8193 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8195 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8198 DCI.AddToWorklist(RV.getNode());
8199 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
8200 N->getValueType(0), RV);
8201 DCI.AddToWorklist(RV.getNode());
8202 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8203 N->getOperand(0), RV);
8205 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
8206 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8208 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8211 DCI.AddToWorklist(RV.getNode());
8212 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
8213 N->getValueType(0), RV,
8214 N->getOperand(1).getOperand(1));
8215 DCI.AddToWorklist(RV.getNode());
8216 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8217 N->getOperand(0), RV);
8221 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8223 DCI.AddToWorklist(RV.getNode());
8224 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8225 N->getOperand(0), RV);
8231 assert(TM.Options.UnsafeFPMath &&
8232 "Reciprocal estimates require UnsafeFPMath");
8234 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8236 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8238 DCI.AddToWorklist(RV.getNode());
8239 RV = DAGCombineFastRecip(RV, DCI);
8241 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8242 // this case and force the answer to 0.
8244 EVT VT = RV.getValueType();
8246 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8247 if (VT.isVector()) {
8248 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8249 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8253 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8254 N->getOperand(0), Zero, ISD::SETEQ);
8255 DCI.AddToWorklist(ZeroCmp.getNode());
8256 DCI.AddToWorklist(RV.getNode());
8258 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8266 case ISD::SINT_TO_FP:
8267 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8268 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8269 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8270 // We allow the src/dst to be either f32/f64, but the intermediate
8271 // type must be i64.
8272 if (N->getOperand(0).getValueType() == MVT::i64 &&
8273 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8274 SDValue Val = N->getOperand(0).getOperand(0);
8275 if (Val.getValueType() == MVT::f32) {
8276 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8277 DCI.AddToWorklist(Val.getNode());
8280 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8281 DCI.AddToWorklist(Val.getNode());
8282 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8283 DCI.AddToWorklist(Val.getNode());
8284 if (N->getValueType(0) == MVT::f32) {
8285 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8286 DAG.getIntPtrConstant(0));
8287 DCI.AddToWorklist(Val.getNode());
8290 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8291 // If the intermediate type is i32, we can avoid the load/store here
8298 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8299 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8300 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8301 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8302 N->getOperand(1).getValueType() == MVT::i32 &&
8303 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8304 SDValue Val = N->getOperand(1).getOperand(0);
8305 if (Val.getValueType() == MVT::f32) {
8306 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8307 DCI.AddToWorklist(Val.getNode());
8309 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8310 DCI.AddToWorklist(Val.getNode());
8313 N->getOperand(0), Val, N->getOperand(2),
8314 DAG.getValueType(N->getOperand(1).getValueType())
8317 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8318 DAG.getVTList(MVT::Other), Ops,
8319 cast<StoreSDNode>(N)->getMemoryVT(),
8320 cast<StoreSDNode>(N)->getMemOperand());
8321 DCI.AddToWorklist(Val.getNode());
8325 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8326 if (cast<StoreSDNode>(N)->isUnindexed() &&
8327 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8328 N->getOperand(1).getNode()->hasOneUse() &&
8329 (N->getOperand(1).getValueType() == MVT::i32 ||
8330 N->getOperand(1).getValueType() == MVT::i16 ||
8331 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8332 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8333 N->getOperand(1).getValueType() == MVT::i64))) {
8334 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8335 // Do an any-extend to 32-bits if this is a half-word input.
8336 if (BSwapOp.getValueType() == MVT::i16)
8337 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8340 N->getOperand(0), BSwapOp, N->getOperand(2),
8341 DAG.getValueType(N->getOperand(1).getValueType())
8344 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8345 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8346 cast<StoreSDNode>(N)->getMemOperand());
8350 LoadSDNode *LD = cast<LoadSDNode>(N);
8351 EVT VT = LD->getValueType(0);
8352 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8353 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8354 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8355 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8356 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8357 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8358 LD->getAlignment() < ABIAlignment) {
8359 // This is a type-legal unaligned Altivec load.
8360 SDValue Chain = LD->getChain();
8361 SDValue Ptr = LD->getBasePtr();
8362 bool isLittleEndian = Subtarget.isLittleEndian();
8364 // This implements the loading of unaligned vectors as described in
8365 // the venerable Apple Velocity Engine overview. Specifically:
8366 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8367 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8369 // The general idea is to expand a sequence of one or more unaligned
8370 // loads into an alignment-based permutation-control instruction (lvsl
8371 // or lvsr), a series of regular vector loads (which always truncate
8372 // their input address to an aligned address), and a series of
8373 // permutations. The results of these permutations are the requested
8374 // loaded values. The trick is that the last "extra" load is not taken
8375 // from the address you might suspect (sizeof(vector) bytes after the
8376 // last requested load), but rather sizeof(vector) - 1 bytes after the
8377 // last requested vector. The point of this is to avoid a page fault if
8378 // the base address happened to be aligned. This works because if the
8379 // base address is aligned, then adding less than a full vector length
8380 // will cause the last vector in the sequence to be (re)loaded.
8381 // Otherwise, the next vector will be fetched as you might suspect was
8384 // We might be able to reuse the permutation generation from
8385 // a different base address offset from this one by an aligned amount.
8386 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8387 // optimization later.
8388 Intrinsic::ID Intr = (isLittleEndian ?
8389 Intrinsic::ppc_altivec_lvsr :
8390 Intrinsic::ppc_altivec_lvsl);
8391 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8393 // Refine the alignment of the original load (a "new" load created here
8394 // which was identical to the first except for the alignment would be
8395 // merged with the existing node regardless).
8396 MachineFunction &MF = DAG.getMachineFunction();
8397 MachineMemOperand *MMO =
8398 MF.getMachineMemOperand(LD->getPointerInfo(),
8399 LD->getMemOperand()->getFlags(),
8400 LD->getMemoryVT().getStoreSize(),
8402 LD->refineAlignment(MMO);
8403 SDValue BaseLoad = SDValue(LD, 0);
8405 // Note that the value of IncOffset (which is provided to the next
8406 // load's pointer info offset value, and thus used to calculate the
8407 // alignment), and the value of IncValue (which is actually used to
8408 // increment the pointer value) are different! This is because we
8409 // require the next load to appear to be aligned, even though it
8410 // is actually offset from the base pointer by a lesser amount.
8411 int IncOffset = VT.getSizeInBits() / 8;
8412 int IncValue = IncOffset;
8414 // Walk (both up and down) the chain looking for another load at the real
8415 // (aligned) offset (the alignment of the other load does not matter in
8416 // this case). If found, then do not use the offset reduction trick, as
8417 // that will prevent the loads from being later combined (as they would
8418 // otherwise be duplicates).
8419 if (!findConsecutiveLoad(LD, DAG))
8422 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8423 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8426 DAG.getLoad(VT, dl, Chain, Ptr,
8427 LD->getPointerInfo().getWithOffset(IncOffset),
8428 LD->isVolatile(), LD->isNonTemporal(),
8429 LD->isInvariant(), ABIAlignment);
8431 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8432 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8434 if (BaseLoad.getValueType() != MVT::v4i32)
8435 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8437 if (ExtraLoad.getValueType() != MVT::v4i32)
8438 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8440 // Because vperm has a big-endian bias, we must reverse the order
8441 // of the input vectors and complement the permute control vector
8442 // when generating little endian code. We have already handled the
8443 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8444 // and ExtraLoad here.
8447 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8448 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8450 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8451 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8453 if (VT != MVT::v4i32)
8454 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8456 // Now we need to be really careful about how we update the users of the
8457 // original load. We cannot just call DCI.CombineTo (or
8458 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8459 // uses created here (the permutation for example) that need to stay.
8460 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8462 SDUse &Use = UI.getUse();
8464 // Note: BaseLoad is checked here because it might not be N, but a
8466 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8467 User == TF.getNode() || Use.getResNo() > 1) {
8472 SDValue To = Use.getResNo() ? TF : Perm;
8475 SmallVector<SDValue, 8> Ops;
8476 for (const SDUse &O : User->ops()) {
8483 DAG.UpdateNodeOperands(User, Ops);
8486 return SDValue(N, 0);
8490 case ISD::INTRINSIC_WO_CHAIN: {
8491 bool isLittleEndian = Subtarget.isLittleEndian();
8492 Intrinsic::ID Intr = (isLittleEndian ?
8493 Intrinsic::ppc_altivec_lvsr :
8494 Intrinsic::ppc_altivec_lvsl);
8495 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8496 N->getOperand(1)->getOpcode() == ISD::ADD) {
8497 SDValue Add = N->getOperand(1);
8499 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8500 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8501 Add.getValueType().getScalarType().getSizeInBits()))) {
8502 SDNode *BasePtr = Add->getOperand(0).getNode();
8503 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8504 UE = BasePtr->use_end(); UI != UE; ++UI) {
8505 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8506 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8508 // We've found another LVSL/LVSR, and this address is an aligned
8509 // multiple of that one. The results will be the same, so use the
8510 // one we've just found instead.
8512 return SDValue(*UI, 0);
8521 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8522 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8523 N->getOperand(0).hasOneUse() &&
8524 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8525 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8526 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8527 N->getValueType(0) == MVT::i64))) {
8528 SDValue Load = N->getOperand(0);
8529 LoadSDNode *LD = cast<LoadSDNode>(Load);
8530 // Create the byte-swapping load.
8532 LD->getChain(), // Chain
8533 LD->getBasePtr(), // Ptr
8534 DAG.getValueType(N->getValueType(0)) // VT
8537 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8538 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8539 MVT::i64 : MVT::i32, MVT::Other),
8540 Ops, LD->getMemoryVT(), LD->getMemOperand());
8542 // If this is an i16 load, insert the truncate.
8543 SDValue ResVal = BSLoad;
8544 if (N->getValueType(0) == MVT::i16)
8545 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8547 // First, combine the bswap away. This makes the value produced by the
8549 DCI.CombineTo(N, ResVal);
8551 // Next, combine the load away, we give it a bogus result value but a real
8552 // chain result. The result value is dead because the bswap is dead.
8553 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8555 // Return N so it doesn't get rechecked!
8556 return SDValue(N, 0);
8560 case PPCISD::VCMP: {
8561 // If a VCMPo node already exists with exactly the same operands as this
8562 // node, use its result instead of this node (VCMPo computes both a CR6 and
8563 // a normal output).
8565 if (!N->getOperand(0).hasOneUse() &&
8566 !N->getOperand(1).hasOneUse() &&
8567 !N->getOperand(2).hasOneUse()) {
8569 // Scan all of the users of the LHS, looking for VCMPo's that match.
8570 SDNode *VCMPoNode = nullptr;
8572 SDNode *LHSN = N->getOperand(0).getNode();
8573 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8575 if (UI->getOpcode() == PPCISD::VCMPo &&
8576 UI->getOperand(1) == N->getOperand(1) &&
8577 UI->getOperand(2) == N->getOperand(2) &&
8578 UI->getOperand(0) == N->getOperand(0)) {
8583 // If there is no VCMPo node, or if the flag value has a single use, don't
8585 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8588 // Look at the (necessarily single) use of the flag value. If it has a
8589 // chain, this transformation is more complex. Note that multiple things
8590 // could use the value result, which we should ignore.
8591 SDNode *FlagUser = nullptr;
8592 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8593 FlagUser == nullptr; ++UI) {
8594 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8596 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8597 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8604 // If the user is a MFOCRF instruction, we know this is safe.
8605 // Otherwise we give up for right now.
8606 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8607 return SDValue(VCMPoNode, 0);
8612 SDValue Cond = N->getOperand(1);
8613 SDValue Target = N->getOperand(2);
8615 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8616 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8617 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8619 // We now need to make the intrinsic dead (it cannot be instruction
8621 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8622 assert(Cond.getNode()->hasOneUse() &&
8623 "Counter decrement has more than one use");
8625 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8626 N->getOperand(0), Target);
8631 // If this is a branch on an altivec predicate comparison, lower this so
8632 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8633 // lowering is done pre-legalize, because the legalizer lowers the predicate
8634 // compare down to code that is difficult to reassemble.
8635 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8636 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8638 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8639 // value. If so, pass-through the AND to get to the intrinsic.
8640 if (LHS.getOpcode() == ISD::AND &&
8641 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8642 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8643 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8644 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8645 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8647 LHS = LHS.getOperand(0);
8649 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8650 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8651 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8652 isa<ConstantSDNode>(RHS)) {
8653 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8654 "Counter decrement comparison is not EQ or NE");
8656 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8657 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8658 (CC == ISD::SETNE && !Val);
8660 // We now need to make the intrinsic dead (it cannot be instruction
8662 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8663 assert(LHS.getNode()->hasOneUse() &&
8664 "Counter decrement has more than one use");
8666 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8667 N->getOperand(0), N->getOperand(4));
8673 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8674 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8675 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8676 assert(isDot && "Can't compare against a vector result!");
8678 // If this is a comparison against something other than 0/1, then we know
8679 // that the condition is never/always true.
8680 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8681 if (Val != 0 && Val != 1) {
8682 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8683 return N->getOperand(0);
8684 // Always !=, turn it into an unconditional branch.
8685 return DAG.getNode(ISD::BR, dl, MVT::Other,
8686 N->getOperand(0), N->getOperand(4));
8689 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8691 // Create the PPCISD altivec 'dot' comparison node.
8693 LHS.getOperand(2), // LHS of compare
8694 LHS.getOperand(3), // RHS of compare
8695 DAG.getConstant(CompareOpc, MVT::i32)
8697 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8698 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8700 // Unpack the result based on how the target uses it.
8701 PPC::Predicate CompOpc;
8702 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8703 default: // Can't happen, don't crash on invalid number though.
8704 case 0: // Branch on the value of the EQ bit of CR6.
8705 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8707 case 1: // Branch on the inverted value of the EQ bit of CR6.
8708 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8710 case 2: // Branch on the value of the LT bit of CR6.
8711 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8713 case 3: // Branch on the inverted value of the LT bit of CR6.
8714 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8718 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8719 DAG.getConstant(CompOpc, MVT::i32),
8720 DAG.getRegister(PPC::CR6, MVT::i32),
8721 N->getOperand(4), CompNode.getValue(1));
8730 //===----------------------------------------------------------------------===//
8731 // Inline Assembly Support
8732 //===----------------------------------------------------------------------===//
8734 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8737 const SelectionDAG &DAG,
8738 unsigned Depth) const {
8739 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8740 switch (Op.getOpcode()) {
8742 case PPCISD::LBRX: {
8743 // lhbrx is known to have the top bits cleared out.
8744 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8745 KnownZero = 0xFFFF0000;
8748 case ISD::INTRINSIC_WO_CHAIN: {
8749 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8751 case Intrinsic::ppc_altivec_vcmpbfp_p:
8752 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8753 case Intrinsic::ppc_altivec_vcmpequb_p:
8754 case Intrinsic::ppc_altivec_vcmpequh_p:
8755 case Intrinsic::ppc_altivec_vcmpequw_p:
8756 case Intrinsic::ppc_altivec_vcmpgefp_p:
8757 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8758 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8759 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8760 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8761 case Intrinsic::ppc_altivec_vcmpgtub_p:
8762 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8763 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8764 KnownZero = ~1U; // All bits but the low one are known to be zero.
8772 /// getConstraintType - Given a constraint, return the type of
8773 /// constraint it is for this target.
8774 PPCTargetLowering::ConstraintType
8775 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8776 if (Constraint.size() == 1) {
8777 switch (Constraint[0]) {
8784 return C_RegisterClass;
8786 // FIXME: While Z does indicate a memory constraint, it specifically
8787 // indicates an r+r address (used in conjunction with the 'y' modifier
8788 // in the replacement string). Currently, we're forcing the base
8789 // register to be r0 in the asm printer (which is interpreted as zero)
8790 // and forming the complete address in the second register. This is
8794 } else if (Constraint == "wc") { // individual CR bits.
8795 return C_RegisterClass;
8796 } else if (Constraint == "wa" || Constraint == "wd" ||
8797 Constraint == "wf" || Constraint == "ws") {
8798 return C_RegisterClass; // VSX registers.
8800 return TargetLowering::getConstraintType(Constraint);
8803 /// Examine constraint type and operand type and determine a weight value.
8804 /// This object must already have been set up with the operand type
8805 /// and the current alternative constraint selected.
8806 TargetLowering::ConstraintWeight
8807 PPCTargetLowering::getSingleConstraintMatchWeight(
8808 AsmOperandInfo &info, const char *constraint) const {
8809 ConstraintWeight weight = CW_Invalid;
8810 Value *CallOperandVal = info.CallOperandVal;
8811 // If we don't have a value, we can't do a match,
8812 // but allow it at the lowest weight.
8813 if (!CallOperandVal)
8815 Type *type = CallOperandVal->getType();
8817 // Look at the constraint type.
8818 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8819 return CW_Register; // an individual CR bit.
8820 else if ((StringRef(constraint) == "wa" ||
8821 StringRef(constraint) == "wd" ||
8822 StringRef(constraint) == "wf") &&
8825 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8828 switch (*constraint) {
8830 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8833 if (type->isIntegerTy())
8834 weight = CW_Register;
8837 if (type->isFloatTy())
8838 weight = CW_Register;
8841 if (type->isDoubleTy())
8842 weight = CW_Register;
8845 if (type->isVectorTy())
8846 weight = CW_Register;
8849 weight = CW_Register;
8858 std::pair<unsigned, const TargetRegisterClass*>
8859 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8861 if (Constraint.size() == 1) {
8862 // GCC RS6000 Constraint Letters
8863 switch (Constraint[0]) {
8865 if (VT == MVT::i64 && Subtarget.isPPC64())
8866 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8867 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8869 if (VT == MVT::i64 && Subtarget.isPPC64())
8870 return std::make_pair(0U, &PPC::G8RCRegClass);
8871 return std::make_pair(0U, &PPC::GPRCRegClass);
8873 if (VT == MVT::f32 || VT == MVT::i32)
8874 return std::make_pair(0U, &PPC::F4RCRegClass);
8875 if (VT == MVT::f64 || VT == MVT::i64)
8876 return std::make_pair(0U, &PPC::F8RCRegClass);
8879 return std::make_pair(0U, &PPC::VRRCRegClass);
8881 return std::make_pair(0U, &PPC::CRRCRegClass);
8883 } else if (Constraint == "wc") { // an individual CR bit.
8884 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8885 } else if (Constraint == "wa" || Constraint == "wd" ||
8886 Constraint == "wf") {
8887 return std::make_pair(0U, &PPC::VSRCRegClass);
8888 } else if (Constraint == "ws") {
8889 return std::make_pair(0U, &PPC::VSFRCRegClass);
8892 std::pair<unsigned, const TargetRegisterClass*> R =
8893 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8895 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8896 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8897 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8899 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8900 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8901 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8902 PPC::GPRCRegClass.contains(R.first)) {
8903 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8904 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8905 PPC::sub_32, &PPC::G8RCRegClass),
8906 &PPC::G8RCRegClass);
8913 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8914 /// vector. If it is invalid, don't add anything to Ops.
8915 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8916 std::string &Constraint,
8917 std::vector<SDValue>&Ops,
8918 SelectionDAG &DAG) const {
8921 // Only support length 1 constraints.
8922 if (Constraint.length() > 1) return;
8924 char Letter = Constraint[0];
8935 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8936 if (!CST) return; // Must be an immediate to match.
8937 unsigned Value = CST->getZExtValue();
8939 default: llvm_unreachable("Unknown constraint letter!");
8940 case 'I': // "I" is a signed 16-bit constant.
8941 if ((short)Value == (int)Value)
8942 Result = DAG.getTargetConstant(Value, Op.getValueType());
8944 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8945 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8946 if ((short)Value == 0)
8947 Result = DAG.getTargetConstant(Value, Op.getValueType());
8949 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8950 if ((Value >> 16) == 0)
8951 Result = DAG.getTargetConstant(Value, Op.getValueType());
8953 case 'M': // "M" is a constant that is greater than 31.
8955 Result = DAG.getTargetConstant(Value, Op.getValueType());
8957 case 'N': // "N" is a positive constant that is an exact power of two.
8958 if ((int)Value > 0 && isPowerOf2_32(Value))
8959 Result = DAG.getTargetConstant(Value, Op.getValueType());
8961 case 'O': // "O" is the constant zero.
8963 Result = DAG.getTargetConstant(Value, Op.getValueType());
8965 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8966 if ((short)-Value == (int)-Value)
8967 Result = DAG.getTargetConstant(Value, Op.getValueType());
8974 if (Result.getNode()) {
8975 Ops.push_back(Result);
8979 // Handle standard constraint letters.
8980 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8983 // isLegalAddressingMode - Return true if the addressing mode represented
8984 // by AM is legal for this target, for a load/store of the specified type.
8985 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8987 // FIXME: PPC does not allow r+i addressing modes for vectors!
8989 // PPC allows a sign-extended 16-bit immediate field.
8990 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8993 // No global is ever allowed as a base.
8997 // PPC only support r+r,
8999 case 0: // "r+i" or just "i", depending on HasBaseReg.
9002 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9004 // Otherwise we have r+r or r+i.
9007 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9009 // Allow 2*r as r+r.
9012 // No other scales are supported.
9019 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9020 SelectionDAG &DAG) const {
9021 MachineFunction &MF = DAG.getMachineFunction();
9022 MachineFrameInfo *MFI = MF.getFrameInfo();
9023 MFI->setReturnAddressIsTaken(true);
9025 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9029 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9031 // Make sure the function does not optimize away the store of the RA to
9033 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9034 FuncInfo->setLRStoreRequired();
9035 bool isPPC64 = Subtarget.isPPC64();
9036 bool isDarwinABI = Subtarget.isDarwinABI();
9039 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9042 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9043 isPPC64? MVT::i64 : MVT::i32);
9044 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9045 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9047 MachinePointerInfo(), false, false, false, 0);
9050 // Just load the return address off the stack.
9051 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9052 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9053 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9056 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9057 SelectionDAG &DAG) const {
9059 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9061 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9062 bool isPPC64 = PtrVT == MVT::i64;
9064 MachineFunction &MF = DAG.getMachineFunction();
9065 MachineFrameInfo *MFI = MF.getFrameInfo();
9066 MFI->setFrameAddressIsTaken(true);
9068 // Naked functions never have a frame pointer, and so we use r1. For all
9069 // other functions, this decision must be delayed until during PEI.
9071 if (MF.getFunction()->getAttributes().hasAttribute(
9072 AttributeSet::FunctionIndex, Attribute::Naked))
9073 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9075 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9077 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9080 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9081 FrameAddr, MachinePointerInfo(), false, false,
9086 // FIXME? Maybe this could be a TableGen attribute on some registers and
9087 // this table could be generated automatically from RegInfo.
9088 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9090 bool isPPC64 = Subtarget.isPPC64();
9091 bool isDarwinABI = Subtarget.isDarwinABI();
9093 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9094 (!isPPC64 && VT != MVT::i32))
9095 report_fatal_error("Invalid register global variable type");
9097 bool is64Bit = isPPC64 && VT == MVT::i64;
9098 unsigned Reg = StringSwitch<unsigned>(RegName)
9099 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9100 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9101 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9102 (is64Bit ? PPC::X13 : PPC::R13))
9107 report_fatal_error("Invalid register name global variable");
9111 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9112 // The PowerPC target isn't yet aware of offsets.
9116 /// getOptimalMemOpType - Returns the target specific optimal type for load
9117 /// and store operations as a result of memset, memcpy, and memmove
9118 /// lowering. If DstAlign is zero that means it's safe to destination
9119 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9120 /// means there isn't a need to check it against alignment requirement,
9121 /// probably because the source does not need to be loaded. If 'IsMemset' is
9122 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9123 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9124 /// source is constant so it does not need to be loaded.
9125 /// It returns EVT::Other if the type should be determined using generic
9126 /// target-independent logic.
9127 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9128 unsigned DstAlign, unsigned SrcAlign,
9129 bool IsMemset, bool ZeroMemset,
9131 MachineFunction &MF) const {
9132 if (Subtarget.isPPC64()) {
9139 /// \brief Returns true if it is beneficial to convert a load of a constant
9140 /// to just the constant itself.
9141 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9143 assert(Ty->isIntegerTy());
9145 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9146 if (BitSize == 0 || BitSize > 64)
9151 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9152 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9154 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9155 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9156 return NumBits1 == 64 && NumBits2 == 32;
9159 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9160 if (!VT1.isInteger() || !VT2.isInteger())
9162 unsigned NumBits1 = VT1.getSizeInBits();
9163 unsigned NumBits2 = VT2.getSizeInBits();
9164 return NumBits1 == 64 && NumBits2 == 32;
9167 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9168 return isInt<16>(Imm) || isUInt<16>(Imm);
9171 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9172 return isInt<16>(Imm) || isUInt<16>(Imm);
9175 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
9178 if (DisablePPCUnaligned)
9181 // PowerPC supports unaligned memory access for simple non-vector types.
9182 // Although accessing unaligned addresses is not as efficient as accessing
9183 // aligned addresses, it is generally more efficient than manual expansion,
9184 // and generally only traps for software emulation when crossing page
9190 if (VT.getSimpleVT().isVector()) {
9191 if (Subtarget.hasVSX()) {
9192 if (VT != MVT::v2f64 && VT != MVT::v2i64)
9199 if (VT == MVT::ppcf128)
9208 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9209 VT = VT.getScalarType();
9214 switch (VT.getSimpleVT().SimpleTy) {
9226 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9227 EVT VT , unsigned DefinedValues) const {
9228 if (VT == MVT::v2i64)
9231 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9234 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9235 if (DisableILPPref || Subtarget.enableMachineScheduler())
9236 return TargetLowering::getSchedulingPreference(N);
9241 // Create a fast isel object.
9243 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9244 const TargetLibraryInfo *LibInfo) const {
9245 return PPC::createFastISel(FuncInfo, LibInfo);