1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/ParameterAttributes.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
38 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
39 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
42 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
43 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()),
44 PPCAtomicLabelIndex(0) {
48 // Use _setjmp/_longjmp instead of setjmp/longjmp.
49 setUseUnderscoreSetJmp(true);
50 setUseUnderscoreLongJmp(true);
52 // Set up the register classes.
53 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
54 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
55 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
57 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
58 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
61 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
63 // PowerPC has pre-inc load and store's.
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
67 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
68 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
72 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
73 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
75 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
76 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
77 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
78 // This is used in the ppcf128->int sequence. Note it has different semantics
79 // from FP_ROUND: that rounds to nearest, this rounds to zero.
80 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
82 // PowerPC has no intrinsics for these particular operations
83 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
85 // PowerPC has no SREM/UREM instructions
86 setOperationAction(ISD::SREM, MVT::i32, Expand);
87 setOperationAction(ISD::UREM, MVT::i32, Expand);
88 setOperationAction(ISD::SREM, MVT::i64, Expand);
89 setOperationAction(ISD::UREM, MVT::i64, Expand);
91 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
92 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
93 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
94 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
95 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
96 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
97 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
98 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
99 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
101 // We don't support sin/cos/sqrt/fmod/pow
102 setOperationAction(ISD::FSIN , MVT::f64, Expand);
103 setOperationAction(ISD::FCOS , MVT::f64, Expand);
104 setOperationAction(ISD::FREM , MVT::f64, Expand);
105 setOperationAction(ISD::FPOW , MVT::f64, Expand);
106 setOperationAction(ISD::FSIN , MVT::f32, Expand);
107 setOperationAction(ISD::FCOS , MVT::f32, Expand);
108 setOperationAction(ISD::FREM , MVT::f32, Expand);
109 setOperationAction(ISD::FPOW , MVT::f32, Expand);
111 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
113 // If we're enabling GP optimizations, use hardware square root
114 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
115 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
116 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
119 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
120 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
122 // PowerPC does not have BSWAP, CTPOP or CTTZ
123 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
124 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
125 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
126 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
127 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
128 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
130 // PowerPC does not have ROTR
131 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
133 // PowerPC does not have Select
134 setOperationAction(ISD::SELECT, MVT::i32, Expand);
135 setOperationAction(ISD::SELECT, MVT::i64, Expand);
136 setOperationAction(ISD::SELECT, MVT::f32, Expand);
137 setOperationAction(ISD::SELECT, MVT::f64, Expand);
139 // PowerPC wants to turn select_cc of FP into fsel when possible.
140 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
143 // PowerPC wants to optimize integer setcc a bit
144 setOperationAction(ISD::SETCC, MVT::i32, Custom);
146 // PowerPC does not have BRCOND which requires SetCC
147 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
149 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
151 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
152 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
154 // PowerPC does not have [U|S]INT_TO_FP
155 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
156 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
158 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
159 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
160 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
161 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
163 // We cannot sextinreg(i1). Expand to shifts.
164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
166 // Support label based line numbers.
167 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
168 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
170 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
171 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
172 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
173 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
176 // We want to legalize GlobalAddress and ConstantPool nodes into the
177 // appropriate instructions to materialize the address.
178 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
179 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
180 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
181 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
182 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
183 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
184 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
185 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
187 // RET must be custom lowered, to meet ABI requirements
188 setOperationAction(ISD::RET , MVT::Other, Custom);
190 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
191 setOperationAction(ISD::VASTART , MVT::Other, Custom);
193 // VAARG is custom lowered with ELF 32 ABI
194 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
195 setOperationAction(ISD::VAARG, MVT::Other, Custom);
197 setOperationAction(ISD::VAARG, MVT::Other, Expand);
199 // Use the default implementation.
200 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
201 setOperationAction(ISD::VAEND , MVT::Other, Expand);
202 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
203 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
204 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
207 setOperationAction(ISD::ATOMIC_LOAD_ADD , MVT::i32 , Custom);
208 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i32 , Custom);
209 setOperationAction(ISD::ATOMIC_SWAP , MVT::i32 , Custom);
210 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
211 setOperationAction(ISD::ATOMIC_LOAD_ADD , MVT::i64 , Custom);
212 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i64 , Custom);
213 setOperationAction(ISD::ATOMIC_SWAP , MVT::i64 , Custom);
216 // We want to custom lower some of our intrinsics.
217 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
219 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
220 // They also have instructions for converting between i64 and fp.
221 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
222 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
223 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
224 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
227 // FIXME: disable this lowered code. This generates 64-bit register values,
228 // and we don't model the fact that the top part is clobbered by calls. We
229 // need to flag these together so that the value isn't live across a call.
230 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
232 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
233 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
235 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
236 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
239 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
240 // 64-bit PowerPC implementations can support i64 types directly
241 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
242 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
243 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
244 // 64-bit PowerPC wants to expand i128 shifts itself.
245 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
246 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
247 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
249 // 32-bit PowerPC wants to expand i64 shifts itself.
250 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
251 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
252 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
255 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
256 // First set operation action for all vector types to expand. Then we
257 // will selectively turn on ones that can be effectively codegen'd.
258 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
259 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
260 MVT VT = (MVT::SimpleValueType)i;
262 // add/sub are legal for all supported vector VT's.
263 setOperationAction(ISD::ADD , VT, Legal);
264 setOperationAction(ISD::SUB , VT, Legal);
266 // We promote all shuffles to v16i8.
267 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
268 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
270 // We promote all non-typed operations to v4i32.
271 setOperationAction(ISD::AND , VT, Promote);
272 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
273 setOperationAction(ISD::OR , VT, Promote);
274 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
275 setOperationAction(ISD::XOR , VT, Promote);
276 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
277 setOperationAction(ISD::LOAD , VT, Promote);
278 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
279 setOperationAction(ISD::SELECT, VT, Promote);
280 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
281 setOperationAction(ISD::STORE, VT, Promote);
282 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
284 // No other operations are legal.
285 setOperationAction(ISD::MUL , VT, Expand);
286 setOperationAction(ISD::SDIV, VT, Expand);
287 setOperationAction(ISD::SREM, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::UREM, VT, Expand);
290 setOperationAction(ISD::FDIV, VT, Expand);
291 setOperationAction(ISD::FNEG, VT, Expand);
292 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
293 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
294 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
295 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
296 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
297 setOperationAction(ISD::UDIVREM, VT, Expand);
298 setOperationAction(ISD::SDIVREM, VT, Expand);
299 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
300 setOperationAction(ISD::FPOW, VT, Expand);
301 setOperationAction(ISD::CTPOP, VT, Expand);
302 setOperationAction(ISD::CTLZ, VT, Expand);
303 setOperationAction(ISD::CTTZ, VT, Expand);
306 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
307 // with merges, splats, etc.
308 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
310 setOperationAction(ISD::AND , MVT::v4i32, Legal);
311 setOperationAction(ISD::OR , MVT::v4i32, Legal);
312 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
313 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
314 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
315 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
317 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
318 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
319 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
320 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
322 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
323 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
324 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
325 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
327 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
328 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
330 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
331 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
332 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
333 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
336 setShiftAmountType(MVT::i32);
337 setSetCCResultContents(ZeroOrOneSetCCResult);
339 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
340 setStackPointerRegisterToSaveRestore(PPC::X1);
341 setExceptionPointerRegister(PPC::X3);
342 setExceptionSelectorRegister(PPC::X4);
344 setStackPointerRegisterToSaveRestore(PPC::R1);
345 setExceptionPointerRegister(PPC::R3);
346 setExceptionSelectorRegister(PPC::R4);
349 // We have target-specific dag combine patterns for the following nodes:
350 setTargetDAGCombine(ISD::SINT_TO_FP);
351 setTargetDAGCombine(ISD::STORE);
352 setTargetDAGCombine(ISD::BR_CC);
353 setTargetDAGCombine(ISD::BSWAP);
355 // Darwin long double math library functions have $LDBL128 appended.
356 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
357 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
358 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
359 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
360 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
361 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
364 computeRegisterProperties();
367 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
368 /// function arguments in the caller parameter area.
369 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
370 TargetMachine &TM = getTargetMachine();
371 // Darwin passes everything on 4 byte boundary.
372 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
378 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
381 case PPCISD::FSEL: return "PPCISD::FSEL";
382 case PPCISD::FCFID: return "PPCISD::FCFID";
383 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
384 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
385 case PPCISD::STFIWX: return "PPCISD::STFIWX";
386 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
387 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
388 case PPCISD::VPERM: return "PPCISD::VPERM";
389 case PPCISD::Hi: return "PPCISD::Hi";
390 case PPCISD::Lo: return "PPCISD::Lo";
391 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
392 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
393 case PPCISD::SRL: return "PPCISD::SRL";
394 case PPCISD::SRA: return "PPCISD::SRA";
395 case PPCISD::SHL: return "PPCISD::SHL";
396 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
397 case PPCISD::STD_32: return "PPCISD::STD_32";
398 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
399 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
400 case PPCISD::MTCTR: return "PPCISD::MTCTR";
401 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
402 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
403 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
404 case PPCISD::MFCR: return "PPCISD::MFCR";
405 case PPCISD::VCMP: return "PPCISD::VCMP";
406 case PPCISD::VCMPo: return "PPCISD::VCMPo";
407 case PPCISD::LBRX: return "PPCISD::LBRX";
408 case PPCISD::STBRX: return "PPCISD::STBRX";
409 case PPCISD::LARX: return "PPCISD::LARX";
410 case PPCISD::STCX: return "PPCISD::STCX";
411 case PPCISD::CMP_UNRESERVE: return "PPCISD::CMP_UNRESERVE";
412 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
413 case PPCISD::MFFS: return "PPCISD::MFFS";
414 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
415 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
416 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
417 case PPCISD::MTFSF: return "PPCISD::MTFSF";
418 case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
419 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
424 MVT PPCTargetLowering::getSetCCResultType(const SDOperand &) const {
429 //===----------------------------------------------------------------------===//
430 // Node matching predicates, for use by the tblgen matching code.
431 //===----------------------------------------------------------------------===//
433 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
434 static bool isFloatingPointZero(SDOperand Op) {
435 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
436 return CFP->getValueAPF().isZero();
437 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
438 // Maybe this has already been legalized into the constant pool?
439 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
440 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
441 return CFP->getValueAPF().isZero();
446 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
447 /// true if Op is undef or if it matches the specified value.
448 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
449 return Op.getOpcode() == ISD::UNDEF ||
450 cast<ConstantSDNode>(Op)->getValue() == Val;
453 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
454 /// VPKUHUM instruction.
455 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
457 for (unsigned i = 0; i != 16; ++i)
458 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
461 for (unsigned i = 0; i != 8; ++i)
462 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
463 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
469 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
470 /// VPKUWUM instruction.
471 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
473 for (unsigned i = 0; i != 16; i += 2)
474 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
475 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
478 for (unsigned i = 0; i != 8; i += 2)
479 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
480 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
481 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
482 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
488 /// isVMerge - Common function, used to match vmrg* shuffles.
490 static bool isVMerge(SDNode *N, unsigned UnitSize,
491 unsigned LHSStart, unsigned RHSStart) {
492 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
493 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
494 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
495 "Unsupported merge size!");
497 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
498 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
499 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
500 LHSStart+j+i*UnitSize) ||
501 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
502 RHSStart+j+i*UnitSize))
508 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
509 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
510 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
512 return isVMerge(N, UnitSize, 8, 24);
513 return isVMerge(N, UnitSize, 8, 8);
516 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
517 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
518 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
520 return isVMerge(N, UnitSize, 0, 16);
521 return isVMerge(N, UnitSize, 0, 0);
525 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
526 /// amount, otherwise return -1.
527 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
528 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
529 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
530 // Find the first non-undef value in the shuffle mask.
532 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
535 if (i == 16) return -1; // all undef.
537 // Otherwise, check to see if the rest of the elements are consequtively
538 // numbered from this value.
539 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
540 if (ShiftAmt < i) return -1;
544 // Check the rest of the elements to see if they are consequtive.
545 for (++i; i != 16; ++i)
546 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
549 // Check the rest of the elements to see if they are consequtive.
550 for (++i; i != 16; ++i)
551 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
558 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
559 /// specifies a splat of a single element that is suitable for input to
560 /// VSPLTB/VSPLTH/VSPLTW.
561 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
562 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
563 N->getNumOperands() == 16 &&
564 (EltSize == 1 || EltSize == 2 || EltSize == 4));
566 // This is a splat operation if each element of the permute is the same, and
567 // if the value doesn't reference the second vector.
568 unsigned ElementBase = 0;
569 SDOperand Elt = N->getOperand(0);
570 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
571 ElementBase = EltV->getValue();
573 return false; // FIXME: Handle UNDEF elements too!
575 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
578 // Check that they are consequtive.
579 for (unsigned i = 1; i != EltSize; ++i) {
580 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
581 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
585 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
586 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
587 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
588 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
589 "Invalid VECTOR_SHUFFLE mask!");
590 for (unsigned j = 0; j != EltSize; ++j)
591 if (N->getOperand(i+j) != N->getOperand(j))
598 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
600 bool PPC::isAllNegativeZeroVector(SDNode *N) {
601 assert(N->getOpcode() == ISD::BUILD_VECTOR);
602 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
603 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
604 return CFP->getValueAPF().isNegZero();
608 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
609 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
610 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
611 assert(isSplatShuffleMask(N, EltSize));
612 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
615 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
616 /// by using a vspltis[bhw] instruction of the specified element size, return
617 /// the constant being splatted. The ByteSize field indicates the number of
618 /// bytes of each element [124] -> [bhw].
619 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
620 SDOperand OpVal(0, 0);
622 // If ByteSize of the splat is bigger than the element size of the
623 // build_vector, then we have a case where we are checking for a splat where
624 // multiple elements of the buildvector are folded together into a single
625 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
626 unsigned EltSize = 16/N->getNumOperands();
627 if (EltSize < ByteSize) {
628 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
629 SDOperand UniquedVals[4];
630 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
632 // See if all of the elements in the buildvector agree across.
633 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
634 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
635 // If the element isn't a constant, bail fully out.
636 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
639 if (UniquedVals[i&(Multiple-1)].Val == 0)
640 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
641 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
642 return SDOperand(); // no match.
645 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
646 // either constant or undef values that are identical for each chunk. See
647 // if these chunks can form into a larger vspltis*.
649 // Check to see if all of the leading entries are either 0 or -1. If
650 // neither, then this won't fit into the immediate field.
651 bool LeadingZero = true;
652 bool LeadingOnes = true;
653 for (unsigned i = 0; i != Multiple-1; ++i) {
654 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
656 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
657 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
659 // Finally, check the least significant entry.
661 if (UniquedVals[Multiple-1].Val == 0)
662 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
663 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
665 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
668 if (UniquedVals[Multiple-1].Val == 0)
669 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
670 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
671 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
672 return DAG.getTargetConstant(Val, MVT::i32);
678 // Check to see if this buildvec has a single non-undef value in its elements.
679 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
680 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
682 OpVal = N->getOperand(i);
683 else if (OpVal != N->getOperand(i))
687 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
689 unsigned ValSizeInBytes = 0;
691 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
692 Value = CN->getValue();
693 ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8;
694 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
695 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
696 Value = FloatToBits(CN->getValueAPF().convertToFloat());
700 // If the splat value is larger than the element value, then we can never do
701 // this splat. The only case that we could fit the replicated bits into our
702 // immediate field for would be zero, and we prefer to use vxor for it.
703 if (ValSizeInBytes < ByteSize) return SDOperand();
705 // If the element value is larger than the splat value, cut it in half and
706 // check to see if the two halves are equal. Continue doing this until we
707 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
708 while (ValSizeInBytes > ByteSize) {
709 ValSizeInBytes >>= 1;
711 // If the top half equals the bottom half, we're still ok.
712 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
713 (Value & ((1 << (8*ValSizeInBytes))-1)))
717 // Properly sign extend the value.
718 int ShAmt = (4-ByteSize)*8;
719 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
721 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
722 if (MaskVal == 0) return SDOperand();
724 // Finally, if this value fits in a 5 bit sext field, return it
725 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
726 return DAG.getTargetConstant(MaskVal, MVT::i32);
730 //===----------------------------------------------------------------------===//
731 // Addressing Mode Selection
732 //===----------------------------------------------------------------------===//
734 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
735 /// or 64-bit immediate, and if the value can be accurately represented as a
736 /// sign extension from a 16-bit value. If so, this returns true and the
738 static bool isIntS16Immediate(SDNode *N, short &Imm) {
739 if (N->getOpcode() != ISD::Constant)
742 Imm = (short)cast<ConstantSDNode>(N)->getValue();
743 if (N->getValueType(0) == MVT::i32)
744 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
746 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
748 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
749 return isIntS16Immediate(Op.Val, Imm);
753 /// SelectAddressRegReg - Given the specified addressed, check to see if it
754 /// can be represented as an indexed [r+r] operation. Returns false if it
755 /// can be more efficiently represented with [r+imm].
756 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
760 if (N.getOpcode() == ISD::ADD) {
761 if (isIntS16Immediate(N.getOperand(1), imm))
763 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
766 Base = N.getOperand(0);
767 Index = N.getOperand(1);
769 } else if (N.getOpcode() == ISD::OR) {
770 if (isIntS16Immediate(N.getOperand(1), imm))
771 return false; // r+i can fold it if we can.
773 // If this is an or of disjoint bitfields, we can codegen this as an add
774 // (for better address arithmetic) if the LHS and RHS of the OR are provably
776 APInt LHSKnownZero, LHSKnownOne;
777 APInt RHSKnownZero, RHSKnownOne;
778 DAG.ComputeMaskedBits(N.getOperand(0),
779 APInt::getAllOnesValue(N.getOperand(0)
780 .getValueSizeInBits()),
781 LHSKnownZero, LHSKnownOne);
783 if (LHSKnownZero.getBoolValue()) {
784 DAG.ComputeMaskedBits(N.getOperand(1),
785 APInt::getAllOnesValue(N.getOperand(1)
786 .getValueSizeInBits()),
787 RHSKnownZero, RHSKnownOne);
788 // If all of the bits are known zero on the LHS or RHS, the add won't
790 if (~(LHSKnownZero | RHSKnownZero) == 0) {
791 Base = N.getOperand(0);
792 Index = N.getOperand(1);
801 /// Returns true if the address N can be represented by a base register plus
802 /// a signed 16-bit displacement [r+imm], and if it is not better
803 /// represented as reg+reg.
804 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
805 SDOperand &Base, SelectionDAG &DAG){
806 // If this can be more profitably realized as r+r, fail.
807 if (SelectAddressRegReg(N, Disp, Base, DAG))
810 if (N.getOpcode() == ISD::ADD) {
812 if (isIntS16Immediate(N.getOperand(1), imm)) {
813 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
814 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
815 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
817 Base = N.getOperand(0);
819 return true; // [r+i]
820 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
821 // Match LOAD (ADD (X, Lo(G))).
822 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
823 && "Cannot handle constant offsets yet!");
824 Disp = N.getOperand(1).getOperand(0); // The global address.
825 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
826 Disp.getOpcode() == ISD::TargetConstantPool ||
827 Disp.getOpcode() == ISD::TargetJumpTable);
828 Base = N.getOperand(0);
829 return true; // [&g+r]
831 } else if (N.getOpcode() == ISD::OR) {
833 if (isIntS16Immediate(N.getOperand(1), imm)) {
834 // If this is an or of disjoint bitfields, we can codegen this as an add
835 // (for better address arithmetic) if the LHS and RHS of the OR are
836 // provably disjoint.
837 APInt LHSKnownZero, LHSKnownOne;
838 DAG.ComputeMaskedBits(N.getOperand(0),
839 APInt::getAllOnesValue(N.getOperand(0)
840 .getValueSizeInBits()),
841 LHSKnownZero, LHSKnownOne);
843 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
844 // If all of the bits are known zero on the LHS or RHS, the add won't
846 Base = N.getOperand(0);
847 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
851 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
852 // Loading from a constant address.
854 // If this address fits entirely in a 16-bit sext immediate field, codegen
857 if (isIntS16Immediate(CN, Imm)) {
858 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
859 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
863 // Handle 32-bit sext immediates with LIS + addr mode.
864 if (CN->getValueType(0) == MVT::i32 ||
865 (int64_t)CN->getValue() == (int)CN->getValue()) {
866 int Addr = (int)CN->getValue();
868 // Otherwise, break this down into an LIS + disp.
869 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
871 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
872 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
873 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
878 Disp = DAG.getTargetConstant(0, getPointerTy());
879 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
880 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
883 return true; // [r+0]
886 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
887 /// represented as an indexed [r+r] operation.
888 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
891 // Check to see if we can easily represent this as an [r+r] address. This
892 // will fail if it thinks that the address is more profitably represented as
893 // reg+imm, e.g. where imm = 0.
894 if (SelectAddressRegReg(N, Base, Index, DAG))
897 // If the operand is an addition, always emit this as [r+r], since this is
898 // better (for code size, and execution, as the memop does the add for free)
899 // than emitting an explicit add.
900 if (N.getOpcode() == ISD::ADD) {
901 Base = N.getOperand(0);
902 Index = N.getOperand(1);
906 // Otherwise, do it the hard way, using R0 as the base register.
907 Base = DAG.getRegister(PPC::R0, N.getValueType());
912 /// SelectAddressRegImmShift - Returns true if the address N can be
913 /// represented by a base register plus a signed 14-bit displacement
914 /// [r+imm*4]. Suitable for use by STD and friends.
915 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
918 // If this can be more profitably realized as r+r, fail.
919 if (SelectAddressRegReg(N, Disp, Base, DAG))
922 if (N.getOpcode() == ISD::ADD) {
924 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
925 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
926 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
927 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
929 Base = N.getOperand(0);
931 return true; // [r+i]
932 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
933 // Match LOAD (ADD (X, Lo(G))).
934 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
935 && "Cannot handle constant offsets yet!");
936 Disp = N.getOperand(1).getOperand(0); // The global address.
937 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
938 Disp.getOpcode() == ISD::TargetConstantPool ||
939 Disp.getOpcode() == ISD::TargetJumpTable);
940 Base = N.getOperand(0);
941 return true; // [&g+r]
943 } else if (N.getOpcode() == ISD::OR) {
945 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
946 // If this is an or of disjoint bitfields, we can codegen this as an add
947 // (for better address arithmetic) if the LHS and RHS of the OR are
948 // provably disjoint.
949 APInt LHSKnownZero, LHSKnownOne;
950 DAG.ComputeMaskedBits(N.getOperand(0),
951 APInt::getAllOnesValue(N.getOperand(0)
952 .getValueSizeInBits()),
953 LHSKnownZero, LHSKnownOne);
954 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
955 // If all of the bits are known zero on the LHS or RHS, the add won't
957 Base = N.getOperand(0);
958 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
962 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
963 // Loading from a constant address. Verify low two bits are clear.
964 if ((CN->getValue() & 3) == 0) {
965 // If this address fits entirely in a 14-bit sext immediate field, codegen
968 if (isIntS16Immediate(CN, Imm)) {
969 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
970 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
974 // Fold the low-part of 32-bit absolute addresses into addr mode.
975 if (CN->getValueType(0) == MVT::i32 ||
976 (int64_t)CN->getValue() == (int)CN->getValue()) {
977 int Addr = (int)CN->getValue();
979 // Otherwise, break this down into an LIS + disp.
980 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
982 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
983 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
984 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
990 Disp = DAG.getTargetConstant(0, getPointerTy());
991 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
992 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
995 return true; // [r+0]
999 /// getPreIndexedAddressParts - returns true by value, base pointer and
1000 /// offset pointer and addressing mode by reference if the node's address
1001 /// can be legally represented as pre-indexed load / store address.
1002 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1004 ISD::MemIndexedMode &AM,
1005 SelectionDAG &DAG) {
1006 // Disabled by default for now.
1007 if (!EnablePPCPreinc) return false;
1011 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1012 Ptr = LD->getBasePtr();
1013 VT = LD->getMemoryVT();
1015 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1017 Ptr = ST->getBasePtr();
1018 VT = ST->getMemoryVT();
1022 // PowerPC doesn't have preinc load/store instructions for vectors.
1026 // TODO: Check reg+reg first.
1028 // LDU/STU use reg+imm*4, others use reg+imm.
1029 if (VT != MVT::i64) {
1031 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1035 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1039 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1040 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1041 // sext i32 to i64 when addr mode is r+i.
1042 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1043 LD->getExtensionType() == ISD::SEXTLOAD &&
1044 isa<ConstantSDNode>(Offset))
1052 //===----------------------------------------------------------------------===//
1053 // LowerOperation implementation
1054 //===----------------------------------------------------------------------===//
1056 SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op,
1057 SelectionDAG &DAG) {
1058 MVT PtrVT = Op.getValueType();
1059 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1060 Constant *C = CP->getConstVal();
1061 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1062 SDOperand Zero = DAG.getConstant(0, PtrVT);
1064 const TargetMachine &TM = DAG.getTarget();
1066 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1067 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1069 // If this is a non-darwin platform, we don't support non-static relo models
1071 if (TM.getRelocationModel() == Reloc::Static ||
1072 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1073 // Generate non-pic code that has direct accesses to the constant pool.
1074 // The address of the global is just (hi(&g)+lo(&g)).
1075 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1078 if (TM.getRelocationModel() == Reloc::PIC_) {
1079 // With PIC, the first instruction is actually "GR+hi(&G)".
1080 Hi = DAG.getNode(ISD::ADD, PtrVT,
1081 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1084 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1088 SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1089 MVT PtrVT = Op.getValueType();
1090 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1091 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1092 SDOperand Zero = DAG.getConstant(0, PtrVT);
1094 const TargetMachine &TM = DAG.getTarget();
1096 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1097 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1099 // If this is a non-darwin platform, we don't support non-static relo models
1101 if (TM.getRelocationModel() == Reloc::Static ||
1102 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1103 // Generate non-pic code that has direct accesses to the constant pool.
1104 // The address of the global is just (hi(&g)+lo(&g)).
1105 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1108 if (TM.getRelocationModel() == Reloc::PIC_) {
1109 // With PIC, the first instruction is actually "GR+hi(&G)".
1110 Hi = DAG.getNode(ISD::ADD, PtrVT,
1111 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1114 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1118 SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op,
1119 SelectionDAG &DAG) {
1120 assert(0 && "TLS not implemented for PPC.");
1121 return SDOperand(); // Not reached
1124 SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op,
1125 SelectionDAG &DAG) {
1126 MVT PtrVT = Op.getValueType();
1127 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1128 GlobalValue *GV = GSDN->getGlobal();
1129 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1130 // If it's a debug information descriptor, don't mess with it.
1131 if (DAG.isVerifiedDebugInfoDesc(Op))
1133 SDOperand Zero = DAG.getConstant(0, PtrVT);
1135 const TargetMachine &TM = DAG.getTarget();
1137 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1138 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1140 // If this is a non-darwin platform, we don't support non-static relo models
1142 if (TM.getRelocationModel() == Reloc::Static ||
1143 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1144 // Generate non-pic code that has direct accesses to globals.
1145 // The address of the global is just (hi(&g)+lo(&g)).
1146 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1149 if (TM.getRelocationModel() == Reloc::PIC_) {
1150 // With PIC, the first instruction is actually "GR+hi(&G)".
1151 Hi = DAG.getNode(ISD::ADD, PtrVT,
1152 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1155 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1157 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1160 // If the global is weak or external, we have to go through the lazy
1162 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1165 SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1166 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1168 // If we're comparing for equality to zero, expose the fact that this is
1169 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1170 // fold the new nodes.
1171 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1172 if (C->isNullValue() && CC == ISD::SETEQ) {
1173 MVT VT = Op.getOperand(0).getValueType();
1174 SDOperand Zext = Op.getOperand(0);
1175 if (VT.bitsLT(MVT::i32)) {
1177 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1179 unsigned Log2b = Log2_32(VT.getSizeInBits());
1180 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1181 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1182 DAG.getConstant(Log2b, MVT::i32));
1183 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1185 // Leave comparisons against 0 and -1 alone for now, since they're usually
1186 // optimized. FIXME: revisit this when we can custom lower all setcc
1188 if (C->isAllOnesValue() || C->isNullValue())
1192 // If we have an integer seteq/setne, turn it into a compare against zero
1193 // by xor'ing the rhs with the lhs, which is faster than setting a
1194 // condition register, reading it back out, and masking the correct bit. The
1195 // normal approach here uses sub to do this instead of xor. Using xor exposes
1196 // the result to other bit-twiddling opportunities.
1197 MVT LHSVT = Op.getOperand(0).getValueType();
1198 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1199 MVT VT = Op.getValueType();
1200 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1202 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1207 SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1208 int VarArgsFrameIndex,
1209 int VarArgsStackOffset,
1210 unsigned VarArgsNumGPR,
1211 unsigned VarArgsNumFPR,
1212 const PPCSubtarget &Subtarget) {
1214 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1215 return SDOperand(); // Not reached
1218 SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1219 int VarArgsFrameIndex,
1220 int VarArgsStackOffset,
1221 unsigned VarArgsNumGPR,
1222 unsigned VarArgsNumFPR,
1223 const PPCSubtarget &Subtarget) {
1225 if (Subtarget.isMachoABI()) {
1226 // vastart just stores the address of the VarArgsFrameIndex slot into the
1227 // memory location argument.
1228 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1229 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1230 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1231 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
1234 // For ELF 32 ABI we follow the layout of the va_list struct.
1235 // We suppose the given va_list is already allocated.
1238 // char gpr; /* index into the array of 8 GPRs
1239 // * stored in the register save area
1240 // * gpr=0 corresponds to r3,
1241 // * gpr=1 to r4, etc.
1243 // char fpr; /* index into the array of 8 FPRs
1244 // * stored in the register save area
1245 // * fpr=0 corresponds to f1,
1246 // * fpr=1 to f2, etc.
1248 // char *overflow_arg_area;
1249 // /* location on stack that holds
1250 // * the next overflow argument
1252 // char *reg_save_area;
1253 // /* where r3:r10 and f1:f8 (if saved)
1259 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1260 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1263 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1265 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1266 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1268 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1269 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1271 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1272 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1274 uint64_t FPROffset = 1;
1275 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1277 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1279 // Store first byte : number of int regs
1280 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1281 Op.getOperand(1), SV, 0);
1282 uint64_t nextOffset = FPROffset;
1283 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1286 // Store second byte : number of float regs
1287 SDOperand secondStore =
1288 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1289 nextOffset += StackOffset;
1290 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1292 // Store second word : arguments given on stack
1293 SDOperand thirdStore =
1294 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1295 nextOffset += FrameOffset;
1296 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1298 // Store third word : arguments given in registers
1299 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
1303 #include "PPCGenCallingConv.inc"
1305 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1306 /// depending on which subtarget is selected.
1307 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1308 if (Subtarget.isMachoABI()) {
1309 static const unsigned FPR[] = {
1310 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1311 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1317 static const unsigned FPR[] = {
1318 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1324 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1326 static unsigned CalculateStackSlotSize(SDOperand Arg, SDOperand Flag,
1327 bool isVarArg, unsigned PtrByteSize) {
1328 MVT ArgVT = Arg.getValueType();
1329 ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Flag)->getArgFlags();
1330 unsigned ArgSize =ArgVT.getSizeInBits()/8;
1331 if (Flags.isByVal())
1332 ArgSize = Flags.getByValSize();
1333 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1339 PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
1341 int &VarArgsFrameIndex,
1342 int &VarArgsStackOffset,
1343 unsigned &VarArgsNumGPR,
1344 unsigned &VarArgsNumFPR,
1345 const PPCSubtarget &Subtarget) {
1346 // TODO: add description of PPC stack frame format, or at least some docs.
1348 MachineFunction &MF = DAG.getMachineFunction();
1349 MachineFrameInfo *MFI = MF.getFrameInfo();
1350 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1351 SmallVector<SDOperand, 8> ArgValues;
1352 SDOperand Root = Op.getOperand(0);
1353 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1355 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1356 bool isPPC64 = PtrVT == MVT::i64;
1357 bool isMachoABI = Subtarget.isMachoABI();
1358 bool isELF32_ABI = Subtarget.isELF32_ABI();
1359 // Potential tail calls could cause overwriting of argument stack slots.
1360 unsigned CC = MF.getFunction()->getCallingConv();
1361 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1362 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1364 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1365 // Area that is at least reserved in caller of this function.
1366 unsigned MinReservedArea = ArgOffset;
1368 static const unsigned GPR_32[] = { // 32-bit registers.
1369 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1370 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1372 static const unsigned GPR_64[] = { // 64-bit registers.
1373 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1374 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1377 static const unsigned *FPR = GetFPR(Subtarget);
1379 static const unsigned VR[] = {
1380 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1381 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1384 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1385 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1386 const unsigned Num_VR_Regs = array_lengthof( VR);
1388 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1390 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1392 // In 32-bit non-varargs functions, the stack space for vectors is after the
1393 // stack space for non-vectors. We do not use this space unless we have
1394 // too many vectors to fit in registers, something that only occurs in
1395 // constructed examples:), but we have to walk the arglist to figure
1396 // that out...for the pathological case, compute VecArgOffset as the
1397 // start of the vector parameter area. Computing VecArgOffset is the
1398 // entire point of the following loop.
1399 // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying
1400 // to handle Elf here.
1401 unsigned VecArgOffset = ArgOffset;
1402 if (!isVarArg && !isPPC64) {
1403 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e;
1405 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1406 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1407 ISD::ArgFlagsTy Flags =
1408 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1410 if (Flags.isByVal()) {
1411 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1412 ObjSize = Flags.getByValSize();
1414 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1415 VecArgOffset += ArgSize;
1419 switch(ObjectVT.getSimpleVT()) {
1420 default: assert(0 && "Unhandled argument type!");
1423 VecArgOffset += isPPC64 ? 8 : 4;
1425 case MVT::i64: // PPC64
1433 // Nothing to do, we're only looking at Nonvector args here.
1438 // We've found where the vector parameter area in memory is. Skip the
1439 // first 12 parameters; these don't use that memory.
1440 VecArgOffset = ((VecArgOffset+15)/16)*16;
1441 VecArgOffset += 12*16;
1443 // Add DAG nodes to load the arguments or copy them out of registers. On
1444 // entry to a function on PPC, the arguments start after the linkage area,
1445 // although the first ones are often in registers.
1447 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1448 // represented with two words (long long or double) must be copied to an
1449 // even GPR_idx value or to an even ArgOffset value.
1451 SmallVector<SDOperand, 8> MemOps;
1452 unsigned nAltivecParamsAtEnd = 0;
1453 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1455 bool needsLoad = false;
1456 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1457 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1458 unsigned ArgSize = ObjSize;
1459 ISD::ArgFlagsTy Flags =
1460 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1461 // See if next argument requires stack alignment in ELF
1462 bool Align = Flags.isSplit();
1464 unsigned CurArgOffset = ArgOffset;
1466 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1467 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1468 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1469 if (isVarArg || isPPC64) {
1470 MinReservedArea = ((MinReservedArea+15)/16)*16;
1471 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1472 Op.getOperand(ArgNo+3),
1475 } else nAltivecParamsAtEnd++;
1477 // Calculate min reserved area.
1478 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1479 Op.getOperand(ArgNo+3),
1483 // FIXME alignment for ELF may not be right
1484 // FIXME the codegen can be much improved in some cases.
1485 // We do not have to keep everything in memory.
1486 if (Flags.isByVal()) {
1487 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1488 ObjSize = Flags.getByValSize();
1489 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1490 // Double word align in ELF
1491 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1492 // Objects of size 1 and 2 are right justified, everything else is
1493 // left justified. This means the memory address is adjusted forwards.
1494 if (ObjSize==1 || ObjSize==2) {
1495 CurArgOffset = CurArgOffset + (4 - ObjSize);
1497 // The value of the object is its address.
1498 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1499 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1500 ArgValues.push_back(FIN);
1501 if (ObjSize==1 || ObjSize==2) {
1502 if (GPR_idx != Num_GPR_Regs) {
1503 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1504 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1505 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1506 SDOperand Store = DAG.getTruncStore(Val.getValue(1), Val, FIN,
1507 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1508 MemOps.push_back(Store);
1510 if (isMachoABI) ArgOffset += PtrByteSize;
1512 ArgOffset += PtrByteSize;
1516 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1517 // Store whatever pieces of the object are in registers
1518 // to memory. ArgVal will be address of the beginning of
1520 if (GPR_idx != Num_GPR_Regs) {
1521 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1522 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1523 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1524 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1525 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1526 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1527 MemOps.push_back(Store);
1529 if (isMachoABI) ArgOffset += PtrByteSize;
1531 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1538 switch (ObjectVT.getSimpleVT()) {
1539 default: assert(0 && "Unhandled argument type!");
1542 // Double word align in ELF
1543 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1545 if (GPR_idx != Num_GPR_Regs) {
1546 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1547 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1548 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1552 ArgSize = PtrByteSize;
1554 // Stack align in ELF
1555 if (needsLoad && Align && isELF32_ABI)
1556 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1557 // All int arguments reserve stack space in Macho ABI.
1558 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1562 case MVT::i64: // PPC64
1563 if (GPR_idx != Num_GPR_Regs) {
1564 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1565 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1566 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1568 if (ObjectVT == MVT::i32) {
1569 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1570 // value to MVT::i64 and then truncate to the correct register size.
1572 ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
1573 DAG.getValueType(ObjectVT));
1574 else if (Flags.isZExt())
1575 ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
1576 DAG.getValueType(ObjectVT));
1578 ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
1585 // All int arguments reserve stack space in Macho ABI.
1586 if (isMachoABI || needsLoad) ArgOffset += 8;
1591 // Every 4 bytes of argument space consumes one of the GPRs available for
1592 // argument passing.
1593 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1595 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1598 if (FPR_idx != Num_FPR_Regs) {
1600 if (ObjectVT == MVT::f32)
1601 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1603 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1604 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1605 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1611 // Stack align in ELF
1612 if (needsLoad && Align && isELF32_ABI)
1613 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1614 // All FP arguments reserve stack space in Macho ABI.
1615 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1621 // Note that vector arguments in registers don't reserve stack space,
1622 // except in varargs functions.
1623 if (VR_idx != Num_VR_Regs) {
1624 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1625 RegInfo.addLiveIn(VR[VR_idx], VReg);
1626 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1628 while ((ArgOffset % 16) != 0) {
1629 ArgOffset += PtrByteSize;
1630 if (GPR_idx != Num_GPR_Regs)
1634 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1638 if (!isVarArg && !isPPC64) {
1639 // Vectors go after all the nonvectors.
1640 CurArgOffset = VecArgOffset;
1643 // Vectors are aligned.
1644 ArgOffset = ((ArgOffset+15)/16)*16;
1645 CurArgOffset = ArgOffset;
1653 // We need to load the argument to a virtual register if we determined above
1654 // that we ran out of physical registers of the appropriate type.
1656 int FI = MFI->CreateFixedObject(ObjSize,
1657 CurArgOffset + (ArgSize - ObjSize),
1659 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1660 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1663 ArgValues.push_back(ArgVal);
1666 // Set the size that is at least reserved in caller of this function. Tail
1667 // call optimized function's reserved stack space needs to be aligned so that
1668 // taking the difference between two stack areas will result in an aligned
1670 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1671 // Add the Altivec parameters at the end, if needed.
1672 if (nAltivecParamsAtEnd) {
1673 MinReservedArea = ((MinReservedArea+15)/16)*16;
1674 MinReservedArea += 16*nAltivecParamsAtEnd;
1677 std::max(MinReservedArea,
1678 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1679 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1680 getStackAlignment();
1681 unsigned AlignMask = TargetAlign-1;
1682 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1683 FI->setMinReservedArea(MinReservedArea);
1685 // If the function takes variable number of arguments, make a frame index for
1686 // the start of the first vararg value... for expansion of llvm.va_start.
1691 VarArgsNumGPR = GPR_idx;
1692 VarArgsNumFPR = FPR_idx;
1694 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1696 depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 +
1697 Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 +
1698 PtrVT.getSizeInBits()/8);
1700 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1707 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1709 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1711 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1712 // stored to the VarArgsFrameIndex on the stack.
1714 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1715 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1716 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1717 MemOps.push_back(Store);
1718 // Increment the address by four for the next argument to store
1719 SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1720 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1724 // If this function is vararg, store any remaining integer argument regs
1725 // to their spots on the stack so that they may be loaded by deferencing the
1726 // result of va_next.
1727 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1730 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1732 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1734 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1735 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1736 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1737 MemOps.push_back(Store);
1738 // Increment the address by four for the next argument to store
1739 SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1740 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1743 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1746 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1747 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1748 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1749 MemOps.push_back(Store);
1750 // Increment the address by eight for the next argument to store
1751 SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1753 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1756 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1758 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1760 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1761 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1762 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1763 MemOps.push_back(Store);
1764 // Increment the address by eight for the next argument to store
1765 SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1767 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1772 if (!MemOps.empty())
1773 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1775 ArgValues.push_back(Root);
1777 // Return the new list of results.
1778 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
1782 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
1785 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
1791 unsigned &nAltivecParamsAtEnd) {
1792 // Count how many bytes are to be pushed on the stack, including the linkage
1793 // area, and parameter passing area. We start with 24/48 bytes, which is
1794 // prereserved space for [SP][CR][LR][3 x unused].
1795 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1796 unsigned NumOps = (Call.getNumOperands() - 5) / 2;
1797 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1799 // Add up all the space actually used.
1800 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
1801 // they all go in registers, but we must reserve stack space for them for
1802 // possible use by the caller. In varargs or 64-bit calls, parameters are
1803 // assigned stack space in order, with padding so Altivec parameters are
1805 nAltivecParamsAtEnd = 0;
1806 for (unsigned i = 0; i != NumOps; ++i) {
1807 SDOperand Arg = Call.getOperand(5+2*i);
1808 SDOperand Flag = Call.getOperand(5+2*i+1);
1809 MVT ArgVT = Arg.getValueType();
1810 // Varargs Altivec parameters are padded to a 16 byte boundary.
1811 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
1812 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
1813 if (!isVarArg && !isPPC64) {
1814 // Non-varargs Altivec parameters go after all the non-Altivec
1815 // parameters; handle those later so we know how much padding we need.
1816 nAltivecParamsAtEnd++;
1819 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
1820 NumBytes = ((NumBytes+15)/16)*16;
1822 NumBytes += CalculateStackSlotSize(Arg, Flag, isVarArg, PtrByteSize);
1825 // Allow for Altivec parameters at the end, if needed.
1826 if (nAltivecParamsAtEnd) {
1827 NumBytes = ((NumBytes+15)/16)*16;
1828 NumBytes += 16*nAltivecParamsAtEnd;
1831 // The prolog code of the callee may store up to 8 GPR argument registers to
1832 // the stack, allowing va_start to index over them in memory if its varargs.
1833 // Because we cannot tell if this is needed on the caller side, we have to
1834 // conservatively assume that it is needed. As such, make sure we have at
1835 // least enough stack space for the caller to store the 8 GPRs.
1836 NumBytes = std::max(NumBytes,
1837 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1839 // Tail call needs the stack to be aligned.
1840 if (CC==CallingConv::Fast && PerformTailCallOpt) {
1841 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1842 getStackAlignment();
1843 unsigned AlignMask = TargetAlign-1;
1844 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
1850 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
1851 /// adjusted to accomodate the arguments for the tailcall.
1852 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
1853 unsigned ParamSize) {
1855 if (!IsTailCall) return 0;
1857 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
1858 unsigned CallerMinReservedArea = FI->getMinReservedArea();
1859 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
1860 // Remember only if the new adjustement is bigger.
1861 if (SPDiff < FI->getTailCallSPDelta())
1862 FI->setTailCallSPDelta(SPDiff);
1867 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1868 /// following the call is a return. A function is eligible if caller/callee
1869 /// calling conventions match, currently only fastcc supports tail calls, and
1870 /// the function CALL is immediatly followed by a RET.
1872 PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1874 SelectionDAG& DAG) const {
1875 // Variable argument functions are not supported.
1876 if (!PerformTailCallOpt ||
1877 cast<ConstantSDNode>(Call.getOperand(2))->getValue() != 0) return false;
1879 if (CheckTailCallReturnConstraints(Call, Ret)) {
1880 MachineFunction &MF = DAG.getMachineFunction();
1881 unsigned CallerCC = MF.getFunction()->getCallingConv();
1882 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1883 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1884 // Functions containing by val parameters are not supported.
1885 for (unsigned i = 0; i != ((Call.getNumOperands()-5)/2); i++) {
1886 ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Call.getOperand(5+2*i+1))
1888 if (Flags.isByVal()) return false;
1891 SDOperand Callee = Call.getOperand(4);
1892 // Non PIC/GOT tail calls are supported.
1893 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1896 // At the moment we can only do local tail calls (in same module, hidden
1897 // or protected) if we are generating PIC.
1898 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1899 return G->getGlobal()->hasHiddenVisibility()
1900 || G->getGlobal()->hasProtectedVisibility();
1907 /// isCallCompatibleAddress - Return the immediate to use if the specified
1908 /// 32-bit value is representable in the immediate field of a BxA instruction.
1909 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1910 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1913 int Addr = C->getValue();
1914 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1915 (Addr << 6 >> 6) != Addr)
1916 return 0; // Top 6 bits have to be sext of immediate.
1918 return DAG.getConstant((int)C->getValue() >> 2,
1919 DAG.getTargetLoweringInfo().getPointerTy()).Val;
1924 struct TailCallArgumentInfo {
1926 SDOperand FrameIdxOp;
1929 TailCallArgumentInfo() : FrameIdx(0) {}
1934 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
1936 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
1938 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
1939 SmallVector<SDOperand, 8> &MemOpChains) {
1940 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
1941 SDOperand Arg = TailCallArgs[i].Arg;
1942 SDOperand FIN = TailCallArgs[i].FrameIdxOp;
1943 int FI = TailCallArgs[i].FrameIdx;
1944 // Store relative to framepointer.
1945 MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN,
1946 PseudoSourceValue::getFixedStack(),
1951 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
1952 /// the appropriate stack slot for the tail call optimized function call.
1953 static SDOperand EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
1954 MachineFunction &MF,
1956 SDOperand OldRetAddr,
1962 // Calculate the new stack slot for the return address.
1963 int SlotSize = isPPC64 ? 8 : 4;
1964 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
1966 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
1968 int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
1970 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
1972 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
1973 SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
1974 Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx,
1975 PseudoSourceValue::getFixedStack(), NewRetAddr);
1976 SDOperand NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
1977 Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx,
1978 PseudoSourceValue::getFixedStack(), NewFPIdx);
1983 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
1984 /// the position of the argument.
1986 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
1987 SDOperand Arg, int SPDiff, unsigned ArgOffset,
1988 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
1989 int Offset = ArgOffset + SPDiff;
1990 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
1991 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1992 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
1993 SDOperand FIN = DAG.getFrameIndex(FI, VT);
1994 TailCallArgumentInfo Info;
1996 Info.FrameIdxOp = FIN;
1998 TailCallArguments.push_back(Info);
2001 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2002 /// stack slot. Returns the chain as result and the loaded frame pointers in
2003 /// LROpOut/FPOpout. Used when tail calling.
2004 SDOperand PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2008 SDOperand &FPOpOut) {
2010 // Load the LR and FP stack slot for later adjusting.
2011 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2012 LROpOut = getReturnAddrFrameIndex(DAG);
2013 LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
2014 Chain = SDOperand(LROpOut.Val, 1);
2015 FPOpOut = getFramePointerFrameIndex(DAG);
2016 FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0);
2017 Chain = SDOperand(FPOpOut.Val, 1);
2022 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2023 /// by "Src" to address "Dst" of size "Size". Alignment information is
2024 /// specified by the specific parameter attribute. The copy will be passed as
2025 /// a byval function parameter.
2026 /// Sometimes what we are copying is the end of a larger object, the part that
2027 /// does not fit in registers.
2029 CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
2030 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2032 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
2033 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false,
2037 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2040 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDOperand Chain,
2041 SDOperand Arg, SDOperand PtrOff, int SPDiff,
2042 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2043 bool isVector, SmallVector<SDOperand, 8> &MemOpChains,
2044 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2045 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2050 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2052 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2053 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
2054 DAG.getConstant(ArgOffset, PtrVT));
2056 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
2057 // Calculate and remember argument location.
2058 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2062 SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
2063 const PPCSubtarget &Subtarget,
2064 TargetMachine &TM) {
2065 SDOperand Chain = Op.getOperand(0);
2066 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
2067 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2068 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 &&
2069 CC == CallingConv::Fast && PerformTailCallOpt;
2070 SDOperand Callee = Op.getOperand(4);
2071 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
2073 bool isMachoABI = Subtarget.isMachoABI();
2074 bool isELF32_ABI = Subtarget.isELF32_ABI();
2076 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2077 bool isPPC64 = PtrVT == MVT::i64;
2078 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2080 MachineFunction &MF = DAG.getMachineFunction();
2082 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
2083 // SelectExpr to use to put the arguments in the appropriate registers.
2084 std::vector<SDOperand> args_to_use;
2086 // Mark this function as potentially containing a function that contains a
2087 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2088 // and restoring the callers stack pointer in this functions epilog. This is
2089 // done because by tail calling the called function might overwrite the value
2090 // in this function's (MF) stack pointer stack slot 0(SP).
2091 if (PerformTailCallOpt && CC==CallingConv::Fast)
2092 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2094 unsigned nAltivecParamsAtEnd = 0;
2096 // Count how many bytes are to be pushed on the stack, including the linkage
2097 // area, and parameter passing area. We start with 24/48 bytes, which is
2098 // prereserved space for [SP][CR][LR][3 x unused].
2100 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC,
2101 Op, nAltivecParamsAtEnd);
2103 // Calculate by how many bytes the stack has to be adjusted in case of tail
2104 // call optimization.
2105 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2107 // Adjust the stack pointer for the new arguments...
2108 // These operations are automatically eliminated by the prolog/epilog pass
2109 Chain = DAG.getCALLSEQ_START(Chain,
2110 DAG.getConstant(NumBytes, PtrVT));
2111 SDOperand CallSeqStart = Chain;
2113 // Load the return address and frame pointer so it can be move somewhere else
2115 SDOperand LROp, FPOp;
2116 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp);
2118 // Set up a copy of the stack pointer for use loading and storing any
2119 // arguments that may not fit in the registers available for argument
2123 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2125 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2127 // Figure out which arguments are going to go in registers, and which in
2128 // memory. Also, if this is a vararg function, floating point operations
2129 // must be stored to our stack, and loaded into integer regs as well, if
2130 // any integer regs are available for argument passing.
2131 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
2132 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2134 static const unsigned GPR_32[] = { // 32-bit registers.
2135 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2136 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2138 static const unsigned GPR_64[] = { // 64-bit registers.
2139 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2140 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2142 static const unsigned *FPR = GetFPR(Subtarget);
2144 static const unsigned VR[] = {
2145 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2146 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2148 const unsigned NumGPRs = array_lengthof(GPR_32);
2149 const unsigned NumFPRs = isMachoABI ? 13 : 8;
2150 const unsigned NumVRs = array_lengthof( VR);
2152 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2154 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
2155 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2157 SmallVector<SDOperand, 8> MemOpChains;
2158 for (unsigned i = 0; i != NumOps; ++i) {
2160 SDOperand Arg = Op.getOperand(5+2*i);
2161 ISD::ArgFlagsTy Flags =
2162 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
2163 // See if next argument requires stack alignment in ELF
2164 bool Align = Flags.isSplit();
2166 // PtrOff will be used to store the current argument to the stack if a
2167 // register cannot be found for it.
2170 // Stack align in ELF 32
2171 if (isELF32_ABI && Align)
2172 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
2173 StackPtr.getValueType());
2175 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2177 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
2179 // On PPC64, promote integers to 64-bit values.
2180 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2181 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2182 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2183 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
2186 // FIXME Elf untested, what are alignment rules?
2187 // FIXME memcpy is used way more than necessary. Correctness first.
2188 if (Flags.isByVal()) {
2189 unsigned Size = Flags.getByValSize();
2190 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2191 if (Size==1 || Size==2) {
2192 // Very small objects are passed right-justified.
2193 // Everything else is passed left-justified.
2194 MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2195 if (GPR_idx != NumGPRs) {
2196 SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
2198 MemOpChains.push_back(Load.getValue(1));
2199 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2201 ArgOffset += PtrByteSize;
2203 SDOperand Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2204 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
2205 SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2206 CallSeqStart.Val->getOperand(0),
2208 // This must go outside the CALLSEQ_START..END.
2209 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2210 CallSeqStart.Val->getOperand(1));
2211 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
2212 Chain = CallSeqStart = NewCallSeqStart;
2213 ArgOffset += PtrByteSize;
2217 // Copy entire object into memory. There are cases where gcc-generated
2218 // code assumes it is there, even if it could be put entirely into
2219 // registers. (This is not what the doc says.)
2220 SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2221 CallSeqStart.Val->getOperand(0),
2223 // This must go outside the CALLSEQ_START..END.
2224 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2225 CallSeqStart.Val->getOperand(1));
2226 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
2227 Chain = CallSeqStart = NewCallSeqStart;
2228 // And copy the pieces of it that fit into registers.
2229 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2230 SDOperand Const = DAG.getConstant(j, PtrOff.getValueType());
2231 SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
2232 if (GPR_idx != NumGPRs) {
2233 SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
2234 MemOpChains.push_back(Load.getValue(1));
2235 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2237 ArgOffset += PtrByteSize;
2239 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2246 switch (Arg.getValueType().getSimpleVT()) {
2247 default: assert(0 && "Unexpected ValueType for argument!");
2250 // Double word align in ELF
2251 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2252 if (GPR_idx != NumGPRs) {
2253 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2255 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2256 isPPC64, isTailCall, false, MemOpChains,
2260 if (inMem || isMachoABI) {
2261 // Stack align in ELF
2262 if (isELF32_ABI && Align)
2263 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2265 ArgOffset += PtrByteSize;
2270 if (FPR_idx != NumFPRs) {
2271 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
2274 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
2275 MemOpChains.push_back(Store);
2277 // Float varargs are always shadowed in available integer registers
2278 if (GPR_idx != NumGPRs) {
2279 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
2280 MemOpChains.push_back(Load.getValue(1));
2281 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2284 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
2285 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
2286 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
2287 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
2288 MemOpChains.push_back(Load.getValue(1));
2289 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2293 // If we have any FPRs remaining, we may also have GPRs remaining.
2294 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2297 if (GPR_idx != NumGPRs)
2299 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
2300 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
2305 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2306 isPPC64, isTailCall, false, MemOpChains,
2310 if (inMem || isMachoABI) {
2311 // Stack align in ELF
2312 if (isELF32_ABI && Align)
2313 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2317 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
2325 // These go aligned on the stack, or in the corresponding R registers
2326 // when within range. The Darwin PPC ABI doc claims they also go in
2327 // V registers; in fact gcc does this only for arguments that are
2328 // prototyped, not for those that match the ... We do it for all
2329 // arguments, seems to work.
2330 while (ArgOffset % 16 !=0) {
2331 ArgOffset += PtrByteSize;
2332 if (GPR_idx != NumGPRs)
2335 // We could elide this store in the case where the object fits
2336 // entirely in R registers. Maybe later.
2337 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
2338 DAG.getConstant(ArgOffset, PtrVT));
2339 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
2340 MemOpChains.push_back(Store);
2341 if (VR_idx != NumVRs) {
2342 SDOperand Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0);
2343 MemOpChains.push_back(Load.getValue(1));
2344 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
2347 for (unsigned i=0; i<16; i+=PtrByteSize) {
2348 if (GPR_idx == NumGPRs)
2350 SDOperand Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
2351 DAG.getConstant(i, PtrVT));
2352 SDOperand Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0);
2353 MemOpChains.push_back(Load.getValue(1));
2354 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2359 // Non-varargs Altivec params generally go in registers, but have
2360 // stack space allocated at the end.
2361 if (VR_idx != NumVRs) {
2362 // Doesn't have GPR space allocated.
2363 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
2364 } else if (nAltivecParamsAtEnd==0) {
2365 // We are emitting Altivec params in order.
2366 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2367 isPPC64, isTailCall, true, MemOpChains,
2374 // If all Altivec parameters fit in registers, as they usually do,
2375 // they get stack space following the non-Altivec parameters. We
2376 // don't track this here because nobody below needs it.
2377 // If there are more Altivec parameters than fit in registers emit
2379 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
2381 // Offset is aligned; skip 1st 12 params which go in V registers.
2382 ArgOffset = ((ArgOffset+15)/16)*16;
2384 for (unsigned i = 0; i != NumOps; ++i) {
2385 SDOperand Arg = Op.getOperand(5+2*i);
2386 MVT ArgType = Arg.getValueType();
2387 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
2388 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
2391 // We are emitting Altivec params in order.
2392 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2393 isPPC64, isTailCall, true, MemOpChains,
2401 if (!MemOpChains.empty())
2402 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2403 &MemOpChains[0], MemOpChains.size());
2405 // Build a sequence of copy-to-reg nodes chained together with token chain
2406 // and flag operands which copy the outgoing args into the appropriate regs.
2408 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2409 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
2411 InFlag = Chain.getValue(1);
2414 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
2415 if (isVarArg && isELF32_ABI) {
2416 SDOperand SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
2417 Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag);
2418 InFlag = Chain.getValue(1);
2421 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2422 // might overwrite each other in case of tail call optimization.
2424 SmallVector<SDOperand, 8> MemOpChains2;
2425 // Do not flag preceeding copytoreg stuff together with the following stuff.
2426 InFlag = SDOperand();
2427 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2429 if (!MemOpChains2.empty())
2430 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2431 &MemOpChains2[0], MemOpChains2.size());
2433 // Store the return address to the appropriate stack slot.
2434 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2435 isPPC64, isMachoABI);
2438 // Emit callseq_end just before tailcall node.
2440 SmallVector<SDOperand, 8> CallSeqOps;
2441 SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2442 CallSeqOps.push_back(Chain);
2443 CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes));
2444 CallSeqOps.push_back(DAG.getIntPtrConstant(0));
2446 CallSeqOps.push_back(InFlag);
2447 Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
2449 InFlag = Chain.getValue(1);
2452 std::vector<MVT> NodeTys;
2453 NodeTys.push_back(MVT::Other); // Returns a chain
2454 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2456 SmallVector<SDOperand, 8> Ops;
2457 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
2459 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2460 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2461 // node so that legalize doesn't hack it.
2462 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2463 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2464 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2465 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2466 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2467 // If this is an absolute destination address, use the munged value.
2468 Callee = SDOperand(Dest, 0);
2470 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2471 // to do the call, we can't use PPCISD::CALL.
2472 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
2473 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
2474 InFlag = Chain.getValue(1);
2476 // Copy the callee address into R12/X12 on darwin.
2478 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
2479 Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag);
2480 InFlag = Chain.getValue(1);
2484 NodeTys.push_back(MVT::Other);
2485 NodeTys.push_back(MVT::Flag);
2486 Ops.push_back(Chain);
2487 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
2489 // Add CTR register as callee so a bctr can be emitted later.
2491 Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
2494 // If this is a direct call, pass the chain and the callee.
2496 Ops.push_back(Chain);
2497 Ops.push_back(Callee);
2499 // If this is a tail call add stack pointer delta.
2501 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2503 // Add argument registers to the end of the list so that they are known live
2505 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2506 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2507 RegsToPass[i].second.getValueType()));
2509 // When performing tail call optimization the callee pops its arguments off
2510 // the stack. Account for this here so these bytes can be pushed back on in
2511 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2512 int BytesCalleePops =
2513 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2516 Ops.push_back(InFlag);
2520 assert(InFlag.Val &&
2521 "Flag must be set. Depend on flag being set in LowerRET");
2522 Chain = DAG.getNode(PPCISD::TAILCALL,
2523 Op.Val->getVTList(), &Ops[0], Ops.size());
2524 return SDOperand(Chain.Val, Op.ResNo);
2527 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
2528 InFlag = Chain.getValue(1);
2530 Chain = DAG.getCALLSEQ_END(Chain,
2531 DAG.getConstant(NumBytes, PtrVT),
2532 DAG.getConstant(BytesCalleePops, PtrVT),
2534 if (Op.Val->getValueType(0) != MVT::Other)
2535 InFlag = Chain.getValue(1);
2537 SmallVector<SDOperand, 16> ResultVals;
2538 SmallVector<CCValAssign, 16> RVLocs;
2539 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
2540 CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
2541 CCInfo.AnalyzeCallResult(Op.Val, RetCC_PPC);
2543 // Copy all of the result registers out of their specified physreg.
2544 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2545 CCValAssign &VA = RVLocs[i];
2546 MVT VT = VA.getValVT();
2547 assert(VA.isRegLoc() && "Can only return in registers!");
2548 Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1);
2549 ResultVals.push_back(Chain.getValue(0));
2550 InFlag = Chain.getValue(2);
2553 // If the function returns void, just return the chain.
2557 // Otherwise, merge everything together with a MERGE_VALUES node.
2558 ResultVals.push_back(Chain);
2559 SDOperand Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
2561 return Res.getValue(Op.ResNo);
2564 SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG,
2565 TargetMachine &TM) {
2566 SmallVector<CCValAssign, 16> RVLocs;
2567 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
2568 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
2569 CCState CCInfo(CC, isVarArg, TM, RVLocs);
2570 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
2572 // If this is the first return lowered for this function, add the regs to the
2573 // liveout set for the function.
2574 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2575 for (unsigned i = 0; i != RVLocs.size(); ++i)
2576 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2579 SDOperand Chain = Op.getOperand(0);
2581 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
2582 if (Chain.getOpcode() == PPCISD::TAILCALL) {
2583 SDOperand TailCall = Chain;
2584 SDOperand TargetAddress = TailCall.getOperand(1);
2585 SDOperand StackAdjustment = TailCall.getOperand(2);
2587 assert(((TargetAddress.getOpcode() == ISD::Register &&
2588 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
2589 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
2590 TargetAddress.getOpcode() == ISD::TargetGlobalAddress ||
2591 isa<ConstantSDNode>(TargetAddress)) &&
2592 "Expecting an global address, external symbol, absolute value or register");
2594 assert(StackAdjustment.getOpcode() == ISD::Constant &&
2595 "Expecting a const value");
2597 SmallVector<SDOperand,8> Operands;
2598 Operands.push_back(Chain.getOperand(0));
2599 Operands.push_back(TargetAddress);
2600 Operands.push_back(StackAdjustment);
2601 // Copy registers used by the call. Last operand is a flag so it is not
2603 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
2604 Operands.push_back(Chain.getOperand(i));
2606 return DAG.getNode(PPCISD::TC_RETURN, MVT::Other, &Operands[0],
2612 // Copy the result values into the output registers.
2613 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2614 CCValAssign &VA = RVLocs[i];
2615 assert(VA.isRegLoc() && "Can only return in registers!");
2616 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
2617 Flag = Chain.getValue(1);
2621 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
2623 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
2626 SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
2627 const PPCSubtarget &Subtarget) {
2628 // When we pop the dynamic allocation we need to restore the SP link.
2630 // Get the corect type for pointers.
2631 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2633 // Construct the stack pointer operand.
2634 bool IsPPC64 = Subtarget.isPPC64();
2635 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2636 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
2638 // Get the operands for the STACKRESTORE.
2639 SDOperand Chain = Op.getOperand(0);
2640 SDOperand SaveSP = Op.getOperand(1);
2642 // Load the old link SP.
2643 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
2645 // Restore the stack pointer.
2646 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
2648 // Store the old link SP.
2649 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
2655 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
2656 MachineFunction &MF = DAG.getMachineFunction();
2657 bool IsPPC64 = PPCSubTarget.isPPC64();
2658 bool isMachoABI = PPCSubTarget.isMachoABI();
2659 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2661 // Get current frame pointer save index. The users of this index will be
2662 // primarily DYNALLOC instructions.
2663 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2664 int RASI = FI->getReturnAddrSaveIndex();
2666 // If the frame pointer save index hasn't been defined yet.
2668 // Find out what the fix offset of the frame pointer save area.
2669 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI);
2670 // Allocate the frame index for frame pointer save area.
2671 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
2673 FI->setReturnAddrSaveIndex(RASI);
2675 return DAG.getFrameIndex(RASI, PtrVT);
2679 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
2680 MachineFunction &MF = DAG.getMachineFunction();
2681 bool IsPPC64 = PPCSubTarget.isPPC64();
2682 bool isMachoABI = PPCSubTarget.isMachoABI();
2683 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2685 // Get current frame pointer save index. The users of this index will be
2686 // primarily DYNALLOC instructions.
2687 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2688 int FPSI = FI->getFramePointerSaveIndex();
2690 // If the frame pointer save index hasn't been defined yet.
2692 // Find out what the fix offset of the frame pointer save area.
2693 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2695 // Allocate the frame index for frame pointer save area.
2696 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
2698 FI->setFramePointerSaveIndex(FPSI);
2700 return DAG.getFrameIndex(FPSI, PtrVT);
2703 SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
2705 const PPCSubtarget &Subtarget) {
2707 SDOperand Chain = Op.getOperand(0);
2708 SDOperand Size = Op.getOperand(1);
2710 // Get the corect type for pointers.
2711 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2713 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
2714 DAG.getConstant(0, PtrVT), Size);
2715 // Construct a node for the frame pointer save index.
2716 SDOperand FPSIdx = getFramePointerFrameIndex(DAG);
2717 // Build a DYNALLOC node.
2718 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
2719 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2720 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2723 SDOperand PPCTargetLowering::LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG) {
2724 MVT VT = Op.Val->getValueType(0);
2725 SDOperand Chain = Op.getOperand(0);
2726 SDOperand Ptr = Op.getOperand(1);
2727 SDOperand Incr = Op.getOperand(2);
2729 // Issue a "load and reserve".
2730 std::vector<MVT> VTs;
2732 VTs.push_back(MVT::Other);
2734 SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32);
2740 SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3);
2741 Chain = Load.getValue(1);
2743 // Compute new value.
2744 SDOperand NewVal = DAG.getNode(ISD::ADD, VT, Load, Incr);
2746 // Issue a "store and check".
2747 SDOperand Ops2[] = {
2753 SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4);
2754 SDOperand OutOps[] = { Load, Store };
2755 return DAG.getMergeValues(OutOps, 2);
2758 SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) {
2759 MVT VT = Op.Val->getValueType(0);
2760 SDOperand Chain = Op.getOperand(0);
2761 SDOperand Ptr = Op.getOperand(1);
2762 SDOperand NewVal = Op.getOperand(2);
2763 SDOperand OldVal = Op.getOperand(3);
2765 // Issue a "load and reserve".
2766 std::vector<MVT> VTs;
2768 VTs.push_back(MVT::Other);
2770 SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32);
2776 SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3);
2777 Chain = Load.getValue(1);
2779 // Compare and unreserve if not equal.
2780 SDOperand Ops2[] = {
2782 OldVal, // Old value
2783 Load, // Value in memory
2786 Chain = DAG.getNode(PPCISD::CMP_UNRESERVE, MVT::Other, Ops2, 4);
2788 // Issue a "store and check".
2789 SDOperand Ops3[] = {
2795 SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops3, 4);
2796 SDOperand OutOps[] = { Load, Store };
2797 return DAG.getMergeValues(OutOps, 2);
2800 SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
2801 MVT VT = Op.Val->getValueType(0);
2802 SDOperand Chain = Op.getOperand(0);
2803 SDOperand Ptr = Op.getOperand(1);
2804 SDOperand NewVal = Op.getOperand(2);
2806 // Issue a "load and reserve".
2807 std::vector<MVT> VTs;
2809 VTs.push_back(MVT::Other);
2811 SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32);
2817 SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3);
2818 Chain = Load.getValue(1);
2820 // Issue a "store and check".
2821 SDOperand Ops2[] = {
2827 SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4);
2828 SDOperand OutOps[] = { Load, Store };
2829 return DAG.getMergeValues(OutOps, 2);
2832 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2834 SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
2835 // Not FP? Not a fsel.
2836 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
2837 !Op.getOperand(2).getValueType().isFloatingPoint())
2840 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2842 // Cannot handle SETEQ/SETNE.
2843 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
2845 MVT ResVT = Op.getValueType();
2846 MVT CmpVT = Op.getOperand(0).getValueType();
2847 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2848 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
2850 // If the RHS of the comparison is a 0.0, we don't need to do the
2851 // subtraction at all.
2852 if (isFloatingPointZero(RHS))
2854 default: break; // SETUO etc aren't handled by fsel.
2858 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2862 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2863 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2864 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2868 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2872 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2873 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2874 return DAG.getNode(PPCISD::FSEL, ResVT,
2875 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2880 default: break; // SETUO etc aren't handled by fsel.
2884 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2885 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2886 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2887 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2891 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2892 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2893 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2894 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2898 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2899 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2900 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2901 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2905 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2906 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2907 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2908 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2913 // FIXME: Split this code up when LegalizeDAGTypes lands.
2914 SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2915 assert(Op.getOperand(0).getValueType().isFloatingPoint());
2916 SDOperand Src = Op.getOperand(0);
2917 if (Src.getValueType() == MVT::f32)
2918 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2921 switch (Op.getValueType().getSimpleVT()) {
2922 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2924 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2927 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2931 // Convert the FP value to an int value through memory.
2932 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
2934 // Emit a store to the stack slot.
2935 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2937 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2939 if (Op.getValueType() == MVT::i32)
2940 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2941 DAG.getConstant(4, FIPtr.getValueType()));
2942 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
2945 SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
2946 SelectionDAG &DAG) {
2947 assert(Op.getValueType() == MVT::ppcf128);
2948 SDNode *Node = Op.Val;
2949 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
2950 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
2951 SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
2952 SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
2954 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2955 // of the long double, and puts FPSCR back the way it was. We do not
2956 // actually model FPSCR.
2957 std::vector<MVT> NodeTys;
2958 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
2960 NodeTys.push_back(MVT::f64); // Return register
2961 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2962 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2963 MFFSreg = Result.getValue(0);
2964 InFlag = Result.getValue(1);
2967 NodeTys.push_back(MVT::Flag); // Returns a flag
2968 Ops[0] = DAG.getConstant(31, MVT::i32);
2970 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2971 InFlag = Result.getValue(0);
2974 NodeTys.push_back(MVT::Flag); // Returns a flag
2975 Ops[0] = DAG.getConstant(30, MVT::i32);
2977 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2978 InFlag = Result.getValue(0);
2981 NodeTys.push_back(MVT::f64); // result of add
2982 NodeTys.push_back(MVT::Flag); // Returns a flag
2986 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2987 FPreg = Result.getValue(0);
2988 InFlag = Result.getValue(1);
2991 NodeTys.push_back(MVT::f64);
2992 Ops[0] = DAG.getConstant(1, MVT::i32);
2996 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
2997 FPreg = Result.getValue(0);
2999 // We know the low half is about to be thrown away, so just use something
3001 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
3004 SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3005 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3006 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3009 if (Op.getOperand(0).getValueType() == MVT::i64) {
3010 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
3011 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
3012 if (Op.getValueType() == MVT::f32)
3013 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
3017 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3018 "Unhandled SINT_TO_FP type in custom expander!");
3019 // Since we only generate this in 64-bit mode, we can take advantage of
3020 // 64-bit registers. In particular, sign extend the input value into the
3021 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3022 // then lfd it and fcfid it.
3023 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3024 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
3025 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3026 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3028 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
3031 // STD the extended value into the stack slot.
3032 MachineMemOperand MO(PseudoSourceValue::getFixedStack(),
3033 MachineMemOperand::MOStore, FrameIdx, 8, 8);
3034 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
3035 DAG.getEntryNode(), Ext64, FIdx,
3036 DAG.getMemOperand(MO));
3037 // Load the value as a double.
3038 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
3040 // FCFID it and return it.
3041 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
3042 if (Op.getValueType() == MVT::f32)
3043 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
3047 SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
3049 The rounding mode is in bits 30:31 of FPSR, and has the following
3056 FLT_ROUNDS, on the other hand, expects the following:
3063 To perform the conversion, we do:
3064 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3067 MachineFunction &MF = DAG.getMachineFunction();
3068 MVT VT = Op.getValueType();
3069 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3070 std::vector<MVT> NodeTys;
3071 SDOperand MFFSreg, InFlag;
3073 // Save FP Control Word to register
3074 NodeTys.push_back(MVT::f64); // return register
3075 NodeTys.push_back(MVT::Flag); // unused in this context
3076 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
3078 // Save FP register to stack slot
3079 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3080 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3081 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
3082 StackSlot, NULL, 0);
3084 // Load FP Control Word from low 32 bits of stack slot.
3085 SDOperand Four = DAG.getConstant(4, PtrVT);
3086 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
3087 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
3089 // Transform as necessary
3091 DAG.getNode(ISD::AND, MVT::i32,
3092 CWD, DAG.getConstant(3, MVT::i32));
3094 DAG.getNode(ISD::SRL, MVT::i32,
3095 DAG.getNode(ISD::AND, MVT::i32,
3096 DAG.getNode(ISD::XOR, MVT::i32,
3097 CWD, DAG.getConstant(3, MVT::i32)),
3098 DAG.getConstant(3, MVT::i32)),
3099 DAG.getConstant(1, MVT::i8));
3102 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
3104 return DAG.getNode((VT.getSizeInBits() < 16 ?
3105 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
3108 SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
3109 MVT VT = Op.getValueType();
3110 unsigned BitWidth = VT.getSizeInBits();
3111 assert(Op.getNumOperands() == 3 &&
3112 VT == Op.getOperand(1).getValueType() &&
3115 // Expand into a bunch of logical ops. Note that these ops
3116 // depend on the PPC behavior for oversized shift amounts.
3117 SDOperand Lo = Op.getOperand(0);
3118 SDOperand Hi = Op.getOperand(1);
3119 SDOperand Amt = Op.getOperand(2);
3120 MVT AmtVT = Amt.getValueType();
3122 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
3123 DAG.getConstant(BitWidth, AmtVT), Amt);
3124 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
3125 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
3126 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3127 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3128 DAG.getConstant(-BitWidth, AmtVT));
3129 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
3130 SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
3131 SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
3132 SDOperand OutOps[] = { OutLo, OutHi };
3133 return DAG.getMergeValues(OutOps, 2);
3136 SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
3137 MVT VT = Op.getValueType();
3138 unsigned BitWidth = VT.getSizeInBits();
3139 assert(Op.getNumOperands() == 3 &&
3140 VT == Op.getOperand(1).getValueType() &&
3143 // Expand into a bunch of logical ops. Note that these ops
3144 // depend on the PPC behavior for oversized shift amounts.
3145 SDOperand Lo = Op.getOperand(0);
3146 SDOperand Hi = Op.getOperand(1);
3147 SDOperand Amt = Op.getOperand(2);
3148 MVT AmtVT = Amt.getValueType();
3150 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
3151 DAG.getConstant(BitWidth, AmtVT), Amt);
3152 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
3153 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
3154 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3155 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3156 DAG.getConstant(-BitWidth, AmtVT));
3157 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
3158 SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
3159 SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
3160 SDOperand OutOps[] = { OutLo, OutHi };
3161 return DAG.getMergeValues(OutOps, 2);
3164 SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
3165 MVT VT = Op.getValueType();
3166 unsigned BitWidth = VT.getSizeInBits();
3167 assert(Op.getNumOperands() == 3 &&
3168 VT == Op.getOperand(1).getValueType() &&
3171 // Expand into a bunch of logical ops, followed by a select_cc.
3172 SDOperand Lo = Op.getOperand(0);
3173 SDOperand Hi = Op.getOperand(1);
3174 SDOperand Amt = Op.getOperand(2);
3175 MVT AmtVT = Amt.getValueType();
3177 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
3178 DAG.getConstant(BitWidth, AmtVT), Amt);
3179 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
3180 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
3181 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3182 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3183 DAG.getConstant(-BitWidth, AmtVT));
3184 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
3185 SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
3186 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
3187 Tmp4, Tmp6, ISD::SETLE);
3188 SDOperand OutOps[] = { OutLo, OutHi };
3189 return DAG.getMergeValues(OutOps, 2);
3192 //===----------------------------------------------------------------------===//
3193 // Vector related lowering.
3196 // If this is a vector of constants or undefs, get the bits. A bit in
3197 // UndefBits is set if the corresponding element of the vector is an
3198 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3199 // zero. Return true if this is not an array of constants, false if it is.
3201 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
3202 uint64_t UndefBits[2]) {
3203 // Start with zero'd results.
3204 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
3206 unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
3207 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3208 SDOperand OpVal = BV->getOperand(i);
3210 unsigned PartNo = i >= e/2; // In the upper 128 bits?
3211 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
3213 uint64_t EltBits = 0;
3214 if (OpVal.getOpcode() == ISD::UNDEF) {
3215 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
3216 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
3218 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
3219 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
3220 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
3221 assert(CN->getValueType(0) == MVT::f32 &&
3222 "Only one legal FP vector type!");
3223 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
3225 // Nonconstant element.
3229 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
3232 //printf("%llx %llx %llx %llx\n",
3233 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
3237 // If this is a splat (repetition) of a value across the whole vector, return
3238 // the smallest size that splats it. For example, "0x01010101010101..." is a
3239 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3240 // SplatSize = 1 byte.
3241 static bool isConstantSplat(const uint64_t Bits128[2],
3242 const uint64_t Undef128[2],
3243 unsigned &SplatBits, unsigned &SplatUndef,
3244 unsigned &SplatSize) {
3246 // Don't let undefs prevent splats from matching. See if the top 64-bits are
3247 // the same as the lower 64-bits, ignoring undefs.
3248 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
3249 return false; // Can't be a splat if two pieces don't match.
3251 uint64_t Bits64 = Bits128[0] | Bits128[1];
3252 uint64_t Undef64 = Undef128[0] & Undef128[1];
3254 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
3256 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
3257 return false; // Can't be a splat if two pieces don't match.
3259 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
3260 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
3262 // If the top 16-bits are different than the lower 16-bits, ignoring
3263 // undefs, we have an i32 splat.
3264 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
3266 SplatUndef = Undef32;
3271 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
3272 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
3274 // If the top 8-bits are different than the lower 8-bits, ignoring
3275 // undefs, we have an i16 splat.
3276 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
3278 SplatUndef = Undef16;
3283 // Otherwise, we have an 8-bit splat.
3284 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
3285 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
3290 /// BuildSplatI - Build a canonical splati of Val with an element size of
3291 /// SplatSize. Cast the result to VT.
3292 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT VT,
3293 SelectionDAG &DAG) {
3294 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3296 static const MVT VTys[] = { // canonical VT to use for each size.
3297 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3300 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3302 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3306 MVT CanonicalVT = VTys[SplatSize-1];
3308 // Build a canonical splat for this value.
3309 SDOperand Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
3310 SmallVector<SDOperand, 8> Ops;
3311 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3312 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
3313 &Ops[0], Ops.size());
3314 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
3317 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3318 /// specified intrinsic ID.
3319 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
3321 MVT DestVT = MVT::Other) {
3322 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3323 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
3324 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3327 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3328 /// specified intrinsic ID.
3329 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
3330 SDOperand Op2, SelectionDAG &DAG,
3331 MVT DestVT = MVT::Other) {
3332 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3333 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
3334 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3338 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3339 /// amount. The result has the specified value type.
3340 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
3341 MVT VT, SelectionDAG &DAG) {
3342 // Force LHS/RHS to be the right type.
3343 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
3344 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
3347 for (unsigned i = 0; i != 16; ++i)
3348 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
3349 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
3350 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
3351 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
3354 // If this is a case we can't handle, return null and let the default
3355 // expansion code take care of it. If we CAN select this case, and if it
3356 // selects to a single instruction, return Op. Otherwise, if we can codegen
3357 // this case more efficiently than a constant pool load, lower it to the
3358 // sequence of ops that should be used.
3359 SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op,
3360 SelectionDAG &DAG) {
3361 // If this is a vector of constants or undefs, get the bits. A bit in
3362 // UndefBits is set if the corresponding element of the vector is an
3363 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3365 uint64_t VectorBits[2];
3366 uint64_t UndefBits[2];
3367 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
3368 return SDOperand(); // Not a constant vector.
3370 // If this is a splat (repetition) of a value across the whole vector, return
3371 // the smallest size that splats it. For example, "0x01010101010101..." is a
3372 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3373 // SplatSize = 1 byte.
3374 unsigned SplatBits, SplatUndef, SplatSize;
3375 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
3376 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
3378 // First, handle single instruction cases.
3381 if (SplatBits == 0) {
3382 // Canonicalize all zero vectors to be v4i32.
3383 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3384 SDOperand Z = DAG.getConstant(0, MVT::i32);
3385 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
3386 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
3391 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3392 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
3393 if (SextVal >= -16 && SextVal <= 15)
3394 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
3397 // Two instruction sequences.
3399 // If this value is in the range [-32,30] and is even, use:
3400 // tmp = VSPLTI[bhw], result = add tmp, tmp
3401 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3402 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
3403 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
3406 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3407 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3409 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3410 // Make -1 and vspltisw -1:
3411 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
3413 // Make the VSLW intrinsic, computing 0x8000_0000.
3414 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3417 // xor by OnesV to invert it.
3418 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
3419 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3422 // Check to see if this is a wide variety of vsplti*, binop self cases.
3423 unsigned SplatBitSize = SplatSize*8;
3424 static const signed char SplatCsts[] = {
3425 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3426 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3429 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3430 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3431 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3432 int i = SplatCsts[idx];
3434 // Figure out what shift amount will be used by altivec if shifted by i in
3436 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3438 // vsplti + shl self.
3439 if (SextVal == (i << (int)TypeShiftAmt)) {
3440 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3441 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3442 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3443 Intrinsic::ppc_altivec_vslw
3445 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3446 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3449 // vsplti + srl self.
3450 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3451 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3452 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3453 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3454 Intrinsic::ppc_altivec_vsrw
3456 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3457 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3460 // vsplti + sra self.
3461 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3462 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3463 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3464 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3465 Intrinsic::ppc_altivec_vsraw
3467 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3468 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3471 // vsplti + rol self.
3472 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3473 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3474 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3475 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3476 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3477 Intrinsic::ppc_altivec_vrlw
3479 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3480 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3483 // t = vsplti c, result = vsldoi t, t, 1
3484 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3485 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3486 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
3488 // t = vsplti c, result = vsldoi t, t, 2
3489 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3490 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3491 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
3493 // t = vsplti c, result = vsldoi t, t, 3
3494 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3495 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3496 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
3500 // Three instruction sequences.
3502 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3503 if (SextVal >= 0 && SextVal <= 31) {
3504 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
3505 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
3506 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
3507 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
3509 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3510 if (SextVal >= -31 && SextVal <= 0) {
3511 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
3512 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
3513 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
3514 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
3521 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3522 /// the specified operations to build the shuffle.
3523 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
3524 SDOperand RHS, SelectionDAG &DAG) {
3525 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3526 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3527 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3530 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3542 if (OpNum == OP_COPY) {
3543 if (LHSID == (1*9+2)*9+3) return LHS;
3544 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3548 SDOperand OpLHS, OpRHS;
3549 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
3550 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
3552 unsigned ShufIdxs[16];
3554 default: assert(0 && "Unknown i32 permute!");
3556 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3557 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3558 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3559 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3562 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3563 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3564 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3565 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3568 for (unsigned i = 0; i != 16; ++i)
3569 ShufIdxs[i] = (i&3)+0;
3572 for (unsigned i = 0; i != 16; ++i)
3573 ShufIdxs[i] = (i&3)+4;
3576 for (unsigned i = 0; i != 16; ++i)
3577 ShufIdxs[i] = (i&3)+8;
3580 for (unsigned i = 0; i != 16; ++i)
3581 ShufIdxs[i] = (i&3)+12;
3584 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
3586 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
3588 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
3591 for (unsigned i = 0; i != 16; ++i)
3592 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
3594 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
3595 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3598 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3599 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3600 /// return the code it can be lowered into. Worst case, it can always be
3601 /// lowered into a vperm.
3602 SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op,
3603 SelectionDAG &DAG) {
3604 SDOperand V1 = Op.getOperand(0);
3605 SDOperand V2 = Op.getOperand(1);
3606 SDOperand PermMask = Op.getOperand(2);
3608 // Cases that are handled by instructions that take permute immediates
3609 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3610 // selected by the instruction selector.
3611 if (V2.getOpcode() == ISD::UNDEF) {
3612 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
3613 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
3614 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
3615 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
3616 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
3617 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
3618 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
3619 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
3620 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
3621 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
3622 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
3623 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
3628 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3629 // and produce a fixed permutation. If any of these match, do not lower to
3631 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
3632 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
3633 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
3634 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
3635 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
3636 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
3637 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
3638 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
3639 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
3642 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3643 // perfect shuffle table to emit an optimal matching sequence.
3644 unsigned PFIndexes[4];
3645 bool isFourElementShuffle = true;
3646 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3647 unsigned EltNo = 8; // Start out undef.
3648 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3649 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
3650 continue; // Undef, ignore it.
3652 unsigned ByteSource =
3653 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
3654 if ((ByteSource & 3) != j) {
3655 isFourElementShuffle = false;
3660 EltNo = ByteSource/4;
3661 } else if (EltNo != ByteSource/4) {
3662 isFourElementShuffle = false;
3666 PFIndexes[i] = EltNo;
3669 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3670 // perfect shuffle vector to determine if it is cost effective to do this as
3671 // discrete instructions, or whether we should use a vperm.
3672 if (isFourElementShuffle) {
3673 // Compute the index in the perfect shuffle table.
3674 unsigned PFTableIndex =
3675 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3677 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3678 unsigned Cost = (PFEntry >> 30);
3680 // Determining when to avoid vperm is tricky. Many things affect the cost
3681 // of vperm, particularly how many times the perm mask needs to be computed.
3682 // For example, if the perm mask can be hoisted out of a loop or is already
3683 // used (perhaps because there are multiple permutes with the same shuffle
3684 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3685 // the loop requires an extra register.
3687 // As a compromise, we only emit discrete instructions if the shuffle can be
3688 // generated in 3 or fewer operations. When we have loop information
3689 // available, if this block is within a loop, we should avoid using vperm
3690 // for 3-operation perms and use a constant pool load instead.
3692 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
3695 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3696 // vector that will get spilled to the constant pool.
3697 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3699 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3700 // that it is in input element units, not in bytes. Convert now.
3701 MVT EltVT = V1.getValueType().getVectorElementType();
3702 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
3704 SmallVector<SDOperand, 16> ResultMask;
3705 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
3707 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
3710 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
3712 for (unsigned j = 0; j != BytesPerElement; ++j)
3713 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3717 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
3718 &ResultMask[0], ResultMask.size());
3719 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
3722 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3723 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3724 /// information about the intrinsic.
3725 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
3727 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
3730 switch (IntrinsicID) {
3731 default: return false;
3732 // Comparison predicates.
3733 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3734 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3735 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3736 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3737 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3738 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3739 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3740 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3741 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3742 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3743 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3744 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3745 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3747 // Normal Comparisons.
3748 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3749 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3750 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3751 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3752 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3753 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3754 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3755 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3756 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3757 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
3758 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
3759 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
3760 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3765 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3766 /// lower, do it, otherwise return null.
3767 SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op,
3768 SelectionDAG &DAG) {
3769 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3770 // opcode number of the comparison.
3773 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3774 return SDOperand(); // Don't custom lower most intrinsics.
3776 // If this is a non-dot comparison, make the VCMP node and we are done.
3778 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
3779 Op.getOperand(1), Op.getOperand(2),
3780 DAG.getConstant(CompareOpc, MVT::i32));
3781 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
3784 // Create the PPCISD altivec 'dot' comparison node.
3786 Op.getOperand(2), // LHS
3787 Op.getOperand(3), // RHS
3788 DAG.getConstant(CompareOpc, MVT::i32)
3790 std::vector<MVT> VTs;
3791 VTs.push_back(Op.getOperand(2).getValueType());
3792 VTs.push_back(MVT::Flag);
3793 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3795 // Now that we have the comparison, emit a copy from the CR to a GPR.
3796 // This is flagged to the above dot comparison.
3797 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
3798 DAG.getRegister(PPC::CR6, MVT::i32),
3799 CompNode.getValue(1));
3801 // Unpack the result based on how the target uses it.
3802 unsigned BitNo; // Bit # of CR6.
3803 bool InvertBit; // Invert result?
3804 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
3805 default: // Can't happen, don't crash on invalid number though.
3806 case 0: // Return the value of the EQ bit of CR6.
3807 BitNo = 0; InvertBit = false;
3809 case 1: // Return the inverted value of the EQ bit of CR6.
3810 BitNo = 0; InvertBit = true;
3812 case 2: // Return the value of the LT bit of CR6.
3813 BitNo = 2; InvertBit = false;
3815 case 3: // Return the inverted value of the LT bit of CR6.
3816 BitNo = 2; InvertBit = true;
3820 // Shift the bit into the low position.
3821 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
3822 DAG.getConstant(8-(3-BitNo), MVT::i32));
3824 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
3825 DAG.getConstant(1, MVT::i32));
3827 // If we are supposed to, toggle the bit.
3829 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
3830 DAG.getConstant(1, MVT::i32));
3834 SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op,
3835 SelectionDAG &DAG) {
3836 // Create a stack slot that is 16-byte aligned.
3837 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3838 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3839 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3840 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3842 // Store the input value into Value#0 of the stack slot.
3843 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
3844 Op.getOperand(0), FIdx, NULL, 0);
3846 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
3849 SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) {
3850 if (Op.getValueType() == MVT::v4i32) {
3851 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3853 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3854 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3856 SDOperand RHSSwap = // = vrlw RHS, 16
3857 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3859 // Shrinkify inputs to v8i16.
3860 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3861 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3862 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3864 // Low parts multiplied together, generating 32-bit results (we ignore the
3866 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3867 LHS, RHS, DAG, MVT::v4i32);
3869 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3870 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3871 // Shift the high parts up 16 bits.
3872 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3873 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3874 } else if (Op.getValueType() == MVT::v8i16) {
3875 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3877 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
3879 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3880 LHS, RHS, Zero, DAG);
3881 } else if (Op.getValueType() == MVT::v16i8) {
3882 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3884 // Multiply the even 8-bit parts, producing 16-bit sums.
3885 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3886 LHS, RHS, DAG, MVT::v8i16);
3887 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3889 // Multiply the odd 8-bit parts, producing 16-bit sums.
3890 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3891 LHS, RHS, DAG, MVT::v8i16);
3892 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3894 // Merge the results together.
3896 for (unsigned i = 0; i != 8; ++i) {
3897 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3898 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3900 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
3901 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3903 assert(0 && "Unknown mul to lower!");
3908 /// LowerOperation - Provide custom lowering hooks for some operations.
3910 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3911 switch (Op.getOpcode()) {
3912 default: assert(0 && "Wasn't expecting to be able to lower this!");
3913 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3914 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3915 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3916 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3917 case ISD::SETCC: return LowerSETCC(Op, DAG);
3919 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3920 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3923 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3924 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3926 case ISD::FORMAL_ARGUMENTS:
3927 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3928 VarArgsStackOffset, VarArgsNumGPR,
3929 VarArgsNumFPR, PPCSubTarget);
3931 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget,
3932 getTargetMachine());
3933 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3934 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3935 case ISD::DYNAMIC_STACKALLOC:
3936 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3938 case ISD::ATOMIC_LOAD_ADD: return LowerAtomicLOAD_ADD(Op, DAG);
3939 case ISD::ATOMIC_CMP_SWAP: return LowerAtomicCMP_SWAP(Op, DAG);
3940 case ISD::ATOMIC_SWAP: return LowerAtomicSWAP(Op, DAG);
3942 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3943 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3944 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3945 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
3946 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3948 // Lower 64-bit shifts.
3949 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3950 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3951 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3953 // Vector-related lowering.
3954 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3955 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3956 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3957 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3958 case ISD::MUL: return LowerMUL(Op, DAG);
3960 // Frame & Return address.
3961 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3962 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3967 SDNode *PPCTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
3968 switch (N->getOpcode()) {
3969 default: assert(0 && "Wasn't expecting to be able to lower this!");
3970 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val;
3975 //===----------------------------------------------------------------------===//
3976 // Other Lowering Code
3977 //===----------------------------------------------------------------------===//
3980 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3981 MachineBasicBlock *BB) {
3982 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3983 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
3984 MI->getOpcode() == PPC::SELECT_CC_I8 ||
3985 MI->getOpcode() == PPC::SELECT_CC_F4 ||
3986 MI->getOpcode() == PPC::SELECT_CC_F8 ||
3987 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
3988 "Unexpected instr type to insert");
3990 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3991 // control-flow pattern. The incoming instruction knows the destination vreg
3992 // to set, the condition code register to branch on, the true/false values to
3993 // select between, and a branch opcode to use.
3994 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3995 ilist<MachineBasicBlock>::iterator It = BB;
4001 // cmpTY ccX, r1, r2
4003 // fallthrough --> copy0MBB
4004 MachineBasicBlock *thisMBB = BB;
4005 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4006 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4007 unsigned SelectPred = MI->getOperand(4).getImm();
4008 BuildMI(BB, TII->get(PPC::BCC))
4009 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4010 MachineFunction *F = BB->getParent();
4011 F->getBasicBlockList().insert(It, copy0MBB);
4012 F->getBasicBlockList().insert(It, sinkMBB);
4013 // Update machine-CFG edges by transferring all successors of the current
4014 // block to the new block which will contain the Phi node for the select.
4015 sinkMBB->transferSuccessors(BB);
4016 // Next, add the true and fallthrough blocks as its successors.
4017 BB->addSuccessor(copy0MBB);
4018 BB->addSuccessor(sinkMBB);
4021 // %FalseValue = ...
4022 // # fallthrough to sinkMBB
4025 // Update machine-CFG edges
4026 BB->addSuccessor(sinkMBB);
4029 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4032 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4033 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4034 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4036 delete MI; // The pseudo instruction is gone now.
4040 //===----------------------------------------------------------------------===//
4041 // Target Optimization Hooks
4042 //===----------------------------------------------------------------------===//
4044 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
4045 DAGCombinerInfo &DCI) const {
4046 TargetMachine &TM = getTargetMachine();
4047 SelectionDAG &DAG = DCI.DAG;
4048 switch (N->getOpcode()) {
4051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4052 if (C->getValue() == 0) // 0 << V -> 0.
4053 return N->getOperand(0);
4057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4058 if (C->getValue() == 0) // 0 >>u V -> 0.
4059 return N->getOperand(0);
4063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4064 if (C->getValue() == 0 || // 0 >>s V -> 0.
4065 C->isAllOnesValue()) // -1 >>s V -> -1.
4066 return N->getOperand(0);
4070 case ISD::SINT_TO_FP:
4071 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4072 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4073 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4074 // We allow the src/dst to be either f32/f64, but the intermediate
4075 // type must be i64.
4076 if (N->getOperand(0).getValueType() == MVT::i64 &&
4077 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4078 SDOperand Val = N->getOperand(0).getOperand(0);
4079 if (Val.getValueType() == MVT::f32) {
4080 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
4081 DCI.AddToWorklist(Val.Val);
4084 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
4085 DCI.AddToWorklist(Val.Val);
4086 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
4087 DCI.AddToWorklist(Val.Val);
4088 if (N->getValueType(0) == MVT::f32) {
4089 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
4090 DAG.getIntPtrConstant(0));
4091 DCI.AddToWorklist(Val.Val);
4094 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4095 // If the intermediate type is i32, we can avoid the load/store here
4102 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4103 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4104 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4105 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4106 N->getOperand(1).getValueType() == MVT::i32 &&
4107 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4108 SDOperand Val = N->getOperand(1).getOperand(0);
4109 if (Val.getValueType() == MVT::f32) {
4110 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
4111 DCI.AddToWorklist(Val.Val);
4113 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
4114 DCI.AddToWorklist(Val.Val);
4116 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
4117 N->getOperand(2), N->getOperand(3));
4118 DCI.AddToWorklist(Val.Val);
4122 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4123 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
4124 N->getOperand(1).Val->hasOneUse() &&
4125 (N->getOperand(1).getValueType() == MVT::i32 ||
4126 N->getOperand(1).getValueType() == MVT::i16)) {
4127 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
4128 // Do an any-extend to 32-bits if this is a half-word input.
4129 if (BSwapOp.getValueType() == MVT::i16)
4130 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
4132 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
4133 N->getOperand(2), N->getOperand(3),
4134 DAG.getValueType(N->getOperand(1).getValueType()));
4138 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4139 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
4140 N->getOperand(0).hasOneUse() &&
4141 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4142 SDOperand Load = N->getOperand(0);
4143 LoadSDNode *LD = cast<LoadSDNode>(Load);
4144 // Create the byte-swapping load.
4145 std::vector<MVT> VTs;
4146 VTs.push_back(MVT::i32);
4147 VTs.push_back(MVT::Other);
4148 SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
4150 LD->getChain(), // Chain
4151 LD->getBasePtr(), // Ptr
4153 DAG.getValueType(N->getValueType(0)) // VT
4155 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
4157 // If this is an i16 load, insert the truncate.
4158 SDOperand ResVal = BSLoad;
4159 if (N->getValueType(0) == MVT::i16)
4160 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
4162 // First, combine the bswap away. This makes the value produced by the
4164 DCI.CombineTo(N, ResVal);
4166 // Next, combine the load away, we give it a bogus result value but a real
4167 // chain result. The result value is dead because the bswap is dead.
4168 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
4170 // Return N so it doesn't get rechecked!
4171 return SDOperand(N, 0);
4175 case PPCISD::VCMP: {
4176 // If a VCMPo node already exists with exactly the same operands as this
4177 // node, use its result instead of this node (VCMPo computes both a CR6 and
4178 // a normal output).
4180 if (!N->getOperand(0).hasOneUse() &&
4181 !N->getOperand(1).hasOneUse() &&
4182 !N->getOperand(2).hasOneUse()) {
4184 // Scan all of the users of the LHS, looking for VCMPo's that match.
4185 SDNode *VCMPoNode = 0;
4187 SDNode *LHSN = N->getOperand(0).Val;
4188 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
4190 if ((*UI).getUser()->getOpcode() == PPCISD::VCMPo &&
4191 (*UI).getUser()->getOperand(1) == N->getOperand(1) &&
4192 (*UI).getUser()->getOperand(2) == N->getOperand(2) &&
4193 (*UI).getUser()->getOperand(0) == N->getOperand(0)) {
4194 VCMPoNode = UI->getUser();
4198 // If there is no VCMPo node, or if the flag value has a single use, don't
4200 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
4203 // Look at the (necessarily single) use of the flag value. If it has a
4204 // chain, this transformation is more complex. Note that multiple things
4205 // could use the value result, which we should ignore.
4206 SDNode *FlagUser = 0;
4207 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
4208 FlagUser == 0; ++UI) {
4209 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
4210 SDNode *User = UI->getUser();
4211 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
4212 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
4219 // If the user is a MFCR instruction, we know this is safe. Otherwise we
4220 // give up for right now.
4221 if (FlagUser->getOpcode() == PPCISD::MFCR)
4222 return SDOperand(VCMPoNode, 0);
4227 // If this is a branch on an altivec predicate comparison, lower this so
4228 // that we don't have to do a MFCR: instead, branch directly on CR6. This
4229 // lowering is done pre-legalize, because the legalizer lowers the predicate
4230 // compare down to code that is difficult to reassemble.
4231 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
4232 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
4236 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
4237 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
4238 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
4239 assert(isDot && "Can't compare against a vector result!");
4241 // If this is a comparison against something other than 0/1, then we know
4242 // that the condition is never/always true.
4243 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
4244 if (Val != 0 && Val != 1) {
4245 if (CC == ISD::SETEQ) // Cond never true, remove branch.
4246 return N->getOperand(0);
4247 // Always !=, turn it into an unconditional branch.
4248 return DAG.getNode(ISD::BR, MVT::Other,
4249 N->getOperand(0), N->getOperand(4));
4252 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
4254 // Create the PPCISD altivec 'dot' comparison node.
4255 std::vector<MVT> VTs;
4257 LHS.getOperand(2), // LHS of compare
4258 LHS.getOperand(3), // RHS of compare
4259 DAG.getConstant(CompareOpc, MVT::i32)
4261 VTs.push_back(LHS.getOperand(2).getValueType());
4262 VTs.push_back(MVT::Flag);
4263 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
4265 // Unpack the result based on how the target uses it.
4266 PPC::Predicate CompOpc;
4267 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
4268 default: // Can't happen, don't crash on invalid number though.
4269 case 0: // Branch on the value of the EQ bit of CR6.
4270 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
4272 case 1: // Branch on the inverted value of the EQ bit of CR6.
4273 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
4275 case 2: // Branch on the value of the LT bit of CR6.
4276 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
4278 case 3: // Branch on the inverted value of the LT bit of CR6.
4279 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
4283 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
4284 DAG.getConstant(CompOpc, MVT::i32),
4285 DAG.getRegister(PPC::CR6, MVT::i32),
4286 N->getOperand(4), CompNode.getValue(1));
4295 //===----------------------------------------------------------------------===//
4296 // Inline Assembly Support
4297 //===----------------------------------------------------------------------===//
4299 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4303 const SelectionDAG &DAG,
4304 unsigned Depth) const {
4305 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4306 switch (Op.getOpcode()) {
4308 case PPCISD::LBRX: {
4309 // lhbrx is known to have the top bits cleared out.
4310 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
4311 KnownZero = 0xFFFF0000;
4314 case ISD::INTRINSIC_WO_CHAIN: {
4315 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
4317 case Intrinsic::ppc_altivec_vcmpbfp_p:
4318 case Intrinsic::ppc_altivec_vcmpeqfp_p:
4319 case Intrinsic::ppc_altivec_vcmpequb_p:
4320 case Intrinsic::ppc_altivec_vcmpequh_p:
4321 case Intrinsic::ppc_altivec_vcmpequw_p:
4322 case Intrinsic::ppc_altivec_vcmpgefp_p:
4323 case Intrinsic::ppc_altivec_vcmpgtfp_p:
4324 case Intrinsic::ppc_altivec_vcmpgtsb_p:
4325 case Intrinsic::ppc_altivec_vcmpgtsh_p:
4326 case Intrinsic::ppc_altivec_vcmpgtsw_p:
4327 case Intrinsic::ppc_altivec_vcmpgtub_p:
4328 case Intrinsic::ppc_altivec_vcmpgtuh_p:
4329 case Intrinsic::ppc_altivec_vcmpgtuw_p:
4330 KnownZero = ~1U; // All bits but the low one are known to be zero.
4338 /// getConstraintType - Given a constraint, return the type of
4339 /// constraint it is for this target.
4340 PPCTargetLowering::ConstraintType
4341 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
4342 if (Constraint.size() == 1) {
4343 switch (Constraint[0]) {
4350 return C_RegisterClass;
4353 return TargetLowering::getConstraintType(Constraint);
4356 std::pair<unsigned, const TargetRegisterClass*>
4357 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4359 if (Constraint.size() == 1) {
4360 // GCC RS6000 Constraint Letters
4361 switch (Constraint[0]) {
4364 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
4365 return std::make_pair(0U, PPC::G8RCRegisterClass);
4366 return std::make_pair(0U, PPC::GPRCRegisterClass);
4369 return std::make_pair(0U, PPC::F4RCRegisterClass);
4370 else if (VT == MVT::f64)
4371 return std::make_pair(0U, PPC::F8RCRegisterClass);
4374 return std::make_pair(0U, PPC::VRRCRegisterClass);
4376 return std::make_pair(0U, PPC::CRRCRegisterClass);
4380 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4384 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4385 /// vector. If it is invalid, don't add anything to Ops.
4386 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
4387 std::vector<SDOperand>&Ops,
4388 SelectionDAG &DAG) const {
4389 SDOperand Result(0,0);
4400 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
4401 if (!CST) return; // Must be an immediate to match.
4402 unsigned Value = CST->getValue();
4404 default: assert(0 && "Unknown constraint letter!");
4405 case 'I': // "I" is a signed 16-bit constant.
4406 if ((short)Value == (int)Value)
4407 Result = DAG.getTargetConstant(Value, Op.getValueType());
4409 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
4410 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
4411 if ((short)Value == 0)
4412 Result = DAG.getTargetConstant(Value, Op.getValueType());
4414 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
4415 if ((Value >> 16) == 0)
4416 Result = DAG.getTargetConstant(Value, Op.getValueType());
4418 case 'M': // "M" is a constant that is greater than 31.
4420 Result = DAG.getTargetConstant(Value, Op.getValueType());
4422 case 'N': // "N" is a positive constant that is an exact power of two.
4423 if ((int)Value > 0 && isPowerOf2_32(Value))
4424 Result = DAG.getTargetConstant(Value, Op.getValueType());
4426 case 'O': // "O" is the constant zero.
4428 Result = DAG.getTargetConstant(Value, Op.getValueType());
4430 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
4431 if ((short)-Value == (int)-Value)
4432 Result = DAG.getTargetConstant(Value, Op.getValueType());
4440 Ops.push_back(Result);
4444 // Handle standard constraint letters.
4445 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
4448 // isLegalAddressingMode - Return true if the addressing mode represented
4449 // by AM is legal for this target, for a load/store of the specified type.
4450 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4451 const Type *Ty) const {
4452 // FIXME: PPC does not allow r+i addressing modes for vectors!
4454 // PPC allows a sign-extended 16-bit immediate field.
4455 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
4458 // No global is ever allowed as a base.
4462 // PPC only support r+r,
4464 case 0: // "r+i" or just "i", depending on HasBaseReg.
4467 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
4469 // Otherwise we have r+r or r+i.
4472 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
4474 // Allow 2*r as r+r.
4477 // No other scales are supported.
4484 /// isLegalAddressImmediate - Return true if the integer value can be used
4485 /// as the offset of the target addressing mode for load / store of the
4487 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
4488 // PPC allows a sign-extended 16-bit immediate field.
4489 return (V > -(1 << 16) && V < (1 << 16)-1);
4492 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
4496 SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4497 // Depths > 0 not supported yet!
4498 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4501 MachineFunction &MF = DAG.getMachineFunction();
4502 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4504 // Just load the return address off the stack.
4505 SDOperand RetAddrFI = getReturnAddrFrameIndex(DAG);
4507 // Make sure the function really does not optimize away the store of the RA
4509 FuncInfo->setLRStoreRequired();
4510 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4513 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4514 // Depths > 0 not supported yet!
4515 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4518 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4519 bool isPPC64 = PtrVT == MVT::i64;
4521 MachineFunction &MF = DAG.getMachineFunction();
4522 MachineFrameInfo *MFI = MF.getFrameInfo();
4523 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
4524 && MFI->getStackSize();
4527 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
4530 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,