1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
49 // FIXME: Remove this once the bug has been fixed!
50 extern cl::opt<bool> ANDIGlueBug;
52 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
53 if (TM.getSubtargetImpl()->isDarwin())
54 return new TargetLoweringObjectFileMachO();
56 if (TM.getSubtargetImpl()->isSVR4ABI())
57 return new PPC64LinuxTargetObjectFile();
59 return new TargetLoweringObjectFileELF();
62 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
63 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
64 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget->isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget->useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget->hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget->hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget->hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget->hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget->hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget->hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget->useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget->useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget->useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget->isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget->isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget->has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (PPCSubTarget.hasFPCVT()) {
371 if (Subtarget->has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget->use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget->hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::CTPOP, VT, Expand);
463 setOperationAction(ISD::CTLZ, VT, Expand);
464 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
465 setOperationAction(ISD::CTTZ, VT, Expand);
466 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
467 setOperationAction(ISD::VSELECT, VT, Expand);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
470 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
471 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
472 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
473 setTruncStoreAction(VT, InnerVT, Expand);
475 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
476 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
480 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
481 // with merges, splats, etc.
482 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
484 setOperationAction(ISD::AND , MVT::v4i32, Legal);
485 setOperationAction(ISD::OR , MVT::v4i32, Legal);
486 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
487 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
488 setOperationAction(ISD::SELECT, MVT::v4i32,
489 Subtarget->useCRBits() ? Legal : Expand);
490 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
491 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
494 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
496 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
497 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
498 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
500 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
501 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
505 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
506 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
508 if (TM.Options.UnsafeFPMath || Subtarget->hasVSX()) {
509 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
510 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
513 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
514 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
515 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
517 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
520 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
525 // Altivec does not contain unordered floating-point compare instructions
526 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
527 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
533 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
536 if (Subtarget->hasVSX()) {
537 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
538 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
540 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
541 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
542 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
543 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
544 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
546 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
548 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
549 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
551 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
552 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
554 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
560 // Share the Altivec comparison restrictions.
561 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
562 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
568 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
571 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
572 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
574 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
576 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
578 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
579 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
581 // VSX v2i64 only supports non-arithmetic operations.
582 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
583 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
585 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
586 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
589 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
591 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
592 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
593 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
594 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
596 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
598 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
599 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
603 // Vector operation legalization checks the result type of
604 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
605 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
610 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
614 if (Subtarget->has64BitSupport()) {
615 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
616 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
619 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
620 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
622 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
624 setBooleanContents(ZeroOrOneBooleanContent);
625 // Altivec instructions set fields to all zeros or all ones.
626 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
629 setStackPointerRegisterToSaveRestore(PPC::X1);
630 setExceptionPointerRegister(PPC::X3);
631 setExceptionSelectorRegister(PPC::X4);
633 setStackPointerRegisterToSaveRestore(PPC::R1);
634 setExceptionPointerRegister(PPC::R3);
635 setExceptionSelectorRegister(PPC::R4);
638 // We have target-specific dag combine patterns for the following nodes:
639 setTargetDAGCombine(ISD::SINT_TO_FP);
640 setTargetDAGCombine(ISD::LOAD);
641 setTargetDAGCombine(ISD::STORE);
642 setTargetDAGCombine(ISD::BR_CC);
643 if (Subtarget->useCRBits())
644 setTargetDAGCombine(ISD::BRCOND);
645 setTargetDAGCombine(ISD::BSWAP);
646 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
648 setTargetDAGCombine(ISD::SIGN_EXTEND);
649 setTargetDAGCombine(ISD::ZERO_EXTEND);
650 setTargetDAGCombine(ISD::ANY_EXTEND);
652 if (Subtarget->useCRBits()) {
653 setTargetDAGCombine(ISD::TRUNCATE);
654 setTargetDAGCombine(ISD::SETCC);
655 setTargetDAGCombine(ISD::SELECT_CC);
658 // Use reciprocal estimates.
659 if (TM.Options.UnsafeFPMath) {
660 setTargetDAGCombine(ISD::FDIV);
661 setTargetDAGCombine(ISD::FSQRT);
664 // Darwin long double math library functions have $LDBL128 appended.
665 if (Subtarget->isDarwin()) {
666 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
667 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
668 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
669 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
670 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
671 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
672 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
673 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
674 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
675 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
678 // With 32 condition bits, we don't need to sink (and duplicate) compares
679 // aggressively in CodeGenPrep.
680 if (Subtarget->useCRBits())
681 setHasMultipleConditionRegisters();
683 setMinFunctionAlignment(2);
684 if (PPCSubTarget.isDarwin())
685 setPrefFunctionAlignment(4);
687 if (isPPC64 && Subtarget->isJITCodeModel())
688 // Temporary workaround for the inability of PPC64 JIT to handle jump
690 setSupportJumpTables(false);
692 setInsertFencesForAtomic(true);
694 if (Subtarget->enableMachineScheduler())
695 setSchedulingPreference(Sched::Source);
697 setSchedulingPreference(Sched::Hybrid);
699 computeRegisterProperties();
701 // The Freescale cores does better with aggressive inlining of memcpy and
702 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
703 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
704 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
705 MaxStoresPerMemset = 32;
706 MaxStoresPerMemsetOptSize = 16;
707 MaxStoresPerMemcpy = 32;
708 MaxStoresPerMemcpyOptSize = 8;
709 MaxStoresPerMemmove = 32;
710 MaxStoresPerMemmoveOptSize = 8;
712 setPrefFunctionAlignment(4);
716 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
717 /// the desired ByVal argument alignment.
718 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
719 unsigned MaxMaxAlign) {
720 if (MaxAlign == MaxMaxAlign)
722 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
723 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
725 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
727 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
728 unsigned EltAlign = 0;
729 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
730 if (EltAlign > MaxAlign)
732 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
733 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
734 unsigned EltAlign = 0;
735 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
736 if (EltAlign > MaxAlign)
738 if (MaxAlign == MaxMaxAlign)
744 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
745 /// function arguments in the caller parameter area.
746 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
747 // Darwin passes everything on 4 byte boundary.
748 if (PPCSubTarget.isDarwin())
751 // 16byte and wider vectors are passed on 16byte boundary.
752 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
753 unsigned Align = PPCSubTarget.isPPC64() ? 8 : 4;
754 if (PPCSubTarget.hasAltivec() || PPCSubTarget.hasQPX())
755 getMaxByValAlign(Ty, Align, PPCSubTarget.hasQPX() ? 32 : 16);
759 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 case PPCISD::FSEL: return "PPCISD::FSEL";
763 case PPCISD::FCFID: return "PPCISD::FCFID";
764 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
765 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
766 case PPCISD::FRE: return "PPCISD::FRE";
767 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
768 case PPCISD::STFIWX: return "PPCISD::STFIWX";
769 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
770 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
771 case PPCISD::VPERM: return "PPCISD::VPERM";
772 case PPCISD::Hi: return "PPCISD::Hi";
773 case PPCISD::Lo: return "PPCISD::Lo";
774 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
775 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
776 case PPCISD::LOAD: return "PPCISD::LOAD";
777 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
778 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
779 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
780 case PPCISD::SRL: return "PPCISD::SRL";
781 case PPCISD::SRA: return "PPCISD::SRA";
782 case PPCISD::SHL: return "PPCISD::SHL";
783 case PPCISD::CALL: return "PPCISD::CALL";
784 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
785 case PPCISD::MTCTR: return "PPCISD::MTCTR";
786 case PPCISD::BCTRL: return "PPCISD::BCTRL";
787 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
788 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
789 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
790 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
791 case PPCISD::VCMP: return "PPCISD::VCMP";
792 case PPCISD::VCMPo: return "PPCISD::VCMPo";
793 case PPCISD::LBRX: return "PPCISD::LBRX";
794 case PPCISD::STBRX: return "PPCISD::STBRX";
795 case PPCISD::LARX: return "PPCISD::LARX";
796 case PPCISD::STCX: return "PPCISD::STCX";
797 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
798 case PPCISD::BDNZ: return "PPCISD::BDNZ";
799 case PPCISD::BDZ: return "PPCISD::BDZ";
800 case PPCISD::MFFS: return "PPCISD::MFFS";
801 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
802 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
803 case PPCISD::CR6SET: return "PPCISD::CR6SET";
804 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
805 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
806 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
807 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
808 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
809 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
810 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
811 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
812 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
813 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
814 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
815 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
816 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
817 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
818 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
819 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
820 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
821 case PPCISD::SC: return "PPCISD::SC";
825 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
827 return PPCSubTarget.useCRBits() ? MVT::i1 : MVT::i32;
828 return VT.changeVectorElementTypeToInteger();
831 //===----------------------------------------------------------------------===//
832 // Node matching predicates, for use by the tblgen matching code.
833 //===----------------------------------------------------------------------===//
835 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
836 static bool isFloatingPointZero(SDValue Op) {
837 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
838 return CFP->getValueAPF().isZero();
839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
840 // Maybe this has already been legalized into the constant pool?
841 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
842 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
843 return CFP->getValueAPF().isZero();
848 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
849 /// true if Op is undef or if it matches the specified value.
850 static bool isConstantOrUndef(int Op, int Val) {
851 return Op < 0 || Op == Val;
854 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
855 /// VPKUHUM instruction.
856 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
858 for (unsigned i = 0; i != 16; ++i)
859 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
862 for (unsigned i = 0; i != 8; ++i)
863 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
864 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
870 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
871 /// VPKUWUM instruction.
872 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
874 for (unsigned i = 0; i != 16; i += 2)
875 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
876 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
879 for (unsigned i = 0; i != 8; i += 2)
880 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
881 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
882 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
883 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
889 /// isVMerge - Common function, used to match vmrg* shuffles.
891 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
892 unsigned LHSStart, unsigned RHSStart) {
893 if (N->getValueType(0) != MVT::v16i8)
895 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
896 "Unsupported merge size!");
898 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
899 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
900 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
901 LHSStart+j+i*UnitSize) ||
902 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
903 RHSStart+j+i*UnitSize))
909 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
910 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
911 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
914 return isVMerge(N, UnitSize, 8, 24);
915 return isVMerge(N, UnitSize, 8, 8);
918 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
919 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
920 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
923 return isVMerge(N, UnitSize, 0, 16);
924 return isVMerge(N, UnitSize, 0, 0);
928 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
929 /// amount, otherwise return -1.
930 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
931 if (N->getValueType(0) != MVT::v16i8)
934 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
936 // Find the first non-undef value in the shuffle mask.
938 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
941 if (i == 16) return -1; // all undef.
943 // Otherwise, check to see if the rest of the elements are consecutively
944 // numbered from this value.
945 unsigned ShiftAmt = SVOp->getMaskElt(i);
946 if (ShiftAmt < i) return -1;
950 // Check the rest of the elements to see if they are consecutive.
951 for (++i; i != 16; ++i)
952 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
955 // Check the rest of the elements to see if they are consecutive.
956 for (++i; i != 16; ++i)
957 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
963 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
964 /// specifies a splat of a single element that is suitable for input to
965 /// VSPLTB/VSPLTH/VSPLTW.
966 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
967 assert(N->getValueType(0) == MVT::v16i8 &&
968 (EltSize == 1 || EltSize == 2 || EltSize == 4));
970 // This is a splat operation if each element of the permute is the same, and
971 // if the value doesn't reference the second vector.
972 unsigned ElementBase = N->getMaskElt(0);
974 // FIXME: Handle UNDEF elements too!
975 if (ElementBase >= 16)
978 // Check that the indices are consecutive, in the case of a multi-byte element
979 // splatted with a v16i8 mask.
980 for (unsigned i = 1; i != EltSize; ++i)
981 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
984 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
985 if (N->getMaskElt(i) < 0) continue;
986 for (unsigned j = 0; j != EltSize; ++j)
987 if (N->getMaskElt(i+j) != N->getMaskElt(j))
993 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
995 bool PPC::isAllNegativeZeroVector(SDNode *N) {
996 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
998 APInt APVal, APUndef;
1002 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1003 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1004 return CFP->getValueAPF().isNegZero();
1009 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1010 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1011 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
1012 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1013 assert(isSplatShuffleMask(SVOp, EltSize));
1014 return SVOp->getMaskElt(0) / EltSize;
1017 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1018 /// by using a vspltis[bhw] instruction of the specified element size, return
1019 /// the constant being splatted. The ByteSize field indicates the number of
1020 /// bytes of each element [124] -> [bhw].
1021 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1022 SDValue OpVal(0, 0);
1024 // If ByteSize of the splat is bigger than the element size of the
1025 // build_vector, then we have a case where we are checking for a splat where
1026 // multiple elements of the buildvector are folded together into a single
1027 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1028 unsigned EltSize = 16/N->getNumOperands();
1029 if (EltSize < ByteSize) {
1030 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1031 SDValue UniquedVals[4];
1032 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1034 // See if all of the elements in the buildvector agree across.
1035 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1036 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1037 // If the element isn't a constant, bail fully out.
1038 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1041 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
1042 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1043 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1044 return SDValue(); // no match.
1047 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1048 // either constant or undef values that are identical for each chunk. See
1049 // if these chunks can form into a larger vspltis*.
1051 // Check to see if all of the leading entries are either 0 or -1. If
1052 // neither, then this won't fit into the immediate field.
1053 bool LeadingZero = true;
1054 bool LeadingOnes = true;
1055 for (unsigned i = 0; i != Multiple-1; ++i) {
1056 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
1058 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1059 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1061 // Finally, check the least significant entry.
1063 if (UniquedVals[Multiple-1].getNode() == 0)
1064 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1065 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1067 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1070 if (UniquedVals[Multiple-1].getNode() == 0)
1071 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1072 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1073 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1074 return DAG.getTargetConstant(Val, MVT::i32);
1080 // Check to see if this buildvec has a single non-undef value in its elements.
1081 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1082 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1083 if (OpVal.getNode() == 0)
1084 OpVal = N->getOperand(i);
1085 else if (OpVal != N->getOperand(i))
1089 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
1091 unsigned ValSizeInBytes = EltSize;
1093 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1094 Value = CN->getZExtValue();
1095 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1096 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1097 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1100 // If the splat value is larger than the element value, then we can never do
1101 // this splat. The only case that we could fit the replicated bits into our
1102 // immediate field for would be zero, and we prefer to use vxor for it.
1103 if (ValSizeInBytes < ByteSize) return SDValue();
1105 // If the element value is larger than the splat value, cut it in half and
1106 // check to see if the two halves are equal. Continue doing this until we
1107 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1108 while (ValSizeInBytes > ByteSize) {
1109 ValSizeInBytes >>= 1;
1111 // If the top half equals the bottom half, we're still ok.
1112 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1113 (Value & ((1 << (8*ValSizeInBytes))-1)))
1117 // Properly sign extend the value.
1118 int MaskVal = SignExtend32(Value, ByteSize * 8);
1120 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1121 if (MaskVal == 0) return SDValue();
1123 // Finally, if this value fits in a 5 bit sext field, return it
1124 if (SignExtend32<5>(MaskVal) == MaskVal)
1125 return DAG.getTargetConstant(MaskVal, MVT::i32);
1129 //===----------------------------------------------------------------------===//
1130 // Addressing Mode Selection
1131 //===----------------------------------------------------------------------===//
1133 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1134 /// or 64-bit immediate, and if the value can be accurately represented as a
1135 /// sign extension from a 16-bit value. If so, this returns true and the
1137 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1138 if (N->getOpcode() != ISD::Constant)
1141 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1142 if (N->getValueType(0) == MVT::i32)
1143 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1145 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1147 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1148 return isIntS16Immediate(Op.getNode(), Imm);
1152 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1153 /// can be represented as an indexed [r+r] operation. Returns false if it
1154 /// can be more efficiently represented with [r+imm].
1155 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1157 SelectionDAG &DAG) const {
1159 if (N.getOpcode() == ISD::ADD) {
1160 if (isIntS16Immediate(N.getOperand(1), imm))
1161 return false; // r+i
1162 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1163 return false; // r+i
1165 Base = N.getOperand(0);
1166 Index = N.getOperand(1);
1168 } else if (N.getOpcode() == ISD::OR) {
1169 if (isIntS16Immediate(N.getOperand(1), imm))
1170 return false; // r+i can fold it if we can.
1172 // If this is an or of disjoint bitfields, we can codegen this as an add
1173 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1175 APInt LHSKnownZero, LHSKnownOne;
1176 APInt RHSKnownZero, RHSKnownOne;
1177 DAG.ComputeMaskedBits(N.getOperand(0),
1178 LHSKnownZero, LHSKnownOne);
1180 if (LHSKnownZero.getBoolValue()) {
1181 DAG.ComputeMaskedBits(N.getOperand(1),
1182 RHSKnownZero, RHSKnownOne);
1183 // If all of the bits are known zero on the LHS or RHS, the add won't
1185 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1186 Base = N.getOperand(0);
1187 Index = N.getOperand(1);
1196 // If we happen to be doing an i64 load or store into a stack slot that has
1197 // less than a 4-byte alignment, then the frame-index elimination may need to
1198 // use an indexed load or store instruction (because the offset may not be a
1199 // multiple of 4). The extra register needed to hold the offset comes from the
1200 // register scavenger, and it is possible that the scavenger will need to use
1201 // an emergency spill slot. As a result, we need to make sure that a spill slot
1202 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1204 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1205 // FIXME: This does not handle the LWA case.
1209 // NOTE: We'll exclude negative FIs here, which come from argument
1210 // lowering, because there are no known test cases triggering this problem
1211 // using packed structures (or similar). We can remove this exclusion if
1212 // we find such a test case. The reason why this is so test-case driven is
1213 // because this entire 'fixup' is only to prevent crashes (from the
1214 // register scavenger) on not-really-valid inputs. For example, if we have:
1216 // %b = bitcast i1* %a to i64*
1217 // store i64* a, i64 b
1218 // then the store should really be marked as 'align 1', but is not. If it
1219 // were marked as 'align 1' then the indexed form would have been
1220 // instruction-selected initially, and the problem this 'fixup' is preventing
1221 // won't happen regardless.
1225 MachineFunction &MF = DAG.getMachineFunction();
1226 MachineFrameInfo *MFI = MF.getFrameInfo();
1228 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1232 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1233 FuncInfo->setHasNonRISpills();
1236 /// Returns true if the address N can be represented by a base register plus
1237 /// a signed 16-bit displacement [r+imm], and if it is not better
1238 /// represented as reg+reg. If Aligned is true, only accept displacements
1239 /// suitable for STD and friends, i.e. multiples of 4.
1240 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1243 bool Aligned) const {
1244 // FIXME dl should come from parent load or store, not from address
1246 // If this can be more profitably realized as r+r, fail.
1247 if (SelectAddressRegReg(N, Disp, Base, DAG))
1250 if (N.getOpcode() == ISD::ADD) {
1252 if (isIntS16Immediate(N.getOperand(1), imm) &&
1253 (!Aligned || (imm & 3) == 0)) {
1254 Disp = DAG.getTargetConstant(imm, N.getValueType());
1255 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1256 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1257 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1259 Base = N.getOperand(0);
1261 return true; // [r+i]
1262 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1263 // Match LOAD (ADD (X, Lo(G))).
1264 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1265 && "Cannot handle constant offsets yet!");
1266 Disp = N.getOperand(1).getOperand(0); // The global address.
1267 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1268 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1269 Disp.getOpcode() == ISD::TargetConstantPool ||
1270 Disp.getOpcode() == ISD::TargetJumpTable);
1271 Base = N.getOperand(0);
1272 return true; // [&g+r]
1274 } else if (N.getOpcode() == ISD::OR) {
1276 if (isIntS16Immediate(N.getOperand(1), imm) &&
1277 (!Aligned || (imm & 3) == 0)) {
1278 // If this is an or of disjoint bitfields, we can codegen this as an add
1279 // (for better address arithmetic) if the LHS and RHS of the OR are
1280 // provably disjoint.
1281 APInt LHSKnownZero, LHSKnownOne;
1282 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1284 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1285 // If all of the bits are known zero on the LHS or RHS, the add won't
1287 Base = N.getOperand(0);
1288 Disp = DAG.getTargetConstant(imm, N.getValueType());
1292 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1293 // Loading from a constant address.
1295 // If this address fits entirely in a 16-bit sext immediate field, codegen
1298 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1299 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1300 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1301 CN->getValueType(0));
1305 // Handle 32-bit sext immediates with LIS + addr mode.
1306 if ((CN->getValueType(0) == MVT::i32 ||
1307 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1308 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1309 int Addr = (int)CN->getZExtValue();
1311 // Otherwise, break this down into an LIS + disp.
1312 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1314 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1315 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1316 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1321 Disp = DAG.getTargetConstant(0, getPointerTy());
1322 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1323 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1324 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1327 return true; // [r+0]
1330 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1331 /// represented as an indexed [r+r] operation.
1332 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1334 SelectionDAG &DAG) const {
1335 // Check to see if we can easily represent this as an [r+r] address. This
1336 // will fail if it thinks that the address is more profitably represented as
1337 // reg+imm, e.g. where imm = 0.
1338 if (SelectAddressRegReg(N, Base, Index, DAG))
1341 // If the operand is an addition, always emit this as [r+r], since this is
1342 // better (for code size, and execution, as the memop does the add for free)
1343 // than emitting an explicit add.
1344 if (N.getOpcode() == ISD::ADD) {
1345 Base = N.getOperand(0);
1346 Index = N.getOperand(1);
1350 // Otherwise, do it the hard way, using R0 as the base register.
1351 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1357 /// getPreIndexedAddressParts - returns true by value, base pointer and
1358 /// offset pointer and addressing mode by reference if the node's address
1359 /// can be legally represented as pre-indexed load / store address.
1360 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1362 ISD::MemIndexedMode &AM,
1363 SelectionDAG &DAG) const {
1364 if (DisablePPCPreinc) return false;
1370 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1371 Ptr = LD->getBasePtr();
1372 VT = LD->getMemoryVT();
1373 Alignment = LD->getAlignment();
1374 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1375 Ptr = ST->getBasePtr();
1376 VT = ST->getMemoryVT();
1377 Alignment = ST->getAlignment();
1382 // PowerPC doesn't have preinc load/store instructions for vectors.
1386 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1388 // Common code will reject creating a pre-inc form if the base pointer
1389 // is a frame index, or if N is a store and the base pointer is either
1390 // the same as or a predecessor of the value being stored. Check for
1391 // those situations here, and try with swapped Base/Offset instead.
1394 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1397 SDValue Val = cast<StoreSDNode>(N)->getValue();
1398 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1403 std::swap(Base, Offset);
1409 // LDU/STU can only handle immediates that are a multiple of 4.
1410 if (VT != MVT::i64) {
1411 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1414 // LDU/STU need an address with at least 4-byte alignment.
1418 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1422 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1423 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1424 // sext i32 to i64 when addr mode is r+i.
1425 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1426 LD->getExtensionType() == ISD::SEXTLOAD &&
1427 isa<ConstantSDNode>(Offset))
1435 //===----------------------------------------------------------------------===//
1436 // LowerOperation implementation
1437 //===----------------------------------------------------------------------===//
1439 /// GetLabelAccessInfo - Return true if we should reference labels using a
1440 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1441 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1442 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1443 HiOpFlags = PPCII::MO_HA;
1444 LoOpFlags = PPCII::MO_LO;
1446 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1447 // non-darwin platform. We don't support PIC on other platforms yet.
1448 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1449 TM.getSubtarget<PPCSubtarget>().isDarwin();
1451 HiOpFlags |= PPCII::MO_PIC_FLAG;
1452 LoOpFlags |= PPCII::MO_PIC_FLAG;
1455 // If this is a reference to a global value that requires a non-lazy-ptr, make
1456 // sure that instruction lowering adds it.
1457 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1458 HiOpFlags |= PPCII::MO_NLP_FLAG;
1459 LoOpFlags |= PPCII::MO_NLP_FLAG;
1461 if (GV->hasHiddenVisibility()) {
1462 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1463 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1470 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1471 SelectionDAG &DAG) {
1472 EVT PtrVT = HiPart.getValueType();
1473 SDValue Zero = DAG.getConstant(0, PtrVT);
1476 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1477 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1479 // With PIC, the first instruction is actually "GR+hi(&G)".
1481 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1482 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1484 // Generate non-pic code that has direct accesses to the constant pool.
1485 // The address of the global is just (hi(&g)+lo(&g)).
1486 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1489 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1490 SelectionDAG &DAG) const {
1491 EVT PtrVT = Op.getValueType();
1492 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1493 const Constant *C = CP->getConstVal();
1495 // 64-bit SVR4 ABI code is always position-independent.
1496 // The actual address of the GlobalValue is stored in the TOC.
1497 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1498 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1499 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1500 DAG.getRegister(PPC::X2, MVT::i64));
1503 unsigned MOHiFlag, MOLoFlag;
1504 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1506 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1508 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1509 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1512 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1513 EVT PtrVT = Op.getValueType();
1514 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1516 // 64-bit SVR4 ABI code is always position-independent.
1517 // The actual address of the GlobalValue is stored in the TOC.
1518 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1519 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1520 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1521 DAG.getRegister(PPC::X2, MVT::i64));
1524 unsigned MOHiFlag, MOLoFlag;
1525 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1526 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1527 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1528 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1531 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1532 SelectionDAG &DAG) const {
1533 EVT PtrVT = Op.getValueType();
1535 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1537 unsigned MOHiFlag, MOLoFlag;
1538 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1539 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1540 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1541 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1544 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1545 SelectionDAG &DAG) const {
1547 // FIXME: TLS addresses currently use medium model code sequences,
1548 // which is the most useful form. Eventually support for small and
1549 // large models could be added if users need it, at the cost of
1550 // additional complexity.
1551 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1553 const GlobalValue *GV = GA->getGlobal();
1554 EVT PtrVT = getPointerTy();
1555 bool is64bit = PPCSubTarget.isPPC64();
1557 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1559 if (Model == TLSModel::LocalExec) {
1560 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1561 PPCII::MO_TPREL_HA);
1562 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1563 PPCII::MO_TPREL_LO);
1564 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1565 is64bit ? MVT::i64 : MVT::i32);
1566 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1567 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1570 if (Model == TLSModel::InitialExec) {
1571 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1572 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1576 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1577 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1578 PtrVT, GOTReg, TGA);
1580 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1581 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1582 PtrVT, TGA, GOTPtr);
1583 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1586 if (Model == TLSModel::GeneralDynamic) {
1587 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1588 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1589 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1591 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1594 // We need a chain node, and don't have one handy. The underlying
1595 // call has no side effects, so using the function entry node
1597 SDValue Chain = DAG.getEntryNode();
1598 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1599 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1600 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1601 PtrVT, ParmReg, TGA);
1602 // The return value from GET_TLS_ADDR really is in X3 already, but
1603 // some hacks are needed here to tie everything together. The extra
1604 // copies dissolve during subsequent transforms.
1605 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1606 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1609 if (Model == TLSModel::LocalDynamic) {
1610 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1611 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1612 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1614 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1617 // We need a chain node, and don't have one handy. The underlying
1618 // call has no side effects, so using the function entry node
1620 SDValue Chain = DAG.getEntryNode();
1621 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1622 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1623 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1624 PtrVT, ParmReg, TGA);
1625 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1626 // some hacks are needed here to tie everything together. The extra
1627 // copies dissolve during subsequent transforms.
1628 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1629 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1630 Chain, ParmReg, TGA);
1631 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1634 llvm_unreachable("Unknown TLS model!");
1637 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1638 SelectionDAG &DAG) const {
1639 EVT PtrVT = Op.getValueType();
1640 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1642 const GlobalValue *GV = GSDN->getGlobal();
1644 // 64-bit SVR4 ABI code is always position-independent.
1645 // The actual address of the GlobalValue is stored in the TOC.
1646 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1647 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1648 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1649 DAG.getRegister(PPC::X2, MVT::i64));
1652 unsigned MOHiFlag, MOLoFlag;
1653 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1656 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1658 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1660 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1662 // If the global reference is actually to a non-lazy-pointer, we have to do an
1663 // extra load to get the address of the global.
1664 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1665 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1666 false, false, false, 0);
1670 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1671 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1674 if (Op.getValueType() == MVT::v2i64) {
1675 // When the operands themselves are v2i64 values, we need to do something
1676 // special because VSX has no underlying comparison operations for these.
1677 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1678 // Equality can be handled by casting to the legal type for Altivec
1679 // comparisons, everything else needs to be expanded.
1680 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1681 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1682 DAG.getSetCC(dl, MVT::v4i32,
1683 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1684 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1691 // We handle most of these in the usual way.
1695 // If we're comparing for equality to zero, expose the fact that this is
1696 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1697 // fold the new nodes.
1698 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1699 if (C->isNullValue() && CC == ISD::SETEQ) {
1700 EVT VT = Op.getOperand(0).getValueType();
1701 SDValue Zext = Op.getOperand(0);
1702 if (VT.bitsLT(MVT::i32)) {
1704 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1706 unsigned Log2b = Log2_32(VT.getSizeInBits());
1707 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1708 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1709 DAG.getConstant(Log2b, MVT::i32));
1710 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1712 // Leave comparisons against 0 and -1 alone for now, since they're usually
1713 // optimized. FIXME: revisit this when we can custom lower all setcc
1715 if (C->isAllOnesValue() || C->isNullValue())
1719 // If we have an integer seteq/setne, turn it into a compare against zero
1720 // by xor'ing the rhs with the lhs, which is faster than setting a
1721 // condition register, reading it back out, and masking the correct bit. The
1722 // normal approach here uses sub to do this instead of xor. Using xor exposes
1723 // the result to other bit-twiddling opportunities.
1724 EVT LHSVT = Op.getOperand(0).getValueType();
1725 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1726 EVT VT = Op.getValueType();
1727 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1729 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1734 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1735 const PPCSubtarget &Subtarget) const {
1736 SDNode *Node = Op.getNode();
1737 EVT VT = Node->getValueType(0);
1738 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1739 SDValue InChain = Node->getOperand(0);
1740 SDValue VAListPtr = Node->getOperand(1);
1741 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1744 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1747 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1748 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1750 InChain = GprIndex.getValue(1);
1752 if (VT == MVT::i64) {
1753 // Check if GprIndex is even
1754 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1755 DAG.getConstant(1, MVT::i32));
1756 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1757 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1758 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1759 DAG.getConstant(1, MVT::i32));
1760 // Align GprIndex to be even if it isn't
1761 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1765 // fpr index is 1 byte after gpr
1766 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1767 DAG.getConstant(1, MVT::i32));
1770 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1771 FprPtr, MachinePointerInfo(SV), MVT::i8,
1773 InChain = FprIndex.getValue(1);
1775 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1776 DAG.getConstant(8, MVT::i32));
1778 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1779 DAG.getConstant(4, MVT::i32));
1782 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1783 MachinePointerInfo(), false, false,
1785 InChain = OverflowArea.getValue(1);
1787 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1788 MachinePointerInfo(), false, false,
1790 InChain = RegSaveArea.getValue(1);
1792 // select overflow_area if index > 8
1793 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1794 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1796 // adjustment constant gpr_index * 4/8
1797 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1798 VT.isInteger() ? GprIndex : FprIndex,
1799 DAG.getConstant(VT.isInteger() ? 4 : 8,
1802 // OurReg = RegSaveArea + RegConstant
1803 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1806 // Floating types are 32 bytes into RegSaveArea
1807 if (VT.isFloatingPoint())
1808 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1809 DAG.getConstant(32, MVT::i32));
1811 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1812 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1813 VT.isInteger() ? GprIndex : FprIndex,
1814 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1817 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1818 VT.isInteger() ? VAListPtr : FprPtr,
1819 MachinePointerInfo(SV),
1820 MVT::i8, false, false, 0);
1822 // determine if we should load from reg_save_area or overflow_area
1823 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1825 // increase overflow_area by 4/8 if gpr/fpr > 8
1826 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1827 DAG.getConstant(VT.isInteger() ? 4 : 8,
1830 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1833 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1835 MachinePointerInfo(),
1836 MVT::i32, false, false, 0);
1838 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1839 false, false, false, 0);
1842 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1843 const PPCSubtarget &Subtarget) const {
1844 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1846 // We have to copy the entire va_list struct:
1847 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1848 return DAG.getMemcpy(Op.getOperand(0), Op,
1849 Op.getOperand(1), Op.getOperand(2),
1850 DAG.getConstant(12, MVT::i32), 8, false, true,
1851 MachinePointerInfo(), MachinePointerInfo());
1854 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1855 SelectionDAG &DAG) const {
1856 return Op.getOperand(0);
1859 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1860 SelectionDAG &DAG) const {
1861 SDValue Chain = Op.getOperand(0);
1862 SDValue Trmp = Op.getOperand(1); // trampoline
1863 SDValue FPtr = Op.getOperand(2); // nested function
1864 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1867 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1868 bool isPPC64 = (PtrVT == MVT::i64);
1870 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1873 TargetLowering::ArgListTy Args;
1874 TargetLowering::ArgListEntry Entry;
1876 Entry.Ty = IntPtrTy;
1877 Entry.Node = Trmp; Args.push_back(Entry);
1879 // TrampSize == (isPPC64 ? 48 : 40);
1880 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1881 isPPC64 ? MVT::i64 : MVT::i32);
1882 Args.push_back(Entry);
1884 Entry.Node = FPtr; Args.push_back(Entry);
1885 Entry.Node = Nest; Args.push_back(Entry);
1887 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1888 TargetLowering::CallLoweringInfo CLI(Chain,
1889 Type::getVoidTy(*DAG.getContext()),
1890 false, false, false, false, 0,
1892 /*isTailCall=*/false,
1893 /*doesNotRet=*/false,
1894 /*isReturnValueUsed=*/true,
1895 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1897 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1899 return CallResult.second;
1902 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1903 const PPCSubtarget &Subtarget) const {
1904 MachineFunction &MF = DAG.getMachineFunction();
1905 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1909 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1910 // vastart just stores the address of the VarArgsFrameIndex slot into the
1911 // memory location argument.
1912 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1913 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1914 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1915 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1916 MachinePointerInfo(SV),
1920 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1921 // We suppose the given va_list is already allocated.
1924 // char gpr; /* index into the array of 8 GPRs
1925 // * stored in the register save area
1926 // * gpr=0 corresponds to r3,
1927 // * gpr=1 to r4, etc.
1929 // char fpr; /* index into the array of 8 FPRs
1930 // * stored in the register save area
1931 // * fpr=0 corresponds to f1,
1932 // * fpr=1 to f2, etc.
1934 // char *overflow_arg_area;
1935 // /* location on stack that holds
1936 // * the next overflow argument
1938 // char *reg_save_area;
1939 // /* where r3:r10 and f1:f8 (if saved)
1945 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1946 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1949 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1951 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1953 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1956 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1957 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1959 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1960 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1962 uint64_t FPROffset = 1;
1963 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1965 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1967 // Store first byte : number of int regs
1968 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1970 MachinePointerInfo(SV),
1971 MVT::i8, false, false, 0);
1972 uint64_t nextOffset = FPROffset;
1973 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1976 // Store second byte : number of float regs
1977 SDValue secondStore =
1978 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1979 MachinePointerInfo(SV, nextOffset), MVT::i8,
1981 nextOffset += StackOffset;
1982 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1984 // Store second word : arguments given on stack
1985 SDValue thirdStore =
1986 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1987 MachinePointerInfo(SV, nextOffset),
1989 nextOffset += FrameOffset;
1990 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1992 // Store third word : arguments given in registers
1993 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1994 MachinePointerInfo(SV, nextOffset),
1999 #include "PPCGenCallingConv.inc"
2001 // Function whose sole purpose is to kill compiler warnings
2002 // stemming from unused functions included from PPCGenCallingConv.inc.
2003 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2004 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2007 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2008 CCValAssign::LocInfo &LocInfo,
2009 ISD::ArgFlagsTy &ArgFlags,
2014 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2016 CCValAssign::LocInfo &LocInfo,
2017 ISD::ArgFlagsTy &ArgFlags,
2019 static const MCPhysReg ArgRegs[] = {
2020 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2021 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2023 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2025 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2027 // Skip one register if the first unallocated register has an even register
2028 // number and there are still argument registers available which have not been
2029 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2030 // need to skip a register if RegNum is odd.
2031 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2032 State.AllocateReg(ArgRegs[RegNum]);
2035 // Always return false here, as this function only makes sure that the first
2036 // unallocated register has an odd register number and does not actually
2037 // allocate a register for the current argument.
2041 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2043 CCValAssign::LocInfo &LocInfo,
2044 ISD::ArgFlagsTy &ArgFlags,
2046 static const MCPhysReg ArgRegs[] = {
2047 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2051 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2053 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2055 // If there is only one Floating-point register left we need to put both f64
2056 // values of a split ppc_fp128 value on the stack.
2057 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2058 State.AllocateReg(ArgRegs[RegNum]);
2061 // Always return false here, as this function only makes sure that the two f64
2062 // values a ppc_fp128 value is split into are both passed in registers or both
2063 // passed on the stack and does not actually allocate a register for the
2064 // current argument.
2068 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2070 static const MCPhysReg *GetFPR() {
2071 static const MCPhysReg FPR[] = {
2072 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2073 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2079 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2081 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2082 unsigned PtrByteSize) {
2083 unsigned ArgSize = ArgVT.getStoreSize();
2084 if (Flags.isByVal())
2085 ArgSize = Flags.getByValSize();
2086 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2092 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2093 CallingConv::ID CallConv, bool isVarArg,
2094 const SmallVectorImpl<ISD::InputArg>
2096 SDLoc dl, SelectionDAG &DAG,
2097 SmallVectorImpl<SDValue> &InVals)
2099 if (PPCSubTarget.isSVR4ABI()) {
2100 if (PPCSubTarget.isPPC64())
2101 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2104 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2107 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2113 PPCTargetLowering::LowerFormalArguments_32SVR4(
2115 CallingConv::ID CallConv, bool isVarArg,
2116 const SmallVectorImpl<ISD::InputArg>
2118 SDLoc dl, SelectionDAG &DAG,
2119 SmallVectorImpl<SDValue> &InVals) const {
2121 // 32-bit SVR4 ABI Stack Frame Layout:
2122 // +-----------------------------------+
2123 // +--> | Back chain |
2124 // | +-----------------------------------+
2125 // | | Floating-point register save area |
2126 // | +-----------------------------------+
2127 // | | General register save area |
2128 // | +-----------------------------------+
2129 // | | CR save word |
2130 // | +-----------------------------------+
2131 // | | VRSAVE save word |
2132 // | +-----------------------------------+
2133 // | | Alignment padding |
2134 // | +-----------------------------------+
2135 // | | Vector register save area |
2136 // | +-----------------------------------+
2137 // | | Local variable space |
2138 // | +-----------------------------------+
2139 // | | Parameter list area |
2140 // | +-----------------------------------+
2141 // | | LR save word |
2142 // | +-----------------------------------+
2143 // SP--> +--- | Back chain |
2144 // +-----------------------------------+
2147 // System V Application Binary Interface PowerPC Processor Supplement
2148 // AltiVec Technology Programming Interface Manual
2150 MachineFunction &MF = DAG.getMachineFunction();
2151 MachineFrameInfo *MFI = MF.getFrameInfo();
2152 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2154 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2155 // Potential tail calls could cause overwriting of argument stack slots.
2156 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2157 (CallConv == CallingConv::Fast));
2158 unsigned PtrByteSize = 4;
2160 // Assign locations to all of the incoming arguments.
2161 SmallVector<CCValAssign, 16> ArgLocs;
2162 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2163 getTargetMachine(), ArgLocs, *DAG.getContext());
2165 // Reserve space for the linkage area on the stack.
2166 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2168 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2170 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2171 CCValAssign &VA = ArgLocs[i];
2173 // Arguments stored in registers.
2174 if (VA.isRegLoc()) {
2175 const TargetRegisterClass *RC;
2176 EVT ValVT = VA.getValVT();
2178 switch (ValVT.getSimpleVT().SimpleTy) {
2180 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2183 RC = &PPC::GPRCRegClass;
2186 RC = &PPC::F4RCRegClass;
2189 if (PPCSubTarget.hasVSX())
2190 RC = &PPC::VSFRCRegClass;
2192 RC = &PPC::F8RCRegClass;
2198 RC = &PPC::VRRCRegClass;
2202 RC = &PPC::VSHRCRegClass;
2206 // Transform the arguments stored in physical registers into virtual ones.
2207 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2208 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2209 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2211 if (ValVT == MVT::i1)
2212 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2214 InVals.push_back(ArgValue);
2216 // Argument stored in memory.
2217 assert(VA.isMemLoc());
2219 unsigned ArgSize = VA.getLocVT().getStoreSize();
2220 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2223 // Create load nodes to retrieve arguments from the stack.
2224 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2225 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2226 MachinePointerInfo(),
2227 false, false, false, 0));
2231 // Assign locations to all of the incoming aggregate by value arguments.
2232 // Aggregates passed by value are stored in the local variable space of the
2233 // caller's stack frame, right above the parameter list area.
2234 SmallVector<CCValAssign, 16> ByValArgLocs;
2235 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2236 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2238 // Reserve stack space for the allocations in CCInfo.
2239 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2241 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2243 // Area that is at least reserved in the caller of this function.
2244 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2246 // Set the size that is at least reserved in caller of this function. Tail
2247 // call optimized function's reserved stack space needs to be aligned so that
2248 // taking the difference between two stack areas will result in an aligned
2250 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2253 std::max(MinReservedArea,
2254 PPCFrameLowering::getMinCallFrameSize(false, false));
2256 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2257 getStackAlignment();
2258 unsigned AlignMask = TargetAlign-1;
2259 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2261 FI->setMinReservedArea(MinReservedArea);
2263 SmallVector<SDValue, 8> MemOps;
2265 // If the function takes variable number of arguments, make a frame index for
2266 // the start of the first vararg value... for expansion of llvm.va_start.
2268 static const MCPhysReg GPArgRegs[] = {
2269 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2270 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2272 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2274 static const MCPhysReg FPArgRegs[] = {
2275 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2278 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2280 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2282 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2285 // Make room for NumGPArgRegs and NumFPArgRegs.
2286 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2287 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2289 FuncInfo->setVarArgsStackOffset(
2290 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2291 CCInfo.getNextStackOffset(), true));
2293 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2294 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2296 // The fixed integer arguments of a variadic function are stored to the
2297 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2298 // the result of va_next.
2299 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2300 // Get an existing live-in vreg, or add a new one.
2301 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2303 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2305 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2306 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2307 MachinePointerInfo(), false, false, 0);
2308 MemOps.push_back(Store);
2309 // Increment the address by four for the next argument to store
2310 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2311 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2314 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2316 // The double arguments are stored to the VarArgsFrameIndex
2318 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2319 // Get an existing live-in vreg, or add a new one.
2320 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2322 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2324 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2325 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2326 MachinePointerInfo(), false, false, 0);
2327 MemOps.push_back(Store);
2328 // Increment the address by eight for the next argument to store
2329 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2331 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2335 if (!MemOps.empty())
2336 Chain = DAG.getNode(ISD::TokenFactor, dl,
2337 MVT::Other, &MemOps[0], MemOps.size());
2342 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2343 // value to MVT::i64 and then truncate to the correct register size.
2345 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2346 SelectionDAG &DAG, SDValue ArgVal,
2349 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2350 DAG.getValueType(ObjectVT));
2351 else if (Flags.isZExt())
2352 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2353 DAG.getValueType(ObjectVT));
2355 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2358 // Set the size that is at least reserved in caller of this function. Tail
2359 // call optimized functions' reserved stack space needs to be aligned so that
2360 // taking the difference between two stack areas will result in an aligned
2363 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2364 unsigned nAltivecParamsAtEnd,
2365 unsigned MinReservedArea,
2366 bool isPPC64) const {
2367 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2368 // Add the Altivec parameters at the end, if needed.
2369 if (nAltivecParamsAtEnd) {
2370 MinReservedArea = ((MinReservedArea+15)/16)*16;
2371 MinReservedArea += 16*nAltivecParamsAtEnd;
2374 std::max(MinReservedArea,
2375 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2376 unsigned TargetAlign
2377 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2378 getStackAlignment();
2379 unsigned AlignMask = TargetAlign-1;
2380 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2381 FI->setMinReservedArea(MinReservedArea);
2385 PPCTargetLowering::LowerFormalArguments_64SVR4(
2387 CallingConv::ID CallConv, bool isVarArg,
2388 const SmallVectorImpl<ISD::InputArg>
2390 SDLoc dl, SelectionDAG &DAG,
2391 SmallVectorImpl<SDValue> &InVals) const {
2392 // TODO: add description of PPC stack frame format, or at least some docs.
2394 MachineFunction &MF = DAG.getMachineFunction();
2395 MachineFrameInfo *MFI = MF.getFrameInfo();
2396 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2398 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2399 // Potential tail calls could cause overwriting of argument stack slots.
2400 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2401 (CallConv == CallingConv::Fast));
2402 unsigned PtrByteSize = 8;
2404 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2405 // Area that is at least reserved in caller of this function.
2406 unsigned MinReservedArea = ArgOffset;
2408 static const MCPhysReg GPR[] = {
2409 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2410 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2413 static const MCPhysReg *FPR = GetFPR();
2415 static const MCPhysReg VR[] = {
2416 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2417 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2419 static const MCPhysReg VSRH[] = {
2420 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2421 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2424 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2425 const unsigned Num_FPR_Regs = 13;
2426 const unsigned Num_VR_Regs = array_lengthof(VR);
2428 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2430 // Add DAG nodes to load the arguments or copy them out of registers. On
2431 // entry to a function on PPC, the arguments start after the linkage area,
2432 // although the first ones are often in registers.
2434 SmallVector<SDValue, 8> MemOps;
2435 unsigned nAltivecParamsAtEnd = 0;
2436 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2437 unsigned CurArgIdx = 0;
2438 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2440 bool needsLoad = false;
2441 EVT ObjectVT = Ins[ArgNo].VT;
2442 unsigned ObjSize = ObjectVT.getStoreSize();
2443 unsigned ArgSize = ObjSize;
2444 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2445 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2446 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2448 unsigned CurArgOffset = ArgOffset;
2450 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2451 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2452 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8 ||
2453 ObjectVT==MVT::v2f64 || ObjectVT==MVT::v2i64) {
2455 MinReservedArea = ((MinReservedArea+15)/16)*16;
2456 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2460 nAltivecParamsAtEnd++;
2462 // Calculate min reserved area.
2463 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2467 // FIXME the codegen can be much improved in some cases.
2468 // We do not have to keep everything in memory.
2469 if (Flags.isByVal()) {
2470 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2471 ObjSize = Flags.getByValSize();
2472 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2473 // Empty aggregate parameters do not take up registers. Examples:
2477 // etc. However, we have to provide a place-holder in InVals, so
2478 // pretend we have an 8-byte item at the current address for that
2481 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2482 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2483 InVals.push_back(FIN);
2487 unsigned BVAlign = Flags.getByValAlign();
2489 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2490 CurArgOffset = ArgOffset;
2493 // All aggregates smaller than 8 bytes must be passed right-justified.
2494 if (ObjSize < PtrByteSize)
2495 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2496 // The value of the object is its address.
2497 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2498 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2499 InVals.push_back(FIN);
2502 if (GPR_idx != Num_GPR_Regs) {
2503 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2504 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2507 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2508 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2509 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2510 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2511 MachinePointerInfo(FuncArg),
2512 ObjType, false, false, 0);
2514 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2515 // store the whole register as-is to the parameter save area
2516 // slot. The address of the parameter was already calculated
2517 // above (InVals.push_back(FIN)) to be the right-justified
2518 // offset within the slot. For this store, we need a new
2519 // frame index that points at the beginning of the slot.
2520 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2521 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2522 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2523 MachinePointerInfo(FuncArg),
2527 MemOps.push_back(Store);
2530 // Whether we copied from a register or not, advance the offset
2531 // into the parameter save area by a full doubleword.
2532 ArgOffset += PtrByteSize;
2536 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2537 // Store whatever pieces of the object are in registers
2538 // to memory. ArgOffset will be the address of the beginning
2540 if (GPR_idx != Num_GPR_Regs) {
2542 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2543 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2544 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2545 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2546 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2547 MachinePointerInfo(FuncArg, j),
2549 MemOps.push_back(Store);
2551 ArgOffset += PtrByteSize;
2553 ArgOffset += ArgSize - j;
2560 switch (ObjectVT.getSimpleVT().SimpleTy) {
2561 default: llvm_unreachable("Unhandled argument type!");
2565 if (GPR_idx != Num_GPR_Regs) {
2566 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2567 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2569 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2570 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2571 // value to MVT::i64 and then truncate to the correct register size.
2572 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2577 ArgSize = PtrByteSize;
2584 // Every 8 bytes of argument space consumes one of the GPRs available for
2585 // argument passing.
2586 if (GPR_idx != Num_GPR_Regs) {
2589 if (FPR_idx != Num_FPR_Regs) {
2592 if (ObjectVT == MVT::f32)
2593 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2595 VReg = MF.addLiveIn(FPR[FPR_idx], PPCSubTarget.hasVSX() ?
2596 &PPC::VSFRCRegClass :
2597 &PPC::F8RCRegClass);
2599 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2603 ArgSize = PtrByteSize;
2614 // Note that vector arguments in registers don't reserve stack space,
2615 // except in varargs functions.
2616 if (VR_idx != Num_VR_Regs) {
2617 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2618 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2619 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2620 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2622 while ((ArgOffset % 16) != 0) {
2623 ArgOffset += PtrByteSize;
2624 if (GPR_idx != Num_GPR_Regs)
2628 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2632 // Vectors are aligned.
2633 ArgOffset = ((ArgOffset+15)/16)*16;
2634 CurArgOffset = ArgOffset;
2641 // We need to load the argument to a virtual register if we determined
2642 // above that we ran out of physical registers of the appropriate type.
2644 int FI = MFI->CreateFixedObject(ObjSize,
2645 CurArgOffset + (ArgSize - ObjSize),
2647 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2648 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2649 false, false, false, 0);
2652 InVals.push_back(ArgVal);
2655 // Set the size that is at least reserved in caller of this function. Tail
2656 // call optimized functions' reserved stack space needs to be aligned so that
2657 // taking the difference between two stack areas will result in an aligned
2659 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2661 // If the function takes variable number of arguments, make a frame index for
2662 // the start of the first vararg value... for expansion of llvm.va_start.
2664 int Depth = ArgOffset;
2666 FuncInfo->setVarArgsFrameIndex(
2667 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2668 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2670 // If this function is vararg, store any remaining integer argument regs
2671 // to their spots on the stack so that they may be loaded by deferencing the
2672 // result of va_next.
2673 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2674 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2675 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2676 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2677 MachinePointerInfo(), false, false, 0);
2678 MemOps.push_back(Store);
2679 // Increment the address by four for the next argument to store
2680 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2681 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2685 if (!MemOps.empty())
2686 Chain = DAG.getNode(ISD::TokenFactor, dl,
2687 MVT::Other, &MemOps[0], MemOps.size());
2693 PPCTargetLowering::LowerFormalArguments_Darwin(
2695 CallingConv::ID CallConv, bool isVarArg,
2696 const SmallVectorImpl<ISD::InputArg>
2698 SDLoc dl, SelectionDAG &DAG,
2699 SmallVectorImpl<SDValue> &InVals) const {
2700 // TODO: add description of PPC stack frame format, or at least some docs.
2702 MachineFunction &MF = DAG.getMachineFunction();
2703 MachineFrameInfo *MFI = MF.getFrameInfo();
2704 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2706 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2707 bool isPPC64 = PtrVT == MVT::i64;
2708 // Potential tail calls could cause overwriting of argument stack slots.
2709 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2710 (CallConv == CallingConv::Fast));
2711 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2713 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2714 // Area that is at least reserved in caller of this function.
2715 unsigned MinReservedArea = ArgOffset;
2717 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2718 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2719 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2721 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2722 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2723 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2726 static const MCPhysReg *FPR = GetFPR();
2728 static const MCPhysReg VR[] = {
2729 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2730 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2733 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2734 const unsigned Num_FPR_Regs = 13;
2735 const unsigned Num_VR_Regs = array_lengthof( VR);
2737 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2739 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2741 // In 32-bit non-varargs functions, the stack space for vectors is after the
2742 // stack space for non-vectors. We do not use this space unless we have
2743 // too many vectors to fit in registers, something that only occurs in
2744 // constructed examples:), but we have to walk the arglist to figure
2745 // that out...for the pathological case, compute VecArgOffset as the
2746 // start of the vector parameter area. Computing VecArgOffset is the
2747 // entire point of the following loop.
2748 unsigned VecArgOffset = ArgOffset;
2749 if (!isVarArg && !isPPC64) {
2750 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2752 EVT ObjectVT = Ins[ArgNo].VT;
2753 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2755 if (Flags.isByVal()) {
2756 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2757 unsigned ObjSize = Flags.getByValSize();
2759 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2760 VecArgOffset += ArgSize;
2764 switch(ObjectVT.getSimpleVT().SimpleTy) {
2765 default: llvm_unreachable("Unhandled argument type!");
2771 case MVT::i64: // PPC64
2773 // FIXME: We are guaranteed to be !isPPC64 at this point.
2774 // Does MVT::i64 apply?
2781 // Nothing to do, we're only looking at Nonvector args here.
2786 // We've found where the vector parameter area in memory is. Skip the
2787 // first 12 parameters; these don't use that memory.
2788 VecArgOffset = ((VecArgOffset+15)/16)*16;
2789 VecArgOffset += 12*16;
2791 // Add DAG nodes to load the arguments or copy them out of registers. On
2792 // entry to a function on PPC, the arguments start after the linkage area,
2793 // although the first ones are often in registers.
2795 SmallVector<SDValue, 8> MemOps;
2796 unsigned nAltivecParamsAtEnd = 0;
2797 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2798 unsigned CurArgIdx = 0;
2799 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2801 bool needsLoad = false;
2802 EVT ObjectVT = Ins[ArgNo].VT;
2803 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2804 unsigned ArgSize = ObjSize;
2805 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2806 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2807 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2809 unsigned CurArgOffset = ArgOffset;
2811 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2812 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2813 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2814 if (isVarArg || isPPC64) {
2815 MinReservedArea = ((MinReservedArea+15)/16)*16;
2816 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2819 } else nAltivecParamsAtEnd++;
2821 // Calculate min reserved area.
2822 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2826 // FIXME the codegen can be much improved in some cases.
2827 // We do not have to keep everything in memory.
2828 if (Flags.isByVal()) {
2829 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2830 ObjSize = Flags.getByValSize();
2831 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2832 // Objects of size 1 and 2 are right justified, everything else is
2833 // left justified. This means the memory address is adjusted forwards.
2834 if (ObjSize==1 || ObjSize==2) {
2835 CurArgOffset = CurArgOffset + (4 - ObjSize);
2837 // The value of the object is its address.
2838 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2839 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2840 InVals.push_back(FIN);
2841 if (ObjSize==1 || ObjSize==2) {
2842 if (GPR_idx != Num_GPR_Regs) {
2845 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2847 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2848 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2849 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2850 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2851 MachinePointerInfo(FuncArg),
2852 ObjType, false, false, 0);
2853 MemOps.push_back(Store);
2857 ArgOffset += PtrByteSize;
2861 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2862 // Store whatever pieces of the object are in registers
2863 // to memory. ArgOffset will be the address of the beginning
2865 if (GPR_idx != Num_GPR_Regs) {
2868 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2870 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2871 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2872 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2873 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2874 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2875 MachinePointerInfo(FuncArg, j),
2877 MemOps.push_back(Store);
2879 ArgOffset += PtrByteSize;
2881 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2888 switch (ObjectVT.getSimpleVT().SimpleTy) {
2889 default: llvm_unreachable("Unhandled argument type!");
2893 if (GPR_idx != Num_GPR_Regs) {
2894 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2895 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2897 if (ObjectVT == MVT::i1)
2898 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2903 ArgSize = PtrByteSize;
2905 // All int arguments reserve stack space in the Darwin ABI.
2906 ArgOffset += PtrByteSize;
2910 case MVT::i64: // PPC64
2911 if (GPR_idx != Num_GPR_Regs) {
2912 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2913 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2915 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2916 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2917 // value to MVT::i64 and then truncate to the correct register size.
2918 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2923 ArgSize = PtrByteSize;
2925 // All int arguments reserve stack space in the Darwin ABI.
2931 // Every 4 bytes of argument space consumes one of the GPRs available for
2932 // argument passing.
2933 if (GPR_idx != Num_GPR_Regs) {
2935 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2938 if (FPR_idx != Num_FPR_Regs) {
2941 if (ObjectVT == MVT::f32)
2942 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2944 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2946 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2952 // All FP arguments reserve stack space in the Darwin ABI.
2953 ArgOffset += isPPC64 ? 8 : ObjSize;
2959 // Note that vector arguments in registers don't reserve stack space,
2960 // except in varargs functions.
2961 if (VR_idx != Num_VR_Regs) {
2962 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2963 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2965 while ((ArgOffset % 16) != 0) {
2966 ArgOffset += PtrByteSize;
2967 if (GPR_idx != Num_GPR_Regs)
2971 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2975 if (!isVarArg && !isPPC64) {
2976 // Vectors go after all the nonvectors.
2977 CurArgOffset = VecArgOffset;
2980 // Vectors are aligned.
2981 ArgOffset = ((ArgOffset+15)/16)*16;
2982 CurArgOffset = ArgOffset;
2990 // We need to load the argument to a virtual register if we determined above
2991 // that we ran out of physical registers of the appropriate type.
2993 int FI = MFI->CreateFixedObject(ObjSize,
2994 CurArgOffset + (ArgSize - ObjSize),
2996 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2997 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2998 false, false, false, 0);
3001 InVals.push_back(ArgVal);
3004 // Set the size that is at least reserved in caller of this function. Tail
3005 // call optimized functions' reserved stack space needs to be aligned so that
3006 // taking the difference between two stack areas will result in an aligned
3008 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
3010 // If the function takes variable number of arguments, make a frame index for
3011 // the start of the first vararg value... for expansion of llvm.va_start.
3013 int Depth = ArgOffset;
3015 FuncInfo->setVarArgsFrameIndex(
3016 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3018 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3020 // If this function is vararg, store any remaining integer argument regs
3021 // to their spots on the stack so that they may be loaded by deferencing the
3022 // result of va_next.
3023 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3027 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3029 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3031 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3032 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3033 MachinePointerInfo(), false, false, 0);
3034 MemOps.push_back(Store);
3035 // Increment the address by four for the next argument to store
3036 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3037 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3041 if (!MemOps.empty())
3042 Chain = DAG.getNode(ISD::TokenFactor, dl,
3043 MVT::Other, &MemOps[0], MemOps.size());
3048 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
3049 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
3051 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
3055 const SmallVectorImpl<ISD::OutputArg>
3057 const SmallVectorImpl<SDValue> &OutVals,
3058 unsigned &nAltivecParamsAtEnd) {
3059 // Count how many bytes are to be pushed on the stack, including the linkage
3060 // area, and parameter passing area. We start with 24/48 bytes, which is
3061 // prereserved space for [SP][CR][LR][3 x unused].
3062 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
3063 unsigned NumOps = Outs.size();
3064 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3066 // Add up all the space actually used.
3067 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
3068 // they all go in registers, but we must reserve stack space for them for
3069 // possible use by the caller. In varargs or 64-bit calls, parameters are
3070 // assigned stack space in order, with padding so Altivec parameters are
3072 nAltivecParamsAtEnd = 0;
3073 for (unsigned i = 0; i != NumOps; ++i) {
3074 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3075 EVT ArgVT = Outs[i].VT;
3076 // Varargs Altivec parameters are padded to a 16 byte boundary.
3077 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
3078 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8 ||
3079 ArgVT==MVT::v2f64 || ArgVT==MVT::v2i64) {
3080 if (!isVarArg && !isPPC64) {
3081 // Non-varargs Altivec parameters go after all the non-Altivec
3082 // parameters; handle those later so we know how much padding we need.
3083 nAltivecParamsAtEnd++;
3086 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
3087 NumBytes = ((NumBytes+15)/16)*16;
3089 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3092 // Allow for Altivec parameters at the end, if needed.
3093 if (nAltivecParamsAtEnd) {
3094 NumBytes = ((NumBytes+15)/16)*16;
3095 NumBytes += 16*nAltivecParamsAtEnd;
3098 // The prolog code of the callee may store up to 8 GPR argument registers to
3099 // the stack, allowing va_start to index over them in memory if its varargs.
3100 // Because we cannot tell if this is needed on the caller side, we have to
3101 // conservatively assume that it is needed. As such, make sure we have at
3102 // least enough stack space for the caller to store the 8 GPRs.
3103 NumBytes = std::max(NumBytes,
3104 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
3106 // Tail call needs the stack to be aligned.
3107 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
3108 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
3109 getFrameLowering()->getStackAlignment();
3110 unsigned AlignMask = TargetAlign-1;
3111 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3117 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3118 /// adjusted to accommodate the arguments for the tailcall.
3119 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3120 unsigned ParamSize) {
3122 if (!isTailCall) return 0;
3124 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3125 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3126 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3127 // Remember only if the new adjustement is bigger.
3128 if (SPDiff < FI->getTailCallSPDelta())
3129 FI->setTailCallSPDelta(SPDiff);
3134 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3135 /// for tail call optimization. Targets which want to do tail call
3136 /// optimization should implement this function.
3138 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3139 CallingConv::ID CalleeCC,
3141 const SmallVectorImpl<ISD::InputArg> &Ins,
3142 SelectionDAG& DAG) const {
3143 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3146 // Variable argument functions are not supported.
3150 MachineFunction &MF = DAG.getMachineFunction();
3151 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3152 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3153 // Functions containing by val parameters are not supported.
3154 for (unsigned i = 0; i != Ins.size(); i++) {
3155 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3156 if (Flags.isByVal()) return false;
3159 // Non-PIC/GOT tail calls are supported.
3160 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3163 // At the moment we can only do local tail calls (in same module, hidden
3164 // or protected) if we are generating PIC.
3165 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3166 return G->getGlobal()->hasHiddenVisibility()
3167 || G->getGlobal()->hasProtectedVisibility();
3173 /// isCallCompatibleAddress - Return the immediate to use if the specified
3174 /// 32-bit value is representable in the immediate field of a BxA instruction.
3175 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3176 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3179 int Addr = C->getZExtValue();
3180 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3181 SignExtend32<26>(Addr) != Addr)
3182 return 0; // Top 6 bits have to be sext of immediate.
3184 return DAG.getConstant((int)C->getZExtValue() >> 2,
3185 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3190 struct TailCallArgumentInfo {
3195 TailCallArgumentInfo() : FrameIdx(0) {}
3200 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3202 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3204 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3205 SmallVectorImpl<SDValue> &MemOpChains,
3207 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3208 SDValue Arg = TailCallArgs[i].Arg;
3209 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3210 int FI = TailCallArgs[i].FrameIdx;
3211 // Store relative to framepointer.
3212 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3213 MachinePointerInfo::getFixedStack(FI),
3218 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3219 /// the appropriate stack slot for the tail call optimized function call.
3220 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3221 MachineFunction &MF,
3230 // Calculate the new stack slot for the return address.
3231 int SlotSize = isPPC64 ? 8 : 4;
3232 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3234 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3235 NewRetAddrLoc, true);
3236 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3237 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3238 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3239 MachinePointerInfo::getFixedStack(NewRetAddr),
3242 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3243 // slot as the FP is never overwritten.
3246 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3247 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3249 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3250 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3251 MachinePointerInfo::getFixedStack(NewFPIdx),
3258 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3259 /// the position of the argument.
3261 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3262 SDValue Arg, int SPDiff, unsigned ArgOffset,
3263 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3264 int Offset = ArgOffset + SPDiff;
3265 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3266 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3267 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3268 SDValue FIN = DAG.getFrameIndex(FI, VT);
3269 TailCallArgumentInfo Info;
3271 Info.FrameIdxOp = FIN;
3273 TailCallArguments.push_back(Info);
3276 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3277 /// stack slot. Returns the chain as result and the loaded frame pointers in
3278 /// LROpOut/FPOpout. Used when tail calling.
3279 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3287 // Load the LR and FP stack slot for later adjusting.
3288 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3289 LROpOut = getReturnAddrFrameIndex(DAG);
3290 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3291 false, false, false, 0);
3292 Chain = SDValue(LROpOut.getNode(), 1);
3294 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3295 // slot as the FP is never overwritten.
3297 FPOpOut = getFramePointerFrameIndex(DAG);
3298 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3299 false, false, false, 0);
3300 Chain = SDValue(FPOpOut.getNode(), 1);
3306 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3307 /// by "Src" to address "Dst" of size "Size". Alignment information is
3308 /// specified by the specific parameter attribute. The copy will be passed as
3309 /// a byval function parameter.
3310 /// Sometimes what we are copying is the end of a larger object, the part that
3311 /// does not fit in registers.
3313 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3314 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3316 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3317 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3318 false, false, MachinePointerInfo(0),
3319 MachinePointerInfo(0));
3322 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3325 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3326 SDValue Arg, SDValue PtrOff, int SPDiff,
3327 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3328 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3329 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3331 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3336 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3338 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3339 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3340 DAG.getConstant(ArgOffset, PtrVT));
3342 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3343 MachinePointerInfo(), false, false, 0));
3344 // Calculate and remember argument location.
3345 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3350 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3351 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3352 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3353 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3354 MachineFunction &MF = DAG.getMachineFunction();
3356 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3357 // might overwrite each other in case of tail call optimization.
3358 SmallVector<SDValue, 8> MemOpChains2;
3359 // Do not flag preceding copytoreg stuff together with the following stuff.
3361 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3363 if (!MemOpChains2.empty())
3364 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3365 &MemOpChains2[0], MemOpChains2.size());
3367 // Store the return address to the appropriate stack slot.
3368 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3369 isPPC64, isDarwinABI, dl);
3371 // Emit callseq_end just before tailcall node.
3372 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3373 DAG.getIntPtrConstant(0, true), InFlag, dl);
3374 InFlag = Chain.getValue(1);
3378 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3379 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3380 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3381 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3382 const PPCSubtarget &PPCSubTarget) {
3384 bool isPPC64 = PPCSubTarget.isPPC64();
3385 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3387 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3388 NodeTys.push_back(MVT::Other); // Returns a chain
3389 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3391 unsigned CallOpc = PPCISD::CALL;
3393 bool needIndirectCall = true;
3394 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3395 // If this is an absolute destination address, use the munged value.
3396 Callee = SDValue(Dest, 0);
3397 needIndirectCall = false;
3400 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3401 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3402 // Use indirect calls for ALL functions calls in JIT mode, since the
3403 // far-call stubs may be outside relocation limits for a BL instruction.
3404 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3405 unsigned OpFlags = 0;
3406 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3407 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3408 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3409 (G->getGlobal()->isDeclaration() ||
3410 G->getGlobal()->isWeakForLinker())) {
3411 // PC-relative references to external symbols should go through $stub,
3412 // unless we're building with the leopard linker or later, which
3413 // automatically synthesizes these stubs.
3414 OpFlags = PPCII::MO_DARWIN_STUB;
3417 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3418 // every direct call is) turn it into a TargetGlobalAddress /
3419 // TargetExternalSymbol node so that legalize doesn't hack it.
3420 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3421 Callee.getValueType(),
3423 needIndirectCall = false;
3427 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3428 unsigned char OpFlags = 0;
3430 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3431 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3432 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3433 // PC-relative references to external symbols should go through $stub,
3434 // unless we're building with the leopard linker or later, which
3435 // automatically synthesizes these stubs.
3436 OpFlags = PPCII::MO_DARWIN_STUB;
3439 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3441 needIndirectCall = false;
3444 if (needIndirectCall) {
3445 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3446 // to do the call, we can't use PPCISD::CALL.
3447 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3449 if (isSVR4ABI && isPPC64) {
3450 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3451 // entry point, but to the function descriptor (the function entry point
3452 // address is part of the function descriptor though).
3453 // The function descriptor is a three doubleword structure with the
3454 // following fields: function entry point, TOC base address and
3455 // environment pointer.
3456 // Thus for a call through a function pointer, the following actions need
3458 // 1. Save the TOC of the caller in the TOC save area of its stack
3459 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3460 // 2. Load the address of the function entry point from the function
3462 // 3. Load the TOC of the callee from the function descriptor into r2.
3463 // 4. Load the environment pointer from the function descriptor into
3465 // 5. Branch to the function entry point address.
3466 // 6. On return of the callee, the TOC of the caller needs to be
3467 // restored (this is done in FinishCall()).
3469 // All those operations are flagged together to ensure that no other
3470 // operations can be scheduled in between. E.g. without flagging the
3471 // operations together, a TOC access in the caller could be scheduled
3472 // between the load of the callee TOC and the branch to the callee, which
3473 // results in the TOC access going through the TOC of the callee instead
3474 // of going through the TOC of the caller, which leads to incorrect code.
3476 // Load the address of the function entry point from the function
3478 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3479 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3480 InFlag.getNode() ? 3 : 2);
3481 Chain = LoadFuncPtr.getValue(1);
3482 InFlag = LoadFuncPtr.getValue(2);
3484 // Load environment pointer into r11.
3485 // Offset of the environment pointer within the function descriptor.
3486 SDValue PtrOff = DAG.getIntPtrConstant(16);
3488 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3489 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3491 Chain = LoadEnvPtr.getValue(1);
3492 InFlag = LoadEnvPtr.getValue(2);
3494 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3496 Chain = EnvVal.getValue(0);
3497 InFlag = EnvVal.getValue(1);
3499 // Load TOC of the callee into r2. We are using a target-specific load
3500 // with r2 hard coded, because the result of a target-independent load
3501 // would never go directly into r2, since r2 is a reserved register (which
3502 // prevents the register allocator from allocating it), resulting in an
3503 // additional register being allocated and an unnecessary move instruction
3505 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3506 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3508 Chain = LoadTOCPtr.getValue(0);
3509 InFlag = LoadTOCPtr.getValue(1);
3511 MTCTROps[0] = Chain;
3512 MTCTROps[1] = LoadFuncPtr;
3513 MTCTROps[2] = InFlag;
3516 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3517 2 + (InFlag.getNode() != 0));
3518 InFlag = Chain.getValue(1);
3521 NodeTys.push_back(MVT::Other);
3522 NodeTys.push_back(MVT::Glue);
3523 Ops.push_back(Chain);
3524 CallOpc = PPCISD::BCTRL;
3526 // Add use of X11 (holding environment pointer)
3527 if (isSVR4ABI && isPPC64)
3528 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3529 // Add CTR register as callee so a bctr can be emitted later.
3531 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3534 // If this is a direct call, pass the chain and the callee.
3535 if (Callee.getNode()) {
3536 Ops.push_back(Chain);
3537 Ops.push_back(Callee);
3539 // If this is a tail call add stack pointer delta.
3541 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3543 // Add argument registers to the end of the list so that they are known live
3545 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3546 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3547 RegsToPass[i].second.getValueType()));
3553 bool isLocalCall(const SDValue &Callee)
3555 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3556 return !G->getGlobal()->isDeclaration() &&
3557 !G->getGlobal()->isWeakForLinker();
3562 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3563 CallingConv::ID CallConv, bool isVarArg,
3564 const SmallVectorImpl<ISD::InputArg> &Ins,
3565 SDLoc dl, SelectionDAG &DAG,
3566 SmallVectorImpl<SDValue> &InVals) const {
3568 SmallVector<CCValAssign, 16> RVLocs;
3569 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3570 getTargetMachine(), RVLocs, *DAG.getContext());
3571 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3573 // Copy all of the result registers out of their specified physreg.
3574 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3575 CCValAssign &VA = RVLocs[i];
3576 assert(VA.isRegLoc() && "Can only return in registers!");
3578 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3579 VA.getLocReg(), VA.getLocVT(), InFlag);
3580 Chain = Val.getValue(1);
3581 InFlag = Val.getValue(2);
3583 switch (VA.getLocInfo()) {
3584 default: llvm_unreachable("Unknown loc info!");
3585 case CCValAssign::Full: break;
3586 case CCValAssign::AExt:
3587 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3589 case CCValAssign::ZExt:
3590 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3591 DAG.getValueType(VA.getValVT()));
3592 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3594 case CCValAssign::SExt:
3595 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3596 DAG.getValueType(VA.getValVT()));
3597 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3601 InVals.push_back(Val);
3608 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3609 bool isTailCall, bool isVarArg,
3611 SmallVector<std::pair<unsigned, SDValue>, 8>
3613 SDValue InFlag, SDValue Chain,
3615 int SPDiff, unsigned NumBytes,
3616 const SmallVectorImpl<ISD::InputArg> &Ins,
3617 SmallVectorImpl<SDValue> &InVals) const {
3618 std::vector<EVT> NodeTys;
3619 SmallVector<SDValue, 8> Ops;
3620 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3621 isTailCall, RegsToPass, Ops, NodeTys,
3624 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3625 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3626 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3628 // When performing tail call optimization the callee pops its arguments off
3629 // the stack. Account for this here so these bytes can be pushed back on in
3630 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3631 int BytesCalleePops =
3632 (CallConv == CallingConv::Fast &&
3633 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3635 // Add a register mask operand representing the call-preserved registers.
3636 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3637 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3638 assert(Mask && "Missing call preserved mask for calling convention");
3639 Ops.push_back(DAG.getRegisterMask(Mask));
3641 if (InFlag.getNode())
3642 Ops.push_back(InFlag);
3646 assert(((Callee.getOpcode() == ISD::Register &&
3647 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3648 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3649 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3650 isa<ConstantSDNode>(Callee)) &&
3651 "Expecting an global address, external symbol, absolute value or register");
3653 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3656 // Add a NOP immediately after the branch instruction when using the 64-bit
3657 // SVR4 ABI. At link time, if caller and callee are in a different module and
3658 // thus have a different TOC, the call will be replaced with a call to a stub
3659 // function which saves the current TOC, loads the TOC of the callee and
3660 // branches to the callee. The NOP will be replaced with a load instruction
3661 // which restores the TOC of the caller from the TOC save slot of the current
3662 // stack frame. If caller and callee belong to the same module (and have the
3663 // same TOC), the NOP will remain unchanged.
3665 bool needsTOCRestore = false;
3666 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3667 if (CallOpc == PPCISD::BCTRL) {
3668 // This is a call through a function pointer.
3669 // Restore the caller TOC from the save area into R2.
3670 // See PrepareCall() for more information about calls through function
3671 // pointers in the 64-bit SVR4 ABI.
3672 // We are using a target-specific load with r2 hard coded, because the
3673 // result of a target-independent load would never go directly into r2,
3674 // since r2 is a reserved register (which prevents the register allocator
3675 // from allocating it), resulting in an additional register being
3676 // allocated and an unnecessary move instruction being generated.
3677 needsTOCRestore = true;
3678 } else if ((CallOpc == PPCISD::CALL) &&
3679 (!isLocalCall(Callee) ||
3680 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3681 // Otherwise insert NOP for non-local calls.
3682 CallOpc = PPCISD::CALL_NOP;
3686 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3687 InFlag = Chain.getValue(1);
3689 if (needsTOCRestore) {
3690 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3691 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3692 InFlag = Chain.getValue(1);
3695 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3696 DAG.getIntPtrConstant(BytesCalleePops, true),
3699 InFlag = Chain.getValue(1);
3701 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3702 Ins, dl, DAG, InVals);
3706 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3707 SmallVectorImpl<SDValue> &InVals) const {
3708 SelectionDAG &DAG = CLI.DAG;
3710 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3711 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3712 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3713 SDValue Chain = CLI.Chain;
3714 SDValue Callee = CLI.Callee;
3715 bool &isTailCall = CLI.IsTailCall;
3716 CallingConv::ID CallConv = CLI.CallConv;
3717 bool isVarArg = CLI.IsVarArg;
3720 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3723 if (PPCSubTarget.isSVR4ABI()) {
3724 if (PPCSubTarget.isPPC64())
3725 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3726 isTailCall, Outs, OutVals, Ins,
3729 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3730 isTailCall, Outs, OutVals, Ins,
3734 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3735 isTailCall, Outs, OutVals, Ins,
3740 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3741 CallingConv::ID CallConv, bool isVarArg,
3743 const SmallVectorImpl<ISD::OutputArg> &Outs,
3744 const SmallVectorImpl<SDValue> &OutVals,
3745 const SmallVectorImpl<ISD::InputArg> &Ins,
3746 SDLoc dl, SelectionDAG &DAG,
3747 SmallVectorImpl<SDValue> &InVals) const {
3748 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3749 // of the 32-bit SVR4 ABI stack frame layout.
3751 assert((CallConv == CallingConv::C ||
3752 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3754 unsigned PtrByteSize = 4;
3756 MachineFunction &MF = DAG.getMachineFunction();
3758 // Mark this function as potentially containing a function that contains a
3759 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3760 // and restoring the callers stack pointer in this functions epilog. This is
3761 // done because by tail calling the called function might overwrite the value
3762 // in this function's (MF) stack pointer stack slot 0(SP).
3763 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3764 CallConv == CallingConv::Fast)
3765 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3767 // Count how many bytes are to be pushed on the stack, including the linkage
3768 // area, parameter list area and the part of the local variable space which
3769 // contains copies of aggregates which are passed by value.
3771 // Assign locations to all of the outgoing arguments.
3772 SmallVector<CCValAssign, 16> ArgLocs;
3773 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3774 getTargetMachine(), ArgLocs, *DAG.getContext());
3776 // Reserve space for the linkage area on the stack.
3777 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3780 // Handle fixed and variable vector arguments differently.
3781 // Fixed vector arguments go into registers as long as registers are
3782 // available. Variable vector arguments always go into memory.
3783 unsigned NumArgs = Outs.size();
3785 for (unsigned i = 0; i != NumArgs; ++i) {
3786 MVT ArgVT = Outs[i].VT;
3787 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3790 if (Outs[i].IsFixed) {
3791 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3794 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3800 errs() << "Call operand #" << i << " has unhandled type "
3801 << EVT(ArgVT).getEVTString() << "\n";
3803 llvm_unreachable(0);
3807 // All arguments are treated the same.
3808 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3811 // Assign locations to all of the outgoing aggregate by value arguments.
3812 SmallVector<CCValAssign, 16> ByValArgLocs;
3813 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3814 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3816 // Reserve stack space for the allocations in CCInfo.
3817 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3819 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3821 // Size of the linkage area, parameter list area and the part of the local
3822 // space variable where copies of aggregates which are passed by value are
3824 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3826 // Calculate by how many bytes the stack has to be adjusted in case of tail
3827 // call optimization.
3828 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3830 // Adjust the stack pointer for the new arguments...
3831 // These operations are automatically eliminated by the prolog/epilog pass
3832 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3834 SDValue CallSeqStart = Chain;
3836 // Load the return address and frame pointer so it can be moved somewhere else
3839 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3842 // Set up a copy of the stack pointer for use loading and storing any
3843 // arguments that may not fit in the registers available for argument
3845 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3847 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3848 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3849 SmallVector<SDValue, 8> MemOpChains;
3851 bool seenFloatArg = false;
3852 // Walk the register/memloc assignments, inserting copies/loads.
3853 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3856 CCValAssign &VA = ArgLocs[i];
3857 SDValue Arg = OutVals[i];
3858 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3860 if (Flags.isByVal()) {
3861 // Argument is an aggregate which is passed by value, thus we need to
3862 // create a copy of it in the local variable space of the current stack
3863 // frame (which is the stack frame of the caller) and pass the address of
3864 // this copy to the callee.
3865 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3866 CCValAssign &ByValVA = ByValArgLocs[j++];
3867 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3869 // Memory reserved in the local variable space of the callers stack frame.
3870 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3872 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3873 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3875 // Create a copy of the argument in the local area of the current
3877 SDValue MemcpyCall =
3878 CreateCopyOfByValArgument(Arg, PtrOff,
3879 CallSeqStart.getNode()->getOperand(0),
3882 // This must go outside the CALLSEQ_START..END.
3883 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3884 CallSeqStart.getNode()->getOperand(1),
3886 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3887 NewCallSeqStart.getNode());
3888 Chain = CallSeqStart = NewCallSeqStart;
3890 // Pass the address of the aggregate copy on the stack either in a
3891 // physical register or in the parameter list area of the current stack
3892 // frame to the callee.
3896 if (VA.isRegLoc()) {
3897 if (Arg.getValueType() == MVT::i1)
3898 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3900 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3901 // Put argument in a physical register.
3902 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3904 // Put argument in the parameter list area of the current stack frame.
3905 assert(VA.isMemLoc());
3906 unsigned LocMemOffset = VA.getLocMemOffset();
3909 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3910 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3912 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3913 MachinePointerInfo(),
3916 // Calculate and remember argument location.
3917 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3923 if (!MemOpChains.empty())
3924 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3925 &MemOpChains[0], MemOpChains.size());
3927 // Build a sequence of copy-to-reg nodes chained together with token chain
3928 // and flag operands which copy the outgoing args into the appropriate regs.
3930 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3931 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3932 RegsToPass[i].second, InFlag);
3933 InFlag = Chain.getValue(1);
3936 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3939 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3940 SDValue Ops[] = { Chain, InFlag };
3942 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3943 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3945 InFlag = Chain.getValue(1);
3949 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3950 false, TailCallArguments);
3952 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3953 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3957 // Copy an argument into memory, being careful to do this outside the
3958 // call sequence for the call to which the argument belongs.
3960 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3961 SDValue CallSeqStart,
3962 ISD::ArgFlagsTy Flags,
3965 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3966 CallSeqStart.getNode()->getOperand(0),
3968 // The MEMCPY must go outside the CALLSEQ_START..END.
3969 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3970 CallSeqStart.getNode()->getOperand(1),
3972 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3973 NewCallSeqStart.getNode());
3974 return NewCallSeqStart;
3978 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3979 CallingConv::ID CallConv, bool isVarArg,
3981 const SmallVectorImpl<ISD::OutputArg> &Outs,
3982 const SmallVectorImpl<SDValue> &OutVals,
3983 const SmallVectorImpl<ISD::InputArg> &Ins,
3984 SDLoc dl, SelectionDAG &DAG,
3985 SmallVectorImpl<SDValue> &InVals) const {
3987 unsigned NumOps = Outs.size();
3989 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3990 unsigned PtrByteSize = 8;
3992 MachineFunction &MF = DAG.getMachineFunction();
3994 // Mark this function as potentially containing a function that contains a
3995 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3996 // and restoring the callers stack pointer in this functions epilog. This is
3997 // done because by tail calling the called function might overwrite the value
3998 // in this function's (MF) stack pointer stack slot 0(SP).
3999 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4000 CallConv == CallingConv::Fast)
4001 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4003 unsigned nAltivecParamsAtEnd = 0;
4005 // Count how many bytes are to be pushed on the stack, including the linkage
4006 // area, and parameter passing area. We start with at least 48 bytes, which
4007 // is reserved space for [SP][CR][LR][3 x unused].
4008 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
4011 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
4012 Outs, OutVals, nAltivecParamsAtEnd);
4014 // Calculate by how many bytes the stack has to be adjusted in case of tail
4015 // call optimization.
4016 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4018 // To protect arguments on the stack from being clobbered in a tail call,
4019 // force all the loads to happen before doing any other lowering.
4021 Chain = DAG.getStackArgumentTokenFactor(Chain);
4023 // Adjust the stack pointer for the new arguments...
4024 // These operations are automatically eliminated by the prolog/epilog pass
4025 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4027 SDValue CallSeqStart = Chain;
4029 // Load the return address and frame pointer so it can be move somewhere else
4032 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4035 // Set up a copy of the stack pointer for use loading and storing any
4036 // arguments that may not fit in the registers available for argument
4038 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4040 // Figure out which arguments are going to go in registers, and which in
4041 // memory. Also, if this is a vararg function, floating point operations
4042 // must be stored to our stack, and loaded into integer regs as well, if
4043 // any integer regs are available for argument passing.
4044 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
4045 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4047 static const MCPhysReg GPR[] = {
4048 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4049 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4051 static const MCPhysReg *FPR = GetFPR();
4053 static const MCPhysReg VR[] = {
4054 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4055 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4057 static const MCPhysReg VSRH[] = {
4058 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4059 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4062 const unsigned NumGPRs = array_lengthof(GPR);
4063 const unsigned NumFPRs = 13;
4064 const unsigned NumVRs = array_lengthof(VR);
4066 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4067 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4069 SmallVector<SDValue, 8> MemOpChains;
4070 for (unsigned i = 0; i != NumOps; ++i) {
4071 SDValue Arg = OutVals[i];
4072 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4074 // PtrOff will be used to store the current argument to the stack if a
4075 // register cannot be found for it.
4078 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4080 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4082 // Promote integers to 64-bit values.
4083 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4084 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4085 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4086 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4089 // FIXME memcpy is used way more than necessary. Correctness first.
4090 // Note: "by value" is code for passing a structure by value, not
4092 if (Flags.isByVal()) {
4093 // Note: Size includes alignment padding, so
4094 // struct x { short a; char b; }
4095 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4096 // These are the proper values we need for right-justifying the
4097 // aggregate in a parameter register.
4098 unsigned Size = Flags.getByValSize();
4100 // An empty aggregate parameter takes up no storage and no
4105 unsigned BVAlign = Flags.getByValAlign();
4107 if (BVAlign % PtrByteSize != 0)
4109 "ByVal alignment is not a multiple of the pointer size");
4111 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
4114 // All aggregates smaller than 8 bytes must be passed right-justified.
4115 if (Size==1 || Size==2 || Size==4) {
4116 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4117 if (GPR_idx != NumGPRs) {
4118 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4119 MachinePointerInfo(), VT,
4121 MemOpChains.push_back(Load.getValue(1));
4122 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4124 ArgOffset += PtrByteSize;
4129 if (GPR_idx == NumGPRs && Size < 8) {
4130 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4131 PtrOff.getValueType());
4132 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4133 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4136 ArgOffset += PtrByteSize;
4139 // Copy entire object into memory. There are cases where gcc-generated
4140 // code assumes it is there, even if it could be put entirely into
4141 // registers. (This is not what the doc says.)
4143 // FIXME: The above statement is likely due to a misunderstanding of the
4144 // documents. All arguments must be copied into the parameter area BY
4145 // THE CALLEE in the event that the callee takes the address of any
4146 // formal argument. That has not yet been implemented. However, it is
4147 // reasonable to use the stack area as a staging area for the register
4150 // Skip this for small aggregates, as we will use the same slot for a
4151 // right-justified copy, below.
4153 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4157 // When a register is available, pass a small aggregate right-justified.
4158 if (Size < 8 && GPR_idx != NumGPRs) {
4159 // The easiest way to get this right-justified in a register
4160 // is to copy the structure into the rightmost portion of a
4161 // local variable slot, then load the whole slot into the
4163 // FIXME: The memcpy seems to produce pretty awful code for
4164 // small aggregates, particularly for packed ones.
4165 // FIXME: It would be preferable to use the slot in the
4166 // parameter save area instead of a new local variable.
4167 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4168 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4169 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4173 // Load the slot into the register.
4174 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4175 MachinePointerInfo(),
4176 false, false, false, 0);
4177 MemOpChains.push_back(Load.getValue(1));
4178 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4180 // Done with this argument.
4181 ArgOffset += PtrByteSize;
4185 // For aggregates larger than PtrByteSize, copy the pieces of the
4186 // object that fit into registers from the parameter save area.
4187 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4188 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4189 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4190 if (GPR_idx != NumGPRs) {
4191 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4192 MachinePointerInfo(),
4193 false, false, false, 0);
4194 MemOpChains.push_back(Load.getValue(1));
4195 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4196 ArgOffset += PtrByteSize;
4198 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4205 switch (Arg.getSimpleValueType().SimpleTy) {
4206 default: llvm_unreachable("Unexpected ValueType for argument!");
4210 if (GPR_idx != NumGPRs) {
4211 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4213 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4214 true, isTailCall, false, MemOpChains,
4215 TailCallArguments, dl);
4217 ArgOffset += PtrByteSize;
4221 if (FPR_idx != NumFPRs) {
4222 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4225 // A single float or an aggregate containing only a single float
4226 // must be passed right-justified in the stack doubleword, and
4227 // in the GPR, if one is available.
4229 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
4230 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4231 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4235 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4236 MachinePointerInfo(), false, false, 0);
4237 MemOpChains.push_back(Store);
4239 // Float varargs are always shadowed in available integer registers
4240 if (GPR_idx != NumGPRs) {
4241 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4242 MachinePointerInfo(), false, false,
4244 MemOpChains.push_back(Load.getValue(1));
4245 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4247 } else if (GPR_idx != NumGPRs)
4248 // If we have any FPRs remaining, we may also have GPRs remaining.
4251 // Single-precision floating-point values are mapped to the
4252 // second (rightmost) word of the stack doubleword.
4253 if (Arg.getValueType() == MVT::f32) {
4254 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4255 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4258 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4259 true, isTailCall, false, MemOpChains,
4260 TailCallArguments, dl);
4271 // These go aligned on the stack, or in the corresponding R registers
4272 // when within range. The Darwin PPC ABI doc claims they also go in
4273 // V registers; in fact gcc does this only for arguments that are
4274 // prototyped, not for those that match the ... We do it for all
4275 // arguments, seems to work.
4276 while (ArgOffset % 16 !=0) {
4277 ArgOffset += PtrByteSize;
4278 if (GPR_idx != NumGPRs)
4281 // We could elide this store in the case where the object fits
4282 // entirely in R registers. Maybe later.
4283 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4284 DAG.getConstant(ArgOffset, PtrVT));
4285 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4286 MachinePointerInfo(), false, false, 0);
4287 MemOpChains.push_back(Store);
4288 if (VR_idx != NumVRs) {
4289 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4290 MachinePointerInfo(),
4291 false, false, false, 0);
4292 MemOpChains.push_back(Load.getValue(1));
4294 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4295 Arg.getSimpleValueType() == MVT::v2i64) ?
4296 VSRH[VR_idx] : VR[VR_idx];
4299 RegsToPass.push_back(std::make_pair(VReg, Load));
4302 for (unsigned i=0; i<16; i+=PtrByteSize) {
4303 if (GPR_idx == NumGPRs)
4305 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4306 DAG.getConstant(i, PtrVT));
4307 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4308 false, false, false, 0);
4309 MemOpChains.push_back(Load.getValue(1));
4310 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4315 // Non-varargs Altivec params generally go in registers, but have
4316 // stack space allocated at the end.
4317 if (VR_idx != NumVRs) {
4318 // Doesn't have GPR space allocated.
4319 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4320 Arg.getSimpleValueType() == MVT::v2i64) ?
4321 VSRH[VR_idx] : VR[VR_idx];
4324 RegsToPass.push_back(std::make_pair(VReg, Arg));
4326 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4327 true, isTailCall, true, MemOpChains,
4328 TailCallArguments, dl);
4335 if (!MemOpChains.empty())
4336 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4337 &MemOpChains[0], MemOpChains.size());
4339 // Check if this is an indirect call (MTCTR/BCTRL).
4340 // See PrepareCall() for more information about calls through function
4341 // pointers in the 64-bit SVR4 ABI.
4343 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4344 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4345 !isBLACompatibleAddress(Callee, DAG)) {
4346 // Load r2 into a virtual register and store it to the TOC save area.
4347 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4348 // TOC save area offset.
4349 SDValue PtrOff = DAG.getIntPtrConstant(40);
4350 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4351 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4353 // R12 must contain the address of an indirect callee. This does not
4354 // mean the MTCTR instruction must use R12; it's easier to model this
4355 // as an extra parameter, so do that.
4356 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4359 // Build a sequence of copy-to-reg nodes chained together with token chain
4360 // and flag operands which copy the outgoing args into the appropriate regs.
4362 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4363 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4364 RegsToPass[i].second, InFlag);
4365 InFlag = Chain.getValue(1);
4369 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4370 FPOp, true, TailCallArguments);
4372 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4373 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4378 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4379 CallingConv::ID CallConv, bool isVarArg,
4381 const SmallVectorImpl<ISD::OutputArg> &Outs,
4382 const SmallVectorImpl<SDValue> &OutVals,
4383 const SmallVectorImpl<ISD::InputArg> &Ins,
4384 SDLoc dl, SelectionDAG &DAG,
4385 SmallVectorImpl<SDValue> &InVals) const {
4387 unsigned NumOps = Outs.size();
4389 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4390 bool isPPC64 = PtrVT == MVT::i64;
4391 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4393 MachineFunction &MF = DAG.getMachineFunction();
4395 // Mark this function as potentially containing a function that contains a
4396 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4397 // and restoring the callers stack pointer in this functions epilog. This is
4398 // done because by tail calling the called function might overwrite the value
4399 // in this function's (MF) stack pointer stack slot 0(SP).
4400 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4401 CallConv == CallingConv::Fast)
4402 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4404 unsigned nAltivecParamsAtEnd = 0;
4406 // Count how many bytes are to be pushed on the stack, including the linkage
4407 // area, and parameter passing area. We start with 24/48 bytes, which is
4408 // prereserved space for [SP][CR][LR][3 x unused].
4410 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4412 nAltivecParamsAtEnd);
4414 // Calculate by how many bytes the stack has to be adjusted in case of tail
4415 // call optimization.
4416 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4418 // To protect arguments on the stack from being clobbered in a tail call,
4419 // force all the loads to happen before doing any other lowering.
4421 Chain = DAG.getStackArgumentTokenFactor(Chain);
4423 // Adjust the stack pointer for the new arguments...
4424 // These operations are automatically eliminated by the prolog/epilog pass
4425 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4427 SDValue CallSeqStart = Chain;
4429 // Load the return address and frame pointer so it can be move somewhere else
4432 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4435 // Set up a copy of the stack pointer for use loading and storing any
4436 // arguments that may not fit in the registers available for argument
4440 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4442 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4444 // Figure out which arguments are going to go in registers, and which in
4445 // memory. Also, if this is a vararg function, floating point operations
4446 // must be stored to our stack, and loaded into integer regs as well, if
4447 // any integer regs are available for argument passing.
4448 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4449 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4451 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4452 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4453 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4455 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4456 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4457 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4459 static const MCPhysReg *FPR = GetFPR();
4461 static const MCPhysReg VR[] = {
4462 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4463 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4465 const unsigned NumGPRs = array_lengthof(GPR_32);
4466 const unsigned NumFPRs = 13;
4467 const unsigned NumVRs = array_lengthof(VR);
4469 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4471 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4472 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4474 SmallVector<SDValue, 8> MemOpChains;
4475 for (unsigned i = 0; i != NumOps; ++i) {
4476 SDValue Arg = OutVals[i];
4477 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4479 // PtrOff will be used to store the current argument to the stack if a
4480 // register cannot be found for it.
4483 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4485 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4487 // On PPC64, promote integers to 64-bit values.
4488 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4489 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4490 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4491 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4494 // FIXME memcpy is used way more than necessary. Correctness first.
4495 // Note: "by value" is code for passing a structure by value, not
4497 if (Flags.isByVal()) {
4498 unsigned Size = Flags.getByValSize();
4499 // Very small objects are passed right-justified. Everything else is
4500 // passed left-justified.
4501 if (Size==1 || Size==2) {
4502 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4503 if (GPR_idx != NumGPRs) {
4504 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4505 MachinePointerInfo(), VT,
4507 MemOpChains.push_back(Load.getValue(1));
4508 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4510 ArgOffset += PtrByteSize;
4512 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4513 PtrOff.getValueType());
4514 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4515 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4518 ArgOffset += PtrByteSize;
4522 // Copy entire object into memory. There are cases where gcc-generated
4523 // code assumes it is there, even if it could be put entirely into
4524 // registers. (This is not what the doc says.)
4525 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4529 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4530 // copy the pieces of the object that fit into registers from the
4531 // parameter save area.
4532 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4533 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4534 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4535 if (GPR_idx != NumGPRs) {
4536 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4537 MachinePointerInfo(),
4538 false, false, false, 0);
4539 MemOpChains.push_back(Load.getValue(1));
4540 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4541 ArgOffset += PtrByteSize;
4543 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4550 switch (Arg.getSimpleValueType().SimpleTy) {
4551 default: llvm_unreachable("Unexpected ValueType for argument!");
4555 if (GPR_idx != NumGPRs) {
4556 if (Arg.getValueType() == MVT::i1)
4557 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4559 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4561 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4562 isPPC64, isTailCall, false, MemOpChains,
4563 TailCallArguments, dl);
4565 ArgOffset += PtrByteSize;
4569 if (FPR_idx != NumFPRs) {
4570 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4573 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4574 MachinePointerInfo(), false, false, 0);
4575 MemOpChains.push_back(Store);
4577 // Float varargs are always shadowed in available integer registers
4578 if (GPR_idx != NumGPRs) {
4579 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4580 MachinePointerInfo(), false, false,
4582 MemOpChains.push_back(Load.getValue(1));
4583 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4585 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4586 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4587 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4588 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4589 MachinePointerInfo(),
4590 false, false, false, 0);
4591 MemOpChains.push_back(Load.getValue(1));
4592 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4595 // If we have any FPRs remaining, we may also have GPRs remaining.
4596 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4598 if (GPR_idx != NumGPRs)
4600 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4601 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4605 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4606 isPPC64, isTailCall, false, MemOpChains,
4607 TailCallArguments, dl);
4611 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4618 // These go aligned on the stack, or in the corresponding R registers
4619 // when within range. The Darwin PPC ABI doc claims they also go in
4620 // V registers; in fact gcc does this only for arguments that are
4621 // prototyped, not for those that match the ... We do it for all
4622 // arguments, seems to work.
4623 while (ArgOffset % 16 !=0) {
4624 ArgOffset += PtrByteSize;
4625 if (GPR_idx != NumGPRs)
4628 // We could elide this store in the case where the object fits
4629 // entirely in R registers. Maybe later.
4630 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4631 DAG.getConstant(ArgOffset, PtrVT));
4632 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4633 MachinePointerInfo(), false, false, 0);
4634 MemOpChains.push_back(Store);
4635 if (VR_idx != NumVRs) {
4636 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4637 MachinePointerInfo(),
4638 false, false, false, 0);
4639 MemOpChains.push_back(Load.getValue(1));
4640 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4643 for (unsigned i=0; i<16; i+=PtrByteSize) {
4644 if (GPR_idx == NumGPRs)
4646 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4647 DAG.getConstant(i, PtrVT));
4648 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4649 false, false, false, 0);
4650 MemOpChains.push_back(Load.getValue(1));
4651 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4656 // Non-varargs Altivec params generally go in registers, but have
4657 // stack space allocated at the end.
4658 if (VR_idx != NumVRs) {
4659 // Doesn't have GPR space allocated.
4660 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4661 } else if (nAltivecParamsAtEnd==0) {
4662 // We are emitting Altivec params in order.
4663 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4664 isPPC64, isTailCall, true, MemOpChains,
4665 TailCallArguments, dl);
4671 // If all Altivec parameters fit in registers, as they usually do,
4672 // they get stack space following the non-Altivec parameters. We
4673 // don't track this here because nobody below needs it.
4674 // If there are more Altivec parameters than fit in registers emit
4676 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4678 // Offset is aligned; skip 1st 12 params which go in V registers.
4679 ArgOffset = ((ArgOffset+15)/16)*16;
4681 for (unsigned i = 0; i != NumOps; ++i) {
4682 SDValue Arg = OutVals[i];
4683 EVT ArgType = Outs[i].VT;
4684 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4685 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4688 // We are emitting Altivec params in order.
4689 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4690 isPPC64, isTailCall, true, MemOpChains,
4691 TailCallArguments, dl);
4698 if (!MemOpChains.empty())
4699 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4700 &MemOpChains[0], MemOpChains.size());
4702 // On Darwin, R12 must contain the address of an indirect callee. This does
4703 // not mean the MTCTR instruction must use R12; it's easier to model this as
4704 // an extra parameter, so do that.
4706 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4707 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4708 !isBLACompatibleAddress(Callee, DAG))
4709 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4710 PPC::R12), Callee));
4712 // Build a sequence of copy-to-reg nodes chained together with token chain
4713 // and flag operands which copy the outgoing args into the appropriate regs.
4715 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4716 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4717 RegsToPass[i].second, InFlag);
4718 InFlag = Chain.getValue(1);
4722 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4723 FPOp, true, TailCallArguments);
4725 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4726 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4731 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4732 MachineFunction &MF, bool isVarArg,
4733 const SmallVectorImpl<ISD::OutputArg> &Outs,
4734 LLVMContext &Context) const {
4735 SmallVector<CCValAssign, 16> RVLocs;
4736 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4738 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4742 PPCTargetLowering::LowerReturn(SDValue Chain,
4743 CallingConv::ID CallConv, bool isVarArg,
4744 const SmallVectorImpl<ISD::OutputArg> &Outs,
4745 const SmallVectorImpl<SDValue> &OutVals,
4746 SDLoc dl, SelectionDAG &DAG) const {
4748 SmallVector<CCValAssign, 16> RVLocs;
4749 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4750 getTargetMachine(), RVLocs, *DAG.getContext());
4751 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4754 SmallVector<SDValue, 4> RetOps(1, Chain);
4756 // Copy the result values into the output registers.
4757 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4758 CCValAssign &VA = RVLocs[i];
4759 assert(VA.isRegLoc() && "Can only return in registers!");
4761 SDValue Arg = OutVals[i];
4763 switch (VA.getLocInfo()) {
4764 default: llvm_unreachable("Unknown loc info!");
4765 case CCValAssign::Full: break;
4766 case CCValAssign::AExt:
4767 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4769 case CCValAssign::ZExt:
4770 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4772 case CCValAssign::SExt:
4773 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4777 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4778 Flag = Chain.getValue(1);
4779 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4782 RetOps[0] = Chain; // Update chain.
4784 // Add the flag if we have it.
4786 RetOps.push_back(Flag);
4788 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4789 &RetOps[0], RetOps.size());
4792 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4793 const PPCSubtarget &Subtarget) const {
4794 // When we pop the dynamic allocation we need to restore the SP link.
4797 // Get the corect type for pointers.
4798 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4800 // Construct the stack pointer operand.
4801 bool isPPC64 = Subtarget.isPPC64();
4802 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4803 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4805 // Get the operands for the STACKRESTORE.
4806 SDValue Chain = Op.getOperand(0);
4807 SDValue SaveSP = Op.getOperand(1);
4809 // Load the old link SP.
4810 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4811 MachinePointerInfo(),
4812 false, false, false, 0);
4814 // Restore the stack pointer.
4815 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4817 // Store the old link SP.
4818 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4825 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4826 MachineFunction &MF = DAG.getMachineFunction();
4827 bool isPPC64 = PPCSubTarget.isPPC64();
4828 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4829 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4831 // Get current frame pointer save index. The users of this index will be
4832 // primarily DYNALLOC instructions.
4833 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4834 int RASI = FI->getReturnAddrSaveIndex();
4836 // If the frame pointer save index hasn't been defined yet.
4838 // Find out what the fix offset of the frame pointer save area.
4839 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4840 // Allocate the frame index for frame pointer save area.
4841 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4843 FI->setReturnAddrSaveIndex(RASI);
4845 return DAG.getFrameIndex(RASI, PtrVT);
4849 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4850 MachineFunction &MF = DAG.getMachineFunction();
4851 bool isPPC64 = PPCSubTarget.isPPC64();
4852 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4853 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4855 // Get current frame pointer save index. The users of this index will be
4856 // primarily DYNALLOC instructions.
4857 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4858 int FPSI = FI->getFramePointerSaveIndex();
4860 // If the frame pointer save index hasn't been defined yet.
4862 // Find out what the fix offset of the frame pointer save area.
4863 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4866 // Allocate the frame index for frame pointer save area.
4867 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4869 FI->setFramePointerSaveIndex(FPSI);
4871 return DAG.getFrameIndex(FPSI, PtrVT);
4874 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4876 const PPCSubtarget &Subtarget) const {
4878 SDValue Chain = Op.getOperand(0);
4879 SDValue Size = Op.getOperand(1);
4882 // Get the corect type for pointers.
4883 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4885 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4886 DAG.getConstant(0, PtrVT), Size);
4887 // Construct a node for the frame pointer save index.
4888 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4889 // Build a DYNALLOC node.
4890 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4891 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4892 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4895 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4896 SelectionDAG &DAG) const {
4898 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4899 DAG.getVTList(MVT::i32, MVT::Other),
4900 Op.getOperand(0), Op.getOperand(1));
4903 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4904 SelectionDAG &DAG) const {
4906 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4907 Op.getOperand(0), Op.getOperand(1));
4910 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4911 assert(Op.getValueType() == MVT::i1 &&
4912 "Custom lowering only for i1 loads");
4914 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4917 LoadSDNode *LD = cast<LoadSDNode>(Op);
4919 SDValue Chain = LD->getChain();
4920 SDValue BasePtr = LD->getBasePtr();
4921 MachineMemOperand *MMO = LD->getMemOperand();
4923 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4924 BasePtr, MVT::i8, MMO);
4925 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4927 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4928 return DAG.getMergeValues(Ops, 2, dl);
4931 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4932 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4933 "Custom lowering only for i1 stores");
4935 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4938 StoreSDNode *ST = cast<StoreSDNode>(Op);
4940 SDValue Chain = ST->getChain();
4941 SDValue BasePtr = ST->getBasePtr();
4942 SDValue Value = ST->getValue();
4943 MachineMemOperand *MMO = ST->getMemOperand();
4945 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4946 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4949 // FIXME: Remove this once the ANDI glue bug is fixed:
4950 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4951 assert(Op.getValueType() == MVT::i1 &&
4952 "Custom lowering only for i1 results");
4955 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
4959 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4961 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4962 // Not FP? Not a fsel.
4963 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4964 !Op.getOperand(2).getValueType().isFloatingPoint())
4967 // We might be able to do better than this under some circumstances, but in
4968 // general, fsel-based lowering of select is a finite-math-only optimization.
4969 // For more information, see section F.3 of the 2.06 ISA specification.
4970 if (!DAG.getTarget().Options.NoInfsFPMath ||
4971 !DAG.getTarget().Options.NoNaNsFPMath)
4974 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4976 EVT ResVT = Op.getValueType();
4977 EVT CmpVT = Op.getOperand(0).getValueType();
4978 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4979 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4982 // If the RHS of the comparison is a 0.0, we don't need to do the
4983 // subtraction at all.
4985 if (isFloatingPointZero(RHS))
4987 default: break; // SETUO etc aren't handled by fsel.
4991 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4992 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4993 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4994 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4995 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4996 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4997 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5000 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5003 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5004 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5005 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5008 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5011 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5012 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5013 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5014 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5019 default: break; // SETUO etc aren't handled by fsel.
5023 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5024 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5025 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5026 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5027 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5028 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5029 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5030 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5033 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5034 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5035 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5036 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5039 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5040 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5041 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5042 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5045 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5046 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5047 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5048 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5051 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5052 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5053 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5054 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5059 // FIXME: Split this code up when LegalizeDAGTypes lands.
5060 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5062 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5063 SDValue Src = Op.getOperand(0);
5064 if (Src.getValueType() == MVT::f32)
5065 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5068 switch (Op.getSimpleValueType().SimpleTy) {
5069 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5071 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5072 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5077 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
5078 "i64 FP_TO_UINT is supported only with FPCVT");
5079 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5085 // Convert the FP value to an int value through memory.
5086 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
5087 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
5088 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5089 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5090 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5092 // Emit a store to the stack slot.
5095 MachineFunction &MF = DAG.getMachineFunction();
5096 MachineMemOperand *MMO =
5097 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5098 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5099 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5100 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
5103 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5104 MPI, false, false, 0);
5106 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5108 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5109 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5110 DAG.getConstant(4, FIPtr.getValueType()));
5111 MPI = MachinePointerInfo();
5114 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5115 false, false, false, 0);
5118 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5119 SelectionDAG &DAG) const {
5121 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5122 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5125 if (Op.getOperand(0).getValueType() == MVT::i1)
5126 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5127 DAG.getConstantFP(1.0, Op.getValueType()),
5128 DAG.getConstantFP(0.0, Op.getValueType()));
5130 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
5131 "UINT_TO_FP is supported only with FPCVT");
5133 // If we have FCFIDS, then use it when converting to single-precision.
5134 // Otherwise, convert to double-precision and then round.
5135 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5136 (Op.getOpcode() == ISD::UINT_TO_FP ?
5137 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5138 (Op.getOpcode() == ISD::UINT_TO_FP ?
5139 PPCISD::FCFIDU : PPCISD::FCFID);
5140 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5141 MVT::f32 : MVT::f64;
5143 if (Op.getOperand(0).getValueType() == MVT::i64) {
5144 SDValue SINT = Op.getOperand(0);
5145 // When converting to single-precision, we actually need to convert
5146 // to double-precision first and then round to single-precision.
5147 // To avoid double-rounding effects during that operation, we have
5148 // to prepare the input operand. Bits that might be truncated when
5149 // converting to double-precision are replaced by a bit that won't
5150 // be lost at this stage, but is below the single-precision rounding
5153 // However, if -enable-unsafe-fp-math is in effect, accept double
5154 // rounding to avoid the extra overhead.
5155 if (Op.getValueType() == MVT::f32 &&
5156 !PPCSubTarget.hasFPCVT() &&
5157 !DAG.getTarget().Options.UnsafeFPMath) {
5159 // Twiddle input to make sure the low 11 bits are zero. (If this
5160 // is the case, we are guaranteed the value will fit into the 53 bit
5161 // mantissa of an IEEE double-precision value without rounding.)
5162 // If any of those low 11 bits were not zero originally, make sure
5163 // bit 12 (value 2048) is set instead, so that the final rounding
5164 // to single-precision gets the correct result.
5165 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5166 SINT, DAG.getConstant(2047, MVT::i64));
5167 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5168 Round, DAG.getConstant(2047, MVT::i64));
5169 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5170 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5171 Round, DAG.getConstant(-2048, MVT::i64));
5173 // However, we cannot use that value unconditionally: if the magnitude
5174 // of the input value is small, the bit-twiddling we did above might
5175 // end up visibly changing the output. Fortunately, in that case, we
5176 // don't need to twiddle bits since the original input will convert
5177 // exactly to double-precision floating-point already. Therefore,
5178 // construct a conditional to use the original value if the top 11
5179 // bits are all sign-bit copies, and use the rounded value computed
5181 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5182 SINT, DAG.getConstant(53, MVT::i32));
5183 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5184 Cond, DAG.getConstant(1, MVT::i64));
5185 Cond = DAG.getSetCC(dl, MVT::i32,
5186 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5188 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5191 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5192 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5194 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
5195 FP = DAG.getNode(ISD::FP_ROUND, dl,
5196 MVT::f32, FP, DAG.getIntPtrConstant(0));
5200 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5201 "Unhandled INT_TO_FP type in custom expander!");
5202 // Since we only generate this in 64-bit mode, we can take advantage of
5203 // 64-bit registers. In particular, sign extend the input value into the
5204 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5205 // then lfd it and fcfid it.
5206 MachineFunction &MF = DAG.getMachineFunction();
5207 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5208 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5211 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
5212 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5213 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5215 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5216 MachinePointerInfo::getFixedStack(FrameIdx),
5219 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5220 "Expected an i32 store");
5221 MachineMemOperand *MMO =
5222 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5223 MachineMemOperand::MOLoad, 4, 4);
5224 SDValue Ops[] = { Store, FIdx };
5225 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5226 PPCISD::LFIWZX : PPCISD::LFIWAX,
5227 dl, DAG.getVTList(MVT::f64, MVT::Other),
5228 Ops, 2, MVT::i32, MMO);
5230 assert(PPCSubTarget.isPPC64() &&
5231 "i32->FP without LFIWAX supported only on PPC64");
5233 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5234 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5236 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5239 // STD the extended value into the stack slot.
5240 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5241 MachinePointerInfo::getFixedStack(FrameIdx),
5244 // Load the value as a double.
5245 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5246 MachinePointerInfo::getFixedStack(FrameIdx),
5247 false, false, false, 0);
5250 // FCFID it and return it.
5251 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5252 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
5253 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5257 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5258 SelectionDAG &DAG) const {
5261 The rounding mode is in bits 30:31 of FPSR, and has the following
5268 FLT_ROUNDS, on the other hand, expects the following:
5275 To perform the conversion, we do:
5276 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5279 MachineFunction &MF = DAG.getMachineFunction();
5280 EVT VT = Op.getValueType();
5281 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5282 SDValue MFFSreg, InFlag;
5284 // Save FP Control Word to register
5286 MVT::f64, // return register
5287 MVT::Glue // unused in this context
5289 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
5291 // Save FP register to stack slot
5292 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5293 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5294 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5295 StackSlot, MachinePointerInfo(), false, false,0);
5297 // Load FP Control Word from low 32 bits of stack slot.
5298 SDValue Four = DAG.getConstant(4, PtrVT);
5299 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5300 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5301 false, false, false, 0);
5303 // Transform as necessary
5305 DAG.getNode(ISD::AND, dl, MVT::i32,
5306 CWD, DAG.getConstant(3, MVT::i32));
5308 DAG.getNode(ISD::SRL, dl, MVT::i32,
5309 DAG.getNode(ISD::AND, dl, MVT::i32,
5310 DAG.getNode(ISD::XOR, dl, MVT::i32,
5311 CWD, DAG.getConstant(3, MVT::i32)),
5312 DAG.getConstant(3, MVT::i32)),
5313 DAG.getConstant(1, MVT::i32));
5316 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5318 return DAG.getNode((VT.getSizeInBits() < 16 ?
5319 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5322 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5323 EVT VT = Op.getValueType();
5324 unsigned BitWidth = VT.getSizeInBits();
5326 assert(Op.getNumOperands() == 3 &&
5327 VT == Op.getOperand(1).getValueType() &&
5330 // Expand into a bunch of logical ops. Note that these ops
5331 // depend on the PPC behavior for oversized shift amounts.
5332 SDValue Lo = Op.getOperand(0);
5333 SDValue Hi = Op.getOperand(1);
5334 SDValue Amt = Op.getOperand(2);
5335 EVT AmtVT = Amt.getValueType();
5337 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5338 DAG.getConstant(BitWidth, AmtVT), Amt);
5339 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5340 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5341 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5342 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5343 DAG.getConstant(-BitWidth, AmtVT));
5344 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5345 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5346 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5347 SDValue OutOps[] = { OutLo, OutHi };
5348 return DAG.getMergeValues(OutOps, 2, dl);
5351 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5352 EVT VT = Op.getValueType();
5354 unsigned BitWidth = VT.getSizeInBits();
5355 assert(Op.getNumOperands() == 3 &&
5356 VT == Op.getOperand(1).getValueType() &&
5359 // Expand into a bunch of logical ops. Note that these ops
5360 // depend on the PPC behavior for oversized shift amounts.
5361 SDValue Lo = Op.getOperand(0);
5362 SDValue Hi = Op.getOperand(1);
5363 SDValue Amt = Op.getOperand(2);
5364 EVT AmtVT = Amt.getValueType();
5366 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5367 DAG.getConstant(BitWidth, AmtVT), Amt);
5368 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5369 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5370 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5371 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5372 DAG.getConstant(-BitWidth, AmtVT));
5373 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5374 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5375 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5376 SDValue OutOps[] = { OutLo, OutHi };
5377 return DAG.getMergeValues(OutOps, 2, dl);
5380 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5382 EVT VT = Op.getValueType();
5383 unsigned BitWidth = VT.getSizeInBits();
5384 assert(Op.getNumOperands() == 3 &&
5385 VT == Op.getOperand(1).getValueType() &&
5388 // Expand into a bunch of logical ops, followed by a select_cc.
5389 SDValue Lo = Op.getOperand(0);
5390 SDValue Hi = Op.getOperand(1);
5391 SDValue Amt = Op.getOperand(2);
5392 EVT AmtVT = Amt.getValueType();
5394 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5395 DAG.getConstant(BitWidth, AmtVT), Amt);
5396 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5397 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5398 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5399 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5400 DAG.getConstant(-BitWidth, AmtVT));
5401 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5402 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5403 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5404 Tmp4, Tmp6, ISD::SETLE);
5405 SDValue OutOps[] = { OutLo, OutHi };
5406 return DAG.getMergeValues(OutOps, 2, dl);
5409 //===----------------------------------------------------------------------===//
5410 // Vector related lowering.
5413 /// BuildSplatI - Build a canonical splati of Val with an element size of
5414 /// SplatSize. Cast the result to VT.
5415 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5416 SelectionDAG &DAG, SDLoc dl) {
5417 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5419 static const EVT VTys[] = { // canonical VT to use for each size.
5420 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5423 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5425 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5429 EVT CanonicalVT = VTys[SplatSize-1];
5431 // Build a canonical splat for this value.
5432 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5433 SmallVector<SDValue, 8> Ops;
5434 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5435 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5436 &Ops[0], Ops.size());
5437 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5440 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5441 /// specified intrinsic ID.
5442 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5443 SelectionDAG &DAG, SDLoc dl,
5444 EVT DestVT = MVT::Other) {
5445 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5446 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5447 DAG.getConstant(IID, MVT::i32), Op);
5450 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5451 /// specified intrinsic ID.
5452 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5453 SelectionDAG &DAG, SDLoc dl,
5454 EVT DestVT = MVT::Other) {
5455 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5456 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5457 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5460 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5461 /// specified intrinsic ID.
5462 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5463 SDValue Op2, SelectionDAG &DAG,
5464 SDLoc dl, EVT DestVT = MVT::Other) {
5465 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5466 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5467 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5471 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5472 /// amount. The result has the specified value type.
5473 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5474 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5475 // Force LHS/RHS to be the right type.
5476 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5477 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5480 for (unsigned i = 0; i != 16; ++i)
5482 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5483 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5486 // If this is a case we can't handle, return null and let the default
5487 // expansion code take care of it. If we CAN select this case, and if it
5488 // selects to a single instruction, return Op. Otherwise, if we can codegen
5489 // this case more efficiently than a constant pool load, lower it to the
5490 // sequence of ops that should be used.
5491 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5492 SelectionDAG &DAG) const {
5494 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5495 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5497 // Check if this is a splat of a constant value.
5498 APInt APSplatBits, APSplatUndef;
5499 unsigned SplatBitSize;
5501 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5502 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5505 unsigned SplatBits = APSplatBits.getZExtValue();
5506 unsigned SplatUndef = APSplatUndef.getZExtValue();
5507 unsigned SplatSize = SplatBitSize / 8;
5509 // First, handle single instruction cases.
5512 if (SplatBits == 0) {
5513 // Canonicalize all zero vectors to be v4i32.
5514 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5515 SDValue Z = DAG.getConstant(0, MVT::i32);
5516 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5517 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5522 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5523 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5525 if (SextVal >= -16 && SextVal <= 15)
5526 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5529 // Two instruction sequences.
5531 // If this value is in the range [-32,30] and is even, use:
5532 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5533 // If this value is in the range [17,31] and is odd, use:
5534 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5535 // If this value is in the range [-31,-17] and is odd, use:
5536 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5537 // Note the last two are three-instruction sequences.
5538 if (SextVal >= -32 && SextVal <= 31) {
5539 // To avoid having these optimizations undone by constant folding,
5540 // we convert to a pseudo that will be expanded later into one of
5542 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5543 EVT VT = Op.getValueType();
5544 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5545 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5546 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5549 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5550 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5552 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5553 // Make -1 and vspltisw -1:
5554 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5556 // Make the VSLW intrinsic, computing 0x8000_0000.
5557 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5560 // xor by OnesV to invert it.
5561 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5562 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5565 // Check to see if this is a wide variety of vsplti*, binop self cases.
5566 static const signed char SplatCsts[] = {
5567 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5568 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5571 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5572 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5573 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5574 int i = SplatCsts[idx];
5576 // Figure out what shift amount will be used by altivec if shifted by i in
5578 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5580 // vsplti + shl self.
5581 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5582 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5583 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5584 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5585 Intrinsic::ppc_altivec_vslw
5587 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5588 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5591 // vsplti + srl self.
5592 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5593 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5594 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5595 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5596 Intrinsic::ppc_altivec_vsrw
5598 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5599 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5602 // vsplti + sra self.
5603 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5604 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5605 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5606 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5607 Intrinsic::ppc_altivec_vsraw
5609 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5610 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5613 // vsplti + rol self.
5614 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5615 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5616 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5617 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5618 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5619 Intrinsic::ppc_altivec_vrlw
5621 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5622 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5625 // t = vsplti c, result = vsldoi t, t, 1
5626 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5627 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5628 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5630 // t = vsplti c, result = vsldoi t, t, 2
5631 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5632 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5633 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5635 // t = vsplti c, result = vsldoi t, t, 3
5636 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5637 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5638 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5645 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5646 /// the specified operations to build the shuffle.
5647 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5648 SDValue RHS, SelectionDAG &DAG,
5650 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5651 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5652 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5655 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5667 if (OpNum == OP_COPY) {
5668 if (LHSID == (1*9+2)*9+3) return LHS;
5669 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5673 SDValue OpLHS, OpRHS;
5674 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5675 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5679 default: llvm_unreachable("Unknown i32 permute!");
5681 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5682 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5683 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5684 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5687 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5688 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5689 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5690 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5693 for (unsigned i = 0; i != 16; ++i)
5694 ShufIdxs[i] = (i&3)+0;
5697 for (unsigned i = 0; i != 16; ++i)
5698 ShufIdxs[i] = (i&3)+4;
5701 for (unsigned i = 0; i != 16; ++i)
5702 ShufIdxs[i] = (i&3)+8;
5705 for (unsigned i = 0; i != 16; ++i)
5706 ShufIdxs[i] = (i&3)+12;
5709 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5711 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5713 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5715 EVT VT = OpLHS.getValueType();
5716 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5717 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5718 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5719 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5722 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5723 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5724 /// return the code it can be lowered into. Worst case, it can always be
5725 /// lowered into a vperm.
5726 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5727 SelectionDAG &DAG) const {
5729 SDValue V1 = Op.getOperand(0);
5730 SDValue V2 = Op.getOperand(1);
5731 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5732 EVT VT = Op.getValueType();
5734 // Cases that are handled by instructions that take permute immediates
5735 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5736 // selected by the instruction selector.
5737 if (V2.getOpcode() == ISD::UNDEF) {
5738 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5739 PPC::isSplatShuffleMask(SVOp, 2) ||
5740 PPC::isSplatShuffleMask(SVOp, 4) ||
5741 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5742 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5743 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5744 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5745 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5746 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5747 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5748 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5749 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5754 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5755 // and produce a fixed permutation. If any of these match, do not lower to
5757 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5758 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5759 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5760 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5761 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5762 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5763 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5764 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5765 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5768 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5769 // perfect shuffle table to emit an optimal matching sequence.
5770 ArrayRef<int> PermMask = SVOp->getMask();
5772 unsigned PFIndexes[4];
5773 bool isFourElementShuffle = true;
5774 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5775 unsigned EltNo = 8; // Start out undef.
5776 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5777 if (PermMask[i*4+j] < 0)
5778 continue; // Undef, ignore it.
5780 unsigned ByteSource = PermMask[i*4+j];
5781 if ((ByteSource & 3) != j) {
5782 isFourElementShuffle = false;
5787 EltNo = ByteSource/4;
5788 } else if (EltNo != ByteSource/4) {
5789 isFourElementShuffle = false;
5793 PFIndexes[i] = EltNo;
5796 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5797 // perfect shuffle vector to determine if it is cost effective to do this as
5798 // discrete instructions, or whether we should use a vperm.
5799 if (isFourElementShuffle) {
5800 // Compute the index in the perfect shuffle table.
5801 unsigned PFTableIndex =
5802 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5804 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5805 unsigned Cost = (PFEntry >> 30);
5807 // Determining when to avoid vperm is tricky. Many things affect the cost
5808 // of vperm, particularly how many times the perm mask needs to be computed.
5809 // For example, if the perm mask can be hoisted out of a loop or is already
5810 // used (perhaps because there are multiple permutes with the same shuffle
5811 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5812 // the loop requires an extra register.
5814 // As a compromise, we only emit discrete instructions if the shuffle can be
5815 // generated in 3 or fewer operations. When we have loop information
5816 // available, if this block is within a loop, we should avoid using vperm
5817 // for 3-operation perms and use a constant pool load instead.
5819 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5822 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5823 // vector that will get spilled to the constant pool.
5824 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5826 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5827 // that it is in input element units, not in bytes. Convert now.
5828 EVT EltVT = V1.getValueType().getVectorElementType();
5829 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5831 SmallVector<SDValue, 16> ResultMask;
5832 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5833 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5835 for (unsigned j = 0; j != BytesPerElement; ++j)
5836 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5840 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5841 &ResultMask[0], ResultMask.size());
5842 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5845 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5846 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5847 /// information about the intrinsic.
5848 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5850 unsigned IntrinsicID =
5851 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5854 switch (IntrinsicID) {
5855 default: return false;
5856 // Comparison predicates.
5857 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5858 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5859 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5860 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5861 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5862 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5863 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5864 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5865 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5866 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5867 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5868 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5869 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5871 // Normal Comparisons.
5872 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5873 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5874 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5875 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5876 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5877 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5878 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5879 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5880 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5881 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5882 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5883 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5884 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5889 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5890 /// lower, do it, otherwise return null.
5891 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5892 SelectionDAG &DAG) const {
5893 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5894 // opcode number of the comparison.
5898 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5899 return SDValue(); // Don't custom lower most intrinsics.
5901 // If this is a non-dot comparison, make the VCMP node and we are done.
5903 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5904 Op.getOperand(1), Op.getOperand(2),
5905 DAG.getConstant(CompareOpc, MVT::i32));
5906 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5909 // Create the PPCISD altivec 'dot' comparison node.
5911 Op.getOperand(2), // LHS
5912 Op.getOperand(3), // RHS
5913 DAG.getConstant(CompareOpc, MVT::i32)
5915 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5916 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5918 // Now that we have the comparison, emit a copy from the CR to a GPR.
5919 // This is flagged to the above dot comparison.
5920 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5921 DAG.getRegister(PPC::CR6, MVT::i32),
5922 CompNode.getValue(1));
5924 // Unpack the result based on how the target uses it.
5925 unsigned BitNo; // Bit # of CR6.
5926 bool InvertBit; // Invert result?
5927 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5928 default: // Can't happen, don't crash on invalid number though.
5929 case 0: // Return the value of the EQ bit of CR6.
5930 BitNo = 0; InvertBit = false;
5932 case 1: // Return the inverted value of the EQ bit of CR6.
5933 BitNo = 0; InvertBit = true;
5935 case 2: // Return the value of the LT bit of CR6.
5936 BitNo = 2; InvertBit = false;
5938 case 3: // Return the inverted value of the LT bit of CR6.
5939 BitNo = 2; InvertBit = true;
5943 // Shift the bit into the low position.
5944 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5945 DAG.getConstant(8-(3-BitNo), MVT::i32));
5947 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5948 DAG.getConstant(1, MVT::i32));
5950 // If we are supposed to, toggle the bit.
5952 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5953 DAG.getConstant(1, MVT::i32));
5957 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
5958 SelectionDAG &DAG) const {
5960 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
5961 // instructions), but for smaller types, we need to first extend up to v2i32
5962 // before doing going farther.
5963 if (Op.getValueType() == MVT::v2i64) {
5964 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
5965 if (ExtVT != MVT::v2i32) {
5966 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
5967 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
5968 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
5969 ExtVT.getVectorElementType(), 4)));
5970 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
5971 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
5972 DAG.getValueType(MVT::v2i32));
5981 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5982 SelectionDAG &DAG) const {
5984 // Create a stack slot that is 16-byte aligned.
5985 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5986 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5987 EVT PtrVT = getPointerTy();
5988 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5990 // Store the input value into Value#0 of the stack slot.
5991 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5992 Op.getOperand(0), FIdx, MachinePointerInfo(),
5995 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5996 false, false, false, 0);
5999 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6001 if (Op.getValueType() == MVT::v4i32) {
6002 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6004 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6005 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6007 SDValue RHSSwap = // = vrlw RHS, 16
6008 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6010 // Shrinkify inputs to v8i16.
6011 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6012 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6013 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6015 // Low parts multiplied together, generating 32-bit results (we ignore the
6017 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6018 LHS, RHS, DAG, dl, MVT::v4i32);
6020 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6021 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6022 // Shift the high parts up 16 bits.
6023 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6025 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6026 } else if (Op.getValueType() == MVT::v8i16) {
6027 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6029 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6031 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6032 LHS, RHS, Zero, DAG, dl);
6033 } else if (Op.getValueType() == MVT::v16i8) {
6034 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6036 // Multiply the even 8-bit parts, producing 16-bit sums.
6037 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6038 LHS, RHS, DAG, dl, MVT::v8i16);
6039 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6041 // Multiply the odd 8-bit parts, producing 16-bit sums.
6042 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6043 LHS, RHS, DAG, dl, MVT::v8i16);
6044 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6046 // Merge the results together.
6048 for (unsigned i = 0; i != 8; ++i) {
6050 Ops[i*2+1] = 2*i+1+16;
6052 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6054 llvm_unreachable("Unknown mul to lower!");
6058 /// LowerOperation - Provide custom lowering hooks for some operations.
6060 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6061 switch (Op.getOpcode()) {
6062 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6063 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6064 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6065 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6066 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6067 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6068 case ISD::SETCC: return LowerSETCC(Op, DAG);
6069 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6070 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6072 return LowerVASTART(Op, DAG, PPCSubTarget);
6075 return LowerVAARG(Op, DAG, PPCSubTarget);
6078 return LowerVACOPY(Op, DAG, PPCSubTarget);
6080 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
6081 case ISD::DYNAMIC_STACKALLOC:
6082 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
6084 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6085 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6087 case ISD::LOAD: return LowerLOAD(Op, DAG);
6088 case ISD::STORE: return LowerSTORE(Op, DAG);
6089 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6090 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6091 case ISD::FP_TO_UINT:
6092 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6094 case ISD::UINT_TO_FP:
6095 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6096 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6098 // Lower 64-bit shifts.
6099 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6100 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6101 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6103 // Vector-related lowering.
6104 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6105 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6106 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6107 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6108 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6109 case ISD::MUL: return LowerMUL(Op, DAG);
6111 // For counter-based loop handling.
6112 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6114 // Frame & Return address.
6115 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6116 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6120 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6121 SmallVectorImpl<SDValue>&Results,
6122 SelectionDAG &DAG) const {
6123 const TargetMachine &TM = getTargetMachine();
6125 switch (N->getOpcode()) {
6127 llvm_unreachable("Do not know how to custom type legalize this operation!");
6128 case ISD::INTRINSIC_W_CHAIN: {
6129 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6130 Intrinsic::ppc_is_decremented_ctr_nonzero)
6133 assert(N->getValueType(0) == MVT::i1 &&
6134 "Unexpected result type for CTR decrement intrinsic");
6135 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6136 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6137 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6140 Results.push_back(NewInt);
6141 Results.push_back(NewInt.getValue(1));
6145 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6146 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6149 EVT VT = N->getValueType(0);
6151 if (VT == MVT::i64) {
6152 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
6154 Results.push_back(NewNode);
6155 Results.push_back(NewNode.getValue(1));
6159 case ISD::FP_ROUND_INREG: {
6160 assert(N->getValueType(0) == MVT::ppcf128);
6161 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6162 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6163 MVT::f64, N->getOperand(0),
6164 DAG.getIntPtrConstant(0));
6165 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6166 MVT::f64, N->getOperand(0),
6167 DAG.getIntPtrConstant(1));
6169 // Add the two halves of the long double in round-to-zero mode.
6170 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6172 // We know the low half is about to be thrown away, so just use something
6174 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6178 case ISD::FP_TO_SINT:
6179 // LowerFP_TO_INT() can only handle f32 and f64.
6180 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6182 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6188 //===----------------------------------------------------------------------===//
6189 // Other Lowering Code
6190 //===----------------------------------------------------------------------===//
6193 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6194 bool is64bit, unsigned BinOpcode) const {
6195 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6196 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6198 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6199 MachineFunction *F = BB->getParent();
6200 MachineFunction::iterator It = BB;
6203 unsigned dest = MI->getOperand(0).getReg();
6204 unsigned ptrA = MI->getOperand(1).getReg();
6205 unsigned ptrB = MI->getOperand(2).getReg();
6206 unsigned incr = MI->getOperand(3).getReg();
6207 DebugLoc dl = MI->getDebugLoc();
6209 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6210 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6211 F->insert(It, loopMBB);
6212 F->insert(It, exitMBB);
6213 exitMBB->splice(exitMBB->begin(), BB,
6214 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6215 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6217 MachineRegisterInfo &RegInfo = F->getRegInfo();
6218 unsigned TmpReg = (!BinOpcode) ? incr :
6219 RegInfo.createVirtualRegister(
6220 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6221 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6225 // fallthrough --> loopMBB
6226 BB->addSuccessor(loopMBB);
6229 // l[wd]arx dest, ptr
6230 // add r0, dest, incr
6231 // st[wd]cx. r0, ptr
6233 // fallthrough --> exitMBB
6235 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6236 .addReg(ptrA).addReg(ptrB);
6238 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6239 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6240 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6241 BuildMI(BB, dl, TII->get(PPC::BCC))
6242 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6243 BB->addSuccessor(loopMBB);
6244 BB->addSuccessor(exitMBB);
6253 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6254 MachineBasicBlock *BB,
6255 bool is8bit, // operation
6256 unsigned BinOpcode) const {
6257 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6258 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6259 // In 64 bit mode we have to use 64 bits for addresses, even though the
6260 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6261 // registers without caring whether they're 32 or 64, but here we're
6262 // doing actual arithmetic on the addresses.
6263 bool is64bit = PPCSubTarget.isPPC64();
6264 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6266 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6267 MachineFunction *F = BB->getParent();
6268 MachineFunction::iterator It = BB;
6271 unsigned dest = MI->getOperand(0).getReg();
6272 unsigned ptrA = MI->getOperand(1).getReg();
6273 unsigned ptrB = MI->getOperand(2).getReg();
6274 unsigned incr = MI->getOperand(3).getReg();
6275 DebugLoc dl = MI->getDebugLoc();
6277 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6278 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6279 F->insert(It, loopMBB);
6280 F->insert(It, exitMBB);
6281 exitMBB->splice(exitMBB->begin(), BB,
6282 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6283 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6285 MachineRegisterInfo &RegInfo = F->getRegInfo();
6286 const TargetRegisterClass *RC =
6287 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6288 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6289 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6290 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6291 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6292 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6293 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6294 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6295 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6296 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6297 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6298 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6299 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6301 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6305 // fallthrough --> loopMBB
6306 BB->addSuccessor(loopMBB);
6308 // The 4-byte load must be aligned, while a char or short may be
6309 // anywhere in the word. Hence all this nasty bookkeeping code.
6310 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6311 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6312 // xori shift, shift1, 24 [16]
6313 // rlwinm ptr, ptr1, 0, 0, 29
6314 // slw incr2, incr, shift
6315 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6316 // slw mask, mask2, shift
6318 // lwarx tmpDest, ptr
6319 // add tmp, tmpDest, incr2
6320 // andc tmp2, tmpDest, mask
6321 // and tmp3, tmp, mask
6322 // or tmp4, tmp3, tmp2
6325 // fallthrough --> exitMBB
6326 // srw dest, tmpDest, shift
6327 if (ptrA != ZeroReg) {
6328 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6329 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6330 .addReg(ptrA).addReg(ptrB);
6334 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6335 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6336 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6337 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6339 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6340 .addReg(Ptr1Reg).addImm(0).addImm(61);
6342 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6343 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6344 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6345 .addReg(incr).addReg(ShiftReg);
6347 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6349 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6350 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6352 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6353 .addReg(Mask2Reg).addReg(ShiftReg);
6356 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6357 .addReg(ZeroReg).addReg(PtrReg);
6359 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6360 .addReg(Incr2Reg).addReg(TmpDestReg);
6361 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6362 .addReg(TmpDestReg).addReg(MaskReg);
6363 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6364 .addReg(TmpReg).addReg(MaskReg);
6365 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6366 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6367 BuildMI(BB, dl, TII->get(PPC::STWCX))
6368 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6369 BuildMI(BB, dl, TII->get(PPC::BCC))
6370 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6371 BB->addSuccessor(loopMBB);
6372 BB->addSuccessor(exitMBB);
6377 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6382 llvm::MachineBasicBlock*
6383 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6384 MachineBasicBlock *MBB) const {
6385 DebugLoc DL = MI->getDebugLoc();
6386 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6388 MachineFunction *MF = MBB->getParent();
6389 MachineRegisterInfo &MRI = MF->getRegInfo();
6391 const BasicBlock *BB = MBB->getBasicBlock();
6392 MachineFunction::iterator I = MBB;
6396 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6397 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6399 unsigned DstReg = MI->getOperand(0).getReg();
6400 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6401 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6402 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6403 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6405 MVT PVT = getPointerTy();
6406 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6407 "Invalid Pointer Size!");
6408 // For v = setjmp(buf), we generate
6411 // SjLjSetup mainMBB
6417 // buf[LabelOffset] = LR
6421 // v = phi(main, restore)
6424 MachineBasicBlock *thisMBB = MBB;
6425 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6426 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6427 MF->insert(I, mainMBB);
6428 MF->insert(I, sinkMBB);
6430 MachineInstrBuilder MIB;
6432 // Transfer the remainder of BB and its successor edges to sinkMBB.
6433 sinkMBB->splice(sinkMBB->begin(), MBB,
6434 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6435 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6437 // Note that the structure of the jmp_buf used here is not compatible
6438 // with that used by libc, and is not designed to be. Specifically, it
6439 // stores only those 'reserved' registers that LLVM does not otherwise
6440 // understand how to spill. Also, by convention, by the time this
6441 // intrinsic is called, Clang has already stored the frame address in the
6442 // first slot of the buffer and stack address in the third. Following the
6443 // X86 target code, we'll store the jump address in the second slot. We also
6444 // need to save the TOC pointer (R2) to handle jumps between shared
6445 // libraries, and that will be stored in the fourth slot. The thread
6446 // identifier (R13) is not affected.
6449 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6450 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6451 const int64_t BPOffset = 4 * PVT.getStoreSize();
6453 // Prepare IP either in reg.
6454 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6455 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6456 unsigned BufReg = MI->getOperand(1).getReg();
6458 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6459 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6463 MIB.setMemRefs(MMOBegin, MMOEnd);
6466 // Naked functions never have a base pointer, and so we use r1. For all
6467 // other functions, this decision must be delayed until during PEI.
6469 if (MF->getFunction()->getAttributes().hasAttribute(
6470 AttributeSet::FunctionIndex, Attribute::Naked))
6471 BaseReg = PPCSubTarget.isPPC64() ? PPC::X1 : PPC::R1;
6473 BaseReg = PPCSubTarget.isPPC64() ? PPC::BP8 : PPC::BP;
6475 MIB = BuildMI(*thisMBB, MI, DL,
6476 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6480 MIB.setMemRefs(MMOBegin, MMOEnd);
6483 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6484 const PPCRegisterInfo *TRI =
6485 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6486 MIB.addRegMask(TRI->getNoPreservedMask());
6488 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6490 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6492 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6494 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6495 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6499 MIB = BuildMI(mainMBB, DL,
6500 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6503 if (PPCSubTarget.isPPC64()) {
6504 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6506 .addImm(LabelOffset)
6509 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6511 .addImm(LabelOffset)
6515 MIB.setMemRefs(MMOBegin, MMOEnd);
6517 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6518 mainMBB->addSuccessor(sinkMBB);
6521 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6522 TII->get(PPC::PHI), DstReg)
6523 .addReg(mainDstReg).addMBB(mainMBB)
6524 .addReg(restoreDstReg).addMBB(thisMBB);
6526 MI->eraseFromParent();
6531 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6532 MachineBasicBlock *MBB) const {
6533 DebugLoc DL = MI->getDebugLoc();
6534 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6536 MachineFunction *MF = MBB->getParent();
6537 MachineRegisterInfo &MRI = MF->getRegInfo();
6540 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6541 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6543 MVT PVT = getPointerTy();
6544 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6545 "Invalid Pointer Size!");
6547 const TargetRegisterClass *RC =
6548 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6549 unsigned Tmp = MRI.createVirtualRegister(RC);
6550 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6551 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6552 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6553 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6555 MachineInstrBuilder MIB;
6557 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6558 const int64_t SPOffset = 2 * PVT.getStoreSize();
6559 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6560 const int64_t BPOffset = 4 * PVT.getStoreSize();
6562 unsigned BufReg = MI->getOperand(0).getReg();
6564 // Reload FP (the jumped-to function may not have had a
6565 // frame pointer, and if so, then its r31 will be restored
6567 if (PVT == MVT::i64) {
6568 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6572 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6576 MIB.setMemRefs(MMOBegin, MMOEnd);
6579 if (PVT == MVT::i64) {
6580 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6581 .addImm(LabelOffset)
6584 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6585 .addImm(LabelOffset)
6588 MIB.setMemRefs(MMOBegin, MMOEnd);
6591 if (PVT == MVT::i64) {
6592 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6596 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6600 MIB.setMemRefs(MMOBegin, MMOEnd);
6603 if (PVT == MVT::i64) {
6604 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6608 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6612 MIB.setMemRefs(MMOBegin, MMOEnd);
6615 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6616 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6620 MIB.setMemRefs(MMOBegin, MMOEnd);
6624 BuildMI(*MBB, MI, DL,
6625 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6626 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6628 MI->eraseFromParent();
6633 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6634 MachineBasicBlock *BB) const {
6635 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6636 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6637 return emitEHSjLjSetJmp(MI, BB);
6638 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6639 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6640 return emitEHSjLjLongJmp(MI, BB);
6643 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6645 // To "insert" these instructions we actually have to insert their
6646 // control-flow patterns.
6647 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6648 MachineFunction::iterator It = BB;
6651 MachineFunction *F = BB->getParent();
6653 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6654 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6655 MI->getOpcode() == PPC::SELECT_I4 ||
6656 MI->getOpcode() == PPC::SELECT_I8)) {
6657 SmallVector<MachineOperand, 2> Cond;
6658 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6659 MI->getOpcode() == PPC::SELECT_CC_I8)
6660 Cond.push_back(MI->getOperand(4));
6662 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6663 Cond.push_back(MI->getOperand(1));
6665 DebugLoc dl = MI->getDebugLoc();
6666 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6667 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6668 Cond, MI->getOperand(2).getReg(),
6669 MI->getOperand(3).getReg());
6670 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6671 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6672 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6673 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6674 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6675 MI->getOpcode() == PPC::SELECT_I4 ||
6676 MI->getOpcode() == PPC::SELECT_I8 ||
6677 MI->getOpcode() == PPC::SELECT_F4 ||
6678 MI->getOpcode() == PPC::SELECT_F8 ||
6679 MI->getOpcode() == PPC::SELECT_VRRC) {
6680 // The incoming instruction knows the destination vreg to set, the
6681 // condition code register to branch on, the true/false values to
6682 // select between, and a branch opcode to use.
6687 // cmpTY ccX, r1, r2
6689 // fallthrough --> copy0MBB
6690 MachineBasicBlock *thisMBB = BB;
6691 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6692 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6693 DebugLoc dl = MI->getDebugLoc();
6694 F->insert(It, copy0MBB);
6695 F->insert(It, sinkMBB);
6697 // Transfer the remainder of BB and its successor edges to sinkMBB.
6698 sinkMBB->splice(sinkMBB->begin(), BB,
6699 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6700 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6702 // Next, add the true and fallthrough blocks as its successors.
6703 BB->addSuccessor(copy0MBB);
6704 BB->addSuccessor(sinkMBB);
6706 if (MI->getOpcode() == PPC::SELECT_I4 ||
6707 MI->getOpcode() == PPC::SELECT_I8 ||
6708 MI->getOpcode() == PPC::SELECT_F4 ||
6709 MI->getOpcode() == PPC::SELECT_F8 ||
6710 MI->getOpcode() == PPC::SELECT_VRRC) {
6711 BuildMI(BB, dl, TII->get(PPC::BC))
6712 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6714 unsigned SelectPred = MI->getOperand(4).getImm();
6715 BuildMI(BB, dl, TII->get(PPC::BCC))
6716 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6720 // %FalseValue = ...
6721 // # fallthrough to sinkMBB
6724 // Update machine-CFG edges
6725 BB->addSuccessor(sinkMBB);
6728 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6731 BuildMI(*BB, BB->begin(), dl,
6732 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6733 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6734 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6736 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6737 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6738 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6739 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6740 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6741 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6742 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6743 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6745 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6746 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6747 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6748 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6749 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6750 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6751 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6752 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6754 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6755 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6756 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6757 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6758 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6759 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6760 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6761 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6763 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6764 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6765 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6766 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6767 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6768 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6769 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6770 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6772 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6773 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6774 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6775 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6776 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6777 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6778 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6779 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6781 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6782 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6783 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6784 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6785 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6786 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6787 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6788 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6790 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6791 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6792 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6793 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6794 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6795 BB = EmitAtomicBinary(MI, BB, false, 0);
6796 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6797 BB = EmitAtomicBinary(MI, BB, true, 0);
6799 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6800 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6801 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6803 unsigned dest = MI->getOperand(0).getReg();
6804 unsigned ptrA = MI->getOperand(1).getReg();
6805 unsigned ptrB = MI->getOperand(2).getReg();
6806 unsigned oldval = MI->getOperand(3).getReg();
6807 unsigned newval = MI->getOperand(4).getReg();
6808 DebugLoc dl = MI->getDebugLoc();
6810 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6811 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6812 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6813 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6814 F->insert(It, loop1MBB);
6815 F->insert(It, loop2MBB);
6816 F->insert(It, midMBB);
6817 F->insert(It, exitMBB);
6818 exitMBB->splice(exitMBB->begin(), BB,
6819 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6820 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6824 // fallthrough --> loopMBB
6825 BB->addSuccessor(loop1MBB);
6828 // l[wd]arx dest, ptr
6829 // cmp[wd] dest, oldval
6832 // st[wd]cx. newval, ptr
6836 // st[wd]cx. dest, ptr
6839 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6840 .addReg(ptrA).addReg(ptrB);
6841 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6842 .addReg(oldval).addReg(dest);
6843 BuildMI(BB, dl, TII->get(PPC::BCC))
6844 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6845 BB->addSuccessor(loop2MBB);
6846 BB->addSuccessor(midMBB);
6849 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6850 .addReg(newval).addReg(ptrA).addReg(ptrB);
6851 BuildMI(BB, dl, TII->get(PPC::BCC))
6852 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6853 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6854 BB->addSuccessor(loop1MBB);
6855 BB->addSuccessor(exitMBB);
6858 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6859 .addReg(dest).addReg(ptrA).addReg(ptrB);
6860 BB->addSuccessor(exitMBB);
6865 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6866 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6867 // We must use 64-bit registers for addresses when targeting 64-bit,
6868 // since we're actually doing arithmetic on them. Other registers
6870 bool is64bit = PPCSubTarget.isPPC64();
6871 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6873 unsigned dest = MI->getOperand(0).getReg();
6874 unsigned ptrA = MI->getOperand(1).getReg();
6875 unsigned ptrB = MI->getOperand(2).getReg();
6876 unsigned oldval = MI->getOperand(3).getReg();
6877 unsigned newval = MI->getOperand(4).getReg();
6878 DebugLoc dl = MI->getDebugLoc();
6880 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6881 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6882 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6883 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6884 F->insert(It, loop1MBB);
6885 F->insert(It, loop2MBB);
6886 F->insert(It, midMBB);
6887 F->insert(It, exitMBB);
6888 exitMBB->splice(exitMBB->begin(), BB,
6889 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6890 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6892 MachineRegisterInfo &RegInfo = F->getRegInfo();
6893 const TargetRegisterClass *RC =
6894 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6895 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6896 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6897 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6898 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6899 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6900 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6901 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6902 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6903 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6904 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6905 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6906 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6907 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6908 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6910 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6911 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6914 // fallthrough --> loopMBB
6915 BB->addSuccessor(loop1MBB);
6917 // The 4-byte load must be aligned, while a char or short may be
6918 // anywhere in the word. Hence all this nasty bookkeeping code.
6919 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6920 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6921 // xori shift, shift1, 24 [16]
6922 // rlwinm ptr, ptr1, 0, 0, 29
6923 // slw newval2, newval, shift
6924 // slw oldval2, oldval,shift
6925 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6926 // slw mask, mask2, shift
6927 // and newval3, newval2, mask
6928 // and oldval3, oldval2, mask
6930 // lwarx tmpDest, ptr
6931 // and tmp, tmpDest, mask
6932 // cmpw tmp, oldval3
6935 // andc tmp2, tmpDest, mask
6936 // or tmp4, tmp2, newval3
6941 // stwcx. tmpDest, ptr
6943 // srw dest, tmpDest, shift
6944 if (ptrA != ZeroReg) {
6945 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6946 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6947 .addReg(ptrA).addReg(ptrB);
6951 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6952 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6953 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6954 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6956 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6957 .addReg(Ptr1Reg).addImm(0).addImm(61);
6959 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6960 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6961 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6962 .addReg(newval).addReg(ShiftReg);
6963 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6964 .addReg(oldval).addReg(ShiftReg);
6966 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6968 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6969 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6970 .addReg(Mask3Reg).addImm(65535);
6972 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6973 .addReg(Mask2Reg).addReg(ShiftReg);
6974 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6975 .addReg(NewVal2Reg).addReg(MaskReg);
6976 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6977 .addReg(OldVal2Reg).addReg(MaskReg);
6980 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6981 .addReg(ZeroReg).addReg(PtrReg);
6982 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6983 .addReg(TmpDestReg).addReg(MaskReg);
6984 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6985 .addReg(TmpReg).addReg(OldVal3Reg);
6986 BuildMI(BB, dl, TII->get(PPC::BCC))
6987 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6988 BB->addSuccessor(loop2MBB);
6989 BB->addSuccessor(midMBB);
6992 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6993 .addReg(TmpDestReg).addReg(MaskReg);
6994 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6995 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6996 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6997 .addReg(ZeroReg).addReg(PtrReg);
6998 BuildMI(BB, dl, TII->get(PPC::BCC))
6999 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7000 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7001 BB->addSuccessor(loop1MBB);
7002 BB->addSuccessor(exitMBB);
7005 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7006 .addReg(ZeroReg).addReg(PtrReg);
7007 BB->addSuccessor(exitMBB);
7012 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7014 } else if (MI->getOpcode() == PPC::FADDrtz) {
7015 // This pseudo performs an FADD with rounding mode temporarily forced
7016 // to round-to-zero. We emit this via custom inserter since the FPSCR
7017 // is not modeled at the SelectionDAG level.
7018 unsigned Dest = MI->getOperand(0).getReg();
7019 unsigned Src1 = MI->getOperand(1).getReg();
7020 unsigned Src2 = MI->getOperand(2).getReg();
7021 DebugLoc dl = MI->getDebugLoc();
7023 MachineRegisterInfo &RegInfo = F->getRegInfo();
7024 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7026 // Save FPSCR value.
7027 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7029 // Set rounding mode to round-to-zero.
7030 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7031 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7033 // Perform addition.
7034 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7036 // Restore FPSCR value.
7037 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7038 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7039 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7040 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7041 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7042 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7043 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7044 PPC::ANDIo8 : PPC::ANDIo;
7045 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7046 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7048 MachineRegisterInfo &RegInfo = F->getRegInfo();
7049 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7050 &PPC::GPRCRegClass :
7051 &PPC::G8RCRegClass);
7053 DebugLoc dl = MI->getDebugLoc();
7054 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7055 .addReg(MI->getOperand(1).getReg()).addImm(1);
7056 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7057 MI->getOperand(0).getReg())
7058 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7060 llvm_unreachable("Unexpected instr type to insert");
7063 MI->eraseFromParent(); // The pseudo instruction is gone now.
7067 //===----------------------------------------------------------------------===//
7068 // Target Optimization Hooks
7069 //===----------------------------------------------------------------------===//
7071 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7072 DAGCombinerInfo &DCI) const {
7073 if (DCI.isAfterLegalizeVectorOps())
7076 EVT VT = Op.getValueType();
7078 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
7079 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
7080 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec()) ||
7081 (VT == MVT::v2f64 && PPCSubTarget.hasVSX())) {
7083 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7084 // For the reciprocal, we need to find the zero of the function:
7085 // F(X) = A X - 1 [which has a zero at X = 1/A]
7087 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7088 // does not require additional intermediate precision]
7090 // Convergence is quadratic, so we essentially double the number of digits
7091 // correct after every iteration. The minimum architected relative
7092 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7093 // 23 digits and double has 52 digits.
7094 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
7095 if (VT.getScalarType() == MVT::f64)
7098 SelectionDAG &DAG = DCI.DAG;
7102 DAG.getConstantFP(1.0, VT.getScalarType());
7103 if (VT.isVector()) {
7104 assert(VT.getVectorNumElements() == 4 &&
7105 "Unknown vector type");
7106 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7107 FPOne, FPOne, FPOne, FPOne);
7110 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7111 DCI.AddToWorklist(Est.getNode());
7113 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7114 for (int i = 0; i < Iterations; ++i) {
7115 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7116 DCI.AddToWorklist(NewEst.getNode());
7118 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7119 DCI.AddToWorklist(NewEst.getNode());
7121 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7122 DCI.AddToWorklist(NewEst.getNode());
7124 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7125 DCI.AddToWorklist(Est.getNode());
7134 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7135 DAGCombinerInfo &DCI) const {
7136 if (DCI.isAfterLegalizeVectorOps())
7139 EVT VT = Op.getValueType();
7141 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
7142 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
7143 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec()) ||
7144 (VT == MVT::v2f64 && PPCSubTarget.hasVSX())) {
7146 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7147 // For the reciprocal sqrt, we need to find the zero of the function:
7148 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7150 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7151 // As a result, we precompute A/2 prior to the iteration loop.
7153 // Convergence is quadratic, so we essentially double the number of digits
7154 // correct after every iteration. The minimum architected relative
7155 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7156 // 23 digits and double has 52 digits.
7157 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
7158 if (VT.getScalarType() == MVT::f64)
7161 SelectionDAG &DAG = DCI.DAG;
7164 SDValue FPThreeHalves =
7165 DAG.getConstantFP(1.5, VT.getScalarType());
7166 if (VT.isVector()) {
7167 assert(VT.getVectorNumElements() == 4 &&
7168 "Unknown vector type");
7169 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7170 FPThreeHalves, FPThreeHalves,
7171 FPThreeHalves, FPThreeHalves);
7174 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7175 DCI.AddToWorklist(Est.getNode());
7177 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7178 // this entire sequence requires only one FP constant.
7179 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7180 DCI.AddToWorklist(HalfArg.getNode());
7182 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7183 DCI.AddToWorklist(HalfArg.getNode());
7185 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7186 for (int i = 0; i < Iterations; ++i) {
7187 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7188 DCI.AddToWorklist(NewEst.getNode());
7190 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7191 DCI.AddToWorklist(NewEst.getNode());
7193 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7194 DCI.AddToWorklist(NewEst.getNode());
7196 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7197 DCI.AddToWorklist(Est.getNode());
7206 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7207 // not enforce equality of the chain operands.
7208 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7209 unsigned Bytes, int Dist,
7210 SelectionDAG &DAG) {
7211 EVT VT = LS->getMemoryVT();
7212 if (VT.getSizeInBits() / 8 != Bytes)
7215 SDValue Loc = LS->getBasePtr();
7216 SDValue BaseLoc = Base->getBasePtr();
7217 if (Loc.getOpcode() == ISD::FrameIndex) {
7218 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7220 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7221 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7222 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7223 int FS = MFI->getObjectSize(FI);
7224 int BFS = MFI->getObjectSize(BFI);
7225 if (FS != BFS || FS != (int)Bytes) return false;
7226 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7230 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7231 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7234 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7235 const GlobalValue *GV1 = NULL;
7236 const GlobalValue *GV2 = NULL;
7237 int64_t Offset1 = 0;
7238 int64_t Offset2 = 0;
7239 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7240 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7241 if (isGA1 && isGA2 && GV1 == GV2)
7242 return Offset1 == (Offset2 + Dist*Bytes);
7246 // Return true is there is a nearyby consecutive load to the one provided
7247 // (regardless of alignment). We search up and down the chain, looking though
7248 // token factors and other loads (but nothing else). As a result, a true
7249 // results indicates that it is safe to create a new consecutive load adjacent
7250 // to the load provided.
7251 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7252 SDValue Chain = LD->getChain();
7253 EVT VT = LD->getMemoryVT();
7255 SmallSet<SDNode *, 16> LoadRoots;
7256 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7257 SmallSet<SDNode *, 16> Visited;
7259 // First, search up the chain, branching to follow all token-factor operands.
7260 // If we find a consecutive load, then we're done, otherwise, record all
7261 // nodes just above the top-level loads and token factors.
7262 while (!Queue.empty()) {
7263 SDNode *ChainNext = Queue.pop_back_val();
7264 if (!Visited.insert(ChainNext))
7267 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7268 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7271 if (!Visited.count(ChainLD->getChain().getNode()))
7272 Queue.push_back(ChainLD->getChain().getNode());
7273 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7274 for (SDNode::op_iterator O = ChainNext->op_begin(),
7275 OE = ChainNext->op_end(); O != OE; ++O)
7276 if (!Visited.count(O->getNode()))
7277 Queue.push_back(O->getNode());
7279 LoadRoots.insert(ChainNext);
7282 // Second, search down the chain, starting from the top-level nodes recorded
7283 // in the first phase. These top-level nodes are the nodes just above all
7284 // loads and token factors. Starting with their uses, recursively look though
7285 // all loads (just the chain uses) and token factors to find a consecutive
7290 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7291 IE = LoadRoots.end(); I != IE; ++I) {
7292 Queue.push_back(*I);
7294 while (!Queue.empty()) {
7295 SDNode *LoadRoot = Queue.pop_back_val();
7296 if (!Visited.insert(LoadRoot))
7299 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7300 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7303 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7304 UE = LoadRoot->use_end(); UI != UE; ++UI)
7305 if (((isa<LoadSDNode>(*UI) &&
7306 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7307 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7308 Queue.push_back(*UI);
7315 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7316 DAGCombinerInfo &DCI) const {
7317 SelectionDAG &DAG = DCI.DAG;
7320 assert(PPCSubTarget.useCRBits() &&
7321 "Expecting to be tracking CR bits");
7322 // If we're tracking CR bits, we need to be careful that we don't have:
7323 // trunc(binary-ops(zext(x), zext(y)))
7325 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7326 // such that we're unnecessarily moving things into GPRs when it would be
7327 // better to keep them in CR bits.
7329 // Note that trunc here can be an actual i1 trunc, or can be the effective
7330 // truncation that comes from a setcc or select_cc.
7331 if (N->getOpcode() == ISD::TRUNCATE &&
7332 N->getValueType(0) != MVT::i1)
7335 if (N->getOperand(0).getValueType() != MVT::i32 &&
7336 N->getOperand(0).getValueType() != MVT::i64)
7339 if (N->getOpcode() == ISD::SETCC ||
7340 N->getOpcode() == ISD::SELECT_CC) {
7341 // If we're looking at a comparison, then we need to make sure that the
7342 // high bits (all except for the first) don't matter the result.
7344 cast<CondCodeSDNode>(N->getOperand(
7345 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7346 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7348 if (ISD::isSignedIntSetCC(CC)) {
7349 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7350 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7352 } else if (ISD::isUnsignedIntSetCC(CC)) {
7353 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7354 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7355 !DAG.MaskedValueIsZero(N->getOperand(1),
7356 APInt::getHighBitsSet(OpBits, OpBits-1)))
7359 // This is neither a signed nor an unsigned comparison, just make sure
7360 // that the high bits are equal.
7361 APInt Op1Zero, Op1One;
7362 APInt Op2Zero, Op2One;
7363 DAG.ComputeMaskedBits(N->getOperand(0), Op1Zero, Op1One);
7364 DAG.ComputeMaskedBits(N->getOperand(1), Op2Zero, Op2One);
7366 // We don't really care about what is known about the first bit (if
7367 // anything), so clear it in all masks prior to comparing them.
7368 Op1Zero.clearBit(0); Op1One.clearBit(0);
7369 Op2Zero.clearBit(0); Op2One.clearBit(0);
7371 if (Op1Zero != Op2Zero || Op1One != Op2One)
7376 // We now know that the higher-order bits are irrelevant, we just need to
7377 // make sure that all of the intermediate operations are bit operations, and
7378 // all inputs are extensions.
7379 if (N->getOperand(0).getOpcode() != ISD::AND &&
7380 N->getOperand(0).getOpcode() != ISD::OR &&
7381 N->getOperand(0).getOpcode() != ISD::XOR &&
7382 N->getOperand(0).getOpcode() != ISD::SELECT &&
7383 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7384 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7385 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7386 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7387 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7390 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7391 N->getOperand(1).getOpcode() != ISD::AND &&
7392 N->getOperand(1).getOpcode() != ISD::OR &&
7393 N->getOperand(1).getOpcode() != ISD::XOR &&
7394 N->getOperand(1).getOpcode() != ISD::SELECT &&
7395 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7396 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7397 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7398 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7399 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7402 SmallVector<SDValue, 4> Inputs;
7403 SmallVector<SDValue, 8> BinOps, PromOps;
7404 SmallPtrSet<SDNode *, 16> Visited;
7406 for (unsigned i = 0; i < 2; ++i) {
7407 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7408 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7409 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7410 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7411 isa<ConstantSDNode>(N->getOperand(i)))
7412 Inputs.push_back(N->getOperand(i));
7414 BinOps.push_back(N->getOperand(i));
7416 if (N->getOpcode() == ISD::TRUNCATE)
7420 // Visit all inputs, collect all binary operations (and, or, xor and
7421 // select) that are all fed by extensions.
7422 while (!BinOps.empty()) {
7423 SDValue BinOp = BinOps.back();
7426 if (!Visited.insert(BinOp.getNode()))
7429 PromOps.push_back(BinOp);
7431 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7432 // The condition of the select is not promoted.
7433 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7435 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7438 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7439 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7440 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7441 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7442 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7443 Inputs.push_back(BinOp.getOperand(i));
7444 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7445 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7446 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7447 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7448 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7449 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7450 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7451 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7452 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7453 BinOps.push_back(BinOp.getOperand(i));
7455 // We have an input that is not an extension or another binary
7456 // operation; we'll abort this transformation.
7462 // Make sure that this is a self-contained cluster of operations (which
7463 // is not quite the same thing as saying that everything has only one
7465 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7466 if (isa<ConstantSDNode>(Inputs[i]))
7469 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7470 UE = Inputs[i].getNode()->use_end();
7473 if (User != N && !Visited.count(User))
7476 // Make sure that we're not going to promote the non-output-value
7477 // operand(s) or SELECT or SELECT_CC.
7478 // FIXME: Although we could sometimes handle this, and it does occur in
7479 // practice that one of the condition inputs to the select is also one of
7480 // the outputs, we currently can't deal with this.
7481 if (User->getOpcode() == ISD::SELECT) {
7482 if (User->getOperand(0) == Inputs[i])
7484 } else if (User->getOpcode() == ISD::SELECT_CC) {
7485 if (User->getOperand(0) == Inputs[i] ||
7486 User->getOperand(1) == Inputs[i])
7492 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7493 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7494 UE = PromOps[i].getNode()->use_end();
7497 if (User != N && !Visited.count(User))
7500 // Make sure that we're not going to promote the non-output-value
7501 // operand(s) or SELECT or SELECT_CC.
7502 // FIXME: Although we could sometimes handle this, and it does occur in
7503 // practice that one of the condition inputs to the select is also one of
7504 // the outputs, we currently can't deal with this.
7505 if (User->getOpcode() == ISD::SELECT) {
7506 if (User->getOperand(0) == PromOps[i])
7508 } else if (User->getOpcode() == ISD::SELECT_CC) {
7509 if (User->getOperand(0) == PromOps[i] ||
7510 User->getOperand(1) == PromOps[i])
7516 // Replace all inputs with the extension operand.
7517 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7518 // Constants may have users outside the cluster of to-be-promoted nodes,
7519 // and so we need to replace those as we do the promotions.
7520 if (isa<ConstantSDNode>(Inputs[i]))
7523 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7526 // Replace all operations (these are all the same, but have a different
7527 // (i1) return type). DAG.getNode will validate that the types of
7528 // a binary operator match, so go through the list in reverse so that
7529 // we've likely promoted both operands first. Any intermediate truncations or
7530 // extensions disappear.
7531 while (!PromOps.empty()) {
7532 SDValue PromOp = PromOps.back();
7535 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7536 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7537 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7538 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7539 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7540 PromOp.getOperand(0).getValueType() != MVT::i1) {
7541 // The operand is not yet ready (see comment below).
7542 PromOps.insert(PromOps.begin(), PromOp);
7546 SDValue RepValue = PromOp.getOperand(0);
7547 if (isa<ConstantSDNode>(RepValue))
7548 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7550 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7555 switch (PromOp.getOpcode()) {
7556 default: C = 0; break;
7557 case ISD::SELECT: C = 1; break;
7558 case ISD::SELECT_CC: C = 2; break;
7561 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7562 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7563 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7564 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7565 // The to-be-promoted operands of this node have not yet been
7566 // promoted (this should be rare because we're going through the
7567 // list backward, but if one of the operands has several users in
7568 // this cluster of to-be-promoted nodes, it is possible).
7569 PromOps.insert(PromOps.begin(), PromOp);
7573 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7574 PromOp.getNode()->op_end());
7576 // If there are any constant inputs, make sure they're replaced now.
7577 for (unsigned i = 0; i < 2; ++i)
7578 if (isa<ConstantSDNode>(Ops[C+i]))
7579 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7581 DAG.ReplaceAllUsesOfValueWith(PromOp,
7582 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1,
7583 Ops.data(), Ops.size()));
7586 // Now we're left with the initial truncation itself.
7587 if (N->getOpcode() == ISD::TRUNCATE)
7588 return N->getOperand(0);
7590 // Otherwise, this is a comparison. The operands to be compared have just
7591 // changed type (to i1), but everything else is the same.
7592 return SDValue(N, 0);
7595 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7596 DAGCombinerInfo &DCI) const {
7597 SelectionDAG &DAG = DCI.DAG;
7600 // If we're tracking CR bits, we need to be careful that we don't have:
7601 // zext(binary-ops(trunc(x), trunc(y)))
7603 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7604 // such that we're unnecessarily moving things into CR bits that can more
7605 // efficiently stay in GPRs. Note that if we're not certain that the high
7606 // bits are set as required by the final extension, we still may need to do
7607 // some masking to get the proper behavior.
7609 // This same functionality is important on PPC64 when dealing with
7610 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7611 // the return values of functions. Because it is so similar, it is handled
7614 if (N->getValueType(0) != MVT::i32 &&
7615 N->getValueType(0) != MVT::i64)
7618 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7619 PPCSubTarget.useCRBits()) ||
7620 (N->getOperand(0).getValueType() == MVT::i32 &&
7621 PPCSubTarget.isPPC64())))
7624 if (N->getOperand(0).getOpcode() != ISD::AND &&
7625 N->getOperand(0).getOpcode() != ISD::OR &&
7626 N->getOperand(0).getOpcode() != ISD::XOR &&
7627 N->getOperand(0).getOpcode() != ISD::SELECT &&
7628 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7631 SmallVector<SDValue, 4> Inputs;
7632 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7633 SmallPtrSet<SDNode *, 16> Visited;
7635 // Visit all inputs, collect all binary operations (and, or, xor and
7636 // select) that are all fed by truncations.
7637 while (!BinOps.empty()) {
7638 SDValue BinOp = BinOps.back();
7641 if (!Visited.insert(BinOp.getNode()))
7644 PromOps.push_back(BinOp);
7646 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7647 // The condition of the select is not promoted.
7648 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7650 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7653 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7654 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7655 Inputs.push_back(BinOp.getOperand(i));
7656 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7657 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7658 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7659 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7660 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7661 BinOps.push_back(BinOp.getOperand(i));
7663 // We have an input that is not a truncation or another binary
7664 // operation; we'll abort this transformation.
7670 // Make sure that this is a self-contained cluster of operations (which
7671 // is not quite the same thing as saying that everything has only one
7673 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7674 if (isa<ConstantSDNode>(Inputs[i]))
7677 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7678 UE = Inputs[i].getNode()->use_end();
7681 if (User != N && !Visited.count(User))
7684 // Make sure that we're not going to promote the non-output-value
7685 // operand(s) or SELECT or SELECT_CC.
7686 // FIXME: Although we could sometimes handle this, and it does occur in
7687 // practice that one of the condition inputs to the select is also one of
7688 // the outputs, we currently can't deal with this.
7689 if (User->getOpcode() == ISD::SELECT) {
7690 if (User->getOperand(0) == Inputs[i])
7692 } else if (User->getOpcode() == ISD::SELECT_CC) {
7693 if (User->getOperand(0) == Inputs[i] ||
7694 User->getOperand(1) == Inputs[i])
7700 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7701 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7702 UE = PromOps[i].getNode()->use_end();
7705 if (User != N && !Visited.count(User))
7708 // Make sure that we're not going to promote the non-output-value
7709 // operand(s) or SELECT or SELECT_CC.
7710 // FIXME: Although we could sometimes handle this, and it does occur in
7711 // practice that one of the condition inputs to the select is also one of
7712 // the outputs, we currently can't deal with this.
7713 if (User->getOpcode() == ISD::SELECT) {
7714 if (User->getOperand(0) == PromOps[i])
7716 } else if (User->getOpcode() == ISD::SELECT_CC) {
7717 if (User->getOperand(0) == PromOps[i] ||
7718 User->getOperand(1) == PromOps[i])
7724 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7725 bool ReallyNeedsExt = false;
7726 if (N->getOpcode() != ISD::ANY_EXTEND) {
7727 // If all of the inputs are not already sign/zero extended, then
7728 // we'll still need to do that at the end.
7729 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7730 if (isa<ConstantSDNode>(Inputs[i]))
7734 Inputs[i].getOperand(0).getValueSizeInBits();
7735 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7737 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7738 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7739 APInt::getHighBitsSet(OpBits,
7740 OpBits-PromBits))) ||
7741 (N->getOpcode() == ISD::SIGN_EXTEND &&
7742 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7743 (OpBits-(PromBits-1)))) {
7744 ReallyNeedsExt = true;
7750 // Replace all inputs, either with the truncation operand, or a
7751 // truncation or extension to the final output type.
7752 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7753 // Constant inputs need to be replaced with the to-be-promoted nodes that
7754 // use them because they might have users outside of the cluster of
7756 if (isa<ConstantSDNode>(Inputs[i]))
7759 SDValue InSrc = Inputs[i].getOperand(0);
7760 if (Inputs[i].getValueType() == N->getValueType(0))
7761 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7762 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7763 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7764 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7765 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7766 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7767 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7769 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7770 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7773 // Replace all operations (these are all the same, but have a different
7774 // (promoted) return type). DAG.getNode will validate that the types of
7775 // a binary operator match, so go through the list in reverse so that
7776 // we've likely promoted both operands first.
7777 while (!PromOps.empty()) {
7778 SDValue PromOp = PromOps.back();
7782 switch (PromOp.getOpcode()) {
7783 default: C = 0; break;
7784 case ISD::SELECT: C = 1; break;
7785 case ISD::SELECT_CC: C = 2; break;
7788 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7789 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7790 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7791 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7792 // The to-be-promoted operands of this node have not yet been
7793 // promoted (this should be rare because we're going through the
7794 // list backward, but if one of the operands has several users in
7795 // this cluster of to-be-promoted nodes, it is possible).
7796 PromOps.insert(PromOps.begin(), PromOp);
7800 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7801 PromOp.getNode()->op_end());
7803 // If this node has constant inputs, then they'll need to be promoted here.
7804 for (unsigned i = 0; i < 2; ++i) {
7805 if (!isa<ConstantSDNode>(Ops[C+i]))
7807 if (Ops[C+i].getValueType() == N->getValueType(0))
7810 if (N->getOpcode() == ISD::SIGN_EXTEND)
7811 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7812 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7813 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7815 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7818 DAG.ReplaceAllUsesOfValueWith(PromOp,
7819 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0),
7820 Ops.data(), Ops.size()));
7823 // Now we're left with the initial extension itself.
7824 if (!ReallyNeedsExt)
7825 return N->getOperand(0);
7827 // To zero extend, just mask off everything except for the first bit (in the
7829 if (N->getOpcode() == ISD::ZERO_EXTEND)
7830 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7831 DAG.getConstant(APInt::getLowBitsSet(
7832 N->getValueSizeInBits(0), PromBits),
7833 N->getValueType(0)));
7835 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7836 "Invalid extension type");
7837 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7839 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7840 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7841 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7842 N->getOperand(0), ShiftCst), ShiftCst);
7845 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7846 DAGCombinerInfo &DCI) const {
7847 const TargetMachine &TM = getTargetMachine();
7848 SelectionDAG &DAG = DCI.DAG;
7850 switch (N->getOpcode()) {
7853 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7854 if (C->isNullValue()) // 0 << V -> 0.
7855 return N->getOperand(0);
7859 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7860 if (C->isNullValue()) // 0 >>u V -> 0.
7861 return N->getOperand(0);
7865 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7866 if (C->isNullValue() || // 0 >>s V -> 0.
7867 C->isAllOnesValue()) // -1 >>s V -> -1.
7868 return N->getOperand(0);
7871 case ISD::SIGN_EXTEND:
7872 case ISD::ZERO_EXTEND:
7873 case ISD::ANY_EXTEND:
7874 return DAGCombineExtBoolTrunc(N, DCI);
7877 case ISD::SELECT_CC:
7878 return DAGCombineTruncBoolExt(N, DCI);
7880 assert(TM.Options.UnsafeFPMath &&
7881 "Reciprocal estimates require UnsafeFPMath");
7883 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7885 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7886 if (RV.getNode() != 0) {
7887 DCI.AddToWorklist(RV.getNode());
7888 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7889 N->getOperand(0), RV);
7891 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7892 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7894 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7896 if (RV.getNode() != 0) {
7897 DCI.AddToWorklist(RV.getNode());
7898 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7899 N->getValueType(0), RV);
7900 DCI.AddToWorklist(RV.getNode());
7901 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7902 N->getOperand(0), RV);
7904 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7905 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7907 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7909 if (RV.getNode() != 0) {
7910 DCI.AddToWorklist(RV.getNode());
7911 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7912 N->getValueType(0), RV,
7913 N->getOperand(1).getOperand(1));
7914 DCI.AddToWorklist(RV.getNode());
7915 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7916 N->getOperand(0), RV);
7920 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7921 if (RV.getNode() != 0) {
7922 DCI.AddToWorklist(RV.getNode());
7923 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7924 N->getOperand(0), RV);
7930 assert(TM.Options.UnsafeFPMath &&
7931 "Reciprocal estimates require UnsafeFPMath");
7933 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7935 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7936 if (RV.getNode() != 0) {
7937 DCI.AddToWorklist(RV.getNode());
7938 RV = DAGCombineFastRecip(RV, DCI);
7939 if (RV.getNode() != 0) {
7940 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
7941 // this case and force the answer to 0.
7943 EVT VT = RV.getValueType();
7945 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
7946 if (VT.isVector()) {
7947 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
7948 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
7952 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
7953 N->getOperand(0), Zero, ISD::SETEQ);
7954 DCI.AddToWorklist(ZeroCmp.getNode());
7955 DCI.AddToWorklist(RV.getNode());
7957 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
7965 case ISD::SINT_TO_FP:
7966 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
7967 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7968 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
7969 // We allow the src/dst to be either f32/f64, but the intermediate
7970 // type must be i64.
7971 if (N->getOperand(0).getValueType() == MVT::i64 &&
7972 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7973 SDValue Val = N->getOperand(0).getOperand(0);
7974 if (Val.getValueType() == MVT::f32) {
7975 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7976 DCI.AddToWorklist(Val.getNode());
7979 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7980 DCI.AddToWorklist(Val.getNode());
7981 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7982 DCI.AddToWorklist(Val.getNode());
7983 if (N->getValueType(0) == MVT::f32) {
7984 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7985 DAG.getIntPtrConstant(0));
7986 DCI.AddToWorklist(Val.getNode());
7989 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7990 // If the intermediate type is i32, we can avoid the load/store here
7997 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7998 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7999 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8000 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8001 N->getOperand(1).getValueType() == MVT::i32 &&
8002 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8003 SDValue Val = N->getOperand(1).getOperand(0);
8004 if (Val.getValueType() == MVT::f32) {
8005 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8006 DCI.AddToWorklist(Val.getNode());
8008 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8009 DCI.AddToWorklist(Val.getNode());
8012 N->getOperand(0), Val, N->getOperand(2),
8013 DAG.getValueType(N->getOperand(1).getValueType())
8016 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8017 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
8018 cast<StoreSDNode>(N)->getMemoryVT(),
8019 cast<StoreSDNode>(N)->getMemOperand());
8020 DCI.AddToWorklist(Val.getNode());
8024 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8025 if (cast<StoreSDNode>(N)->isUnindexed() &&
8026 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8027 N->getOperand(1).getNode()->hasOneUse() &&
8028 (N->getOperand(1).getValueType() == MVT::i32 ||
8029 N->getOperand(1).getValueType() == MVT::i16 ||
8030 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8031 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8032 N->getOperand(1).getValueType() == MVT::i64))) {
8033 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8034 // Do an any-extend to 32-bits if this is a half-word input.
8035 if (BSwapOp.getValueType() == MVT::i16)
8036 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8039 N->getOperand(0), BSwapOp, N->getOperand(2),
8040 DAG.getValueType(N->getOperand(1).getValueType())
8043 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8044 Ops, array_lengthof(Ops),
8045 cast<StoreSDNode>(N)->getMemoryVT(),
8046 cast<StoreSDNode>(N)->getMemOperand());
8050 LoadSDNode *LD = cast<LoadSDNode>(N);
8051 EVT VT = LD->getValueType(0);
8052 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8053 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8054 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8055 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8056 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8057 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8058 LD->getAlignment() < ABIAlignment) {
8059 // This is a type-legal unaligned Altivec load.
8060 SDValue Chain = LD->getChain();
8061 SDValue Ptr = LD->getBasePtr();
8063 // This implements the loading of unaligned vectors as described in
8064 // the venerable Apple Velocity Engine overview. Specifically:
8065 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8066 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8068 // The general idea is to expand a sequence of one or more unaligned
8069 // loads into a alignment-based permutation-control instruction (lvsl),
8070 // a series of regular vector loads (which always truncate their
8071 // input address to an aligned address), and a series of permutations.
8072 // The results of these permutations are the requested loaded values.
8073 // The trick is that the last "extra" load is not taken from the address
8074 // you might suspect (sizeof(vector) bytes after the last requested
8075 // load), but rather sizeof(vector) - 1 bytes after the last
8076 // requested vector. The point of this is to avoid a page fault if the
8077 // base address happened to be aligned. This works because if the base
8078 // address is aligned, then adding less than a full vector length will
8079 // cause the last vector in the sequence to be (re)loaded. Otherwise,
8080 // the next vector will be fetched as you might suspect was necessary.
8082 // We might be able to reuse the permutation generation from
8083 // a different base address offset from this one by an aligned amount.
8084 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8085 // optimization later.
8086 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
8087 DAG, dl, MVT::v16i8);
8089 // Refine the alignment of the original load (a "new" load created here
8090 // which was identical to the first except for the alignment would be
8091 // merged with the existing node regardless).
8092 MachineFunction &MF = DAG.getMachineFunction();
8093 MachineMemOperand *MMO =
8094 MF.getMachineMemOperand(LD->getPointerInfo(),
8095 LD->getMemOperand()->getFlags(),
8096 LD->getMemoryVT().getStoreSize(),
8098 LD->refineAlignment(MMO);
8099 SDValue BaseLoad = SDValue(LD, 0);
8101 // Note that the value of IncOffset (which is provided to the next
8102 // load's pointer info offset value, and thus used to calculate the
8103 // alignment), and the value of IncValue (which is actually used to
8104 // increment the pointer value) are different! This is because we
8105 // require the next load to appear to be aligned, even though it
8106 // is actually offset from the base pointer by a lesser amount.
8107 int IncOffset = VT.getSizeInBits() / 8;
8108 int IncValue = IncOffset;
8110 // Walk (both up and down) the chain looking for another load at the real
8111 // (aligned) offset (the alignment of the other load does not matter in
8112 // this case). If found, then do not use the offset reduction trick, as
8113 // that will prevent the loads from being later combined (as they would
8114 // otherwise be duplicates).
8115 if (!findConsecutiveLoad(LD, DAG))
8118 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8119 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8122 DAG.getLoad(VT, dl, Chain, Ptr,
8123 LD->getPointerInfo().getWithOffset(IncOffset),
8124 LD->isVolatile(), LD->isNonTemporal(),
8125 LD->isInvariant(), ABIAlignment);
8127 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8128 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8130 if (BaseLoad.getValueType() != MVT::v4i32)
8131 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8133 if (ExtraLoad.getValueType() != MVT::v4i32)
8134 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8136 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8137 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8139 if (VT != MVT::v4i32)
8140 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8142 // Now we need to be really careful about how we update the users of the
8143 // original load. We cannot just call DCI.CombineTo (or
8144 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8145 // uses created here (the permutation for example) that need to stay.
8146 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8148 SDUse &Use = UI.getUse();
8150 // Note: BaseLoad is checked here because it might not be N, but a
8152 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8153 User == TF.getNode() || Use.getResNo() > 1) {
8158 SDValue To = Use.getResNo() ? TF : Perm;
8161 SmallVector<SDValue, 8> Ops;
8162 for (SDNode::op_iterator O = User->op_begin(),
8163 OE = User->op_end(); O != OE; ++O) {
8170 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
8173 return SDValue(N, 0);
8177 case ISD::INTRINSIC_WO_CHAIN:
8178 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
8179 Intrinsic::ppc_altivec_lvsl &&
8180 N->getOperand(1)->getOpcode() == ISD::ADD) {
8181 SDValue Add = N->getOperand(1);
8183 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8184 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8185 Add.getValueType().getScalarType().getSizeInBits()))) {
8186 SDNode *BasePtr = Add->getOperand(0).getNode();
8187 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8188 UE = BasePtr->use_end(); UI != UE; ++UI) {
8189 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8190 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8191 Intrinsic::ppc_altivec_lvsl) {
8192 // We've found another LVSL, and this address if an aligned
8193 // multiple of that one. The results will be the same, so use the
8194 // one we've just found instead.
8196 return SDValue(*UI, 0);
8204 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8205 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8206 N->getOperand(0).hasOneUse() &&
8207 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8208 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8209 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8210 N->getValueType(0) == MVT::i64))) {
8211 SDValue Load = N->getOperand(0);
8212 LoadSDNode *LD = cast<LoadSDNode>(Load);
8213 // Create the byte-swapping load.
8215 LD->getChain(), // Chain
8216 LD->getBasePtr(), // Ptr
8217 DAG.getValueType(N->getValueType(0)) // VT
8220 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8221 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8222 MVT::i64 : MVT::i32, MVT::Other),
8223 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
8225 // If this is an i16 load, insert the truncate.
8226 SDValue ResVal = BSLoad;
8227 if (N->getValueType(0) == MVT::i16)
8228 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8230 // First, combine the bswap away. This makes the value produced by the
8232 DCI.CombineTo(N, ResVal);
8234 // Next, combine the load away, we give it a bogus result value but a real
8235 // chain result. The result value is dead because the bswap is dead.
8236 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8238 // Return N so it doesn't get rechecked!
8239 return SDValue(N, 0);
8243 case PPCISD::VCMP: {
8244 // If a VCMPo node already exists with exactly the same operands as this
8245 // node, use its result instead of this node (VCMPo computes both a CR6 and
8246 // a normal output).
8248 if (!N->getOperand(0).hasOneUse() &&
8249 !N->getOperand(1).hasOneUse() &&
8250 !N->getOperand(2).hasOneUse()) {
8252 // Scan all of the users of the LHS, looking for VCMPo's that match.
8253 SDNode *VCMPoNode = 0;
8255 SDNode *LHSN = N->getOperand(0).getNode();
8256 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8258 if (UI->getOpcode() == PPCISD::VCMPo &&
8259 UI->getOperand(1) == N->getOperand(1) &&
8260 UI->getOperand(2) == N->getOperand(2) &&
8261 UI->getOperand(0) == N->getOperand(0)) {
8266 // If there is no VCMPo node, or if the flag value has a single use, don't
8268 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8271 // Look at the (necessarily single) use of the flag value. If it has a
8272 // chain, this transformation is more complex. Note that multiple things
8273 // could use the value result, which we should ignore.
8274 SDNode *FlagUser = 0;
8275 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8276 FlagUser == 0; ++UI) {
8277 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8279 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8280 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8287 // If the user is a MFOCRF instruction, we know this is safe.
8288 // Otherwise we give up for right now.
8289 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8290 return SDValue(VCMPoNode, 0);
8295 SDValue Cond = N->getOperand(1);
8296 SDValue Target = N->getOperand(2);
8298 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8299 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8300 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8302 // We now need to make the intrinsic dead (it cannot be instruction
8304 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8305 assert(Cond.getNode()->hasOneUse() &&
8306 "Counter decrement has more than one use");
8308 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8309 N->getOperand(0), Target);
8314 // If this is a branch on an altivec predicate comparison, lower this so
8315 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8316 // lowering is done pre-legalize, because the legalizer lowers the predicate
8317 // compare down to code that is difficult to reassemble.
8318 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8319 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8321 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8322 // value. If so, pass-through the AND to get to the intrinsic.
8323 if (LHS.getOpcode() == ISD::AND &&
8324 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8325 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8326 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8327 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8328 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8330 LHS = LHS.getOperand(0);
8332 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8333 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8334 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8335 isa<ConstantSDNode>(RHS)) {
8336 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8337 "Counter decrement comparison is not EQ or NE");
8339 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8340 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8341 (CC == ISD::SETNE && !Val);
8343 // We now need to make the intrinsic dead (it cannot be instruction
8345 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8346 assert(LHS.getNode()->hasOneUse() &&
8347 "Counter decrement has more than one use");
8349 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8350 N->getOperand(0), N->getOperand(4));
8356 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8357 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8358 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8359 assert(isDot && "Can't compare against a vector result!");
8361 // If this is a comparison against something other than 0/1, then we know
8362 // that the condition is never/always true.
8363 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8364 if (Val != 0 && Val != 1) {
8365 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8366 return N->getOperand(0);
8367 // Always !=, turn it into an unconditional branch.
8368 return DAG.getNode(ISD::BR, dl, MVT::Other,
8369 N->getOperand(0), N->getOperand(4));
8372 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8374 // Create the PPCISD altivec 'dot' comparison node.
8376 LHS.getOperand(2), // LHS of compare
8377 LHS.getOperand(3), // RHS of compare
8378 DAG.getConstant(CompareOpc, MVT::i32)
8380 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8381 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
8383 // Unpack the result based on how the target uses it.
8384 PPC::Predicate CompOpc;
8385 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8386 default: // Can't happen, don't crash on invalid number though.
8387 case 0: // Branch on the value of the EQ bit of CR6.
8388 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8390 case 1: // Branch on the inverted value of the EQ bit of CR6.
8391 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8393 case 2: // Branch on the value of the LT bit of CR6.
8394 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8396 case 3: // Branch on the inverted value of the LT bit of CR6.
8397 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8401 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8402 DAG.getConstant(CompOpc, MVT::i32),
8403 DAG.getRegister(PPC::CR6, MVT::i32),
8404 N->getOperand(4), CompNode.getValue(1));
8413 //===----------------------------------------------------------------------===//
8414 // Inline Assembly Support
8415 //===----------------------------------------------------------------------===//
8417 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8420 const SelectionDAG &DAG,
8421 unsigned Depth) const {
8422 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8423 switch (Op.getOpcode()) {
8425 case PPCISD::LBRX: {
8426 // lhbrx is known to have the top bits cleared out.
8427 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8428 KnownZero = 0xFFFF0000;
8431 case ISD::INTRINSIC_WO_CHAIN: {
8432 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8434 case Intrinsic::ppc_altivec_vcmpbfp_p:
8435 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8436 case Intrinsic::ppc_altivec_vcmpequb_p:
8437 case Intrinsic::ppc_altivec_vcmpequh_p:
8438 case Intrinsic::ppc_altivec_vcmpequw_p:
8439 case Intrinsic::ppc_altivec_vcmpgefp_p:
8440 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8441 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8442 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8443 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8444 case Intrinsic::ppc_altivec_vcmpgtub_p:
8445 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8446 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8447 KnownZero = ~1U; // All bits but the low one are known to be zero.
8455 /// getConstraintType - Given a constraint, return the type of
8456 /// constraint it is for this target.
8457 PPCTargetLowering::ConstraintType
8458 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8459 if (Constraint.size() == 1) {
8460 switch (Constraint[0]) {
8467 return C_RegisterClass;
8469 // FIXME: While Z does indicate a memory constraint, it specifically
8470 // indicates an r+r address (used in conjunction with the 'y' modifier
8471 // in the replacement string). Currently, we're forcing the base
8472 // register to be r0 in the asm printer (which is interpreted as zero)
8473 // and forming the complete address in the second register. This is
8477 } else if (Constraint == "wc") { // individual CR bits.
8478 return C_RegisterClass;
8479 } else if (Constraint == "wa" || Constraint == "wd" ||
8480 Constraint == "wf" || Constraint == "ws") {
8481 return C_RegisterClass; // VSX registers.
8483 return TargetLowering::getConstraintType(Constraint);
8486 /// Examine constraint type and operand type and determine a weight value.
8487 /// This object must already have been set up with the operand type
8488 /// and the current alternative constraint selected.
8489 TargetLowering::ConstraintWeight
8490 PPCTargetLowering::getSingleConstraintMatchWeight(
8491 AsmOperandInfo &info, const char *constraint) const {
8492 ConstraintWeight weight = CW_Invalid;
8493 Value *CallOperandVal = info.CallOperandVal;
8494 // If we don't have a value, we can't do a match,
8495 // but allow it at the lowest weight.
8496 if (CallOperandVal == NULL)
8498 Type *type = CallOperandVal->getType();
8500 // Look at the constraint type.
8501 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8502 return CW_Register; // an individual CR bit.
8503 else if ((StringRef(constraint) == "wa" ||
8504 StringRef(constraint) == "wd" ||
8505 StringRef(constraint) == "wf") &&
8508 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8511 switch (*constraint) {
8513 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8516 if (type->isIntegerTy())
8517 weight = CW_Register;
8520 if (type->isFloatTy())
8521 weight = CW_Register;
8524 if (type->isDoubleTy())
8525 weight = CW_Register;
8528 if (type->isVectorTy())
8529 weight = CW_Register;
8532 weight = CW_Register;
8541 std::pair<unsigned, const TargetRegisterClass*>
8542 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8544 if (Constraint.size() == 1) {
8545 // GCC RS6000 Constraint Letters
8546 switch (Constraint[0]) {
8548 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
8549 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8550 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8552 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
8553 return std::make_pair(0U, &PPC::G8RCRegClass);
8554 return std::make_pair(0U, &PPC::GPRCRegClass);
8556 if (VT == MVT::f32 || VT == MVT::i32)
8557 return std::make_pair(0U, &PPC::F4RCRegClass);
8558 if (VT == MVT::f64 || VT == MVT::i64)
8559 return std::make_pair(0U, &PPC::F8RCRegClass);
8562 return std::make_pair(0U, &PPC::VRRCRegClass);
8564 return std::make_pair(0U, &PPC::CRRCRegClass);
8566 } else if (Constraint == "wc") { // an individual CR bit.
8567 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8568 } else if (Constraint == "wa" || Constraint == "wd" ||
8569 Constraint == "wf") {
8570 return std::make_pair(0U, &PPC::VSRCRegClass);
8571 } else if (Constraint == "ws") {
8572 return std::make_pair(0U, &PPC::VSFRCRegClass);
8575 std::pair<unsigned, const TargetRegisterClass*> R =
8576 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8578 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8579 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8580 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8582 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8583 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8584 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
8585 PPC::GPRCRegClass.contains(R.first)) {
8586 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8587 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8588 PPC::sub_32, &PPC::G8RCRegClass),
8589 &PPC::G8RCRegClass);
8596 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8597 /// vector. If it is invalid, don't add anything to Ops.
8598 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8599 std::string &Constraint,
8600 std::vector<SDValue>&Ops,
8601 SelectionDAG &DAG) const {
8602 SDValue Result(0,0);
8604 // Only support length 1 constraints.
8605 if (Constraint.length() > 1) return;
8607 char Letter = Constraint[0];
8618 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8619 if (!CST) return; // Must be an immediate to match.
8620 unsigned Value = CST->getZExtValue();
8622 default: llvm_unreachable("Unknown constraint letter!");
8623 case 'I': // "I" is a signed 16-bit constant.
8624 if ((short)Value == (int)Value)
8625 Result = DAG.getTargetConstant(Value, Op.getValueType());
8627 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8628 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8629 if ((short)Value == 0)
8630 Result = DAG.getTargetConstant(Value, Op.getValueType());
8632 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8633 if ((Value >> 16) == 0)
8634 Result = DAG.getTargetConstant(Value, Op.getValueType());
8636 case 'M': // "M" is a constant that is greater than 31.
8638 Result = DAG.getTargetConstant(Value, Op.getValueType());
8640 case 'N': // "N" is a positive constant that is an exact power of two.
8641 if ((int)Value > 0 && isPowerOf2_32(Value))
8642 Result = DAG.getTargetConstant(Value, Op.getValueType());
8644 case 'O': // "O" is the constant zero.
8646 Result = DAG.getTargetConstant(Value, Op.getValueType());
8648 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8649 if ((short)-Value == (int)-Value)
8650 Result = DAG.getTargetConstant(Value, Op.getValueType());
8657 if (Result.getNode()) {
8658 Ops.push_back(Result);
8662 // Handle standard constraint letters.
8663 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8666 // isLegalAddressingMode - Return true if the addressing mode represented
8667 // by AM is legal for this target, for a load/store of the specified type.
8668 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8670 // FIXME: PPC does not allow r+i addressing modes for vectors!
8672 // PPC allows a sign-extended 16-bit immediate field.
8673 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8676 // No global is ever allowed as a base.
8680 // PPC only support r+r,
8682 case 0: // "r+i" or just "i", depending on HasBaseReg.
8685 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8687 // Otherwise we have r+r or r+i.
8690 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8692 // Allow 2*r as r+r.
8695 // No other scales are supported.
8702 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8703 SelectionDAG &DAG) const {
8704 MachineFunction &MF = DAG.getMachineFunction();
8705 MachineFrameInfo *MFI = MF.getFrameInfo();
8706 MFI->setReturnAddressIsTaken(true);
8708 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8712 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8714 // Make sure the function does not optimize away the store of the RA to
8716 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8717 FuncInfo->setLRStoreRequired();
8718 bool isPPC64 = PPCSubTarget.isPPC64();
8719 bool isDarwinABI = PPCSubTarget.isDarwinABI();
8722 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8725 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8726 isPPC64? MVT::i64 : MVT::i32);
8727 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8728 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8730 MachinePointerInfo(), false, false, false, 0);
8733 // Just load the return address off the stack.
8734 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8735 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8736 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8739 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8740 SelectionDAG &DAG) const {
8742 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8744 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8745 bool isPPC64 = PtrVT == MVT::i64;
8747 MachineFunction &MF = DAG.getMachineFunction();
8748 MachineFrameInfo *MFI = MF.getFrameInfo();
8749 MFI->setFrameAddressIsTaken(true);
8751 // Naked functions never have a frame pointer, and so we use r1. For all
8752 // other functions, this decision must be delayed until during PEI.
8754 if (MF.getFunction()->getAttributes().hasAttribute(
8755 AttributeSet::FunctionIndex, Attribute::Naked))
8756 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8758 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8760 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8763 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8764 FrameAddr, MachinePointerInfo(), false, false,
8770 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8771 // The PowerPC target isn't yet aware of offsets.
8775 /// getOptimalMemOpType - Returns the target specific optimal type for load
8776 /// and store operations as a result of memset, memcpy, and memmove
8777 /// lowering. If DstAlign is zero that means it's safe to destination
8778 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8779 /// means there isn't a need to check it against alignment requirement,
8780 /// probably because the source does not need to be loaded. If 'IsMemset' is
8781 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8782 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8783 /// source is constant so it does not need to be loaded.
8784 /// It returns EVT::Other if the type should be determined using generic
8785 /// target-independent logic.
8786 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8787 unsigned DstAlign, unsigned SrcAlign,
8788 bool IsMemset, bool ZeroMemset,
8790 MachineFunction &MF) const {
8791 if (this->PPCSubTarget.isPPC64()) {
8798 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8801 if (DisablePPCUnaligned)
8804 // PowerPC supports unaligned memory access for simple non-vector types.
8805 // Although accessing unaligned addresses is not as efficient as accessing
8806 // aligned addresses, it is generally more efficient than manual expansion,
8807 // and generally only traps for software emulation when crossing page
8813 if (VT.getSimpleVT().isVector()) {
8814 if (PPCSubTarget.hasVSX()) {
8815 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8822 if (VT == MVT::ppcf128)
8831 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8832 VT = VT.getScalarType();
8837 switch (VT.getSimpleVT().SimpleTy) {
8849 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
8850 EVT VT , unsigned DefinedValues) const {
8851 if (VT == MVT::v2i64)
8854 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
8857 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
8858 if (DisableILPPref || PPCSubTarget.enableMachineScheduler())
8859 return TargetLowering::getSchedulingPreference(N);
8864 // Create a fast isel object.
8866 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
8867 const TargetLibraryInfo *LibInfo) const {
8868 return PPC::createFastISel(FuncInfo, LibInfo);