1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Support/CommandLine.h"
36 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
37 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
40 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
41 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
45 // Use _setjmp/_longjmp instead of setjmp/longjmp.
46 setUseUnderscoreSetJmp(true);
47 setUseUnderscoreLongJmp(true);
49 // Set up the register classes.
50 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
51 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
52 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC does not have truncstore for i1.
59 setStoreXAction(MVT::i1, Promote);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
74 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
76 // PowerPC has no intrinsics for these particular operations
77 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
78 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
79 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
81 // PowerPC has no SREM/UREM instructions
82 setOperationAction(ISD::SREM, MVT::i32, Expand);
83 setOperationAction(ISD::UREM, MVT::i32, Expand);
84 setOperationAction(ISD::SREM, MVT::i64, Expand);
85 setOperationAction(ISD::UREM, MVT::i64, Expand);
87 // We don't support sin/cos/sqrt/fmod
88 setOperationAction(ISD::FSIN , MVT::f64, Expand);
89 setOperationAction(ISD::FCOS , MVT::f64, Expand);
90 setOperationAction(ISD::FREM , MVT::f64, Expand);
91 setOperationAction(ISD::FSIN , MVT::f32, Expand);
92 setOperationAction(ISD::FCOS , MVT::f32, Expand);
93 setOperationAction(ISD::FREM , MVT::f32, Expand);
95 // If we're enabling GP optimizations, use hardware square root
96 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
97 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
98 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
101 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
102 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
104 // PowerPC does not have BSWAP, CTPOP or CTTZ
105 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
106 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
107 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
108 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
109 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
110 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
112 // PowerPC does not have ROTR
113 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
115 // PowerPC does not have Select
116 setOperationAction(ISD::SELECT, MVT::i32, Expand);
117 setOperationAction(ISD::SELECT, MVT::i64, Expand);
118 setOperationAction(ISD::SELECT, MVT::f32, Expand);
119 setOperationAction(ISD::SELECT, MVT::f64, Expand);
121 // PowerPC wants to turn select_cc of FP into fsel when possible.
122 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
123 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
125 // PowerPC wants to optimize integer setcc a bit
126 setOperationAction(ISD::SETCC, MVT::i32, Custom);
128 // PowerPC does not have BRCOND which requires SetCC
129 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
131 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
133 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
134 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
136 // PowerPC does not have [U|S]INT_TO_FP
137 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
138 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
140 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
141 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
142 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
143 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
145 // We cannot sextinreg(i1). Expand to shifts.
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
148 // Support label based line numbers.
149 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
150 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
151 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
152 setOperationAction(ISD::LABEL, MVT::Other, Expand);
154 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
155 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
156 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
157 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
160 // We want to legalize GlobalAddress and ConstantPool nodes into the
161 // appropriate instructions to materialize the address.
162 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
163 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
164 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
165 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
166 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
167 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
168 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
169 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
171 // RET must be custom lowered, to meet ABI requirements
172 setOperationAction(ISD::RET , MVT::Other, Custom);
174 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
175 setOperationAction(ISD::VASTART , MVT::Other, Custom);
177 // VAARG is custom lowered with ELF 32 ABI
178 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
179 setOperationAction(ISD::VAARG, MVT::Other, Custom);
181 setOperationAction(ISD::VAARG, MVT::Other, Expand);
183 // Use the default implementation.
184 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
185 setOperationAction(ISD::VAEND , MVT::Other, Expand);
186 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
187 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
188 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
189 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
191 // We want to custom lower some of our intrinsics.
192 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
194 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
195 // They also have instructions for converting between i64 and fp.
196 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
197 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
198 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
199 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
200 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
202 // FIXME: disable this lowered code. This generates 64-bit register values,
203 // and we don't model the fact that the top part is clobbered by calls. We
204 // need to flag these together so that the value isn't live across a call.
205 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
207 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
208 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
210 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
211 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
214 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
215 // 64 bit PowerPC implementations can support i64 types directly
216 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
217 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
218 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
220 // 32 bit PowerPC wants to expand i64 shifts itself.
221 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
222 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
223 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
226 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
227 // First set operation action for all vector types to expand. Then we
228 // will selectively turn on ones that can be effectively codegen'd.
229 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
230 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
231 // add/sub are legal for all supported vector VT's.
232 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
233 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
235 // We promote all shuffles to v16i8.
236 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
237 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
239 // We promote all non-typed operations to v4i32.
240 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
241 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
242 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
243 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
244 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
245 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
246 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
247 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
248 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
249 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
250 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
251 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
253 // No other operations are legal.
254 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
255 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
256 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
257 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
258 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
259 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
260 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
261 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
262 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
263 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
265 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
268 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
269 // with merges, splats, etc.
270 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
272 setOperationAction(ISD::AND , MVT::v4i32, Legal);
273 setOperationAction(ISD::OR , MVT::v4i32, Legal);
274 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
275 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
276 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
277 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
279 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
280 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
281 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
282 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
284 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
285 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
286 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
287 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
289 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
290 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
292 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
293 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
294 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
295 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
298 setSetCCResultType(MVT::i32);
299 setShiftAmountType(MVT::i32);
300 setSetCCResultContents(ZeroOrOneSetCCResult);
302 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
303 setStackPointerRegisterToSaveRestore(PPC::X1);
304 setExceptionPointerRegister(PPC::X3);
305 setExceptionSelectorRegister(PPC::X4);
307 setStackPointerRegisterToSaveRestore(PPC::R1);
308 setExceptionPointerRegister(PPC::R3);
309 setExceptionSelectorRegister(PPC::R4);
312 // We have target-specific dag combine patterns for the following nodes:
313 setTargetDAGCombine(ISD::SINT_TO_FP);
314 setTargetDAGCombine(ISD::STORE);
315 setTargetDAGCombine(ISD::BR_CC);
316 setTargetDAGCombine(ISD::BSWAP);
318 computeRegisterProperties();
321 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
324 case PPCISD::FSEL: return "PPCISD::FSEL";
325 case PPCISD::FCFID: return "PPCISD::FCFID";
326 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
327 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
328 case PPCISD::STFIWX: return "PPCISD::STFIWX";
329 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
330 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
331 case PPCISD::VPERM: return "PPCISD::VPERM";
332 case PPCISD::Hi: return "PPCISD::Hi";
333 case PPCISD::Lo: return "PPCISD::Lo";
334 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
335 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
336 case PPCISD::SRL: return "PPCISD::SRL";
337 case PPCISD::SRA: return "PPCISD::SRA";
338 case PPCISD::SHL: return "PPCISD::SHL";
339 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
340 case PPCISD::STD_32: return "PPCISD::STD_32";
341 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
342 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
343 case PPCISD::MTCTR: return "PPCISD::MTCTR";
344 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
345 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
346 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
347 case PPCISD::MFCR: return "PPCISD::MFCR";
348 case PPCISD::VCMP: return "PPCISD::VCMP";
349 case PPCISD::VCMPo: return "PPCISD::VCMPo";
350 case PPCISD::LBRX: return "PPCISD::LBRX";
351 case PPCISD::STBRX: return "PPCISD::STBRX";
352 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
356 //===----------------------------------------------------------------------===//
357 // Node matching predicates, for use by the tblgen matching code.
358 //===----------------------------------------------------------------------===//
360 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
361 static bool isFloatingPointZero(SDOperand Op) {
362 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
363 return CFP->getValueAPF().isZero();
364 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
365 // Maybe this has already been legalized into the constant pool?
366 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
367 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
368 return CFP->getValueAPF().isZero();
373 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
374 /// true if Op is undef or if it matches the specified value.
375 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
376 return Op.getOpcode() == ISD::UNDEF ||
377 cast<ConstantSDNode>(Op)->getValue() == Val;
380 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
381 /// VPKUHUM instruction.
382 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
384 for (unsigned i = 0; i != 16; ++i)
385 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
388 for (unsigned i = 0; i != 8; ++i)
389 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
390 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
396 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
397 /// VPKUWUM instruction.
398 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
400 for (unsigned i = 0; i != 16; i += 2)
401 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
402 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
405 for (unsigned i = 0; i != 8; i += 2)
406 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
407 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
408 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
409 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
415 /// isVMerge - Common function, used to match vmrg* shuffles.
417 static bool isVMerge(SDNode *N, unsigned UnitSize,
418 unsigned LHSStart, unsigned RHSStart) {
419 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
420 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
421 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
422 "Unsupported merge size!");
424 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
425 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
426 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
427 LHSStart+j+i*UnitSize) ||
428 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
429 RHSStart+j+i*UnitSize))
435 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
436 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
437 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
439 return isVMerge(N, UnitSize, 8, 24);
440 return isVMerge(N, UnitSize, 8, 8);
443 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
444 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
445 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
447 return isVMerge(N, UnitSize, 0, 16);
448 return isVMerge(N, UnitSize, 0, 0);
452 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
453 /// amount, otherwise return -1.
454 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
455 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
456 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
457 // Find the first non-undef value in the shuffle mask.
459 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
462 if (i == 16) return -1; // all undef.
464 // Otherwise, check to see if the rest of the elements are consequtively
465 // numbered from this value.
466 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
467 if (ShiftAmt < i) return -1;
471 // Check the rest of the elements to see if they are consequtive.
472 for (++i; i != 16; ++i)
473 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
476 // Check the rest of the elements to see if they are consequtive.
477 for (++i; i != 16; ++i)
478 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
485 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
486 /// specifies a splat of a single element that is suitable for input to
487 /// VSPLTB/VSPLTH/VSPLTW.
488 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
489 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
490 N->getNumOperands() == 16 &&
491 (EltSize == 1 || EltSize == 2 || EltSize == 4));
493 // This is a splat operation if each element of the permute is the same, and
494 // if the value doesn't reference the second vector.
495 unsigned ElementBase = 0;
496 SDOperand Elt = N->getOperand(0);
497 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
498 ElementBase = EltV->getValue();
500 return false; // FIXME: Handle UNDEF elements too!
502 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
505 // Check that they are consequtive.
506 for (unsigned i = 1; i != EltSize; ++i) {
507 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
508 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
512 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
513 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
514 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
515 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
516 "Invalid VECTOR_SHUFFLE mask!");
517 for (unsigned j = 0; j != EltSize; ++j)
518 if (N->getOperand(i+j) != N->getOperand(j))
525 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
527 bool PPC::isAllNegativeZeroVector(SDNode *N) {
528 assert(N->getOpcode() == ISD::BUILD_VECTOR);
529 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
530 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
531 return CFP->getValueAPF().isNegZero();
535 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
536 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
537 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
538 assert(isSplatShuffleMask(N, EltSize));
539 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
542 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
543 /// by using a vspltis[bhw] instruction of the specified element size, return
544 /// the constant being splatted. The ByteSize field indicates the number of
545 /// bytes of each element [124] -> [bhw].
546 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
547 SDOperand OpVal(0, 0);
549 // If ByteSize of the splat is bigger than the element size of the
550 // build_vector, then we have a case where we are checking for a splat where
551 // multiple elements of the buildvector are folded together into a single
552 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
553 unsigned EltSize = 16/N->getNumOperands();
554 if (EltSize < ByteSize) {
555 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
556 SDOperand UniquedVals[4];
557 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
559 // See if all of the elements in the buildvector agree across.
560 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
561 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
562 // If the element isn't a constant, bail fully out.
563 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
566 if (UniquedVals[i&(Multiple-1)].Val == 0)
567 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
568 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
569 return SDOperand(); // no match.
572 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
573 // either constant or undef values that are identical for each chunk. See
574 // if these chunks can form into a larger vspltis*.
576 // Check to see if all of the leading entries are either 0 or -1. If
577 // neither, then this won't fit into the immediate field.
578 bool LeadingZero = true;
579 bool LeadingOnes = true;
580 for (unsigned i = 0; i != Multiple-1; ++i) {
581 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
583 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
584 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
586 // Finally, check the least significant entry.
588 if (UniquedVals[Multiple-1].Val == 0)
589 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
590 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
592 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
595 if (UniquedVals[Multiple-1].Val == 0)
596 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
597 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
598 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
599 return DAG.getTargetConstant(Val, MVT::i32);
605 // Check to see if this buildvec has a single non-undef value in its elements.
606 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
607 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
609 OpVal = N->getOperand(i);
610 else if (OpVal != N->getOperand(i))
614 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
616 unsigned ValSizeInBytes = 0;
618 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
619 Value = CN->getValue();
620 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
621 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
622 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
623 Value = FloatToBits(CN->getValueAPF().convertToFloat());
627 // If the splat value is larger than the element value, then we can never do
628 // this splat. The only case that we could fit the replicated bits into our
629 // immediate field for would be zero, and we prefer to use vxor for it.
630 if (ValSizeInBytes < ByteSize) return SDOperand();
632 // If the element value is larger than the splat value, cut it in half and
633 // check to see if the two halves are equal. Continue doing this until we
634 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
635 while (ValSizeInBytes > ByteSize) {
636 ValSizeInBytes >>= 1;
638 // If the top half equals the bottom half, we're still ok.
639 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
640 (Value & ((1 << (8*ValSizeInBytes))-1)))
644 // Properly sign extend the value.
645 int ShAmt = (4-ByteSize)*8;
646 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
648 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
649 if (MaskVal == 0) return SDOperand();
651 // Finally, if this value fits in a 5 bit sext field, return it
652 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
653 return DAG.getTargetConstant(MaskVal, MVT::i32);
657 //===----------------------------------------------------------------------===//
658 // Addressing Mode Selection
659 //===----------------------------------------------------------------------===//
661 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
662 /// or 64-bit immediate, and if the value can be accurately represented as a
663 /// sign extension from a 16-bit value. If so, this returns true and the
665 static bool isIntS16Immediate(SDNode *N, short &Imm) {
666 if (N->getOpcode() != ISD::Constant)
669 Imm = (short)cast<ConstantSDNode>(N)->getValue();
670 if (N->getValueType(0) == MVT::i32)
671 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
673 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
675 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
676 return isIntS16Immediate(Op.Val, Imm);
680 /// SelectAddressRegReg - Given the specified addressed, check to see if it
681 /// can be represented as an indexed [r+r] operation. Returns false if it
682 /// can be more efficiently represented with [r+imm].
683 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
687 if (N.getOpcode() == ISD::ADD) {
688 if (isIntS16Immediate(N.getOperand(1), imm))
690 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
693 Base = N.getOperand(0);
694 Index = N.getOperand(1);
696 } else if (N.getOpcode() == ISD::OR) {
697 if (isIntS16Immediate(N.getOperand(1), imm))
698 return false; // r+i can fold it if we can.
700 // If this is an or of disjoint bitfields, we can codegen this as an add
701 // (for better address arithmetic) if the LHS and RHS of the OR are provably
703 uint64_t LHSKnownZero, LHSKnownOne;
704 uint64_t RHSKnownZero, RHSKnownOne;
705 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
708 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
709 // If all of the bits are known zero on the LHS or RHS, the add won't
711 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
712 Base = N.getOperand(0);
713 Index = N.getOperand(1);
722 /// Returns true if the address N can be represented by a base register plus
723 /// a signed 16-bit displacement [r+imm], and if it is not better
724 /// represented as reg+reg.
725 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
726 SDOperand &Base, SelectionDAG &DAG){
727 // If this can be more profitably realized as r+r, fail.
728 if (SelectAddressRegReg(N, Disp, Base, DAG))
731 if (N.getOpcode() == ISD::ADD) {
733 if (isIntS16Immediate(N.getOperand(1), imm)) {
734 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
735 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
736 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
738 Base = N.getOperand(0);
740 return true; // [r+i]
741 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
742 // Match LOAD (ADD (X, Lo(G))).
743 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
744 && "Cannot handle constant offsets yet!");
745 Disp = N.getOperand(1).getOperand(0); // The global address.
746 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
747 Disp.getOpcode() == ISD::TargetConstantPool ||
748 Disp.getOpcode() == ISD::TargetJumpTable);
749 Base = N.getOperand(0);
750 return true; // [&g+r]
752 } else if (N.getOpcode() == ISD::OR) {
754 if (isIntS16Immediate(N.getOperand(1), imm)) {
755 // If this is an or of disjoint bitfields, we can codegen this as an add
756 // (for better address arithmetic) if the LHS and RHS of the OR are
757 // provably disjoint.
758 uint64_t LHSKnownZero, LHSKnownOne;
759 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
760 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
761 // If all of the bits are known zero on the LHS or RHS, the add won't
763 Base = N.getOperand(0);
764 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
768 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
769 // Loading from a constant address.
771 // If this address fits entirely in a 16-bit sext immediate field, codegen
774 if (isIntS16Immediate(CN, Imm)) {
775 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
776 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
780 // Handle 32-bit sext immediates with LIS + addr mode.
781 if (CN->getValueType(0) == MVT::i32 ||
782 (int64_t)CN->getValue() == (int)CN->getValue()) {
783 int Addr = (int)CN->getValue();
785 // Otherwise, break this down into an LIS + disp.
786 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
788 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
789 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
790 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
795 Disp = DAG.getTargetConstant(0, getPointerTy());
796 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
797 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
800 return true; // [r+0]
803 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
804 /// represented as an indexed [r+r] operation.
805 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
808 // Check to see if we can easily represent this as an [r+r] address. This
809 // will fail if it thinks that the address is more profitably represented as
810 // reg+imm, e.g. where imm = 0.
811 if (SelectAddressRegReg(N, Base, Index, DAG))
814 // If the operand is an addition, always emit this as [r+r], since this is
815 // better (for code size, and execution, as the memop does the add for free)
816 // than emitting an explicit add.
817 if (N.getOpcode() == ISD::ADD) {
818 Base = N.getOperand(0);
819 Index = N.getOperand(1);
823 // Otherwise, do it the hard way, using R0 as the base register.
824 Base = DAG.getRegister(PPC::R0, N.getValueType());
829 /// SelectAddressRegImmShift - Returns true if the address N can be
830 /// represented by a base register plus a signed 14-bit displacement
831 /// [r+imm*4]. Suitable for use by STD and friends.
832 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
835 // If this can be more profitably realized as r+r, fail.
836 if (SelectAddressRegReg(N, Disp, Base, DAG))
839 if (N.getOpcode() == ISD::ADD) {
841 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
842 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
843 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
844 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
846 Base = N.getOperand(0);
848 return true; // [r+i]
849 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
850 // Match LOAD (ADD (X, Lo(G))).
851 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
852 && "Cannot handle constant offsets yet!");
853 Disp = N.getOperand(1).getOperand(0); // The global address.
854 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
855 Disp.getOpcode() == ISD::TargetConstantPool ||
856 Disp.getOpcode() == ISD::TargetJumpTable);
857 Base = N.getOperand(0);
858 return true; // [&g+r]
860 } else if (N.getOpcode() == ISD::OR) {
862 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
863 // If this is an or of disjoint bitfields, we can codegen this as an add
864 // (for better address arithmetic) if the LHS and RHS of the OR are
865 // provably disjoint.
866 uint64_t LHSKnownZero, LHSKnownOne;
867 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
868 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
869 // If all of the bits are known zero on the LHS or RHS, the add won't
871 Base = N.getOperand(0);
872 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
876 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
877 // Loading from a constant address. Verify low two bits are clear.
878 if ((CN->getValue() & 3) == 0) {
879 // If this address fits entirely in a 14-bit sext immediate field, codegen
882 if (isIntS16Immediate(CN, Imm)) {
883 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
884 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
888 // Fold the low-part of 32-bit absolute addresses into addr mode.
889 if (CN->getValueType(0) == MVT::i32 ||
890 (int64_t)CN->getValue() == (int)CN->getValue()) {
891 int Addr = (int)CN->getValue();
893 // Otherwise, break this down into an LIS + disp.
894 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
896 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
897 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
898 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
904 Disp = DAG.getTargetConstant(0, getPointerTy());
905 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
906 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
909 return true; // [r+0]
913 /// getPreIndexedAddressParts - returns true by value, base pointer and
914 /// offset pointer and addressing mode by reference if the node's address
915 /// can be legally represented as pre-indexed load / store address.
916 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
918 ISD::MemIndexedMode &AM,
920 // Disabled by default for now.
921 if (!EnablePPCPreinc) return false;
925 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
926 Ptr = LD->getBasePtr();
927 VT = LD->getLoadedVT();
929 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
931 Ptr = ST->getBasePtr();
932 VT = ST->getStoredVT();
936 // PowerPC doesn't have preinc load/store instructions for vectors.
937 if (MVT::isVector(VT))
940 // TODO: Check reg+reg first.
942 // LDU/STU use reg+imm*4, others use reg+imm.
943 if (VT != MVT::i64) {
945 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
949 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
953 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
954 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
955 // sext i32 to i64 when addr mode is r+i.
956 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 &&
957 LD->getExtensionType() == ISD::SEXTLOAD &&
958 isa<ConstantSDNode>(Offset))
966 //===----------------------------------------------------------------------===//
967 // LowerOperation implementation
968 //===----------------------------------------------------------------------===//
970 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
971 MVT::ValueType PtrVT = Op.getValueType();
972 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
973 Constant *C = CP->getConstVal();
974 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
975 SDOperand Zero = DAG.getConstant(0, PtrVT);
977 const TargetMachine &TM = DAG.getTarget();
979 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
980 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
982 // If this is a non-darwin platform, we don't support non-static relo models
984 if (TM.getRelocationModel() == Reloc::Static ||
985 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
986 // Generate non-pic code that has direct accesses to the constant pool.
987 // The address of the global is just (hi(&g)+lo(&g)).
988 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
991 if (TM.getRelocationModel() == Reloc::PIC_) {
992 // With PIC, the first instruction is actually "GR+hi(&G)".
993 Hi = DAG.getNode(ISD::ADD, PtrVT,
994 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
997 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1001 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1002 MVT::ValueType PtrVT = Op.getValueType();
1003 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1004 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1005 SDOperand Zero = DAG.getConstant(0, PtrVT);
1007 const TargetMachine &TM = DAG.getTarget();
1009 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1010 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1012 // If this is a non-darwin platform, we don't support non-static relo models
1014 if (TM.getRelocationModel() == Reloc::Static ||
1015 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1016 // Generate non-pic code that has direct accesses to the constant pool.
1017 // The address of the global is just (hi(&g)+lo(&g)).
1018 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1021 if (TM.getRelocationModel() == Reloc::PIC_) {
1022 // With PIC, the first instruction is actually "GR+hi(&G)".
1023 Hi = DAG.getNode(ISD::ADD, PtrVT,
1024 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1027 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1031 static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
1032 assert(0 && "TLS not implemented for PPC.");
1035 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
1036 MVT::ValueType PtrVT = Op.getValueType();
1037 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1038 GlobalValue *GV = GSDN->getGlobal();
1039 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1040 SDOperand Zero = DAG.getConstant(0, PtrVT);
1042 const TargetMachine &TM = DAG.getTarget();
1044 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1045 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1047 // If this is a non-darwin platform, we don't support non-static relo models
1049 if (TM.getRelocationModel() == Reloc::Static ||
1050 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1051 // Generate non-pic code that has direct accesses to globals.
1052 // The address of the global is just (hi(&g)+lo(&g)).
1053 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1056 if (TM.getRelocationModel() == Reloc::PIC_) {
1057 // With PIC, the first instruction is actually "GR+hi(&G)".
1058 Hi = DAG.getNode(ISD::ADD, PtrVT,
1059 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1062 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1064 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1067 // If the global is weak or external, we have to go through the lazy
1069 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1072 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1073 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1075 // If we're comparing for equality to zero, expose the fact that this is
1076 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1077 // fold the new nodes.
1078 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1079 if (C->isNullValue() && CC == ISD::SETEQ) {
1080 MVT::ValueType VT = Op.getOperand(0).getValueType();
1081 SDOperand Zext = Op.getOperand(0);
1082 if (VT < MVT::i32) {
1084 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1086 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1087 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1088 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1089 DAG.getConstant(Log2b, MVT::i32));
1090 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1092 // Leave comparisons against 0 and -1 alone for now, since they're usually
1093 // optimized. FIXME: revisit this when we can custom lower all setcc
1095 if (C->isAllOnesValue() || C->isNullValue())
1099 // If we have an integer seteq/setne, turn it into a compare against zero
1100 // by xor'ing the rhs with the lhs, which is faster than setting a
1101 // condition register, reading it back out, and masking the correct bit. The
1102 // normal approach here uses sub to do this instead of xor. Using xor exposes
1103 // the result to other bit-twiddling opportunities.
1104 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1105 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1106 MVT::ValueType VT = Op.getValueType();
1107 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1109 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1114 static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1115 int VarArgsFrameIndex,
1116 int VarArgsStackOffset,
1117 unsigned VarArgsNumGPR,
1118 unsigned VarArgsNumFPR,
1119 const PPCSubtarget &Subtarget) {
1121 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1124 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1125 int VarArgsFrameIndex,
1126 int VarArgsStackOffset,
1127 unsigned VarArgsNumGPR,
1128 unsigned VarArgsNumFPR,
1129 const PPCSubtarget &Subtarget) {
1131 if (Subtarget.isMachoABI()) {
1132 // vastart just stores the address of the VarArgsFrameIndex slot into the
1133 // memory location argument.
1134 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1135 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1136 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1137 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
1141 // For ELF 32 ABI we follow the layout of the va_list struct.
1142 // We suppose the given va_list is already allocated.
1145 // char gpr; /* index into the array of 8 GPRs
1146 // * stored in the register save area
1147 // * gpr=0 corresponds to r3,
1148 // * gpr=1 to r4, etc.
1150 // char fpr; /* index into the array of 8 FPRs
1151 // * stored in the register save area
1152 // * fpr=0 corresponds to f1,
1153 // * fpr=1 to f2, etc.
1155 // char *overflow_arg_area;
1156 // /* location on stack that holds
1157 // * the next overflow argument
1159 // char *reg_save_area;
1160 // /* where r3:r10 and f1:f8 (if saved)
1166 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1167 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1170 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1172 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1173 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1175 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8,
1177 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1,
1179 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT);
1181 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1183 // Store first byte : number of int regs
1184 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1185 Op.getOperand(1), SV->getValue(),
1187 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1190 // Store second byte : number of float regs
1191 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr,
1192 SV->getValue(), SV->getOffset());
1193 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1195 // Store second word : arguments given on stack
1196 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr,
1197 SV->getValue(), SV->getOffset());
1198 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1200 // Store third word : arguments given in registers
1201 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(),
1206 #include "PPCGenCallingConv.inc"
1208 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1209 /// depending on which subtarget is selected.
1210 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1211 if (Subtarget.isMachoABI()) {
1212 static const unsigned FPR[] = {
1213 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1214 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1220 static const unsigned FPR[] = {
1221 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1227 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1228 int &VarArgsFrameIndex,
1229 int &VarArgsStackOffset,
1230 unsigned &VarArgsNumGPR,
1231 unsigned &VarArgsNumFPR,
1232 const PPCSubtarget &Subtarget) {
1233 // TODO: add description of PPC stack frame format, or at least some docs.
1235 MachineFunction &MF = DAG.getMachineFunction();
1236 MachineFrameInfo *MFI = MF.getFrameInfo();
1237 SSARegMap *RegMap = MF.getSSARegMap();
1238 SmallVector<SDOperand, 8> ArgValues;
1239 SDOperand Root = Op.getOperand(0);
1241 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1242 bool isPPC64 = PtrVT == MVT::i64;
1243 bool isMachoABI = Subtarget.isMachoABI();
1244 bool isELF32_ABI = Subtarget.isELF32_ABI();
1245 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1247 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1249 static const unsigned GPR_32[] = { // 32-bit registers.
1250 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1251 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1253 static const unsigned GPR_64[] = { // 64-bit registers.
1254 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1255 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1258 static const unsigned *FPR = GetFPR(Subtarget);
1260 static const unsigned VR[] = {
1261 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1262 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1265 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1266 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1267 const unsigned Num_VR_Regs = array_lengthof( VR);
1269 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1271 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1273 // Add DAG nodes to load the arguments or copy them out of registers. On
1274 // entry to a function on PPC, the arguments start after the linkage area,
1275 // although the first ones are often in registers.
1277 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1278 // represented with two words (long long or double) must be copied to an
1279 // even GPR_idx value or to an even ArgOffset value.
1281 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1283 bool needsLoad = false;
1284 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1285 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1286 unsigned ArgSize = ObjSize;
1287 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1288 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1289 // See if next argument requires stack alignment in ELF
1290 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1291 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1292 (!(Flags & AlignFlag)));
1294 unsigned CurArgOffset = ArgOffset;
1296 default: assert(0 && "Unhandled argument type!");
1298 // Double word align in ELF
1299 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1300 if (GPR_idx != Num_GPR_Regs) {
1301 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1302 MF.addLiveIn(GPR[GPR_idx], VReg);
1303 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1307 ArgSize = PtrByteSize;
1309 // Stack align in ELF
1310 if (needsLoad && Expand && isELF32_ABI)
1311 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1312 // All int arguments reserve stack space in Macho ABI.
1313 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1316 case MVT::i64: // PPC64
1317 if (GPR_idx != Num_GPR_Regs) {
1318 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1319 MF.addLiveIn(GPR[GPR_idx], VReg);
1320 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1325 // All int arguments reserve stack space in Macho ABI.
1326 if (isMachoABI || needsLoad) ArgOffset += 8;
1331 // Every 4 bytes of argument space consumes one of the GPRs available for
1332 // argument passing.
1333 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1335 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1338 if (FPR_idx != Num_FPR_Regs) {
1340 if (ObjectVT == MVT::f32)
1341 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1343 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1344 MF.addLiveIn(FPR[FPR_idx], VReg);
1345 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1351 // Stack align in ELF
1352 if (needsLoad && Expand && isELF32_ABI)
1353 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1354 // All FP arguments reserve stack space in Macho ABI.
1355 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1361 // Note that vector arguments in registers don't reserve stack space.
1362 if (VR_idx != Num_VR_Regs) {
1363 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
1364 MF.addLiveIn(VR[VR_idx], VReg);
1365 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1368 // This should be simple, but requires getting 16-byte aligned stack
1370 assert(0 && "Loading VR argument not implemented yet!");
1376 // We need to load the argument to a virtual register if we determined above
1377 // that we ran out of physical registers of the appropriate type
1379 // If the argument is actually used, emit a load from the right stack
1381 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1382 int FI = MFI->CreateFixedObject(ObjSize,
1383 CurArgOffset + (ArgSize - ObjSize));
1384 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1385 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1387 // Don't emit a dead load.
1388 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1392 ArgValues.push_back(ArgVal);
1395 // If the function takes variable number of arguments, make a frame index for
1396 // the start of the first vararg value... for expansion of llvm.va_start.
1397 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1402 VarArgsNumGPR = GPR_idx;
1403 VarArgsNumFPR = FPR_idx;
1405 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1407 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1408 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1409 MVT::getSizeInBits(PtrVT)/8);
1411 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1418 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1420 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1422 SmallVector<SDOperand, 8> MemOps;
1424 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1425 // stored to the VarArgsFrameIndex on the stack.
1427 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1428 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1429 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1430 MemOps.push_back(Store);
1431 // Increment the address by four for the next argument to store
1432 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1433 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1437 // If this function is vararg, store any remaining integer argument regs
1438 // to their spots on the stack so that they may be loaded by deferencing the
1439 // result of va_next.
1440 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1443 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1445 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1447 MF.addLiveIn(GPR[GPR_idx], VReg);
1448 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1449 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1450 MemOps.push_back(Store);
1451 // Increment the address by four for the next argument to store
1452 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1453 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1456 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1459 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1460 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1461 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1462 MemOps.push_back(Store);
1463 // Increment the address by eight for the next argument to store
1464 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1466 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1469 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1471 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1473 MF.addLiveIn(FPR[FPR_idx], VReg);
1474 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1475 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1476 MemOps.push_back(Store);
1477 // Increment the address by eight for the next argument to store
1478 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1480 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1484 if (!MemOps.empty())
1485 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1488 ArgValues.push_back(Root);
1490 // Return the new list of results.
1491 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1492 Op.Val->value_end());
1493 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1496 /// isCallCompatibleAddress - Return the immediate to use if the specified
1497 /// 32-bit value is representable in the immediate field of a BxA instruction.
1498 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1499 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1502 int Addr = C->getValue();
1503 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1504 (Addr << 6 >> 6) != Addr)
1505 return 0; // Top 6 bits have to be sext of immediate.
1507 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
1511 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
1512 const PPCSubtarget &Subtarget) {
1513 SDOperand Chain = Op.getOperand(0);
1514 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1515 SDOperand Callee = Op.getOperand(4);
1516 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1518 bool isMachoABI = Subtarget.isMachoABI();
1519 bool isELF32_ABI = Subtarget.isELF32_ABI();
1521 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1522 bool isPPC64 = PtrVT == MVT::i64;
1523 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1525 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1526 // SelectExpr to use to put the arguments in the appropriate registers.
1527 std::vector<SDOperand> args_to_use;
1529 // Count how many bytes are to be pushed on the stack, including the linkage
1530 // area, and parameter passing area. We start with 24/48 bytes, which is
1531 // prereserved space for [SP][CR][LR][3 x unused].
1532 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1534 // Add up all the space actually used.
1535 for (unsigned i = 0; i != NumOps; ++i) {
1536 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1537 ArgSize = std::max(ArgSize, PtrByteSize);
1538 NumBytes += ArgSize;
1541 // The prolog code of the callee may store up to 8 GPR argument registers to
1542 // the stack, allowing va_start to index over them in memory if its varargs.
1543 // Because we cannot tell if this is needed on the caller side, we have to
1544 // conservatively assume that it is needed. As such, make sure we have at
1545 // least enough stack space for the caller to store the 8 GPRs.
1546 NumBytes = std::max(NumBytes,
1547 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1549 // Adjust the stack pointer for the new arguments...
1550 // These operations are automatically eliminated by the prolog/epilog pass
1551 Chain = DAG.getCALLSEQ_START(Chain,
1552 DAG.getConstant(NumBytes, PtrVT));
1554 // Set up a copy of the stack pointer for use loading and storing any
1555 // arguments that may not fit in the registers available for argument
1559 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1561 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1563 // Figure out which arguments are going to go in registers, and which in
1564 // memory. Also, if this is a vararg function, floating point operations
1565 // must be stored to our stack, and loaded into integer regs as well, if
1566 // any integer regs are available for argument passing.
1567 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1568 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1570 static const unsigned GPR_32[] = { // 32-bit registers.
1571 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1572 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1574 static const unsigned GPR_64[] = { // 64-bit registers.
1575 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1576 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1578 static const unsigned *FPR = GetFPR(Subtarget);
1580 static const unsigned VR[] = {
1581 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1582 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1584 const unsigned NumGPRs = array_lengthof(GPR_32);
1585 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1586 const unsigned NumVRs = array_lengthof( VR);
1588 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1590 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1591 SmallVector<SDOperand, 8> MemOpChains;
1592 for (unsigned i = 0; i != NumOps; ++i) {
1594 SDOperand Arg = Op.getOperand(5+2*i);
1595 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1596 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1597 // See if next argument requires stack alignment in ELF
1598 unsigned next = 5+2*(i+1)+1;
1599 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1600 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1601 (!(Flags & AlignFlag)));
1603 // PtrOff will be used to store the current argument to the stack if a
1604 // register cannot be found for it.
1607 // Stack align in ELF 32
1608 if (isELF32_ABI && Expand)
1609 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1610 StackPtr.getValueType());
1612 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1614 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1616 // On PPC64, promote integers to 64-bit values.
1617 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1618 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1620 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1623 switch (Arg.getValueType()) {
1624 default: assert(0 && "Unexpected ValueType for argument!");
1627 // Double word align in ELF
1628 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1629 if (GPR_idx != NumGPRs) {
1630 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1632 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1635 if (inMem || isMachoABI) {
1636 // Stack align in ELF
1637 if (isELF32_ABI && Expand)
1638 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1640 ArgOffset += PtrByteSize;
1646 // Float varargs need to be promoted to double.
1647 if (Arg.getValueType() == MVT::f32)
1648 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1651 if (FPR_idx != NumFPRs) {
1652 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1655 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1656 MemOpChains.push_back(Store);
1658 // Float varargs are always shadowed in available integer registers
1659 if (GPR_idx != NumGPRs) {
1660 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1661 MemOpChains.push_back(Load.getValue(1));
1662 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1665 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1666 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1667 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1668 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1669 MemOpChains.push_back(Load.getValue(1));
1670 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1674 // If we have any FPRs remaining, we may also have GPRs remaining.
1675 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1678 if (GPR_idx != NumGPRs)
1680 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1681 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1686 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1689 if (inMem || isMachoABI) {
1690 // Stack align in ELF
1691 if (isELF32_ABI && Expand)
1692 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1696 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1703 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1704 assert(VR_idx != NumVRs &&
1705 "Don't support passing more than 12 vector args yet!");
1706 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1710 if (!MemOpChains.empty())
1711 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1712 &MemOpChains[0], MemOpChains.size());
1714 // Build a sequence of copy-to-reg nodes chained together with token chain
1715 // and flag operands which copy the outgoing args into the appropriate regs.
1717 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1718 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1720 InFlag = Chain.getValue(1);
1723 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1724 if (isVarArg && isELF32_ABI) {
1725 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1726 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1727 InFlag = Chain.getValue(1);
1730 std::vector<MVT::ValueType> NodeTys;
1731 NodeTys.push_back(MVT::Other); // Returns a chain
1732 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1734 SmallVector<SDOperand, 8> Ops;
1735 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1737 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1738 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1739 // node so that legalize doesn't hack it.
1740 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1741 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1742 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1743 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1744 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1745 // If this is an absolute destination address, use the munged value.
1746 Callee = SDOperand(Dest, 0);
1748 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1749 // to do the call, we can't use PPCISD::CALL.
1750 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1751 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1752 InFlag = Chain.getValue(1);
1754 // Copy the callee address into R12 on darwin.
1756 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1757 InFlag = Chain.getValue(1);
1761 NodeTys.push_back(MVT::Other);
1762 NodeTys.push_back(MVT::Flag);
1763 Ops.push_back(Chain);
1764 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1768 // If this is a direct call, pass the chain and the callee.
1770 Ops.push_back(Chain);
1771 Ops.push_back(Callee);
1774 // Add argument registers to the end of the list so that they are known live
1776 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1777 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1778 RegsToPass[i].second.getValueType()));
1781 Ops.push_back(InFlag);
1782 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1783 InFlag = Chain.getValue(1);
1785 SDOperand ResultVals[3];
1786 unsigned NumResults = 0;
1789 // If the call has results, copy the values out of the ret val registers.
1790 switch (Op.Val->getValueType(0)) {
1791 default: assert(0 && "Unexpected ret value!");
1792 case MVT::Other: break;
1794 if (Op.Val->getValueType(1) == MVT::i32) {
1795 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1796 ResultVals[0] = Chain.getValue(0);
1797 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
1798 Chain.getValue(2)).getValue(1);
1799 ResultVals[1] = Chain.getValue(0);
1801 NodeTys.push_back(MVT::i32);
1803 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1804 ResultVals[0] = Chain.getValue(0);
1807 NodeTys.push_back(MVT::i32);
1810 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1811 ResultVals[0] = Chain.getValue(0);
1813 NodeTys.push_back(MVT::i64);
1817 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1818 InFlag).getValue(1);
1819 ResultVals[0] = Chain.getValue(0);
1821 NodeTys.push_back(Op.Val->getValueType(0));
1827 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1828 InFlag).getValue(1);
1829 ResultVals[0] = Chain.getValue(0);
1831 NodeTys.push_back(Op.Val->getValueType(0));
1835 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1836 DAG.getConstant(NumBytes, PtrVT));
1837 NodeTys.push_back(MVT::Other);
1839 // If the function returns void, just return the chain.
1840 if (NumResults == 0)
1843 // Otherwise, merge everything together with a MERGE_VALUES node.
1844 ResultVals[NumResults++] = Chain;
1845 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1846 ResultVals, NumResults);
1847 return Res.getValue(Op.ResNo);
1850 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1851 SmallVector<CCValAssign, 16> RVLocs;
1852 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1853 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1854 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1855 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1857 // If this is the first return lowered for this function, add the regs to the
1858 // liveout set for the function.
1859 if (DAG.getMachineFunction().liveout_empty()) {
1860 for (unsigned i = 0; i != RVLocs.size(); ++i)
1861 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
1864 SDOperand Chain = Op.getOperand(0);
1867 // Copy the result values into the output registers.
1868 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1869 CCValAssign &VA = RVLocs[i];
1870 assert(VA.isRegLoc() && "Can only return in registers!");
1871 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1872 Flag = Chain.getValue(1);
1876 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
1878 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
1881 static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
1882 const PPCSubtarget &Subtarget) {
1883 // When we pop the dynamic allocation we need to restore the SP link.
1885 // Get the corect type for pointers.
1886 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1888 // Construct the stack pointer operand.
1889 bool IsPPC64 = Subtarget.isPPC64();
1890 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
1891 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
1893 // Get the operands for the STACKRESTORE.
1894 SDOperand Chain = Op.getOperand(0);
1895 SDOperand SaveSP = Op.getOperand(1);
1897 // Load the old link SP.
1898 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
1900 // Restore the stack pointer.
1901 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
1903 // Store the old link SP.
1904 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
1907 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1908 const PPCSubtarget &Subtarget) {
1909 MachineFunction &MF = DAG.getMachineFunction();
1910 bool IsPPC64 = Subtarget.isPPC64();
1911 bool isMachoABI = Subtarget.isMachoABI();
1913 // Get current frame pointer save index. The users of this index will be
1914 // primarily DYNALLOC instructions.
1915 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1916 int FPSI = FI->getFramePointerSaveIndex();
1918 // If the frame pointer save index hasn't been defined yet.
1920 // Find out what the fix offset of the frame pointer save area.
1921 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
1923 // Allocate the frame index for frame pointer save area.
1924 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
1926 FI->setFramePointerSaveIndex(FPSI);
1930 SDOperand Chain = Op.getOperand(0);
1931 SDOperand Size = Op.getOperand(1);
1933 // Get the corect type for pointers.
1934 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1936 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
1937 DAG.getConstant(0, PtrVT), Size);
1938 // Construct a node for the frame pointer save index.
1939 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
1940 // Build a DYNALLOC node.
1941 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
1942 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
1943 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
1947 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1949 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1950 // Not FP? Not a fsel.
1951 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1952 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1955 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1957 // Cannot handle SETEQ/SETNE.
1958 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1960 MVT::ValueType ResVT = Op.getValueType();
1961 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1962 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1963 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1965 // If the RHS of the comparison is a 0.0, we don't need to do the
1966 // subtraction at all.
1967 if (isFloatingPointZero(RHS))
1969 default: break; // SETUO etc aren't handled by fsel.
1973 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1977 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1978 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1979 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1983 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1987 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1988 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1989 return DAG.getNode(PPCISD::FSEL, ResVT,
1990 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1995 default: break; // SETUO etc aren't handled by fsel.
1999 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2000 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2001 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2002 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2006 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2007 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2008 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2009 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2013 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2014 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2015 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2016 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2020 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2021 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2022 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2023 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2028 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2029 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2030 SDOperand Src = Op.getOperand(0);
2031 if (Src.getValueType() == MVT::f32)
2032 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2035 switch (Op.getValueType()) {
2036 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2038 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2041 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2045 // Convert the FP value to an int value through memory.
2046 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
2047 if (Op.getValueType() == MVT::i32)
2048 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
2052 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2053 if (Op.getOperand(0).getValueType() == MVT::i64) {
2054 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2055 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2056 if (Op.getValueType() == MVT::f32)
2057 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
2061 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2062 "Unhandled SINT_TO_FP type in custom expander!");
2063 // Since we only generate this in 64-bit mode, we can take advantage of
2064 // 64-bit registers. In particular, sign extend the input value into the
2065 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2066 // then lfd it and fcfid it.
2067 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2068 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2069 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2070 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2072 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2075 // STD the extended value into the stack slot.
2076 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2077 DAG.getEntryNode(), Ext64, FIdx,
2078 DAG.getSrcValue(NULL));
2079 // Load the value as a double.
2080 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2082 // FCFID it and return it.
2083 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2084 if (Op.getValueType() == MVT::f32)
2085 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
2089 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2090 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2091 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2093 // Expand into a bunch of logical ops. Note that these ops
2094 // depend on the PPC behavior for oversized shift amounts.
2095 SDOperand Lo = Op.getOperand(0);
2096 SDOperand Hi = Op.getOperand(1);
2097 SDOperand Amt = Op.getOperand(2);
2099 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2100 DAG.getConstant(32, MVT::i32), Amt);
2101 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2102 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2103 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2104 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2105 DAG.getConstant(-32U, MVT::i32));
2106 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2107 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2108 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2109 SDOperand OutOps[] = { OutLo, OutHi };
2110 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2114 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2115 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2116 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2118 // Otherwise, expand into a bunch of logical ops. Note that these ops
2119 // depend on the PPC behavior for oversized shift amounts.
2120 SDOperand Lo = Op.getOperand(0);
2121 SDOperand Hi = Op.getOperand(1);
2122 SDOperand Amt = Op.getOperand(2);
2124 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2125 DAG.getConstant(32, MVT::i32), Amt);
2126 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2127 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2128 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2129 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2130 DAG.getConstant(-32U, MVT::i32));
2131 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2132 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2133 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2134 SDOperand OutOps[] = { OutLo, OutHi };
2135 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2139 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2140 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2141 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2143 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2144 SDOperand Lo = Op.getOperand(0);
2145 SDOperand Hi = Op.getOperand(1);
2146 SDOperand Amt = Op.getOperand(2);
2148 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2149 DAG.getConstant(32, MVT::i32), Amt);
2150 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2151 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2152 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2153 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2154 DAG.getConstant(-32U, MVT::i32));
2155 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2156 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2157 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2158 Tmp4, Tmp6, ISD::SETLE);
2159 SDOperand OutOps[] = { OutLo, OutHi };
2160 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2164 //===----------------------------------------------------------------------===//
2165 // Vector related lowering.
2168 // If this is a vector of constants or undefs, get the bits. A bit in
2169 // UndefBits is set if the corresponding element of the vector is an
2170 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2171 // zero. Return true if this is not an array of constants, false if it is.
2173 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2174 uint64_t UndefBits[2]) {
2175 // Start with zero'd results.
2176 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2178 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2179 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2180 SDOperand OpVal = BV->getOperand(i);
2182 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2183 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2185 uint64_t EltBits = 0;
2186 if (OpVal.getOpcode() == ISD::UNDEF) {
2187 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2188 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2190 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2191 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2192 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2193 assert(CN->getValueType(0) == MVT::f32 &&
2194 "Only one legal FP vector type!");
2195 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
2197 // Nonconstant element.
2201 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2204 //printf("%llx %llx %llx %llx\n",
2205 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2209 // If this is a splat (repetition) of a value across the whole vector, return
2210 // the smallest size that splats it. For example, "0x01010101010101..." is a
2211 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2212 // SplatSize = 1 byte.
2213 static bool isConstantSplat(const uint64_t Bits128[2],
2214 const uint64_t Undef128[2],
2215 unsigned &SplatBits, unsigned &SplatUndef,
2216 unsigned &SplatSize) {
2218 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2219 // the same as the lower 64-bits, ignoring undefs.
2220 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2221 return false; // Can't be a splat if two pieces don't match.
2223 uint64_t Bits64 = Bits128[0] | Bits128[1];
2224 uint64_t Undef64 = Undef128[0] & Undef128[1];
2226 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2228 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2229 return false; // Can't be a splat if two pieces don't match.
2231 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2232 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2234 // If the top 16-bits are different than the lower 16-bits, ignoring
2235 // undefs, we have an i32 splat.
2236 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2238 SplatUndef = Undef32;
2243 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2244 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2246 // If the top 8-bits are different than the lower 8-bits, ignoring
2247 // undefs, we have an i16 splat.
2248 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2250 SplatUndef = Undef16;
2255 // Otherwise, we have an 8-bit splat.
2256 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2257 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2262 /// BuildSplatI - Build a canonical splati of Val with an element size of
2263 /// SplatSize. Cast the result to VT.
2264 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2265 SelectionDAG &DAG) {
2266 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2268 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2269 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2272 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2274 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2278 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2280 // Build a canonical splat for this value.
2281 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2282 SmallVector<SDOperand, 8> Ops;
2283 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2284 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2285 &Ops[0], Ops.size());
2286 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2289 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2290 /// specified intrinsic ID.
2291 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2293 MVT::ValueType DestVT = MVT::Other) {
2294 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2295 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2296 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2299 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2300 /// specified intrinsic ID.
2301 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2302 SDOperand Op2, SelectionDAG &DAG,
2303 MVT::ValueType DestVT = MVT::Other) {
2304 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2305 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2306 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2310 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2311 /// amount. The result has the specified value type.
2312 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2313 MVT::ValueType VT, SelectionDAG &DAG) {
2314 // Force LHS/RHS to be the right type.
2315 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2316 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2319 for (unsigned i = 0; i != 16; ++i)
2320 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2321 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2322 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2323 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2326 // If this is a case we can't handle, return null and let the default
2327 // expansion code take care of it. If we CAN select this case, and if it
2328 // selects to a single instruction, return Op. Otherwise, if we can codegen
2329 // this case more efficiently than a constant pool load, lower it to the
2330 // sequence of ops that should be used.
2331 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2332 // If this is a vector of constants or undefs, get the bits. A bit in
2333 // UndefBits is set if the corresponding element of the vector is an
2334 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2336 uint64_t VectorBits[2];
2337 uint64_t UndefBits[2];
2338 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2339 return SDOperand(); // Not a constant vector.
2341 // If this is a splat (repetition) of a value across the whole vector, return
2342 // the smallest size that splats it. For example, "0x01010101010101..." is a
2343 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2344 // SplatSize = 1 byte.
2345 unsigned SplatBits, SplatUndef, SplatSize;
2346 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2347 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2349 // First, handle single instruction cases.
2352 if (SplatBits == 0) {
2353 // Canonicalize all zero vectors to be v4i32.
2354 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2355 SDOperand Z = DAG.getConstant(0, MVT::i32);
2356 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2357 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2362 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2363 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2364 if (SextVal >= -16 && SextVal <= 15)
2365 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2368 // Two instruction sequences.
2370 // If this value is in the range [-32,30] and is even, use:
2371 // tmp = VSPLTI[bhw], result = add tmp, tmp
2372 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2373 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2374 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2377 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2378 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2380 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2381 // Make -1 and vspltisw -1:
2382 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2384 // Make the VSLW intrinsic, computing 0x8000_0000.
2385 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2388 // xor by OnesV to invert it.
2389 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2390 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2393 // Check to see if this is a wide variety of vsplti*, binop self cases.
2394 unsigned SplatBitSize = SplatSize*8;
2395 static const signed char SplatCsts[] = {
2396 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2397 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2400 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
2401 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2402 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2403 int i = SplatCsts[idx];
2405 // Figure out what shift amount will be used by altivec if shifted by i in
2407 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2409 // vsplti + shl self.
2410 if (SextVal == (i << (int)TypeShiftAmt)) {
2411 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2412 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2413 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2414 Intrinsic::ppc_altivec_vslw
2416 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2417 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2420 // vsplti + srl self.
2421 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2422 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2423 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2424 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2425 Intrinsic::ppc_altivec_vsrw
2427 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2428 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2431 // vsplti + sra self.
2432 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2433 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2434 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2435 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2436 Intrinsic::ppc_altivec_vsraw
2438 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2439 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2442 // vsplti + rol self.
2443 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2444 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2445 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2446 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2447 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2448 Intrinsic::ppc_altivec_vrlw
2450 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2451 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2454 // t = vsplti c, result = vsldoi t, t, 1
2455 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2456 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2457 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2459 // t = vsplti c, result = vsldoi t, t, 2
2460 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2461 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2462 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2464 // t = vsplti c, result = vsldoi t, t, 3
2465 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2466 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2467 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2471 // Three instruction sequences.
2473 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2474 if (SextVal >= 0 && SextVal <= 31) {
2475 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2476 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2477 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
2478 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2480 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2481 if (SextVal >= -31 && SextVal <= 0) {
2482 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2483 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2484 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
2485 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2492 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2493 /// the specified operations to build the shuffle.
2494 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2495 SDOperand RHS, SelectionDAG &DAG) {
2496 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2497 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2498 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2501 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2513 if (OpNum == OP_COPY) {
2514 if (LHSID == (1*9+2)*9+3) return LHS;
2515 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2519 SDOperand OpLHS, OpRHS;
2520 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2521 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2523 unsigned ShufIdxs[16];
2525 default: assert(0 && "Unknown i32 permute!");
2527 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2528 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2529 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2530 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2533 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2534 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2535 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2536 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2539 for (unsigned i = 0; i != 16; ++i)
2540 ShufIdxs[i] = (i&3)+0;
2543 for (unsigned i = 0; i != 16; ++i)
2544 ShufIdxs[i] = (i&3)+4;
2547 for (unsigned i = 0; i != 16; ++i)
2548 ShufIdxs[i] = (i&3)+8;
2551 for (unsigned i = 0; i != 16; ++i)
2552 ShufIdxs[i] = (i&3)+12;
2555 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2557 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2559 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2562 for (unsigned i = 0; i != 16; ++i)
2563 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2565 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2566 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2569 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2570 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2571 /// return the code it can be lowered into. Worst case, it can always be
2572 /// lowered into a vperm.
2573 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2574 SDOperand V1 = Op.getOperand(0);
2575 SDOperand V2 = Op.getOperand(1);
2576 SDOperand PermMask = Op.getOperand(2);
2578 // Cases that are handled by instructions that take permute immediates
2579 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2580 // selected by the instruction selector.
2581 if (V2.getOpcode() == ISD::UNDEF) {
2582 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2583 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2584 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2585 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2586 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2587 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2588 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2589 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2590 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2591 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2592 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2593 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2598 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2599 // and produce a fixed permutation. If any of these match, do not lower to
2601 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2602 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2603 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2604 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2605 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2606 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2607 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2608 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2609 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2612 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2613 // perfect shuffle table to emit an optimal matching sequence.
2614 unsigned PFIndexes[4];
2615 bool isFourElementShuffle = true;
2616 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2617 unsigned EltNo = 8; // Start out undef.
2618 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2619 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2620 continue; // Undef, ignore it.
2622 unsigned ByteSource =
2623 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2624 if ((ByteSource & 3) != j) {
2625 isFourElementShuffle = false;
2630 EltNo = ByteSource/4;
2631 } else if (EltNo != ByteSource/4) {
2632 isFourElementShuffle = false;
2636 PFIndexes[i] = EltNo;
2639 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2640 // perfect shuffle vector to determine if it is cost effective to do this as
2641 // discrete instructions, or whether we should use a vperm.
2642 if (isFourElementShuffle) {
2643 // Compute the index in the perfect shuffle table.
2644 unsigned PFTableIndex =
2645 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2647 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2648 unsigned Cost = (PFEntry >> 30);
2650 // Determining when to avoid vperm is tricky. Many things affect the cost
2651 // of vperm, particularly how many times the perm mask needs to be computed.
2652 // For example, if the perm mask can be hoisted out of a loop or is already
2653 // used (perhaps because there are multiple permutes with the same shuffle
2654 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2655 // the loop requires an extra register.
2657 // As a compromise, we only emit discrete instructions if the shuffle can be
2658 // generated in 3 or fewer operations. When we have loop information
2659 // available, if this block is within a loop, we should avoid using vperm
2660 // for 3-operation perms and use a constant pool load instead.
2662 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2665 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2666 // vector that will get spilled to the constant pool.
2667 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2669 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2670 // that it is in input element units, not in bytes. Convert now.
2671 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
2672 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2674 SmallVector<SDOperand, 16> ResultMask;
2675 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2677 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2680 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2682 for (unsigned j = 0; j != BytesPerElement; ++j)
2683 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2687 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2688 &ResultMask[0], ResultMask.size());
2689 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2692 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2693 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2694 /// information about the intrinsic.
2695 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2697 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2700 switch (IntrinsicID) {
2701 default: return false;
2702 // Comparison predicates.
2703 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2704 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2705 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2706 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2707 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2708 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2709 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2710 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2711 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2712 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2713 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2714 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2715 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2717 // Normal Comparisons.
2718 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2719 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2720 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2721 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2722 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2723 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2724 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2725 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2726 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2727 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2728 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2729 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2730 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2735 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2736 /// lower, do it, otherwise return null.
2737 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2738 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2739 // opcode number of the comparison.
2742 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2743 return SDOperand(); // Don't custom lower most intrinsics.
2745 // If this is a non-dot comparison, make the VCMP node and we are done.
2747 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2748 Op.getOperand(1), Op.getOperand(2),
2749 DAG.getConstant(CompareOpc, MVT::i32));
2750 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2753 // Create the PPCISD altivec 'dot' comparison node.
2755 Op.getOperand(2), // LHS
2756 Op.getOperand(3), // RHS
2757 DAG.getConstant(CompareOpc, MVT::i32)
2759 std::vector<MVT::ValueType> VTs;
2760 VTs.push_back(Op.getOperand(2).getValueType());
2761 VTs.push_back(MVT::Flag);
2762 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2764 // Now that we have the comparison, emit a copy from the CR to a GPR.
2765 // This is flagged to the above dot comparison.
2766 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2767 DAG.getRegister(PPC::CR6, MVT::i32),
2768 CompNode.getValue(1));
2770 // Unpack the result based on how the target uses it.
2771 unsigned BitNo; // Bit # of CR6.
2772 bool InvertBit; // Invert result?
2773 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2774 default: // Can't happen, don't crash on invalid number though.
2775 case 0: // Return the value of the EQ bit of CR6.
2776 BitNo = 0; InvertBit = false;
2778 case 1: // Return the inverted value of the EQ bit of CR6.
2779 BitNo = 0; InvertBit = true;
2781 case 2: // Return the value of the LT bit of CR6.
2782 BitNo = 2; InvertBit = false;
2784 case 3: // Return the inverted value of the LT bit of CR6.
2785 BitNo = 2; InvertBit = true;
2789 // Shift the bit into the low position.
2790 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2791 DAG.getConstant(8-(3-BitNo), MVT::i32));
2793 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2794 DAG.getConstant(1, MVT::i32));
2796 // If we are supposed to, toggle the bit.
2798 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2799 DAG.getConstant(1, MVT::i32));
2803 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2804 // Create a stack slot that is 16-byte aligned.
2805 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2806 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2807 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2808 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2810 // Store the input value into Value#0 of the stack slot.
2811 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2812 Op.getOperand(0), FIdx, NULL, 0);
2814 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
2817 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2818 if (Op.getValueType() == MVT::v4i32) {
2819 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2821 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2822 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2824 SDOperand RHSSwap = // = vrlw RHS, 16
2825 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2827 // Shrinkify inputs to v8i16.
2828 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2829 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2830 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2832 // Low parts multiplied together, generating 32-bit results (we ignore the
2834 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2835 LHS, RHS, DAG, MVT::v4i32);
2837 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2838 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2839 // Shift the high parts up 16 bits.
2840 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2841 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2842 } else if (Op.getValueType() == MVT::v8i16) {
2843 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2845 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2847 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2848 LHS, RHS, Zero, DAG);
2849 } else if (Op.getValueType() == MVT::v16i8) {
2850 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2852 // Multiply the even 8-bit parts, producing 16-bit sums.
2853 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2854 LHS, RHS, DAG, MVT::v8i16);
2855 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2857 // Multiply the odd 8-bit parts, producing 16-bit sums.
2858 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2859 LHS, RHS, DAG, MVT::v8i16);
2860 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2862 // Merge the results together.
2864 for (unsigned i = 0; i != 8; ++i) {
2865 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2866 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2868 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2869 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2871 assert(0 && "Unknown mul to lower!");
2876 /// LowerOperation - Provide custom lowering hooks for some operations.
2878 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2879 switch (Op.getOpcode()) {
2880 default: assert(0 && "Wasn't expecting to be able to lower this!");
2881 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2882 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2883 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2884 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2885 case ISD::SETCC: return LowerSETCC(Op, DAG);
2887 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
2888 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
2891 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
2892 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
2894 case ISD::FORMAL_ARGUMENTS:
2895 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
2896 VarArgsStackOffset, VarArgsNumGPR,
2897 VarArgsNumFPR, PPCSubTarget);
2899 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
2900 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
2901 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
2902 case ISD::DYNAMIC_STACKALLOC:
2903 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
2905 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2906 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2907 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2909 // Lower 64-bit shifts.
2910 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
2911 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
2912 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
2914 // Vector-related lowering.
2915 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2916 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2917 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2918 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2919 case ISD::MUL: return LowerMUL(Op, DAG);
2921 // Frame & Return address. Currently unimplemented
2922 case ISD::RETURNADDR: break;
2923 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2928 //===----------------------------------------------------------------------===//
2929 // Other Lowering Code
2930 //===----------------------------------------------------------------------===//
2933 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2934 MachineBasicBlock *BB) {
2935 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2936 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2937 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2938 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2939 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2940 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2941 "Unexpected instr type to insert");
2943 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2944 // control-flow pattern. The incoming instruction knows the destination vreg
2945 // to set, the condition code register to branch on, the true/false values to
2946 // select between, and a branch opcode to use.
2947 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2948 ilist<MachineBasicBlock>::iterator It = BB;
2954 // cmpTY ccX, r1, r2
2956 // fallthrough --> copy0MBB
2957 MachineBasicBlock *thisMBB = BB;
2958 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2959 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2960 unsigned SelectPred = MI->getOperand(4).getImm();
2961 BuildMI(BB, TII->get(PPC::BCC))
2962 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2963 MachineFunction *F = BB->getParent();
2964 F->getBasicBlockList().insert(It, copy0MBB);
2965 F->getBasicBlockList().insert(It, sinkMBB);
2966 // Update machine-CFG edges by first adding all successors of the current
2967 // block to the new block which will contain the Phi node for the select.
2968 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2969 e = BB->succ_end(); i != e; ++i)
2970 sinkMBB->addSuccessor(*i);
2971 // Next, remove all successors of the current block, and add the true
2972 // and fallthrough blocks as its successors.
2973 while(!BB->succ_empty())
2974 BB->removeSuccessor(BB->succ_begin());
2975 BB->addSuccessor(copy0MBB);
2976 BB->addSuccessor(sinkMBB);
2979 // %FalseValue = ...
2980 // # fallthrough to sinkMBB
2983 // Update machine-CFG edges
2984 BB->addSuccessor(sinkMBB);
2987 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2990 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
2991 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2992 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2994 delete MI; // The pseudo instruction is gone now.
2998 //===----------------------------------------------------------------------===//
2999 // Target Optimization Hooks
3000 //===----------------------------------------------------------------------===//
3002 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3003 DAGCombinerInfo &DCI) const {
3004 TargetMachine &TM = getTargetMachine();
3005 SelectionDAG &DAG = DCI.DAG;
3006 switch (N->getOpcode()) {
3009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3010 if (C->getValue() == 0) // 0 << V -> 0.
3011 return N->getOperand(0);
3015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3016 if (C->getValue() == 0) // 0 >>u V -> 0.
3017 return N->getOperand(0);
3021 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3022 if (C->getValue() == 0 || // 0 >>s V -> 0.
3023 C->isAllOnesValue()) // -1 >>s V -> -1.
3024 return N->getOperand(0);
3028 case ISD::SINT_TO_FP:
3029 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3030 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3031 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3032 // We allow the src/dst to be either f32/f64, but the intermediate
3033 // type must be i64.
3034 if (N->getOperand(0).getValueType() == MVT::i64) {
3035 SDOperand Val = N->getOperand(0).getOperand(0);
3036 if (Val.getValueType() == MVT::f32) {
3037 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3038 DCI.AddToWorklist(Val.Val);
3041 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3042 DCI.AddToWorklist(Val.Val);
3043 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3044 DCI.AddToWorklist(Val.Val);
3045 if (N->getValueType(0) == MVT::f32) {
3046 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
3047 DCI.AddToWorklist(Val.Val);
3050 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3051 // If the intermediate type is i32, we can avoid the load/store here
3058 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3059 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3060 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3061 N->getOperand(1).getValueType() == MVT::i32) {
3062 SDOperand Val = N->getOperand(1).getOperand(0);
3063 if (Val.getValueType() == MVT::f32) {
3064 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3065 DCI.AddToWorklist(Val.Val);
3067 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3068 DCI.AddToWorklist(Val.Val);
3070 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3071 N->getOperand(2), N->getOperand(3));
3072 DCI.AddToWorklist(Val.Val);
3076 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3077 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3078 N->getOperand(1).Val->hasOneUse() &&
3079 (N->getOperand(1).getValueType() == MVT::i32 ||
3080 N->getOperand(1).getValueType() == MVT::i16)) {
3081 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3082 // Do an any-extend to 32-bits if this is a half-word input.
3083 if (BSwapOp.getValueType() == MVT::i16)
3084 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3086 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3087 N->getOperand(2), N->getOperand(3),
3088 DAG.getValueType(N->getOperand(1).getValueType()));
3092 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3093 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3094 N->getOperand(0).hasOneUse() &&
3095 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3096 SDOperand Load = N->getOperand(0);
3097 LoadSDNode *LD = cast<LoadSDNode>(Load);
3098 // Create the byte-swapping load.
3099 std::vector<MVT::ValueType> VTs;
3100 VTs.push_back(MVT::i32);
3101 VTs.push_back(MVT::Other);
3102 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
3104 LD->getChain(), // Chain
3105 LD->getBasePtr(), // Ptr
3107 DAG.getValueType(N->getValueType(0)) // VT
3109 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3111 // If this is an i16 load, insert the truncate.
3112 SDOperand ResVal = BSLoad;
3113 if (N->getValueType(0) == MVT::i16)
3114 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3116 // First, combine the bswap away. This makes the value produced by the
3118 DCI.CombineTo(N, ResVal);
3120 // Next, combine the load away, we give it a bogus result value but a real
3121 // chain result. The result value is dead because the bswap is dead.
3122 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3124 // Return N so it doesn't get rechecked!
3125 return SDOperand(N, 0);
3129 case PPCISD::VCMP: {
3130 // If a VCMPo node already exists with exactly the same operands as this
3131 // node, use its result instead of this node (VCMPo computes both a CR6 and
3132 // a normal output).
3134 if (!N->getOperand(0).hasOneUse() &&
3135 !N->getOperand(1).hasOneUse() &&
3136 !N->getOperand(2).hasOneUse()) {
3138 // Scan all of the users of the LHS, looking for VCMPo's that match.
3139 SDNode *VCMPoNode = 0;
3141 SDNode *LHSN = N->getOperand(0).Val;
3142 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3144 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3145 (*UI)->getOperand(1) == N->getOperand(1) &&
3146 (*UI)->getOperand(2) == N->getOperand(2) &&
3147 (*UI)->getOperand(0) == N->getOperand(0)) {
3152 // If there is no VCMPo node, or if the flag value has a single use, don't
3154 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3157 // Look at the (necessarily single) use of the flag value. If it has a
3158 // chain, this transformation is more complex. Note that multiple things
3159 // could use the value result, which we should ignore.
3160 SDNode *FlagUser = 0;
3161 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3162 FlagUser == 0; ++UI) {
3163 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3165 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3166 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3173 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3174 // give up for right now.
3175 if (FlagUser->getOpcode() == PPCISD::MFCR)
3176 return SDOperand(VCMPoNode, 0);
3181 // If this is a branch on an altivec predicate comparison, lower this so
3182 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3183 // lowering is done pre-legalize, because the legalizer lowers the predicate
3184 // compare down to code that is difficult to reassemble.
3185 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3186 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3190 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3191 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3192 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3193 assert(isDot && "Can't compare against a vector result!");
3195 // If this is a comparison against something other than 0/1, then we know
3196 // that the condition is never/always true.
3197 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3198 if (Val != 0 && Val != 1) {
3199 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3200 return N->getOperand(0);
3201 // Always !=, turn it into an unconditional branch.
3202 return DAG.getNode(ISD::BR, MVT::Other,
3203 N->getOperand(0), N->getOperand(4));
3206 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3208 // Create the PPCISD altivec 'dot' comparison node.
3209 std::vector<MVT::ValueType> VTs;
3211 LHS.getOperand(2), // LHS of compare
3212 LHS.getOperand(3), // RHS of compare
3213 DAG.getConstant(CompareOpc, MVT::i32)
3215 VTs.push_back(LHS.getOperand(2).getValueType());
3216 VTs.push_back(MVT::Flag);
3217 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3219 // Unpack the result based on how the target uses it.
3220 PPC::Predicate CompOpc;
3221 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3222 default: // Can't happen, don't crash on invalid number though.
3223 case 0: // Branch on the value of the EQ bit of CR6.
3224 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3226 case 1: // Branch on the inverted value of the EQ bit of CR6.
3227 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3229 case 2: // Branch on the value of the LT bit of CR6.
3230 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3232 case 3: // Branch on the inverted value of the LT bit of CR6.
3233 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3237 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3238 DAG.getConstant(CompOpc, MVT::i32),
3239 DAG.getRegister(PPC::CR6, MVT::i32),
3240 N->getOperand(4), CompNode.getValue(1));
3249 //===----------------------------------------------------------------------===//
3250 // Inline Assembly Support
3251 //===----------------------------------------------------------------------===//
3253 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3255 uint64_t &KnownZero,
3257 const SelectionDAG &DAG,
3258 unsigned Depth) const {
3261 switch (Op.getOpcode()) {
3263 case PPCISD::LBRX: {
3264 // lhbrx is known to have the top bits cleared out.
3265 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3266 KnownZero = 0xFFFF0000;
3269 case ISD::INTRINSIC_WO_CHAIN: {
3270 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3272 case Intrinsic::ppc_altivec_vcmpbfp_p:
3273 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3274 case Intrinsic::ppc_altivec_vcmpequb_p:
3275 case Intrinsic::ppc_altivec_vcmpequh_p:
3276 case Intrinsic::ppc_altivec_vcmpequw_p:
3277 case Intrinsic::ppc_altivec_vcmpgefp_p:
3278 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3279 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3280 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3281 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3282 case Intrinsic::ppc_altivec_vcmpgtub_p:
3283 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3284 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3285 KnownZero = ~1U; // All bits but the low one are known to be zero.
3293 /// getConstraintType - Given a constraint, return the type of
3294 /// constraint it is for this target.
3295 PPCTargetLowering::ConstraintType
3296 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3297 if (Constraint.size() == 1) {
3298 switch (Constraint[0]) {
3305 return C_RegisterClass;
3308 return TargetLowering::getConstraintType(Constraint);
3311 std::pair<unsigned, const TargetRegisterClass*>
3312 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3313 MVT::ValueType VT) const {
3314 if (Constraint.size() == 1) {
3315 // GCC RS6000 Constraint Letters
3316 switch (Constraint[0]) {
3319 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3320 return std::make_pair(0U, PPC::G8RCRegisterClass);
3321 return std::make_pair(0U, PPC::GPRCRegisterClass);
3324 return std::make_pair(0U, PPC::F4RCRegisterClass);
3325 else if (VT == MVT::f64)
3326 return std::make_pair(0U, PPC::F8RCRegisterClass);
3329 return std::make_pair(0U, PPC::VRRCRegisterClass);
3331 return std::make_pair(0U, PPC::CRRCRegisterClass);
3335 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3339 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3340 /// vector. If it is invalid, don't add anything to Ops.
3341 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3342 std::vector<SDOperand>&Ops,
3343 SelectionDAG &DAG) {
3344 SDOperand Result(0,0);
3355 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3356 if (!CST) return; // Must be an immediate to match.
3357 unsigned Value = CST->getValue();
3359 default: assert(0 && "Unknown constraint letter!");
3360 case 'I': // "I" is a signed 16-bit constant.
3361 if ((short)Value == (int)Value)
3362 Result = DAG.getTargetConstant(Value, Op.getValueType());
3364 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3365 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3366 if ((short)Value == 0)
3367 Result = DAG.getTargetConstant(Value, Op.getValueType());
3369 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3370 if ((Value >> 16) == 0)
3371 Result = DAG.getTargetConstant(Value, Op.getValueType());
3373 case 'M': // "M" is a constant that is greater than 31.
3375 Result = DAG.getTargetConstant(Value, Op.getValueType());
3377 case 'N': // "N" is a positive constant that is an exact power of two.
3378 if ((int)Value > 0 && isPowerOf2_32(Value))
3379 Result = DAG.getTargetConstant(Value, Op.getValueType());
3381 case 'O': // "O" is the constant zero.
3383 Result = DAG.getTargetConstant(Value, Op.getValueType());
3385 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3386 if ((short)-Value == (int)-Value)
3387 Result = DAG.getTargetConstant(Value, Op.getValueType());
3395 Ops.push_back(Result);
3399 // Handle standard constraint letters.
3400 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
3403 // isLegalAddressingMode - Return true if the addressing mode represented
3404 // by AM is legal for this target, for a load/store of the specified type.
3405 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3406 const Type *Ty) const {
3407 // FIXME: PPC does not allow r+i addressing modes for vectors!
3409 // PPC allows a sign-extended 16-bit immediate field.
3410 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3413 // No global is ever allowed as a base.
3417 // PPC only support r+r,
3419 case 0: // "r+i" or just "i", depending on HasBaseReg.
3422 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3424 // Otherwise we have r+r or r+i.
3427 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3429 // Allow 2*r as r+r.
3432 // No other scales are supported.
3439 /// isLegalAddressImmediate - Return true if the integer value can be used
3440 /// as the offset of the target addressing mode for load / store of the
3442 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3443 // PPC allows a sign-extended 16-bit immediate field.
3444 return (V > -(1 << 16) && V < (1 << 16)-1);
3447 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3451 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)
3453 // Depths > 0 not supported yet!
3454 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3457 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3458 bool isPPC64 = PtrVT == MVT::i64;
3460 MachineFunction &MF = DAG.getMachineFunction();
3461 MachineFrameInfo *MFI = MF.getFrameInfo();
3462 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3463 && MFI->getStackSize();
3466 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3469 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,