1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 // FIXME: Remove this once soft-float is supported.
46 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
47 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
49 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
50 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
52 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
53 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
55 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
56 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
58 // FIXME: Remove this once the bug has been fixed!
59 extern cl::opt<bool> ANDIGlueBug;
61 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
62 const PPCSubtarget &STI)
63 : TargetLowering(TM), Subtarget(STI) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
69 // arguments are at least 4/8 bytes aligned.
70 bool isPPC64 = Subtarget.isPPC64();
71 setMinStackArgumentAlignment(isPPC64 ? 8:4);
73 // Set up the register classes.
74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
78 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
79 for (MVT VT : MVT::integer_valuetypes()) {
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // PowerPC has pre-inc load and store's.
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
102 if (Subtarget.useCRBits()) {
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
105 if (isPPC64 || Subtarget.hasFPCVT()) {
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
107 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
108 isPPC64 ? MVT::i64 : MVT::i32);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
110 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
111 isPPC64 ? MVT::i64 : MVT::i32);
113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
117 // PowerPC does not support direct load / store of condition registers
118 setOperationAction(ISD::LOAD, MVT::i1, Custom);
119 setOperationAction(ISD::STORE, MVT::i1, Custom);
121 // FIXME: Remove this once the ANDI glue bug is fixed:
123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setTruncStoreAction(VT, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget.hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
186 Subtarget.hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget.hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget.hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget.hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget.useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget.useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget.useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget.isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget.isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget.has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (Subtarget.hasFPCVT()) {
372 if (Subtarget.has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget.use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget.hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (MVT VT : MVT::vector_valuetypes()) {
405 // add/sub are legal for all supported vector VT's.
406 setOperationAction(ISD::ADD, VT, Legal);
407 setOperationAction(ISD::SUB, VT, Legal);
409 // Vector instructions introduced in P8
410 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
411 setOperationAction(ISD::CTPOP, VT, Legal);
412 setOperationAction(ISD::CTLZ, VT, Legal);
415 setOperationAction(ISD::CTPOP, VT, Expand);
416 setOperationAction(ISD::CTLZ, VT, Expand);
419 // We promote all shuffles to v16i8.
420 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
421 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
423 // We promote all non-typed operations to v4i32.
424 setOperationAction(ISD::AND , VT, Promote);
425 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 setOperationAction(ISD::OR , VT, Promote);
427 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 setOperationAction(ISD::XOR , VT, Promote);
429 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 setOperationAction(ISD::LOAD , VT, Promote);
431 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 setOperationAction(ISD::SELECT, VT, Promote);
433 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 setOperationAction(ISD::SELECT_CC, VT, Promote);
435 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
436 setOperationAction(ISD::STORE, VT, Promote);
437 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
439 // No other operations are legal.
440 setOperationAction(ISD::MUL , VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::SREM, VT, Expand);
443 setOperationAction(ISD::UDIV, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
445 setOperationAction(ISD::FDIV, VT, Expand);
446 setOperationAction(ISD::FREM, VT, Expand);
447 setOperationAction(ISD::FNEG, VT, Expand);
448 setOperationAction(ISD::FSQRT, VT, Expand);
449 setOperationAction(ISD::FLOG, VT, Expand);
450 setOperationAction(ISD::FLOG10, VT, Expand);
451 setOperationAction(ISD::FLOG2, VT, Expand);
452 setOperationAction(ISD::FEXP, VT, Expand);
453 setOperationAction(ISD::FEXP2, VT, Expand);
454 setOperationAction(ISD::FSIN, VT, Expand);
455 setOperationAction(ISD::FCOS, VT, Expand);
456 setOperationAction(ISD::FABS, VT, Expand);
457 setOperationAction(ISD::FPOWI, VT, Expand);
458 setOperationAction(ISD::FFLOOR, VT, Expand);
459 setOperationAction(ISD::FCEIL, VT, Expand);
460 setOperationAction(ISD::FTRUNC, VT, Expand);
461 setOperationAction(ISD::FRINT, VT, Expand);
462 setOperationAction(ISD::FNEARBYINT, VT, Expand);
463 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
464 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
465 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
466 setOperationAction(ISD::MULHU, VT, Expand);
467 setOperationAction(ISD::MULHS, VT, Expand);
468 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
469 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
470 setOperationAction(ISD::UDIVREM, VT, Expand);
471 setOperationAction(ISD::SDIVREM, VT, Expand);
472 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
473 setOperationAction(ISD::FPOW, VT, Expand);
474 setOperationAction(ISD::BSWAP, VT, Expand);
475 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
476 setOperationAction(ISD::CTTZ, VT, Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
478 setOperationAction(ISD::VSELECT, VT, Expand);
479 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
481 for (MVT InnerVT : MVT::vector_valuetypes()) {
482 setTruncStoreAction(VT, InnerVT, Expand);
483 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
484 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
485 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
489 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
490 // with merges, splats, etc.
491 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
493 setOperationAction(ISD::AND , MVT::v4i32, Legal);
494 setOperationAction(ISD::OR , MVT::v4i32, Legal);
495 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
496 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
497 setOperationAction(ISD::SELECT, MVT::v4i32,
498 Subtarget.useCRBits() ? Legal : Expand);
499 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
500 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
501 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
504 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
505 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
506 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
507 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
509 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
511 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
512 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
514 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
515 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
517 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
518 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
519 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
522 if (Subtarget.hasP8Altivec())
523 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
525 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
527 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
528 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
530 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
531 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
535 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
536 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
538 // Altivec does not contain unordered floating-point compare instructions
539 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
540 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
541 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
542 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
544 if (Subtarget.hasVSX()) {
545 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
546 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
547 if (Subtarget.hasP8Vector()) {
548 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
549 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
551 if (Subtarget.hasDirectMove()) {
552 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
553 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
554 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
555 // FIXME: this is causing bootstrap failures, disable temporarily
556 //setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
557 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
558 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
559 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
560 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
562 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
564 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
565 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
566 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
567 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
568 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
570 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
572 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
573 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
575 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
576 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
578 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
579 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
580 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
581 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
582 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
584 // Share the Altivec comparison restrictions.
585 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
586 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
587 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
588 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
590 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
591 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
593 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
595 if (Subtarget.hasP8Vector())
596 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
598 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
600 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
601 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
602 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
604 if (Subtarget.hasP8Altivec()) {
605 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
606 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
607 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
609 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
612 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
613 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
614 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
616 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
618 // VSX v2i64 only supports non-arithmetic operations.
619 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
620 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
623 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
624 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
625 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
626 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
628 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
630 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
631 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
632 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
633 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
635 // Vector operation legalization checks the result type of
636 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
637 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
638 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
639 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
640 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
642 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
645 if (Subtarget.hasP8Altivec()) {
646 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
647 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
651 if (Subtarget.hasQPX()) {
652 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
653 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
654 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
655 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
657 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
658 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
660 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
661 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
663 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
664 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
666 if (!Subtarget.useCRBits())
667 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
668 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
670 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
671 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
672 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
673 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
674 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
675 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
676 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
678 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
679 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
681 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
682 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
683 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
685 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
686 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
687 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
688 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
689 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
690 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
691 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
692 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
693 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
694 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
695 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
697 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
698 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
700 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
701 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
703 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
705 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
706 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
707 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
708 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
710 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
711 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
713 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
714 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
716 if (!Subtarget.useCRBits())
717 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
718 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
721 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
722 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
723 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
724 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
725 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
726 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
728 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
729 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
731 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
732 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
733 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
734 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
735 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
736 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
737 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
738 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
739 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
740 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
741 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
743 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
744 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
746 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
747 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
749 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
751 setOperationAction(ISD::AND , MVT::v4i1, Legal);
752 setOperationAction(ISD::OR , MVT::v4i1, Legal);
753 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
755 if (!Subtarget.useCRBits())
756 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
757 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
759 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
760 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
762 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
763 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
764 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
765 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
766 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
767 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
768 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
770 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
771 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
773 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
775 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
776 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
777 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
778 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
780 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
781 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
782 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
783 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
785 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
786 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
788 // These need to set FE_INEXACT, and so cannot be vectorized here.
789 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
790 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
792 if (TM.Options.UnsafeFPMath) {
793 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
794 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
796 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
797 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
799 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
800 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
802 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
803 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
807 if (Subtarget.has64BitSupport())
808 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
810 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
813 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
814 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
817 setBooleanContents(ZeroOrOneBooleanContent);
819 if (Subtarget.hasAltivec()) {
820 // Altivec instructions set fields to all zeros or all ones.
821 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
825 // These libcalls are not available in 32-bit.
826 setLibcallName(RTLIB::SHL_I128, nullptr);
827 setLibcallName(RTLIB::SRL_I128, nullptr);
828 setLibcallName(RTLIB::SRA_I128, nullptr);
832 setStackPointerRegisterToSaveRestore(PPC::X1);
833 setExceptionPointerRegister(PPC::X3);
834 setExceptionSelectorRegister(PPC::X4);
836 setStackPointerRegisterToSaveRestore(PPC::R1);
837 setExceptionPointerRegister(PPC::R3);
838 setExceptionSelectorRegister(PPC::R4);
841 // We have target-specific dag combine patterns for the following nodes:
842 setTargetDAGCombine(ISD::SINT_TO_FP);
843 if (Subtarget.hasFPCVT())
844 setTargetDAGCombine(ISD::UINT_TO_FP);
845 setTargetDAGCombine(ISD::LOAD);
846 setTargetDAGCombine(ISD::STORE);
847 setTargetDAGCombine(ISD::BR_CC);
848 if (Subtarget.useCRBits())
849 setTargetDAGCombine(ISD::BRCOND);
850 setTargetDAGCombine(ISD::BSWAP);
851 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
852 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
853 setTargetDAGCombine(ISD::INTRINSIC_VOID);
855 setTargetDAGCombine(ISD::SIGN_EXTEND);
856 setTargetDAGCombine(ISD::ZERO_EXTEND);
857 setTargetDAGCombine(ISD::ANY_EXTEND);
859 if (Subtarget.useCRBits()) {
860 setTargetDAGCombine(ISD::TRUNCATE);
861 setTargetDAGCombine(ISD::SETCC);
862 setTargetDAGCombine(ISD::SELECT_CC);
865 // Use reciprocal estimates.
866 if (TM.Options.UnsafeFPMath) {
867 setTargetDAGCombine(ISD::FDIV);
868 setTargetDAGCombine(ISD::FSQRT);
871 // Darwin long double math library functions have $LDBL128 appended.
872 if (Subtarget.isDarwin()) {
873 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
874 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
875 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
876 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
877 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
878 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
879 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
880 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
881 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
882 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
885 // With 32 condition bits, we don't need to sink (and duplicate) compares
886 // aggressively in CodeGenPrep.
887 if (Subtarget.useCRBits()) {
888 setHasMultipleConditionRegisters();
889 setJumpIsExpensive();
892 setMinFunctionAlignment(2);
893 if (Subtarget.isDarwin())
894 setPrefFunctionAlignment(4);
896 switch (Subtarget.getDarwinDirective()) {
900 case PPC::DIR_E500mc:
909 setPrefFunctionAlignment(4);
910 setPrefLoopAlignment(4);
914 setInsertFencesForAtomic(true);
916 if (Subtarget.enableMachineScheduler())
917 setSchedulingPreference(Sched::Source);
919 setSchedulingPreference(Sched::Hybrid);
921 computeRegisterProperties(STI.getRegisterInfo());
923 // The Freescale cores do better with aggressive inlining of memcpy and
924 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
925 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
926 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
927 MaxStoresPerMemset = 32;
928 MaxStoresPerMemsetOptSize = 16;
929 MaxStoresPerMemcpy = 32;
930 MaxStoresPerMemcpyOptSize = 8;
931 MaxStoresPerMemmove = 32;
932 MaxStoresPerMemmoveOptSize = 8;
933 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
934 // The A2 also benefits from (very) aggressive inlining of memcpy and
935 // friends. The overhead of a the function call, even when warm, can be
936 // over one hundred cycles.
937 MaxStoresPerMemset = 128;
938 MaxStoresPerMemcpy = 128;
939 MaxStoresPerMemmove = 128;
943 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
944 /// the desired ByVal argument alignment.
945 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
946 unsigned MaxMaxAlign) {
947 if (MaxAlign == MaxMaxAlign)
949 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
950 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
952 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
954 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
955 unsigned EltAlign = 0;
956 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
957 if (EltAlign > MaxAlign)
959 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
960 for (auto *EltTy : STy->elements()) {
961 unsigned EltAlign = 0;
962 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
963 if (EltAlign > MaxAlign)
965 if (MaxAlign == MaxMaxAlign)
971 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
972 /// function arguments in the caller parameter area.
973 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
974 const DataLayout &DL) const {
975 // Darwin passes everything on 4 byte boundary.
976 if (Subtarget.isDarwin())
979 // 16byte and wider vectors are passed on 16byte boundary.
980 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
981 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
982 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
983 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
987 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
988 switch ((PPCISD::NodeType)Opcode) {
989 case PPCISD::FIRST_NUMBER: break;
990 case PPCISD::FSEL: return "PPCISD::FSEL";
991 case PPCISD::FCFID: return "PPCISD::FCFID";
992 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
993 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
994 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
995 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
996 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
997 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
998 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
999 case PPCISD::FRE: return "PPCISD::FRE";
1000 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1001 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1002 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
1003 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
1004 case PPCISD::VPERM: return "PPCISD::VPERM";
1005 case PPCISD::CMPB: return "PPCISD::CMPB";
1006 case PPCISD::Hi: return "PPCISD::Hi";
1007 case PPCISD::Lo: return "PPCISD::Lo";
1008 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1009 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1010 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1011 case PPCISD::SRL: return "PPCISD::SRL";
1012 case PPCISD::SRA: return "PPCISD::SRA";
1013 case PPCISD::SHL: return "PPCISD::SHL";
1014 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1015 case PPCISD::CALL: return "PPCISD::CALL";
1016 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1017 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1018 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1019 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1020 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1021 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1022 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1023 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1024 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1025 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1026 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1027 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1028 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1029 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1030 case PPCISD::VCMP: return "PPCISD::VCMP";
1031 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1032 case PPCISD::LBRX: return "PPCISD::LBRX";
1033 case PPCISD::STBRX: return "PPCISD::STBRX";
1034 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1035 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1036 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1037 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1038 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1039 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1040 case PPCISD::BDZ: return "PPCISD::BDZ";
1041 case PPCISD::MFFS: return "PPCISD::MFFS";
1042 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1043 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1044 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1045 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1046 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1047 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1048 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1049 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1050 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1051 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1052 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1053 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1054 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1055 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1056 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1057 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1058 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1059 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1060 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1061 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1062 case PPCISD::SC: return "PPCISD::SC";
1063 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1064 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1065 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1066 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1067 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1068 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1069 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1070 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1071 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1072 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1077 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1080 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1082 if (Subtarget.hasQPX())
1083 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1085 return VT.changeVectorElementTypeToInteger();
1088 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1089 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1093 //===----------------------------------------------------------------------===//
1094 // Node matching predicates, for use by the tblgen matching code.
1095 //===----------------------------------------------------------------------===//
1097 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1098 static bool isFloatingPointZero(SDValue Op) {
1099 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1100 return CFP->getValueAPF().isZero();
1101 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1102 // Maybe this has already been legalized into the constant pool?
1103 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1104 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1105 return CFP->getValueAPF().isZero();
1110 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1111 /// true if Op is undef or if it matches the specified value.
1112 static bool isConstantOrUndef(int Op, int Val) {
1113 return Op < 0 || Op == Val;
1116 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1117 /// VPKUHUM instruction.
1118 /// The ShuffleKind distinguishes between big-endian operations with
1119 /// two different inputs (0), either-endian operations with two identical
1120 /// inputs (1), and little-endian operations with two different inputs (2).
1121 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1122 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1123 SelectionDAG &DAG) {
1124 bool IsLE = DAG.getDataLayout().isLittleEndian();
1125 if (ShuffleKind == 0) {
1128 for (unsigned i = 0; i != 16; ++i)
1129 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1131 } else if (ShuffleKind == 2) {
1134 for (unsigned i = 0; i != 16; ++i)
1135 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1137 } else if (ShuffleKind == 1) {
1138 unsigned j = IsLE ? 0 : 1;
1139 for (unsigned i = 0; i != 8; ++i)
1140 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1141 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1147 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1148 /// VPKUWUM instruction.
1149 /// The ShuffleKind distinguishes between big-endian operations with
1150 /// two different inputs (0), either-endian operations with two identical
1151 /// inputs (1), and little-endian operations with two different inputs (2).
1152 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1153 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1154 SelectionDAG &DAG) {
1155 bool IsLE = DAG.getDataLayout().isLittleEndian();
1156 if (ShuffleKind == 0) {
1159 for (unsigned i = 0; i != 16; i += 2)
1160 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1161 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1163 } else if (ShuffleKind == 2) {
1166 for (unsigned i = 0; i != 16; i += 2)
1167 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1168 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1170 } else if (ShuffleKind == 1) {
1171 unsigned j = IsLE ? 0 : 2;
1172 for (unsigned i = 0; i != 8; i += 2)
1173 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1174 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1175 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1176 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1182 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1183 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1184 /// current subtarget.
1186 /// The ShuffleKind distinguishes between big-endian operations with
1187 /// two different inputs (0), either-endian operations with two identical
1188 /// inputs (1), and little-endian operations with two different inputs (2).
1189 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1190 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1191 SelectionDAG &DAG) {
1192 const PPCSubtarget& Subtarget =
1193 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1194 if (!Subtarget.hasP8Vector())
1197 bool IsLE = DAG.getDataLayout().isLittleEndian();
1198 if (ShuffleKind == 0) {
1201 for (unsigned i = 0; i != 16; i += 4)
1202 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1203 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1204 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1205 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1207 } else if (ShuffleKind == 2) {
1210 for (unsigned i = 0; i != 16; i += 4)
1211 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1212 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1213 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1214 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1216 } else if (ShuffleKind == 1) {
1217 unsigned j = IsLE ? 0 : 4;
1218 for (unsigned i = 0; i != 8; i += 4)
1219 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1220 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1221 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1222 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1223 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1224 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1225 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1226 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1232 /// isVMerge - Common function, used to match vmrg* shuffles.
1234 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1235 unsigned LHSStart, unsigned RHSStart) {
1236 if (N->getValueType(0) != MVT::v16i8)
1238 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1239 "Unsupported merge size!");
1241 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1242 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1243 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1244 LHSStart+j+i*UnitSize) ||
1245 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1246 RHSStart+j+i*UnitSize))
1252 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1253 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1254 /// The ShuffleKind distinguishes between big-endian merges with two
1255 /// different inputs (0), either-endian merges with two identical inputs (1),
1256 /// and little-endian merges with two different inputs (2). For the latter,
1257 /// the input operands are swapped (see PPCInstrAltivec.td).
1258 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1259 unsigned ShuffleKind, SelectionDAG &DAG) {
1260 if (DAG.getDataLayout().isLittleEndian()) {
1261 if (ShuffleKind == 1) // unary
1262 return isVMerge(N, UnitSize, 0, 0);
1263 else if (ShuffleKind == 2) // swapped
1264 return isVMerge(N, UnitSize, 0, 16);
1268 if (ShuffleKind == 1) // unary
1269 return isVMerge(N, UnitSize, 8, 8);
1270 else if (ShuffleKind == 0) // normal
1271 return isVMerge(N, UnitSize, 8, 24);
1277 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1278 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1279 /// The ShuffleKind distinguishes between big-endian merges with two
1280 /// different inputs (0), either-endian merges with two identical inputs (1),
1281 /// and little-endian merges with two different inputs (2). For the latter,
1282 /// the input operands are swapped (see PPCInstrAltivec.td).
1283 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1284 unsigned ShuffleKind, SelectionDAG &DAG) {
1285 if (DAG.getDataLayout().isLittleEndian()) {
1286 if (ShuffleKind == 1) // unary
1287 return isVMerge(N, UnitSize, 8, 8);
1288 else if (ShuffleKind == 2) // swapped
1289 return isVMerge(N, UnitSize, 8, 24);
1293 if (ShuffleKind == 1) // unary
1294 return isVMerge(N, UnitSize, 0, 0);
1295 else if (ShuffleKind == 0) // normal
1296 return isVMerge(N, UnitSize, 0, 16);
1303 * \brief Common function used to match vmrgew and vmrgow shuffles
1305 * The indexOffset determines whether to look for even or odd words in
1306 * the shuffle mask. This is based on the of the endianness of the target
1309 * - Use offset of 0 to check for odd elements
1310 * - Use offset of 4 to check for even elements
1312 * - Use offset of 0 to check for even elements
1313 * - Use offset of 4 to check for odd elements
1314 * A detailed description of the vector element ordering for little endian and
1315 * big endian can be found at
1316 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1317 * Targeting your applications - what little endian and big endian IBM XL C/C++
1318 * compiler differences mean to you
1320 * The mask to the shuffle vector instruction specifies the indices of the
1321 * elements from the two input vectors to place in the result. The elements are
1322 * numbered in array-access order, starting with the first vector. These vectors
1323 * are always of type v16i8, thus each vector will contain 16 elements of size
1324 * 8. More info on the shuffle vector can be found in the
1325 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1326 * Language Reference.
1328 * The RHSStartValue indicates whether the same input vectors are used (unary)
1329 * or two different input vectors are used, based on the following:
1330 * - If the instruction uses the same vector for both inputs, the range of the
1331 * indices will be 0 to 15. In this case, the RHSStart value passed should
1333 * - If the instruction has two different vectors then the range of the
1334 * indices will be 0 to 31. In this case, the RHSStart value passed should
1335 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1336 * to 31 specify elements in the second vector).
1338 * \param[in] N The shuffle vector SD Node to analyze
1339 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1340 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1341 * vector to the shuffle_vector instruction
1342 * \return true iff this shuffle vector represents an even or odd word merge
1344 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1345 unsigned RHSStartValue) {
1346 if (N->getValueType(0) != MVT::v16i8)
1349 for (unsigned i = 0; i < 2; ++i)
1350 for (unsigned j = 0; j < 4; ++j)
1351 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1352 i*RHSStartValue+j+IndexOffset) ||
1353 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1354 i*RHSStartValue+j+IndexOffset+8))
1360 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1361 * vmrgow instructions.
1363 * \param[in] N The shuffle vector SD Node to analyze
1364 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1365 * \param[in] ShuffleKind Identify the type of merge:
1366 * - 0 = big-endian merge with two different inputs;
1367 * - 1 = either-endian merge with two identical inputs;
1368 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1369 * little-endian merges).
1370 * \param[in] DAG The current SelectionDAG
1371 * \return true iff this shuffle mask
1373 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1374 unsigned ShuffleKind, SelectionDAG &DAG) {
1375 if (DAG.getDataLayout().isLittleEndian()) {
1376 unsigned indexOffset = CheckEven ? 4 : 0;
1377 if (ShuffleKind == 1) // Unary
1378 return isVMerge(N, indexOffset, 0);
1379 else if (ShuffleKind == 2) // swapped
1380 return isVMerge(N, indexOffset, 16);
1385 unsigned indexOffset = CheckEven ? 0 : 4;
1386 if (ShuffleKind == 1) // Unary
1387 return isVMerge(N, indexOffset, 0);
1388 else if (ShuffleKind == 0) // Normal
1389 return isVMerge(N, indexOffset, 16);
1396 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1397 /// amount, otherwise return -1.
1398 /// The ShuffleKind distinguishes between big-endian operations with two
1399 /// different inputs (0), either-endian operations with two identical inputs
1400 /// (1), and little-endian operations with two different inputs (2). For the
1401 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1402 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1403 SelectionDAG &DAG) {
1404 if (N->getValueType(0) != MVT::v16i8)
1407 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1409 // Find the first non-undef value in the shuffle mask.
1411 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1414 if (i == 16) return -1; // all undef.
1416 // Otherwise, check to see if the rest of the elements are consecutively
1417 // numbered from this value.
1418 unsigned ShiftAmt = SVOp->getMaskElt(i);
1419 if (ShiftAmt < i) return -1;
1422 bool isLE = DAG.getDataLayout().isLittleEndian();
1424 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1425 // Check the rest of the elements to see if they are consecutive.
1426 for (++i; i != 16; ++i)
1427 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1429 } else if (ShuffleKind == 1) {
1430 // Check the rest of the elements to see if they are consecutive.
1431 for (++i; i != 16; ++i)
1432 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1438 ShiftAmt = 16 - ShiftAmt;
1443 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1444 /// specifies a splat of a single element that is suitable for input to
1445 /// VSPLTB/VSPLTH/VSPLTW.
1446 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1447 assert(N->getValueType(0) == MVT::v16i8 &&
1448 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1450 // The consecutive indices need to specify an element, not part of two
1451 // different elements. So abandon ship early if this isn't the case.
1452 if (N->getMaskElt(0) % EltSize != 0)
1455 // This is a splat operation if each element of the permute is the same, and
1456 // if the value doesn't reference the second vector.
1457 unsigned ElementBase = N->getMaskElt(0);
1459 // FIXME: Handle UNDEF elements too!
1460 if (ElementBase >= 16)
1463 // Check that the indices are consecutive, in the case of a multi-byte element
1464 // splatted with a v16i8 mask.
1465 for (unsigned i = 1; i != EltSize; ++i)
1466 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1469 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1470 if (N->getMaskElt(i) < 0) continue;
1471 for (unsigned j = 0; j != EltSize; ++j)
1472 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1478 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1479 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1480 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1481 SelectionDAG &DAG) {
1482 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1483 assert(isSplatShuffleMask(SVOp, EltSize));
1484 if (DAG.getDataLayout().isLittleEndian())
1485 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1487 return SVOp->getMaskElt(0) / EltSize;
1490 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1491 /// by using a vspltis[bhw] instruction of the specified element size, return
1492 /// the constant being splatted. The ByteSize field indicates the number of
1493 /// bytes of each element [124] -> [bhw].
1494 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1495 SDValue OpVal(nullptr, 0);
1497 // If ByteSize of the splat is bigger than the element size of the
1498 // build_vector, then we have a case where we are checking for a splat where
1499 // multiple elements of the buildvector are folded together into a single
1500 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1501 unsigned EltSize = 16/N->getNumOperands();
1502 if (EltSize < ByteSize) {
1503 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1504 SDValue UniquedVals[4];
1505 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1507 // See if all of the elements in the buildvector agree across.
1508 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1509 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1510 // If the element isn't a constant, bail fully out.
1511 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1514 if (!UniquedVals[i&(Multiple-1)].getNode())
1515 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1516 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1517 return SDValue(); // no match.
1520 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1521 // either constant or undef values that are identical for each chunk. See
1522 // if these chunks can form into a larger vspltis*.
1524 // Check to see if all of the leading entries are either 0 or -1. If
1525 // neither, then this won't fit into the immediate field.
1526 bool LeadingZero = true;
1527 bool LeadingOnes = true;
1528 for (unsigned i = 0; i != Multiple-1; ++i) {
1529 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1531 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1532 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1534 // Finally, check the least significant entry.
1536 if (!UniquedVals[Multiple-1].getNode())
1537 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1538 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1539 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1540 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1543 if (!UniquedVals[Multiple-1].getNode())
1544 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1545 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1546 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1547 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1553 // Check to see if this buildvec has a single non-undef value in its elements.
1554 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1555 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1556 if (!OpVal.getNode())
1557 OpVal = N->getOperand(i);
1558 else if (OpVal != N->getOperand(i))
1562 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1564 unsigned ValSizeInBytes = EltSize;
1566 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1567 Value = CN->getZExtValue();
1568 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1569 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1570 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1573 // If the splat value is larger than the element value, then we can never do
1574 // this splat. The only case that we could fit the replicated bits into our
1575 // immediate field for would be zero, and we prefer to use vxor for it.
1576 if (ValSizeInBytes < ByteSize) return SDValue();
1578 // If the element value is larger than the splat value, check if it consists
1579 // of a repeated bit pattern of size ByteSize.
1580 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1583 // Properly sign extend the value.
1584 int MaskVal = SignExtend32(Value, ByteSize * 8);
1586 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1587 if (MaskVal == 0) return SDValue();
1589 // Finally, if this value fits in a 5 bit sext field, return it
1590 if (SignExtend32<5>(MaskVal) == MaskVal)
1591 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1595 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1596 /// amount, otherwise return -1.
1597 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1598 EVT VT = N->getValueType(0);
1599 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1602 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1604 // Find the first non-undef value in the shuffle mask.
1606 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1609 if (i == 4) return -1; // all undef.
1611 // Otherwise, check to see if the rest of the elements are consecutively
1612 // numbered from this value.
1613 unsigned ShiftAmt = SVOp->getMaskElt(i);
1614 if (ShiftAmt < i) return -1;
1617 // Check the rest of the elements to see if they are consecutive.
1618 for (++i; i != 4; ++i)
1619 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1625 //===----------------------------------------------------------------------===//
1626 // Addressing Mode Selection
1627 //===----------------------------------------------------------------------===//
1629 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1630 /// or 64-bit immediate, and if the value can be accurately represented as a
1631 /// sign extension from a 16-bit value. If so, this returns true and the
1633 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1634 if (!isa<ConstantSDNode>(N))
1637 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1638 if (N->getValueType(0) == MVT::i32)
1639 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1641 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1643 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1644 return isIntS16Immediate(Op.getNode(), Imm);
1647 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1648 /// can be represented as an indexed [r+r] operation. Returns false if it
1649 /// can be more efficiently represented with [r+imm].
1650 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1652 SelectionDAG &DAG) const {
1654 if (N.getOpcode() == ISD::ADD) {
1655 if (isIntS16Immediate(N.getOperand(1), imm))
1656 return false; // r+i
1657 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1658 return false; // r+i
1660 Base = N.getOperand(0);
1661 Index = N.getOperand(1);
1663 } else if (N.getOpcode() == ISD::OR) {
1664 if (isIntS16Immediate(N.getOperand(1), imm))
1665 return false; // r+i can fold it if we can.
1667 // If this is an or of disjoint bitfields, we can codegen this as an add
1668 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1670 APInt LHSKnownZero, LHSKnownOne;
1671 APInt RHSKnownZero, RHSKnownOne;
1672 DAG.computeKnownBits(N.getOperand(0),
1673 LHSKnownZero, LHSKnownOne);
1675 if (LHSKnownZero.getBoolValue()) {
1676 DAG.computeKnownBits(N.getOperand(1),
1677 RHSKnownZero, RHSKnownOne);
1678 // If all of the bits are known zero on the LHS or RHS, the add won't
1680 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1681 Base = N.getOperand(0);
1682 Index = N.getOperand(1);
1691 // If we happen to be doing an i64 load or store into a stack slot that has
1692 // less than a 4-byte alignment, then the frame-index elimination may need to
1693 // use an indexed load or store instruction (because the offset may not be a
1694 // multiple of 4). The extra register needed to hold the offset comes from the
1695 // register scavenger, and it is possible that the scavenger will need to use
1696 // an emergency spill slot. As a result, we need to make sure that a spill slot
1697 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1699 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1700 // FIXME: This does not handle the LWA case.
1704 // NOTE: We'll exclude negative FIs here, which come from argument
1705 // lowering, because there are no known test cases triggering this problem
1706 // using packed structures (or similar). We can remove this exclusion if
1707 // we find such a test case. The reason why this is so test-case driven is
1708 // because this entire 'fixup' is only to prevent crashes (from the
1709 // register scavenger) on not-really-valid inputs. For example, if we have:
1711 // %b = bitcast i1* %a to i64*
1712 // store i64* a, i64 b
1713 // then the store should really be marked as 'align 1', but is not. If it
1714 // were marked as 'align 1' then the indexed form would have been
1715 // instruction-selected initially, and the problem this 'fixup' is preventing
1716 // won't happen regardless.
1720 MachineFunction &MF = DAG.getMachineFunction();
1721 MachineFrameInfo *MFI = MF.getFrameInfo();
1723 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1727 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1728 FuncInfo->setHasNonRISpills();
1731 /// Returns true if the address N can be represented by a base register plus
1732 /// a signed 16-bit displacement [r+imm], and if it is not better
1733 /// represented as reg+reg. If Aligned is true, only accept displacements
1734 /// suitable for STD and friends, i.e. multiples of 4.
1735 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1738 bool Aligned) const {
1739 // FIXME dl should come from parent load or store, not from address
1741 // If this can be more profitably realized as r+r, fail.
1742 if (SelectAddressRegReg(N, Disp, Base, DAG))
1745 if (N.getOpcode() == ISD::ADD) {
1747 if (isIntS16Immediate(N.getOperand(1), imm) &&
1748 (!Aligned || (imm & 3) == 0)) {
1749 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1750 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1751 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1752 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1754 Base = N.getOperand(0);
1756 return true; // [r+i]
1757 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1758 // Match LOAD (ADD (X, Lo(G))).
1759 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1760 && "Cannot handle constant offsets yet!");
1761 Disp = N.getOperand(1).getOperand(0); // The global address.
1762 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1763 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1764 Disp.getOpcode() == ISD::TargetConstantPool ||
1765 Disp.getOpcode() == ISD::TargetJumpTable);
1766 Base = N.getOperand(0);
1767 return true; // [&g+r]
1769 } else if (N.getOpcode() == ISD::OR) {
1771 if (isIntS16Immediate(N.getOperand(1), imm) &&
1772 (!Aligned || (imm & 3) == 0)) {
1773 // If this is an or of disjoint bitfields, we can codegen this as an add
1774 // (for better address arithmetic) if the LHS and RHS of the OR are
1775 // provably disjoint.
1776 APInt LHSKnownZero, LHSKnownOne;
1777 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1779 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1780 // If all of the bits are known zero on the LHS or RHS, the add won't
1782 if (FrameIndexSDNode *FI =
1783 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1784 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1785 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1787 Base = N.getOperand(0);
1789 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1793 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1794 // Loading from a constant address.
1796 // If this address fits entirely in a 16-bit sext immediate field, codegen
1799 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1800 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1801 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1802 CN->getValueType(0));
1806 // Handle 32-bit sext immediates with LIS + addr mode.
1807 if ((CN->getValueType(0) == MVT::i32 ||
1808 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1809 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1810 int Addr = (int)CN->getZExtValue();
1812 // Otherwise, break this down into an LIS + disp.
1813 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1815 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1817 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1818 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1823 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
1824 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1825 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1826 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1829 return true; // [r+0]
1832 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1833 /// represented as an indexed [r+r] operation.
1834 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1836 SelectionDAG &DAG) const {
1837 // Check to see if we can easily represent this as an [r+r] address. This
1838 // will fail if it thinks that the address is more profitably represented as
1839 // reg+imm, e.g. where imm = 0.
1840 if (SelectAddressRegReg(N, Base, Index, DAG))
1843 // If the operand is an addition, always emit this as [r+r], since this is
1844 // better (for code size, and execution, as the memop does the add for free)
1845 // than emitting an explicit add.
1846 if (N.getOpcode() == ISD::ADD) {
1847 Base = N.getOperand(0);
1848 Index = N.getOperand(1);
1852 // Otherwise, do it the hard way, using R0 as the base register.
1853 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1859 /// getPreIndexedAddressParts - returns true by value, base pointer and
1860 /// offset pointer and addressing mode by reference if the node's address
1861 /// can be legally represented as pre-indexed load / store address.
1862 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1864 ISD::MemIndexedMode &AM,
1865 SelectionDAG &DAG) const {
1866 if (DisablePPCPreinc) return false;
1872 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1873 Ptr = LD->getBasePtr();
1874 VT = LD->getMemoryVT();
1875 Alignment = LD->getAlignment();
1876 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1877 Ptr = ST->getBasePtr();
1878 VT = ST->getMemoryVT();
1879 Alignment = ST->getAlignment();
1884 // PowerPC doesn't have preinc load/store instructions for vectors (except
1885 // for QPX, which does have preinc r+r forms).
1886 if (VT.isVector()) {
1887 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1889 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1895 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1897 // Common code will reject creating a pre-inc form if the base pointer
1898 // is a frame index, or if N is a store and the base pointer is either
1899 // the same as or a predecessor of the value being stored. Check for
1900 // those situations here, and try with swapped Base/Offset instead.
1903 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1906 SDValue Val = cast<StoreSDNode>(N)->getValue();
1907 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1912 std::swap(Base, Offset);
1918 // LDU/STU can only handle immediates that are a multiple of 4.
1919 if (VT != MVT::i64) {
1920 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1923 // LDU/STU need an address with at least 4-byte alignment.
1927 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1931 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1932 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1933 // sext i32 to i64 when addr mode is r+i.
1934 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1935 LD->getExtensionType() == ISD::SEXTLOAD &&
1936 isa<ConstantSDNode>(Offset))
1944 //===----------------------------------------------------------------------===//
1945 // LowerOperation implementation
1946 //===----------------------------------------------------------------------===//
1948 /// GetLabelAccessInfo - Return true if we should reference labels using a
1949 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1950 static bool GetLabelAccessInfo(const TargetMachine &TM,
1951 const PPCSubtarget &Subtarget,
1952 unsigned &HiOpFlags, unsigned &LoOpFlags,
1953 const GlobalValue *GV = nullptr) {
1954 HiOpFlags = PPCII::MO_HA;
1955 LoOpFlags = PPCII::MO_LO;
1957 // Don't use the pic base if not in PIC relocation model.
1958 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1961 HiOpFlags |= PPCII::MO_PIC_FLAG;
1962 LoOpFlags |= PPCII::MO_PIC_FLAG;
1965 // If this is a reference to a global value that requires a non-lazy-ptr, make
1966 // sure that instruction lowering adds it.
1967 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1968 HiOpFlags |= PPCII::MO_NLP_FLAG;
1969 LoOpFlags |= PPCII::MO_NLP_FLAG;
1971 if (GV->hasHiddenVisibility()) {
1972 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1973 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1980 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1981 SelectionDAG &DAG) {
1983 EVT PtrVT = HiPart.getValueType();
1984 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1986 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1987 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1989 // With PIC, the first instruction is actually "GR+hi(&G)".
1991 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1992 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1994 // Generate non-pic code that has direct accesses to the constant pool.
1995 // The address of the global is just (hi(&g)+lo(&g)).
1996 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1999 static void setUsesTOCBasePtr(MachineFunction &MF) {
2000 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2001 FuncInfo->setUsesTOCBasePtr();
2004 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2005 setUsesTOCBasePtr(DAG.getMachineFunction());
2008 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
2010 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2011 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2012 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2014 SDValue Ops[] = { GA, Reg };
2015 return DAG.getMemIntrinsicNode(
2016 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2017 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0, false, true,
2021 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2022 SelectionDAG &DAG) const {
2023 EVT PtrVT = Op.getValueType();
2024 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2025 const Constant *C = CP->getConstVal();
2027 // 64-bit SVR4 ABI code is always position-independent.
2028 // The actual address of the GlobalValue is stored in the TOC.
2029 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2030 setUsesTOCBasePtr(DAG);
2031 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2032 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2035 unsigned MOHiFlag, MOLoFlag;
2037 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2039 if (isPIC && Subtarget.isSVR4ABI()) {
2040 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2041 PPCII::MO_PIC_FLAG);
2042 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2046 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2048 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2049 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2052 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2053 EVT PtrVT = Op.getValueType();
2054 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2056 // 64-bit SVR4 ABI code is always position-independent.
2057 // The actual address of the GlobalValue is stored in the TOC.
2058 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2059 setUsesTOCBasePtr(DAG);
2060 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2061 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2064 unsigned MOHiFlag, MOLoFlag;
2066 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2068 if (isPIC && Subtarget.isSVR4ABI()) {
2069 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2070 PPCII::MO_PIC_FLAG);
2071 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2074 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2075 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2076 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2079 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2080 SelectionDAG &DAG) const {
2081 EVT PtrVT = Op.getValueType();
2082 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2083 const BlockAddress *BA = BASDN->getBlockAddress();
2085 // 64-bit SVR4 ABI code is always position-independent.
2086 // The actual BlockAddress is stored in the TOC.
2087 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2088 setUsesTOCBasePtr(DAG);
2089 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2090 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2093 unsigned MOHiFlag, MOLoFlag;
2095 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2096 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2097 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2098 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2101 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2102 SelectionDAG &DAG) const {
2104 // FIXME: TLS addresses currently use medium model code sequences,
2105 // which is the most useful form. Eventually support for small and
2106 // large models could be added if users need it, at the cost of
2107 // additional complexity.
2108 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2109 if (DAG.getTarget().Options.EmulatedTLS)
2110 return LowerToTLSEmulatedModel(GA, DAG);
2113 const GlobalValue *GV = GA->getGlobal();
2114 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2115 bool is64bit = Subtarget.isPPC64();
2116 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2117 PICLevel::Level picLevel = M->getPICLevel();
2119 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2121 if (Model == TLSModel::LocalExec) {
2122 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2123 PPCII::MO_TPREL_HA);
2124 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2125 PPCII::MO_TPREL_LO);
2126 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2127 is64bit ? MVT::i64 : MVT::i32);
2128 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2129 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2132 if (Model == TLSModel::InitialExec) {
2133 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2134 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2138 setUsesTOCBasePtr(DAG);
2139 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2140 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2141 PtrVT, GOTReg, TGA);
2143 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2144 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2145 PtrVT, TGA, GOTPtr);
2146 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2149 if (Model == TLSModel::GeneralDynamic) {
2150 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2153 setUsesTOCBasePtr(DAG);
2154 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2155 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2158 if (picLevel == PICLevel::Small)
2159 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2161 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2163 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2167 if (Model == TLSModel::LocalDynamic) {
2168 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2171 setUsesTOCBasePtr(DAG);
2172 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2173 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2176 if (picLevel == PICLevel::Small)
2177 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2179 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2181 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2182 PtrVT, GOTPtr, TGA, TGA);
2183 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2184 PtrVT, TLSAddr, TGA);
2185 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2188 llvm_unreachable("Unknown TLS model!");
2191 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2192 SelectionDAG &DAG) const {
2193 EVT PtrVT = Op.getValueType();
2194 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2196 const GlobalValue *GV = GSDN->getGlobal();
2198 // 64-bit SVR4 ABI code is always position-independent.
2199 // The actual address of the GlobalValue is stored in the TOC.
2200 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2201 setUsesTOCBasePtr(DAG);
2202 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2203 return getTOCEntry(DAG, DL, true, GA);
2206 unsigned MOHiFlag, MOLoFlag;
2208 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2210 if (isPIC && Subtarget.isSVR4ABI()) {
2211 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2213 PPCII::MO_PIC_FLAG);
2214 return getTOCEntry(DAG, DL, false, GA);
2218 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2220 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2222 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2224 // If the global reference is actually to a non-lazy-pointer, we have to do an
2225 // extra load to get the address of the global.
2226 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2227 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2228 false, false, false, 0);
2232 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2233 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2236 if (Op.getValueType() == MVT::v2i64) {
2237 // When the operands themselves are v2i64 values, we need to do something
2238 // special because VSX has no underlying comparison operations for these.
2239 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2240 // Equality can be handled by casting to the legal type for Altivec
2241 // comparisons, everything else needs to be expanded.
2242 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2243 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2244 DAG.getSetCC(dl, MVT::v4i32,
2245 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2246 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2253 // We handle most of these in the usual way.
2257 // If we're comparing for equality to zero, expose the fact that this is
2258 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2259 // fold the new nodes.
2260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2261 if (C->isNullValue() && CC == ISD::SETEQ) {
2262 EVT VT = Op.getOperand(0).getValueType();
2263 SDValue Zext = Op.getOperand(0);
2264 if (VT.bitsLT(MVT::i32)) {
2266 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2268 unsigned Log2b = Log2_32(VT.getSizeInBits());
2269 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2270 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2271 DAG.getConstant(Log2b, dl, MVT::i32));
2272 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2274 // Leave comparisons against 0 and -1 alone for now, since they're usually
2275 // optimized. FIXME: revisit this when we can custom lower all setcc
2277 if (C->isAllOnesValue() || C->isNullValue())
2281 // If we have an integer seteq/setne, turn it into a compare against zero
2282 // by xor'ing the rhs with the lhs, which is faster than setting a
2283 // condition register, reading it back out, and masking the correct bit. The
2284 // normal approach here uses sub to do this instead of xor. Using xor exposes
2285 // the result to other bit-twiddling opportunities.
2286 EVT LHSVT = Op.getOperand(0).getValueType();
2287 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2288 EVT VT = Op.getValueType();
2289 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2291 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2296 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2297 const PPCSubtarget &Subtarget) const {
2298 SDNode *Node = Op.getNode();
2299 EVT VT = Node->getValueType(0);
2300 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2301 SDValue InChain = Node->getOperand(0);
2302 SDValue VAListPtr = Node->getOperand(1);
2303 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2306 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2309 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2310 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2311 false, false, false, 0);
2312 InChain = GprIndex.getValue(1);
2314 if (VT == MVT::i64) {
2315 // Check if GprIndex is even
2316 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2317 DAG.getConstant(1, dl, MVT::i32));
2318 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2319 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2320 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2321 DAG.getConstant(1, dl, MVT::i32));
2322 // Align GprIndex to be even if it isn't
2323 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2327 // fpr index is 1 byte after gpr
2328 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2329 DAG.getConstant(1, dl, MVT::i32));
2332 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2333 FprPtr, MachinePointerInfo(SV), MVT::i8,
2334 false, false, false, 0);
2335 InChain = FprIndex.getValue(1);
2337 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2338 DAG.getConstant(8, dl, MVT::i32));
2340 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2341 DAG.getConstant(4, dl, MVT::i32));
2344 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2345 MachinePointerInfo(), false, false,
2347 InChain = OverflowArea.getValue(1);
2349 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2350 MachinePointerInfo(), false, false,
2352 InChain = RegSaveArea.getValue(1);
2354 // select overflow_area if index > 8
2355 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2356 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2358 // adjustment constant gpr_index * 4/8
2359 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2360 VT.isInteger() ? GprIndex : FprIndex,
2361 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2364 // OurReg = RegSaveArea + RegConstant
2365 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2368 // Floating types are 32 bytes into RegSaveArea
2369 if (VT.isFloatingPoint())
2370 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2371 DAG.getConstant(32, dl, MVT::i32));
2373 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2374 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2375 VT.isInteger() ? GprIndex : FprIndex,
2376 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2379 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2380 VT.isInteger() ? VAListPtr : FprPtr,
2381 MachinePointerInfo(SV),
2382 MVT::i8, false, false, 0);
2384 // determine if we should load from reg_save_area or overflow_area
2385 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2387 // increase overflow_area by 4/8 if gpr/fpr > 8
2388 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2389 DAG.getConstant(VT.isInteger() ? 4 : 8,
2392 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2395 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2397 MachinePointerInfo(),
2398 MVT::i32, false, false, 0);
2400 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2401 false, false, false, 0);
2404 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2405 const PPCSubtarget &Subtarget) const {
2406 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2408 // We have to copy the entire va_list struct:
2409 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2410 return DAG.getMemcpy(Op.getOperand(0), Op,
2411 Op.getOperand(1), Op.getOperand(2),
2412 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2413 false, MachinePointerInfo(), MachinePointerInfo());
2416 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2417 SelectionDAG &DAG) const {
2418 return Op.getOperand(0);
2421 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2422 SelectionDAG &DAG) const {
2423 SDValue Chain = Op.getOperand(0);
2424 SDValue Trmp = Op.getOperand(1); // trampoline
2425 SDValue FPtr = Op.getOperand(2); // nested function
2426 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2429 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2430 bool isPPC64 = (PtrVT == MVT::i64);
2431 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2433 TargetLowering::ArgListTy Args;
2434 TargetLowering::ArgListEntry Entry;
2436 Entry.Ty = IntPtrTy;
2437 Entry.Node = Trmp; Args.push_back(Entry);
2439 // TrampSize == (isPPC64 ? 48 : 40);
2440 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2441 isPPC64 ? MVT::i64 : MVT::i32);
2442 Args.push_back(Entry);
2444 Entry.Node = FPtr; Args.push_back(Entry);
2445 Entry.Node = Nest; Args.push_back(Entry);
2447 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2448 TargetLowering::CallLoweringInfo CLI(DAG);
2449 CLI.setDebugLoc(dl).setChain(Chain)
2450 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2451 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2452 std::move(Args), 0);
2454 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2455 return CallResult.second;
2458 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2459 const PPCSubtarget &Subtarget) const {
2460 MachineFunction &MF = DAG.getMachineFunction();
2461 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2465 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2466 // vastart just stores the address of the VarArgsFrameIndex slot into the
2467 // memory location argument.
2468 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2469 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2470 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2471 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2472 MachinePointerInfo(SV),
2476 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2477 // We suppose the given va_list is already allocated.
2480 // char gpr; /* index into the array of 8 GPRs
2481 // * stored in the register save area
2482 // * gpr=0 corresponds to r3,
2483 // * gpr=1 to r4, etc.
2485 // char fpr; /* index into the array of 8 FPRs
2486 // * stored in the register save area
2487 // * fpr=0 corresponds to f1,
2488 // * fpr=1 to f2, etc.
2490 // char *overflow_arg_area;
2491 // /* location on stack that holds
2492 // * the next overflow argument
2494 // char *reg_save_area;
2495 // /* where r3:r10 and f1:f8 (if saved)
2500 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2501 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2503 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2505 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2507 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2510 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2511 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2513 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2514 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2516 uint64_t FPROffset = 1;
2517 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2519 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2521 // Store first byte : number of int regs
2522 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2524 MachinePointerInfo(SV),
2525 MVT::i8, false, false, 0);
2526 uint64_t nextOffset = FPROffset;
2527 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2530 // Store second byte : number of float regs
2531 SDValue secondStore =
2532 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2533 MachinePointerInfo(SV, nextOffset), MVT::i8,
2535 nextOffset += StackOffset;
2536 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2538 // Store second word : arguments given on stack
2539 SDValue thirdStore =
2540 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2541 MachinePointerInfo(SV, nextOffset),
2543 nextOffset += FrameOffset;
2544 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2546 // Store third word : arguments given in registers
2547 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2548 MachinePointerInfo(SV, nextOffset),
2553 #include "PPCGenCallingConv.inc"
2555 // Function whose sole purpose is to kill compiler warnings
2556 // stemming from unused functions included from PPCGenCallingConv.inc.
2557 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2558 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2561 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2562 CCValAssign::LocInfo &LocInfo,
2563 ISD::ArgFlagsTy &ArgFlags,
2568 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2570 CCValAssign::LocInfo &LocInfo,
2571 ISD::ArgFlagsTy &ArgFlags,
2573 static const MCPhysReg ArgRegs[] = {
2574 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2575 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2577 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2579 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2581 // Skip one register if the first unallocated register has an even register
2582 // number and there are still argument registers available which have not been
2583 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2584 // need to skip a register if RegNum is odd.
2585 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2586 State.AllocateReg(ArgRegs[RegNum]);
2589 // Always return false here, as this function only makes sure that the first
2590 // unallocated register has an odd register number and does not actually
2591 // allocate a register for the current argument.
2595 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2597 CCValAssign::LocInfo &LocInfo,
2598 ISD::ArgFlagsTy &ArgFlags,
2600 static const MCPhysReg ArgRegs[] = {
2601 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2605 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2607 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2609 // If there is only one Floating-point register left we need to put both f64
2610 // values of a split ppc_fp128 value on the stack.
2611 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2612 State.AllocateReg(ArgRegs[RegNum]);
2615 // Always return false here, as this function only makes sure that the two f64
2616 // values a ppc_fp128 value is split into are both passed in registers or both
2617 // passed on the stack and does not actually allocate a register for the
2618 // current argument.
2622 /// FPR - The set of FP registers that should be allocated for arguments,
2624 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2625 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2626 PPC::F11, PPC::F12, PPC::F13};
2628 /// QFPR - The set of QPX registers that should be allocated for arguments.
2629 static const MCPhysReg QFPR[] = {
2630 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2631 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2633 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2635 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2636 unsigned PtrByteSize) {
2637 unsigned ArgSize = ArgVT.getStoreSize();
2638 if (Flags.isByVal())
2639 ArgSize = Flags.getByValSize();
2641 // Round up to multiples of the pointer size, except for array members,
2642 // which are always packed.
2643 if (!Flags.isInConsecutiveRegs())
2644 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2649 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2651 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2652 ISD::ArgFlagsTy Flags,
2653 unsigned PtrByteSize) {
2654 unsigned Align = PtrByteSize;
2656 // Altivec parameters are padded to a 16 byte boundary.
2657 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2658 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2659 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2660 ArgVT == MVT::v1i128)
2662 // QPX vector types stored in double-precision are padded to a 32 byte
2664 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2667 // ByVal parameters are aligned as requested.
2668 if (Flags.isByVal()) {
2669 unsigned BVAlign = Flags.getByValAlign();
2670 if (BVAlign > PtrByteSize) {
2671 if (BVAlign % PtrByteSize != 0)
2673 "ByVal alignment is not a multiple of the pointer size");
2679 // Array members are always packed to their original alignment.
2680 if (Flags.isInConsecutiveRegs()) {
2681 // If the array member was split into multiple registers, the first
2682 // needs to be aligned to the size of the full type. (Except for
2683 // ppcf128, which is only aligned as its f64 components.)
2684 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2685 Align = OrigVT.getStoreSize();
2687 Align = ArgVT.getStoreSize();
2693 /// CalculateStackSlotUsed - Return whether this argument will use its
2694 /// stack slot (instead of being passed in registers). ArgOffset,
2695 /// AvailableFPRs, and AvailableVRs must hold the current argument
2696 /// position, and will be updated to account for this argument.
2697 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2698 ISD::ArgFlagsTy Flags,
2699 unsigned PtrByteSize,
2700 unsigned LinkageSize,
2701 unsigned ParamAreaSize,
2702 unsigned &ArgOffset,
2703 unsigned &AvailableFPRs,
2704 unsigned &AvailableVRs, bool HasQPX) {
2705 bool UseMemory = false;
2707 // Respect alignment of argument on the stack.
2709 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2710 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2711 // If there's no space left in the argument save area, we must
2712 // use memory (this check also catches zero-sized arguments).
2713 if (ArgOffset >= LinkageSize + ParamAreaSize)
2716 // Allocate argument on the stack.
2717 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2718 if (Flags.isInConsecutiveRegsLast())
2719 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2720 // If we overran the argument save area, we must use memory
2721 // (this check catches arguments passed partially in memory)
2722 if (ArgOffset > LinkageSize + ParamAreaSize)
2725 // However, if the argument is actually passed in an FPR or a VR,
2726 // we don't use memory after all.
2727 if (!Flags.isByVal()) {
2728 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2729 // QPX registers overlap with the scalar FP registers.
2730 (HasQPX && (ArgVT == MVT::v4f32 ||
2731 ArgVT == MVT::v4f64 ||
2732 ArgVT == MVT::v4i1)))
2733 if (AvailableFPRs > 0) {
2737 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2738 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2739 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2740 ArgVT == MVT::v1i128)
2741 if (AvailableVRs > 0) {
2750 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2751 /// ensure minimum alignment required for target.
2752 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2753 unsigned NumBytes) {
2754 unsigned TargetAlign = Lowering->getStackAlignment();
2755 unsigned AlignMask = TargetAlign - 1;
2756 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2761 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2762 CallingConv::ID CallConv, bool isVarArg,
2763 const SmallVectorImpl<ISD::InputArg>
2765 SDLoc dl, SelectionDAG &DAG,
2766 SmallVectorImpl<SDValue> &InVals)
2768 if (Subtarget.isSVR4ABI()) {
2769 if (Subtarget.isPPC64())
2770 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2773 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2776 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2782 PPCTargetLowering::LowerFormalArguments_32SVR4(
2784 CallingConv::ID CallConv, bool isVarArg,
2785 const SmallVectorImpl<ISD::InputArg>
2787 SDLoc dl, SelectionDAG &DAG,
2788 SmallVectorImpl<SDValue> &InVals) const {
2790 // 32-bit SVR4 ABI Stack Frame Layout:
2791 // +-----------------------------------+
2792 // +--> | Back chain |
2793 // | +-----------------------------------+
2794 // | | Floating-point register save area |
2795 // | +-----------------------------------+
2796 // | | General register save area |
2797 // | +-----------------------------------+
2798 // | | CR save word |
2799 // | +-----------------------------------+
2800 // | | VRSAVE save word |
2801 // | +-----------------------------------+
2802 // | | Alignment padding |
2803 // | +-----------------------------------+
2804 // | | Vector register save area |
2805 // | +-----------------------------------+
2806 // | | Local variable space |
2807 // | +-----------------------------------+
2808 // | | Parameter list area |
2809 // | +-----------------------------------+
2810 // | | LR save word |
2811 // | +-----------------------------------+
2812 // SP--> +--- | Back chain |
2813 // +-----------------------------------+
2816 // System V Application Binary Interface PowerPC Processor Supplement
2817 // AltiVec Technology Programming Interface Manual
2819 MachineFunction &MF = DAG.getMachineFunction();
2820 MachineFrameInfo *MFI = MF.getFrameInfo();
2821 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2823 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2824 // Potential tail calls could cause overwriting of argument stack slots.
2825 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2826 (CallConv == CallingConv::Fast));
2827 unsigned PtrByteSize = 4;
2829 // Assign locations to all of the incoming arguments.
2830 SmallVector<CCValAssign, 16> ArgLocs;
2831 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2834 // Reserve space for the linkage area on the stack.
2835 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2836 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2838 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2841 CCValAssign &VA = ArgLocs[i];
2843 // Arguments stored in registers.
2844 if (VA.isRegLoc()) {
2845 const TargetRegisterClass *RC;
2846 EVT ValVT = VA.getValVT();
2848 switch (ValVT.getSimpleVT().SimpleTy) {
2850 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2853 RC = &PPC::GPRCRegClass;
2856 if (Subtarget.hasP8Vector())
2857 RC = &PPC::VSSRCRegClass;
2859 RC = &PPC::F4RCRegClass;
2862 if (Subtarget.hasVSX())
2863 RC = &PPC::VSFRCRegClass;
2865 RC = &PPC::F8RCRegClass;
2870 RC = &PPC::VRRCRegClass;
2873 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2877 RC = &PPC::VSHRCRegClass;
2880 RC = &PPC::QFRCRegClass;
2883 RC = &PPC::QBRCRegClass;
2887 // Transform the arguments stored in physical registers into virtual ones.
2888 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2889 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2890 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2892 if (ValVT == MVT::i1)
2893 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2895 InVals.push_back(ArgValue);
2897 // Argument stored in memory.
2898 assert(VA.isMemLoc());
2900 unsigned ArgSize = VA.getLocVT().getStoreSize();
2901 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2904 // Create load nodes to retrieve arguments from the stack.
2905 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2906 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2907 MachinePointerInfo(),
2908 false, false, false, 0));
2912 // Assign locations to all of the incoming aggregate by value arguments.
2913 // Aggregates passed by value are stored in the local variable space of the
2914 // caller's stack frame, right above the parameter list area.
2915 SmallVector<CCValAssign, 16> ByValArgLocs;
2916 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2917 ByValArgLocs, *DAG.getContext());
2919 // Reserve stack space for the allocations in CCInfo.
2920 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2922 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2924 // Area that is at least reserved in the caller of this function.
2925 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2926 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2928 // Set the size that is at least reserved in caller of this function. Tail
2929 // call optimized function's reserved stack space needs to be aligned so that
2930 // taking the difference between two stack areas will result in an aligned
2933 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2934 FuncInfo->setMinReservedArea(MinReservedArea);
2936 SmallVector<SDValue, 8> MemOps;
2938 // If the function takes variable number of arguments, make a frame index for
2939 // the start of the first vararg value... for expansion of llvm.va_start.
2941 static const MCPhysReg GPArgRegs[] = {
2942 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2943 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2945 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2947 static const MCPhysReg FPArgRegs[] = {
2948 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2951 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2952 if (DisablePPCFloatInVariadic)
2955 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2956 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2958 // Make room for NumGPArgRegs and NumFPArgRegs.
2959 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2960 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2962 FuncInfo->setVarArgsStackOffset(
2963 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2964 CCInfo.getNextStackOffset(), true));
2966 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2967 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2969 // The fixed integer arguments of a variadic function are stored to the
2970 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2971 // the result of va_next.
2972 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2973 // Get an existing live-in vreg, or add a new one.
2974 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2976 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2978 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2979 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2980 MachinePointerInfo(), false, false, 0);
2981 MemOps.push_back(Store);
2982 // Increment the address by four for the next argument to store
2983 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2984 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2987 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2989 // The double arguments are stored to the VarArgsFrameIndex
2991 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2992 // Get an existing live-in vreg, or add a new one.
2993 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2995 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2997 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2998 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2999 MachinePointerInfo(), false, false, 0);
3000 MemOps.push_back(Store);
3001 // Increment the address by eight for the next argument to store
3002 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3004 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3008 if (!MemOps.empty())
3009 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3014 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3015 // value to MVT::i64 and then truncate to the correct register size.
3017 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
3018 SelectionDAG &DAG, SDValue ArgVal,
3021 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3022 DAG.getValueType(ObjectVT));
3023 else if (Flags.isZExt())
3024 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3025 DAG.getValueType(ObjectVT));
3027 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3031 PPCTargetLowering::LowerFormalArguments_64SVR4(
3033 CallingConv::ID CallConv, bool isVarArg,
3034 const SmallVectorImpl<ISD::InputArg>
3036 SDLoc dl, SelectionDAG &DAG,
3037 SmallVectorImpl<SDValue> &InVals) const {
3038 // TODO: add description of PPC stack frame format, or at least some docs.
3040 bool isELFv2ABI = Subtarget.isELFv2ABI();
3041 bool isLittleEndian = Subtarget.isLittleEndian();
3042 MachineFunction &MF = DAG.getMachineFunction();
3043 MachineFrameInfo *MFI = MF.getFrameInfo();
3044 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3046 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3047 "fastcc not supported on varargs functions");
3049 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3050 // Potential tail calls could cause overwriting of argument stack slots.
3051 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3052 (CallConv == CallingConv::Fast));
3053 unsigned PtrByteSize = 8;
3054 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3056 static const MCPhysReg GPR[] = {
3057 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3058 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3060 static const MCPhysReg VR[] = {
3061 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3062 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3064 static const MCPhysReg VSRH[] = {
3065 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3066 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3069 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3070 const unsigned Num_FPR_Regs = 13;
3071 const unsigned Num_VR_Regs = array_lengthof(VR);
3072 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3074 // Do a first pass over the arguments to determine whether the ABI
3075 // guarantees that our caller has allocated the parameter save area
3076 // on its stack frame. In the ELFv1 ABI, this is always the case;
3077 // in the ELFv2 ABI, it is true if this is a vararg function or if
3078 // any parameter is located in a stack slot.
3080 bool HasParameterArea = !isELFv2ABI || isVarArg;
3081 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3082 unsigned NumBytes = LinkageSize;
3083 unsigned AvailableFPRs = Num_FPR_Regs;
3084 unsigned AvailableVRs = Num_VR_Regs;
3085 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3086 if (Ins[i].Flags.isNest())
3089 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3090 PtrByteSize, LinkageSize, ParamAreaSize,
3091 NumBytes, AvailableFPRs, AvailableVRs,
3092 Subtarget.hasQPX()))
3093 HasParameterArea = true;
3096 // Add DAG nodes to load the arguments or copy them out of registers. On
3097 // entry to a function on PPC, the arguments start after the linkage area,
3098 // although the first ones are often in registers.
3100 unsigned ArgOffset = LinkageSize;
3101 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3102 unsigned &QFPR_idx = FPR_idx;
3103 SmallVector<SDValue, 8> MemOps;
3104 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3105 unsigned CurArgIdx = 0;
3106 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3108 bool needsLoad = false;
3109 EVT ObjectVT = Ins[ArgNo].VT;
3110 EVT OrigVT = Ins[ArgNo].ArgVT;
3111 unsigned ObjSize = ObjectVT.getStoreSize();
3112 unsigned ArgSize = ObjSize;
3113 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3114 if (Ins[ArgNo].isOrigArg()) {
3115 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3116 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3118 // We re-align the argument offset for each argument, except when using the
3119 // fast calling convention, when we need to make sure we do that only when
3120 // we'll actually use a stack slot.
3121 unsigned CurArgOffset, Align;
3122 auto ComputeArgOffset = [&]() {
3123 /* Respect alignment of argument on the stack. */
3124 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3125 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3126 CurArgOffset = ArgOffset;
3129 if (CallConv != CallingConv::Fast) {
3132 /* Compute GPR index associated with argument offset. */
3133 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3134 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3137 // FIXME the codegen can be much improved in some cases.
3138 // We do not have to keep everything in memory.
3139 if (Flags.isByVal()) {
3140 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3142 if (CallConv == CallingConv::Fast)
3145 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3146 ObjSize = Flags.getByValSize();
3147 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3148 // Empty aggregate parameters do not take up registers. Examples:
3152 // etc. However, we have to provide a place-holder in InVals, so
3153 // pretend we have an 8-byte item at the current address for that
3156 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3157 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3158 InVals.push_back(FIN);
3162 // Create a stack object covering all stack doublewords occupied
3163 // by the argument. If the argument is (fully or partially) on
3164 // the stack, or if the argument is fully in registers but the
3165 // caller has allocated the parameter save anyway, we can refer
3166 // directly to the caller's stack frame. Otherwise, create a
3167 // local copy in our own frame.
3169 if (HasParameterArea ||
3170 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3171 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3173 FI = MFI->CreateStackObject(ArgSize, Align, false);
3174 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3176 // Handle aggregates smaller than 8 bytes.
3177 if (ObjSize < PtrByteSize) {
3178 // The value of the object is its address, which differs from the
3179 // address of the enclosing doubleword on big-endian systems.
3181 if (!isLittleEndian) {
3182 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3183 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3185 InVals.push_back(Arg);
3187 if (GPR_idx != Num_GPR_Regs) {
3188 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3189 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3192 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3193 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3194 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3195 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3196 MachinePointerInfo(&*FuncArg), ObjType,
3199 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3200 // store the whole register as-is to the parameter save area
3203 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3204 MachinePointerInfo(&*FuncArg), false, false, 0);
3207 MemOps.push_back(Store);
3209 // Whether we copied from a register or not, advance the offset
3210 // into the parameter save area by a full doubleword.
3211 ArgOffset += PtrByteSize;
3215 // The value of the object is its address, which is the address of
3216 // its first stack doubleword.
3217 InVals.push_back(FIN);
3219 // Store whatever pieces of the object are in registers to memory.
3220 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3221 if (GPR_idx == Num_GPR_Regs)
3224 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3225 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3228 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3229 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3232 DAG.getStore(Val.getValue(1), dl, Val, Addr,
3233 MachinePointerInfo(&*FuncArg, j), false, false, 0);
3234 MemOps.push_back(Store);
3237 ArgOffset += ArgSize;
3241 switch (ObjectVT.getSimpleVT().SimpleTy) {
3242 default: llvm_unreachable("Unhandled argument type!");
3246 if (Flags.isNest()) {
3247 // The 'nest' parameter, if any, is passed in R11.
3248 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3249 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3251 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3252 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3257 // These can be scalar arguments or elements of an integer array type
3258 // passed directly. Clang may use those instead of "byval" aggregate
3259 // types to avoid forcing arguments to memory unnecessarily.
3260 if (GPR_idx != Num_GPR_Regs) {
3261 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3262 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3264 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3265 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3266 // value to MVT::i64 and then truncate to the correct register size.
3267 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3269 if (CallConv == CallingConv::Fast)
3273 ArgSize = PtrByteSize;
3275 if (CallConv != CallingConv::Fast || needsLoad)
3281 // These can be scalar arguments or elements of a float array type
3282 // passed directly. The latter are used to implement ELFv2 homogenous
3283 // float aggregates.
3284 if (FPR_idx != Num_FPR_Regs) {
3287 if (ObjectVT == MVT::f32)
3288 VReg = MF.addLiveIn(FPR[FPR_idx],
3289 Subtarget.hasP8Vector()
3290 ? &PPC::VSSRCRegClass
3291 : &PPC::F4RCRegClass);
3293 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3294 ? &PPC::VSFRCRegClass
3295 : &PPC::F8RCRegClass);
3297 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3299 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3300 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3301 // once we support fp <-> gpr moves.
3303 // This can only ever happen in the presence of f32 array types,
3304 // since otherwise we never run out of FPRs before running out
3306 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3307 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3309 if (ObjectVT == MVT::f32) {
3310 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3311 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3312 DAG.getConstant(32, dl, MVT::i32));
3313 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3316 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3318 if (CallConv == CallingConv::Fast)
3324 // When passing an array of floats, the array occupies consecutive
3325 // space in the argument area; only round up to the next doubleword
3326 // at the end of the array. Otherwise, each float takes 8 bytes.
3327 if (CallConv != CallingConv::Fast || needsLoad) {
3328 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3329 ArgOffset += ArgSize;
3330 if (Flags.isInConsecutiveRegsLast())
3331 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3341 if (!Subtarget.hasQPX()) {
3342 // These can be scalar arguments or elements of a vector array type
3343 // passed directly. The latter are used to implement ELFv2 homogenous
3344 // vector aggregates.
3345 if (VR_idx != Num_VR_Regs) {
3346 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3347 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3348 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3349 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3352 if (CallConv == CallingConv::Fast)
3357 if (CallConv != CallingConv::Fast || needsLoad)
3362 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3363 "Invalid QPX parameter type");
3368 // QPX vectors are treated like their scalar floating-point subregisters
3369 // (except that they're larger).
3370 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3371 if (QFPR_idx != Num_QFPR_Regs) {
3372 const TargetRegisterClass *RC;
3373 switch (ObjectVT.getSimpleVT().SimpleTy) {
3374 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3375 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3376 default: RC = &PPC::QBRCRegClass; break;
3379 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3380 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3383 if (CallConv == CallingConv::Fast)
3387 if (CallConv != CallingConv::Fast || needsLoad)
3392 // We need to load the argument to a virtual register if we determined
3393 // above that we ran out of physical registers of the appropriate type.
3395 if (ObjSize < ArgSize && !isLittleEndian)
3396 CurArgOffset += ArgSize - ObjSize;
3397 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3398 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3399 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3400 false, false, false, 0);
3403 InVals.push_back(ArgVal);
3406 // Area that is at least reserved in the caller of this function.
3407 unsigned MinReservedArea;
3408 if (HasParameterArea)
3409 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3411 MinReservedArea = LinkageSize;
3413 // Set the size that is at least reserved in caller of this function. Tail
3414 // call optimized functions' reserved stack space needs to be aligned so that
3415 // taking the difference between two stack areas will result in an aligned
3418 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3419 FuncInfo->setMinReservedArea(MinReservedArea);
3421 // If the function takes variable number of arguments, make a frame index for
3422 // the start of the first vararg value... for expansion of llvm.va_start.
3424 int Depth = ArgOffset;
3426 FuncInfo->setVarArgsFrameIndex(
3427 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3428 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3430 // If this function is vararg, store any remaining integer argument regs
3431 // to their spots on the stack so that they may be loaded by deferencing the
3432 // result of va_next.
3433 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3434 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3435 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3436 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3437 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3438 MachinePointerInfo(), false, false, 0);
3439 MemOps.push_back(Store);
3440 // Increment the address by four for the next argument to store
3441 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3442 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3446 if (!MemOps.empty())
3447 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3453 PPCTargetLowering::LowerFormalArguments_Darwin(
3455 CallingConv::ID CallConv, bool isVarArg,
3456 const SmallVectorImpl<ISD::InputArg>
3458 SDLoc dl, SelectionDAG &DAG,
3459 SmallVectorImpl<SDValue> &InVals) const {
3460 // TODO: add description of PPC stack frame format, or at least some docs.
3462 MachineFunction &MF = DAG.getMachineFunction();
3463 MachineFrameInfo *MFI = MF.getFrameInfo();
3464 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3466 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3467 bool isPPC64 = PtrVT == MVT::i64;
3468 // Potential tail calls could cause overwriting of argument stack slots.
3469 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3470 (CallConv == CallingConv::Fast));
3471 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3472 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3473 unsigned ArgOffset = LinkageSize;
3474 // Area that is at least reserved in caller of this function.
3475 unsigned MinReservedArea = ArgOffset;
3477 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3478 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3479 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3481 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3482 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3483 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3485 static const MCPhysReg VR[] = {
3486 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3487 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3490 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3491 const unsigned Num_FPR_Regs = 13;
3492 const unsigned Num_VR_Regs = array_lengthof( VR);
3494 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3496 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3498 // In 32-bit non-varargs functions, the stack space for vectors is after the
3499 // stack space for non-vectors. We do not use this space unless we have
3500 // too many vectors to fit in registers, something that only occurs in
3501 // constructed examples:), but we have to walk the arglist to figure
3502 // that out...for the pathological case, compute VecArgOffset as the
3503 // start of the vector parameter area. Computing VecArgOffset is the
3504 // entire point of the following loop.
3505 unsigned VecArgOffset = ArgOffset;
3506 if (!isVarArg && !isPPC64) {
3507 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3509 EVT ObjectVT = Ins[ArgNo].VT;
3510 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3512 if (Flags.isByVal()) {
3513 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3514 unsigned ObjSize = Flags.getByValSize();
3516 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3517 VecArgOffset += ArgSize;
3521 switch(ObjectVT.getSimpleVT().SimpleTy) {
3522 default: llvm_unreachable("Unhandled argument type!");
3528 case MVT::i64: // PPC64
3530 // FIXME: We are guaranteed to be !isPPC64 at this point.
3531 // Does MVT::i64 apply?
3538 // Nothing to do, we're only looking at Nonvector args here.
3543 // We've found where the vector parameter area in memory is. Skip the
3544 // first 12 parameters; these don't use that memory.
3545 VecArgOffset = ((VecArgOffset+15)/16)*16;
3546 VecArgOffset += 12*16;
3548 // Add DAG nodes to load the arguments or copy them out of registers. On
3549 // entry to a function on PPC, the arguments start after the linkage area,
3550 // although the first ones are often in registers.
3552 SmallVector<SDValue, 8> MemOps;
3553 unsigned nAltivecParamsAtEnd = 0;
3554 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3555 unsigned CurArgIdx = 0;
3556 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3558 bool needsLoad = false;
3559 EVT ObjectVT = Ins[ArgNo].VT;
3560 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3561 unsigned ArgSize = ObjSize;
3562 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3563 if (Ins[ArgNo].isOrigArg()) {
3564 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3565 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3567 unsigned CurArgOffset = ArgOffset;
3569 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3570 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3571 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3572 if (isVarArg || isPPC64) {
3573 MinReservedArea = ((MinReservedArea+15)/16)*16;
3574 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3577 } else nAltivecParamsAtEnd++;
3579 // Calculate min reserved area.
3580 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3584 // FIXME the codegen can be much improved in some cases.
3585 // We do not have to keep everything in memory.
3586 if (Flags.isByVal()) {
3587 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3589 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3590 ObjSize = Flags.getByValSize();
3591 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3592 // Objects of size 1 and 2 are right justified, everything else is
3593 // left justified. This means the memory address is adjusted forwards.
3594 if (ObjSize==1 || ObjSize==2) {
3595 CurArgOffset = CurArgOffset + (4 - ObjSize);
3597 // The value of the object is its address.
3598 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3599 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3600 InVals.push_back(FIN);
3601 if (ObjSize==1 || ObjSize==2) {
3602 if (GPR_idx != Num_GPR_Regs) {
3605 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3607 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3608 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3609 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3610 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3611 MachinePointerInfo(&*FuncArg),
3612 ObjType, false, false, 0);
3613 MemOps.push_back(Store);
3617 ArgOffset += PtrByteSize;
3621 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3622 // Store whatever pieces of the object are in registers
3623 // to memory. ArgOffset will be the address of the beginning
3625 if (GPR_idx != Num_GPR_Regs) {
3628 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3630 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3631 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3632 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3633 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3635 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3636 MachinePointerInfo(&*FuncArg, j), false, false, 0);
3637 MemOps.push_back(Store);
3639 ArgOffset += PtrByteSize;
3641 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3648 switch (ObjectVT.getSimpleVT().SimpleTy) {
3649 default: llvm_unreachable("Unhandled argument type!");
3653 if (GPR_idx != Num_GPR_Regs) {
3654 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3655 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3657 if (ObjectVT == MVT::i1)
3658 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3663 ArgSize = PtrByteSize;
3665 // All int arguments reserve stack space in the Darwin ABI.
3666 ArgOffset += PtrByteSize;
3670 case MVT::i64: // PPC64
3671 if (GPR_idx != Num_GPR_Regs) {
3672 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3673 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3675 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3676 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3677 // value to MVT::i64 and then truncate to the correct register size.
3678 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3683 ArgSize = PtrByteSize;
3685 // All int arguments reserve stack space in the Darwin ABI.
3691 // Every 4 bytes of argument space consumes one of the GPRs available for
3692 // argument passing.
3693 if (GPR_idx != Num_GPR_Regs) {
3695 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3698 if (FPR_idx != Num_FPR_Regs) {
3701 if (ObjectVT == MVT::f32)
3702 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3704 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3706 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3712 // All FP arguments reserve stack space in the Darwin ABI.
3713 ArgOffset += isPPC64 ? 8 : ObjSize;
3719 // Note that vector arguments in registers don't reserve stack space,
3720 // except in varargs functions.
3721 if (VR_idx != Num_VR_Regs) {
3722 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3723 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3725 while ((ArgOffset % 16) != 0) {
3726 ArgOffset += PtrByteSize;
3727 if (GPR_idx != Num_GPR_Regs)
3731 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3735 if (!isVarArg && !isPPC64) {
3736 // Vectors go after all the nonvectors.
3737 CurArgOffset = VecArgOffset;
3740 // Vectors are aligned.
3741 ArgOffset = ((ArgOffset+15)/16)*16;
3742 CurArgOffset = ArgOffset;
3750 // We need to load the argument to a virtual register if we determined above
3751 // that we ran out of physical registers of the appropriate type.
3753 int FI = MFI->CreateFixedObject(ObjSize,
3754 CurArgOffset + (ArgSize - ObjSize),
3756 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3757 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3758 false, false, false, 0);
3761 InVals.push_back(ArgVal);
3764 // Allow for Altivec parameters at the end, if needed.
3765 if (nAltivecParamsAtEnd) {
3766 MinReservedArea = ((MinReservedArea+15)/16)*16;
3767 MinReservedArea += 16*nAltivecParamsAtEnd;
3770 // Area that is at least reserved in the caller of this function.
3771 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3773 // Set the size that is at least reserved in caller of this function. Tail
3774 // call optimized functions' reserved stack space needs to be aligned so that
3775 // taking the difference between two stack areas will result in an aligned
3778 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3779 FuncInfo->setMinReservedArea(MinReservedArea);
3781 // If the function takes variable number of arguments, make a frame index for
3782 // the start of the first vararg value... for expansion of llvm.va_start.
3784 int Depth = ArgOffset;
3786 FuncInfo->setVarArgsFrameIndex(
3787 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3789 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3791 // If this function is vararg, store any remaining integer argument regs
3792 // to their spots on the stack so that they may be loaded by deferencing the
3793 // result of va_next.
3794 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3798 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3800 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3802 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3803 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3804 MachinePointerInfo(), false, false, 0);
3805 MemOps.push_back(Store);
3806 // Increment the address by four for the next argument to store
3807 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3808 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3812 if (!MemOps.empty())
3813 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3818 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3819 /// adjusted to accommodate the arguments for the tailcall.
3820 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3821 unsigned ParamSize) {
3823 if (!isTailCall) return 0;
3825 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3826 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3827 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3828 // Remember only if the new adjustement is bigger.
3829 if (SPDiff < FI->getTailCallSPDelta())
3830 FI->setTailCallSPDelta(SPDiff);
3835 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3836 /// for tail call optimization. Targets which want to do tail call
3837 /// optimization should implement this function.
3839 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3840 CallingConv::ID CalleeCC,
3842 const SmallVectorImpl<ISD::InputArg> &Ins,
3843 SelectionDAG& DAG) const {
3844 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3847 // Variable argument functions are not supported.
3851 MachineFunction &MF = DAG.getMachineFunction();
3852 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3853 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3854 // Functions containing by val parameters are not supported.
3855 for (unsigned i = 0; i != Ins.size(); i++) {
3856 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3857 if (Flags.isByVal()) return false;
3860 // Non-PIC/GOT tail calls are supported.
3861 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3864 // At the moment we can only do local tail calls (in same module, hidden
3865 // or protected) if we are generating PIC.
3866 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3867 return G->getGlobal()->hasHiddenVisibility()
3868 || G->getGlobal()->hasProtectedVisibility();
3874 /// isCallCompatibleAddress - Return the immediate to use if the specified
3875 /// 32-bit value is representable in the immediate field of a BxA instruction.
3876 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3877 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3878 if (!C) return nullptr;
3880 int Addr = C->getZExtValue();
3881 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3882 SignExtend32<26>(Addr) != Addr)
3883 return nullptr; // Top 6 bits have to be sext of immediate.
3885 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3886 DAG.getTargetLoweringInfo().getPointerTy(
3887 DAG.getDataLayout())).getNode();
3892 struct TailCallArgumentInfo {
3897 TailCallArgumentInfo() : FrameIdx(0) {}
3901 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3903 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3905 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3906 SmallVectorImpl<SDValue> &MemOpChains,
3908 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3909 SDValue Arg = TailCallArgs[i].Arg;
3910 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3911 int FI = TailCallArgs[i].FrameIdx;
3912 // Store relative to framepointer.
3913 MemOpChains.push_back(DAG.getStore(
3914 Chain, dl, Arg, FIN,
3915 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
3920 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3921 /// the appropriate stack slot for the tail call optimized function call.
3922 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3923 MachineFunction &MF,
3932 // Calculate the new stack slot for the return address.
3933 int SlotSize = isPPC64 ? 8 : 4;
3934 const PPCFrameLowering *FL =
3935 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3936 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3937 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3938 NewRetAddrLoc, true);
3939 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3940 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3941 Chain = DAG.getStore(
3942 Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3943 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewRetAddr),
3946 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3947 // slot as the FP is never overwritten.
3949 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3950 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3952 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3953 Chain = DAG.getStore(
3954 Chain, dl, OldFP, NewFramePtrIdx,
3955 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewFPIdx),
3962 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3963 /// the position of the argument.
3965 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3966 SDValue Arg, int SPDiff, unsigned ArgOffset,
3967 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3968 int Offset = ArgOffset + SPDiff;
3969 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3970 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3971 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3972 SDValue FIN = DAG.getFrameIndex(FI, VT);
3973 TailCallArgumentInfo Info;
3975 Info.FrameIdxOp = FIN;
3977 TailCallArguments.push_back(Info);
3980 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3981 /// stack slot. Returns the chain as result and the loaded frame pointers in
3982 /// LROpOut/FPOpout. Used when tail calling.
3983 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3991 // Load the LR and FP stack slot for later adjusting.
3992 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3993 LROpOut = getReturnAddrFrameIndex(DAG);
3994 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3995 false, false, false, 0);
3996 Chain = SDValue(LROpOut.getNode(), 1);
3998 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3999 // slot as the FP is never overwritten.
4001 FPOpOut = getFramePointerFrameIndex(DAG);
4002 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
4003 false, false, false, 0);
4004 Chain = SDValue(FPOpOut.getNode(), 1);
4010 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4011 /// by "Src" to address "Dst" of size "Size". Alignment information is
4012 /// specified by the specific parameter attribute. The copy will be passed as
4013 /// a byval function parameter.
4014 /// Sometimes what we are copying is the end of a larger object, the part that
4015 /// does not fit in registers.
4017 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
4018 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
4020 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4021 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4022 false, false, false, MachinePointerInfo(),
4023 MachinePointerInfo());
4026 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4029 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
4030 SDValue Arg, SDValue PtrOff, int SPDiff,
4031 unsigned ArgOffset, bool isPPC64, bool isTailCall,
4032 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4033 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
4035 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4040 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4042 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4043 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4044 DAG.getConstant(ArgOffset, dl, PtrVT));
4046 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4047 MachinePointerInfo(), false, false, 0));
4048 // Calculate and remember argument location.
4049 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4054 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4055 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4056 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4057 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4058 MachineFunction &MF = DAG.getMachineFunction();
4060 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4061 // might overwrite each other in case of tail call optimization.
4062 SmallVector<SDValue, 8> MemOpChains2;
4063 // Do not flag preceding copytoreg stuff together with the following stuff.
4065 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4067 if (!MemOpChains2.empty())
4068 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4070 // Store the return address to the appropriate stack slot.
4071 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4072 isPPC64, isDarwinABI, dl);
4074 // Emit callseq_end just before tailcall node.
4075 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4076 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4077 InFlag = Chain.getValue(1);
4080 // Is this global address that of a function that can be called by name? (as
4081 // opposed to something that must hold a descriptor for an indirect call).
4082 static bool isFunctionGlobalAddress(SDValue Callee) {
4083 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4084 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4085 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4088 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4095 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4096 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4097 bool isTailCall, bool IsPatchPoint, bool hasNest,
4098 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4099 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4100 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4102 bool isPPC64 = Subtarget.isPPC64();
4103 bool isSVR4ABI = Subtarget.isSVR4ABI();
4104 bool isELFv2ABI = Subtarget.isELFv2ABI();
4106 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4107 NodeTys.push_back(MVT::Other); // Returns a chain
4108 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4110 unsigned CallOpc = PPCISD::CALL;
4112 bool needIndirectCall = true;
4113 if (!isSVR4ABI || !isPPC64)
4114 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4115 // If this is an absolute destination address, use the munged value.
4116 Callee = SDValue(Dest, 0);
4117 needIndirectCall = false;
4120 if (isFunctionGlobalAddress(Callee)) {
4121 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4122 // A call to a TLS address is actually an indirect call to a
4123 // thread-specific pointer.
4124 unsigned OpFlags = 0;
4125 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4126 (Subtarget.getTargetTriple().isMacOSX() &&
4127 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4128 !G->getGlobal()->isStrongDefinitionForLinker()) ||
4129 (Subtarget.isTargetELF() && !isPPC64 &&
4130 !G->getGlobal()->hasLocalLinkage() &&
4131 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4132 // PC-relative references to external symbols should go through $stub,
4133 // unless we're building with the leopard linker or later, which
4134 // automatically synthesizes these stubs.
4135 OpFlags = PPCII::MO_PLT_OR_STUB;
4138 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4139 // every direct call is) turn it into a TargetGlobalAddress /
4140 // TargetExternalSymbol node so that legalize doesn't hack it.
4141 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4142 Callee.getValueType(), 0, OpFlags);
4143 needIndirectCall = false;
4146 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4147 unsigned char OpFlags = 0;
4149 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4150 (Subtarget.getTargetTriple().isMacOSX() &&
4151 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4152 (Subtarget.isTargetELF() && !isPPC64 &&
4153 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4154 // PC-relative references to external symbols should go through $stub,
4155 // unless we're building with the leopard linker or later, which
4156 // automatically synthesizes these stubs.
4157 OpFlags = PPCII::MO_PLT_OR_STUB;
4160 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4162 needIndirectCall = false;
4166 // We'll form an invalid direct call when lowering a patchpoint; the full
4167 // sequence for an indirect call is complicated, and many of the
4168 // instructions introduced might have side effects (and, thus, can't be
4169 // removed later). The call itself will be removed as soon as the
4170 // argument/return lowering is complete, so the fact that it has the wrong
4171 // kind of operands should not really matter.
4172 needIndirectCall = false;
4175 if (needIndirectCall) {
4176 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4177 // to do the call, we can't use PPCISD::CALL.
4178 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4180 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4181 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4182 // entry point, but to the function descriptor (the function entry point
4183 // address is part of the function descriptor though).
4184 // The function descriptor is a three doubleword structure with the
4185 // following fields: function entry point, TOC base address and
4186 // environment pointer.
4187 // Thus for a call through a function pointer, the following actions need
4189 // 1. Save the TOC of the caller in the TOC save area of its stack
4190 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4191 // 2. Load the address of the function entry point from the function
4193 // 3. Load the TOC of the callee from the function descriptor into r2.
4194 // 4. Load the environment pointer from the function descriptor into
4196 // 5. Branch to the function entry point address.
4197 // 6. On return of the callee, the TOC of the caller needs to be
4198 // restored (this is done in FinishCall()).
4200 // The loads are scheduled at the beginning of the call sequence, and the
4201 // register copies are flagged together to ensure that no other
4202 // operations can be scheduled in between. E.g. without flagging the
4203 // copies together, a TOC access in the caller could be scheduled between
4204 // the assignment of the callee TOC and the branch to the callee, which
4205 // results in the TOC access going through the TOC of the callee instead
4206 // of going through the TOC of the caller, which leads to incorrect code.
4208 // Load the address of the function entry point from the function
4210 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4211 if (LDChain.getValueType() == MVT::Glue)
4212 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4214 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4216 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4217 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4218 false, false, LoadsInv, 8);
4220 // Load environment pointer into r11.
4221 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4222 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4223 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4224 MPI.getWithOffset(16), false, false,
4227 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4228 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4229 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4230 MPI.getWithOffset(8), false, false,
4233 setUsesTOCBasePtr(DAG);
4234 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4236 Chain = TOCVal.getValue(0);
4237 InFlag = TOCVal.getValue(1);
4239 // If the function call has an explicit 'nest' parameter, it takes the
4240 // place of the environment pointer.
4242 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4245 Chain = EnvVal.getValue(0);
4246 InFlag = EnvVal.getValue(1);
4249 MTCTROps[0] = Chain;
4250 MTCTROps[1] = LoadFuncPtr;
4251 MTCTROps[2] = InFlag;
4254 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4255 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4256 InFlag = Chain.getValue(1);
4259 NodeTys.push_back(MVT::Other);
4260 NodeTys.push_back(MVT::Glue);
4261 Ops.push_back(Chain);
4262 CallOpc = PPCISD::BCTRL;
4263 Callee.setNode(nullptr);
4264 // Add use of X11 (holding environment pointer)
4265 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4266 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4267 // Add CTR register as callee so a bctr can be emitted later.
4269 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4272 // If this is a direct call, pass the chain and the callee.
4273 if (Callee.getNode()) {
4274 Ops.push_back(Chain);
4275 Ops.push_back(Callee);
4277 // If this is a tail call add stack pointer delta.
4279 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4281 // Add argument registers to the end of the list so that they are known live
4283 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4284 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4285 RegsToPass[i].second.getValueType()));
4287 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4289 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4290 setUsesTOCBasePtr(DAG);
4291 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4298 bool isLocalCall(const SDValue &Callee)
4300 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4301 return G->getGlobal()->isStrongDefinitionForLinker();
4306 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4307 CallingConv::ID CallConv, bool isVarArg,
4308 const SmallVectorImpl<ISD::InputArg> &Ins,
4309 SDLoc dl, SelectionDAG &DAG,
4310 SmallVectorImpl<SDValue> &InVals) const {
4312 SmallVector<CCValAssign, 16> RVLocs;
4313 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4315 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4317 // Copy all of the result registers out of their specified physreg.
4318 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4319 CCValAssign &VA = RVLocs[i];
4320 assert(VA.isRegLoc() && "Can only return in registers!");
4322 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4323 VA.getLocReg(), VA.getLocVT(), InFlag);
4324 Chain = Val.getValue(1);
4325 InFlag = Val.getValue(2);
4327 switch (VA.getLocInfo()) {
4328 default: llvm_unreachable("Unknown loc info!");
4329 case CCValAssign::Full: break;
4330 case CCValAssign::AExt:
4331 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4333 case CCValAssign::ZExt:
4334 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4335 DAG.getValueType(VA.getValVT()));
4336 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4338 case CCValAssign::SExt:
4339 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4340 DAG.getValueType(VA.getValVT()));
4341 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4345 InVals.push_back(Val);
4352 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4353 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4354 bool hasNest, SelectionDAG &DAG,
4355 SmallVector<std::pair<unsigned, SDValue>, 8>
4357 SDValue InFlag, SDValue Chain,
4358 SDValue CallSeqStart, SDValue &Callee,
4359 int SPDiff, unsigned NumBytes,
4360 const SmallVectorImpl<ISD::InputArg> &Ins,
4361 SmallVectorImpl<SDValue> &InVals,
4362 ImmutableCallSite *CS) const {
4364 std::vector<EVT> NodeTys;
4365 SmallVector<SDValue, 8> Ops;
4366 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4367 SPDiff, isTailCall, IsPatchPoint, hasNest,
4368 RegsToPass, Ops, NodeTys, CS, Subtarget);
4370 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4371 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4372 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4374 // When performing tail call optimization the callee pops its arguments off
4375 // the stack. Account for this here so these bytes can be pushed back on in
4376 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4377 int BytesCalleePops =
4378 (CallConv == CallingConv::Fast &&
4379 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4381 // Add a register mask operand representing the call-preserved registers.
4382 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4383 const uint32_t *Mask =
4384 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4385 assert(Mask && "Missing call preserved mask for calling convention");
4386 Ops.push_back(DAG.getRegisterMask(Mask));
4388 if (InFlag.getNode())
4389 Ops.push_back(InFlag);
4393 assert(((Callee.getOpcode() == ISD::Register &&
4394 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4395 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4396 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4397 isa<ConstantSDNode>(Callee)) &&
4398 "Expecting an global address, external symbol, absolute value or register");
4400 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4401 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4404 // Add a NOP immediately after the branch instruction when using the 64-bit
4405 // SVR4 ABI. At link time, if caller and callee are in a different module and
4406 // thus have a different TOC, the call will be replaced with a call to a stub
4407 // function which saves the current TOC, loads the TOC of the callee and
4408 // branches to the callee. The NOP will be replaced with a load instruction
4409 // which restores the TOC of the caller from the TOC save slot of the current
4410 // stack frame. If caller and callee belong to the same module (and have the
4411 // same TOC), the NOP will remain unchanged.
4413 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4415 if (CallOpc == PPCISD::BCTRL) {
4416 // This is a call through a function pointer.
4417 // Restore the caller TOC from the save area into R2.
4418 // See PrepareCall() for more information about calls through function
4419 // pointers in the 64-bit SVR4 ABI.
4420 // We are using a target-specific load with r2 hard coded, because the
4421 // result of a target-independent load would never go directly into r2,
4422 // since r2 is a reserved register (which prevents the register allocator
4423 // from allocating it), resulting in an additional register being
4424 // allocated and an unnecessary move instruction being generated.
4425 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4427 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4428 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4429 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4430 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4431 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4433 // The address needs to go after the chain input but before the flag (or
4434 // any other variadic arguments).
4435 Ops.insert(std::next(Ops.begin()), AddTOC);
4436 } else if ((CallOpc == PPCISD::CALL) &&
4437 (!isLocalCall(Callee) ||
4438 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4439 // Otherwise insert NOP for non-local calls.
4440 CallOpc = PPCISD::CALL_NOP;
4443 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4444 InFlag = Chain.getValue(1);
4446 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4447 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4450 InFlag = Chain.getValue(1);
4452 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4453 Ins, dl, DAG, InVals);
4457 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4458 SmallVectorImpl<SDValue> &InVals) const {
4459 SelectionDAG &DAG = CLI.DAG;
4461 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4462 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4463 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4464 SDValue Chain = CLI.Chain;
4465 SDValue Callee = CLI.Callee;
4466 bool &isTailCall = CLI.IsTailCall;
4467 CallingConv::ID CallConv = CLI.CallConv;
4468 bool isVarArg = CLI.IsVarArg;
4469 bool IsPatchPoint = CLI.IsPatchPoint;
4470 ImmutableCallSite *CS = CLI.CS;
4473 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4476 if (!isTailCall && CS && CS->isMustTailCall())
4477 report_fatal_error("failed to perform tail call elimination on a call "
4478 "site marked musttail");
4480 if (Subtarget.isSVR4ABI()) {
4481 if (Subtarget.isPPC64())
4482 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4483 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4484 dl, DAG, InVals, CS);
4486 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4487 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4488 dl, DAG, InVals, CS);
4491 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4492 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4493 dl, DAG, InVals, CS);
4497 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4498 CallingConv::ID CallConv, bool isVarArg,
4499 bool isTailCall, bool IsPatchPoint,
4500 const SmallVectorImpl<ISD::OutputArg> &Outs,
4501 const SmallVectorImpl<SDValue> &OutVals,
4502 const SmallVectorImpl<ISD::InputArg> &Ins,
4503 SDLoc dl, SelectionDAG &DAG,
4504 SmallVectorImpl<SDValue> &InVals,
4505 ImmutableCallSite *CS) const {
4506 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4507 // of the 32-bit SVR4 ABI stack frame layout.
4509 assert((CallConv == CallingConv::C ||
4510 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4512 unsigned PtrByteSize = 4;
4514 MachineFunction &MF = DAG.getMachineFunction();
4516 // Mark this function as potentially containing a function that contains a
4517 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4518 // and restoring the callers stack pointer in this functions epilog. This is
4519 // done because by tail calling the called function might overwrite the value
4520 // in this function's (MF) stack pointer stack slot 0(SP).
4521 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4522 CallConv == CallingConv::Fast)
4523 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4525 // Count how many bytes are to be pushed on the stack, including the linkage
4526 // area, parameter list area and the part of the local variable space which
4527 // contains copies of aggregates which are passed by value.
4529 // Assign locations to all of the outgoing arguments.
4530 SmallVector<CCValAssign, 16> ArgLocs;
4531 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4534 // Reserve space for the linkage area on the stack.
4535 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4539 // Handle fixed and variable vector arguments differently.
4540 // Fixed vector arguments go into registers as long as registers are
4541 // available. Variable vector arguments always go into memory.
4542 unsigned NumArgs = Outs.size();
4544 for (unsigned i = 0; i != NumArgs; ++i) {
4545 MVT ArgVT = Outs[i].VT;
4546 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4549 if (Outs[i].IsFixed) {
4550 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4553 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4559 errs() << "Call operand #" << i << " has unhandled type "
4560 << EVT(ArgVT).getEVTString() << "\n";
4562 llvm_unreachable(nullptr);
4566 // All arguments are treated the same.
4567 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4570 // Assign locations to all of the outgoing aggregate by value arguments.
4571 SmallVector<CCValAssign, 16> ByValArgLocs;
4572 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4573 ByValArgLocs, *DAG.getContext());
4575 // Reserve stack space for the allocations in CCInfo.
4576 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4578 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4580 // Size of the linkage area, parameter list area and the part of the local
4581 // space variable where copies of aggregates which are passed by value are
4583 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4585 // Calculate by how many bytes the stack has to be adjusted in case of tail
4586 // call optimization.
4587 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4589 // Adjust the stack pointer for the new arguments...
4590 // These operations are automatically eliminated by the prolog/epilog pass
4591 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4593 SDValue CallSeqStart = Chain;
4595 // Load the return address and frame pointer so it can be moved somewhere else
4598 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4601 // Set up a copy of the stack pointer for use loading and storing any
4602 // arguments that may not fit in the registers available for argument
4604 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4606 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4607 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4608 SmallVector<SDValue, 8> MemOpChains;
4610 bool seenFloatArg = false;
4611 // Walk the register/memloc assignments, inserting copies/loads.
4612 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4615 CCValAssign &VA = ArgLocs[i];
4616 SDValue Arg = OutVals[i];
4617 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4619 if (Flags.isByVal()) {
4620 // Argument is an aggregate which is passed by value, thus we need to
4621 // create a copy of it in the local variable space of the current stack
4622 // frame (which is the stack frame of the caller) and pass the address of
4623 // this copy to the callee.
4624 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4625 CCValAssign &ByValVA = ByValArgLocs[j++];
4626 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4628 // Memory reserved in the local variable space of the callers stack frame.
4629 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4631 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4632 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4635 // Create a copy of the argument in the local area of the current
4637 SDValue MemcpyCall =
4638 CreateCopyOfByValArgument(Arg, PtrOff,
4639 CallSeqStart.getNode()->getOperand(0),
4642 // This must go outside the CALLSEQ_START..END.
4643 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4644 CallSeqStart.getNode()->getOperand(1),
4646 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4647 NewCallSeqStart.getNode());
4648 Chain = CallSeqStart = NewCallSeqStart;
4650 // Pass the address of the aggregate copy on the stack either in a
4651 // physical register or in the parameter list area of the current stack
4652 // frame to the callee.
4656 if (VA.isRegLoc()) {
4657 if (Arg.getValueType() == MVT::i1)
4658 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4660 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4661 // Put argument in a physical register.
4662 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4664 // Put argument in the parameter list area of the current stack frame.
4665 assert(VA.isMemLoc());
4666 unsigned LocMemOffset = VA.getLocMemOffset();
4669 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4670 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4673 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4674 MachinePointerInfo(),
4677 // Calculate and remember argument location.
4678 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4684 if (!MemOpChains.empty())
4685 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4687 // Build a sequence of copy-to-reg nodes chained together with token chain
4688 // and flag operands which copy the outgoing args into the appropriate regs.
4690 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4691 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4692 RegsToPass[i].second, InFlag);
4693 InFlag = Chain.getValue(1);
4696 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4699 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4700 SDValue Ops[] = { Chain, InFlag };
4702 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4703 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4705 InFlag = Chain.getValue(1);
4709 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4710 false, TailCallArguments);
4712 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
4713 /* unused except on PPC64 ELFv1 */ false, DAG,
4714 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4715 NumBytes, Ins, InVals, CS);
4718 // Copy an argument into memory, being careful to do this outside the
4719 // call sequence for the call to which the argument belongs.
4721 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4722 SDValue CallSeqStart,
4723 ISD::ArgFlagsTy Flags,
4726 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4727 CallSeqStart.getNode()->getOperand(0),
4729 // The MEMCPY must go outside the CALLSEQ_START..END.
4730 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4731 CallSeqStart.getNode()->getOperand(1),
4733 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4734 NewCallSeqStart.getNode());
4735 return NewCallSeqStart;
4739 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4740 CallingConv::ID CallConv, bool isVarArg,
4741 bool isTailCall, bool IsPatchPoint,
4742 const SmallVectorImpl<ISD::OutputArg> &Outs,
4743 const SmallVectorImpl<SDValue> &OutVals,
4744 const SmallVectorImpl<ISD::InputArg> &Ins,
4745 SDLoc dl, SelectionDAG &DAG,
4746 SmallVectorImpl<SDValue> &InVals,
4747 ImmutableCallSite *CS) const {
4749 bool isELFv2ABI = Subtarget.isELFv2ABI();
4750 bool isLittleEndian = Subtarget.isLittleEndian();
4751 unsigned NumOps = Outs.size();
4752 bool hasNest = false;
4754 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4755 unsigned PtrByteSize = 8;
4757 MachineFunction &MF = DAG.getMachineFunction();
4759 // Mark this function as potentially containing a function that contains a
4760 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4761 // and restoring the callers stack pointer in this functions epilog. This is
4762 // done because by tail calling the called function might overwrite the value
4763 // in this function's (MF) stack pointer stack slot 0(SP).
4764 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4765 CallConv == CallingConv::Fast)
4766 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4768 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4769 "fastcc not supported on varargs functions");
4771 // Count how many bytes are to be pushed on the stack, including the linkage
4772 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4773 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4774 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4775 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4776 unsigned NumBytes = LinkageSize;
4777 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4778 unsigned &QFPR_idx = FPR_idx;
4780 static const MCPhysReg GPR[] = {
4781 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4782 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4784 static const MCPhysReg VR[] = {
4785 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4786 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4788 static const MCPhysReg VSRH[] = {
4789 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4790 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4793 const unsigned NumGPRs = array_lengthof(GPR);
4794 const unsigned NumFPRs = 13;
4795 const unsigned NumVRs = array_lengthof(VR);
4796 const unsigned NumQFPRs = NumFPRs;
4798 // When using the fast calling convention, we don't provide backing for
4799 // arguments that will be in registers.
4800 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4802 // Add up all the space actually used.
4803 for (unsigned i = 0; i != NumOps; ++i) {
4804 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4805 EVT ArgVT = Outs[i].VT;
4806 EVT OrigVT = Outs[i].ArgVT;
4811 if (CallConv == CallingConv::Fast) {
4812 if (Flags.isByVal())
4813 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4815 switch (ArgVT.getSimpleVT().SimpleTy) {
4816 default: llvm_unreachable("Unexpected ValueType for argument!");
4820 if (++NumGPRsUsed <= NumGPRs)
4829 if (++NumVRsUsed <= NumVRs)
4833 // When using QPX, this is handled like a FP register, otherwise, it
4834 // is an Altivec register.
4835 if (Subtarget.hasQPX()) {
4836 if (++NumFPRsUsed <= NumFPRs)
4839 if (++NumVRsUsed <= NumVRs)
4845 case MVT::v4f64: // QPX
4846 case MVT::v4i1: // QPX
4847 if (++NumFPRsUsed <= NumFPRs)
4853 /* Respect alignment of argument on the stack. */
4855 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4856 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4858 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4859 if (Flags.isInConsecutiveRegsLast())
4860 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4863 unsigned NumBytesActuallyUsed = NumBytes;
4865 // The prolog code of the callee may store up to 8 GPR argument registers to
4866 // the stack, allowing va_start to index over them in memory if its varargs.
4867 // Because we cannot tell if this is needed on the caller side, we have to
4868 // conservatively assume that it is needed. As such, make sure we have at
4869 // least enough stack space for the caller to store the 8 GPRs.
4870 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4871 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4873 // Tail call needs the stack to be aligned.
4874 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4875 CallConv == CallingConv::Fast)
4876 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4878 // Calculate by how many bytes the stack has to be adjusted in case of tail
4879 // call optimization.
4880 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4882 // To protect arguments on the stack from being clobbered in a tail call,
4883 // force all the loads to happen before doing any other lowering.
4885 Chain = DAG.getStackArgumentTokenFactor(Chain);
4887 // Adjust the stack pointer for the new arguments...
4888 // These operations are automatically eliminated by the prolog/epilog pass
4889 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4891 SDValue CallSeqStart = Chain;
4893 // Load the return address and frame pointer so it can be move somewhere else
4896 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4899 // Set up a copy of the stack pointer for use loading and storing any
4900 // arguments that may not fit in the registers available for argument
4902 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4904 // Figure out which arguments are going to go in registers, and which in
4905 // memory. Also, if this is a vararg function, floating point operations
4906 // must be stored to our stack, and loaded into integer regs as well, if
4907 // any integer regs are available for argument passing.
4908 unsigned ArgOffset = LinkageSize;
4910 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4911 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4913 SmallVector<SDValue, 8> MemOpChains;
4914 for (unsigned i = 0; i != NumOps; ++i) {
4915 SDValue Arg = OutVals[i];
4916 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4917 EVT ArgVT = Outs[i].VT;
4918 EVT OrigVT = Outs[i].ArgVT;
4920 // PtrOff will be used to store the current argument to the stack if a
4921 // register cannot be found for it.
4924 // We re-align the argument offset for each argument, except when using the
4925 // fast calling convention, when we need to make sure we do that only when
4926 // we'll actually use a stack slot.
4927 auto ComputePtrOff = [&]() {
4928 /* Respect alignment of argument on the stack. */
4930 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4931 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4933 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4935 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4938 if (CallConv != CallingConv::Fast) {
4941 /* Compute GPR index associated with argument offset. */
4942 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4943 GPR_idx = std::min(GPR_idx, NumGPRs);
4946 // Promote integers to 64-bit values.
4947 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4948 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4949 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4950 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4953 // FIXME memcpy is used way more than necessary. Correctness first.
4954 // Note: "by value" is code for passing a structure by value, not
4956 if (Flags.isByVal()) {
4957 // Note: Size includes alignment padding, so
4958 // struct x { short a; char b; }
4959 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4960 // These are the proper values we need for right-justifying the
4961 // aggregate in a parameter register.
4962 unsigned Size = Flags.getByValSize();
4964 // An empty aggregate parameter takes up no storage and no
4969 if (CallConv == CallingConv::Fast)
4972 // All aggregates smaller than 8 bytes must be passed right-justified.
4973 if (Size==1 || Size==2 || Size==4) {
4974 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4975 if (GPR_idx != NumGPRs) {
4976 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4977 MachinePointerInfo(), VT,
4978 false, false, false, 0);
4979 MemOpChains.push_back(Load.getValue(1));
4980 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4982 ArgOffset += PtrByteSize;
4987 if (GPR_idx == NumGPRs && Size < 8) {
4988 SDValue AddPtr = PtrOff;
4989 if (!isLittleEndian) {
4990 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4991 PtrOff.getValueType());
4992 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4994 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4997 ArgOffset += PtrByteSize;
5000 // Copy entire object into memory. There are cases where gcc-generated
5001 // code assumes it is there, even if it could be put entirely into
5002 // registers. (This is not what the doc says.)
5004 // FIXME: The above statement is likely due to a misunderstanding of the
5005 // documents. All arguments must be copied into the parameter area BY
5006 // THE CALLEE in the event that the callee takes the address of any
5007 // formal argument. That has not yet been implemented. However, it is
5008 // reasonable to use the stack area as a staging area for the register
5011 // Skip this for small aggregates, as we will use the same slot for a
5012 // right-justified copy, below.
5014 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5018 // When a register is available, pass a small aggregate right-justified.
5019 if (Size < 8 && GPR_idx != NumGPRs) {
5020 // The easiest way to get this right-justified in a register
5021 // is to copy the structure into the rightmost portion of a
5022 // local variable slot, then load the whole slot into the
5024 // FIXME: The memcpy seems to produce pretty awful code for
5025 // small aggregates, particularly for packed ones.
5026 // FIXME: It would be preferable to use the slot in the
5027 // parameter save area instead of a new local variable.
5028 SDValue AddPtr = PtrOff;
5029 if (!isLittleEndian) {
5030 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5031 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5033 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5037 // Load the slot into the register.
5038 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
5039 MachinePointerInfo(),
5040 false, false, false, 0);
5041 MemOpChains.push_back(Load.getValue(1));
5042 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5044 // Done with this argument.
5045 ArgOffset += PtrByteSize;
5049 // For aggregates larger than PtrByteSize, copy the pieces of the
5050 // object that fit into registers from the parameter save area.
5051 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5052 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5053 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5054 if (GPR_idx != NumGPRs) {
5055 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5056 MachinePointerInfo(),
5057 false, false, false, 0);
5058 MemOpChains.push_back(Load.getValue(1));
5059 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5060 ArgOffset += PtrByteSize;
5062 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5069 switch (Arg.getSimpleValueType().SimpleTy) {
5070 default: llvm_unreachable("Unexpected ValueType for argument!");
5074 if (Flags.isNest()) {
5075 // The 'nest' parameter, if any, is passed in R11.
5076 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5081 // These can be scalar arguments or elements of an integer array type
5082 // passed directly. Clang may use those instead of "byval" aggregate
5083 // types to avoid forcing arguments to memory unnecessarily.
5084 if (GPR_idx != NumGPRs) {
5085 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5087 if (CallConv == CallingConv::Fast)
5090 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5091 true, isTailCall, false, MemOpChains,
5092 TailCallArguments, dl);
5093 if (CallConv == CallingConv::Fast)
5094 ArgOffset += PtrByteSize;
5096 if (CallConv != CallingConv::Fast)
5097 ArgOffset += PtrByteSize;
5101 // These can be scalar arguments or elements of a float array type
5102 // passed directly. The latter are used to implement ELFv2 homogenous
5103 // float aggregates.
5105 // Named arguments go into FPRs first, and once they overflow, the
5106 // remaining arguments go into GPRs and then the parameter save area.
5107 // Unnamed arguments for vararg functions always go to GPRs and
5108 // then the parameter save area. For now, put all arguments to vararg
5109 // routines always in both locations (FPR *and* GPR or stack slot).
5110 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5111 bool NeededLoad = false;
5113 // First load the argument into the next available FPR.
5114 if (FPR_idx != NumFPRs)
5115 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5117 // Next, load the argument into GPR or stack slot if needed.
5118 if (!NeedGPROrStack)
5120 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5121 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5122 // once we support fp <-> gpr moves.
5124 // In the non-vararg case, this can only ever happen in the
5125 // presence of f32 array types, since otherwise we never run
5126 // out of FPRs before running out of GPRs.
5129 // Double values are always passed in a single GPR.
5130 if (Arg.getValueType() != MVT::f32) {
5131 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5133 // Non-array float values are extended and passed in a GPR.
5134 } else if (!Flags.isInConsecutiveRegs()) {
5135 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5136 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5138 // If we have an array of floats, we collect every odd element
5139 // together with its predecessor into one GPR.
5140 } else if (ArgOffset % PtrByteSize != 0) {
5142 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5143 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5144 if (!isLittleEndian)
5146 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5148 // The final element, if even, goes into the first half of a GPR.
5149 } else if (Flags.isInConsecutiveRegsLast()) {
5150 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5151 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5152 if (!isLittleEndian)
5153 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5154 DAG.getConstant(32, dl, MVT::i32));
5156 // Non-final even elements are skipped; they will be handled
5157 // together the with subsequent argument on the next go-around.
5161 if (ArgVal.getNode())
5162 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5164 if (CallConv == CallingConv::Fast)
5167 // Single-precision floating-point values are mapped to the
5168 // second (rightmost) word of the stack doubleword.
5169 if (Arg.getValueType() == MVT::f32 &&
5170 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5171 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5172 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5175 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5176 true, isTailCall, false, MemOpChains,
5177 TailCallArguments, dl);
5181 // When passing an array of floats, the array occupies consecutive
5182 // space in the argument area; only round up to the next doubleword
5183 // at the end of the array. Otherwise, each float takes 8 bytes.
5184 if (CallConv != CallingConv::Fast || NeededLoad) {
5185 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5186 Flags.isInConsecutiveRegs()) ? 4 : 8;
5187 if (Flags.isInConsecutiveRegsLast())
5188 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5199 if (!Subtarget.hasQPX()) {
5200 // These can be scalar arguments or elements of a vector array type
5201 // passed directly. The latter are used to implement ELFv2 homogenous
5202 // vector aggregates.
5204 // For a varargs call, named arguments go into VRs or on the stack as
5205 // usual; unnamed arguments always go to the stack or the corresponding
5206 // GPRs when within range. For now, we always put the value in both
5207 // locations (or even all three).
5209 // We could elide this store in the case where the object fits
5210 // entirely in R registers. Maybe later.
5211 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5212 MachinePointerInfo(), false, false, 0);
5213 MemOpChains.push_back(Store);
5214 if (VR_idx != NumVRs) {
5215 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5216 MachinePointerInfo(),
5217 false, false, false, 0);
5218 MemOpChains.push_back(Load.getValue(1));
5220 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5221 Arg.getSimpleValueType() == MVT::v2i64) ?
5222 VSRH[VR_idx] : VR[VR_idx];
5225 RegsToPass.push_back(std::make_pair(VReg, Load));
5228 for (unsigned i=0; i<16; i+=PtrByteSize) {
5229 if (GPR_idx == NumGPRs)
5231 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5232 DAG.getConstant(i, dl, PtrVT));
5233 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5234 false, false, false, 0);
5235 MemOpChains.push_back(Load.getValue(1));
5236 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5241 // Non-varargs Altivec params go into VRs or on the stack.
5242 if (VR_idx != NumVRs) {
5243 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5244 Arg.getSimpleValueType() == MVT::v2i64) ?
5245 VSRH[VR_idx] : VR[VR_idx];
5248 RegsToPass.push_back(std::make_pair(VReg, Arg));
5250 if (CallConv == CallingConv::Fast)
5253 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5254 true, isTailCall, true, MemOpChains,
5255 TailCallArguments, dl);
5256 if (CallConv == CallingConv::Fast)
5260 if (CallConv != CallingConv::Fast)
5265 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5266 "Invalid QPX parameter type");
5271 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5273 // We could elide this store in the case where the object fits
5274 // entirely in R registers. Maybe later.
5275 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5276 MachinePointerInfo(), false, false, 0);
5277 MemOpChains.push_back(Store);
5278 if (QFPR_idx != NumQFPRs) {
5279 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5280 Store, PtrOff, MachinePointerInfo(),
5281 false, false, false, 0);
5282 MemOpChains.push_back(Load.getValue(1));
5283 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5285 ArgOffset += (IsF32 ? 16 : 32);
5286 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5287 if (GPR_idx == NumGPRs)
5289 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5290 DAG.getConstant(i, dl, PtrVT));
5291 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5292 false, false, false, 0);
5293 MemOpChains.push_back(Load.getValue(1));
5294 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5299 // Non-varargs QPX params go into registers or on the stack.
5300 if (QFPR_idx != NumQFPRs) {
5301 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5303 if (CallConv == CallingConv::Fast)
5306 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5307 true, isTailCall, true, MemOpChains,
5308 TailCallArguments, dl);
5309 if (CallConv == CallingConv::Fast)
5310 ArgOffset += (IsF32 ? 16 : 32);
5313 if (CallConv != CallingConv::Fast)
5314 ArgOffset += (IsF32 ? 16 : 32);
5320 assert(NumBytesActuallyUsed == ArgOffset);
5321 (void)NumBytesActuallyUsed;
5323 if (!MemOpChains.empty())
5324 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5326 // Check if this is an indirect call (MTCTR/BCTRL).
5327 // See PrepareCall() for more information about calls through function
5328 // pointers in the 64-bit SVR4 ABI.
5329 if (!isTailCall && !IsPatchPoint &&
5330 !isFunctionGlobalAddress(Callee) &&
5331 !isa<ExternalSymbolSDNode>(Callee)) {
5332 // Load r2 into a virtual register and store it to the TOC save area.
5333 setUsesTOCBasePtr(DAG);
5334 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5335 // TOC save area offset.
5336 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5337 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5338 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5339 Chain = DAG.getStore(
5340 Val.getValue(1), dl, Val, AddPtr,
5341 MachinePointerInfo::getStack(DAG.getMachineFunction(), TOCSaveOffset),
5343 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5344 // This does not mean the MTCTR instruction must use R12; it's easier
5345 // to model this as an extra parameter, so do that.
5346 if (isELFv2ABI && !IsPatchPoint)
5347 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5350 // Build a sequence of copy-to-reg nodes chained together with token chain
5351 // and flag operands which copy the outgoing args into the appropriate regs.
5353 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5354 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5355 RegsToPass[i].second, InFlag);
5356 InFlag = Chain.getValue(1);
5360 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5361 FPOp, true, TailCallArguments);
5363 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, hasNest,
5364 DAG, RegsToPass, InFlag, Chain, CallSeqStart, Callee,
5365 SPDiff, NumBytes, Ins, InVals, CS);
5369 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5370 CallingConv::ID CallConv, bool isVarArg,
5371 bool isTailCall, bool IsPatchPoint,
5372 const SmallVectorImpl<ISD::OutputArg> &Outs,
5373 const SmallVectorImpl<SDValue> &OutVals,
5374 const SmallVectorImpl<ISD::InputArg> &Ins,
5375 SDLoc dl, SelectionDAG &DAG,
5376 SmallVectorImpl<SDValue> &InVals,
5377 ImmutableCallSite *CS) const {
5379 unsigned NumOps = Outs.size();
5381 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5382 bool isPPC64 = PtrVT == MVT::i64;
5383 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5385 MachineFunction &MF = DAG.getMachineFunction();
5387 // Mark this function as potentially containing a function that contains a
5388 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5389 // and restoring the callers stack pointer in this functions epilog. This is
5390 // done because by tail calling the called function might overwrite the value
5391 // in this function's (MF) stack pointer stack slot 0(SP).
5392 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5393 CallConv == CallingConv::Fast)
5394 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5396 // Count how many bytes are to be pushed on the stack, including the linkage
5397 // area, and parameter passing area. We start with 24/48 bytes, which is
5398 // prereserved space for [SP][CR][LR][3 x unused].
5399 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5400 unsigned NumBytes = LinkageSize;
5402 // Add up all the space actually used.
5403 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5404 // they all go in registers, but we must reserve stack space for them for
5405 // possible use by the caller. In varargs or 64-bit calls, parameters are
5406 // assigned stack space in order, with padding so Altivec parameters are
5408 unsigned nAltivecParamsAtEnd = 0;
5409 for (unsigned i = 0; i != NumOps; ++i) {
5410 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5411 EVT ArgVT = Outs[i].VT;
5412 // Varargs Altivec parameters are padded to a 16 byte boundary.
5413 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5414 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5415 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5416 if (!isVarArg && !isPPC64) {
5417 // Non-varargs Altivec parameters go after all the non-Altivec
5418 // parameters; handle those later so we know how much padding we need.
5419 nAltivecParamsAtEnd++;
5422 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5423 NumBytes = ((NumBytes+15)/16)*16;
5425 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5428 // Allow for Altivec parameters at the end, if needed.
5429 if (nAltivecParamsAtEnd) {
5430 NumBytes = ((NumBytes+15)/16)*16;
5431 NumBytes += 16*nAltivecParamsAtEnd;
5434 // The prolog code of the callee may store up to 8 GPR argument registers to
5435 // the stack, allowing va_start to index over them in memory if its varargs.
5436 // Because we cannot tell if this is needed on the caller side, we have to
5437 // conservatively assume that it is needed. As such, make sure we have at
5438 // least enough stack space for the caller to store the 8 GPRs.
5439 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5441 // Tail call needs the stack to be aligned.
5442 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5443 CallConv == CallingConv::Fast)
5444 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5446 // Calculate by how many bytes the stack has to be adjusted in case of tail
5447 // call optimization.
5448 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5450 // To protect arguments on the stack from being clobbered in a tail call,
5451 // force all the loads to happen before doing any other lowering.
5453 Chain = DAG.getStackArgumentTokenFactor(Chain);
5455 // Adjust the stack pointer for the new arguments...
5456 // These operations are automatically eliminated by the prolog/epilog pass
5457 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5459 SDValue CallSeqStart = Chain;
5461 // Load the return address and frame pointer so it can be move somewhere else
5464 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5467 // Set up a copy of the stack pointer for use loading and storing any
5468 // arguments that may not fit in the registers available for argument
5472 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5474 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5476 // Figure out which arguments are going to go in registers, and which in
5477 // memory. Also, if this is a vararg function, floating point operations
5478 // must be stored to our stack, and loaded into integer regs as well, if
5479 // any integer regs are available for argument passing.
5480 unsigned ArgOffset = LinkageSize;
5481 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5483 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5484 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5485 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5487 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5488 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5489 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5491 static const MCPhysReg VR[] = {
5492 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5493 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5495 const unsigned NumGPRs = array_lengthof(GPR_32);
5496 const unsigned NumFPRs = 13;
5497 const unsigned NumVRs = array_lengthof(VR);
5499 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5501 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5502 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5504 SmallVector<SDValue, 8> MemOpChains;
5505 for (unsigned i = 0; i != NumOps; ++i) {
5506 SDValue Arg = OutVals[i];
5507 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5509 // PtrOff will be used to store the current argument to the stack if a
5510 // register cannot be found for it.
5513 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5515 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5517 // On PPC64, promote integers to 64-bit values.
5518 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5519 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5520 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5521 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5524 // FIXME memcpy is used way more than necessary. Correctness first.
5525 // Note: "by value" is code for passing a structure by value, not
5527 if (Flags.isByVal()) {
5528 unsigned Size = Flags.getByValSize();
5529 // Very small objects are passed right-justified. Everything else is
5530 // passed left-justified.
5531 if (Size==1 || Size==2) {
5532 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5533 if (GPR_idx != NumGPRs) {
5534 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5535 MachinePointerInfo(), VT,
5536 false, false, false, 0);
5537 MemOpChains.push_back(Load.getValue(1));
5538 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5540 ArgOffset += PtrByteSize;
5542 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5543 PtrOff.getValueType());
5544 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5545 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5548 ArgOffset += PtrByteSize;
5552 // Copy entire object into memory. There are cases where gcc-generated
5553 // code assumes it is there, even if it could be put entirely into
5554 // registers. (This is not what the doc says.)
5555 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5559 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5560 // copy the pieces of the object that fit into registers from the
5561 // parameter save area.
5562 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5563 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5564 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5565 if (GPR_idx != NumGPRs) {
5566 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5567 MachinePointerInfo(),
5568 false, false, false, 0);
5569 MemOpChains.push_back(Load.getValue(1));
5570 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5571 ArgOffset += PtrByteSize;
5573 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5580 switch (Arg.getSimpleValueType().SimpleTy) {
5581 default: llvm_unreachable("Unexpected ValueType for argument!");
5585 if (GPR_idx != NumGPRs) {
5586 if (Arg.getValueType() == MVT::i1)
5587 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5589 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5591 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5592 isPPC64, isTailCall, false, MemOpChains,
5593 TailCallArguments, dl);
5595 ArgOffset += PtrByteSize;
5599 if (FPR_idx != NumFPRs) {
5600 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5603 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5604 MachinePointerInfo(), false, false, 0);
5605 MemOpChains.push_back(Store);
5607 // Float varargs are always shadowed in available integer registers
5608 if (GPR_idx != NumGPRs) {
5609 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5610 MachinePointerInfo(), false, false,
5612 MemOpChains.push_back(Load.getValue(1));
5613 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5615 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5616 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5617 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5618 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5619 MachinePointerInfo(),
5620 false, false, false, 0);
5621 MemOpChains.push_back(Load.getValue(1));
5622 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5625 // If we have any FPRs remaining, we may also have GPRs remaining.
5626 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5628 if (GPR_idx != NumGPRs)
5630 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5631 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5635 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5636 isPPC64, isTailCall, false, MemOpChains,
5637 TailCallArguments, dl);
5641 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5648 // These go aligned on the stack, or in the corresponding R registers
5649 // when within range. The Darwin PPC ABI doc claims they also go in
5650 // V registers; in fact gcc does this only for arguments that are
5651 // prototyped, not for those that match the ... We do it for all
5652 // arguments, seems to work.
5653 while (ArgOffset % 16 !=0) {
5654 ArgOffset += PtrByteSize;
5655 if (GPR_idx != NumGPRs)
5658 // We could elide this store in the case where the object fits
5659 // entirely in R registers. Maybe later.
5660 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5661 DAG.getConstant(ArgOffset, dl, PtrVT));
5662 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5663 MachinePointerInfo(), false, false, 0);
5664 MemOpChains.push_back(Store);
5665 if (VR_idx != NumVRs) {
5666 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5667 MachinePointerInfo(),
5668 false, false, false, 0);
5669 MemOpChains.push_back(Load.getValue(1));
5670 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5673 for (unsigned i=0; i<16; i+=PtrByteSize) {
5674 if (GPR_idx == NumGPRs)
5676 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5677 DAG.getConstant(i, dl, PtrVT));
5678 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5679 false, false, false, 0);
5680 MemOpChains.push_back(Load.getValue(1));
5681 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5686 // Non-varargs Altivec params generally go in registers, but have
5687 // stack space allocated at the end.
5688 if (VR_idx != NumVRs) {
5689 // Doesn't have GPR space allocated.
5690 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5691 } else if (nAltivecParamsAtEnd==0) {
5692 // We are emitting Altivec params in order.
5693 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5694 isPPC64, isTailCall, true, MemOpChains,
5695 TailCallArguments, dl);
5701 // If all Altivec parameters fit in registers, as they usually do,
5702 // they get stack space following the non-Altivec parameters. We
5703 // don't track this here because nobody below needs it.
5704 // If there are more Altivec parameters than fit in registers emit
5706 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5708 // Offset is aligned; skip 1st 12 params which go in V registers.
5709 ArgOffset = ((ArgOffset+15)/16)*16;
5711 for (unsigned i = 0; i != NumOps; ++i) {
5712 SDValue Arg = OutVals[i];
5713 EVT ArgType = Outs[i].VT;
5714 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5715 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5718 // We are emitting Altivec params in order.
5719 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5720 isPPC64, isTailCall, true, MemOpChains,
5721 TailCallArguments, dl);
5728 if (!MemOpChains.empty())
5729 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5731 // On Darwin, R12 must contain the address of an indirect callee. This does
5732 // not mean the MTCTR instruction must use R12; it's easier to model this as
5733 // an extra parameter, so do that.
5735 !isFunctionGlobalAddress(Callee) &&
5736 !isa<ExternalSymbolSDNode>(Callee) &&
5737 !isBLACompatibleAddress(Callee, DAG))
5738 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5739 PPC::R12), Callee));
5741 // Build a sequence of copy-to-reg nodes chained together with token chain
5742 // and flag operands which copy the outgoing args into the appropriate regs.
5744 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5745 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5746 RegsToPass[i].second, InFlag);
5747 InFlag = Chain.getValue(1);
5751 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5752 FPOp, true, TailCallArguments);
5754 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5755 /* unused except on PPC64 ELFv1 */ false, DAG,
5756 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5757 NumBytes, Ins, InVals, CS);
5761 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5762 MachineFunction &MF, bool isVarArg,
5763 const SmallVectorImpl<ISD::OutputArg> &Outs,
5764 LLVMContext &Context) const {
5765 SmallVector<CCValAssign, 16> RVLocs;
5766 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5767 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5771 PPCTargetLowering::LowerReturn(SDValue Chain,
5772 CallingConv::ID CallConv, bool isVarArg,
5773 const SmallVectorImpl<ISD::OutputArg> &Outs,
5774 const SmallVectorImpl<SDValue> &OutVals,
5775 SDLoc dl, SelectionDAG &DAG) const {
5777 SmallVector<CCValAssign, 16> RVLocs;
5778 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5780 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5783 SmallVector<SDValue, 4> RetOps(1, Chain);
5785 // Copy the result values into the output registers.
5786 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5787 CCValAssign &VA = RVLocs[i];
5788 assert(VA.isRegLoc() && "Can only return in registers!");
5790 SDValue Arg = OutVals[i];
5792 switch (VA.getLocInfo()) {
5793 default: llvm_unreachable("Unknown loc info!");
5794 case CCValAssign::Full: break;
5795 case CCValAssign::AExt:
5796 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5798 case CCValAssign::ZExt:
5799 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5801 case CCValAssign::SExt:
5802 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5806 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5807 Flag = Chain.getValue(1);
5808 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5811 RetOps[0] = Chain; // Update chain.
5813 // Add the flag if we have it.
5815 RetOps.push_back(Flag);
5817 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5820 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5821 const PPCSubtarget &Subtarget) const {
5822 // When we pop the dynamic allocation we need to restore the SP link.
5825 // Get the corect type for pointers.
5826 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5828 // Construct the stack pointer operand.
5829 bool isPPC64 = Subtarget.isPPC64();
5830 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5831 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5833 // Get the operands for the STACKRESTORE.
5834 SDValue Chain = Op.getOperand(0);
5835 SDValue SaveSP = Op.getOperand(1);
5837 // Load the old link SP.
5838 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5839 MachinePointerInfo(),
5840 false, false, false, 0);
5842 // Restore the stack pointer.
5843 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5845 // Store the old link SP.
5846 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5850 SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG &DAG) const {
5851 MachineFunction &MF = DAG.getMachineFunction();
5852 bool isPPC64 = Subtarget.isPPC64();
5853 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5855 // Get current frame pointer save index. The users of this index will be
5856 // primarily DYNALLOC instructions.
5857 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5858 int RASI = FI->getReturnAddrSaveIndex();
5860 // If the frame pointer save index hasn't been defined yet.
5862 // Find out what the fix offset of the frame pointer save area.
5863 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5864 // Allocate the frame index for frame pointer save area.
5865 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5867 FI->setReturnAddrSaveIndex(RASI);
5869 return DAG.getFrameIndex(RASI, PtrVT);
5873 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5874 MachineFunction &MF = DAG.getMachineFunction();
5875 bool isPPC64 = Subtarget.isPPC64();
5876 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5878 // Get current frame pointer save index. The users of this index will be
5879 // primarily DYNALLOC instructions.
5880 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5881 int FPSI = FI->getFramePointerSaveIndex();
5883 // If the frame pointer save index hasn't been defined yet.
5885 // Find out what the fix offset of the frame pointer save area.
5886 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5887 // Allocate the frame index for frame pointer save area.
5888 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5890 FI->setFramePointerSaveIndex(FPSI);
5892 return DAG.getFrameIndex(FPSI, PtrVT);
5895 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5897 const PPCSubtarget &Subtarget) const {
5899 SDValue Chain = Op.getOperand(0);
5900 SDValue Size = Op.getOperand(1);
5903 // Get the corect type for pointers.
5904 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5906 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5907 DAG.getConstant(0, dl, PtrVT), Size);
5908 // Construct a node for the frame pointer save index.
5909 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5910 // Build a DYNALLOC node.
5911 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5912 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5913 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5916 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5917 SelectionDAG &DAG) const {
5919 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5920 DAG.getVTList(MVT::i32, MVT::Other),
5921 Op.getOperand(0), Op.getOperand(1));
5924 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5925 SelectionDAG &DAG) const {
5927 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5928 Op.getOperand(0), Op.getOperand(1));
5931 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5932 if (Op.getValueType().isVector())
5933 return LowerVectorLoad(Op, DAG);
5935 assert(Op.getValueType() == MVT::i1 &&
5936 "Custom lowering only for i1 loads");
5938 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5941 LoadSDNode *LD = cast<LoadSDNode>(Op);
5943 SDValue Chain = LD->getChain();
5944 SDValue BasePtr = LD->getBasePtr();
5945 MachineMemOperand *MMO = LD->getMemOperand();
5948 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
5949 BasePtr, MVT::i8, MMO);
5950 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5952 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5953 return DAG.getMergeValues(Ops, dl);
5956 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5957 if (Op.getOperand(1).getValueType().isVector())
5958 return LowerVectorStore(Op, DAG);
5960 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5961 "Custom lowering only for i1 stores");
5963 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5966 StoreSDNode *ST = cast<StoreSDNode>(Op);
5968 SDValue Chain = ST->getChain();
5969 SDValue BasePtr = ST->getBasePtr();
5970 SDValue Value = ST->getValue();
5971 MachineMemOperand *MMO = ST->getMemOperand();
5973 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
5975 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5978 // FIXME: Remove this once the ANDI glue bug is fixed:
5979 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5980 assert(Op.getValueType() == MVT::i1 &&
5981 "Custom lowering only for i1 results");
5984 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5988 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5990 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5991 // Not FP? Not a fsel.
5992 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5993 !Op.getOperand(2).getValueType().isFloatingPoint())
5996 // We might be able to do better than this under some circumstances, but in
5997 // general, fsel-based lowering of select is a finite-math-only optimization.
5998 // For more information, see section F.3 of the 2.06 ISA specification.
5999 if (!DAG.getTarget().Options.NoInfsFPMath ||
6000 !DAG.getTarget().Options.NoNaNsFPMath)
6002 // TODO: Propagate flags from the select rather than global settings.
6004 Flags.setNoInfs(true);
6005 Flags.setNoNaNs(true);
6007 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
6009 EVT ResVT = Op.getValueType();
6010 EVT CmpVT = Op.getOperand(0).getValueType();
6011 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6012 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
6015 // If the RHS of the comparison is a 0.0, we don't need to do the
6016 // subtraction at all.
6018 if (isFloatingPointZero(RHS))
6020 default: break; // SETUO etc aren't handled by fsel.
6024 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6025 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6026 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6027 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6028 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6029 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6030 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
6033 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6036 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6037 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6038 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6041 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6044 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6045 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6046 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6047 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
6052 default: break; // SETUO etc aren't handled by fsel.
6056 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6057 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6058 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6059 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6060 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6061 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6062 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6063 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6066 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6067 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6068 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6069 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6072 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6073 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6074 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6075 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6078 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6079 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6080 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6081 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6084 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6085 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6086 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6087 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6092 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6095 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6096 SDValue Src = Op.getOperand(0);
6097 if (Src.getValueType() == MVT::f32)
6098 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6101 switch (Op.getSimpleValueType().SimpleTy) {
6102 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6105 Op.getOpcode() == ISD::FP_TO_SINT
6107 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6111 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6112 "i64 FP_TO_UINT is supported only with FPCVT");
6113 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6119 // Convert the FP value to an int value through memory.
6120 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6121 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6122 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6123 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6124 MachinePointerInfo MPI =
6125 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
6127 // Emit a store to the stack slot.
6130 MachineFunction &MF = DAG.getMachineFunction();
6131 MachineMemOperand *MMO =
6132 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6133 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6134 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6135 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6137 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6138 MPI, false, false, 0);
6140 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6142 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6143 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6144 DAG.getConstant(4, dl, FIPtr.getValueType()));
6145 MPI = MPI.getWithOffset(4);
6153 /// \brief Custom lowers floating point to integer conversions to use
6154 /// the direct move instructions available in ISA 2.07 to avoid the
6155 /// need for load/store combinations.
6156 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6159 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6160 SDValue Src = Op.getOperand(0);
6162 if (Src.getValueType() == MVT::f32)
6163 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6166 switch (Op.getSimpleValueType().SimpleTy) {
6167 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6170 Op.getOpcode() == ISD::FP_TO_SINT
6172 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6174 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6177 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6178 "i64 FP_TO_UINT is supported only with FPCVT");
6179 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6182 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6188 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6190 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6191 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6194 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6196 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6197 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6201 // We're trying to insert a regular store, S, and then a load, L. If the
6202 // incoming value, O, is a load, we might just be able to have our load use the
6203 // address used by O. However, we don't know if anything else will store to
6204 // that address before we can load from it. To prevent this situation, we need
6205 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6206 // the same chain operand as O, we create a token factor from the chain results
6207 // of O and L, and we replace all uses of O's chain result with that token
6208 // factor (see spliceIntoChain below for this last part).
6209 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6212 ISD::LoadExtType ET) const {
6214 if (ET == ISD::NON_EXTLOAD &&
6215 (Op.getOpcode() == ISD::FP_TO_UINT ||
6216 Op.getOpcode() == ISD::FP_TO_SINT) &&
6217 isOperationLegalOrCustom(Op.getOpcode(),
6218 Op.getOperand(0).getValueType())) {
6220 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6224 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6225 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6226 LD->isNonTemporal())
6228 if (LD->getMemoryVT() != MemVT)
6231 RLI.Ptr = LD->getBasePtr();
6232 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6233 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6234 "Non-pre-inc AM on PPC?");
6235 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6239 RLI.Chain = LD->getChain();
6240 RLI.MPI = LD->getPointerInfo();
6241 RLI.IsInvariant = LD->isInvariant();
6242 RLI.Alignment = LD->getAlignment();
6243 RLI.AAInfo = LD->getAAInfo();
6244 RLI.Ranges = LD->getRanges();
6246 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6250 // Given the head of the old chain, ResChain, insert a token factor containing
6251 // it and NewResChain, and make users of ResChain now be users of that token
6253 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6254 SDValue NewResChain,
6255 SelectionDAG &DAG) const {
6259 SDLoc dl(NewResChain);
6261 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6262 NewResChain, DAG.getUNDEF(MVT::Other));
6263 assert(TF.getNode() != NewResChain.getNode() &&
6264 "A new TF really is required here");
6266 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6267 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6270 /// \brief Custom lowers integer to floating point conversions to use
6271 /// the direct move instructions available in ISA 2.07 to avoid the
6272 /// need for load/store combinations.
6273 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6276 assert((Op.getValueType() == MVT::f32 ||
6277 Op.getValueType() == MVT::f64) &&
6278 "Invalid floating point type as target of conversion");
6279 assert(Subtarget.hasFPCVT() &&
6280 "Int to FP conversions with direct moves require FPCVT");
6282 SDValue Src = Op.getOperand(0);
6283 bool SinglePrec = Op.getValueType() == MVT::f32;
6284 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6285 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6286 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6287 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6290 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6292 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6295 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6296 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6302 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6303 SelectionDAG &DAG) const {
6306 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6307 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6310 SDValue Value = Op.getOperand(0);
6311 // The values are now known to be -1 (false) or 1 (true). To convert this
6312 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6313 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6314 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6316 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6317 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, FPHalfs, FPHalfs,
6320 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6322 if (Op.getValueType() != MVT::v4f64)
6323 Value = DAG.getNode(ISD::FP_ROUND, dl,
6324 Op.getValueType(), Value,
6325 DAG.getIntPtrConstant(1, dl));
6329 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6330 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6333 if (Op.getOperand(0).getValueType() == MVT::i1)
6334 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6335 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6336 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6338 // If we have direct moves, we can do all the conversion, skip the store/load
6339 // however, without FPCVT we can't do most conversions.
6340 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6341 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6343 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6344 "UINT_TO_FP is supported only with FPCVT");
6346 // If we have FCFIDS, then use it when converting to single-precision.
6347 // Otherwise, convert to double-precision and then round.
6348 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6349 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6351 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6353 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6357 if (Op.getOperand(0).getValueType() == MVT::i64) {
6358 SDValue SINT = Op.getOperand(0);
6359 // When converting to single-precision, we actually need to convert
6360 // to double-precision first and then round to single-precision.
6361 // To avoid double-rounding effects during that operation, we have
6362 // to prepare the input operand. Bits that might be truncated when
6363 // converting to double-precision are replaced by a bit that won't
6364 // be lost at this stage, but is below the single-precision rounding
6367 // However, if -enable-unsafe-fp-math is in effect, accept double
6368 // rounding to avoid the extra overhead.
6369 if (Op.getValueType() == MVT::f32 &&
6370 !Subtarget.hasFPCVT() &&
6371 !DAG.getTarget().Options.UnsafeFPMath) {
6373 // Twiddle input to make sure the low 11 bits are zero. (If this
6374 // is the case, we are guaranteed the value will fit into the 53 bit
6375 // mantissa of an IEEE double-precision value without rounding.)
6376 // If any of those low 11 bits were not zero originally, make sure
6377 // bit 12 (value 2048) is set instead, so that the final rounding
6378 // to single-precision gets the correct result.
6379 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6380 SINT, DAG.getConstant(2047, dl, MVT::i64));
6381 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6382 Round, DAG.getConstant(2047, dl, MVT::i64));
6383 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6384 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6385 Round, DAG.getConstant(-2048, dl, MVT::i64));
6387 // However, we cannot use that value unconditionally: if the magnitude
6388 // of the input value is small, the bit-twiddling we did above might
6389 // end up visibly changing the output. Fortunately, in that case, we
6390 // don't need to twiddle bits since the original input will convert
6391 // exactly to double-precision floating-point already. Therefore,
6392 // construct a conditional to use the original value if the top 11
6393 // bits are all sign-bit copies, and use the rounded value computed
6395 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6396 SINT, DAG.getConstant(53, dl, MVT::i32));
6397 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6398 Cond, DAG.getConstant(1, dl, MVT::i64));
6399 Cond = DAG.getSetCC(dl, MVT::i32,
6400 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6402 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6408 MachineFunction &MF = DAG.getMachineFunction();
6409 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6410 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6411 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6413 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6414 } else if (Subtarget.hasLFIWAX() &&
6415 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6416 MachineMemOperand *MMO =
6417 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6418 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6419 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6420 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6421 DAG.getVTList(MVT::f64, MVT::Other),
6422 Ops, MVT::i32, MMO);
6423 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6424 } else if (Subtarget.hasFPCVT() &&
6425 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6426 MachineMemOperand *MMO =
6427 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6428 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6429 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6430 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6431 DAG.getVTList(MVT::f64, MVT::Other),
6432 Ops, MVT::i32, MMO);
6433 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6434 } else if (((Subtarget.hasLFIWAX() &&
6435 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6436 (Subtarget.hasFPCVT() &&
6437 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6438 SINT.getOperand(0).getValueType() == MVT::i32) {
6439 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6440 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
6442 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6443 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6445 SDValue Store = DAG.getStore(
6446 DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6447 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6450 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6451 "Expected an i32 store");
6456 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6459 MachineMemOperand *MMO =
6460 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6461 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6462 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6463 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6464 PPCISD::LFIWZX : PPCISD::LFIWAX,
6465 dl, DAG.getVTList(MVT::f64, MVT::Other),
6466 Ops, MVT::i32, MMO);
6468 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6470 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6472 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6473 FP = DAG.getNode(ISD::FP_ROUND, dl,
6474 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6478 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6479 "Unhandled INT_TO_FP type in custom expander!");
6480 // Since we only generate this in 64-bit mode, we can take advantage of
6481 // 64-bit registers. In particular, sign extend the input value into the
6482 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6483 // then lfd it and fcfid it.
6484 MachineFunction &MF = DAG.getMachineFunction();
6485 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6486 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6489 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6492 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6494 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6495 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6497 SDValue Store = DAG.getStore(
6498 DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6499 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6502 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6503 "Expected an i32 store");
6508 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6512 MachineMemOperand *MMO =
6513 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6514 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6515 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6516 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6517 PPCISD::LFIWZX : PPCISD::LFIWAX,
6518 dl, DAG.getVTList(MVT::f64, MVT::Other),
6519 Ops, MVT::i32, MMO);
6521 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6523 assert(Subtarget.isPPC64() &&
6524 "i32->FP without LFIWAX supported only on PPC64");
6526 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6527 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6529 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6532 // STD the extended value into the stack slot.
6533 SDValue Store = DAG.getStore(
6534 DAG.getEntryNode(), dl, Ext64, FIdx,
6535 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6538 // Load the value as a double.
6540 MVT::f64, dl, Store, FIdx,
6541 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6542 false, false, false, 0);
6545 // FCFID it and return it.
6546 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6547 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6548 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6549 DAG.getIntPtrConstant(0, dl));
6553 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6554 SelectionDAG &DAG) const {
6557 The rounding mode is in bits 30:31 of FPSR, and has the following
6564 FLT_ROUNDS, on the other hand, expects the following:
6571 To perform the conversion, we do:
6572 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6575 MachineFunction &MF = DAG.getMachineFunction();
6576 EVT VT = Op.getValueType();
6577 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6579 // Save FP Control Word to register
6581 MVT::f64, // return register
6582 MVT::Glue // unused in this context
6584 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6586 // Save FP register to stack slot
6587 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6588 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6589 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6590 StackSlot, MachinePointerInfo(), false, false,0);
6592 // Load FP Control Word from low 32 bits of stack slot.
6593 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6594 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6595 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6596 false, false, false, 0);
6598 // Transform as necessary
6600 DAG.getNode(ISD::AND, dl, MVT::i32,
6601 CWD, DAG.getConstant(3, dl, MVT::i32));
6603 DAG.getNode(ISD::SRL, dl, MVT::i32,
6604 DAG.getNode(ISD::AND, dl, MVT::i32,
6605 DAG.getNode(ISD::XOR, dl, MVT::i32,
6606 CWD, DAG.getConstant(3, dl, MVT::i32)),
6607 DAG.getConstant(3, dl, MVT::i32)),
6608 DAG.getConstant(1, dl, MVT::i32));
6611 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6613 return DAG.getNode((VT.getSizeInBits() < 16 ?
6614 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6617 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6618 EVT VT = Op.getValueType();
6619 unsigned BitWidth = VT.getSizeInBits();
6621 assert(Op.getNumOperands() == 3 &&
6622 VT == Op.getOperand(1).getValueType() &&
6625 // Expand into a bunch of logical ops. Note that these ops
6626 // depend on the PPC behavior for oversized shift amounts.
6627 SDValue Lo = Op.getOperand(0);
6628 SDValue Hi = Op.getOperand(1);
6629 SDValue Amt = Op.getOperand(2);
6630 EVT AmtVT = Amt.getValueType();
6632 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6633 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6634 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6635 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6636 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6637 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6638 DAG.getConstant(-BitWidth, dl, AmtVT));
6639 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6640 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6641 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6642 SDValue OutOps[] = { OutLo, OutHi };
6643 return DAG.getMergeValues(OutOps, dl);
6646 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6647 EVT VT = Op.getValueType();
6649 unsigned BitWidth = VT.getSizeInBits();
6650 assert(Op.getNumOperands() == 3 &&
6651 VT == Op.getOperand(1).getValueType() &&
6654 // Expand into a bunch of logical ops. Note that these ops
6655 // depend on the PPC behavior for oversized shift amounts.
6656 SDValue Lo = Op.getOperand(0);
6657 SDValue Hi = Op.getOperand(1);
6658 SDValue Amt = Op.getOperand(2);
6659 EVT AmtVT = Amt.getValueType();
6661 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6662 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6663 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6664 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6665 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6666 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6667 DAG.getConstant(-BitWidth, dl, AmtVT));
6668 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6669 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6670 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6671 SDValue OutOps[] = { OutLo, OutHi };
6672 return DAG.getMergeValues(OutOps, dl);
6675 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6677 EVT VT = Op.getValueType();
6678 unsigned BitWidth = VT.getSizeInBits();
6679 assert(Op.getNumOperands() == 3 &&
6680 VT == Op.getOperand(1).getValueType() &&
6683 // Expand into a bunch of logical ops, followed by a select_cc.
6684 SDValue Lo = Op.getOperand(0);
6685 SDValue Hi = Op.getOperand(1);
6686 SDValue Amt = Op.getOperand(2);
6687 EVT AmtVT = Amt.getValueType();
6689 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6690 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6691 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6692 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6693 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6694 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6695 DAG.getConstant(-BitWidth, dl, AmtVT));
6696 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6697 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6698 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6699 Tmp4, Tmp6, ISD::SETLE);
6700 SDValue OutOps[] = { OutLo, OutHi };
6701 return DAG.getMergeValues(OutOps, dl);
6704 //===----------------------------------------------------------------------===//
6705 // Vector related lowering.
6708 /// BuildSplatI - Build a canonical splati of Val with an element size of
6709 /// SplatSize. Cast the result to VT.
6710 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6711 SelectionDAG &DAG, SDLoc dl) {
6712 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6714 static const MVT VTys[] = { // canonical VT to use for each size.
6715 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6718 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6720 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6724 EVT CanonicalVT = VTys[SplatSize-1];
6726 // Build a canonical splat for this value.
6727 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6728 SmallVector<SDValue, 8> Ops;
6729 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6730 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6731 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6734 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6735 /// specified intrinsic ID.
6736 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6737 SelectionDAG &DAG, SDLoc dl,
6738 EVT DestVT = MVT::Other) {
6739 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6740 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6741 DAG.getConstant(IID, dl, MVT::i32), Op);
6744 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6745 /// specified intrinsic ID.
6746 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6747 SelectionDAG &DAG, SDLoc dl,
6748 EVT DestVT = MVT::Other) {
6749 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6750 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6751 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6754 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6755 /// specified intrinsic ID.
6756 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6757 SDValue Op2, SelectionDAG &DAG,
6758 SDLoc dl, EVT DestVT = MVT::Other) {
6759 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6760 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6761 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6764 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6765 /// amount. The result has the specified value type.
6766 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6767 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6768 // Force LHS/RHS to be the right type.
6769 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6770 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6773 for (unsigned i = 0; i != 16; ++i)
6775 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6776 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6779 // If this is a case we can't handle, return null and let the default
6780 // expansion code take care of it. If we CAN select this case, and if it
6781 // selects to a single instruction, return Op. Otherwise, if we can codegen
6782 // this case more efficiently than a constant pool load, lower it to the
6783 // sequence of ops that should be used.
6784 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6785 SelectionDAG &DAG) const {
6787 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6788 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6790 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6791 // We first build an i32 vector, load it into a QPX register,
6792 // then convert it to a floating-point vector and compare it
6793 // to a zero vector to get the boolean result.
6794 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6795 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6796 MachinePointerInfo PtrInfo =
6797 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6798 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6799 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6801 assert(BVN->getNumOperands() == 4 &&
6802 "BUILD_VECTOR for v4i1 does not have 4 operands");
6804 bool IsConst = true;
6805 for (unsigned i = 0; i < 4; ++i) {
6806 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6807 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6815 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6817 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6819 SmallVector<Constant*, 4> CV(4, NegOne);
6820 for (unsigned i = 0; i < 4; ++i) {
6821 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6822 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6823 else if (cast<ConstantSDNode>(BVN->getOperand(i))->
6824 getConstantIntValue()->isZero())
6830 Constant *CP = ConstantVector::get(CV);
6831 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
6832 16 /* alignment */);
6834 SmallVector<SDValue, 2> Ops;
6835 Ops.push_back(DAG.getEntryNode());
6836 Ops.push_back(CPIdx);
6838 SmallVector<EVT, 2> ValueVTs;
6839 ValueVTs.push_back(MVT::v4i1);
6840 ValueVTs.push_back(MVT::Other); // chain
6841 SDVTList VTs = DAG.getVTList(ValueVTs);
6843 return DAG.getMemIntrinsicNode(
6844 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
6845 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
6848 SmallVector<SDValue, 4> Stores;
6849 for (unsigned i = 0; i < 4; ++i) {
6850 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6852 unsigned Offset = 4*i;
6853 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6854 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6856 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6857 if (StoreSize > 4) {
6858 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6859 BVN->getOperand(i), Idx,
6860 PtrInfo.getWithOffset(Offset),
6861 MVT::i32, false, false, 0));
6863 SDValue StoreValue = BVN->getOperand(i);
6865 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6867 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6869 PtrInfo.getWithOffset(Offset),
6875 if (!Stores.empty())
6876 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6878 StoreChain = DAG.getEntryNode();
6880 // Now load from v4i32 into the QPX register; this will extend it to
6881 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6882 // is typed as v4f64 because the QPX register integer states are not
6883 // explicitly represented.
6885 SmallVector<SDValue, 2> Ops;
6886 Ops.push_back(StoreChain);
6887 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6888 Ops.push_back(FIdx);
6890 SmallVector<EVT, 2> ValueVTs;
6891 ValueVTs.push_back(MVT::v4f64);
6892 ValueVTs.push_back(MVT::Other); // chain
6893 SDVTList VTs = DAG.getVTList(ValueVTs);
6895 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6896 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6897 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6898 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6901 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6902 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6903 FPZeros, FPZeros, FPZeros, FPZeros);
6905 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6908 // All other QPX vectors are handled by generic code.
6909 if (Subtarget.hasQPX())
6912 // Check if this is a splat of a constant value.
6913 APInt APSplatBits, APSplatUndef;
6914 unsigned SplatBitSize;
6916 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6917 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6921 unsigned SplatBits = APSplatBits.getZExtValue();
6922 unsigned SplatUndef = APSplatUndef.getZExtValue();
6923 unsigned SplatSize = SplatBitSize / 8;
6925 // First, handle single instruction cases.
6928 if (SplatBits == 0) {
6929 // Canonicalize all zero vectors to be v4i32.
6930 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6931 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6932 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6933 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6938 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6939 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6941 if (SextVal >= -16 && SextVal <= 15)
6942 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6944 // Two instruction sequences.
6946 // If this value is in the range [-32,30] and is even, use:
6947 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6948 // If this value is in the range [17,31] and is odd, use:
6949 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6950 // If this value is in the range [-31,-17] and is odd, use:
6951 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6952 // Note the last two are three-instruction sequences.
6953 if (SextVal >= -32 && SextVal <= 31) {
6954 // To avoid having these optimizations undone by constant folding,
6955 // we convert to a pseudo that will be expanded later into one of
6957 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6958 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6959 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6960 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6961 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6962 if (VT == Op.getValueType())
6965 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6968 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6969 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6971 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6972 // Make -1 and vspltisw -1:
6973 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6975 // Make the VSLW intrinsic, computing 0x8000_0000.
6976 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6979 // xor by OnesV to invert it.
6980 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6981 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6984 // Check to see if this is a wide variety of vsplti*, binop self cases.
6985 static const signed char SplatCsts[] = {
6986 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6987 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6990 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6991 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6992 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6993 int i = SplatCsts[idx];
6995 // Figure out what shift amount will be used by altivec if shifted by i in
6997 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6999 // vsplti + shl self.
7000 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
7001 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7002 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7003 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
7004 Intrinsic::ppc_altivec_vslw
7006 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7007 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7010 // vsplti + srl self.
7011 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7012 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7013 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7014 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
7015 Intrinsic::ppc_altivec_vsrw
7017 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7018 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7021 // vsplti + sra self.
7022 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7023 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7024 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7025 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
7026 Intrinsic::ppc_altivec_vsraw
7028 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7029 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7032 // vsplti + rol self.
7033 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
7034 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
7035 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7036 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7037 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
7038 Intrinsic::ppc_altivec_vrlw
7040 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7041 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7044 // t = vsplti c, result = vsldoi t, t, 1
7045 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
7046 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7047 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1;
7048 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7050 // t = vsplti c, result = vsldoi t, t, 2
7051 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
7052 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7053 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2;
7054 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7056 // t = vsplti c, result = vsldoi t, t, 3
7057 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
7058 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7059 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3;
7060 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7067 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7068 /// the specified operations to build the shuffle.
7069 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7070 SDValue RHS, SelectionDAG &DAG,
7072 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7073 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7074 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7077 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7089 if (OpNum == OP_COPY) {
7090 if (LHSID == (1*9+2)*9+3) return LHS;
7091 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7095 SDValue OpLHS, OpRHS;
7096 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7097 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7101 default: llvm_unreachable("Unknown i32 permute!");
7103 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7104 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7105 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7106 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7109 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7110 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7111 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7112 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7115 for (unsigned i = 0; i != 16; ++i)
7116 ShufIdxs[i] = (i&3)+0;
7119 for (unsigned i = 0; i != 16; ++i)
7120 ShufIdxs[i] = (i&3)+4;
7123 for (unsigned i = 0; i != 16; ++i)
7124 ShufIdxs[i] = (i&3)+8;
7127 for (unsigned i = 0; i != 16; ++i)
7128 ShufIdxs[i] = (i&3)+12;
7131 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7133 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7135 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7137 EVT VT = OpLHS.getValueType();
7138 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7139 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7140 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7141 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7144 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7145 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7146 /// return the code it can be lowered into. Worst case, it can always be
7147 /// lowered into a vperm.
7148 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7149 SelectionDAG &DAG) const {
7151 SDValue V1 = Op.getOperand(0);
7152 SDValue V2 = Op.getOperand(1);
7153 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7154 EVT VT = Op.getValueType();
7155 bool isLittleEndian = Subtarget.isLittleEndian();
7157 if (Subtarget.hasQPX()) {
7158 if (VT.getVectorNumElements() != 4)
7161 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7163 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7164 if (AlignIdx != -1) {
7165 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7166 DAG.getConstant(AlignIdx, dl, MVT::i32));
7167 } else if (SVOp->isSplat()) {
7168 int SplatIdx = SVOp->getSplatIndex();
7169 if (SplatIdx >= 4) {
7174 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7177 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7178 DAG.getConstant(SplatIdx, dl, MVT::i32));
7181 // Lower this into a qvgpci/qvfperm pair.
7183 // Compute the qvgpci literal
7185 for (unsigned i = 0; i < 4; ++i) {
7186 int m = SVOp->getMaskElt(i);
7187 unsigned mm = m >= 0 ? (unsigned) m : i;
7188 idx |= mm << (3-i)*3;
7191 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7192 DAG.getConstant(idx, dl, MVT::i32));
7193 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7196 // Cases that are handled by instructions that take permute immediates
7197 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7198 // selected by the instruction selector.
7199 if (V2.getOpcode() == ISD::UNDEF) {
7200 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7201 PPC::isSplatShuffleMask(SVOp, 2) ||
7202 PPC::isSplatShuffleMask(SVOp, 4) ||
7203 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7204 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7205 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7206 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7207 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7208 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7209 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7210 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7211 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7212 (Subtarget.hasP8Altivec() && (
7213 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7214 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7215 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
7220 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7221 // and produce a fixed permutation. If any of these match, do not lower to
7223 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7224 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7225 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7226 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7227 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7228 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7229 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7230 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7231 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7232 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7233 (Subtarget.hasP8Altivec() && (
7234 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7235 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7236 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
7239 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7240 // perfect shuffle table to emit an optimal matching sequence.
7241 ArrayRef<int> PermMask = SVOp->getMask();
7243 unsigned PFIndexes[4];
7244 bool isFourElementShuffle = true;
7245 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7246 unsigned EltNo = 8; // Start out undef.
7247 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7248 if (PermMask[i*4+j] < 0)
7249 continue; // Undef, ignore it.
7251 unsigned ByteSource = PermMask[i*4+j];
7252 if ((ByteSource & 3) != j) {
7253 isFourElementShuffle = false;
7258 EltNo = ByteSource/4;
7259 } else if (EltNo != ByteSource/4) {
7260 isFourElementShuffle = false;
7264 PFIndexes[i] = EltNo;
7267 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7268 // perfect shuffle vector to determine if it is cost effective to do this as
7269 // discrete instructions, or whether we should use a vperm.
7270 // For now, we skip this for little endian until such time as we have a
7271 // little-endian perfect shuffle table.
7272 if (isFourElementShuffle && !isLittleEndian) {
7273 // Compute the index in the perfect shuffle table.
7274 unsigned PFTableIndex =
7275 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7277 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7278 unsigned Cost = (PFEntry >> 30);
7280 // Determining when to avoid vperm is tricky. Many things affect the cost
7281 // of vperm, particularly how many times the perm mask needs to be computed.
7282 // For example, if the perm mask can be hoisted out of a loop or is already
7283 // used (perhaps because there are multiple permutes with the same shuffle
7284 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7285 // the loop requires an extra register.
7287 // As a compromise, we only emit discrete instructions if the shuffle can be
7288 // generated in 3 or fewer operations. When we have loop information
7289 // available, if this block is within a loop, we should avoid using vperm
7290 // for 3-operation perms and use a constant pool load instead.
7292 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7295 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7296 // vector that will get spilled to the constant pool.
7297 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7299 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7300 // that it is in input element units, not in bytes. Convert now.
7302 // For little endian, the order of the input vectors is reversed, and
7303 // the permutation mask is complemented with respect to 31. This is
7304 // necessary to produce proper semantics with the big-endian-biased vperm
7306 EVT EltVT = V1.getValueType().getVectorElementType();
7307 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7309 SmallVector<SDValue, 16> ResultMask;
7310 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7311 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7313 for (unsigned j = 0; j != BytesPerElement; ++j)
7315 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7318 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7322 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7325 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7328 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7332 /// getVectorCompareInfo - Given an intrinsic, return false if it is not a
7333 /// vector comparison. If it is, return true and fill in Opc/isDot with
7334 /// information about the intrinsic.
7335 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
7336 bool &isDot, const PPCSubtarget &Subtarget) {
7337 unsigned IntrinsicID =
7338 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7341 switch (IntrinsicID) {
7342 default: return false;
7343 // Comparison predicates.
7344 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7345 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7346 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7347 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7348 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7349 case Intrinsic::ppc_altivec_vcmpequd_p:
7350 if (Subtarget.hasP8Altivec()) {
7357 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7358 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7359 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7360 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7361 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7362 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7363 if (Subtarget.hasP8Altivec()) {
7370 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7371 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7372 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7373 case Intrinsic::ppc_altivec_vcmpgtud_p:
7374 if (Subtarget.hasP8Altivec()) {
7381 // VSX predicate comparisons use the same infrastructure
7382 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
7383 case Intrinsic::ppc_vsx_xvcmpgedp_p:
7384 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
7385 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
7386 case Intrinsic::ppc_vsx_xvcmpgesp_p:
7387 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
7388 if (Subtarget.hasVSX()) {
7389 switch (IntrinsicID) {
7390 case Intrinsic::ppc_vsx_xvcmpeqdp_p: CompareOpc = 99; break;
7391 case Intrinsic::ppc_vsx_xvcmpgedp_p: CompareOpc = 115; break;
7392 case Intrinsic::ppc_vsx_xvcmpgtdp_p: CompareOpc = 107; break;
7393 case Intrinsic::ppc_vsx_xvcmpeqsp_p: CompareOpc = 67; break;
7394 case Intrinsic::ppc_vsx_xvcmpgesp_p: CompareOpc = 83; break;
7395 case Intrinsic::ppc_vsx_xvcmpgtsp_p: CompareOpc = 75; break;
7404 // Normal Comparisons.
7405 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7406 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7407 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7408 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7409 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7410 case Intrinsic::ppc_altivec_vcmpequd:
7411 if (Subtarget.hasP8Altivec()) {
7418 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7419 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7420 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7421 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7422 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7423 case Intrinsic::ppc_altivec_vcmpgtsd:
7424 if (Subtarget.hasP8Altivec()) {
7431 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7432 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7433 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7434 case Intrinsic::ppc_altivec_vcmpgtud:
7435 if (Subtarget.hasP8Altivec()) {
7446 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7447 /// lower, do it, otherwise return null.
7448 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7449 SelectionDAG &DAG) const {
7450 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7451 // opcode number of the comparison.
7455 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget))
7456 return SDValue(); // Don't custom lower most intrinsics.
7458 // If this is a non-dot comparison, make the VCMP node and we are done.
7460 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7461 Op.getOperand(1), Op.getOperand(2),
7462 DAG.getConstant(CompareOpc, dl, MVT::i32));
7463 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7466 // Create the PPCISD altivec 'dot' comparison node.
7468 Op.getOperand(2), // LHS
7469 Op.getOperand(3), // RHS
7470 DAG.getConstant(CompareOpc, dl, MVT::i32)
7472 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7473 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7475 // Now that we have the comparison, emit a copy from the CR to a GPR.
7476 // This is flagged to the above dot comparison.
7477 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7478 DAG.getRegister(PPC::CR6, MVT::i32),
7479 CompNode.getValue(1));
7481 // Unpack the result based on how the target uses it.
7482 unsigned BitNo; // Bit # of CR6.
7483 bool InvertBit; // Invert result?
7484 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7485 default: // Can't happen, don't crash on invalid number though.
7486 case 0: // Return the value of the EQ bit of CR6.
7487 BitNo = 0; InvertBit = false;
7489 case 1: // Return the inverted value of the EQ bit of CR6.
7490 BitNo = 0; InvertBit = true;
7492 case 2: // Return the value of the LT bit of CR6.
7493 BitNo = 2; InvertBit = false;
7495 case 3: // Return the inverted value of the LT bit of CR6.
7496 BitNo = 2; InvertBit = true;
7500 // Shift the bit into the low position.
7501 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7502 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7504 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7505 DAG.getConstant(1, dl, MVT::i32));
7507 // If we are supposed to, toggle the bit.
7509 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7510 DAG.getConstant(1, dl, MVT::i32));
7514 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7515 SelectionDAG &DAG) const {
7517 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7518 // instructions), but for smaller types, we need to first extend up to v2i32
7519 // before doing going farther.
7520 if (Op.getValueType() == MVT::v2i64) {
7521 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7522 if (ExtVT != MVT::v2i32) {
7523 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7524 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7525 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7526 ExtVT.getVectorElementType(), 4)));
7527 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7528 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7529 DAG.getValueType(MVT::v2i32));
7538 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7539 SelectionDAG &DAG) const {
7541 // Create a stack slot that is 16-byte aligned.
7542 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7543 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7544 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7545 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7547 // Store the input value into Value#0 of the stack slot.
7548 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7549 Op.getOperand(0), FIdx, MachinePointerInfo(),
7552 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7553 false, false, false, 0);
7556 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7557 SelectionDAG &DAG) const {
7559 SDNode *N = Op.getNode();
7561 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7562 "Unknown extract_vector_elt type");
7564 SDValue Value = N->getOperand(0);
7566 // The first part of this is like the store lowering except that we don't
7567 // need to track the chain.
7569 // The values are now known to be -1 (false) or 1 (true). To convert this
7570 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7571 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7572 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7574 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7575 // understand how to form the extending load.
7576 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7577 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7578 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7580 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7582 // Now convert to an integer and store.
7583 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7584 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7587 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7588 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7589 MachinePointerInfo PtrInfo =
7590 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7591 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7592 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7594 SDValue StoreChain = DAG.getEntryNode();
7595 SmallVector<SDValue, 2> Ops;
7596 Ops.push_back(StoreChain);
7597 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7598 Ops.push_back(Value);
7599 Ops.push_back(FIdx);
7601 SmallVector<EVT, 2> ValueVTs;
7602 ValueVTs.push_back(MVT::Other); // chain
7603 SDVTList VTs = DAG.getVTList(ValueVTs);
7605 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7606 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7608 // Extract the value requested.
7609 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7610 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7611 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7613 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7614 PtrInfo.getWithOffset(Offset),
7615 false, false, false, 0);
7617 if (!Subtarget.useCRBits())
7620 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7623 /// Lowering for QPX v4i1 loads
7624 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7625 SelectionDAG &DAG) const {
7627 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7628 SDValue LoadChain = LN->getChain();
7629 SDValue BasePtr = LN->getBasePtr();
7631 if (Op.getValueType() == MVT::v4f64 ||
7632 Op.getValueType() == MVT::v4f32) {
7633 EVT MemVT = LN->getMemoryVT();
7634 unsigned Alignment = LN->getAlignment();
7636 // If this load is properly aligned, then it is legal.
7637 if (Alignment >= MemVT.getStoreSize())
7640 EVT ScalarVT = Op.getValueType().getScalarType(),
7641 ScalarMemVT = MemVT.getScalarType();
7642 unsigned Stride = ScalarMemVT.getStoreSize();
7644 SmallVector<SDValue, 8> Vals, LoadChains;
7645 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7647 if (ScalarVT != ScalarMemVT)
7649 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7651 LN->getPointerInfo().getWithOffset(Idx*Stride),
7652 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7653 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7657 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7658 LN->getPointerInfo().getWithOffset(Idx*Stride),
7659 LN->isVolatile(), LN->isNonTemporal(),
7660 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7663 if (Idx == 0 && LN->isIndexed()) {
7664 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7665 "Unknown addressing mode on vector load");
7666 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7667 LN->getAddressingMode());
7670 Vals.push_back(Load);
7671 LoadChains.push_back(Load.getValue(1));
7673 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7674 DAG.getConstant(Stride, dl,
7675 BasePtr.getValueType()));
7678 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7679 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7680 Op.getValueType(), Vals);
7682 if (LN->isIndexed()) {
7683 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7684 return DAG.getMergeValues(RetOps, dl);
7687 SDValue RetOps[] = { Value, TF };
7688 return DAG.getMergeValues(RetOps, dl);
7691 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7692 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7694 // To lower v4i1 from a byte array, we load the byte elements of the
7695 // vector and then reuse the BUILD_VECTOR logic.
7697 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7698 for (unsigned i = 0; i < 4; ++i) {
7699 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7700 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7702 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7703 dl, MVT::i32, LoadChain, Idx,
7704 LN->getPointerInfo().getWithOffset(i),
7705 MVT::i8 /* memory type */,
7706 LN->isVolatile(), LN->isNonTemporal(),
7708 1 /* alignment */, LN->getAAInfo()));
7709 VectElmtChains.push_back(VectElmts[i].getValue(1));
7712 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7713 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7715 SDValue RVals[] = { Value, LoadChain };
7716 return DAG.getMergeValues(RVals, dl);
7719 /// Lowering for QPX v4i1 stores
7720 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7721 SelectionDAG &DAG) const {
7723 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7724 SDValue StoreChain = SN->getChain();
7725 SDValue BasePtr = SN->getBasePtr();
7726 SDValue Value = SN->getValue();
7728 if (Value.getValueType() == MVT::v4f64 ||
7729 Value.getValueType() == MVT::v4f32) {
7730 EVT MemVT = SN->getMemoryVT();
7731 unsigned Alignment = SN->getAlignment();
7733 // If this store is properly aligned, then it is legal.
7734 if (Alignment >= MemVT.getStoreSize())
7737 EVT ScalarVT = Value.getValueType().getScalarType(),
7738 ScalarMemVT = MemVT.getScalarType();
7739 unsigned Stride = ScalarMemVT.getStoreSize();
7741 SmallVector<SDValue, 8> Stores;
7742 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7743 SDValue Ex = DAG.getNode(
7744 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7745 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
7747 if (ScalarVT != ScalarMemVT)
7749 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7750 SN->getPointerInfo().getWithOffset(Idx*Stride),
7751 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7752 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7755 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7756 SN->getPointerInfo().getWithOffset(Idx*Stride),
7757 SN->isVolatile(), SN->isNonTemporal(),
7758 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7760 if (Idx == 0 && SN->isIndexed()) {
7761 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7762 "Unknown addressing mode on vector store");
7763 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7764 SN->getAddressingMode());
7767 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7768 DAG.getConstant(Stride, dl,
7769 BasePtr.getValueType()));
7770 Stores.push_back(Store);
7773 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7775 if (SN->isIndexed()) {
7776 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7777 return DAG.getMergeValues(RetOps, dl);
7783 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7784 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7786 // The values are now known to be -1 (false) or 1 (true). To convert this
7787 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7788 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7789 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7791 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7792 // understand how to form the extending load.
7793 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7794 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7795 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7797 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7799 // Now convert to an integer and store.
7800 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7801 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7804 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7805 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7806 MachinePointerInfo PtrInfo =
7807 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7808 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7809 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7811 SmallVector<SDValue, 2> Ops;
7812 Ops.push_back(StoreChain);
7813 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7814 Ops.push_back(Value);
7815 Ops.push_back(FIdx);
7817 SmallVector<EVT, 2> ValueVTs;
7818 ValueVTs.push_back(MVT::Other); // chain
7819 SDVTList VTs = DAG.getVTList(ValueVTs);
7821 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7822 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7824 // Move data into the byte array.
7825 SmallVector<SDValue, 4> Loads, LoadChains;
7826 for (unsigned i = 0; i < 4; ++i) {
7827 unsigned Offset = 4*i;
7828 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7829 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7831 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7832 PtrInfo.getWithOffset(Offset),
7833 false, false, false, 0));
7834 LoadChains.push_back(Loads[i].getValue(1));
7837 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7839 SmallVector<SDValue, 4> Stores;
7840 for (unsigned i = 0; i < 4; ++i) {
7841 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7842 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7844 Stores.push_back(DAG.getTruncStore(
7845 StoreChain, dl, Loads[i], Idx, SN->getPointerInfo().getWithOffset(i),
7846 MVT::i8 /* memory type */, SN->isNonTemporal(), SN->isVolatile(),
7847 1 /* alignment */, SN->getAAInfo()));
7850 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7855 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7857 if (Op.getValueType() == MVT::v4i32) {
7858 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7860 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7861 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7863 SDValue RHSSwap = // = vrlw RHS, 16
7864 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7866 // Shrinkify inputs to v8i16.
7867 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7868 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7869 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7871 // Low parts multiplied together, generating 32-bit results (we ignore the
7873 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7874 LHS, RHS, DAG, dl, MVT::v4i32);
7876 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7877 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7878 // Shift the high parts up 16 bits.
7879 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7881 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7882 } else if (Op.getValueType() == MVT::v8i16) {
7883 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7885 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7887 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7888 LHS, RHS, Zero, DAG, dl);
7889 } else if (Op.getValueType() == MVT::v16i8) {
7890 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7891 bool isLittleEndian = Subtarget.isLittleEndian();
7893 // Multiply the even 8-bit parts, producing 16-bit sums.
7894 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7895 LHS, RHS, DAG, dl, MVT::v8i16);
7896 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7898 // Multiply the odd 8-bit parts, producing 16-bit sums.
7899 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7900 LHS, RHS, DAG, dl, MVT::v8i16);
7901 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7903 // Merge the results together. Because vmuleub and vmuloub are
7904 // instructions with a big-endian bias, we must reverse the
7905 // element numbering and reverse the meaning of "odd" and "even"
7906 // when generating little endian code.
7908 for (unsigned i = 0; i != 8; ++i) {
7909 if (isLittleEndian) {
7911 Ops[i*2+1] = 2*i+16;
7914 Ops[i*2+1] = 2*i+1+16;
7918 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7920 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7922 llvm_unreachable("Unknown mul to lower!");
7926 /// LowerOperation - Provide custom lowering hooks for some operations.
7928 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7929 switch (Op.getOpcode()) {
7930 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7931 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7932 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7933 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7934 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7935 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7936 case ISD::SETCC: return LowerSETCC(Op, DAG);
7937 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7938 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7940 return LowerVASTART(Op, DAG, Subtarget);
7943 return LowerVAARG(Op, DAG, Subtarget);
7946 return LowerVACOPY(Op, DAG, Subtarget);
7948 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7949 case ISD::DYNAMIC_STACKALLOC:
7950 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7952 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7953 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7955 case ISD::LOAD: return LowerLOAD(Op, DAG);
7956 case ISD::STORE: return LowerSTORE(Op, DAG);
7957 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7958 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7959 case ISD::FP_TO_UINT:
7960 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7962 case ISD::UINT_TO_FP:
7963 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7964 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7966 // Lower 64-bit shifts.
7967 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7968 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7969 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7971 // Vector-related lowering.
7972 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7973 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7974 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7975 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7976 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7977 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7978 case ISD::MUL: return LowerMUL(Op, DAG);
7980 // For counter-based loop handling.
7981 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7983 // Frame & Return address.
7984 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7985 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7989 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7990 SmallVectorImpl<SDValue>&Results,
7991 SelectionDAG &DAG) const {
7993 switch (N->getOpcode()) {
7995 llvm_unreachable("Do not know how to custom type legalize this operation!");
7996 case ISD::READCYCLECOUNTER: {
7997 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7998 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
8000 Results.push_back(RTB);
8001 Results.push_back(RTB.getValue(1));
8002 Results.push_back(RTB.getValue(2));
8005 case ISD::INTRINSIC_W_CHAIN: {
8006 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
8007 Intrinsic::ppc_is_decremented_ctr_nonzero)
8010 assert(N->getValueType(0) == MVT::i1 &&
8011 "Unexpected result type for CTR decrement intrinsic");
8012 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
8013 N->getValueType(0));
8014 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
8015 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
8018 Results.push_back(NewInt);
8019 Results.push_back(NewInt.getValue(1));
8023 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
8026 EVT VT = N->getValueType(0);
8028 if (VT == MVT::i64) {
8029 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
8031 Results.push_back(NewNode);
8032 Results.push_back(NewNode.getValue(1));
8036 case ISD::FP_ROUND_INREG: {
8037 assert(N->getValueType(0) == MVT::ppcf128);
8038 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
8039 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8040 MVT::f64, N->getOperand(0),
8041 DAG.getIntPtrConstant(0, dl));
8042 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8043 MVT::f64, N->getOperand(0),
8044 DAG.getIntPtrConstant(1, dl));
8046 // Add the two halves of the long double in round-to-zero mode.
8047 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
8049 // We know the low half is about to be thrown away, so just use something
8051 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
8055 case ISD::FP_TO_SINT:
8056 case ISD::FP_TO_UINT:
8057 // LowerFP_TO_INT() can only handle f32 and f64.
8058 if (N->getOperand(0).getValueType() == MVT::ppcf128)
8060 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
8065 //===----------------------------------------------------------------------===//
8066 // Other Lowering Code
8067 //===----------------------------------------------------------------------===//
8069 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
8070 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8071 Function *Func = Intrinsic::getDeclaration(M, Id);
8072 return Builder.CreateCall(Func, {});
8075 // The mappings for emitLeading/TrailingFence is taken from
8076 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
8077 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
8078 AtomicOrdering Ord, bool IsStore,
8079 bool IsLoad) const {
8080 if (Ord == SequentiallyConsistent)
8081 return callIntrinsic(Builder, Intrinsic::ppc_sync);
8082 if (isAtLeastRelease(Ord))
8083 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8087 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
8088 AtomicOrdering Ord, bool IsStore,
8089 bool IsLoad) const {
8090 if (IsLoad && isAtLeastAcquire(Ord))
8091 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8092 // FIXME: this is too conservative, a dependent branch + isync is enough.
8093 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8094 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8095 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8100 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8101 unsigned AtomicSize,
8102 unsigned BinOpcode) const {
8103 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8104 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8106 auto LoadMnemonic = PPC::LDARX;
8107 auto StoreMnemonic = PPC::STDCX;
8108 switch (AtomicSize) {
8110 llvm_unreachable("Unexpected size of atomic entity");
8112 LoadMnemonic = PPC::LBARX;
8113 StoreMnemonic = PPC::STBCX;
8114 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8117 LoadMnemonic = PPC::LHARX;
8118 StoreMnemonic = PPC::STHCX;
8119 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8122 LoadMnemonic = PPC::LWARX;
8123 StoreMnemonic = PPC::STWCX;
8126 LoadMnemonic = PPC::LDARX;
8127 StoreMnemonic = PPC::STDCX;
8131 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8132 MachineFunction *F = BB->getParent();
8133 MachineFunction::iterator It = ++BB->getIterator();
8135 unsigned dest = MI->getOperand(0).getReg();
8136 unsigned ptrA = MI->getOperand(1).getReg();
8137 unsigned ptrB = MI->getOperand(2).getReg();
8138 unsigned incr = MI->getOperand(3).getReg();
8139 DebugLoc dl = MI->getDebugLoc();
8141 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8142 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8143 F->insert(It, loopMBB);
8144 F->insert(It, exitMBB);
8145 exitMBB->splice(exitMBB->begin(), BB,
8146 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8147 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8149 MachineRegisterInfo &RegInfo = F->getRegInfo();
8150 unsigned TmpReg = (!BinOpcode) ? incr :
8151 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8152 : &PPC::GPRCRegClass);
8156 // fallthrough --> loopMBB
8157 BB->addSuccessor(loopMBB);
8160 // l[wd]arx dest, ptr
8161 // add r0, dest, incr
8162 // st[wd]cx. r0, ptr
8164 // fallthrough --> exitMBB
8166 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8167 .addReg(ptrA).addReg(ptrB);
8169 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8170 BuildMI(BB, dl, TII->get(StoreMnemonic))
8171 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8172 BuildMI(BB, dl, TII->get(PPC::BCC))
8173 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8174 BB->addSuccessor(loopMBB);
8175 BB->addSuccessor(exitMBB);
8184 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8185 MachineBasicBlock *BB,
8186 bool is8bit, // operation
8187 unsigned BinOpcode) const {
8188 // If we support part-word atomic mnemonics, just use them
8189 if (Subtarget.hasPartwordAtomics())
8190 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8192 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8193 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8194 // In 64 bit mode we have to use 64 bits for addresses, even though the
8195 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8196 // registers without caring whether they're 32 or 64, but here we're
8197 // doing actual arithmetic on the addresses.
8198 bool is64bit = Subtarget.isPPC64();
8199 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8201 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8202 MachineFunction *F = BB->getParent();
8203 MachineFunction::iterator It = ++BB->getIterator();
8205 unsigned dest = MI->getOperand(0).getReg();
8206 unsigned ptrA = MI->getOperand(1).getReg();
8207 unsigned ptrB = MI->getOperand(2).getReg();
8208 unsigned incr = MI->getOperand(3).getReg();
8209 DebugLoc dl = MI->getDebugLoc();
8211 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8212 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8213 F->insert(It, loopMBB);
8214 F->insert(It, exitMBB);
8215 exitMBB->splice(exitMBB->begin(), BB,
8216 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8217 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8219 MachineRegisterInfo &RegInfo = F->getRegInfo();
8220 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8221 : &PPC::GPRCRegClass;
8222 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8223 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8224 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8225 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8226 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8227 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8228 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8229 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8230 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8231 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8232 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8234 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8238 // fallthrough --> loopMBB
8239 BB->addSuccessor(loopMBB);
8241 // The 4-byte load must be aligned, while a char or short may be
8242 // anywhere in the word. Hence all this nasty bookkeeping code.
8243 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8244 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8245 // xori shift, shift1, 24 [16]
8246 // rlwinm ptr, ptr1, 0, 0, 29
8247 // slw incr2, incr, shift
8248 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8249 // slw mask, mask2, shift
8251 // lwarx tmpDest, ptr
8252 // add tmp, tmpDest, incr2
8253 // andc tmp2, tmpDest, mask
8254 // and tmp3, tmp, mask
8255 // or tmp4, tmp3, tmp2
8258 // fallthrough --> exitMBB
8259 // srw dest, tmpDest, shift
8260 if (ptrA != ZeroReg) {
8261 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8262 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8263 .addReg(ptrA).addReg(ptrB);
8267 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8268 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8269 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8270 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8272 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8273 .addReg(Ptr1Reg).addImm(0).addImm(61);
8275 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8276 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8277 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8278 .addReg(incr).addReg(ShiftReg);
8280 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8282 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8283 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8285 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8286 .addReg(Mask2Reg).addReg(ShiftReg);
8289 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8290 .addReg(ZeroReg).addReg(PtrReg);
8292 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8293 .addReg(Incr2Reg).addReg(TmpDestReg);
8294 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8295 .addReg(TmpDestReg).addReg(MaskReg);
8296 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8297 .addReg(TmpReg).addReg(MaskReg);
8298 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8299 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8300 BuildMI(BB, dl, TII->get(PPC::STWCX))
8301 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8302 BuildMI(BB, dl, TII->get(PPC::BCC))
8303 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8304 BB->addSuccessor(loopMBB);
8305 BB->addSuccessor(exitMBB);
8310 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8315 llvm::MachineBasicBlock*
8316 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8317 MachineBasicBlock *MBB) const {
8318 DebugLoc DL = MI->getDebugLoc();
8319 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8321 MachineFunction *MF = MBB->getParent();
8322 MachineRegisterInfo &MRI = MF->getRegInfo();
8324 const BasicBlock *BB = MBB->getBasicBlock();
8325 MachineFunction::iterator I = ++MBB->getIterator();
8328 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8329 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8331 unsigned DstReg = MI->getOperand(0).getReg();
8332 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8333 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8334 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8335 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8337 MVT PVT = getPointerTy(MF->getDataLayout());
8338 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8339 "Invalid Pointer Size!");
8340 // For v = setjmp(buf), we generate
8343 // SjLjSetup mainMBB
8349 // buf[LabelOffset] = LR
8353 // v = phi(main, restore)
8356 MachineBasicBlock *thisMBB = MBB;
8357 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8358 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8359 MF->insert(I, mainMBB);
8360 MF->insert(I, sinkMBB);
8362 MachineInstrBuilder MIB;
8364 // Transfer the remainder of BB and its successor edges to sinkMBB.
8365 sinkMBB->splice(sinkMBB->begin(), MBB,
8366 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8367 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8369 // Note that the structure of the jmp_buf used here is not compatible
8370 // with that used by libc, and is not designed to be. Specifically, it
8371 // stores only those 'reserved' registers that LLVM does not otherwise
8372 // understand how to spill. Also, by convention, by the time this
8373 // intrinsic is called, Clang has already stored the frame address in the
8374 // first slot of the buffer and stack address in the third. Following the
8375 // X86 target code, we'll store the jump address in the second slot. We also
8376 // need to save the TOC pointer (R2) to handle jumps between shared
8377 // libraries, and that will be stored in the fourth slot. The thread
8378 // identifier (R13) is not affected.
8381 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8382 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8383 const int64_t BPOffset = 4 * PVT.getStoreSize();
8385 // Prepare IP either in reg.
8386 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8387 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8388 unsigned BufReg = MI->getOperand(1).getReg();
8390 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8391 setUsesTOCBasePtr(*MBB->getParent());
8392 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8396 MIB.setMemRefs(MMOBegin, MMOEnd);
8399 // Naked functions never have a base pointer, and so we use r1. For all
8400 // other functions, this decision must be delayed until during PEI.
8402 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8403 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8405 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8407 MIB = BuildMI(*thisMBB, MI, DL,
8408 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8412 MIB.setMemRefs(MMOBegin, MMOEnd);
8415 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8416 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8417 MIB.addRegMask(TRI->getNoPreservedMask());
8419 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8421 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8423 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8425 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
8426 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
8431 BuildMI(mainMBB, DL,
8432 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8435 if (Subtarget.isPPC64()) {
8436 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8438 .addImm(LabelOffset)
8441 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8443 .addImm(LabelOffset)
8447 MIB.setMemRefs(MMOBegin, MMOEnd);
8449 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8450 mainMBB->addSuccessor(sinkMBB);
8453 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8454 TII->get(PPC::PHI), DstReg)
8455 .addReg(mainDstReg).addMBB(mainMBB)
8456 .addReg(restoreDstReg).addMBB(thisMBB);
8458 MI->eraseFromParent();
8463 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8464 MachineBasicBlock *MBB) const {
8465 DebugLoc DL = MI->getDebugLoc();
8466 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8468 MachineFunction *MF = MBB->getParent();
8469 MachineRegisterInfo &MRI = MF->getRegInfo();
8472 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8473 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8475 MVT PVT = getPointerTy(MF->getDataLayout());
8476 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8477 "Invalid Pointer Size!");
8479 const TargetRegisterClass *RC =
8480 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8481 unsigned Tmp = MRI.createVirtualRegister(RC);
8482 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8483 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8484 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8488 : (Subtarget.isSVR4ABI() &&
8489 MF->getTarget().getRelocationModel() == Reloc::PIC_
8493 MachineInstrBuilder MIB;
8495 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8496 const int64_t SPOffset = 2 * PVT.getStoreSize();
8497 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8498 const int64_t BPOffset = 4 * PVT.getStoreSize();
8500 unsigned BufReg = MI->getOperand(0).getReg();
8502 // Reload FP (the jumped-to function may not have had a
8503 // frame pointer, and if so, then its r31 will be restored
8505 if (PVT == MVT::i64) {
8506 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8510 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8514 MIB.setMemRefs(MMOBegin, MMOEnd);
8517 if (PVT == MVT::i64) {
8518 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8519 .addImm(LabelOffset)
8522 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8523 .addImm(LabelOffset)
8526 MIB.setMemRefs(MMOBegin, MMOEnd);
8529 if (PVT == MVT::i64) {
8530 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8534 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8538 MIB.setMemRefs(MMOBegin, MMOEnd);
8541 if (PVT == MVT::i64) {
8542 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8546 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8550 MIB.setMemRefs(MMOBegin, MMOEnd);
8553 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8554 setUsesTOCBasePtr(*MBB->getParent());
8555 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8559 MIB.setMemRefs(MMOBegin, MMOEnd);
8563 BuildMI(*MBB, MI, DL,
8564 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8565 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8567 MI->eraseFromParent();
8572 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8573 MachineBasicBlock *BB) const {
8574 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8575 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8576 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8577 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8578 // Call lowering should have added an r2 operand to indicate a dependence
8579 // on the TOC base pointer value. It can't however, because there is no
8580 // way to mark the dependence as implicit there, and so the stackmap code
8581 // will confuse it with a regular operand. Instead, add the dependence
8583 setUsesTOCBasePtr(*BB->getParent());
8584 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8587 return emitPatchPoint(MI, BB);
8590 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8591 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8592 return emitEHSjLjSetJmp(MI, BB);
8593 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8594 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8595 return emitEHSjLjLongJmp(MI, BB);
8598 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8600 // To "insert" these instructions we actually have to insert their
8601 // control-flow patterns.
8602 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8603 MachineFunction::iterator It = ++BB->getIterator();
8605 MachineFunction *F = BB->getParent();
8607 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8608 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8609 MI->getOpcode() == PPC::SELECT_I4 ||
8610 MI->getOpcode() == PPC::SELECT_I8)) {
8611 SmallVector<MachineOperand, 2> Cond;
8612 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8613 MI->getOpcode() == PPC::SELECT_CC_I8)
8614 Cond.push_back(MI->getOperand(4));
8616 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8617 Cond.push_back(MI->getOperand(1));
8619 DebugLoc dl = MI->getDebugLoc();
8620 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8621 Cond, MI->getOperand(2).getReg(),
8622 MI->getOperand(3).getReg());
8623 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8624 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8625 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8626 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8627 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8628 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8629 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8630 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8631 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8632 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8633 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8634 MI->getOpcode() == PPC::SELECT_I4 ||
8635 MI->getOpcode() == PPC::SELECT_I8 ||
8636 MI->getOpcode() == PPC::SELECT_F4 ||
8637 MI->getOpcode() == PPC::SELECT_F8 ||
8638 MI->getOpcode() == PPC::SELECT_QFRC ||
8639 MI->getOpcode() == PPC::SELECT_QSRC ||
8640 MI->getOpcode() == PPC::SELECT_QBRC ||
8641 MI->getOpcode() == PPC::SELECT_VRRC ||
8642 MI->getOpcode() == PPC::SELECT_VSFRC ||
8643 MI->getOpcode() == PPC::SELECT_VSSRC ||
8644 MI->getOpcode() == PPC::SELECT_VSRC) {
8645 // The incoming instruction knows the destination vreg to set, the
8646 // condition code register to branch on, the true/false values to
8647 // select between, and a branch opcode to use.
8652 // cmpTY ccX, r1, r2
8654 // fallthrough --> copy0MBB
8655 MachineBasicBlock *thisMBB = BB;
8656 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8657 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8658 DebugLoc dl = MI->getDebugLoc();
8659 F->insert(It, copy0MBB);
8660 F->insert(It, sinkMBB);
8662 // Transfer the remainder of BB and its successor edges to sinkMBB.
8663 sinkMBB->splice(sinkMBB->begin(), BB,
8664 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8665 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8667 // Next, add the true and fallthrough blocks as its successors.
8668 BB->addSuccessor(copy0MBB);
8669 BB->addSuccessor(sinkMBB);
8671 if (MI->getOpcode() == PPC::SELECT_I4 ||
8672 MI->getOpcode() == PPC::SELECT_I8 ||
8673 MI->getOpcode() == PPC::SELECT_F4 ||
8674 MI->getOpcode() == PPC::SELECT_F8 ||
8675 MI->getOpcode() == PPC::SELECT_QFRC ||
8676 MI->getOpcode() == PPC::SELECT_QSRC ||
8677 MI->getOpcode() == PPC::SELECT_QBRC ||
8678 MI->getOpcode() == PPC::SELECT_VRRC ||
8679 MI->getOpcode() == PPC::SELECT_VSFRC ||
8680 MI->getOpcode() == PPC::SELECT_VSSRC ||
8681 MI->getOpcode() == PPC::SELECT_VSRC) {
8682 BuildMI(BB, dl, TII->get(PPC::BC))
8683 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8685 unsigned SelectPred = MI->getOperand(4).getImm();
8686 BuildMI(BB, dl, TII->get(PPC::BCC))
8687 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8691 // %FalseValue = ...
8692 // # fallthrough to sinkMBB
8695 // Update machine-CFG edges
8696 BB->addSuccessor(sinkMBB);
8699 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8702 BuildMI(*BB, BB->begin(), dl,
8703 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8704 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8705 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8706 } else if (MI->getOpcode() == PPC::ReadTB) {
8707 // To read the 64-bit time-base register on a 32-bit target, we read the
8708 // two halves. Should the counter have wrapped while it was being read, we
8709 // need to try again.
8712 // mfspr Rx,TBU # load from TBU
8713 // mfspr Ry,TB # load from TB
8714 // mfspr Rz,TBU # load from TBU
8715 // cmpw crX,Rx,Rz # check if 'old'='new'
8716 // bne readLoop # branch if they're not equal
8719 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8720 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8721 DebugLoc dl = MI->getDebugLoc();
8722 F->insert(It, readMBB);
8723 F->insert(It, sinkMBB);
8725 // Transfer the remainder of BB and its successor edges to sinkMBB.
8726 sinkMBB->splice(sinkMBB->begin(), BB,
8727 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8728 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8730 BB->addSuccessor(readMBB);
8733 MachineRegisterInfo &RegInfo = F->getRegInfo();
8734 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8735 unsigned LoReg = MI->getOperand(0).getReg();
8736 unsigned HiReg = MI->getOperand(1).getReg();
8738 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8739 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8740 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8742 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8744 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8745 .addReg(HiReg).addReg(ReadAgainReg);
8746 BuildMI(BB, dl, TII->get(PPC::BCC))
8747 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8749 BB->addSuccessor(readMBB);
8750 BB->addSuccessor(sinkMBB);
8752 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8753 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8754 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8755 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8756 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8757 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8758 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8759 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8761 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8762 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8763 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8764 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8765 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8766 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8767 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8768 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8770 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8771 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8772 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8773 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8774 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8775 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8776 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8777 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8779 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8780 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8781 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8782 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8783 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8784 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8785 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8786 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8788 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8789 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8790 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8791 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8792 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8793 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8794 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8795 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8797 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8798 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8799 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8800 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8801 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8802 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8803 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8804 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8806 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8807 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8808 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8809 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8810 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8811 BB = EmitAtomicBinary(MI, BB, 4, 0);
8812 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8813 BB = EmitAtomicBinary(MI, BB, 8, 0);
8815 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8816 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8817 (Subtarget.hasPartwordAtomics() &&
8818 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8819 (Subtarget.hasPartwordAtomics() &&
8820 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8821 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8823 auto LoadMnemonic = PPC::LDARX;
8824 auto StoreMnemonic = PPC::STDCX;
8825 switch(MI->getOpcode()) {
8827 llvm_unreachable("Compare and swap of unknown size");
8828 case PPC::ATOMIC_CMP_SWAP_I8:
8829 LoadMnemonic = PPC::LBARX;
8830 StoreMnemonic = PPC::STBCX;
8831 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8833 case PPC::ATOMIC_CMP_SWAP_I16:
8834 LoadMnemonic = PPC::LHARX;
8835 StoreMnemonic = PPC::STHCX;
8836 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8838 case PPC::ATOMIC_CMP_SWAP_I32:
8839 LoadMnemonic = PPC::LWARX;
8840 StoreMnemonic = PPC::STWCX;
8842 case PPC::ATOMIC_CMP_SWAP_I64:
8843 LoadMnemonic = PPC::LDARX;
8844 StoreMnemonic = PPC::STDCX;
8847 unsigned dest = MI->getOperand(0).getReg();
8848 unsigned ptrA = MI->getOperand(1).getReg();
8849 unsigned ptrB = MI->getOperand(2).getReg();
8850 unsigned oldval = MI->getOperand(3).getReg();
8851 unsigned newval = MI->getOperand(4).getReg();
8852 DebugLoc dl = MI->getDebugLoc();
8854 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8855 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8856 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8857 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8858 F->insert(It, loop1MBB);
8859 F->insert(It, loop2MBB);
8860 F->insert(It, midMBB);
8861 F->insert(It, exitMBB);
8862 exitMBB->splice(exitMBB->begin(), BB,
8863 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8864 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8868 // fallthrough --> loopMBB
8869 BB->addSuccessor(loop1MBB);
8872 // l[bhwd]arx dest, ptr
8873 // cmp[wd] dest, oldval
8876 // st[bhwd]cx. newval, ptr
8880 // st[bhwd]cx. dest, ptr
8883 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8884 .addReg(ptrA).addReg(ptrB);
8885 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8886 .addReg(oldval).addReg(dest);
8887 BuildMI(BB, dl, TII->get(PPC::BCC))
8888 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8889 BB->addSuccessor(loop2MBB);
8890 BB->addSuccessor(midMBB);
8893 BuildMI(BB, dl, TII->get(StoreMnemonic))
8894 .addReg(newval).addReg(ptrA).addReg(ptrB);
8895 BuildMI(BB, dl, TII->get(PPC::BCC))
8896 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8897 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8898 BB->addSuccessor(loop1MBB);
8899 BB->addSuccessor(exitMBB);
8902 BuildMI(BB, dl, TII->get(StoreMnemonic))
8903 .addReg(dest).addReg(ptrA).addReg(ptrB);
8904 BB->addSuccessor(exitMBB);
8909 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8910 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8911 // We must use 64-bit registers for addresses when targeting 64-bit,
8912 // since we're actually doing arithmetic on them. Other registers
8914 bool is64bit = Subtarget.isPPC64();
8915 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8917 unsigned dest = MI->getOperand(0).getReg();
8918 unsigned ptrA = MI->getOperand(1).getReg();
8919 unsigned ptrB = MI->getOperand(2).getReg();
8920 unsigned oldval = MI->getOperand(3).getReg();
8921 unsigned newval = MI->getOperand(4).getReg();
8922 DebugLoc dl = MI->getDebugLoc();
8924 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8925 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8926 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8927 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8928 F->insert(It, loop1MBB);
8929 F->insert(It, loop2MBB);
8930 F->insert(It, midMBB);
8931 F->insert(It, exitMBB);
8932 exitMBB->splice(exitMBB->begin(), BB,
8933 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8934 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8936 MachineRegisterInfo &RegInfo = F->getRegInfo();
8937 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8938 : &PPC::GPRCRegClass;
8939 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8940 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8941 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8942 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8943 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8944 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8945 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8946 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8947 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8948 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8949 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8950 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8951 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8953 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8954 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8957 // fallthrough --> loopMBB
8958 BB->addSuccessor(loop1MBB);
8960 // The 4-byte load must be aligned, while a char or short may be
8961 // anywhere in the word. Hence all this nasty bookkeeping code.
8962 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8963 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8964 // xori shift, shift1, 24 [16]
8965 // rlwinm ptr, ptr1, 0, 0, 29
8966 // slw newval2, newval, shift
8967 // slw oldval2, oldval,shift
8968 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8969 // slw mask, mask2, shift
8970 // and newval3, newval2, mask
8971 // and oldval3, oldval2, mask
8973 // lwarx tmpDest, ptr
8974 // and tmp, tmpDest, mask
8975 // cmpw tmp, oldval3
8978 // andc tmp2, tmpDest, mask
8979 // or tmp4, tmp2, newval3
8984 // stwcx. tmpDest, ptr
8986 // srw dest, tmpDest, shift
8987 if (ptrA != ZeroReg) {
8988 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8989 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8990 .addReg(ptrA).addReg(ptrB);
8994 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8995 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8996 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8997 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8999 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
9000 .addReg(Ptr1Reg).addImm(0).addImm(61);
9002 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
9003 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
9004 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
9005 .addReg(newval).addReg(ShiftReg);
9006 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
9007 .addReg(oldval).addReg(ShiftReg);
9009 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
9011 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
9012 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
9013 .addReg(Mask3Reg).addImm(65535);
9015 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
9016 .addReg(Mask2Reg).addReg(ShiftReg);
9017 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
9018 .addReg(NewVal2Reg).addReg(MaskReg);
9019 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
9020 .addReg(OldVal2Reg).addReg(MaskReg);
9023 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
9024 .addReg(ZeroReg).addReg(PtrReg);
9025 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
9026 .addReg(TmpDestReg).addReg(MaskReg);
9027 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
9028 .addReg(TmpReg).addReg(OldVal3Reg);
9029 BuildMI(BB, dl, TII->get(PPC::BCC))
9030 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
9031 BB->addSuccessor(loop2MBB);
9032 BB->addSuccessor(midMBB);
9035 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
9036 .addReg(TmpDestReg).addReg(MaskReg);
9037 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
9038 .addReg(Tmp2Reg).addReg(NewVal3Reg);
9039 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
9040 .addReg(ZeroReg).addReg(PtrReg);
9041 BuildMI(BB, dl, TII->get(PPC::BCC))
9042 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
9043 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
9044 BB->addSuccessor(loop1MBB);
9045 BB->addSuccessor(exitMBB);
9048 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
9049 .addReg(ZeroReg).addReg(PtrReg);
9050 BB->addSuccessor(exitMBB);
9055 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
9057 } else if (MI->getOpcode() == PPC::FADDrtz) {
9058 // This pseudo performs an FADD with rounding mode temporarily forced
9059 // to round-to-zero. We emit this via custom inserter since the FPSCR
9060 // is not modeled at the SelectionDAG level.
9061 unsigned Dest = MI->getOperand(0).getReg();
9062 unsigned Src1 = MI->getOperand(1).getReg();
9063 unsigned Src2 = MI->getOperand(2).getReg();
9064 DebugLoc dl = MI->getDebugLoc();
9066 MachineRegisterInfo &RegInfo = F->getRegInfo();
9067 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
9069 // Save FPSCR value.
9070 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
9072 // Set rounding mode to round-to-zero.
9073 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
9074 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
9076 // Perform addition.
9077 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
9079 // Restore FPSCR value.
9080 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
9081 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9082 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
9083 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9084 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9085 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9086 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9087 PPC::ANDIo8 : PPC::ANDIo;
9088 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9089 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9091 MachineRegisterInfo &RegInfo = F->getRegInfo();
9092 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9093 &PPC::GPRCRegClass :
9094 &PPC::G8RCRegClass);
9096 DebugLoc dl = MI->getDebugLoc();
9097 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9098 .addReg(MI->getOperand(1).getReg()).addImm(1);
9099 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9100 MI->getOperand(0).getReg())
9101 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9102 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9103 DebugLoc Dl = MI->getDebugLoc();
9104 MachineRegisterInfo &RegInfo = F->getRegInfo();
9105 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9106 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9109 llvm_unreachable("Unexpected instr type to insert");
9112 MI->eraseFromParent(); // The pseudo instruction is gone now.
9116 //===----------------------------------------------------------------------===//
9117 // Target Optimization Hooks
9118 //===----------------------------------------------------------------------===//
9120 static std::string getRecipOp(const char *Base, EVT VT) {
9121 std::string RecipOp(Base);
9122 if (VT.getScalarType() == MVT::f64)
9128 RecipOp = "vec-" + RecipOp;
9133 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9134 DAGCombinerInfo &DCI,
9135 unsigned &RefinementSteps,
9136 bool &UseOneConstNR) const {
9137 EVT VT = Operand.getValueType();
9138 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9139 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9140 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9141 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9142 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9143 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9144 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9145 std::string RecipOp = getRecipOp("sqrt", VT);
9146 if (!Recips.isEnabled(RecipOp))
9149 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9150 UseOneConstNR = true;
9151 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9156 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9157 DAGCombinerInfo &DCI,
9158 unsigned &RefinementSteps) const {
9159 EVT VT = Operand.getValueType();
9160 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9161 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9162 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9163 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9164 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9165 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9166 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9167 std::string RecipOp = getRecipOp("div", VT);
9168 if (!Recips.isEnabled(RecipOp))
9171 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9172 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9177 unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
9178 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9179 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9180 // enabled for division), this functionality is redundant with the default
9181 // combiner logic (once the division -> reciprocal/multiply transformation
9182 // has taken place). As a result, this matters more for older cores than for
9185 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9186 // reciprocal if there are two or more FDIVs (for embedded cores with only
9187 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9188 switch (Subtarget.getDarwinDirective()) {
9193 case PPC::DIR_E500mc:
9194 case PPC::DIR_E5500:
9199 // isConsecutiveLSLoc needs to work even if all adds have not yet been
9200 // collapsed, and so we need to look through chains of them.
9201 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
9202 int64_t& Offset, SelectionDAG &DAG) {
9203 if (DAG.isBaseWithConstantOffset(Loc)) {
9204 Base = Loc.getOperand(0);
9205 Offset += cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
9207 // The base might itself be a base plus an offset, and if so, accumulate
9209 getBaseWithConstantOffset(Loc.getOperand(0), Base, Offset, DAG);
9213 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9214 unsigned Bytes, int Dist,
9215 SelectionDAG &DAG) {
9216 if (VT.getSizeInBits() / 8 != Bytes)
9219 SDValue BaseLoc = Base->getBasePtr();
9220 if (Loc.getOpcode() == ISD::FrameIndex) {
9221 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9223 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9224 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9225 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9226 int FS = MFI->getObjectSize(FI);
9227 int BFS = MFI->getObjectSize(BFI);
9228 if (FS != BFS || FS != (int)Bytes) return false;
9229 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9232 SDValue Base1 = Loc, Base2 = BaseLoc;
9233 int64_t Offset1 = 0, Offset2 = 0;
9234 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG);
9235 getBaseWithConstantOffset(BaseLoc, Base2, Offset2, DAG);
9236 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes))
9239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9240 const GlobalValue *GV1 = nullptr;
9241 const GlobalValue *GV2 = nullptr;
9244 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9245 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9246 if (isGA1 && isGA2 && GV1 == GV2)
9247 return Offset1 == (Offset2 + Dist*Bytes);
9251 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9252 // not enforce equality of the chain operands.
9253 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9254 unsigned Bytes, int Dist,
9255 SelectionDAG &DAG) {
9256 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9257 EVT VT = LS->getMemoryVT();
9258 SDValue Loc = LS->getBasePtr();
9259 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9262 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9264 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9265 default: return false;
9266 case Intrinsic::ppc_qpx_qvlfd:
9267 case Intrinsic::ppc_qpx_qvlfda:
9270 case Intrinsic::ppc_qpx_qvlfs:
9271 case Intrinsic::ppc_qpx_qvlfsa:
9274 case Intrinsic::ppc_qpx_qvlfcd:
9275 case Intrinsic::ppc_qpx_qvlfcda:
9278 case Intrinsic::ppc_qpx_qvlfcs:
9279 case Intrinsic::ppc_qpx_qvlfcsa:
9282 case Intrinsic::ppc_qpx_qvlfiwa:
9283 case Intrinsic::ppc_qpx_qvlfiwz:
9284 case Intrinsic::ppc_altivec_lvx:
9285 case Intrinsic::ppc_altivec_lvxl:
9286 case Intrinsic::ppc_vsx_lxvw4x:
9289 case Intrinsic::ppc_vsx_lxvd2x:
9292 case Intrinsic::ppc_altivec_lvebx:
9295 case Intrinsic::ppc_altivec_lvehx:
9298 case Intrinsic::ppc_altivec_lvewx:
9303 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9306 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9308 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9309 default: return false;
9310 case Intrinsic::ppc_qpx_qvstfd:
9311 case Intrinsic::ppc_qpx_qvstfda:
9314 case Intrinsic::ppc_qpx_qvstfs:
9315 case Intrinsic::ppc_qpx_qvstfsa:
9318 case Intrinsic::ppc_qpx_qvstfcd:
9319 case Intrinsic::ppc_qpx_qvstfcda:
9322 case Intrinsic::ppc_qpx_qvstfcs:
9323 case Intrinsic::ppc_qpx_qvstfcsa:
9326 case Intrinsic::ppc_qpx_qvstfiw:
9327 case Intrinsic::ppc_qpx_qvstfiwa:
9328 case Intrinsic::ppc_altivec_stvx:
9329 case Intrinsic::ppc_altivec_stvxl:
9330 case Intrinsic::ppc_vsx_stxvw4x:
9333 case Intrinsic::ppc_vsx_stxvd2x:
9336 case Intrinsic::ppc_altivec_stvebx:
9339 case Intrinsic::ppc_altivec_stvehx:
9342 case Intrinsic::ppc_altivec_stvewx:
9347 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9353 // Return true is there is a nearyby consecutive load to the one provided
9354 // (regardless of alignment). We search up and down the chain, looking though
9355 // token factors and other loads (but nothing else). As a result, a true result
9356 // indicates that it is safe to create a new consecutive load adjacent to the
9358 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9359 SDValue Chain = LD->getChain();
9360 EVT VT = LD->getMemoryVT();
9362 SmallSet<SDNode *, 16> LoadRoots;
9363 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9364 SmallSet<SDNode *, 16> Visited;
9366 // First, search up the chain, branching to follow all token-factor operands.
9367 // If we find a consecutive load, then we're done, otherwise, record all
9368 // nodes just above the top-level loads and token factors.
9369 while (!Queue.empty()) {
9370 SDNode *ChainNext = Queue.pop_back_val();
9371 if (!Visited.insert(ChainNext).second)
9374 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9375 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9378 if (!Visited.count(ChainLD->getChain().getNode()))
9379 Queue.push_back(ChainLD->getChain().getNode());
9380 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9381 for (const SDUse &O : ChainNext->ops())
9382 if (!Visited.count(O.getNode()))
9383 Queue.push_back(O.getNode());
9385 LoadRoots.insert(ChainNext);
9388 // Second, search down the chain, starting from the top-level nodes recorded
9389 // in the first phase. These top-level nodes are the nodes just above all
9390 // loads and token factors. Starting with their uses, recursively look though
9391 // all loads (just the chain uses) and token factors to find a consecutive
9396 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9397 IE = LoadRoots.end(); I != IE; ++I) {
9398 Queue.push_back(*I);
9400 while (!Queue.empty()) {
9401 SDNode *LoadRoot = Queue.pop_back_val();
9402 if (!Visited.insert(LoadRoot).second)
9405 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9406 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9409 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9410 UE = LoadRoot->use_end(); UI != UE; ++UI)
9411 if (((isa<MemSDNode>(*UI) &&
9412 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9413 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9414 Queue.push_back(*UI);
9421 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9422 DAGCombinerInfo &DCI) const {
9423 SelectionDAG &DAG = DCI.DAG;
9426 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9427 // If we're tracking CR bits, we need to be careful that we don't have:
9428 // trunc(binary-ops(zext(x), zext(y)))
9430 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9431 // such that we're unnecessarily moving things into GPRs when it would be
9432 // better to keep them in CR bits.
9434 // Note that trunc here can be an actual i1 trunc, or can be the effective
9435 // truncation that comes from a setcc or select_cc.
9436 if (N->getOpcode() == ISD::TRUNCATE &&
9437 N->getValueType(0) != MVT::i1)
9440 if (N->getOperand(0).getValueType() != MVT::i32 &&
9441 N->getOperand(0).getValueType() != MVT::i64)
9444 if (N->getOpcode() == ISD::SETCC ||
9445 N->getOpcode() == ISD::SELECT_CC) {
9446 // If we're looking at a comparison, then we need to make sure that the
9447 // high bits (all except for the first) don't matter the result.
9449 cast<CondCodeSDNode>(N->getOperand(
9450 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9451 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9453 if (ISD::isSignedIntSetCC(CC)) {
9454 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9455 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9457 } else if (ISD::isUnsignedIntSetCC(CC)) {
9458 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9459 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9460 !DAG.MaskedValueIsZero(N->getOperand(1),
9461 APInt::getHighBitsSet(OpBits, OpBits-1)))
9464 // This is neither a signed nor an unsigned comparison, just make sure
9465 // that the high bits are equal.
9466 APInt Op1Zero, Op1One;
9467 APInt Op2Zero, Op2One;
9468 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9469 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9471 // We don't really care about what is known about the first bit (if
9472 // anything), so clear it in all masks prior to comparing them.
9473 Op1Zero.clearBit(0); Op1One.clearBit(0);
9474 Op2Zero.clearBit(0); Op2One.clearBit(0);
9476 if (Op1Zero != Op2Zero || Op1One != Op2One)
9481 // We now know that the higher-order bits are irrelevant, we just need to
9482 // make sure that all of the intermediate operations are bit operations, and
9483 // all inputs are extensions.
9484 if (N->getOperand(0).getOpcode() != ISD::AND &&
9485 N->getOperand(0).getOpcode() != ISD::OR &&
9486 N->getOperand(0).getOpcode() != ISD::XOR &&
9487 N->getOperand(0).getOpcode() != ISD::SELECT &&
9488 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9489 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9490 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9491 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9492 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9495 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9496 N->getOperand(1).getOpcode() != ISD::AND &&
9497 N->getOperand(1).getOpcode() != ISD::OR &&
9498 N->getOperand(1).getOpcode() != ISD::XOR &&
9499 N->getOperand(1).getOpcode() != ISD::SELECT &&
9500 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9501 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9502 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9503 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9504 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9507 SmallVector<SDValue, 4> Inputs;
9508 SmallVector<SDValue, 8> BinOps, PromOps;
9509 SmallPtrSet<SDNode *, 16> Visited;
9511 for (unsigned i = 0; i < 2; ++i) {
9512 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9513 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9514 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9515 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9516 isa<ConstantSDNode>(N->getOperand(i)))
9517 Inputs.push_back(N->getOperand(i));
9519 BinOps.push_back(N->getOperand(i));
9521 if (N->getOpcode() == ISD::TRUNCATE)
9525 // Visit all inputs, collect all binary operations (and, or, xor and
9526 // select) that are all fed by extensions.
9527 while (!BinOps.empty()) {
9528 SDValue BinOp = BinOps.back();
9531 if (!Visited.insert(BinOp.getNode()).second)
9534 PromOps.push_back(BinOp);
9536 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9537 // The condition of the select is not promoted.
9538 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9540 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9543 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9544 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9545 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9546 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9547 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9548 Inputs.push_back(BinOp.getOperand(i));
9549 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9550 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9551 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9552 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9553 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9554 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9555 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9556 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9557 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9558 BinOps.push_back(BinOp.getOperand(i));
9560 // We have an input that is not an extension or another binary
9561 // operation; we'll abort this transformation.
9567 // Make sure that this is a self-contained cluster of operations (which
9568 // is not quite the same thing as saying that everything has only one
9570 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9571 if (isa<ConstantSDNode>(Inputs[i]))
9574 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9575 UE = Inputs[i].getNode()->use_end();
9578 if (User != N && !Visited.count(User))
9581 // Make sure that we're not going to promote the non-output-value
9582 // operand(s) or SELECT or SELECT_CC.
9583 // FIXME: Although we could sometimes handle this, and it does occur in
9584 // practice that one of the condition inputs to the select is also one of
9585 // the outputs, we currently can't deal with this.
9586 if (User->getOpcode() == ISD::SELECT) {
9587 if (User->getOperand(0) == Inputs[i])
9589 } else if (User->getOpcode() == ISD::SELECT_CC) {
9590 if (User->getOperand(0) == Inputs[i] ||
9591 User->getOperand(1) == Inputs[i])
9597 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9598 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9599 UE = PromOps[i].getNode()->use_end();
9602 if (User != N && !Visited.count(User))
9605 // Make sure that we're not going to promote the non-output-value
9606 // operand(s) or SELECT or SELECT_CC.
9607 // FIXME: Although we could sometimes handle this, and it does occur in
9608 // practice that one of the condition inputs to the select is also one of
9609 // the outputs, we currently can't deal with this.
9610 if (User->getOpcode() == ISD::SELECT) {
9611 if (User->getOperand(0) == PromOps[i])
9613 } else if (User->getOpcode() == ISD::SELECT_CC) {
9614 if (User->getOperand(0) == PromOps[i] ||
9615 User->getOperand(1) == PromOps[i])
9621 // Replace all inputs with the extension operand.
9622 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9623 // Constants may have users outside the cluster of to-be-promoted nodes,
9624 // and so we need to replace those as we do the promotions.
9625 if (isa<ConstantSDNode>(Inputs[i]))
9628 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9631 // Replace all operations (these are all the same, but have a different
9632 // (i1) return type). DAG.getNode will validate that the types of
9633 // a binary operator match, so go through the list in reverse so that
9634 // we've likely promoted both operands first. Any intermediate truncations or
9635 // extensions disappear.
9636 while (!PromOps.empty()) {
9637 SDValue PromOp = PromOps.back();
9640 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9641 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9642 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9643 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9644 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9645 PromOp.getOperand(0).getValueType() != MVT::i1) {
9646 // The operand is not yet ready (see comment below).
9647 PromOps.insert(PromOps.begin(), PromOp);
9651 SDValue RepValue = PromOp.getOperand(0);
9652 if (isa<ConstantSDNode>(RepValue))
9653 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9655 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9660 switch (PromOp.getOpcode()) {
9661 default: C = 0; break;
9662 case ISD::SELECT: C = 1; break;
9663 case ISD::SELECT_CC: C = 2; break;
9666 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9667 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9668 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9669 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9670 // The to-be-promoted operands of this node have not yet been
9671 // promoted (this should be rare because we're going through the
9672 // list backward, but if one of the operands has several users in
9673 // this cluster of to-be-promoted nodes, it is possible).
9674 PromOps.insert(PromOps.begin(), PromOp);
9678 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9679 PromOp.getNode()->op_end());
9681 // If there are any constant inputs, make sure they're replaced now.
9682 for (unsigned i = 0; i < 2; ++i)
9683 if (isa<ConstantSDNode>(Ops[C+i]))
9684 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9686 DAG.ReplaceAllUsesOfValueWith(PromOp,
9687 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9690 // Now we're left with the initial truncation itself.
9691 if (N->getOpcode() == ISD::TRUNCATE)
9692 return N->getOperand(0);
9694 // Otherwise, this is a comparison. The operands to be compared have just
9695 // changed type (to i1), but everything else is the same.
9696 return SDValue(N, 0);
9699 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9700 DAGCombinerInfo &DCI) const {
9701 SelectionDAG &DAG = DCI.DAG;
9704 // If we're tracking CR bits, we need to be careful that we don't have:
9705 // zext(binary-ops(trunc(x), trunc(y)))
9707 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9708 // such that we're unnecessarily moving things into CR bits that can more
9709 // efficiently stay in GPRs. Note that if we're not certain that the high
9710 // bits are set as required by the final extension, we still may need to do
9711 // some masking to get the proper behavior.
9713 // This same functionality is important on PPC64 when dealing with
9714 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9715 // the return values of functions. Because it is so similar, it is handled
9718 if (N->getValueType(0) != MVT::i32 &&
9719 N->getValueType(0) != MVT::i64)
9722 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9723 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9726 if (N->getOperand(0).getOpcode() != ISD::AND &&
9727 N->getOperand(0).getOpcode() != ISD::OR &&
9728 N->getOperand(0).getOpcode() != ISD::XOR &&
9729 N->getOperand(0).getOpcode() != ISD::SELECT &&
9730 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9733 SmallVector<SDValue, 4> Inputs;
9734 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9735 SmallPtrSet<SDNode *, 16> Visited;
9737 // Visit all inputs, collect all binary operations (and, or, xor and
9738 // select) that are all fed by truncations.
9739 while (!BinOps.empty()) {
9740 SDValue BinOp = BinOps.back();
9743 if (!Visited.insert(BinOp.getNode()).second)
9746 PromOps.push_back(BinOp);
9748 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9749 // The condition of the select is not promoted.
9750 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9752 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9755 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9756 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9757 Inputs.push_back(BinOp.getOperand(i));
9758 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9759 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9760 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9761 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9762 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9763 BinOps.push_back(BinOp.getOperand(i));
9765 // We have an input that is not a truncation or another binary
9766 // operation; we'll abort this transformation.
9772 // The operands of a select that must be truncated when the select is
9773 // promoted because the operand is actually part of the to-be-promoted set.
9774 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9776 // Make sure that this is a self-contained cluster of operations (which
9777 // is not quite the same thing as saying that everything has only one
9779 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9780 if (isa<ConstantSDNode>(Inputs[i]))
9783 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9784 UE = Inputs[i].getNode()->use_end();
9787 if (User != N && !Visited.count(User))
9790 // If we're going to promote the non-output-value operand(s) or SELECT or
9791 // SELECT_CC, record them for truncation.
9792 if (User->getOpcode() == ISD::SELECT) {
9793 if (User->getOperand(0) == Inputs[i])
9794 SelectTruncOp[0].insert(std::make_pair(User,
9795 User->getOperand(0).getValueType()));
9796 } else if (User->getOpcode() == ISD::SELECT_CC) {
9797 if (User->getOperand(0) == Inputs[i])
9798 SelectTruncOp[0].insert(std::make_pair(User,
9799 User->getOperand(0).getValueType()));
9800 if (User->getOperand(1) == Inputs[i])
9801 SelectTruncOp[1].insert(std::make_pair(User,
9802 User->getOperand(1).getValueType()));
9807 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9808 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9809 UE = PromOps[i].getNode()->use_end();
9812 if (User != N && !Visited.count(User))
9815 // If we're going to promote the non-output-value operand(s) or SELECT or
9816 // SELECT_CC, record them for truncation.
9817 if (User->getOpcode() == ISD::SELECT) {
9818 if (User->getOperand(0) == PromOps[i])
9819 SelectTruncOp[0].insert(std::make_pair(User,
9820 User->getOperand(0).getValueType()));
9821 } else if (User->getOpcode() == ISD::SELECT_CC) {
9822 if (User->getOperand(0) == PromOps[i])
9823 SelectTruncOp[0].insert(std::make_pair(User,
9824 User->getOperand(0).getValueType()));
9825 if (User->getOperand(1) == PromOps[i])
9826 SelectTruncOp[1].insert(std::make_pair(User,
9827 User->getOperand(1).getValueType()));
9832 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9833 bool ReallyNeedsExt = false;
9834 if (N->getOpcode() != ISD::ANY_EXTEND) {
9835 // If all of the inputs are not already sign/zero extended, then
9836 // we'll still need to do that at the end.
9837 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9838 if (isa<ConstantSDNode>(Inputs[i]))
9842 Inputs[i].getOperand(0).getValueSizeInBits();
9843 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9845 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9846 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9847 APInt::getHighBitsSet(OpBits,
9848 OpBits-PromBits))) ||
9849 (N->getOpcode() == ISD::SIGN_EXTEND &&
9850 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9851 (OpBits-(PromBits-1)))) {
9852 ReallyNeedsExt = true;
9858 // Replace all inputs, either with the truncation operand, or a
9859 // truncation or extension to the final output type.
9860 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9861 // Constant inputs need to be replaced with the to-be-promoted nodes that
9862 // use them because they might have users outside of the cluster of
9864 if (isa<ConstantSDNode>(Inputs[i]))
9867 SDValue InSrc = Inputs[i].getOperand(0);
9868 if (Inputs[i].getValueType() == N->getValueType(0))
9869 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9870 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9871 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9872 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9873 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9874 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9875 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9877 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9878 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9881 // Replace all operations (these are all the same, but have a different
9882 // (promoted) return type). DAG.getNode will validate that the types of
9883 // a binary operator match, so go through the list in reverse so that
9884 // we've likely promoted both operands first.
9885 while (!PromOps.empty()) {
9886 SDValue PromOp = PromOps.back();
9890 switch (PromOp.getOpcode()) {
9891 default: C = 0; break;
9892 case ISD::SELECT: C = 1; break;
9893 case ISD::SELECT_CC: C = 2; break;
9896 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9897 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9898 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9899 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9900 // The to-be-promoted operands of this node have not yet been
9901 // promoted (this should be rare because we're going through the
9902 // list backward, but if one of the operands has several users in
9903 // this cluster of to-be-promoted nodes, it is possible).
9904 PromOps.insert(PromOps.begin(), PromOp);
9908 // For SELECT and SELECT_CC nodes, we do a similar check for any
9909 // to-be-promoted comparison inputs.
9910 if (PromOp.getOpcode() == ISD::SELECT ||
9911 PromOp.getOpcode() == ISD::SELECT_CC) {
9912 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9913 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9914 (SelectTruncOp[1].count(PromOp.getNode()) &&
9915 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9916 PromOps.insert(PromOps.begin(), PromOp);
9921 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9922 PromOp.getNode()->op_end());
9924 // If this node has constant inputs, then they'll need to be promoted here.
9925 for (unsigned i = 0; i < 2; ++i) {
9926 if (!isa<ConstantSDNode>(Ops[C+i]))
9928 if (Ops[C+i].getValueType() == N->getValueType(0))
9931 if (N->getOpcode() == ISD::SIGN_EXTEND)
9932 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9933 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9934 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9936 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9939 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9940 // truncate them again to the original value type.
9941 if (PromOp.getOpcode() == ISD::SELECT ||
9942 PromOp.getOpcode() == ISD::SELECT_CC) {
9943 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9944 if (SI0 != SelectTruncOp[0].end())
9945 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9946 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9947 if (SI1 != SelectTruncOp[1].end())
9948 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9951 DAG.ReplaceAllUsesOfValueWith(PromOp,
9952 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9955 // Now we're left with the initial extension itself.
9956 if (!ReallyNeedsExt)
9957 return N->getOperand(0);
9959 // To zero extend, just mask off everything except for the first bit (in the
9961 if (N->getOpcode() == ISD::ZERO_EXTEND)
9962 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9963 DAG.getConstant(APInt::getLowBitsSet(
9964 N->getValueSizeInBits(0), PromBits),
9965 dl, N->getValueType(0)));
9967 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9968 "Invalid extension type");
9969 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
9971 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9973 ISD::SRA, dl, N->getValueType(0),
9974 DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst),
9978 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9979 DAGCombinerInfo &DCI) const {
9980 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9981 N->getOpcode() == ISD::UINT_TO_FP) &&
9982 "Need an int -> FP conversion node here");
9984 if (!Subtarget.has64BitSupport())
9987 SelectionDAG &DAG = DCI.DAG;
9991 // Don't handle ppc_fp128 here or i1 conversions.
9992 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9994 if (Op.getOperand(0).getValueType() == MVT::i1)
9997 // For i32 intermediate values, unfortunately, the conversion functions
9998 // leave the upper 32 bits of the value are undefined. Within the set of
9999 // scalar instructions, we have no method for zero- or sign-extending the
10000 // value. Thus, we cannot handle i32 intermediate values here.
10001 if (Op.getOperand(0).getValueType() == MVT::i32)
10004 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
10005 "UINT_TO_FP is supported only with FPCVT");
10007 // If we have FCFIDS, then use it when converting to single-precision.
10008 // Otherwise, convert to double-precision and then round.
10009 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10010 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
10012 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
10014 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10018 // If we're converting from a float, to an int, and back to a float again,
10019 // then we don't need the store/load pair at all.
10020 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
10021 Subtarget.hasFPCVT()) ||
10022 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
10023 SDValue Src = Op.getOperand(0).getOperand(0);
10024 if (Src.getValueType() == MVT::f32) {
10025 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
10026 DCI.AddToWorklist(Src.getNode());
10027 } else if (Src.getValueType() != MVT::f64) {
10028 // Make sure that we don't pick up a ppc_fp128 source value.
10033 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
10036 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
10037 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
10039 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
10040 FP = DAG.getNode(ISD::FP_ROUND, dl,
10041 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
10042 DCI.AddToWorklist(FP.getNode());
10051 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
10052 // builtins) into loads with swaps.
10053 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
10054 DAGCombinerInfo &DCI) const {
10055 SelectionDAG &DAG = DCI.DAG;
10059 MachineMemOperand *MMO;
10061 switch (N->getOpcode()) {
10063 llvm_unreachable("Unexpected opcode for little endian VSX load");
10065 LoadSDNode *LD = cast<LoadSDNode>(N);
10066 Chain = LD->getChain();
10067 Base = LD->getBasePtr();
10068 MMO = LD->getMemOperand();
10069 // If the MMO suggests this isn't a load of a full vector, leave
10070 // things alone. For a built-in, we have to make the change for
10071 // correctness, so if there is a size problem that will be a bug.
10072 if (MMO->getSize() < 16)
10076 case ISD::INTRINSIC_W_CHAIN: {
10077 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10078 Chain = Intrin->getChain();
10079 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
10080 // us what we want. Get operand 2 instead.
10081 Base = Intrin->getOperand(2);
10082 MMO = Intrin->getMemOperand();
10087 MVT VecTy = N->getValueType(0).getSimpleVT();
10088 SDValue LoadOps[] = { Chain, Base };
10089 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
10090 DAG.getVTList(VecTy, MVT::Other),
10091 LoadOps, VecTy, MMO);
10092 DCI.AddToWorklist(Load.getNode());
10093 Chain = Load.getValue(1);
10094 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10095 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
10096 DCI.AddToWorklist(Swap.getNode());
10100 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
10101 // builtins) into stores with swaps.
10102 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
10103 DAGCombinerInfo &DCI) const {
10104 SelectionDAG &DAG = DCI.DAG;
10109 MachineMemOperand *MMO;
10111 switch (N->getOpcode()) {
10113 llvm_unreachable("Unexpected opcode for little endian VSX store");
10115 StoreSDNode *ST = cast<StoreSDNode>(N);
10116 Chain = ST->getChain();
10117 Base = ST->getBasePtr();
10118 MMO = ST->getMemOperand();
10120 // If the MMO suggests this isn't a store of a full vector, leave
10121 // things alone. For a built-in, we have to make the change for
10122 // correctness, so if there is a size problem that will be a bug.
10123 if (MMO->getSize() < 16)
10127 case ISD::INTRINSIC_VOID: {
10128 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10129 Chain = Intrin->getChain();
10130 // Intrin->getBasePtr() oddly does not get what we want.
10131 Base = Intrin->getOperand(3);
10132 MMO = Intrin->getMemOperand();
10138 SDValue Src = N->getOperand(SrcOpnd);
10139 MVT VecTy = Src.getValueType().getSimpleVT();
10140 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10141 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10142 DCI.AddToWorklist(Swap.getNode());
10143 Chain = Swap.getValue(1);
10144 SDValue StoreOps[] = { Chain, Swap, Base };
10145 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10146 DAG.getVTList(MVT::Other),
10147 StoreOps, VecTy, MMO);
10148 DCI.AddToWorklist(Store.getNode());
10152 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10153 DAGCombinerInfo &DCI) const {
10154 SelectionDAG &DAG = DCI.DAG;
10156 switch (N->getOpcode()) {
10159 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10160 if (C->isNullValue()) // 0 << V -> 0.
10161 return N->getOperand(0);
10165 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10166 if (C->isNullValue()) // 0 >>u V -> 0.
10167 return N->getOperand(0);
10171 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10172 if (C->isNullValue() || // 0 >>s V -> 0.
10173 C->isAllOnesValue()) // -1 >>s V -> -1.
10174 return N->getOperand(0);
10177 case ISD::SIGN_EXTEND:
10178 case ISD::ZERO_EXTEND:
10179 case ISD::ANY_EXTEND:
10180 return DAGCombineExtBoolTrunc(N, DCI);
10181 case ISD::TRUNCATE:
10183 case ISD::SELECT_CC:
10184 return DAGCombineTruncBoolExt(N, DCI);
10185 case ISD::SINT_TO_FP:
10186 case ISD::UINT_TO_FP:
10187 return combineFPToIntToFP(N, DCI);
10189 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10190 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10191 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10192 N->getOperand(1).getValueType() == MVT::i32 &&
10193 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10194 SDValue Val = N->getOperand(1).getOperand(0);
10195 if (Val.getValueType() == MVT::f32) {
10196 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10197 DCI.AddToWorklist(Val.getNode());
10199 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10200 DCI.AddToWorklist(Val.getNode());
10203 N->getOperand(0), Val, N->getOperand(2),
10204 DAG.getValueType(N->getOperand(1).getValueType())
10207 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10208 DAG.getVTList(MVT::Other), Ops,
10209 cast<StoreSDNode>(N)->getMemoryVT(),
10210 cast<StoreSDNode>(N)->getMemOperand());
10211 DCI.AddToWorklist(Val.getNode());
10215 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10216 if (cast<StoreSDNode>(N)->isUnindexed() &&
10217 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10218 N->getOperand(1).getNode()->hasOneUse() &&
10219 (N->getOperand(1).getValueType() == MVT::i32 ||
10220 N->getOperand(1).getValueType() == MVT::i16 ||
10221 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10222 N->getOperand(1).getValueType() == MVT::i64))) {
10223 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10224 // Do an any-extend to 32-bits if this is a half-word input.
10225 if (BSwapOp.getValueType() == MVT::i16)
10226 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10229 N->getOperand(0), BSwapOp, N->getOperand(2),
10230 DAG.getValueType(N->getOperand(1).getValueType())
10233 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10234 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10235 cast<StoreSDNode>(N)->getMemOperand());
10238 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10239 EVT VT = N->getOperand(1).getValueType();
10240 if (VT.isSimple()) {
10241 MVT StoreVT = VT.getSimpleVT();
10242 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10243 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10244 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10245 return expandVSXStoreForLE(N, DCI);
10250 LoadSDNode *LD = cast<LoadSDNode>(N);
10251 EVT VT = LD->getValueType(0);
10253 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10254 if (VT.isSimple()) {
10255 MVT LoadVT = VT.getSimpleVT();
10256 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10257 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10258 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10259 return expandVSXLoadForLE(N, DCI);
10262 EVT MemVT = LD->getMemoryVT();
10263 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10264 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
10265 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10266 unsigned ScalarABIAlignment = DAG.getDataLayout().getABITypeAlignment(STy);
10267 if (LD->isUnindexed() && VT.isVector() &&
10268 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10269 // P8 and later hardware should just use LOAD.
10270 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10271 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10272 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10273 LD->getAlignment() >= ScalarABIAlignment)) &&
10274 LD->getAlignment() < ABIAlignment) {
10275 // This is a type-legal unaligned Altivec or QPX load.
10276 SDValue Chain = LD->getChain();
10277 SDValue Ptr = LD->getBasePtr();
10278 bool isLittleEndian = Subtarget.isLittleEndian();
10280 // This implements the loading of unaligned vectors as described in
10281 // the venerable Apple Velocity Engine overview. Specifically:
10282 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10283 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10285 // The general idea is to expand a sequence of one or more unaligned
10286 // loads into an alignment-based permutation-control instruction (lvsl
10287 // or lvsr), a series of regular vector loads (which always truncate
10288 // their input address to an aligned address), and a series of
10289 // permutations. The results of these permutations are the requested
10290 // loaded values. The trick is that the last "extra" load is not taken
10291 // from the address you might suspect (sizeof(vector) bytes after the
10292 // last requested load), but rather sizeof(vector) - 1 bytes after the
10293 // last requested vector. The point of this is to avoid a page fault if
10294 // the base address happened to be aligned. This works because if the
10295 // base address is aligned, then adding less than a full vector length
10296 // will cause the last vector in the sequence to be (re)loaded.
10297 // Otherwise, the next vector will be fetched as you might suspect was
10300 // We might be able to reuse the permutation generation from
10301 // a different base address offset from this one by an aligned amount.
10302 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10303 // optimization later.
10304 Intrinsic::ID Intr, IntrLD, IntrPerm;
10305 MVT PermCntlTy, PermTy, LDTy;
10306 if (Subtarget.hasAltivec()) {
10307 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10308 Intrinsic::ppc_altivec_lvsl;
10309 IntrLD = Intrinsic::ppc_altivec_lvx;
10310 IntrPerm = Intrinsic::ppc_altivec_vperm;
10311 PermCntlTy = MVT::v16i8;
10312 PermTy = MVT::v4i32;
10315 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10316 Intrinsic::ppc_qpx_qvlpcls;
10317 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10318 Intrinsic::ppc_qpx_qvlfs;
10319 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10320 PermCntlTy = MVT::v4f64;
10321 PermTy = MVT::v4f64;
10322 LDTy = MemVT.getSimpleVT();
10325 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10327 // Create the new MMO for the new base load. It is like the original MMO,
10328 // but represents an area in memory almost twice the vector size centered
10329 // on the original address. If the address is unaligned, we might start
10330 // reading up to (sizeof(vector)-1) bytes below the address of the
10331 // original unaligned load.
10332 MachineFunction &MF = DAG.getMachineFunction();
10333 MachineMemOperand *BaseMMO =
10334 MF.getMachineMemOperand(LD->getMemOperand(),
10335 -(long)MemVT.getStoreSize()+1,
10336 2*MemVT.getStoreSize()-1);
10338 // Create the new base load.
10340 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
10341 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10343 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10344 DAG.getVTList(PermTy, MVT::Other),
10345 BaseLoadOps, LDTy, BaseMMO);
10347 // Note that the value of IncOffset (which is provided to the next
10348 // load's pointer info offset value, and thus used to calculate the
10349 // alignment), and the value of IncValue (which is actually used to
10350 // increment the pointer value) are different! This is because we
10351 // require the next load to appear to be aligned, even though it
10352 // is actually offset from the base pointer by a lesser amount.
10353 int IncOffset = VT.getSizeInBits() / 8;
10354 int IncValue = IncOffset;
10356 // Walk (both up and down) the chain looking for another load at the real
10357 // (aligned) offset (the alignment of the other load does not matter in
10358 // this case). If found, then do not use the offset reduction trick, as
10359 // that will prevent the loads from being later combined (as they would
10360 // otherwise be duplicates).
10361 if (!findConsecutiveLoad(LD, DAG))
10364 SDValue Increment =
10365 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
10366 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10368 MachineMemOperand *ExtraMMO =
10369 MF.getMachineMemOperand(LD->getMemOperand(),
10370 1, 2*MemVT.getStoreSize()-1);
10371 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10372 SDValue ExtraLoad =
10373 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10374 DAG.getVTList(PermTy, MVT::Other),
10375 ExtraLoadOps, LDTy, ExtraMMO);
10377 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10378 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10380 // Because vperm has a big-endian bias, we must reverse the order
10381 // of the input vectors and complement the permute control vector
10382 // when generating little endian code. We have already handled the
10383 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10384 // and ExtraLoad here.
10386 if (isLittleEndian)
10387 Perm = BuildIntrinsicOp(IntrPerm,
10388 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10390 Perm = BuildIntrinsicOp(IntrPerm,
10391 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10394 Perm = Subtarget.hasAltivec() ?
10395 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10396 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10397 DAG.getTargetConstant(1, dl, MVT::i64));
10398 // second argument is 1 because this rounding
10399 // is always exact.
10401 // The output of the permutation is our loaded result, the TokenFactor is
10403 DCI.CombineTo(N, Perm, TF);
10404 return SDValue(N, 0);
10408 case ISD::INTRINSIC_WO_CHAIN: {
10409 bool isLittleEndian = Subtarget.isLittleEndian();
10410 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10411 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10412 : Intrinsic::ppc_altivec_lvsl);
10413 if ((IID == Intr ||
10414 IID == Intrinsic::ppc_qpx_qvlpcld ||
10415 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10416 N->getOperand(1)->getOpcode() == ISD::ADD) {
10417 SDValue Add = N->getOperand(1);
10419 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10420 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10422 if (DAG.MaskedValueIsZero(
10423 Add->getOperand(1),
10424 APInt::getAllOnesValue(Bits /* alignment */)
10426 Add.getValueType().getScalarType().getSizeInBits()))) {
10427 SDNode *BasePtr = Add->getOperand(0).getNode();
10428 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10429 UE = BasePtr->use_end();
10431 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10432 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10433 // We've found another LVSL/LVSR, and this address is an aligned
10434 // multiple of that one. The results will be the same, so use the
10435 // one we've just found instead.
10437 return SDValue(*UI, 0);
10442 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10443 SDNode *BasePtr = Add->getOperand(0).getNode();
10444 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10445 UE = BasePtr->use_end(); UI != UE; ++UI) {
10446 if (UI->getOpcode() == ISD::ADD &&
10447 isa<ConstantSDNode>(UI->getOperand(1)) &&
10448 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10449 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10450 (1ULL << Bits) == 0) {
10451 SDNode *OtherAdd = *UI;
10452 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10453 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10454 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10455 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10456 return SDValue(*VI, 0);
10466 case ISD::INTRINSIC_W_CHAIN: {
10467 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10468 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10469 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10472 case Intrinsic::ppc_vsx_lxvw4x:
10473 case Intrinsic::ppc_vsx_lxvd2x:
10474 return expandVSXLoadForLE(N, DCI);
10479 case ISD::INTRINSIC_VOID: {
10480 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10481 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10482 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10485 case Intrinsic::ppc_vsx_stxvw4x:
10486 case Intrinsic::ppc_vsx_stxvd2x:
10487 return expandVSXStoreForLE(N, DCI);
10493 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10494 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10495 N->getOperand(0).hasOneUse() &&
10496 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10497 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10498 N->getValueType(0) == MVT::i64))) {
10499 SDValue Load = N->getOperand(0);
10500 LoadSDNode *LD = cast<LoadSDNode>(Load);
10501 // Create the byte-swapping load.
10503 LD->getChain(), // Chain
10504 LD->getBasePtr(), // Ptr
10505 DAG.getValueType(N->getValueType(0)) // VT
10508 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10509 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10510 MVT::i64 : MVT::i32, MVT::Other),
10511 Ops, LD->getMemoryVT(), LD->getMemOperand());
10513 // If this is an i16 load, insert the truncate.
10514 SDValue ResVal = BSLoad;
10515 if (N->getValueType(0) == MVT::i16)
10516 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10518 // First, combine the bswap away. This makes the value produced by the
10520 DCI.CombineTo(N, ResVal);
10522 // Next, combine the load away, we give it a bogus result value but a real
10523 // chain result. The result value is dead because the bswap is dead.
10524 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10526 // Return N so it doesn't get rechecked!
10527 return SDValue(N, 0);
10531 case PPCISD::VCMP: {
10532 // If a VCMPo node already exists with exactly the same operands as this
10533 // node, use its result instead of this node (VCMPo computes both a CR6 and
10534 // a normal output).
10536 if (!N->getOperand(0).hasOneUse() &&
10537 !N->getOperand(1).hasOneUse() &&
10538 !N->getOperand(2).hasOneUse()) {
10540 // Scan all of the users of the LHS, looking for VCMPo's that match.
10541 SDNode *VCMPoNode = nullptr;
10543 SDNode *LHSN = N->getOperand(0).getNode();
10544 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10546 if (UI->getOpcode() == PPCISD::VCMPo &&
10547 UI->getOperand(1) == N->getOperand(1) &&
10548 UI->getOperand(2) == N->getOperand(2) &&
10549 UI->getOperand(0) == N->getOperand(0)) {
10554 // If there is no VCMPo node, or if the flag value has a single use, don't
10556 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10559 // Look at the (necessarily single) use of the flag value. If it has a
10560 // chain, this transformation is more complex. Note that multiple things
10561 // could use the value result, which we should ignore.
10562 SDNode *FlagUser = nullptr;
10563 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10564 FlagUser == nullptr; ++UI) {
10565 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10566 SDNode *User = *UI;
10567 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10568 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10575 // If the user is a MFOCRF instruction, we know this is safe.
10576 // Otherwise we give up for right now.
10577 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10578 return SDValue(VCMPoNode, 0);
10582 case ISD::BRCOND: {
10583 SDValue Cond = N->getOperand(1);
10584 SDValue Target = N->getOperand(2);
10586 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10587 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10588 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10590 // We now need to make the intrinsic dead (it cannot be instruction
10592 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10593 assert(Cond.getNode()->hasOneUse() &&
10594 "Counter decrement has more than one use");
10596 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10597 N->getOperand(0), Target);
10602 // If this is a branch on an altivec predicate comparison, lower this so
10603 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10604 // lowering is done pre-legalize, because the legalizer lowers the predicate
10605 // compare down to code that is difficult to reassemble.
10606 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10607 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10609 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10610 // value. If so, pass-through the AND to get to the intrinsic.
10611 if (LHS.getOpcode() == ISD::AND &&
10612 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10613 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10614 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10615 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10616 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
10618 LHS = LHS.getOperand(0);
10620 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10621 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10622 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10623 isa<ConstantSDNode>(RHS)) {
10624 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10625 "Counter decrement comparison is not EQ or NE");
10627 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10628 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10629 (CC == ISD::SETNE && !Val);
10631 // We now need to make the intrinsic dead (it cannot be instruction
10633 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10634 assert(LHS.getNode()->hasOneUse() &&
10635 "Counter decrement has more than one use");
10637 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10638 N->getOperand(0), N->getOperand(4));
10644 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10645 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10646 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10647 assert(isDot && "Can't compare against a vector result!");
10649 // If this is a comparison against something other than 0/1, then we know
10650 // that the condition is never/always true.
10651 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10652 if (Val != 0 && Val != 1) {
10653 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10654 return N->getOperand(0);
10655 // Always !=, turn it into an unconditional branch.
10656 return DAG.getNode(ISD::BR, dl, MVT::Other,
10657 N->getOperand(0), N->getOperand(4));
10660 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10662 // Create the PPCISD altivec 'dot' comparison node.
10664 LHS.getOperand(2), // LHS of compare
10665 LHS.getOperand(3), // RHS of compare
10666 DAG.getConstant(CompareOpc, dl, MVT::i32)
10668 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10669 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10671 // Unpack the result based on how the target uses it.
10672 PPC::Predicate CompOpc;
10673 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10674 default: // Can't happen, don't crash on invalid number though.
10675 case 0: // Branch on the value of the EQ bit of CR6.
10676 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10678 case 1: // Branch on the inverted value of the EQ bit of CR6.
10679 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10681 case 2: // Branch on the value of the LT bit of CR6.
10682 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10684 case 3: // Branch on the inverted value of the LT bit of CR6.
10685 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10689 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10690 DAG.getConstant(CompOpc, dl, MVT::i32),
10691 DAG.getRegister(PPC::CR6, MVT::i32),
10692 N->getOperand(4), CompNode.getValue(1));
10702 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10704 std::vector<SDNode *> *Created) const {
10705 // fold (sdiv X, pow2)
10706 EVT VT = N->getValueType(0);
10707 if (VT == MVT::i64 && !Subtarget.isPPC64())
10709 if ((VT != MVT::i32 && VT != MVT::i64) ||
10710 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10714 SDValue N0 = N->getOperand(0);
10716 bool IsNegPow2 = (-Divisor).isPowerOf2();
10717 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10718 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10720 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10722 Created->push_back(Op.getNode());
10725 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10727 Created->push_back(Op.getNode());
10733 //===----------------------------------------------------------------------===//
10734 // Inline Assembly Support
10735 //===----------------------------------------------------------------------===//
10737 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10740 const SelectionDAG &DAG,
10741 unsigned Depth) const {
10742 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10743 switch (Op.getOpcode()) {
10745 case PPCISD::LBRX: {
10746 // lhbrx is known to have the top bits cleared out.
10747 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10748 KnownZero = 0xFFFF0000;
10751 case ISD::INTRINSIC_WO_CHAIN: {
10752 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10754 case Intrinsic::ppc_altivec_vcmpbfp_p:
10755 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10756 case Intrinsic::ppc_altivec_vcmpequb_p:
10757 case Intrinsic::ppc_altivec_vcmpequh_p:
10758 case Intrinsic::ppc_altivec_vcmpequw_p:
10759 case Intrinsic::ppc_altivec_vcmpequd_p:
10760 case Intrinsic::ppc_altivec_vcmpgefp_p:
10761 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10762 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10763 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10764 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10765 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10766 case Intrinsic::ppc_altivec_vcmpgtub_p:
10767 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10768 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10769 case Intrinsic::ppc_altivec_vcmpgtud_p:
10770 KnownZero = ~1U; // All bits but the low one are known to be zero.
10777 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10778 switch (Subtarget.getDarwinDirective()) {
10781 case PPC::DIR_PWR4:
10782 case PPC::DIR_PWR5:
10783 case PPC::DIR_PWR5X:
10784 case PPC::DIR_PWR6:
10785 case PPC::DIR_PWR6X:
10786 case PPC::DIR_PWR7:
10787 case PPC::DIR_PWR8: {
10791 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10793 // For small loops (between 5 and 8 instructions), align to a 32-byte
10794 // boundary so that the entire loop fits in one instruction-cache line.
10795 uint64_t LoopSize = 0;
10796 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10797 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10798 LoopSize += TII->GetInstSizeInBytes(J);
10800 if (LoopSize > 16 && LoopSize <= 32)
10807 return TargetLowering::getPrefLoopAlignment(ML);
10810 /// getConstraintType - Given a constraint, return the type of
10811 /// constraint it is for this target.
10812 PPCTargetLowering::ConstraintType
10813 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10814 if (Constraint.size() == 1) {
10815 switch (Constraint[0]) {
10822 return C_RegisterClass;
10824 // FIXME: While Z does indicate a memory constraint, it specifically
10825 // indicates an r+r address (used in conjunction with the 'y' modifier
10826 // in the replacement string). Currently, we're forcing the base
10827 // register to be r0 in the asm printer (which is interpreted as zero)
10828 // and forming the complete address in the second register. This is
10832 } else if (Constraint == "wc") { // individual CR bits.
10833 return C_RegisterClass;
10834 } else if (Constraint == "wa" || Constraint == "wd" ||
10835 Constraint == "wf" || Constraint == "ws") {
10836 return C_RegisterClass; // VSX registers.
10838 return TargetLowering::getConstraintType(Constraint);
10841 /// Examine constraint type and operand type and determine a weight value.
10842 /// This object must already have been set up with the operand type
10843 /// and the current alternative constraint selected.
10844 TargetLowering::ConstraintWeight
10845 PPCTargetLowering::getSingleConstraintMatchWeight(
10846 AsmOperandInfo &info, const char *constraint) const {
10847 ConstraintWeight weight = CW_Invalid;
10848 Value *CallOperandVal = info.CallOperandVal;
10849 // If we don't have a value, we can't do a match,
10850 // but allow it at the lowest weight.
10851 if (!CallOperandVal)
10853 Type *type = CallOperandVal->getType();
10855 // Look at the constraint type.
10856 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10857 return CW_Register; // an individual CR bit.
10858 else if ((StringRef(constraint) == "wa" ||
10859 StringRef(constraint) == "wd" ||
10860 StringRef(constraint) == "wf") &&
10861 type->isVectorTy())
10862 return CW_Register;
10863 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10864 return CW_Register;
10866 switch (*constraint) {
10868 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10871 if (type->isIntegerTy())
10872 weight = CW_Register;
10875 if (type->isFloatTy())
10876 weight = CW_Register;
10879 if (type->isDoubleTy())
10880 weight = CW_Register;
10883 if (type->isVectorTy())
10884 weight = CW_Register;
10887 weight = CW_Register;
10890 weight = CW_Memory;
10896 std::pair<unsigned, const TargetRegisterClass *>
10897 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10898 StringRef Constraint,
10900 if (Constraint.size() == 1) {
10901 // GCC RS6000 Constraint Letters
10902 switch (Constraint[0]) {
10903 case 'b': // R1-R31
10904 if (VT == MVT::i64 && Subtarget.isPPC64())
10905 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10906 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10907 case 'r': // R0-R31
10908 if (VT == MVT::i64 && Subtarget.isPPC64())
10909 return std::make_pair(0U, &PPC::G8RCRegClass);
10910 return std::make_pair(0U, &PPC::GPRCRegClass);
10912 if (VT == MVT::f32 || VT == MVT::i32)
10913 return std::make_pair(0U, &PPC::F4RCRegClass);
10914 if (VT == MVT::f64 || VT == MVT::i64)
10915 return std::make_pair(0U, &PPC::F8RCRegClass);
10916 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10917 return std::make_pair(0U, &PPC::QFRCRegClass);
10918 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10919 return std::make_pair(0U, &PPC::QSRCRegClass);
10922 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10923 return std::make_pair(0U, &PPC::QFRCRegClass);
10924 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10925 return std::make_pair(0U, &PPC::QSRCRegClass);
10926 return std::make_pair(0U, &PPC::VRRCRegClass);
10928 return std::make_pair(0U, &PPC::CRRCRegClass);
10930 } else if (Constraint == "wc" && Subtarget.useCRBits()) {
10931 // An individual CR bit.
10932 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10933 } else if (Constraint == "wa" || Constraint == "wd" ||
10934 Constraint == "wf") {
10935 return std::make_pair(0U, &PPC::VSRCRegClass);
10936 } else if (Constraint == "ws") {
10937 if (VT == MVT::f32)
10938 return std::make_pair(0U, &PPC::VSSRCRegClass);
10940 return std::make_pair(0U, &PPC::VSFRCRegClass);
10943 std::pair<unsigned, const TargetRegisterClass *> R =
10944 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10946 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10947 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10948 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10950 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10951 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10952 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10953 PPC::GPRCRegClass.contains(R.first))
10954 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10955 PPC::sub_32, &PPC::G8RCRegClass),
10956 &PPC::G8RCRegClass);
10958 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10959 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10960 R.first = PPC::CR0;
10961 R.second = &PPC::CRRCRegClass;
10967 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10968 /// vector. If it is invalid, don't add anything to Ops.
10969 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10970 std::string &Constraint,
10971 std::vector<SDValue>&Ops,
10972 SelectionDAG &DAG) const {
10975 // Only support length 1 constraints.
10976 if (Constraint.length() > 1) return;
10978 char Letter = Constraint[0];
10989 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10990 if (!CST) return; // Must be an immediate to match.
10992 int64_t Value = CST->getSExtValue();
10993 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10994 // numbers are printed as such.
10996 default: llvm_unreachable("Unknown constraint letter!");
10997 case 'I': // "I" is a signed 16-bit constant.
10998 if (isInt<16>(Value))
10999 Result = DAG.getTargetConstant(Value, dl, TCVT);
11001 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
11002 if (isShiftedUInt<16, 16>(Value))
11003 Result = DAG.getTargetConstant(Value, dl, TCVT);
11005 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
11006 if (isShiftedInt<16, 16>(Value))
11007 Result = DAG.getTargetConstant(Value, dl, TCVT);
11009 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
11010 if (isUInt<16>(Value))
11011 Result = DAG.getTargetConstant(Value, dl, TCVT);
11013 case 'M': // "M" is a constant that is greater than 31.
11015 Result = DAG.getTargetConstant(Value, dl, TCVT);
11017 case 'N': // "N" is a positive constant that is an exact power of two.
11018 if (Value > 0 && isPowerOf2_64(Value))
11019 Result = DAG.getTargetConstant(Value, dl, TCVT);
11021 case 'O': // "O" is the constant zero.
11023 Result = DAG.getTargetConstant(Value, dl, TCVT);
11025 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
11026 if (isInt<16>(-Value))
11027 Result = DAG.getTargetConstant(Value, dl, TCVT);
11034 if (Result.getNode()) {
11035 Ops.push_back(Result);
11039 // Handle standard constraint letters.
11040 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11043 // isLegalAddressingMode - Return true if the addressing mode represented
11044 // by AM is legal for this target, for a load/store of the specified type.
11045 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
11046 const AddrMode &AM, Type *Ty,
11047 unsigned AS) const {
11048 // PPC does not allow r+i addressing modes for vectors!
11049 if (Ty->isVectorTy() && AM.BaseOffs != 0)
11052 // PPC allows a sign-extended 16-bit immediate field.
11053 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
11056 // No global is ever allowed as a base.
11060 // PPC only support r+r,
11061 switch (AM.Scale) {
11062 case 0: // "r+i" or just "i", depending on HasBaseReg.
11065 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
11067 // Otherwise we have r+r or r+i.
11070 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
11072 // Allow 2*r as r+r.
11075 // No other scales are supported.
11082 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
11083 SelectionDAG &DAG) const {
11084 MachineFunction &MF = DAG.getMachineFunction();
11085 MachineFrameInfo *MFI = MF.getFrameInfo();
11086 MFI->setReturnAddressIsTaken(true);
11088 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
11092 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11094 // Make sure the function does not optimize away the store of the RA to
11096 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
11097 FuncInfo->setLRStoreRequired();
11098 bool isPPC64 = Subtarget.isPPC64();
11099 auto PtrVT = getPointerTy(MF.getDataLayout());
11102 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11104 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
11105 isPPC64 ? MVT::i64 : MVT::i32);
11106 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11107 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
11108 MachinePointerInfo(), false, false, false, 0);
11111 // Just load the return address off the stack.
11112 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
11113 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
11114 MachinePointerInfo(), false, false, false, 0);
11117 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
11118 SelectionDAG &DAG) const {
11120 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11122 MachineFunction &MF = DAG.getMachineFunction();
11123 MachineFrameInfo *MFI = MF.getFrameInfo();
11124 MFI->setFrameAddressIsTaken(true);
11126 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
11127 bool isPPC64 = PtrVT == MVT::i64;
11129 // Naked functions never have a frame pointer, and so we use r1. For all
11130 // other functions, this decision must be delayed until during PEI.
11132 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11133 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11135 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11137 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11140 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11141 FrameAddr, MachinePointerInfo(), false, false,
11146 // FIXME? Maybe this could be a TableGen attribute on some registers and
11147 // this table could be generated automatically from RegInfo.
11148 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
11149 SelectionDAG &DAG) const {
11150 bool isPPC64 = Subtarget.isPPC64();
11151 bool isDarwinABI = Subtarget.isDarwinABI();
11153 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11154 (!isPPC64 && VT != MVT::i32))
11155 report_fatal_error("Invalid register global variable type");
11157 bool is64Bit = isPPC64 && VT == MVT::i64;
11158 unsigned Reg = StringSwitch<unsigned>(RegName)
11159 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11160 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11161 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11162 (is64Bit ? PPC::X13 : PPC::R13))
11167 report_fatal_error("Invalid register name global variable");
11171 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11172 // The PowerPC target isn't yet aware of offsets.
11176 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11178 unsigned Intrinsic) const {
11180 switch (Intrinsic) {
11181 case Intrinsic::ppc_qpx_qvlfd:
11182 case Intrinsic::ppc_qpx_qvlfs:
11183 case Intrinsic::ppc_qpx_qvlfcd:
11184 case Intrinsic::ppc_qpx_qvlfcs:
11185 case Intrinsic::ppc_qpx_qvlfiwa:
11186 case Intrinsic::ppc_qpx_qvlfiwz:
11187 case Intrinsic::ppc_altivec_lvx:
11188 case Intrinsic::ppc_altivec_lvxl:
11189 case Intrinsic::ppc_altivec_lvebx:
11190 case Intrinsic::ppc_altivec_lvehx:
11191 case Intrinsic::ppc_altivec_lvewx:
11192 case Intrinsic::ppc_vsx_lxvd2x:
11193 case Intrinsic::ppc_vsx_lxvw4x: {
11195 switch (Intrinsic) {
11196 case Intrinsic::ppc_altivec_lvebx:
11199 case Intrinsic::ppc_altivec_lvehx:
11202 case Intrinsic::ppc_altivec_lvewx:
11205 case Intrinsic::ppc_vsx_lxvd2x:
11208 case Intrinsic::ppc_qpx_qvlfd:
11211 case Intrinsic::ppc_qpx_qvlfs:
11214 case Intrinsic::ppc_qpx_qvlfcd:
11217 case Intrinsic::ppc_qpx_qvlfcs:
11225 Info.opc = ISD::INTRINSIC_W_CHAIN;
11227 Info.ptrVal = I.getArgOperand(0);
11228 Info.offset = -VT.getStoreSize()+1;
11229 Info.size = 2*VT.getStoreSize()-1;
11232 Info.readMem = true;
11233 Info.writeMem = false;
11236 case Intrinsic::ppc_qpx_qvlfda:
11237 case Intrinsic::ppc_qpx_qvlfsa:
11238 case Intrinsic::ppc_qpx_qvlfcda:
11239 case Intrinsic::ppc_qpx_qvlfcsa:
11240 case Intrinsic::ppc_qpx_qvlfiwaa:
11241 case Intrinsic::ppc_qpx_qvlfiwza: {
11243 switch (Intrinsic) {
11244 case Intrinsic::ppc_qpx_qvlfda:
11247 case Intrinsic::ppc_qpx_qvlfsa:
11250 case Intrinsic::ppc_qpx_qvlfcda:
11253 case Intrinsic::ppc_qpx_qvlfcsa:
11261 Info.opc = ISD::INTRINSIC_W_CHAIN;
11263 Info.ptrVal = I.getArgOperand(0);
11265 Info.size = VT.getStoreSize();
11268 Info.readMem = true;
11269 Info.writeMem = false;
11272 case Intrinsic::ppc_qpx_qvstfd:
11273 case Intrinsic::ppc_qpx_qvstfs:
11274 case Intrinsic::ppc_qpx_qvstfcd:
11275 case Intrinsic::ppc_qpx_qvstfcs:
11276 case Intrinsic::ppc_qpx_qvstfiw:
11277 case Intrinsic::ppc_altivec_stvx:
11278 case Intrinsic::ppc_altivec_stvxl:
11279 case Intrinsic::ppc_altivec_stvebx:
11280 case Intrinsic::ppc_altivec_stvehx:
11281 case Intrinsic::ppc_altivec_stvewx:
11282 case Intrinsic::ppc_vsx_stxvd2x:
11283 case Intrinsic::ppc_vsx_stxvw4x: {
11285 switch (Intrinsic) {
11286 case Intrinsic::ppc_altivec_stvebx:
11289 case Intrinsic::ppc_altivec_stvehx:
11292 case Intrinsic::ppc_altivec_stvewx:
11295 case Intrinsic::ppc_vsx_stxvd2x:
11298 case Intrinsic::ppc_qpx_qvstfd:
11301 case Intrinsic::ppc_qpx_qvstfs:
11304 case Intrinsic::ppc_qpx_qvstfcd:
11307 case Intrinsic::ppc_qpx_qvstfcs:
11315 Info.opc = ISD::INTRINSIC_VOID;
11317 Info.ptrVal = I.getArgOperand(1);
11318 Info.offset = -VT.getStoreSize()+1;
11319 Info.size = 2*VT.getStoreSize()-1;
11322 Info.readMem = false;
11323 Info.writeMem = true;
11326 case Intrinsic::ppc_qpx_qvstfda:
11327 case Intrinsic::ppc_qpx_qvstfsa:
11328 case Intrinsic::ppc_qpx_qvstfcda:
11329 case Intrinsic::ppc_qpx_qvstfcsa:
11330 case Intrinsic::ppc_qpx_qvstfiwa: {
11332 switch (Intrinsic) {
11333 case Intrinsic::ppc_qpx_qvstfda:
11336 case Intrinsic::ppc_qpx_qvstfsa:
11339 case Intrinsic::ppc_qpx_qvstfcda:
11342 case Intrinsic::ppc_qpx_qvstfcsa:
11350 Info.opc = ISD::INTRINSIC_VOID;
11352 Info.ptrVal = I.getArgOperand(1);
11354 Info.size = VT.getStoreSize();
11357 Info.readMem = false;
11358 Info.writeMem = true;
11368 /// getOptimalMemOpType - Returns the target specific optimal type for load
11369 /// and store operations as a result of memset, memcpy, and memmove
11370 /// lowering. If DstAlign is zero that means it's safe to destination
11371 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11372 /// means there isn't a need to check it against alignment requirement,
11373 /// probably because the source does not need to be loaded. If 'IsMemset' is
11374 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11375 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11376 /// source is constant so it does not need to be loaded.
11377 /// It returns EVT::Other if the type should be determined using generic
11378 /// target-independent logic.
11379 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11380 unsigned DstAlign, unsigned SrcAlign,
11381 bool IsMemset, bool ZeroMemset,
11383 MachineFunction &MF) const {
11384 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11385 const Function *F = MF.getFunction();
11386 // When expanding a memset, require at least two QPX instructions to cover
11387 // the cost of loading the value to be stored from the constant pool.
11388 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11389 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11390 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11394 // We should use Altivec/VSX loads and stores when available. For unaligned
11395 // addresses, unaligned VSX loads are only fast starting with the P8.
11396 if (Subtarget.hasAltivec() && Size >= 16 &&
11397 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11398 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11402 if (Subtarget.isPPC64()) {
11409 /// \brief Returns true if it is beneficial to convert a load of a constant
11410 /// to just the constant itself.
11411 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11413 assert(Ty->isIntegerTy());
11415 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11416 if (BitSize == 0 || BitSize > 64)
11421 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11422 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11424 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11425 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11426 return NumBits1 == 64 && NumBits2 == 32;
11429 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11430 if (!VT1.isInteger() || !VT2.isInteger())
11432 unsigned NumBits1 = VT1.getSizeInBits();
11433 unsigned NumBits2 = VT2.getSizeInBits();
11434 return NumBits1 == 64 && NumBits2 == 32;
11437 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11438 // Generally speaking, zexts are not free, but they are free when they can be
11439 // folded with other operations.
11440 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11441 EVT MemVT = LD->getMemoryVT();
11442 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11443 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11444 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11445 LD->getExtensionType() == ISD::ZEXTLOAD))
11449 // FIXME: Add other cases...
11450 // - 32-bit shifts with a zext to i64
11451 // - zext after ctlz, bswap, etc.
11452 // - zext after and by a constant mask
11454 return TargetLowering::isZExtFree(Val, VT2);
11457 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11458 assert(VT.isFloatingPoint());
11462 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11463 return isInt<16>(Imm) || isUInt<16>(Imm);
11466 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11467 return isInt<16>(Imm) || isUInt<16>(Imm);
11470 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11473 bool *Fast) const {
11474 if (DisablePPCUnaligned)
11477 // PowerPC supports unaligned memory access for simple non-vector types.
11478 // Although accessing unaligned addresses is not as efficient as accessing
11479 // aligned addresses, it is generally more efficient than manual expansion,
11480 // and generally only traps for software emulation when crossing page
11483 if (!VT.isSimple())
11486 if (VT.getSimpleVT().isVector()) {
11487 if (Subtarget.hasVSX()) {
11488 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11489 VT != MVT::v4f32 && VT != MVT::v4i32)
11496 if (VT == MVT::ppcf128)
11505 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11506 VT = VT.getScalarType();
11508 if (!VT.isSimple())
11511 switch (VT.getSimpleVT().SimpleTy) {
11523 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11524 // LR is a callee-save register, but we must treat it as clobbered by any call
11525 // site. Hence we include LR in the scratch registers, which are in turn added
11526 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11527 // to CTR, which is used by any indirect call.
11528 static const MCPhysReg ScratchRegs[] = {
11529 PPC::X12, PPC::LR8, PPC::CTR8, 0
11532 return ScratchRegs;
11536 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11537 EVT VT , unsigned DefinedValues) const {
11538 if (VT == MVT::v2i64)
11539 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
11541 if (Subtarget.hasQPX()) {
11542 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11546 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11549 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11550 if (DisableILPPref || Subtarget.enableMachineScheduler())
11551 return TargetLowering::getSchedulingPreference(N);
11556 // Create a fast isel object.
11558 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11559 const TargetLibraryInfo *LibInfo) const {
11560 return PPC::createFastISel(FuncInfo, LibInfo);