1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 // FIXME: Remove this once soft-float is supported.
43 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
44 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
47 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
49 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
50 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
52 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
53 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
55 // FIXME: Remove this once the bug has been fixed!
56 extern cl::opt<bool> ANDIGlueBug;
58 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
59 // If it isn't a Mach-O file then it's going to be a linux ELF
62 return new TargetLoweringObjectFileMachO();
64 return new PPC64LinuxTargetObjectFile();
67 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
68 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
69 Subtarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
77 // arguments are at least 4/8 bytes aligned.
78 bool isPPC64 = Subtarget.isPPC64();
79 setMinStackArgumentAlignment(isPPC64 ? 8:4);
81 // Set up the register classes.
82 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
83 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
84 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
86 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
90 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
92 // PowerPC has pre-inc load and store's.
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
102 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
104 if (Subtarget.useCRBits()) {
105 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
107 if (isPPC64 || Subtarget.hasFPCVT()) {
108 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
109 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
110 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
112 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
113 isPPC64 ? MVT::i64 : MVT::i32);
115 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
116 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
119 // PowerPC does not support direct load / store of condition registers
120 setOperationAction(ISD::LOAD, MVT::i1, Custom);
121 setOperationAction(ISD::STORE, MVT::i1, Custom);
123 // FIXME: Remove this once the ANDI glue bug is fixed:
125 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
127 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
128 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
129 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
130 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
131 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
132 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
134 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
137 // This is used in the ppcf128->int sequence. Note it has different semantics
138 // from FP_ROUND: that rounds to nearest, this rounds to zero.
139 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
141 // We do not currently implement these libm ops for PowerPC.
142 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
145 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
146 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
147 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
149 // PowerPC has no SREM/UREM instructions
150 setOperationAction(ISD::SREM, MVT::i32, Expand);
151 setOperationAction(ISD::UREM, MVT::i32, Expand);
152 setOperationAction(ISD::SREM, MVT::i64, Expand);
153 setOperationAction(ISD::UREM, MVT::i64, Expand);
155 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
156 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
157 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
158 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
159 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
160 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
161 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
162 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
163 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
165 // We don't support sin/cos/sqrt/fmod/pow
166 setOperationAction(ISD::FSIN , MVT::f64, Expand);
167 setOperationAction(ISD::FCOS , MVT::f64, Expand);
168 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
169 setOperationAction(ISD::FREM , MVT::f64, Expand);
170 setOperationAction(ISD::FPOW , MVT::f64, Expand);
171 setOperationAction(ISD::FMA , MVT::f64, Legal);
172 setOperationAction(ISD::FSIN , MVT::f32, Expand);
173 setOperationAction(ISD::FCOS , MVT::f32, Expand);
174 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
175 setOperationAction(ISD::FREM , MVT::f32, Expand);
176 setOperationAction(ISD::FPOW , MVT::f32, Expand);
177 setOperationAction(ISD::FMA , MVT::f32, Legal);
179 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
181 // If we're enabling GP optimizations, use hardware square root
182 if (!Subtarget.hasFSQRT() &&
183 !(TM.Options.UnsafeFPMath &&
184 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
185 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
187 if (!Subtarget.hasFSQRT() &&
188 !(TM.Options.UnsafeFPMath &&
189 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
190 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
192 if (Subtarget.hasFCPSGN()) {
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
196 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
197 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
200 if (Subtarget.hasFPRND()) {
201 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
202 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
203 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
204 setOperationAction(ISD::FROUND, MVT::f64, Legal);
206 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
207 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
208 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
209 setOperationAction(ISD::FROUND, MVT::f32, Legal);
212 // PowerPC does not have BSWAP, CTPOP or CTTZ
213 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
217 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
218 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
219 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
220 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
222 if (Subtarget.hasPOPCNTD()) {
223 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
226 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
227 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
230 // PowerPC does not have ROTR
231 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
232 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
234 if (!Subtarget.useCRBits()) {
235 // PowerPC does not have Select
236 setOperationAction(ISD::SELECT, MVT::i32, Expand);
237 setOperationAction(ISD::SELECT, MVT::i64, Expand);
238 setOperationAction(ISD::SELECT, MVT::f32, Expand);
239 setOperationAction(ISD::SELECT, MVT::f64, Expand);
242 // PowerPC wants to turn select_cc of FP into fsel when possible.
243 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
244 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
246 // PowerPC wants to optimize integer setcc a bit
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::SETCC, MVT::i32, Custom);
250 // PowerPC does not have BRCOND which requires SetCC
251 if (!Subtarget.useCRBits())
252 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
254 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
256 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
257 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
259 // PowerPC does not have [U|S]INT_TO_FP
260 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
261 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
264 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
265 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
266 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
268 // We cannot sextinreg(i1). Expand to shifts.
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
271 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
272 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
273 // support continuation, user-level threading, and etc.. As a result, no
274 // other SjLj exception interfaces are implemented and please don't build
275 // your own exception handling based on them.
276 // LLVM/Clang supports zero-cost DWARF exception handling.
277 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
278 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
280 // We want to legalize GlobalAddress and ConstantPool nodes into the
281 // appropriate instructions to materialize the address.
282 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
284 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
285 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
286 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
287 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
288 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
289 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
290 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
291 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
294 setOperationAction(ISD::TRAP, MVT::Other, Legal);
296 // TRAMPOLINE is custom lowered.
297 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
298 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
300 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
301 setOperationAction(ISD::VASTART , MVT::Other, Custom);
303 if (Subtarget.isSVR4ABI()) {
305 // VAARG always uses double-word chunks, so promote anything smaller.
306 setOperationAction(ISD::VAARG, MVT::i1, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i8, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::i16, Promote);
311 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
312 setOperationAction(ISD::VAARG, MVT::i32, Promote);
313 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
314 setOperationAction(ISD::VAARG, MVT::Other, Expand);
316 // VAARG is custom lowered with the 32-bit SVR4 ABI.
317 setOperationAction(ISD::VAARG, MVT::Other, Custom);
318 setOperationAction(ISD::VAARG, MVT::i64, Custom);
321 setOperationAction(ISD::VAARG, MVT::Other, Expand);
323 if (Subtarget.isSVR4ABI() && !isPPC64)
324 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
325 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
327 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
329 // Use the default implementation.
330 setOperationAction(ISD::VAEND , MVT::Other, Expand);
331 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
332 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
333 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
334 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
336 // We want to custom lower some of our intrinsics.
337 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
339 // To handle counter-based loop conditions.
340 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
342 // Comparisons that require checking two conditions.
343 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
351 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
352 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
353 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
354 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
356 if (Subtarget.has64BitSupport()) {
357 // They also have instructions for converting between i64 and fp.
358 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
359 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
360 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
361 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
362 // This is just the low 32 bits of a (signed) fp->i64 conversion.
363 // We cannot do this with Promote because i64 is not a legal type.
364 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
366 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
367 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
369 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
370 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
373 // With the instructions enabled under FPCVT, we can do everything.
374 if (Subtarget.hasFPCVT()) {
375 if (Subtarget.has64BitSupport()) {
376 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
377 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
378 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
382 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
383 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
384 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
385 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
388 if (Subtarget.use64BitRegs()) {
389 // 64-bit PowerPC implementations can support i64 types directly
390 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
391 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
392 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
393 // 64-bit PowerPC wants to expand i128 shifts itself.
394 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
395 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
396 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
398 // 32-bit PowerPC wants to expand i64 shifts itself.
399 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
400 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
401 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
404 if (Subtarget.hasAltivec()) {
405 // First set operation action for all vector types to expand. Then we
406 // will selectively turn on ones that can be effectively codegen'd.
407 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
408 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
409 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
411 // add/sub are legal for all supported vector VT's.
412 setOperationAction(ISD::ADD , VT, Legal);
413 setOperationAction(ISD::SUB , VT, Legal);
415 // We promote all shuffles to v16i8.
416 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
417 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
419 // We promote all non-typed operations to v4i32.
420 setOperationAction(ISD::AND , VT, Promote);
421 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
422 setOperationAction(ISD::OR , VT, Promote);
423 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
424 setOperationAction(ISD::XOR , VT, Promote);
425 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
426 setOperationAction(ISD::LOAD , VT, Promote);
427 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
428 setOperationAction(ISD::SELECT, VT, Promote);
429 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
430 setOperationAction(ISD::STORE, VT, Promote);
431 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
433 // No other operations are legal.
434 setOperationAction(ISD::MUL , VT, Expand);
435 setOperationAction(ISD::SDIV, VT, Expand);
436 setOperationAction(ISD::SREM, VT, Expand);
437 setOperationAction(ISD::UDIV, VT, Expand);
438 setOperationAction(ISD::UREM, VT, Expand);
439 setOperationAction(ISD::FDIV, VT, Expand);
440 setOperationAction(ISD::FREM, VT, Expand);
441 setOperationAction(ISD::FNEG, VT, Expand);
442 setOperationAction(ISD::FSQRT, VT, Expand);
443 setOperationAction(ISD::FLOG, VT, Expand);
444 setOperationAction(ISD::FLOG10, VT, Expand);
445 setOperationAction(ISD::FLOG2, VT, Expand);
446 setOperationAction(ISD::FEXP, VT, Expand);
447 setOperationAction(ISD::FEXP2, VT, Expand);
448 setOperationAction(ISD::FSIN, VT, Expand);
449 setOperationAction(ISD::FCOS, VT, Expand);
450 setOperationAction(ISD::FABS, VT, Expand);
451 setOperationAction(ISD::FPOWI, VT, Expand);
452 setOperationAction(ISD::FFLOOR, VT, Expand);
453 setOperationAction(ISD::FCEIL, VT, Expand);
454 setOperationAction(ISD::FTRUNC, VT, Expand);
455 setOperationAction(ISD::FRINT, VT, Expand);
456 setOperationAction(ISD::FNEARBYINT, VT, Expand);
457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
458 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
459 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
460 setOperationAction(ISD::MULHU, VT, Expand);
461 setOperationAction(ISD::MULHS, VT, Expand);
462 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
463 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
464 setOperationAction(ISD::UDIVREM, VT, Expand);
465 setOperationAction(ISD::SDIVREM, VT, Expand);
466 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
467 setOperationAction(ISD::FPOW, VT, Expand);
468 setOperationAction(ISD::BSWAP, VT, Expand);
469 setOperationAction(ISD::CTPOP, VT, Expand);
470 setOperationAction(ISD::CTLZ, VT, Expand);
471 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
472 setOperationAction(ISD::CTTZ, VT, Expand);
473 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
474 setOperationAction(ISD::VSELECT, VT, Expand);
475 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
477 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
478 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
479 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
480 setTruncStoreAction(VT, InnerVT, Expand);
482 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
483 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
484 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
487 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
488 // with merges, splats, etc.
489 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
491 setOperationAction(ISD::AND , MVT::v4i32, Legal);
492 setOperationAction(ISD::OR , MVT::v4i32, Legal);
493 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
494 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
495 setOperationAction(ISD::SELECT, MVT::v4i32,
496 Subtarget.useCRBits() ? Legal : Expand);
497 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
500 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
501 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
502 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
503 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
504 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
505 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
507 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
508 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
509 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
512 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
513 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
515 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
516 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
517 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
520 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
521 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
522 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
524 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
525 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
527 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
528 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
529 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
530 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
532 // Altivec does not contain unordered floating-point compare instructions
533 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
536 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
538 if (Subtarget.hasVSX()) {
539 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
540 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
542 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
543 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
544 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
545 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
546 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
548 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
550 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
551 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
553 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
554 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
560 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
562 // Share the Altivec comparison restrictions.
563 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
568 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
569 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
571 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
573 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
575 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
576 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
578 // VSX v2i64 only supports non-arithmetic operations.
579 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
580 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
582 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
583 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
584 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
586 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
588 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
589 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
590 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
591 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
593 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
595 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
596 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
597 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
598 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
600 // Vector operation legalization checks the result type of
601 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
602 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
603 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
604 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
605 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
607 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
611 if (Subtarget.has64BitSupport()) {
612 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
613 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
617 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
618 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
621 setBooleanContents(ZeroOrOneBooleanContent);
622 // Altivec instructions set fields to all zeros or all ones.
623 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
626 // These libcalls are not available in 32-bit.
627 setLibcallName(RTLIB::SHL_I128, nullptr);
628 setLibcallName(RTLIB::SRL_I128, nullptr);
629 setLibcallName(RTLIB::SRA_I128, nullptr);
633 setStackPointerRegisterToSaveRestore(PPC::X1);
634 setExceptionPointerRegister(PPC::X3);
635 setExceptionSelectorRegister(PPC::X4);
637 setStackPointerRegisterToSaveRestore(PPC::R1);
638 setExceptionPointerRegister(PPC::R3);
639 setExceptionSelectorRegister(PPC::R4);
642 // We have target-specific dag combine patterns for the following nodes:
643 setTargetDAGCombine(ISD::SINT_TO_FP);
644 setTargetDAGCombine(ISD::LOAD);
645 setTargetDAGCombine(ISD::STORE);
646 setTargetDAGCombine(ISD::BR_CC);
647 if (Subtarget.useCRBits())
648 setTargetDAGCombine(ISD::BRCOND);
649 setTargetDAGCombine(ISD::BSWAP);
650 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
652 setTargetDAGCombine(ISD::SIGN_EXTEND);
653 setTargetDAGCombine(ISD::ZERO_EXTEND);
654 setTargetDAGCombine(ISD::ANY_EXTEND);
656 if (Subtarget.useCRBits()) {
657 setTargetDAGCombine(ISD::TRUNCATE);
658 setTargetDAGCombine(ISD::SETCC);
659 setTargetDAGCombine(ISD::SELECT_CC);
662 // Use reciprocal estimates.
663 if (TM.Options.UnsafeFPMath) {
664 setTargetDAGCombine(ISD::FDIV);
665 setTargetDAGCombine(ISD::FSQRT);
668 // Darwin long double math library functions have $LDBL128 appended.
669 if (Subtarget.isDarwin()) {
670 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
671 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
672 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
673 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
674 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
675 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
676 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
677 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
678 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
679 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
682 // With 32 condition bits, we don't need to sink (and duplicate) compares
683 // aggressively in CodeGenPrep.
684 if (Subtarget.useCRBits())
685 setHasMultipleConditionRegisters();
687 setMinFunctionAlignment(2);
688 if (Subtarget.isDarwin())
689 setPrefFunctionAlignment(4);
691 setInsertFencesForAtomic(true);
693 if (Subtarget.enableMachineScheduler())
694 setSchedulingPreference(Sched::Source);
696 setSchedulingPreference(Sched::Hybrid);
698 computeRegisterProperties();
700 // The Freescale cores does better with aggressive inlining of memcpy and
701 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
702 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
703 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
704 MaxStoresPerMemset = 32;
705 MaxStoresPerMemsetOptSize = 16;
706 MaxStoresPerMemcpy = 32;
707 MaxStoresPerMemcpyOptSize = 8;
708 MaxStoresPerMemmove = 32;
709 MaxStoresPerMemmoveOptSize = 8;
711 setPrefFunctionAlignment(4);
715 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
716 /// the desired ByVal argument alignment.
717 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
718 unsigned MaxMaxAlign) {
719 if (MaxAlign == MaxMaxAlign)
721 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
722 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
724 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
726 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
727 unsigned EltAlign = 0;
728 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
729 if (EltAlign > MaxAlign)
731 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
732 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
733 unsigned EltAlign = 0;
734 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
735 if (EltAlign > MaxAlign)
737 if (MaxAlign == MaxMaxAlign)
743 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
744 /// function arguments in the caller parameter area.
745 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
746 // Darwin passes everything on 4 byte boundary.
747 if (Subtarget.isDarwin())
750 // 16byte and wider vectors are passed on 16byte boundary.
751 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
752 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
753 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
754 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
758 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
760 default: return nullptr;
761 case PPCISD::FSEL: return "PPCISD::FSEL";
762 case PPCISD::FCFID: return "PPCISD::FCFID";
763 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
764 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
765 case PPCISD::FRE: return "PPCISD::FRE";
766 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
767 case PPCISD::STFIWX: return "PPCISD::STFIWX";
768 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
769 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
770 case PPCISD::VPERM: return "PPCISD::VPERM";
771 case PPCISD::Hi: return "PPCISD::Hi";
772 case PPCISD::Lo: return "PPCISD::Lo";
773 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
774 case PPCISD::LOAD: return "PPCISD::LOAD";
775 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
776 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
777 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
778 case PPCISD::SRL: return "PPCISD::SRL";
779 case PPCISD::SRA: return "PPCISD::SRA";
780 case PPCISD::SHL: return "PPCISD::SHL";
781 case PPCISD::CALL: return "PPCISD::CALL";
782 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
783 case PPCISD::MTCTR: return "PPCISD::MTCTR";
784 case PPCISD::BCTRL: return "PPCISD::BCTRL";
785 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
786 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
787 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
788 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
789 case PPCISD::VCMP: return "PPCISD::VCMP";
790 case PPCISD::VCMPo: return "PPCISD::VCMPo";
791 case PPCISD::LBRX: return "PPCISD::LBRX";
792 case PPCISD::STBRX: return "PPCISD::STBRX";
793 case PPCISD::LARX: return "PPCISD::LARX";
794 case PPCISD::STCX: return "PPCISD::STCX";
795 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
796 case PPCISD::BDNZ: return "PPCISD::BDNZ";
797 case PPCISD::BDZ: return "PPCISD::BDZ";
798 case PPCISD::MFFS: return "PPCISD::MFFS";
799 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
800 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
801 case PPCISD::CR6SET: return "PPCISD::CR6SET";
802 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
803 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
804 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
805 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
806 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
807 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
808 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
809 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
810 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
811 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
812 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
813 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
814 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
815 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
816 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
817 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
818 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
819 case PPCISD::SC: return "PPCISD::SC";
823 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
825 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
826 return VT.changeVectorElementTypeToInteger();
829 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
830 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
834 //===----------------------------------------------------------------------===//
835 // Node matching predicates, for use by the tblgen matching code.
836 //===----------------------------------------------------------------------===//
838 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
839 static bool isFloatingPointZero(SDValue Op) {
840 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
841 return CFP->getValueAPF().isZero();
842 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
843 // Maybe this has already been legalized into the constant pool?
844 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
845 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
846 return CFP->getValueAPF().isZero();
851 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
852 /// true if Op is undef or if it matches the specified value.
853 static bool isConstantOrUndef(int Op, int Val) {
854 return Op < 0 || Op == Val;
857 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
858 /// VPKUHUM instruction.
859 /// The ShuffleKind distinguishes between big-endian operations with
860 /// two different inputs (0), either-endian operations with two identical
861 /// inputs (1), and little-endian operantion with two different inputs (2).
862 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
863 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
865 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
866 if (ShuffleKind == 0) {
869 for (unsigned i = 0; i != 16; ++i)
870 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
872 } else if (ShuffleKind == 2) {
875 for (unsigned i = 0; i != 16; ++i)
876 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
878 } else if (ShuffleKind == 1) {
879 unsigned j = IsLE ? 0 : 1;
880 for (unsigned i = 0; i != 8; ++i)
881 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
882 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
888 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
889 /// VPKUWUM instruction.
890 /// The ShuffleKind distinguishes between big-endian operations with
891 /// two different inputs (0), either-endian operations with two identical
892 /// inputs (1), and little-endian operantion with two different inputs (2).
893 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
894 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
896 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
897 if (ShuffleKind == 0) {
900 for (unsigned i = 0; i != 16; i += 2)
901 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
902 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
904 } else if (ShuffleKind == 2) {
907 for (unsigned i = 0; i != 16; i += 2)
908 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
909 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
911 } else if (ShuffleKind == 1) {
912 unsigned j = IsLE ? 0 : 2;
913 for (unsigned i = 0; i != 8; i += 2)
914 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
915 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
916 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
917 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
923 /// isVMerge - Common function, used to match vmrg* shuffles.
925 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
926 unsigned LHSStart, unsigned RHSStart) {
927 if (N->getValueType(0) != MVT::v16i8)
929 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
930 "Unsupported merge size!");
932 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
933 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
934 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
935 LHSStart+j+i*UnitSize) ||
936 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
937 RHSStart+j+i*UnitSize))
943 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
944 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
945 /// The ShuffleKind distinguishes between big-endian merges with two
946 /// different inputs (0), either-endian merges with two identical inputs (1),
947 /// and little-endian merges with two different inputs (2). For the latter,
948 /// the input operands are swapped (see PPCInstrAltivec.td).
949 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
950 unsigned ShuffleKind, SelectionDAG &DAG) {
951 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
952 if (ShuffleKind == 1) // unary
953 return isVMerge(N, UnitSize, 0, 0);
954 else if (ShuffleKind == 2) // swapped
955 return isVMerge(N, UnitSize, 0, 16);
959 if (ShuffleKind == 1) // unary
960 return isVMerge(N, UnitSize, 8, 8);
961 else if (ShuffleKind == 0) // normal
962 return isVMerge(N, UnitSize, 8, 24);
968 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
969 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
970 /// The ShuffleKind distinguishes between big-endian merges with two
971 /// different inputs (0), either-endian merges with two identical inputs (1),
972 /// and little-endian merges with two different inputs (2). For the latter,
973 /// the input operands are swapped (see PPCInstrAltivec.td).
974 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
975 unsigned ShuffleKind, SelectionDAG &DAG) {
976 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
977 if (ShuffleKind == 1) // unary
978 return isVMerge(N, UnitSize, 8, 8);
979 else if (ShuffleKind == 2) // swapped
980 return isVMerge(N, UnitSize, 8, 24);
984 if (ShuffleKind == 1) // unary
985 return isVMerge(N, UnitSize, 0, 0);
986 else if (ShuffleKind == 0) // normal
987 return isVMerge(N, UnitSize, 0, 16);
994 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
995 /// amount, otherwise return -1.
996 /// The ShuffleKind distinguishes between big-endian operations with two
997 /// different inputs (0), either-endian operations with two identical inputs
998 /// (1), and little-endian operations with two different inputs (2). For the
999 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1000 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1001 SelectionDAG &DAG) {
1002 if (N->getValueType(0) != MVT::v16i8)
1005 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1007 // Find the first non-undef value in the shuffle mask.
1009 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1012 if (i == 16) return -1; // all undef.
1014 // Otherwise, check to see if the rest of the elements are consecutively
1015 // numbered from this value.
1016 unsigned ShiftAmt = SVOp->getMaskElt(i);
1017 if (ShiftAmt < i) return -1;
1020 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1023 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1024 // Check the rest of the elements to see if they are consecutive.
1025 for (++i; i != 16; ++i)
1026 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1028 } else if (ShuffleKind == 1) {
1029 // Check the rest of the elements to see if they are consecutive.
1030 for (++i; i != 16; ++i)
1031 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1036 if (ShuffleKind == 2 && isLE)
1037 ShiftAmt = 16 - ShiftAmt;
1042 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1043 /// specifies a splat of a single element that is suitable for input to
1044 /// VSPLTB/VSPLTH/VSPLTW.
1045 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1046 assert(N->getValueType(0) == MVT::v16i8 &&
1047 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1049 // This is a splat operation if each element of the permute is the same, and
1050 // if the value doesn't reference the second vector.
1051 unsigned ElementBase = N->getMaskElt(0);
1053 // FIXME: Handle UNDEF elements too!
1054 if (ElementBase >= 16)
1057 // Check that the indices are consecutive, in the case of a multi-byte element
1058 // splatted with a v16i8 mask.
1059 for (unsigned i = 1; i != EltSize; ++i)
1060 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1063 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1064 if (N->getMaskElt(i) < 0) continue;
1065 for (unsigned j = 0; j != EltSize; ++j)
1066 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1072 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1074 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1075 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1077 APInt APVal, APUndef;
1081 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1082 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1083 return CFP->getValueAPF().isNegZero();
1088 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1089 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1090 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1091 SelectionDAG &DAG) {
1092 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1093 assert(isSplatShuffleMask(SVOp, EltSize));
1094 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1095 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1097 return SVOp->getMaskElt(0) / EltSize;
1100 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1101 /// by using a vspltis[bhw] instruction of the specified element size, return
1102 /// the constant being splatted. The ByteSize field indicates the number of
1103 /// bytes of each element [124] -> [bhw].
1104 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1105 SDValue OpVal(nullptr, 0);
1107 // If ByteSize of the splat is bigger than the element size of the
1108 // build_vector, then we have a case where we are checking for a splat where
1109 // multiple elements of the buildvector are folded together into a single
1110 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1111 unsigned EltSize = 16/N->getNumOperands();
1112 if (EltSize < ByteSize) {
1113 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1114 SDValue UniquedVals[4];
1115 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1117 // See if all of the elements in the buildvector agree across.
1118 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1119 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1120 // If the element isn't a constant, bail fully out.
1121 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1124 if (!UniquedVals[i&(Multiple-1)].getNode())
1125 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1126 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1127 return SDValue(); // no match.
1130 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1131 // either constant or undef values that are identical for each chunk. See
1132 // if these chunks can form into a larger vspltis*.
1134 // Check to see if all of the leading entries are either 0 or -1. If
1135 // neither, then this won't fit into the immediate field.
1136 bool LeadingZero = true;
1137 bool LeadingOnes = true;
1138 for (unsigned i = 0; i != Multiple-1; ++i) {
1139 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1141 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1142 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1144 // Finally, check the least significant entry.
1146 if (!UniquedVals[Multiple-1].getNode())
1147 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1148 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1150 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1153 if (!UniquedVals[Multiple-1].getNode())
1154 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1155 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1156 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1157 return DAG.getTargetConstant(Val, MVT::i32);
1163 // Check to see if this buildvec has a single non-undef value in its elements.
1164 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1165 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1166 if (!OpVal.getNode())
1167 OpVal = N->getOperand(i);
1168 else if (OpVal != N->getOperand(i))
1172 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1174 unsigned ValSizeInBytes = EltSize;
1176 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1177 Value = CN->getZExtValue();
1178 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1179 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1180 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1183 // If the splat value is larger than the element value, then we can never do
1184 // this splat. The only case that we could fit the replicated bits into our
1185 // immediate field for would be zero, and we prefer to use vxor for it.
1186 if (ValSizeInBytes < ByteSize) return SDValue();
1188 // If the element value is larger than the splat value, cut it in half and
1189 // check to see if the two halves are equal. Continue doing this until we
1190 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1191 while (ValSizeInBytes > ByteSize) {
1192 ValSizeInBytes >>= 1;
1194 // If the top half equals the bottom half, we're still ok.
1195 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1196 (Value & ((1 << (8*ValSizeInBytes))-1)))
1200 // Properly sign extend the value.
1201 int MaskVal = SignExtend32(Value, ByteSize * 8);
1203 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1204 if (MaskVal == 0) return SDValue();
1206 // Finally, if this value fits in a 5 bit sext field, return it
1207 if (SignExtend32<5>(MaskVal) == MaskVal)
1208 return DAG.getTargetConstant(MaskVal, MVT::i32);
1212 //===----------------------------------------------------------------------===//
1213 // Addressing Mode Selection
1214 //===----------------------------------------------------------------------===//
1216 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1217 /// or 64-bit immediate, and if the value can be accurately represented as a
1218 /// sign extension from a 16-bit value. If so, this returns true and the
1220 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1221 if (!isa<ConstantSDNode>(N))
1224 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1225 if (N->getValueType(0) == MVT::i32)
1226 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1228 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1230 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1231 return isIntS16Immediate(Op.getNode(), Imm);
1235 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1236 /// can be represented as an indexed [r+r] operation. Returns false if it
1237 /// can be more efficiently represented with [r+imm].
1238 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1240 SelectionDAG &DAG) const {
1242 if (N.getOpcode() == ISD::ADD) {
1243 if (isIntS16Immediate(N.getOperand(1), imm))
1244 return false; // r+i
1245 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1246 return false; // r+i
1248 Base = N.getOperand(0);
1249 Index = N.getOperand(1);
1251 } else if (N.getOpcode() == ISD::OR) {
1252 if (isIntS16Immediate(N.getOperand(1), imm))
1253 return false; // r+i can fold it if we can.
1255 // If this is an or of disjoint bitfields, we can codegen this as an add
1256 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1258 APInt LHSKnownZero, LHSKnownOne;
1259 APInt RHSKnownZero, RHSKnownOne;
1260 DAG.computeKnownBits(N.getOperand(0),
1261 LHSKnownZero, LHSKnownOne);
1263 if (LHSKnownZero.getBoolValue()) {
1264 DAG.computeKnownBits(N.getOperand(1),
1265 RHSKnownZero, RHSKnownOne);
1266 // If all of the bits are known zero on the LHS or RHS, the add won't
1268 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1269 Base = N.getOperand(0);
1270 Index = N.getOperand(1);
1279 // If we happen to be doing an i64 load or store into a stack slot that has
1280 // less than a 4-byte alignment, then the frame-index elimination may need to
1281 // use an indexed load or store instruction (because the offset may not be a
1282 // multiple of 4). The extra register needed to hold the offset comes from the
1283 // register scavenger, and it is possible that the scavenger will need to use
1284 // an emergency spill slot. As a result, we need to make sure that a spill slot
1285 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1287 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1288 // FIXME: This does not handle the LWA case.
1292 // NOTE: We'll exclude negative FIs here, which come from argument
1293 // lowering, because there are no known test cases triggering this problem
1294 // using packed structures (or similar). We can remove this exclusion if
1295 // we find such a test case. The reason why this is so test-case driven is
1296 // because this entire 'fixup' is only to prevent crashes (from the
1297 // register scavenger) on not-really-valid inputs. For example, if we have:
1299 // %b = bitcast i1* %a to i64*
1300 // store i64* a, i64 b
1301 // then the store should really be marked as 'align 1', but is not. If it
1302 // were marked as 'align 1' then the indexed form would have been
1303 // instruction-selected initially, and the problem this 'fixup' is preventing
1304 // won't happen regardless.
1308 MachineFunction &MF = DAG.getMachineFunction();
1309 MachineFrameInfo *MFI = MF.getFrameInfo();
1311 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1315 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1316 FuncInfo->setHasNonRISpills();
1319 /// Returns true if the address N can be represented by a base register plus
1320 /// a signed 16-bit displacement [r+imm], and if it is not better
1321 /// represented as reg+reg. If Aligned is true, only accept displacements
1322 /// suitable for STD and friends, i.e. multiples of 4.
1323 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1326 bool Aligned) const {
1327 // FIXME dl should come from parent load or store, not from address
1329 // If this can be more profitably realized as r+r, fail.
1330 if (SelectAddressRegReg(N, Disp, Base, DAG))
1333 if (N.getOpcode() == ISD::ADD) {
1335 if (isIntS16Immediate(N.getOperand(1), imm) &&
1336 (!Aligned || (imm & 3) == 0)) {
1337 Disp = DAG.getTargetConstant(imm, N.getValueType());
1338 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1339 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1340 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1342 Base = N.getOperand(0);
1344 return true; // [r+i]
1345 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1346 // Match LOAD (ADD (X, Lo(G))).
1347 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1348 && "Cannot handle constant offsets yet!");
1349 Disp = N.getOperand(1).getOperand(0); // The global address.
1350 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1351 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1352 Disp.getOpcode() == ISD::TargetConstantPool ||
1353 Disp.getOpcode() == ISD::TargetJumpTable);
1354 Base = N.getOperand(0);
1355 return true; // [&g+r]
1357 } else if (N.getOpcode() == ISD::OR) {
1359 if (isIntS16Immediate(N.getOperand(1), imm) &&
1360 (!Aligned || (imm & 3) == 0)) {
1361 // If this is an or of disjoint bitfields, we can codegen this as an add
1362 // (for better address arithmetic) if the LHS and RHS of the OR are
1363 // provably disjoint.
1364 APInt LHSKnownZero, LHSKnownOne;
1365 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1367 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1368 // If all of the bits are known zero on the LHS or RHS, the add won't
1370 if (FrameIndexSDNode *FI =
1371 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1372 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1373 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1375 Base = N.getOperand(0);
1377 Disp = DAG.getTargetConstant(imm, N.getValueType());
1381 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1382 // Loading from a constant address.
1384 // If this address fits entirely in a 16-bit sext immediate field, codegen
1387 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1388 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1389 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1390 CN->getValueType(0));
1394 // Handle 32-bit sext immediates with LIS + addr mode.
1395 if ((CN->getValueType(0) == MVT::i32 ||
1396 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1397 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1398 int Addr = (int)CN->getZExtValue();
1400 // Otherwise, break this down into an LIS + disp.
1401 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1403 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1404 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1405 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1410 Disp = DAG.getTargetConstant(0, getPointerTy());
1411 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1412 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1413 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1416 return true; // [r+0]
1419 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1420 /// represented as an indexed [r+r] operation.
1421 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1423 SelectionDAG &DAG) const {
1424 // Check to see if we can easily represent this as an [r+r] address. This
1425 // will fail if it thinks that the address is more profitably represented as
1426 // reg+imm, e.g. where imm = 0.
1427 if (SelectAddressRegReg(N, Base, Index, DAG))
1430 // If the operand is an addition, always emit this as [r+r], since this is
1431 // better (for code size, and execution, as the memop does the add for free)
1432 // than emitting an explicit add.
1433 if (N.getOpcode() == ISD::ADD) {
1434 Base = N.getOperand(0);
1435 Index = N.getOperand(1);
1439 // Otherwise, do it the hard way, using R0 as the base register.
1440 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1446 /// getPreIndexedAddressParts - returns true by value, base pointer and
1447 /// offset pointer and addressing mode by reference if the node's address
1448 /// can be legally represented as pre-indexed load / store address.
1449 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1451 ISD::MemIndexedMode &AM,
1452 SelectionDAG &DAG) const {
1453 if (DisablePPCPreinc) return false;
1459 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1460 Ptr = LD->getBasePtr();
1461 VT = LD->getMemoryVT();
1462 Alignment = LD->getAlignment();
1463 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1464 Ptr = ST->getBasePtr();
1465 VT = ST->getMemoryVT();
1466 Alignment = ST->getAlignment();
1471 // PowerPC doesn't have preinc load/store instructions for vectors.
1475 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1477 // Common code will reject creating a pre-inc form if the base pointer
1478 // is a frame index, or if N is a store and the base pointer is either
1479 // the same as or a predecessor of the value being stored. Check for
1480 // those situations here, and try with swapped Base/Offset instead.
1483 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1486 SDValue Val = cast<StoreSDNode>(N)->getValue();
1487 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1492 std::swap(Base, Offset);
1498 // LDU/STU can only handle immediates that are a multiple of 4.
1499 if (VT != MVT::i64) {
1500 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1503 // LDU/STU need an address with at least 4-byte alignment.
1507 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1511 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1512 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1513 // sext i32 to i64 when addr mode is r+i.
1514 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1515 LD->getExtensionType() == ISD::SEXTLOAD &&
1516 isa<ConstantSDNode>(Offset))
1524 //===----------------------------------------------------------------------===//
1525 // LowerOperation implementation
1526 //===----------------------------------------------------------------------===//
1528 /// GetLabelAccessInfo - Return true if we should reference labels using a
1529 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1530 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1531 unsigned &LoOpFlags,
1532 const GlobalValue *GV = nullptr) {
1533 HiOpFlags = PPCII::MO_HA;
1534 LoOpFlags = PPCII::MO_LO;
1536 // Don't use the pic base if not in PIC relocation model.
1537 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1540 HiOpFlags |= PPCII::MO_PIC_FLAG;
1541 LoOpFlags |= PPCII::MO_PIC_FLAG;
1544 // If this is a reference to a global value that requires a non-lazy-ptr, make
1545 // sure that instruction lowering adds it.
1546 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1547 HiOpFlags |= PPCII::MO_NLP_FLAG;
1548 LoOpFlags |= PPCII::MO_NLP_FLAG;
1550 if (GV->hasHiddenVisibility()) {
1551 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1552 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1559 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1560 SelectionDAG &DAG) {
1561 EVT PtrVT = HiPart.getValueType();
1562 SDValue Zero = DAG.getConstant(0, PtrVT);
1565 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1566 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1568 // With PIC, the first instruction is actually "GR+hi(&G)".
1570 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1571 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1573 // Generate non-pic code that has direct accesses to the constant pool.
1574 // The address of the global is just (hi(&g)+lo(&g)).
1575 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1578 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1579 SelectionDAG &DAG) const {
1580 EVT PtrVT = Op.getValueType();
1581 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1582 const Constant *C = CP->getConstVal();
1584 // 64-bit SVR4 ABI code is always position-independent.
1585 // The actual address of the GlobalValue is stored in the TOC.
1586 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1587 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1588 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1589 DAG.getRegister(PPC::X2, MVT::i64));
1592 unsigned MOHiFlag, MOLoFlag;
1593 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1595 if (isPIC && Subtarget.isSVR4ABI()) {
1596 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1597 PPCII::MO_PIC_FLAG);
1599 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1600 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1604 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1606 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1607 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1610 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1611 EVT PtrVT = Op.getValueType();
1612 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1614 // 64-bit SVR4 ABI code is always position-independent.
1615 // The actual address of the GlobalValue is stored in the TOC.
1616 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1617 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1618 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1619 DAG.getRegister(PPC::X2, MVT::i64));
1622 unsigned MOHiFlag, MOLoFlag;
1623 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1625 if (isPIC && Subtarget.isSVR4ABI()) {
1626 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1627 PPCII::MO_PIC_FLAG);
1629 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1630 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1633 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1634 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1635 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1638 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1639 SelectionDAG &DAG) const {
1640 EVT PtrVT = Op.getValueType();
1641 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1642 const BlockAddress *BA = BASDN->getBlockAddress();
1644 // 64-bit SVR4 ABI code is always position-independent.
1645 // The actual BlockAddress is stored in the TOC.
1646 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1647 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1648 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1649 DAG.getRegister(PPC::X2, MVT::i64));
1652 unsigned MOHiFlag, MOLoFlag;
1653 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1654 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1655 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1656 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1659 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1660 SelectionDAG &DAG) const {
1662 // FIXME: TLS addresses currently use medium model code sequences,
1663 // which is the most useful form. Eventually support for small and
1664 // large models could be added if users need it, at the cost of
1665 // additional complexity.
1666 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1668 const GlobalValue *GV = GA->getGlobal();
1669 EVT PtrVT = getPointerTy();
1670 bool is64bit = Subtarget.isPPC64();
1672 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1674 if (Model == TLSModel::LocalExec) {
1675 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1676 PPCII::MO_TPREL_HA);
1677 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1678 PPCII::MO_TPREL_LO);
1679 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1680 is64bit ? MVT::i64 : MVT::i32);
1681 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1682 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1685 if (Model == TLSModel::InitialExec) {
1686 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1687 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1691 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1692 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1693 PtrVT, GOTReg, TGA);
1695 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1696 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1697 PtrVT, TGA, GOTPtr);
1698 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1701 if (Model == TLSModel::GeneralDynamic) {
1702 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1705 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1706 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1709 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1711 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1714 // We need a chain node, and don't have one handy. The underlying
1715 // call has no side effects, so using the function entry node
1717 SDValue Chain = DAG.getEntryNode();
1718 Chain = DAG.getCopyToReg(Chain, dl,
1719 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1720 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1721 is64bit ? MVT::i64 : MVT::i32);
1722 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1723 PtrVT, ParmReg, TGA);
1724 // The return value from GET_TLS_ADDR really is in X3 already, but
1725 // some hacks are needed here to tie everything together. The extra
1726 // copies dissolve during subsequent transforms.
1727 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1728 return DAG.getCopyFromReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, PtrVT);
1731 if (Model == TLSModel::LocalDynamic) {
1732 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1735 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1736 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1739 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1741 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1744 // We need a chain node, and don't have one handy. The underlying
1745 // call has no side effects, so using the function entry node
1747 SDValue Chain = DAG.getEntryNode();
1748 Chain = DAG.getCopyToReg(Chain, dl,
1749 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1750 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1751 is64bit ? MVT::i64 : MVT::i32);
1752 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1753 PtrVT, ParmReg, TGA);
1754 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1755 // some hacks are needed here to tie everything together. The extra
1756 // copies dissolve during subsequent transforms.
1757 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1758 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1759 Chain, ParmReg, TGA);
1760 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1763 llvm_unreachable("Unknown TLS model!");
1766 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1767 SelectionDAG &DAG) const {
1768 EVT PtrVT = Op.getValueType();
1769 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1771 const GlobalValue *GV = GSDN->getGlobal();
1773 // 64-bit SVR4 ABI code is always position-independent.
1774 // The actual address of the GlobalValue is stored in the TOC.
1775 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1776 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1777 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1778 DAG.getRegister(PPC::X2, MVT::i64));
1781 unsigned MOHiFlag, MOLoFlag;
1782 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1784 if (isPIC && Subtarget.isSVR4ABI()) {
1785 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1787 PPCII::MO_PIC_FLAG);
1788 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1789 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1793 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1795 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1797 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1799 // If the global reference is actually to a non-lazy-pointer, we have to do an
1800 // extra load to get the address of the global.
1801 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1802 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1803 false, false, false, 0);
1807 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1808 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1811 if (Op.getValueType() == MVT::v2i64) {
1812 // When the operands themselves are v2i64 values, we need to do something
1813 // special because VSX has no underlying comparison operations for these.
1814 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1815 // Equality can be handled by casting to the legal type for Altivec
1816 // comparisons, everything else needs to be expanded.
1817 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1818 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1819 DAG.getSetCC(dl, MVT::v4i32,
1820 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1821 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1828 // We handle most of these in the usual way.
1832 // If we're comparing for equality to zero, expose the fact that this is
1833 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1834 // fold the new nodes.
1835 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1836 if (C->isNullValue() && CC == ISD::SETEQ) {
1837 EVT VT = Op.getOperand(0).getValueType();
1838 SDValue Zext = Op.getOperand(0);
1839 if (VT.bitsLT(MVT::i32)) {
1841 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1843 unsigned Log2b = Log2_32(VT.getSizeInBits());
1844 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1845 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1846 DAG.getConstant(Log2b, MVT::i32));
1847 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1849 // Leave comparisons against 0 and -1 alone for now, since they're usually
1850 // optimized. FIXME: revisit this when we can custom lower all setcc
1852 if (C->isAllOnesValue() || C->isNullValue())
1856 // If we have an integer seteq/setne, turn it into a compare against zero
1857 // by xor'ing the rhs with the lhs, which is faster than setting a
1858 // condition register, reading it back out, and masking the correct bit. The
1859 // normal approach here uses sub to do this instead of xor. Using xor exposes
1860 // the result to other bit-twiddling opportunities.
1861 EVT LHSVT = Op.getOperand(0).getValueType();
1862 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1863 EVT VT = Op.getValueType();
1864 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1866 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1871 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1872 const PPCSubtarget &Subtarget) const {
1873 SDNode *Node = Op.getNode();
1874 EVT VT = Node->getValueType(0);
1875 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1876 SDValue InChain = Node->getOperand(0);
1877 SDValue VAListPtr = Node->getOperand(1);
1878 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1881 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1884 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1885 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1886 false, false, false, 0);
1887 InChain = GprIndex.getValue(1);
1889 if (VT == MVT::i64) {
1890 // Check if GprIndex is even
1891 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1892 DAG.getConstant(1, MVT::i32));
1893 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1894 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1895 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1896 DAG.getConstant(1, MVT::i32));
1897 // Align GprIndex to be even if it isn't
1898 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1902 // fpr index is 1 byte after gpr
1903 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1904 DAG.getConstant(1, MVT::i32));
1907 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1908 FprPtr, MachinePointerInfo(SV), MVT::i8,
1909 false, false, false, 0);
1910 InChain = FprIndex.getValue(1);
1912 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1913 DAG.getConstant(8, MVT::i32));
1915 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1916 DAG.getConstant(4, MVT::i32));
1919 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1920 MachinePointerInfo(), false, false,
1922 InChain = OverflowArea.getValue(1);
1924 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1925 MachinePointerInfo(), false, false,
1927 InChain = RegSaveArea.getValue(1);
1929 // select overflow_area if index > 8
1930 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1931 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1933 // adjustment constant gpr_index * 4/8
1934 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1935 VT.isInteger() ? GprIndex : FprIndex,
1936 DAG.getConstant(VT.isInteger() ? 4 : 8,
1939 // OurReg = RegSaveArea + RegConstant
1940 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1943 // Floating types are 32 bytes into RegSaveArea
1944 if (VT.isFloatingPoint())
1945 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1946 DAG.getConstant(32, MVT::i32));
1948 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1949 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1950 VT.isInteger() ? GprIndex : FprIndex,
1951 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1954 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1955 VT.isInteger() ? VAListPtr : FprPtr,
1956 MachinePointerInfo(SV),
1957 MVT::i8, false, false, 0);
1959 // determine if we should load from reg_save_area or overflow_area
1960 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1962 // increase overflow_area by 4/8 if gpr/fpr > 8
1963 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1964 DAG.getConstant(VT.isInteger() ? 4 : 8,
1967 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1970 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1972 MachinePointerInfo(),
1973 MVT::i32, false, false, 0);
1975 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1976 false, false, false, 0);
1979 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1980 const PPCSubtarget &Subtarget) const {
1981 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1983 // We have to copy the entire va_list struct:
1984 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1985 return DAG.getMemcpy(Op.getOperand(0), Op,
1986 Op.getOperand(1), Op.getOperand(2),
1987 DAG.getConstant(12, MVT::i32), 8, false, true,
1988 MachinePointerInfo(), MachinePointerInfo());
1991 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1992 SelectionDAG &DAG) const {
1993 return Op.getOperand(0);
1996 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1997 SelectionDAG &DAG) const {
1998 SDValue Chain = Op.getOperand(0);
1999 SDValue Trmp = Op.getOperand(1); // trampoline
2000 SDValue FPtr = Op.getOperand(2); // nested function
2001 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2004 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2005 bool isPPC64 = (PtrVT == MVT::i64);
2007 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2010 TargetLowering::ArgListTy Args;
2011 TargetLowering::ArgListEntry Entry;
2013 Entry.Ty = IntPtrTy;
2014 Entry.Node = Trmp; Args.push_back(Entry);
2016 // TrampSize == (isPPC64 ? 48 : 40);
2017 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2018 isPPC64 ? MVT::i64 : MVT::i32);
2019 Args.push_back(Entry);
2021 Entry.Node = FPtr; Args.push_back(Entry);
2022 Entry.Node = Nest; Args.push_back(Entry);
2024 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2025 TargetLowering::CallLoweringInfo CLI(DAG);
2026 CLI.setDebugLoc(dl).setChain(Chain)
2027 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2028 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2029 std::move(Args), 0);
2031 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2032 return CallResult.second;
2035 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2036 const PPCSubtarget &Subtarget) const {
2037 MachineFunction &MF = DAG.getMachineFunction();
2038 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2042 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2043 // vastart just stores the address of the VarArgsFrameIndex slot into the
2044 // memory location argument.
2045 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2046 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2047 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2048 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2049 MachinePointerInfo(SV),
2053 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2054 // We suppose the given va_list is already allocated.
2057 // char gpr; /* index into the array of 8 GPRs
2058 // * stored in the register save area
2059 // * gpr=0 corresponds to r3,
2060 // * gpr=1 to r4, etc.
2062 // char fpr; /* index into the array of 8 FPRs
2063 // * stored in the register save area
2064 // * fpr=0 corresponds to f1,
2065 // * fpr=1 to f2, etc.
2067 // char *overflow_arg_area;
2068 // /* location on stack that holds
2069 // * the next overflow argument
2071 // char *reg_save_area;
2072 // /* where r3:r10 and f1:f8 (if saved)
2078 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2079 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2082 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2084 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2086 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2089 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2090 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2092 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2093 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2095 uint64_t FPROffset = 1;
2096 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2098 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2100 // Store first byte : number of int regs
2101 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2103 MachinePointerInfo(SV),
2104 MVT::i8, false, false, 0);
2105 uint64_t nextOffset = FPROffset;
2106 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2109 // Store second byte : number of float regs
2110 SDValue secondStore =
2111 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2112 MachinePointerInfo(SV, nextOffset), MVT::i8,
2114 nextOffset += StackOffset;
2115 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2117 // Store second word : arguments given on stack
2118 SDValue thirdStore =
2119 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2120 MachinePointerInfo(SV, nextOffset),
2122 nextOffset += FrameOffset;
2123 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2125 // Store third word : arguments given in registers
2126 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2127 MachinePointerInfo(SV, nextOffset),
2132 #include "PPCGenCallingConv.inc"
2134 // Function whose sole purpose is to kill compiler warnings
2135 // stemming from unused functions included from PPCGenCallingConv.inc.
2136 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2137 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2140 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2141 CCValAssign::LocInfo &LocInfo,
2142 ISD::ArgFlagsTy &ArgFlags,
2147 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2149 CCValAssign::LocInfo &LocInfo,
2150 ISD::ArgFlagsTy &ArgFlags,
2152 static const MCPhysReg ArgRegs[] = {
2153 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2154 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2156 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2158 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2160 // Skip one register if the first unallocated register has an even register
2161 // number and there are still argument registers available which have not been
2162 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2163 // need to skip a register if RegNum is odd.
2164 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2165 State.AllocateReg(ArgRegs[RegNum]);
2168 // Always return false here, as this function only makes sure that the first
2169 // unallocated register has an odd register number and does not actually
2170 // allocate a register for the current argument.
2174 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2176 CCValAssign::LocInfo &LocInfo,
2177 ISD::ArgFlagsTy &ArgFlags,
2179 static const MCPhysReg ArgRegs[] = {
2180 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2184 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2186 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2188 // If there is only one Floating-point register left we need to put both f64
2189 // values of a split ppc_fp128 value on the stack.
2190 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2191 State.AllocateReg(ArgRegs[RegNum]);
2194 // Always return false here, as this function only makes sure that the two f64
2195 // values a ppc_fp128 value is split into are both passed in registers or both
2196 // passed on the stack and does not actually allocate a register for the
2197 // current argument.
2201 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2203 static const MCPhysReg *GetFPR() {
2204 static const MCPhysReg FPR[] = {
2205 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2206 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2212 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2214 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2215 unsigned PtrByteSize) {
2216 unsigned ArgSize = ArgVT.getStoreSize();
2217 if (Flags.isByVal())
2218 ArgSize = Flags.getByValSize();
2220 // Round up to multiples of the pointer size, except for array members,
2221 // which are always packed.
2222 if (!Flags.isInConsecutiveRegs())
2223 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2228 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2230 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2231 ISD::ArgFlagsTy Flags,
2232 unsigned PtrByteSize) {
2233 unsigned Align = PtrByteSize;
2235 // Altivec parameters are padded to a 16 byte boundary.
2236 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2237 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2238 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2241 // ByVal parameters are aligned as requested.
2242 if (Flags.isByVal()) {
2243 unsigned BVAlign = Flags.getByValAlign();
2244 if (BVAlign > PtrByteSize) {
2245 if (BVAlign % PtrByteSize != 0)
2247 "ByVal alignment is not a multiple of the pointer size");
2253 // Array members are always packed to their original alignment.
2254 if (Flags.isInConsecutiveRegs()) {
2255 // If the array member was split into multiple registers, the first
2256 // needs to be aligned to the size of the full type. (Except for
2257 // ppcf128, which is only aligned as its f64 components.)
2258 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2259 Align = OrigVT.getStoreSize();
2261 Align = ArgVT.getStoreSize();
2267 /// CalculateStackSlotUsed - Return whether this argument will use its
2268 /// stack slot (instead of being passed in registers). ArgOffset,
2269 /// AvailableFPRs, and AvailableVRs must hold the current argument
2270 /// position, and will be updated to account for this argument.
2271 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2272 ISD::ArgFlagsTy Flags,
2273 unsigned PtrByteSize,
2274 unsigned LinkageSize,
2275 unsigned ParamAreaSize,
2276 unsigned &ArgOffset,
2277 unsigned &AvailableFPRs,
2278 unsigned &AvailableVRs) {
2279 bool UseMemory = false;
2281 // Respect alignment of argument on the stack.
2283 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2284 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2285 // If there's no space left in the argument save area, we must
2286 // use memory (this check also catches zero-sized arguments).
2287 if (ArgOffset >= LinkageSize + ParamAreaSize)
2290 // Allocate argument on the stack.
2291 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2292 if (Flags.isInConsecutiveRegsLast())
2293 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2294 // If we overran the argument save area, we must use memory
2295 // (this check catches arguments passed partially in memory)
2296 if (ArgOffset > LinkageSize + ParamAreaSize)
2299 // However, if the argument is actually passed in an FPR or a VR,
2300 // we don't use memory after all.
2301 if (!Flags.isByVal()) {
2302 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2303 if (AvailableFPRs > 0) {
2307 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2308 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2309 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2310 if (AvailableVRs > 0) {
2319 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2320 /// ensure minimum alignment required for target.
2321 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2322 unsigned NumBytes) {
2323 unsigned TargetAlign =
2324 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2325 unsigned AlignMask = TargetAlign - 1;
2326 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2331 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2332 CallingConv::ID CallConv, bool isVarArg,
2333 const SmallVectorImpl<ISD::InputArg>
2335 SDLoc dl, SelectionDAG &DAG,
2336 SmallVectorImpl<SDValue> &InVals)
2338 if (Subtarget.isSVR4ABI()) {
2339 if (Subtarget.isPPC64())
2340 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2343 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2346 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2352 PPCTargetLowering::LowerFormalArguments_32SVR4(
2354 CallingConv::ID CallConv, bool isVarArg,
2355 const SmallVectorImpl<ISD::InputArg>
2357 SDLoc dl, SelectionDAG &DAG,
2358 SmallVectorImpl<SDValue> &InVals) const {
2360 // 32-bit SVR4 ABI Stack Frame Layout:
2361 // +-----------------------------------+
2362 // +--> | Back chain |
2363 // | +-----------------------------------+
2364 // | | Floating-point register save area |
2365 // | +-----------------------------------+
2366 // | | General register save area |
2367 // | +-----------------------------------+
2368 // | | CR save word |
2369 // | +-----------------------------------+
2370 // | | VRSAVE save word |
2371 // | +-----------------------------------+
2372 // | | Alignment padding |
2373 // | +-----------------------------------+
2374 // | | Vector register save area |
2375 // | +-----------------------------------+
2376 // | | Local variable space |
2377 // | +-----------------------------------+
2378 // | | Parameter list area |
2379 // | +-----------------------------------+
2380 // | | LR save word |
2381 // | +-----------------------------------+
2382 // SP--> +--- | Back chain |
2383 // +-----------------------------------+
2386 // System V Application Binary Interface PowerPC Processor Supplement
2387 // AltiVec Technology Programming Interface Manual
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 MachineFrameInfo *MFI = MF.getFrameInfo();
2391 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2393 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2394 // Potential tail calls could cause overwriting of argument stack slots.
2395 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2396 (CallConv == CallingConv::Fast));
2397 unsigned PtrByteSize = 4;
2399 // Assign locations to all of the incoming arguments.
2400 SmallVector<CCValAssign, 16> ArgLocs;
2401 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2404 // Reserve space for the linkage area on the stack.
2405 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2406 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2408 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2410 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2411 CCValAssign &VA = ArgLocs[i];
2413 // Arguments stored in registers.
2414 if (VA.isRegLoc()) {
2415 const TargetRegisterClass *RC;
2416 EVT ValVT = VA.getValVT();
2418 switch (ValVT.getSimpleVT().SimpleTy) {
2420 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2423 RC = &PPC::GPRCRegClass;
2426 RC = &PPC::F4RCRegClass;
2429 if (Subtarget.hasVSX())
2430 RC = &PPC::VSFRCRegClass;
2432 RC = &PPC::F8RCRegClass;
2438 RC = &PPC::VRRCRegClass;
2442 RC = &PPC::VSHRCRegClass;
2446 // Transform the arguments stored in physical registers into virtual ones.
2447 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2448 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2449 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2451 if (ValVT == MVT::i1)
2452 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2454 InVals.push_back(ArgValue);
2456 // Argument stored in memory.
2457 assert(VA.isMemLoc());
2459 unsigned ArgSize = VA.getLocVT().getStoreSize();
2460 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2463 // Create load nodes to retrieve arguments from the stack.
2464 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2465 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2466 MachinePointerInfo(),
2467 false, false, false, 0));
2471 // Assign locations to all of the incoming aggregate by value arguments.
2472 // Aggregates passed by value are stored in the local variable space of the
2473 // caller's stack frame, right above the parameter list area.
2474 SmallVector<CCValAssign, 16> ByValArgLocs;
2475 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2476 ByValArgLocs, *DAG.getContext());
2478 // Reserve stack space for the allocations in CCInfo.
2479 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2481 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2483 // Area that is at least reserved in the caller of this function.
2484 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2485 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2487 // Set the size that is at least reserved in caller of this function. Tail
2488 // call optimized function's reserved stack space needs to be aligned so that
2489 // taking the difference between two stack areas will result in an aligned
2491 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2492 FuncInfo->setMinReservedArea(MinReservedArea);
2494 SmallVector<SDValue, 8> MemOps;
2496 // If the function takes variable number of arguments, make a frame index for
2497 // the start of the first vararg value... for expansion of llvm.va_start.
2499 static const MCPhysReg GPArgRegs[] = {
2500 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2501 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2503 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2505 static const MCPhysReg FPArgRegs[] = {
2506 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2509 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2510 if (DisablePPCFloatInVariadic)
2513 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2515 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2518 // Make room for NumGPArgRegs and NumFPArgRegs.
2519 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2520 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2522 FuncInfo->setVarArgsStackOffset(
2523 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2524 CCInfo.getNextStackOffset(), true));
2526 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2527 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2529 // The fixed integer arguments of a variadic function are stored to the
2530 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2531 // the result of va_next.
2532 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2533 // Get an existing live-in vreg, or add a new one.
2534 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2536 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2538 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2539 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2540 MachinePointerInfo(), false, false, 0);
2541 MemOps.push_back(Store);
2542 // Increment the address by four for the next argument to store
2543 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2544 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2547 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2549 // The double arguments are stored to the VarArgsFrameIndex
2551 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2552 // Get an existing live-in vreg, or add a new one.
2553 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2555 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2557 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2558 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2559 MachinePointerInfo(), false, false, 0);
2560 MemOps.push_back(Store);
2561 // Increment the address by eight for the next argument to store
2562 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2564 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2568 if (!MemOps.empty())
2569 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2574 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2575 // value to MVT::i64 and then truncate to the correct register size.
2577 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2578 SelectionDAG &DAG, SDValue ArgVal,
2581 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2582 DAG.getValueType(ObjectVT));
2583 else if (Flags.isZExt())
2584 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2585 DAG.getValueType(ObjectVT));
2587 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2591 PPCTargetLowering::LowerFormalArguments_64SVR4(
2593 CallingConv::ID CallConv, bool isVarArg,
2594 const SmallVectorImpl<ISD::InputArg>
2596 SDLoc dl, SelectionDAG &DAG,
2597 SmallVectorImpl<SDValue> &InVals) const {
2598 // TODO: add description of PPC stack frame format, or at least some docs.
2600 bool isELFv2ABI = Subtarget.isELFv2ABI();
2601 bool isLittleEndian = Subtarget.isLittleEndian();
2602 MachineFunction &MF = DAG.getMachineFunction();
2603 MachineFrameInfo *MFI = MF.getFrameInfo();
2604 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2606 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2607 // Potential tail calls could cause overwriting of argument stack slots.
2608 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2609 (CallConv == CallingConv::Fast));
2610 unsigned PtrByteSize = 8;
2612 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2615 static const MCPhysReg GPR[] = {
2616 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2617 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2620 static const MCPhysReg *FPR = GetFPR();
2622 static const MCPhysReg VR[] = {
2623 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2624 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2626 static const MCPhysReg VSRH[] = {
2627 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2628 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2631 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2632 const unsigned Num_FPR_Regs = 13;
2633 const unsigned Num_VR_Regs = array_lengthof(VR);
2635 // Do a first pass over the arguments to determine whether the ABI
2636 // guarantees that our caller has allocated the parameter save area
2637 // on its stack frame. In the ELFv1 ABI, this is always the case;
2638 // in the ELFv2 ABI, it is true if this is a vararg function or if
2639 // any parameter is located in a stack slot.
2641 bool HasParameterArea = !isELFv2ABI || isVarArg;
2642 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2643 unsigned NumBytes = LinkageSize;
2644 unsigned AvailableFPRs = Num_FPR_Regs;
2645 unsigned AvailableVRs = Num_VR_Regs;
2646 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2647 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2648 PtrByteSize, LinkageSize, ParamAreaSize,
2649 NumBytes, AvailableFPRs, AvailableVRs))
2650 HasParameterArea = true;
2652 // Add DAG nodes to load the arguments or copy them out of registers. On
2653 // entry to a function on PPC, the arguments start after the linkage area,
2654 // although the first ones are often in registers.
2656 unsigned ArgOffset = LinkageSize;
2657 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2658 SmallVector<SDValue, 8> MemOps;
2659 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2660 unsigned CurArgIdx = 0;
2661 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2663 bool needsLoad = false;
2664 EVT ObjectVT = Ins[ArgNo].VT;
2665 EVT OrigVT = Ins[ArgNo].ArgVT;
2666 unsigned ObjSize = ObjectVT.getStoreSize();
2667 unsigned ArgSize = ObjSize;
2668 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2669 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2670 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2672 /* Respect alignment of argument on the stack. */
2674 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2675 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2676 unsigned CurArgOffset = ArgOffset;
2678 /* Compute GPR index associated with argument offset. */
2679 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2680 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2682 // FIXME the codegen can be much improved in some cases.
2683 // We do not have to keep everything in memory.
2684 if (Flags.isByVal()) {
2685 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2686 ObjSize = Flags.getByValSize();
2687 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2688 // Empty aggregate parameters do not take up registers. Examples:
2692 // etc. However, we have to provide a place-holder in InVals, so
2693 // pretend we have an 8-byte item at the current address for that
2696 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2697 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2698 InVals.push_back(FIN);
2702 // Create a stack object covering all stack doublewords occupied
2703 // by the argument. If the argument is (fully or partially) on
2704 // the stack, or if the argument is fully in registers but the
2705 // caller has allocated the parameter save anyway, we can refer
2706 // directly to the caller's stack frame. Otherwise, create a
2707 // local copy in our own frame.
2709 if (HasParameterArea ||
2710 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2711 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2713 FI = MFI->CreateStackObject(ArgSize, Align, false);
2714 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2716 // Handle aggregates smaller than 8 bytes.
2717 if (ObjSize < PtrByteSize) {
2718 // The value of the object is its address, which differs from the
2719 // address of the enclosing doubleword on big-endian systems.
2721 if (!isLittleEndian) {
2722 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2723 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2725 InVals.push_back(Arg);
2727 if (GPR_idx != Num_GPR_Regs) {
2728 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2729 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2732 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2733 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2734 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2735 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2736 MachinePointerInfo(FuncArg),
2737 ObjType, false, false, 0);
2739 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2740 // store the whole register as-is to the parameter save area
2742 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2743 MachinePointerInfo(FuncArg),
2747 MemOps.push_back(Store);
2749 // Whether we copied from a register or not, advance the offset
2750 // into the parameter save area by a full doubleword.
2751 ArgOffset += PtrByteSize;
2755 // The value of the object is its address, which is the address of
2756 // its first stack doubleword.
2757 InVals.push_back(FIN);
2759 // Store whatever pieces of the object are in registers to memory.
2760 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2761 if (GPR_idx == Num_GPR_Regs)
2764 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2765 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2768 SDValue Off = DAG.getConstant(j, PtrVT);
2769 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2771 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2772 MachinePointerInfo(FuncArg, j),
2774 MemOps.push_back(Store);
2777 ArgOffset += ArgSize;
2781 switch (ObjectVT.getSimpleVT().SimpleTy) {
2782 default: llvm_unreachable("Unhandled argument type!");
2786 // These can be scalar arguments or elements of an integer array type
2787 // passed directly. Clang may use those instead of "byval" aggregate
2788 // types to avoid forcing arguments to memory unnecessarily.
2789 if (GPR_idx != Num_GPR_Regs) {
2790 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2791 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2793 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2794 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2795 // value to MVT::i64 and then truncate to the correct register size.
2796 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2799 ArgSize = PtrByteSize;
2806 // These can be scalar arguments or elements of a float array type
2807 // passed directly. The latter are used to implement ELFv2 homogenous
2808 // float aggregates.
2809 if (FPR_idx != Num_FPR_Regs) {
2812 if (ObjectVT == MVT::f32)
2813 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2815 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2816 &PPC::VSFRCRegClass :
2817 &PPC::F8RCRegClass);
2819 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2821 } else if (GPR_idx != Num_GPR_Regs) {
2822 // This can only ever happen in the presence of f32 array types,
2823 // since otherwise we never run out of FPRs before running out
2825 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2826 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2828 if (ObjectVT == MVT::f32) {
2829 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2830 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2831 DAG.getConstant(32, MVT::i32));
2832 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2835 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2840 // When passing an array of floats, the array occupies consecutive
2841 // space in the argument area; only round up to the next doubleword
2842 // at the end of the array. Otherwise, each float takes 8 bytes.
2843 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2844 ArgOffset += ArgSize;
2845 if (Flags.isInConsecutiveRegsLast())
2846 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2854 // These can be scalar arguments or elements of a vector array type
2855 // passed directly. The latter are used to implement ELFv2 homogenous
2856 // vector aggregates.
2857 if (VR_idx != Num_VR_Regs) {
2858 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2859 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2860 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2861 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2870 // We need to load the argument to a virtual register if we determined
2871 // above that we ran out of physical registers of the appropriate type.
2873 if (ObjSize < ArgSize && !isLittleEndian)
2874 CurArgOffset += ArgSize - ObjSize;
2875 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2876 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2877 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2878 false, false, false, 0);
2881 InVals.push_back(ArgVal);
2884 // Area that is at least reserved in the caller of this function.
2885 unsigned MinReservedArea;
2886 if (HasParameterArea)
2887 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2889 MinReservedArea = LinkageSize;
2891 // Set the size that is at least reserved in caller of this function. Tail
2892 // call optimized functions' reserved stack space needs to be aligned so that
2893 // taking the difference between two stack areas will result in an aligned
2895 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2896 FuncInfo->setMinReservedArea(MinReservedArea);
2898 // If the function takes variable number of arguments, make a frame index for
2899 // the start of the first vararg value... for expansion of llvm.va_start.
2901 int Depth = ArgOffset;
2903 FuncInfo->setVarArgsFrameIndex(
2904 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2905 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2907 // If this function is vararg, store any remaining integer argument regs
2908 // to their spots on the stack so that they may be loaded by deferencing the
2909 // result of va_next.
2910 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2911 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2912 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2913 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2914 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2915 MachinePointerInfo(), false, false, 0);
2916 MemOps.push_back(Store);
2917 // Increment the address by four for the next argument to store
2918 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2919 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2923 if (!MemOps.empty())
2924 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2930 PPCTargetLowering::LowerFormalArguments_Darwin(
2932 CallingConv::ID CallConv, bool isVarArg,
2933 const SmallVectorImpl<ISD::InputArg>
2935 SDLoc dl, SelectionDAG &DAG,
2936 SmallVectorImpl<SDValue> &InVals) const {
2937 // TODO: add description of PPC stack frame format, or at least some docs.
2939 MachineFunction &MF = DAG.getMachineFunction();
2940 MachineFrameInfo *MFI = MF.getFrameInfo();
2941 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2943 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2944 bool isPPC64 = PtrVT == MVT::i64;
2945 // Potential tail calls could cause overwriting of argument stack slots.
2946 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2947 (CallConv == CallingConv::Fast));
2948 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2950 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2952 unsigned ArgOffset = LinkageSize;
2953 // Area that is at least reserved in caller of this function.
2954 unsigned MinReservedArea = ArgOffset;
2956 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2957 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2958 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2960 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2961 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2962 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2965 static const MCPhysReg *FPR = GetFPR();
2967 static const MCPhysReg VR[] = {
2968 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2969 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2972 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2973 const unsigned Num_FPR_Regs = 13;
2974 const unsigned Num_VR_Regs = array_lengthof( VR);
2976 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2978 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2980 // In 32-bit non-varargs functions, the stack space for vectors is after the
2981 // stack space for non-vectors. We do not use this space unless we have
2982 // too many vectors to fit in registers, something that only occurs in
2983 // constructed examples:), but we have to walk the arglist to figure
2984 // that out...for the pathological case, compute VecArgOffset as the
2985 // start of the vector parameter area. Computing VecArgOffset is the
2986 // entire point of the following loop.
2987 unsigned VecArgOffset = ArgOffset;
2988 if (!isVarArg && !isPPC64) {
2989 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2991 EVT ObjectVT = Ins[ArgNo].VT;
2992 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2994 if (Flags.isByVal()) {
2995 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2996 unsigned ObjSize = Flags.getByValSize();
2998 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2999 VecArgOffset += ArgSize;
3003 switch(ObjectVT.getSimpleVT().SimpleTy) {
3004 default: llvm_unreachable("Unhandled argument type!");
3010 case MVT::i64: // PPC64
3012 // FIXME: We are guaranteed to be !isPPC64 at this point.
3013 // Does MVT::i64 apply?
3020 // Nothing to do, we're only looking at Nonvector args here.
3025 // We've found where the vector parameter area in memory is. Skip the
3026 // first 12 parameters; these don't use that memory.
3027 VecArgOffset = ((VecArgOffset+15)/16)*16;
3028 VecArgOffset += 12*16;
3030 // Add DAG nodes to load the arguments or copy them out of registers. On
3031 // entry to a function on PPC, the arguments start after the linkage area,
3032 // although the first ones are often in registers.
3034 SmallVector<SDValue, 8> MemOps;
3035 unsigned nAltivecParamsAtEnd = 0;
3036 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3037 unsigned CurArgIdx = 0;
3038 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3040 bool needsLoad = false;
3041 EVT ObjectVT = Ins[ArgNo].VT;
3042 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3043 unsigned ArgSize = ObjSize;
3044 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3045 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3046 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3048 unsigned CurArgOffset = ArgOffset;
3050 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3051 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3052 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3053 if (isVarArg || isPPC64) {
3054 MinReservedArea = ((MinReservedArea+15)/16)*16;
3055 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3058 } else nAltivecParamsAtEnd++;
3060 // Calculate min reserved area.
3061 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3065 // FIXME the codegen can be much improved in some cases.
3066 // We do not have to keep everything in memory.
3067 if (Flags.isByVal()) {
3068 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3069 ObjSize = Flags.getByValSize();
3070 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3071 // Objects of size 1 and 2 are right justified, everything else is
3072 // left justified. This means the memory address is adjusted forwards.
3073 if (ObjSize==1 || ObjSize==2) {
3074 CurArgOffset = CurArgOffset + (4 - ObjSize);
3076 // The value of the object is its address.
3077 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3078 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3079 InVals.push_back(FIN);
3080 if (ObjSize==1 || ObjSize==2) {
3081 if (GPR_idx != Num_GPR_Regs) {
3084 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3086 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3087 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3088 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3089 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3090 MachinePointerInfo(FuncArg),
3091 ObjType, false, false, 0);
3092 MemOps.push_back(Store);
3096 ArgOffset += PtrByteSize;
3100 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3101 // Store whatever pieces of the object are in registers
3102 // to memory. ArgOffset will be the address of the beginning
3104 if (GPR_idx != Num_GPR_Regs) {
3107 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3109 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3110 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3111 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3112 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3113 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3114 MachinePointerInfo(FuncArg, j),
3116 MemOps.push_back(Store);
3118 ArgOffset += PtrByteSize;
3120 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3127 switch (ObjectVT.getSimpleVT().SimpleTy) {
3128 default: llvm_unreachable("Unhandled argument type!");
3132 if (GPR_idx != Num_GPR_Regs) {
3133 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3134 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3136 if (ObjectVT == MVT::i1)
3137 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3142 ArgSize = PtrByteSize;
3144 // All int arguments reserve stack space in the Darwin ABI.
3145 ArgOffset += PtrByteSize;
3149 case MVT::i64: // PPC64
3150 if (GPR_idx != Num_GPR_Regs) {
3151 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3152 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3154 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3155 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3156 // value to MVT::i64 and then truncate to the correct register size.
3157 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3162 ArgSize = PtrByteSize;
3164 // All int arguments reserve stack space in the Darwin ABI.
3170 // Every 4 bytes of argument space consumes one of the GPRs available for
3171 // argument passing.
3172 if (GPR_idx != Num_GPR_Regs) {
3174 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3177 if (FPR_idx != Num_FPR_Regs) {
3180 if (ObjectVT == MVT::f32)
3181 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3183 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3185 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3191 // All FP arguments reserve stack space in the Darwin ABI.
3192 ArgOffset += isPPC64 ? 8 : ObjSize;
3198 // Note that vector arguments in registers don't reserve stack space,
3199 // except in varargs functions.
3200 if (VR_idx != Num_VR_Regs) {
3201 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3202 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3204 while ((ArgOffset % 16) != 0) {
3205 ArgOffset += PtrByteSize;
3206 if (GPR_idx != Num_GPR_Regs)
3210 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3214 if (!isVarArg && !isPPC64) {
3215 // Vectors go after all the nonvectors.
3216 CurArgOffset = VecArgOffset;
3219 // Vectors are aligned.
3220 ArgOffset = ((ArgOffset+15)/16)*16;
3221 CurArgOffset = ArgOffset;
3229 // We need to load the argument to a virtual register if we determined above
3230 // that we ran out of physical registers of the appropriate type.
3232 int FI = MFI->CreateFixedObject(ObjSize,
3233 CurArgOffset + (ArgSize - ObjSize),
3235 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3236 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3237 false, false, false, 0);
3240 InVals.push_back(ArgVal);
3243 // Allow for Altivec parameters at the end, if needed.
3244 if (nAltivecParamsAtEnd) {
3245 MinReservedArea = ((MinReservedArea+15)/16)*16;
3246 MinReservedArea += 16*nAltivecParamsAtEnd;
3249 // Area that is at least reserved in the caller of this function.
3250 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3252 // Set the size that is at least reserved in caller of this function. Tail
3253 // call optimized functions' reserved stack space needs to be aligned so that
3254 // taking the difference between two stack areas will result in an aligned
3256 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3257 FuncInfo->setMinReservedArea(MinReservedArea);
3259 // If the function takes variable number of arguments, make a frame index for
3260 // the start of the first vararg value... for expansion of llvm.va_start.
3262 int Depth = ArgOffset;
3264 FuncInfo->setVarArgsFrameIndex(
3265 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3267 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3269 // If this function is vararg, store any remaining integer argument regs
3270 // to their spots on the stack so that they may be loaded by deferencing the
3271 // result of va_next.
3272 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3276 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3278 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3280 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3281 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3282 MachinePointerInfo(), false, false, 0);
3283 MemOps.push_back(Store);
3284 // Increment the address by four for the next argument to store
3285 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3286 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3290 if (!MemOps.empty())
3291 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3296 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3297 /// adjusted to accommodate the arguments for the tailcall.
3298 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3299 unsigned ParamSize) {
3301 if (!isTailCall) return 0;
3303 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3304 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3305 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3306 // Remember only if the new adjustement is bigger.
3307 if (SPDiff < FI->getTailCallSPDelta())
3308 FI->setTailCallSPDelta(SPDiff);
3313 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3314 /// for tail call optimization. Targets which want to do tail call
3315 /// optimization should implement this function.
3317 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3318 CallingConv::ID CalleeCC,
3320 const SmallVectorImpl<ISD::InputArg> &Ins,
3321 SelectionDAG& DAG) const {
3322 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3325 // Variable argument functions are not supported.
3329 MachineFunction &MF = DAG.getMachineFunction();
3330 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3331 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3332 // Functions containing by val parameters are not supported.
3333 for (unsigned i = 0; i != Ins.size(); i++) {
3334 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3335 if (Flags.isByVal()) return false;
3338 // Non-PIC/GOT tail calls are supported.
3339 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3342 // At the moment we can only do local tail calls (in same module, hidden
3343 // or protected) if we are generating PIC.
3344 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3345 return G->getGlobal()->hasHiddenVisibility()
3346 || G->getGlobal()->hasProtectedVisibility();
3352 /// isCallCompatibleAddress - Return the immediate to use if the specified
3353 /// 32-bit value is representable in the immediate field of a BxA instruction.
3354 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3355 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3356 if (!C) return nullptr;
3358 int Addr = C->getZExtValue();
3359 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3360 SignExtend32<26>(Addr) != Addr)
3361 return nullptr; // Top 6 bits have to be sext of immediate.
3363 return DAG.getConstant((int)C->getZExtValue() >> 2,
3364 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3369 struct TailCallArgumentInfo {
3374 TailCallArgumentInfo() : FrameIdx(0) {}
3379 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3381 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3383 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3384 SmallVectorImpl<SDValue> &MemOpChains,
3386 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3387 SDValue Arg = TailCallArgs[i].Arg;
3388 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3389 int FI = TailCallArgs[i].FrameIdx;
3390 // Store relative to framepointer.
3391 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3392 MachinePointerInfo::getFixedStack(FI),
3397 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3398 /// the appropriate stack slot for the tail call optimized function call.
3399 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3400 MachineFunction &MF,
3409 // Calculate the new stack slot for the return address.
3410 int SlotSize = isPPC64 ? 8 : 4;
3411 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3413 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3414 NewRetAddrLoc, true);
3415 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3416 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3417 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3418 MachinePointerInfo::getFixedStack(NewRetAddr),
3421 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3422 // slot as the FP is never overwritten.
3425 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3426 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3428 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3429 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3430 MachinePointerInfo::getFixedStack(NewFPIdx),
3437 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3438 /// the position of the argument.
3440 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3441 SDValue Arg, int SPDiff, unsigned ArgOffset,
3442 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3443 int Offset = ArgOffset + SPDiff;
3444 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3445 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3446 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3447 SDValue FIN = DAG.getFrameIndex(FI, VT);
3448 TailCallArgumentInfo Info;
3450 Info.FrameIdxOp = FIN;
3452 TailCallArguments.push_back(Info);
3455 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3456 /// stack slot. Returns the chain as result and the loaded frame pointers in
3457 /// LROpOut/FPOpout. Used when tail calling.
3458 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3466 // Load the LR and FP stack slot for later adjusting.
3467 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3468 LROpOut = getReturnAddrFrameIndex(DAG);
3469 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3470 false, false, false, 0);
3471 Chain = SDValue(LROpOut.getNode(), 1);
3473 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3474 // slot as the FP is never overwritten.
3476 FPOpOut = getFramePointerFrameIndex(DAG);
3477 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3478 false, false, false, 0);
3479 Chain = SDValue(FPOpOut.getNode(), 1);
3485 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3486 /// by "Src" to address "Dst" of size "Size". Alignment information is
3487 /// specified by the specific parameter attribute. The copy will be passed as
3488 /// a byval function parameter.
3489 /// Sometimes what we are copying is the end of a larger object, the part that
3490 /// does not fit in registers.
3492 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3493 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3495 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3496 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3497 false, false, MachinePointerInfo(),
3498 MachinePointerInfo());
3501 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3504 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3505 SDValue Arg, SDValue PtrOff, int SPDiff,
3506 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3507 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3508 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3510 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3515 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3517 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3518 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3519 DAG.getConstant(ArgOffset, PtrVT));
3521 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3522 MachinePointerInfo(), false, false, 0));
3523 // Calculate and remember argument location.
3524 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3529 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3530 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3531 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3532 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3533 MachineFunction &MF = DAG.getMachineFunction();
3535 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3536 // might overwrite each other in case of tail call optimization.
3537 SmallVector<SDValue, 8> MemOpChains2;
3538 // Do not flag preceding copytoreg stuff together with the following stuff.
3540 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3542 if (!MemOpChains2.empty())
3543 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3545 // Store the return address to the appropriate stack slot.
3546 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3547 isPPC64, isDarwinABI, dl);
3549 // Emit callseq_end just before tailcall node.
3550 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3551 DAG.getIntPtrConstant(0, true), InFlag, dl);
3552 InFlag = Chain.getValue(1);
3556 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3557 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3558 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3559 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3560 const PPCSubtarget &Subtarget) {
3562 bool isPPC64 = Subtarget.isPPC64();
3563 bool isSVR4ABI = Subtarget.isSVR4ABI();
3564 bool isELFv2ABI = Subtarget.isELFv2ABI();
3566 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3567 NodeTys.push_back(MVT::Other); // Returns a chain
3568 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3570 unsigned CallOpc = PPCISD::CALL;
3572 bool needIndirectCall = true;
3573 if (!isSVR4ABI || !isPPC64)
3574 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3575 // If this is an absolute destination address, use the munged value.
3576 Callee = SDValue(Dest, 0);
3577 needIndirectCall = false;
3580 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3581 unsigned OpFlags = 0;
3582 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3583 (Subtarget.getTargetTriple().isMacOSX() &&
3584 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3585 (G->getGlobal()->isDeclaration() ||
3586 G->getGlobal()->isWeakForLinker())) ||
3587 (Subtarget.isTargetELF() && !isPPC64 &&
3588 !G->getGlobal()->hasLocalLinkage() &&
3589 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3590 // PC-relative references to external symbols should go through $stub,
3591 // unless we're building with the leopard linker or later, which
3592 // automatically synthesizes these stubs.
3593 OpFlags = PPCII::MO_PLT_OR_STUB;
3596 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3597 // every direct call is) turn it into a TargetGlobalAddress /
3598 // TargetExternalSymbol node so that legalize doesn't hack it.
3599 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3600 Callee.getValueType(), 0, OpFlags);
3601 needIndirectCall = false;
3604 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3605 unsigned char OpFlags = 0;
3607 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3608 (Subtarget.getTargetTriple().isMacOSX() &&
3609 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3610 (Subtarget.isTargetELF() && !isPPC64 &&
3611 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3612 // PC-relative references to external symbols should go through $stub,
3613 // unless we're building with the leopard linker or later, which
3614 // automatically synthesizes these stubs.
3615 OpFlags = PPCII::MO_PLT_OR_STUB;
3618 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3620 needIndirectCall = false;
3623 if (needIndirectCall) {
3624 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3625 // to do the call, we can't use PPCISD::CALL.
3626 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3628 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3629 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3630 // entry point, but to the function descriptor (the function entry point
3631 // address is part of the function descriptor though).
3632 // The function descriptor is a three doubleword structure with the
3633 // following fields: function entry point, TOC base address and
3634 // environment pointer.
3635 // Thus for a call through a function pointer, the following actions need
3637 // 1. Save the TOC of the caller in the TOC save area of its stack
3638 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3639 // 2. Load the address of the function entry point from the function
3641 // 3. Load the TOC of the callee from the function descriptor into r2.
3642 // 4. Load the environment pointer from the function descriptor into
3644 // 5. Branch to the function entry point address.
3645 // 6. On return of the callee, the TOC of the caller needs to be
3646 // restored (this is done in FinishCall()).
3648 // All those operations are flagged together to ensure that no other
3649 // operations can be scheduled in between. E.g. without flagging the
3650 // operations together, a TOC access in the caller could be scheduled
3651 // between the load of the callee TOC and the branch to the callee, which
3652 // results in the TOC access going through the TOC of the callee instead
3653 // of going through the TOC of the caller, which leads to incorrect code.
3655 // Load the address of the function entry point from the function
3657 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3658 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3659 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3660 Chain = LoadFuncPtr.getValue(1);
3661 InFlag = LoadFuncPtr.getValue(2);
3663 // Load environment pointer into r11.
3664 // Offset of the environment pointer within the function descriptor.
3665 SDValue PtrOff = DAG.getIntPtrConstant(16);
3667 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3668 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3670 Chain = LoadEnvPtr.getValue(1);
3671 InFlag = LoadEnvPtr.getValue(2);
3673 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3675 Chain = EnvVal.getValue(0);
3676 InFlag = EnvVal.getValue(1);
3678 // Load TOC of the callee into r2. We are using a target-specific load
3679 // with r2 hard coded, because the result of a target-independent load
3680 // would never go directly into r2, since r2 is a reserved register (which
3681 // prevents the register allocator from allocating it), resulting in an
3682 // additional register being allocated and an unnecessary move instruction
3684 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3685 SDValue TOCOff = DAG.getIntPtrConstant(8);
3686 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3687 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3689 Chain = LoadTOCPtr.getValue(0);
3690 InFlag = LoadTOCPtr.getValue(1);
3692 MTCTROps[0] = Chain;
3693 MTCTROps[1] = LoadFuncPtr;
3694 MTCTROps[2] = InFlag;
3697 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3698 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3699 InFlag = Chain.getValue(1);
3702 NodeTys.push_back(MVT::Other);
3703 NodeTys.push_back(MVT::Glue);
3704 Ops.push_back(Chain);
3705 CallOpc = PPCISD::BCTRL;
3706 Callee.setNode(nullptr);
3707 // Add use of X11 (holding environment pointer)
3708 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3709 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3710 // Add CTR register as callee so a bctr can be emitted later.
3712 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3715 // If this is a direct call, pass the chain and the callee.
3716 if (Callee.getNode()) {
3717 Ops.push_back(Chain);
3718 Ops.push_back(Callee);
3720 // If this is a tail call add stack pointer delta.
3722 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3724 // Add argument registers to the end of the list so that they are known live
3726 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3727 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3728 RegsToPass[i].second.getValueType()));
3730 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3731 if (Callee.getNode() && isELFv2ABI)
3732 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3738 bool isLocalCall(const SDValue &Callee)
3740 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3741 return !G->getGlobal()->isDeclaration() &&
3742 !G->getGlobal()->isWeakForLinker();
3747 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3748 CallingConv::ID CallConv, bool isVarArg,
3749 const SmallVectorImpl<ISD::InputArg> &Ins,
3750 SDLoc dl, SelectionDAG &DAG,
3751 SmallVectorImpl<SDValue> &InVals) const {
3753 SmallVector<CCValAssign, 16> RVLocs;
3754 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3756 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3758 // Copy all of the result registers out of their specified physreg.
3759 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3760 CCValAssign &VA = RVLocs[i];
3761 assert(VA.isRegLoc() && "Can only return in registers!");
3763 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3764 VA.getLocReg(), VA.getLocVT(), InFlag);
3765 Chain = Val.getValue(1);
3766 InFlag = Val.getValue(2);
3768 switch (VA.getLocInfo()) {
3769 default: llvm_unreachable("Unknown loc info!");
3770 case CCValAssign::Full: break;
3771 case CCValAssign::AExt:
3772 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3774 case CCValAssign::ZExt:
3775 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3776 DAG.getValueType(VA.getValVT()));
3777 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3779 case CCValAssign::SExt:
3780 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3781 DAG.getValueType(VA.getValVT()));
3782 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3786 InVals.push_back(Val);
3793 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3794 bool isTailCall, bool isVarArg,
3796 SmallVector<std::pair<unsigned, SDValue>, 8>
3798 SDValue InFlag, SDValue Chain,
3800 int SPDiff, unsigned NumBytes,
3801 const SmallVectorImpl<ISD::InputArg> &Ins,
3802 SmallVectorImpl<SDValue> &InVals) const {
3804 bool isELFv2ABI = Subtarget.isELFv2ABI();
3805 std::vector<EVT> NodeTys;
3806 SmallVector<SDValue, 8> Ops;
3807 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3808 isTailCall, RegsToPass, Ops, NodeTys,
3811 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3812 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3813 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3815 // When performing tail call optimization the callee pops its arguments off
3816 // the stack. Account for this here so these bytes can be pushed back on in
3817 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3818 int BytesCalleePops =
3819 (CallConv == CallingConv::Fast &&
3820 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3822 // Add a register mask operand representing the call-preserved registers.
3823 const TargetRegisterInfo *TRI =
3824 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3825 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3826 assert(Mask && "Missing call preserved mask for calling convention");
3827 Ops.push_back(DAG.getRegisterMask(Mask));
3829 if (InFlag.getNode())
3830 Ops.push_back(InFlag);
3834 assert(((Callee.getOpcode() == ISD::Register &&
3835 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3836 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3837 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3838 isa<ConstantSDNode>(Callee)) &&
3839 "Expecting an global address, external symbol, absolute value or register");
3841 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3844 // Add a NOP immediately after the branch instruction when using the 64-bit
3845 // SVR4 ABI. At link time, if caller and callee are in a different module and
3846 // thus have a different TOC, the call will be replaced with a call to a stub
3847 // function which saves the current TOC, loads the TOC of the callee and
3848 // branches to the callee. The NOP will be replaced with a load instruction
3849 // which restores the TOC of the caller from the TOC save slot of the current
3850 // stack frame. If caller and callee belong to the same module (and have the
3851 // same TOC), the NOP will remain unchanged.
3853 bool needsTOCRestore = false;
3854 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3855 if (CallOpc == PPCISD::BCTRL) {
3856 // This is a call through a function pointer.
3857 // Restore the caller TOC from the save area into R2.
3858 // See PrepareCall() for more information about calls through function
3859 // pointers in the 64-bit SVR4 ABI.
3860 // We are using a target-specific load with r2 hard coded, because the
3861 // result of a target-independent load would never go directly into r2,
3862 // since r2 is a reserved register (which prevents the register allocator
3863 // from allocating it), resulting in an additional register being
3864 // allocated and an unnecessary move instruction being generated.
3865 needsTOCRestore = true;
3866 } else if ((CallOpc == PPCISD::CALL) &&
3867 (!isLocalCall(Callee) ||
3868 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3869 // Otherwise insert NOP for non-local calls.
3870 CallOpc = PPCISD::CALL_NOP;
3874 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3875 InFlag = Chain.getValue(1);
3877 if (needsTOCRestore) {
3878 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3879 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3880 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3881 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3882 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3883 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3884 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3885 InFlag = Chain.getValue(1);
3888 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3889 DAG.getIntPtrConstant(BytesCalleePops, true),
3892 InFlag = Chain.getValue(1);
3894 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3895 Ins, dl, DAG, InVals);
3899 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3900 SmallVectorImpl<SDValue> &InVals) const {
3901 SelectionDAG &DAG = CLI.DAG;
3903 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3904 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3905 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3906 SDValue Chain = CLI.Chain;
3907 SDValue Callee = CLI.Callee;
3908 bool &isTailCall = CLI.IsTailCall;
3909 CallingConv::ID CallConv = CLI.CallConv;
3910 bool isVarArg = CLI.IsVarArg;
3913 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3916 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3917 report_fatal_error("failed to perform tail call elimination on a call "
3918 "site marked musttail");
3920 if (Subtarget.isSVR4ABI()) {
3921 if (Subtarget.isPPC64())
3922 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3923 isTailCall, Outs, OutVals, Ins,
3926 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3927 isTailCall, Outs, OutVals, Ins,
3931 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3932 isTailCall, Outs, OutVals, Ins,
3937 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3938 CallingConv::ID CallConv, bool isVarArg,
3940 const SmallVectorImpl<ISD::OutputArg> &Outs,
3941 const SmallVectorImpl<SDValue> &OutVals,
3942 const SmallVectorImpl<ISD::InputArg> &Ins,
3943 SDLoc dl, SelectionDAG &DAG,
3944 SmallVectorImpl<SDValue> &InVals) const {
3945 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3946 // of the 32-bit SVR4 ABI stack frame layout.
3948 assert((CallConv == CallingConv::C ||
3949 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3951 unsigned PtrByteSize = 4;
3953 MachineFunction &MF = DAG.getMachineFunction();
3955 // Mark this function as potentially containing a function that contains a
3956 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3957 // and restoring the callers stack pointer in this functions epilog. This is
3958 // done because by tail calling the called function might overwrite the value
3959 // in this function's (MF) stack pointer stack slot 0(SP).
3960 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3961 CallConv == CallingConv::Fast)
3962 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3964 // Count how many bytes are to be pushed on the stack, including the linkage
3965 // area, parameter list area and the part of the local variable space which
3966 // contains copies of aggregates which are passed by value.
3968 // Assign locations to all of the outgoing arguments.
3969 SmallVector<CCValAssign, 16> ArgLocs;
3970 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3973 // Reserve space for the linkage area on the stack.
3974 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3978 // Handle fixed and variable vector arguments differently.
3979 // Fixed vector arguments go into registers as long as registers are
3980 // available. Variable vector arguments always go into memory.
3981 unsigned NumArgs = Outs.size();
3983 for (unsigned i = 0; i != NumArgs; ++i) {
3984 MVT ArgVT = Outs[i].VT;
3985 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3988 if (Outs[i].IsFixed) {
3989 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3992 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3998 errs() << "Call operand #" << i << " has unhandled type "
3999 << EVT(ArgVT).getEVTString() << "\n";
4001 llvm_unreachable(nullptr);
4005 // All arguments are treated the same.
4006 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4009 // Assign locations to all of the outgoing aggregate by value arguments.
4010 SmallVector<CCValAssign, 16> ByValArgLocs;
4011 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4012 ByValArgLocs, *DAG.getContext());
4014 // Reserve stack space for the allocations in CCInfo.
4015 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4017 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4019 // Size of the linkage area, parameter list area and the part of the local
4020 // space variable where copies of aggregates which are passed by value are
4022 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4024 // Calculate by how many bytes the stack has to be adjusted in case of tail
4025 // call optimization.
4026 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4028 // Adjust the stack pointer for the new arguments...
4029 // These operations are automatically eliminated by the prolog/epilog pass
4030 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4032 SDValue CallSeqStart = Chain;
4034 // Load the return address and frame pointer so it can be moved somewhere else
4037 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4040 // Set up a copy of the stack pointer for use loading and storing any
4041 // arguments that may not fit in the registers available for argument
4043 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4045 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4046 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4047 SmallVector<SDValue, 8> MemOpChains;
4049 bool seenFloatArg = false;
4050 // Walk the register/memloc assignments, inserting copies/loads.
4051 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4054 CCValAssign &VA = ArgLocs[i];
4055 SDValue Arg = OutVals[i];
4056 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4058 if (Flags.isByVal()) {
4059 // Argument is an aggregate which is passed by value, thus we need to
4060 // create a copy of it in the local variable space of the current stack
4061 // frame (which is the stack frame of the caller) and pass the address of
4062 // this copy to the callee.
4063 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4064 CCValAssign &ByValVA = ByValArgLocs[j++];
4065 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4067 // Memory reserved in the local variable space of the callers stack frame.
4068 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4070 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4071 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4073 // Create a copy of the argument in the local area of the current
4075 SDValue MemcpyCall =
4076 CreateCopyOfByValArgument(Arg, PtrOff,
4077 CallSeqStart.getNode()->getOperand(0),
4080 // This must go outside the CALLSEQ_START..END.
4081 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4082 CallSeqStart.getNode()->getOperand(1),
4084 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4085 NewCallSeqStart.getNode());
4086 Chain = CallSeqStart = NewCallSeqStart;
4088 // Pass the address of the aggregate copy on the stack either in a
4089 // physical register or in the parameter list area of the current stack
4090 // frame to the callee.
4094 if (VA.isRegLoc()) {
4095 if (Arg.getValueType() == MVT::i1)
4096 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4098 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4099 // Put argument in a physical register.
4100 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4102 // Put argument in the parameter list area of the current stack frame.
4103 assert(VA.isMemLoc());
4104 unsigned LocMemOffset = VA.getLocMemOffset();
4107 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4108 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4110 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4111 MachinePointerInfo(),
4114 // Calculate and remember argument location.
4115 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4121 if (!MemOpChains.empty())
4122 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4124 // Build a sequence of copy-to-reg nodes chained together with token chain
4125 // and flag operands which copy the outgoing args into the appropriate regs.
4127 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4128 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4129 RegsToPass[i].second, InFlag);
4130 InFlag = Chain.getValue(1);
4133 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4136 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4137 SDValue Ops[] = { Chain, InFlag };
4139 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4140 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4142 InFlag = Chain.getValue(1);
4146 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4147 false, TailCallArguments);
4149 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4150 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4154 // Copy an argument into memory, being careful to do this outside the
4155 // call sequence for the call to which the argument belongs.
4157 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4158 SDValue CallSeqStart,
4159 ISD::ArgFlagsTy Flags,
4162 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4163 CallSeqStart.getNode()->getOperand(0),
4165 // The MEMCPY must go outside the CALLSEQ_START..END.
4166 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4167 CallSeqStart.getNode()->getOperand(1),
4169 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4170 NewCallSeqStart.getNode());
4171 return NewCallSeqStart;
4175 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4176 CallingConv::ID CallConv, bool isVarArg,
4178 const SmallVectorImpl<ISD::OutputArg> &Outs,
4179 const SmallVectorImpl<SDValue> &OutVals,
4180 const SmallVectorImpl<ISD::InputArg> &Ins,
4181 SDLoc dl, SelectionDAG &DAG,
4182 SmallVectorImpl<SDValue> &InVals) const {
4184 bool isELFv2ABI = Subtarget.isELFv2ABI();
4185 bool isLittleEndian = Subtarget.isLittleEndian();
4186 unsigned NumOps = Outs.size();
4188 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4189 unsigned PtrByteSize = 8;
4191 MachineFunction &MF = DAG.getMachineFunction();
4193 // Mark this function as potentially containing a function that contains a
4194 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4195 // and restoring the callers stack pointer in this functions epilog. This is
4196 // done because by tail calling the called function might overwrite the value
4197 // in this function's (MF) stack pointer stack slot 0(SP).
4198 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4199 CallConv == CallingConv::Fast)
4200 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4202 // Count how many bytes are to be pushed on the stack, including the linkage
4203 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4204 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4205 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4206 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4208 unsigned NumBytes = LinkageSize;
4210 // Add up all the space actually used.
4211 for (unsigned i = 0; i != NumOps; ++i) {
4212 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4213 EVT ArgVT = Outs[i].VT;
4214 EVT OrigVT = Outs[i].ArgVT;
4216 /* Respect alignment of argument on the stack. */
4218 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4219 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4221 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4222 if (Flags.isInConsecutiveRegsLast())
4223 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4226 unsigned NumBytesActuallyUsed = NumBytes;
4228 // The prolog code of the callee may store up to 8 GPR argument registers to
4229 // the stack, allowing va_start to index over them in memory if its varargs.
4230 // Because we cannot tell if this is needed on the caller side, we have to
4231 // conservatively assume that it is needed. As such, make sure we have at
4232 // least enough stack space for the caller to store the 8 GPRs.
4233 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4234 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4236 // Tail call needs the stack to be aligned.
4237 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4238 CallConv == CallingConv::Fast)
4239 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4241 // Calculate by how many bytes the stack has to be adjusted in case of tail
4242 // call optimization.
4243 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4245 // To protect arguments on the stack from being clobbered in a tail call,
4246 // force all the loads to happen before doing any other lowering.
4248 Chain = DAG.getStackArgumentTokenFactor(Chain);
4250 // Adjust the stack pointer for the new arguments...
4251 // These operations are automatically eliminated by the prolog/epilog pass
4252 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4254 SDValue CallSeqStart = Chain;
4256 // Load the return address and frame pointer so it can be move somewhere else
4259 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4262 // Set up a copy of the stack pointer for use loading and storing any
4263 // arguments that may not fit in the registers available for argument
4265 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4267 // Figure out which arguments are going to go in registers, and which in
4268 // memory. Also, if this is a vararg function, floating point operations
4269 // must be stored to our stack, and loaded into integer regs as well, if
4270 // any integer regs are available for argument passing.
4271 unsigned ArgOffset = LinkageSize;
4272 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4274 static const MCPhysReg GPR[] = {
4275 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4276 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4278 static const MCPhysReg *FPR = GetFPR();
4280 static const MCPhysReg VR[] = {
4281 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4282 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4284 static const MCPhysReg VSRH[] = {
4285 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4286 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4289 const unsigned NumGPRs = array_lengthof(GPR);
4290 const unsigned NumFPRs = 13;
4291 const unsigned NumVRs = array_lengthof(VR);
4293 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4294 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4296 SmallVector<SDValue, 8> MemOpChains;
4297 for (unsigned i = 0; i != NumOps; ++i) {
4298 SDValue Arg = OutVals[i];
4299 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4300 EVT ArgVT = Outs[i].VT;
4301 EVT OrigVT = Outs[i].ArgVT;
4303 /* Respect alignment of argument on the stack. */
4305 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4306 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4308 /* Compute GPR index associated with argument offset. */
4309 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4310 GPR_idx = std::min(GPR_idx, NumGPRs);
4312 // PtrOff will be used to store the current argument to the stack if a
4313 // register cannot be found for it.
4316 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4318 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4320 // Promote integers to 64-bit values.
4321 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4322 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4323 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4324 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4327 // FIXME memcpy is used way more than necessary. Correctness first.
4328 // Note: "by value" is code for passing a structure by value, not
4330 if (Flags.isByVal()) {
4331 // Note: Size includes alignment padding, so
4332 // struct x { short a; char b; }
4333 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4334 // These are the proper values we need for right-justifying the
4335 // aggregate in a parameter register.
4336 unsigned Size = Flags.getByValSize();
4338 // An empty aggregate parameter takes up no storage and no
4343 // All aggregates smaller than 8 bytes must be passed right-justified.
4344 if (Size==1 || Size==2 || Size==4) {
4345 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4346 if (GPR_idx != NumGPRs) {
4347 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4348 MachinePointerInfo(), VT,
4349 false, false, false, 0);
4350 MemOpChains.push_back(Load.getValue(1));
4351 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4353 ArgOffset += PtrByteSize;
4358 if (GPR_idx == NumGPRs && Size < 8) {
4359 SDValue AddPtr = PtrOff;
4360 if (!isLittleEndian) {
4361 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4362 PtrOff.getValueType());
4363 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4365 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4368 ArgOffset += PtrByteSize;
4371 // Copy entire object into memory. There are cases where gcc-generated
4372 // code assumes it is there, even if it could be put entirely into
4373 // registers. (This is not what the doc says.)
4375 // FIXME: The above statement is likely due to a misunderstanding of the
4376 // documents. All arguments must be copied into the parameter area BY
4377 // THE CALLEE in the event that the callee takes the address of any
4378 // formal argument. That has not yet been implemented. However, it is
4379 // reasonable to use the stack area as a staging area for the register
4382 // Skip this for small aggregates, as we will use the same slot for a
4383 // right-justified copy, below.
4385 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4389 // When a register is available, pass a small aggregate right-justified.
4390 if (Size < 8 && GPR_idx != NumGPRs) {
4391 // The easiest way to get this right-justified in a register
4392 // is to copy the structure into the rightmost portion of a
4393 // local variable slot, then load the whole slot into the
4395 // FIXME: The memcpy seems to produce pretty awful code for
4396 // small aggregates, particularly for packed ones.
4397 // FIXME: It would be preferable to use the slot in the
4398 // parameter save area instead of a new local variable.
4399 SDValue AddPtr = PtrOff;
4400 if (!isLittleEndian) {
4401 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4402 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4404 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4408 // Load the slot into the register.
4409 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4410 MachinePointerInfo(),
4411 false, false, false, 0);
4412 MemOpChains.push_back(Load.getValue(1));
4413 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4415 // Done with this argument.
4416 ArgOffset += PtrByteSize;
4420 // For aggregates larger than PtrByteSize, copy the pieces of the
4421 // object that fit into registers from the parameter save area.
4422 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4423 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4424 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4425 if (GPR_idx != NumGPRs) {
4426 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4427 MachinePointerInfo(),
4428 false, false, false, 0);
4429 MemOpChains.push_back(Load.getValue(1));
4430 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4431 ArgOffset += PtrByteSize;
4433 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4440 switch (Arg.getSimpleValueType().SimpleTy) {
4441 default: llvm_unreachable("Unexpected ValueType for argument!");
4445 // These can be scalar arguments or elements of an integer array type
4446 // passed directly. Clang may use those instead of "byval" aggregate
4447 // types to avoid forcing arguments to memory unnecessarily.
4448 if (GPR_idx != NumGPRs) {
4449 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4451 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4452 true, isTailCall, false, MemOpChains,
4453 TailCallArguments, dl);
4455 ArgOffset += PtrByteSize;
4459 // These can be scalar arguments or elements of a float array type
4460 // passed directly. The latter are used to implement ELFv2 homogenous
4461 // float aggregates.
4463 // Named arguments go into FPRs first, and once they overflow, the
4464 // remaining arguments go into GPRs and then the parameter save area.
4465 // Unnamed arguments for vararg functions always go to GPRs and
4466 // then the parameter save area. For now, put all arguments to vararg
4467 // routines always in both locations (FPR *and* GPR or stack slot).
4468 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4470 // First load the argument into the next available FPR.
4471 if (FPR_idx != NumFPRs)
4472 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4474 // Next, load the argument into GPR or stack slot if needed.
4475 if (!NeedGPROrStack)
4477 else if (GPR_idx != NumGPRs) {
4478 // In the non-vararg case, this can only ever happen in the
4479 // presence of f32 array types, since otherwise we never run
4480 // out of FPRs before running out of GPRs.
4483 // Double values are always passed in a single GPR.
4484 if (Arg.getValueType() != MVT::f32) {
4485 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4487 // Non-array float values are extended and passed in a GPR.
4488 } else if (!Flags.isInConsecutiveRegs()) {
4489 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4490 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4492 // If we have an array of floats, we collect every odd element
4493 // together with its predecessor into one GPR.
4494 } else if (ArgOffset % PtrByteSize != 0) {
4496 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4497 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4498 if (!isLittleEndian)
4500 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4502 // The final element, if even, goes into the first half of a GPR.
4503 } else if (Flags.isInConsecutiveRegsLast()) {
4504 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4505 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4506 if (!isLittleEndian)
4507 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4508 DAG.getConstant(32, MVT::i32));
4510 // Non-final even elements are skipped; they will be handled
4511 // together the with subsequent argument on the next go-around.
4515 if (ArgVal.getNode())
4516 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4518 // Single-precision floating-point values are mapped to the
4519 // second (rightmost) word of the stack doubleword.
4520 if (Arg.getValueType() == MVT::f32 &&
4521 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4522 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4523 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4526 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4527 true, isTailCall, false, MemOpChains,
4528 TailCallArguments, dl);
4530 // When passing an array of floats, the array occupies consecutive
4531 // space in the argument area; only round up to the next doubleword
4532 // at the end of the array. Otherwise, each float takes 8 bytes.
4533 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4534 Flags.isInConsecutiveRegs()) ? 4 : 8;
4535 if (Flags.isInConsecutiveRegsLast())
4536 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4545 // These can be scalar arguments or elements of a vector array type
4546 // passed directly. The latter are used to implement ELFv2 homogenous
4547 // vector aggregates.
4549 // For a varargs call, named arguments go into VRs or on the stack as
4550 // usual; unnamed arguments always go to the stack or the corresponding
4551 // GPRs when within range. For now, we always put the value in both
4552 // locations (or even all three).
4554 // We could elide this store in the case where the object fits
4555 // entirely in R registers. Maybe later.
4556 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4557 MachinePointerInfo(), false, false, 0);
4558 MemOpChains.push_back(Store);
4559 if (VR_idx != NumVRs) {
4560 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4561 MachinePointerInfo(),
4562 false, false, false, 0);
4563 MemOpChains.push_back(Load.getValue(1));
4565 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4566 Arg.getSimpleValueType() == MVT::v2i64) ?
4567 VSRH[VR_idx] : VR[VR_idx];
4570 RegsToPass.push_back(std::make_pair(VReg, Load));
4573 for (unsigned i=0; i<16; i+=PtrByteSize) {
4574 if (GPR_idx == NumGPRs)
4576 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4577 DAG.getConstant(i, PtrVT));
4578 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4579 false, false, false, 0);
4580 MemOpChains.push_back(Load.getValue(1));
4581 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4586 // Non-varargs Altivec params go into VRs or on the stack.
4587 if (VR_idx != NumVRs) {
4588 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4589 Arg.getSimpleValueType() == MVT::v2i64) ?
4590 VSRH[VR_idx] : VR[VR_idx];
4593 RegsToPass.push_back(std::make_pair(VReg, Arg));
4595 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4596 true, isTailCall, true, MemOpChains,
4597 TailCallArguments, dl);
4604 assert(NumBytesActuallyUsed == ArgOffset);
4605 (void)NumBytesActuallyUsed;
4607 if (!MemOpChains.empty())
4608 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4610 // Check if this is an indirect call (MTCTR/BCTRL).
4611 // See PrepareCall() for more information about calls through function
4612 // pointers in the 64-bit SVR4 ABI.
4614 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4615 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4616 // Load r2 into a virtual register and store it to the TOC save area.
4617 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4618 // TOC save area offset.
4619 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4620 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4621 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4622 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4624 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4625 // This does not mean the MTCTR instruction must use R12; it's easier
4626 // to model this as an extra parameter, so do that.
4628 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4631 // Build a sequence of copy-to-reg nodes chained together with token chain
4632 // and flag operands which copy the outgoing args into the appropriate regs.
4634 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4635 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4636 RegsToPass[i].second, InFlag);
4637 InFlag = Chain.getValue(1);
4641 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4642 FPOp, true, TailCallArguments);
4644 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4645 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4650 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4651 CallingConv::ID CallConv, bool isVarArg,
4653 const SmallVectorImpl<ISD::OutputArg> &Outs,
4654 const SmallVectorImpl<SDValue> &OutVals,
4655 const SmallVectorImpl<ISD::InputArg> &Ins,
4656 SDLoc dl, SelectionDAG &DAG,
4657 SmallVectorImpl<SDValue> &InVals) const {
4659 unsigned NumOps = Outs.size();
4661 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4662 bool isPPC64 = PtrVT == MVT::i64;
4663 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4665 MachineFunction &MF = DAG.getMachineFunction();
4667 // Mark this function as potentially containing a function that contains a
4668 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4669 // and restoring the callers stack pointer in this functions epilog. This is
4670 // done because by tail calling the called function might overwrite the value
4671 // in this function's (MF) stack pointer stack slot 0(SP).
4672 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4673 CallConv == CallingConv::Fast)
4674 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4676 // Count how many bytes are to be pushed on the stack, including the linkage
4677 // area, and parameter passing area. We start with 24/48 bytes, which is
4678 // prereserved space for [SP][CR][LR][3 x unused].
4679 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4681 unsigned NumBytes = LinkageSize;
4683 // Add up all the space actually used.
4684 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4685 // they all go in registers, but we must reserve stack space for them for
4686 // possible use by the caller. In varargs or 64-bit calls, parameters are
4687 // assigned stack space in order, with padding so Altivec parameters are
4689 unsigned nAltivecParamsAtEnd = 0;
4690 for (unsigned i = 0; i != NumOps; ++i) {
4691 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4692 EVT ArgVT = Outs[i].VT;
4693 // Varargs Altivec parameters are padded to a 16 byte boundary.
4694 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4695 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4696 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4697 if (!isVarArg && !isPPC64) {
4698 // Non-varargs Altivec parameters go after all the non-Altivec
4699 // parameters; handle those later so we know how much padding we need.
4700 nAltivecParamsAtEnd++;
4703 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4704 NumBytes = ((NumBytes+15)/16)*16;
4706 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4709 // Allow for Altivec parameters at the end, if needed.
4710 if (nAltivecParamsAtEnd) {
4711 NumBytes = ((NumBytes+15)/16)*16;
4712 NumBytes += 16*nAltivecParamsAtEnd;
4715 // The prolog code of the callee may store up to 8 GPR argument registers to
4716 // the stack, allowing va_start to index over them in memory if its varargs.
4717 // Because we cannot tell if this is needed on the caller side, we have to
4718 // conservatively assume that it is needed. As such, make sure we have at
4719 // least enough stack space for the caller to store the 8 GPRs.
4720 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4722 // Tail call needs the stack to be aligned.
4723 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4724 CallConv == CallingConv::Fast)
4725 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4727 // Calculate by how many bytes the stack has to be adjusted in case of tail
4728 // call optimization.
4729 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4731 // To protect arguments on the stack from being clobbered in a tail call,
4732 // force all the loads to happen before doing any other lowering.
4734 Chain = DAG.getStackArgumentTokenFactor(Chain);
4736 // Adjust the stack pointer for the new arguments...
4737 // These operations are automatically eliminated by the prolog/epilog pass
4738 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4740 SDValue CallSeqStart = Chain;
4742 // Load the return address and frame pointer so it can be move somewhere else
4745 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4748 // Set up a copy of the stack pointer for use loading and storing any
4749 // arguments that may not fit in the registers available for argument
4753 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4755 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4757 // Figure out which arguments are going to go in registers, and which in
4758 // memory. Also, if this is a vararg function, floating point operations
4759 // must be stored to our stack, and loaded into integer regs as well, if
4760 // any integer regs are available for argument passing.
4761 unsigned ArgOffset = LinkageSize;
4762 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4764 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4765 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4766 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4768 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4769 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4770 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4772 static const MCPhysReg *FPR = GetFPR();
4774 static const MCPhysReg VR[] = {
4775 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4776 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4778 const unsigned NumGPRs = array_lengthof(GPR_32);
4779 const unsigned NumFPRs = 13;
4780 const unsigned NumVRs = array_lengthof(VR);
4782 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4784 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4785 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4787 SmallVector<SDValue, 8> MemOpChains;
4788 for (unsigned i = 0; i != NumOps; ++i) {
4789 SDValue Arg = OutVals[i];
4790 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4792 // PtrOff will be used to store the current argument to the stack if a
4793 // register cannot be found for it.
4796 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4798 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4800 // On PPC64, promote integers to 64-bit values.
4801 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4802 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4803 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4804 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4807 // FIXME memcpy is used way more than necessary. Correctness first.
4808 // Note: "by value" is code for passing a structure by value, not
4810 if (Flags.isByVal()) {
4811 unsigned Size = Flags.getByValSize();
4812 // Very small objects are passed right-justified. Everything else is
4813 // passed left-justified.
4814 if (Size==1 || Size==2) {
4815 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4816 if (GPR_idx != NumGPRs) {
4817 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4818 MachinePointerInfo(), VT,
4819 false, false, false, 0);
4820 MemOpChains.push_back(Load.getValue(1));
4821 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4823 ArgOffset += PtrByteSize;
4825 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4826 PtrOff.getValueType());
4827 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4828 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4831 ArgOffset += PtrByteSize;
4835 // Copy entire object into memory. There are cases where gcc-generated
4836 // code assumes it is there, even if it could be put entirely into
4837 // registers. (This is not what the doc says.)
4838 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4842 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4843 // copy the pieces of the object that fit into registers from the
4844 // parameter save area.
4845 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4846 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4847 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4848 if (GPR_idx != NumGPRs) {
4849 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4850 MachinePointerInfo(),
4851 false, false, false, 0);
4852 MemOpChains.push_back(Load.getValue(1));
4853 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4854 ArgOffset += PtrByteSize;
4856 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4863 switch (Arg.getSimpleValueType().SimpleTy) {
4864 default: llvm_unreachable("Unexpected ValueType for argument!");
4868 if (GPR_idx != NumGPRs) {
4869 if (Arg.getValueType() == MVT::i1)
4870 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4872 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4874 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4875 isPPC64, isTailCall, false, MemOpChains,
4876 TailCallArguments, dl);
4878 ArgOffset += PtrByteSize;
4882 if (FPR_idx != NumFPRs) {
4883 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4886 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4887 MachinePointerInfo(), false, false, 0);
4888 MemOpChains.push_back(Store);
4890 // Float varargs are always shadowed in available integer registers
4891 if (GPR_idx != NumGPRs) {
4892 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4893 MachinePointerInfo(), false, false,
4895 MemOpChains.push_back(Load.getValue(1));
4896 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4898 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4899 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4900 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4901 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4902 MachinePointerInfo(),
4903 false, false, false, 0);
4904 MemOpChains.push_back(Load.getValue(1));
4905 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4908 // If we have any FPRs remaining, we may also have GPRs remaining.
4909 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4911 if (GPR_idx != NumGPRs)
4913 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4914 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4918 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4919 isPPC64, isTailCall, false, MemOpChains,
4920 TailCallArguments, dl);
4924 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4931 // These go aligned on the stack, or in the corresponding R registers
4932 // when within range. The Darwin PPC ABI doc claims they also go in
4933 // V registers; in fact gcc does this only for arguments that are
4934 // prototyped, not for those that match the ... We do it for all
4935 // arguments, seems to work.
4936 while (ArgOffset % 16 !=0) {
4937 ArgOffset += PtrByteSize;
4938 if (GPR_idx != NumGPRs)
4941 // We could elide this store in the case where the object fits
4942 // entirely in R registers. Maybe later.
4943 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4944 DAG.getConstant(ArgOffset, PtrVT));
4945 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4946 MachinePointerInfo(), false, false, 0);
4947 MemOpChains.push_back(Store);
4948 if (VR_idx != NumVRs) {
4949 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4950 MachinePointerInfo(),
4951 false, false, false, 0);
4952 MemOpChains.push_back(Load.getValue(1));
4953 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4956 for (unsigned i=0; i<16; i+=PtrByteSize) {
4957 if (GPR_idx == NumGPRs)
4959 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4960 DAG.getConstant(i, PtrVT));
4961 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4962 false, false, false, 0);
4963 MemOpChains.push_back(Load.getValue(1));
4964 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4969 // Non-varargs Altivec params generally go in registers, but have
4970 // stack space allocated at the end.
4971 if (VR_idx != NumVRs) {
4972 // Doesn't have GPR space allocated.
4973 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4974 } else if (nAltivecParamsAtEnd==0) {
4975 // We are emitting Altivec params in order.
4976 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4977 isPPC64, isTailCall, true, MemOpChains,
4978 TailCallArguments, dl);
4984 // If all Altivec parameters fit in registers, as they usually do,
4985 // they get stack space following the non-Altivec parameters. We
4986 // don't track this here because nobody below needs it.
4987 // If there are more Altivec parameters than fit in registers emit
4989 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4991 // Offset is aligned; skip 1st 12 params which go in V registers.
4992 ArgOffset = ((ArgOffset+15)/16)*16;
4994 for (unsigned i = 0; i != NumOps; ++i) {
4995 SDValue Arg = OutVals[i];
4996 EVT ArgType = Outs[i].VT;
4997 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4998 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5001 // We are emitting Altivec params in order.
5002 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5003 isPPC64, isTailCall, true, MemOpChains,
5004 TailCallArguments, dl);
5011 if (!MemOpChains.empty())
5012 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5014 // On Darwin, R12 must contain the address of an indirect callee. This does
5015 // not mean the MTCTR instruction must use R12; it's easier to model this as
5016 // an extra parameter, so do that.
5018 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5019 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5020 !isBLACompatibleAddress(Callee, DAG))
5021 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5022 PPC::R12), Callee));
5024 // Build a sequence of copy-to-reg nodes chained together with token chain
5025 // and flag operands which copy the outgoing args into the appropriate regs.
5027 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5028 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5029 RegsToPass[i].second, InFlag);
5030 InFlag = Chain.getValue(1);
5034 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5035 FPOp, true, TailCallArguments);
5037 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5038 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5043 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5044 MachineFunction &MF, bool isVarArg,
5045 const SmallVectorImpl<ISD::OutputArg> &Outs,
5046 LLVMContext &Context) const {
5047 SmallVector<CCValAssign, 16> RVLocs;
5048 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5049 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5053 PPCTargetLowering::LowerReturn(SDValue Chain,
5054 CallingConv::ID CallConv, bool isVarArg,
5055 const SmallVectorImpl<ISD::OutputArg> &Outs,
5056 const SmallVectorImpl<SDValue> &OutVals,
5057 SDLoc dl, SelectionDAG &DAG) const {
5059 SmallVector<CCValAssign, 16> RVLocs;
5060 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5062 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5065 SmallVector<SDValue, 4> RetOps(1, Chain);
5067 // Copy the result values into the output registers.
5068 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5069 CCValAssign &VA = RVLocs[i];
5070 assert(VA.isRegLoc() && "Can only return in registers!");
5072 SDValue Arg = OutVals[i];
5074 switch (VA.getLocInfo()) {
5075 default: llvm_unreachable("Unknown loc info!");
5076 case CCValAssign::Full: break;
5077 case CCValAssign::AExt:
5078 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5080 case CCValAssign::ZExt:
5081 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5083 case CCValAssign::SExt:
5084 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5088 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5089 Flag = Chain.getValue(1);
5090 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5093 RetOps[0] = Chain; // Update chain.
5095 // Add the flag if we have it.
5097 RetOps.push_back(Flag);
5099 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5102 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5103 const PPCSubtarget &Subtarget) const {
5104 // When we pop the dynamic allocation we need to restore the SP link.
5107 // Get the corect type for pointers.
5108 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5110 // Construct the stack pointer operand.
5111 bool isPPC64 = Subtarget.isPPC64();
5112 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5113 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5115 // Get the operands for the STACKRESTORE.
5116 SDValue Chain = Op.getOperand(0);
5117 SDValue SaveSP = Op.getOperand(1);
5119 // Load the old link SP.
5120 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5121 MachinePointerInfo(),
5122 false, false, false, 0);
5124 // Restore the stack pointer.
5125 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5127 // Store the old link SP.
5128 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5135 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5136 MachineFunction &MF = DAG.getMachineFunction();
5137 bool isPPC64 = Subtarget.isPPC64();
5138 bool isDarwinABI = Subtarget.isDarwinABI();
5139 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5141 // Get current frame pointer save index. The users of this index will be
5142 // primarily DYNALLOC instructions.
5143 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5144 int RASI = FI->getReturnAddrSaveIndex();
5146 // If the frame pointer save index hasn't been defined yet.
5148 // Find out what the fix offset of the frame pointer save area.
5149 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5150 // Allocate the frame index for frame pointer save area.
5151 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5153 FI->setReturnAddrSaveIndex(RASI);
5155 return DAG.getFrameIndex(RASI, PtrVT);
5159 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5160 MachineFunction &MF = DAG.getMachineFunction();
5161 bool isPPC64 = Subtarget.isPPC64();
5162 bool isDarwinABI = Subtarget.isDarwinABI();
5163 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5165 // Get current frame pointer save index. The users of this index will be
5166 // primarily DYNALLOC instructions.
5167 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5168 int FPSI = FI->getFramePointerSaveIndex();
5170 // If the frame pointer save index hasn't been defined yet.
5172 // Find out what the fix offset of the frame pointer save area.
5173 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5176 // Allocate the frame index for frame pointer save area.
5177 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5179 FI->setFramePointerSaveIndex(FPSI);
5181 return DAG.getFrameIndex(FPSI, PtrVT);
5184 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5186 const PPCSubtarget &Subtarget) const {
5188 SDValue Chain = Op.getOperand(0);
5189 SDValue Size = Op.getOperand(1);
5192 // Get the corect type for pointers.
5193 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5195 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5196 DAG.getConstant(0, PtrVT), Size);
5197 // Construct a node for the frame pointer save index.
5198 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5199 // Build a DYNALLOC node.
5200 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5201 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5202 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5205 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5206 SelectionDAG &DAG) const {
5208 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5209 DAG.getVTList(MVT::i32, MVT::Other),
5210 Op.getOperand(0), Op.getOperand(1));
5213 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5214 SelectionDAG &DAG) const {
5216 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5217 Op.getOperand(0), Op.getOperand(1));
5220 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5221 assert(Op.getValueType() == MVT::i1 &&
5222 "Custom lowering only for i1 loads");
5224 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5227 LoadSDNode *LD = cast<LoadSDNode>(Op);
5229 SDValue Chain = LD->getChain();
5230 SDValue BasePtr = LD->getBasePtr();
5231 MachineMemOperand *MMO = LD->getMemOperand();
5233 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5234 BasePtr, MVT::i8, MMO);
5235 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5237 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5238 return DAG.getMergeValues(Ops, dl);
5241 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5242 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5243 "Custom lowering only for i1 stores");
5245 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5248 StoreSDNode *ST = cast<StoreSDNode>(Op);
5250 SDValue Chain = ST->getChain();
5251 SDValue BasePtr = ST->getBasePtr();
5252 SDValue Value = ST->getValue();
5253 MachineMemOperand *MMO = ST->getMemOperand();
5255 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5256 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5259 // FIXME: Remove this once the ANDI glue bug is fixed:
5260 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5261 assert(Op.getValueType() == MVT::i1 &&
5262 "Custom lowering only for i1 results");
5265 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5269 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5271 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5272 // Not FP? Not a fsel.
5273 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5274 !Op.getOperand(2).getValueType().isFloatingPoint())
5277 // We might be able to do better than this under some circumstances, but in
5278 // general, fsel-based lowering of select is a finite-math-only optimization.
5279 // For more information, see section F.3 of the 2.06 ISA specification.
5280 if (!DAG.getTarget().Options.NoInfsFPMath ||
5281 !DAG.getTarget().Options.NoNaNsFPMath)
5284 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5286 EVT ResVT = Op.getValueType();
5287 EVT CmpVT = Op.getOperand(0).getValueType();
5288 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5289 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5292 // If the RHS of the comparison is a 0.0, we don't need to do the
5293 // subtraction at all.
5295 if (isFloatingPointZero(RHS))
5297 default: break; // SETUO etc aren't handled by fsel.
5301 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5302 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5303 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5304 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5305 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5306 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5307 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5310 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5313 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5314 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5315 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5318 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5321 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5322 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5323 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5324 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5329 default: break; // SETUO etc aren't handled by fsel.
5333 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5334 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5335 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5336 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5337 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5338 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5339 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5340 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5343 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5344 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5345 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5346 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5349 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5350 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5351 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5352 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5355 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5356 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5357 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5358 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5361 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5362 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5363 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5364 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5369 // FIXME: Split this code up when LegalizeDAGTypes lands.
5370 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5372 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5373 SDValue Src = Op.getOperand(0);
5374 if (Src.getValueType() == MVT::f32)
5375 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5378 switch (Op.getSimpleValueType().SimpleTy) {
5379 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5381 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5382 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5387 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5388 "i64 FP_TO_UINT is supported only with FPCVT");
5389 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5395 // Convert the FP value to an int value through memory.
5396 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5397 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5398 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5399 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5400 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5402 // Emit a store to the stack slot.
5405 MachineFunction &MF = DAG.getMachineFunction();
5406 MachineMemOperand *MMO =
5407 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5408 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5409 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5410 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5412 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5413 MPI, false, false, 0);
5415 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5417 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5418 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5419 DAG.getConstant(4, FIPtr.getValueType()));
5420 MPI = MachinePointerInfo();
5423 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5424 false, false, false, 0);
5427 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5428 SelectionDAG &DAG) const {
5430 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5431 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5434 if (Op.getOperand(0).getValueType() == MVT::i1)
5435 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5436 DAG.getConstantFP(1.0, Op.getValueType()),
5437 DAG.getConstantFP(0.0, Op.getValueType()));
5439 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5440 "UINT_TO_FP is supported only with FPCVT");
5442 // If we have FCFIDS, then use it when converting to single-precision.
5443 // Otherwise, convert to double-precision and then round.
5444 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5445 (Op.getOpcode() == ISD::UINT_TO_FP ?
5446 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5447 (Op.getOpcode() == ISD::UINT_TO_FP ?
5448 PPCISD::FCFIDU : PPCISD::FCFID);
5449 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5450 MVT::f32 : MVT::f64;
5452 if (Op.getOperand(0).getValueType() == MVT::i64) {
5453 SDValue SINT = Op.getOperand(0);
5454 // When converting to single-precision, we actually need to convert
5455 // to double-precision first and then round to single-precision.
5456 // To avoid double-rounding effects during that operation, we have
5457 // to prepare the input operand. Bits that might be truncated when
5458 // converting to double-precision are replaced by a bit that won't
5459 // be lost at this stage, but is below the single-precision rounding
5462 // However, if -enable-unsafe-fp-math is in effect, accept double
5463 // rounding to avoid the extra overhead.
5464 if (Op.getValueType() == MVT::f32 &&
5465 !Subtarget.hasFPCVT() &&
5466 !DAG.getTarget().Options.UnsafeFPMath) {
5468 // Twiddle input to make sure the low 11 bits are zero. (If this
5469 // is the case, we are guaranteed the value will fit into the 53 bit
5470 // mantissa of an IEEE double-precision value without rounding.)
5471 // If any of those low 11 bits were not zero originally, make sure
5472 // bit 12 (value 2048) is set instead, so that the final rounding
5473 // to single-precision gets the correct result.
5474 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5475 SINT, DAG.getConstant(2047, MVT::i64));
5476 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5477 Round, DAG.getConstant(2047, MVT::i64));
5478 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5479 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5480 Round, DAG.getConstant(-2048, MVT::i64));
5482 // However, we cannot use that value unconditionally: if the magnitude
5483 // of the input value is small, the bit-twiddling we did above might
5484 // end up visibly changing the output. Fortunately, in that case, we
5485 // don't need to twiddle bits since the original input will convert
5486 // exactly to double-precision floating-point already. Therefore,
5487 // construct a conditional to use the original value if the top 11
5488 // bits are all sign-bit copies, and use the rounded value computed
5490 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5491 SINT, DAG.getConstant(53, MVT::i32));
5492 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5493 Cond, DAG.getConstant(1, MVT::i64));
5494 Cond = DAG.getSetCC(dl, MVT::i32,
5495 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5497 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5500 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5501 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5503 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5504 FP = DAG.getNode(ISD::FP_ROUND, dl,
5505 MVT::f32, FP, DAG.getIntPtrConstant(0));
5509 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5510 "Unhandled INT_TO_FP type in custom expander!");
5511 // Since we only generate this in 64-bit mode, we can take advantage of
5512 // 64-bit registers. In particular, sign extend the input value into the
5513 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5514 // then lfd it and fcfid it.
5515 MachineFunction &MF = DAG.getMachineFunction();
5516 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5517 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5520 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5521 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5522 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5524 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5525 MachinePointerInfo::getFixedStack(FrameIdx),
5528 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5529 "Expected an i32 store");
5530 MachineMemOperand *MMO =
5531 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5532 MachineMemOperand::MOLoad, 4, 4);
5533 SDValue Ops[] = { Store, FIdx };
5534 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5535 PPCISD::LFIWZX : PPCISD::LFIWAX,
5536 dl, DAG.getVTList(MVT::f64, MVT::Other),
5537 Ops, MVT::i32, MMO);
5539 assert(Subtarget.isPPC64() &&
5540 "i32->FP without LFIWAX supported only on PPC64");
5542 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5543 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5545 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5548 // STD the extended value into the stack slot.
5549 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5550 MachinePointerInfo::getFixedStack(FrameIdx),
5553 // Load the value as a double.
5554 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5555 MachinePointerInfo::getFixedStack(FrameIdx),
5556 false, false, false, 0);
5559 // FCFID it and return it.
5560 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5561 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5562 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5566 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5567 SelectionDAG &DAG) const {
5570 The rounding mode is in bits 30:31 of FPSR, and has the following
5577 FLT_ROUNDS, on the other hand, expects the following:
5584 To perform the conversion, we do:
5585 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5588 MachineFunction &MF = DAG.getMachineFunction();
5589 EVT VT = Op.getValueType();
5590 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5592 // Save FP Control Word to register
5594 MVT::f64, // return register
5595 MVT::Glue // unused in this context
5597 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5599 // Save FP register to stack slot
5600 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5601 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5602 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5603 StackSlot, MachinePointerInfo(), false, false,0);
5605 // Load FP Control Word from low 32 bits of stack slot.
5606 SDValue Four = DAG.getConstant(4, PtrVT);
5607 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5608 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5609 false, false, false, 0);
5611 // Transform as necessary
5613 DAG.getNode(ISD::AND, dl, MVT::i32,
5614 CWD, DAG.getConstant(3, MVT::i32));
5616 DAG.getNode(ISD::SRL, dl, MVT::i32,
5617 DAG.getNode(ISD::AND, dl, MVT::i32,
5618 DAG.getNode(ISD::XOR, dl, MVT::i32,
5619 CWD, DAG.getConstant(3, MVT::i32)),
5620 DAG.getConstant(3, MVT::i32)),
5621 DAG.getConstant(1, MVT::i32));
5624 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5626 return DAG.getNode((VT.getSizeInBits() < 16 ?
5627 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5630 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5631 EVT VT = Op.getValueType();
5632 unsigned BitWidth = VT.getSizeInBits();
5634 assert(Op.getNumOperands() == 3 &&
5635 VT == Op.getOperand(1).getValueType() &&
5638 // Expand into a bunch of logical ops. Note that these ops
5639 // depend on the PPC behavior for oversized shift amounts.
5640 SDValue Lo = Op.getOperand(0);
5641 SDValue Hi = Op.getOperand(1);
5642 SDValue Amt = Op.getOperand(2);
5643 EVT AmtVT = Amt.getValueType();
5645 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5646 DAG.getConstant(BitWidth, AmtVT), Amt);
5647 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5648 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5649 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5650 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5651 DAG.getConstant(-BitWidth, AmtVT));
5652 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5653 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5654 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5655 SDValue OutOps[] = { OutLo, OutHi };
5656 return DAG.getMergeValues(OutOps, dl);
5659 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5660 EVT VT = Op.getValueType();
5662 unsigned BitWidth = VT.getSizeInBits();
5663 assert(Op.getNumOperands() == 3 &&
5664 VT == Op.getOperand(1).getValueType() &&
5667 // Expand into a bunch of logical ops. Note that these ops
5668 // depend on the PPC behavior for oversized shift amounts.
5669 SDValue Lo = Op.getOperand(0);
5670 SDValue Hi = Op.getOperand(1);
5671 SDValue Amt = Op.getOperand(2);
5672 EVT AmtVT = Amt.getValueType();
5674 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5675 DAG.getConstant(BitWidth, AmtVT), Amt);
5676 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5677 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5678 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5679 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5680 DAG.getConstant(-BitWidth, AmtVT));
5681 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5682 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5683 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5684 SDValue OutOps[] = { OutLo, OutHi };
5685 return DAG.getMergeValues(OutOps, dl);
5688 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5690 EVT VT = Op.getValueType();
5691 unsigned BitWidth = VT.getSizeInBits();
5692 assert(Op.getNumOperands() == 3 &&
5693 VT == Op.getOperand(1).getValueType() &&
5696 // Expand into a bunch of logical ops, followed by a select_cc.
5697 SDValue Lo = Op.getOperand(0);
5698 SDValue Hi = Op.getOperand(1);
5699 SDValue Amt = Op.getOperand(2);
5700 EVT AmtVT = Amt.getValueType();
5702 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5703 DAG.getConstant(BitWidth, AmtVT), Amt);
5704 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5705 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5706 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5707 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5708 DAG.getConstant(-BitWidth, AmtVT));
5709 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5710 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5711 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5712 Tmp4, Tmp6, ISD::SETLE);
5713 SDValue OutOps[] = { OutLo, OutHi };
5714 return DAG.getMergeValues(OutOps, dl);
5717 //===----------------------------------------------------------------------===//
5718 // Vector related lowering.
5721 /// BuildSplatI - Build a canonical splati of Val with an element size of
5722 /// SplatSize. Cast the result to VT.
5723 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5724 SelectionDAG &DAG, SDLoc dl) {
5725 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5727 static const EVT VTys[] = { // canonical VT to use for each size.
5728 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5731 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5733 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5737 EVT CanonicalVT = VTys[SplatSize-1];
5739 // Build a canonical splat for this value.
5740 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5741 SmallVector<SDValue, 8> Ops;
5742 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5743 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5744 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5747 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5748 /// specified intrinsic ID.
5749 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5750 SelectionDAG &DAG, SDLoc dl,
5751 EVT DestVT = MVT::Other) {
5752 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5753 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5754 DAG.getConstant(IID, MVT::i32), Op);
5757 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5758 /// specified intrinsic ID.
5759 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5760 SelectionDAG &DAG, SDLoc dl,
5761 EVT DestVT = MVT::Other) {
5762 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5763 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5764 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5767 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5768 /// specified intrinsic ID.
5769 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5770 SDValue Op2, SelectionDAG &DAG,
5771 SDLoc dl, EVT DestVT = MVT::Other) {
5772 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5773 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5774 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5778 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5779 /// amount. The result has the specified value type.
5780 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5781 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5782 // Force LHS/RHS to be the right type.
5783 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5784 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5787 for (unsigned i = 0; i != 16; ++i)
5789 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5790 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5793 // If this is a case we can't handle, return null and let the default
5794 // expansion code take care of it. If we CAN select this case, and if it
5795 // selects to a single instruction, return Op. Otherwise, if we can codegen
5796 // this case more efficiently than a constant pool load, lower it to the
5797 // sequence of ops that should be used.
5798 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5799 SelectionDAG &DAG) const {
5801 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5802 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5804 // Check if this is a splat of a constant value.
5805 APInt APSplatBits, APSplatUndef;
5806 unsigned SplatBitSize;
5808 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5809 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5812 unsigned SplatBits = APSplatBits.getZExtValue();
5813 unsigned SplatUndef = APSplatUndef.getZExtValue();
5814 unsigned SplatSize = SplatBitSize / 8;
5816 // First, handle single instruction cases.
5819 if (SplatBits == 0) {
5820 // Canonicalize all zero vectors to be v4i32.
5821 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5822 SDValue Z = DAG.getConstant(0, MVT::i32);
5823 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5824 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5829 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5830 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5832 if (SextVal >= -16 && SextVal <= 15)
5833 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5836 // Two instruction sequences.
5838 // If this value is in the range [-32,30] and is even, use:
5839 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5840 // If this value is in the range [17,31] and is odd, use:
5841 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5842 // If this value is in the range [-31,-17] and is odd, use:
5843 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5844 // Note the last two are three-instruction sequences.
5845 if (SextVal >= -32 && SextVal <= 31) {
5846 // To avoid having these optimizations undone by constant folding,
5847 // we convert to a pseudo that will be expanded later into one of
5849 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5850 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5851 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5852 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5853 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5854 if (VT == Op.getValueType())
5857 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5860 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5861 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5863 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5864 // Make -1 and vspltisw -1:
5865 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5867 // Make the VSLW intrinsic, computing 0x8000_0000.
5868 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5871 // xor by OnesV to invert it.
5872 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5873 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5876 // The remaining cases assume either big endian element order or
5877 // a splat-size that equates to the element size of the vector
5878 // to be built. An example that doesn't work for little endian is
5879 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5880 // and a vector element size of 16 bits. The code below will
5881 // produce the vector in big endian element order, which for little
5882 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5884 // For now, just avoid these optimizations in that case.
5885 // FIXME: Develop correct optimizations for LE with mismatched
5886 // splat and element sizes.
5888 if (Subtarget.isLittleEndian() &&
5889 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5892 // Check to see if this is a wide variety of vsplti*, binop self cases.
5893 static const signed char SplatCsts[] = {
5894 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5895 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5898 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5899 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5900 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5901 int i = SplatCsts[idx];
5903 // Figure out what shift amount will be used by altivec if shifted by i in
5905 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5907 // vsplti + shl self.
5908 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5909 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5910 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5911 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5912 Intrinsic::ppc_altivec_vslw
5914 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5915 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5918 // vsplti + srl self.
5919 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5920 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5921 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5922 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5923 Intrinsic::ppc_altivec_vsrw
5925 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5926 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5929 // vsplti + sra self.
5930 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5931 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5932 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5933 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5934 Intrinsic::ppc_altivec_vsraw
5936 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5937 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5940 // vsplti + rol self.
5941 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5942 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5943 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5944 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5945 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5946 Intrinsic::ppc_altivec_vrlw
5948 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5949 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5952 // t = vsplti c, result = vsldoi t, t, 1
5953 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5954 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5955 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5957 // t = vsplti c, result = vsldoi t, t, 2
5958 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5959 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5960 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5962 // t = vsplti c, result = vsldoi t, t, 3
5963 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5964 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5965 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5972 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5973 /// the specified operations to build the shuffle.
5974 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5975 SDValue RHS, SelectionDAG &DAG,
5977 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5978 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5979 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5982 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5994 if (OpNum == OP_COPY) {
5995 if (LHSID == (1*9+2)*9+3) return LHS;
5996 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6000 SDValue OpLHS, OpRHS;
6001 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6002 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6006 default: llvm_unreachable("Unknown i32 permute!");
6008 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6009 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6010 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6011 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6014 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6015 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6016 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6017 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6020 for (unsigned i = 0; i != 16; ++i)
6021 ShufIdxs[i] = (i&3)+0;
6024 for (unsigned i = 0; i != 16; ++i)
6025 ShufIdxs[i] = (i&3)+4;
6028 for (unsigned i = 0; i != 16; ++i)
6029 ShufIdxs[i] = (i&3)+8;
6032 for (unsigned i = 0; i != 16; ++i)
6033 ShufIdxs[i] = (i&3)+12;
6036 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6038 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6040 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6042 EVT VT = OpLHS.getValueType();
6043 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6044 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6045 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6046 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6049 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6050 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6051 /// return the code it can be lowered into. Worst case, it can always be
6052 /// lowered into a vperm.
6053 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6054 SelectionDAG &DAG) const {
6056 SDValue V1 = Op.getOperand(0);
6057 SDValue V2 = Op.getOperand(1);
6058 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6059 EVT VT = Op.getValueType();
6060 bool isLittleEndian = Subtarget.isLittleEndian();
6062 // Cases that are handled by instructions that take permute immediates
6063 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6064 // selected by the instruction selector.
6065 if (V2.getOpcode() == ISD::UNDEF) {
6066 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6067 PPC::isSplatShuffleMask(SVOp, 2) ||
6068 PPC::isSplatShuffleMask(SVOp, 4) ||
6069 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6070 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6071 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6072 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6073 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6074 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6075 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6076 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6077 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6082 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6083 // and produce a fixed permutation. If any of these match, do not lower to
6085 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6086 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6087 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6088 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6089 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6090 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6091 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6092 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6093 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6094 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6097 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6098 // perfect shuffle table to emit an optimal matching sequence.
6099 ArrayRef<int> PermMask = SVOp->getMask();
6101 unsigned PFIndexes[4];
6102 bool isFourElementShuffle = true;
6103 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6104 unsigned EltNo = 8; // Start out undef.
6105 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6106 if (PermMask[i*4+j] < 0)
6107 continue; // Undef, ignore it.
6109 unsigned ByteSource = PermMask[i*4+j];
6110 if ((ByteSource & 3) != j) {
6111 isFourElementShuffle = false;
6116 EltNo = ByteSource/4;
6117 } else if (EltNo != ByteSource/4) {
6118 isFourElementShuffle = false;
6122 PFIndexes[i] = EltNo;
6125 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6126 // perfect shuffle vector to determine if it is cost effective to do this as
6127 // discrete instructions, or whether we should use a vperm.
6128 // For now, we skip this for little endian until such time as we have a
6129 // little-endian perfect shuffle table.
6130 if (isFourElementShuffle && !isLittleEndian) {
6131 // Compute the index in the perfect shuffle table.
6132 unsigned PFTableIndex =
6133 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6135 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6136 unsigned Cost = (PFEntry >> 30);
6138 // Determining when to avoid vperm is tricky. Many things affect the cost
6139 // of vperm, particularly how many times the perm mask needs to be computed.
6140 // For example, if the perm mask can be hoisted out of a loop or is already
6141 // used (perhaps because there are multiple permutes with the same shuffle
6142 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6143 // the loop requires an extra register.
6145 // As a compromise, we only emit discrete instructions if the shuffle can be
6146 // generated in 3 or fewer operations. When we have loop information
6147 // available, if this block is within a loop, we should avoid using vperm
6148 // for 3-operation perms and use a constant pool load instead.
6150 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6153 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6154 // vector that will get spilled to the constant pool.
6155 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6157 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6158 // that it is in input element units, not in bytes. Convert now.
6160 // For little endian, the order of the input vectors is reversed, and
6161 // the permutation mask is complemented with respect to 31. This is
6162 // necessary to produce proper semantics with the big-endian-biased vperm
6164 EVT EltVT = V1.getValueType().getVectorElementType();
6165 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6167 SmallVector<SDValue, 16> ResultMask;
6168 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6169 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6171 for (unsigned j = 0; j != BytesPerElement; ++j)
6173 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6176 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6180 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6183 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6186 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6190 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6191 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6192 /// information about the intrinsic.
6193 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6195 unsigned IntrinsicID =
6196 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6199 switch (IntrinsicID) {
6200 default: return false;
6201 // Comparison predicates.
6202 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6203 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6204 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6205 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6206 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6207 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6208 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6209 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6210 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6211 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6212 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6213 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6214 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6216 // Normal Comparisons.
6217 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6218 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6219 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6220 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6221 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6222 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6223 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6224 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6225 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6226 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6227 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6228 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6229 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6234 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6235 /// lower, do it, otherwise return null.
6236 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6237 SelectionDAG &DAG) const {
6238 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6239 // opcode number of the comparison.
6243 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6244 return SDValue(); // Don't custom lower most intrinsics.
6246 // If this is a non-dot comparison, make the VCMP node and we are done.
6248 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6249 Op.getOperand(1), Op.getOperand(2),
6250 DAG.getConstant(CompareOpc, MVT::i32));
6251 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6254 // Create the PPCISD altivec 'dot' comparison node.
6256 Op.getOperand(2), // LHS
6257 Op.getOperand(3), // RHS
6258 DAG.getConstant(CompareOpc, MVT::i32)
6260 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6261 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6263 // Now that we have the comparison, emit a copy from the CR to a GPR.
6264 // This is flagged to the above dot comparison.
6265 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6266 DAG.getRegister(PPC::CR6, MVT::i32),
6267 CompNode.getValue(1));
6269 // Unpack the result based on how the target uses it.
6270 unsigned BitNo; // Bit # of CR6.
6271 bool InvertBit; // Invert result?
6272 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6273 default: // Can't happen, don't crash on invalid number though.
6274 case 0: // Return the value of the EQ bit of CR6.
6275 BitNo = 0; InvertBit = false;
6277 case 1: // Return the inverted value of the EQ bit of CR6.
6278 BitNo = 0; InvertBit = true;
6280 case 2: // Return the value of the LT bit of CR6.
6281 BitNo = 2; InvertBit = false;
6283 case 3: // Return the inverted value of the LT bit of CR6.
6284 BitNo = 2; InvertBit = true;
6288 // Shift the bit into the low position.
6289 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6290 DAG.getConstant(8-(3-BitNo), MVT::i32));
6292 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6293 DAG.getConstant(1, MVT::i32));
6295 // If we are supposed to, toggle the bit.
6297 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6298 DAG.getConstant(1, MVT::i32));
6302 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6303 SelectionDAG &DAG) const {
6305 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6306 // instructions), but for smaller types, we need to first extend up to v2i32
6307 // before doing going farther.
6308 if (Op.getValueType() == MVT::v2i64) {
6309 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6310 if (ExtVT != MVT::v2i32) {
6311 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6312 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6313 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6314 ExtVT.getVectorElementType(), 4)));
6315 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6316 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6317 DAG.getValueType(MVT::v2i32));
6326 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6327 SelectionDAG &DAG) const {
6329 // Create a stack slot that is 16-byte aligned.
6330 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6331 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6332 EVT PtrVT = getPointerTy();
6333 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6335 // Store the input value into Value#0 of the stack slot.
6336 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6337 Op.getOperand(0), FIdx, MachinePointerInfo(),
6340 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6341 false, false, false, 0);
6344 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6346 if (Op.getValueType() == MVT::v4i32) {
6347 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6349 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6350 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6352 SDValue RHSSwap = // = vrlw RHS, 16
6353 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6355 // Shrinkify inputs to v8i16.
6356 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6357 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6358 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6360 // Low parts multiplied together, generating 32-bit results (we ignore the
6362 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6363 LHS, RHS, DAG, dl, MVT::v4i32);
6365 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6366 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6367 // Shift the high parts up 16 bits.
6368 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6370 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6371 } else if (Op.getValueType() == MVT::v8i16) {
6372 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6374 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6376 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6377 LHS, RHS, Zero, DAG, dl);
6378 } else if (Op.getValueType() == MVT::v16i8) {
6379 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6380 bool isLittleEndian = Subtarget.isLittleEndian();
6382 // Multiply the even 8-bit parts, producing 16-bit sums.
6383 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6384 LHS, RHS, DAG, dl, MVT::v8i16);
6385 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6387 // Multiply the odd 8-bit parts, producing 16-bit sums.
6388 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6389 LHS, RHS, DAG, dl, MVT::v8i16);
6390 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6392 // Merge the results together. Because vmuleub and vmuloub are
6393 // instructions with a big-endian bias, we must reverse the
6394 // element numbering and reverse the meaning of "odd" and "even"
6395 // when generating little endian code.
6397 for (unsigned i = 0; i != 8; ++i) {
6398 if (isLittleEndian) {
6400 Ops[i*2+1] = 2*i+16;
6403 Ops[i*2+1] = 2*i+1+16;
6407 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6409 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6411 llvm_unreachable("Unknown mul to lower!");
6415 /// LowerOperation - Provide custom lowering hooks for some operations.
6417 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6418 switch (Op.getOpcode()) {
6419 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6420 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6421 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6422 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6423 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6424 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6425 case ISD::SETCC: return LowerSETCC(Op, DAG);
6426 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6427 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6429 return LowerVASTART(Op, DAG, Subtarget);
6432 return LowerVAARG(Op, DAG, Subtarget);
6435 return LowerVACOPY(Op, DAG, Subtarget);
6437 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6438 case ISD::DYNAMIC_STACKALLOC:
6439 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6441 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6442 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6444 case ISD::LOAD: return LowerLOAD(Op, DAG);
6445 case ISD::STORE: return LowerSTORE(Op, DAG);
6446 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6447 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6448 case ISD::FP_TO_UINT:
6449 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6451 case ISD::UINT_TO_FP:
6452 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6453 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6455 // Lower 64-bit shifts.
6456 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6457 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6458 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6460 // Vector-related lowering.
6461 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6462 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6463 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6464 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6465 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6466 case ISD::MUL: return LowerMUL(Op, DAG);
6468 // For counter-based loop handling.
6469 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6471 // Frame & Return address.
6472 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6473 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6477 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6478 SmallVectorImpl<SDValue>&Results,
6479 SelectionDAG &DAG) const {
6480 const TargetMachine &TM = getTargetMachine();
6482 switch (N->getOpcode()) {
6484 llvm_unreachable("Do not know how to custom type legalize this operation!");
6485 case ISD::INTRINSIC_W_CHAIN: {
6486 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6487 Intrinsic::ppc_is_decremented_ctr_nonzero)
6490 assert(N->getValueType(0) == MVT::i1 &&
6491 "Unexpected result type for CTR decrement intrinsic");
6492 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6493 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6494 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6497 Results.push_back(NewInt);
6498 Results.push_back(NewInt.getValue(1));
6502 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6503 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6506 EVT VT = N->getValueType(0);
6508 if (VT == MVT::i64) {
6509 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6511 Results.push_back(NewNode);
6512 Results.push_back(NewNode.getValue(1));
6516 case ISD::FP_ROUND_INREG: {
6517 assert(N->getValueType(0) == MVT::ppcf128);
6518 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6519 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6520 MVT::f64, N->getOperand(0),
6521 DAG.getIntPtrConstant(0));
6522 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6523 MVT::f64, N->getOperand(0),
6524 DAG.getIntPtrConstant(1));
6526 // Add the two halves of the long double in round-to-zero mode.
6527 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6529 // We know the low half is about to be thrown away, so just use something
6531 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6535 case ISD::FP_TO_SINT:
6536 // LowerFP_TO_INT() can only handle f32 and f64.
6537 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6539 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6545 //===----------------------------------------------------------------------===//
6546 // Other Lowering Code
6547 //===----------------------------------------------------------------------===//
6549 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6550 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6551 Function *Func = Intrinsic::getDeclaration(M, Id);
6552 return Builder.CreateCall(Func);
6555 // The mappings for emitLeading/TrailingFence is taken from
6556 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6557 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6558 AtomicOrdering Ord, bool IsStore,
6559 bool IsLoad) const {
6560 if (Ord == SequentiallyConsistent)
6561 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6562 else if (isAtLeastRelease(Ord))
6563 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6568 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6569 AtomicOrdering Ord, bool IsStore,
6570 bool IsLoad) const {
6571 if (IsLoad && isAtLeastAcquire(Ord))
6572 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6573 // FIXME: this is too conservative, a dependent branch + isync is enough.
6574 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6575 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6576 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6582 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6583 bool is64bit, unsigned BinOpcode) const {
6584 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6585 const TargetInstrInfo *TII =
6586 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6588 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6589 MachineFunction *F = BB->getParent();
6590 MachineFunction::iterator It = BB;
6593 unsigned dest = MI->getOperand(0).getReg();
6594 unsigned ptrA = MI->getOperand(1).getReg();
6595 unsigned ptrB = MI->getOperand(2).getReg();
6596 unsigned incr = MI->getOperand(3).getReg();
6597 DebugLoc dl = MI->getDebugLoc();
6599 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6600 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6601 F->insert(It, loopMBB);
6602 F->insert(It, exitMBB);
6603 exitMBB->splice(exitMBB->begin(), BB,
6604 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6605 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6607 MachineRegisterInfo &RegInfo = F->getRegInfo();
6608 unsigned TmpReg = (!BinOpcode) ? incr :
6609 RegInfo.createVirtualRegister(
6610 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6611 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6615 // fallthrough --> loopMBB
6616 BB->addSuccessor(loopMBB);
6619 // l[wd]arx dest, ptr
6620 // add r0, dest, incr
6621 // st[wd]cx. r0, ptr
6623 // fallthrough --> exitMBB
6625 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6626 .addReg(ptrA).addReg(ptrB);
6628 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6629 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6630 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6631 BuildMI(BB, dl, TII->get(PPC::BCC))
6632 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6633 BB->addSuccessor(loopMBB);
6634 BB->addSuccessor(exitMBB);
6643 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6644 MachineBasicBlock *BB,
6645 bool is8bit, // operation
6646 unsigned BinOpcode) const {
6647 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6648 const TargetInstrInfo *TII =
6649 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6650 // In 64 bit mode we have to use 64 bits for addresses, even though the
6651 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6652 // registers without caring whether they're 32 or 64, but here we're
6653 // doing actual arithmetic on the addresses.
6654 bool is64bit = Subtarget.isPPC64();
6655 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6657 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6658 MachineFunction *F = BB->getParent();
6659 MachineFunction::iterator It = BB;
6662 unsigned dest = MI->getOperand(0).getReg();
6663 unsigned ptrA = MI->getOperand(1).getReg();
6664 unsigned ptrB = MI->getOperand(2).getReg();
6665 unsigned incr = MI->getOperand(3).getReg();
6666 DebugLoc dl = MI->getDebugLoc();
6668 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6669 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6670 F->insert(It, loopMBB);
6671 F->insert(It, exitMBB);
6672 exitMBB->splice(exitMBB->begin(), BB,
6673 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6674 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6676 MachineRegisterInfo &RegInfo = F->getRegInfo();
6677 const TargetRegisterClass *RC =
6678 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6679 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6680 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6681 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6682 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6683 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6684 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6685 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6686 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6687 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6688 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6689 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6690 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6692 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6696 // fallthrough --> loopMBB
6697 BB->addSuccessor(loopMBB);
6699 // The 4-byte load must be aligned, while a char or short may be
6700 // anywhere in the word. Hence all this nasty bookkeeping code.
6701 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6702 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6703 // xori shift, shift1, 24 [16]
6704 // rlwinm ptr, ptr1, 0, 0, 29
6705 // slw incr2, incr, shift
6706 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6707 // slw mask, mask2, shift
6709 // lwarx tmpDest, ptr
6710 // add tmp, tmpDest, incr2
6711 // andc tmp2, tmpDest, mask
6712 // and tmp3, tmp, mask
6713 // or tmp4, tmp3, tmp2
6716 // fallthrough --> exitMBB
6717 // srw dest, tmpDest, shift
6718 if (ptrA != ZeroReg) {
6719 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6720 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6721 .addReg(ptrA).addReg(ptrB);
6725 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6726 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6727 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6728 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6730 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6731 .addReg(Ptr1Reg).addImm(0).addImm(61);
6733 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6734 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6735 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6736 .addReg(incr).addReg(ShiftReg);
6738 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6740 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6741 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6743 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6744 .addReg(Mask2Reg).addReg(ShiftReg);
6747 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6748 .addReg(ZeroReg).addReg(PtrReg);
6750 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6751 .addReg(Incr2Reg).addReg(TmpDestReg);
6752 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6753 .addReg(TmpDestReg).addReg(MaskReg);
6754 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6755 .addReg(TmpReg).addReg(MaskReg);
6756 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6757 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6758 BuildMI(BB, dl, TII->get(PPC::STWCX))
6759 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6760 BuildMI(BB, dl, TII->get(PPC::BCC))
6761 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6762 BB->addSuccessor(loopMBB);
6763 BB->addSuccessor(exitMBB);
6768 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6773 llvm::MachineBasicBlock*
6774 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6775 MachineBasicBlock *MBB) const {
6776 DebugLoc DL = MI->getDebugLoc();
6777 const TargetInstrInfo *TII =
6778 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6780 MachineFunction *MF = MBB->getParent();
6781 MachineRegisterInfo &MRI = MF->getRegInfo();
6783 const BasicBlock *BB = MBB->getBasicBlock();
6784 MachineFunction::iterator I = MBB;
6788 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6789 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6791 unsigned DstReg = MI->getOperand(0).getReg();
6792 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6793 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6794 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6795 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6797 MVT PVT = getPointerTy();
6798 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6799 "Invalid Pointer Size!");
6800 // For v = setjmp(buf), we generate
6803 // SjLjSetup mainMBB
6809 // buf[LabelOffset] = LR
6813 // v = phi(main, restore)
6816 MachineBasicBlock *thisMBB = MBB;
6817 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6818 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6819 MF->insert(I, mainMBB);
6820 MF->insert(I, sinkMBB);
6822 MachineInstrBuilder MIB;
6824 // Transfer the remainder of BB and its successor edges to sinkMBB.
6825 sinkMBB->splice(sinkMBB->begin(), MBB,
6826 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6827 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6829 // Note that the structure of the jmp_buf used here is not compatible
6830 // with that used by libc, and is not designed to be. Specifically, it
6831 // stores only those 'reserved' registers that LLVM does not otherwise
6832 // understand how to spill. Also, by convention, by the time this
6833 // intrinsic is called, Clang has already stored the frame address in the
6834 // first slot of the buffer and stack address in the third. Following the
6835 // X86 target code, we'll store the jump address in the second slot. We also
6836 // need to save the TOC pointer (R2) to handle jumps between shared
6837 // libraries, and that will be stored in the fourth slot. The thread
6838 // identifier (R13) is not affected.
6841 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6842 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6843 const int64_t BPOffset = 4 * PVT.getStoreSize();
6845 // Prepare IP either in reg.
6846 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6847 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6848 unsigned BufReg = MI->getOperand(1).getReg();
6850 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6851 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6855 MIB.setMemRefs(MMOBegin, MMOEnd);
6858 // Naked functions never have a base pointer, and so we use r1. For all
6859 // other functions, this decision must be delayed until during PEI.
6861 if (MF->getFunction()->getAttributes().hasAttribute(
6862 AttributeSet::FunctionIndex, Attribute::Naked))
6863 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6865 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6867 MIB = BuildMI(*thisMBB, MI, DL,
6868 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6872 MIB.setMemRefs(MMOBegin, MMOEnd);
6875 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6876 const PPCRegisterInfo *TRI =
6877 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
6878 MIB.addRegMask(TRI->getNoPreservedMask());
6880 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6882 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6884 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6886 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6887 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6891 MIB = BuildMI(mainMBB, DL,
6892 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6895 if (Subtarget.isPPC64()) {
6896 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6898 .addImm(LabelOffset)
6901 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6903 .addImm(LabelOffset)
6907 MIB.setMemRefs(MMOBegin, MMOEnd);
6909 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6910 mainMBB->addSuccessor(sinkMBB);
6913 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6914 TII->get(PPC::PHI), DstReg)
6915 .addReg(mainDstReg).addMBB(mainMBB)
6916 .addReg(restoreDstReg).addMBB(thisMBB);
6918 MI->eraseFromParent();
6923 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6924 MachineBasicBlock *MBB) const {
6925 DebugLoc DL = MI->getDebugLoc();
6926 const TargetInstrInfo *TII =
6927 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6929 MachineFunction *MF = MBB->getParent();
6930 MachineRegisterInfo &MRI = MF->getRegInfo();
6933 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6934 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6936 MVT PVT = getPointerTy();
6937 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6938 "Invalid Pointer Size!");
6940 const TargetRegisterClass *RC =
6941 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6942 unsigned Tmp = MRI.createVirtualRegister(RC);
6943 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6944 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6945 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6946 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6947 (Subtarget.isSVR4ABI() &&
6948 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6949 PPC::R29 : PPC::R30);
6951 MachineInstrBuilder MIB;
6953 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6954 const int64_t SPOffset = 2 * PVT.getStoreSize();
6955 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6956 const int64_t BPOffset = 4 * PVT.getStoreSize();
6958 unsigned BufReg = MI->getOperand(0).getReg();
6960 // Reload FP (the jumped-to function may not have had a
6961 // frame pointer, and if so, then its r31 will be restored
6963 if (PVT == MVT::i64) {
6964 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6968 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6972 MIB.setMemRefs(MMOBegin, MMOEnd);
6975 if (PVT == MVT::i64) {
6976 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6977 .addImm(LabelOffset)
6980 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6981 .addImm(LabelOffset)
6984 MIB.setMemRefs(MMOBegin, MMOEnd);
6987 if (PVT == MVT::i64) {
6988 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6992 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6996 MIB.setMemRefs(MMOBegin, MMOEnd);
6999 if (PVT == MVT::i64) {
7000 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7004 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7008 MIB.setMemRefs(MMOBegin, MMOEnd);
7011 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7012 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7016 MIB.setMemRefs(MMOBegin, MMOEnd);
7020 BuildMI(*MBB, MI, DL,
7021 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7022 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7024 MI->eraseFromParent();
7029 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7030 MachineBasicBlock *BB) const {
7031 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7032 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7033 return emitEHSjLjSetJmp(MI, BB);
7034 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7035 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7036 return emitEHSjLjLongJmp(MI, BB);
7039 const TargetInstrInfo *TII =
7040 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7042 // To "insert" these instructions we actually have to insert their
7043 // control-flow patterns.
7044 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7045 MachineFunction::iterator It = BB;
7048 MachineFunction *F = BB->getParent();
7050 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7051 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7052 MI->getOpcode() == PPC::SELECT_I4 ||
7053 MI->getOpcode() == PPC::SELECT_I8)) {
7054 SmallVector<MachineOperand, 2> Cond;
7055 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7056 MI->getOpcode() == PPC::SELECT_CC_I8)
7057 Cond.push_back(MI->getOperand(4));
7059 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7060 Cond.push_back(MI->getOperand(1));
7062 DebugLoc dl = MI->getDebugLoc();
7063 const TargetInstrInfo *TII =
7064 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7065 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7066 Cond, MI->getOperand(2).getReg(),
7067 MI->getOperand(3).getReg());
7068 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7069 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7070 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7071 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7072 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7073 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7074 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7075 MI->getOpcode() == PPC::SELECT_I4 ||
7076 MI->getOpcode() == PPC::SELECT_I8 ||
7077 MI->getOpcode() == PPC::SELECT_F4 ||
7078 MI->getOpcode() == PPC::SELECT_F8 ||
7079 MI->getOpcode() == PPC::SELECT_VRRC ||
7080 MI->getOpcode() == PPC::SELECT_VSFRC ||
7081 MI->getOpcode() == PPC::SELECT_VSRC) {
7082 // The incoming instruction knows the destination vreg to set, the
7083 // condition code register to branch on, the true/false values to
7084 // select between, and a branch opcode to use.
7089 // cmpTY ccX, r1, r2
7091 // fallthrough --> copy0MBB
7092 MachineBasicBlock *thisMBB = BB;
7093 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7094 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7095 DebugLoc dl = MI->getDebugLoc();
7096 F->insert(It, copy0MBB);
7097 F->insert(It, sinkMBB);
7099 // Transfer the remainder of BB and its successor edges to sinkMBB.
7100 sinkMBB->splice(sinkMBB->begin(), BB,
7101 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7102 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7104 // Next, add the true and fallthrough blocks as its successors.
7105 BB->addSuccessor(copy0MBB);
7106 BB->addSuccessor(sinkMBB);
7108 if (MI->getOpcode() == PPC::SELECT_I4 ||
7109 MI->getOpcode() == PPC::SELECT_I8 ||
7110 MI->getOpcode() == PPC::SELECT_F4 ||
7111 MI->getOpcode() == PPC::SELECT_F8 ||
7112 MI->getOpcode() == PPC::SELECT_VRRC ||
7113 MI->getOpcode() == PPC::SELECT_VSFRC ||
7114 MI->getOpcode() == PPC::SELECT_VSRC) {
7115 BuildMI(BB, dl, TII->get(PPC::BC))
7116 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7118 unsigned SelectPred = MI->getOperand(4).getImm();
7119 BuildMI(BB, dl, TII->get(PPC::BCC))
7120 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7124 // %FalseValue = ...
7125 // # fallthrough to sinkMBB
7128 // Update machine-CFG edges
7129 BB->addSuccessor(sinkMBB);
7132 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7135 BuildMI(*BB, BB->begin(), dl,
7136 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7137 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7138 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7140 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7141 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7142 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7143 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7144 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7145 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7146 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7147 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7149 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7150 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7151 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7152 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7153 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7154 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7155 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7156 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7158 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7159 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7160 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7161 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7162 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7163 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7164 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7165 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7167 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7168 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7169 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7170 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7171 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7172 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7173 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7174 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7176 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7177 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7178 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7179 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7180 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7181 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7182 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7183 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7185 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7186 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7187 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7188 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7189 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7190 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7191 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7192 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7194 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7195 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7196 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7197 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7198 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7199 BB = EmitAtomicBinary(MI, BB, false, 0);
7200 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7201 BB = EmitAtomicBinary(MI, BB, true, 0);
7203 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7204 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7205 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7207 unsigned dest = MI->getOperand(0).getReg();
7208 unsigned ptrA = MI->getOperand(1).getReg();
7209 unsigned ptrB = MI->getOperand(2).getReg();
7210 unsigned oldval = MI->getOperand(3).getReg();
7211 unsigned newval = MI->getOperand(4).getReg();
7212 DebugLoc dl = MI->getDebugLoc();
7214 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7215 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7216 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7217 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7218 F->insert(It, loop1MBB);
7219 F->insert(It, loop2MBB);
7220 F->insert(It, midMBB);
7221 F->insert(It, exitMBB);
7222 exitMBB->splice(exitMBB->begin(), BB,
7223 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7224 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7228 // fallthrough --> loopMBB
7229 BB->addSuccessor(loop1MBB);
7232 // l[wd]arx dest, ptr
7233 // cmp[wd] dest, oldval
7236 // st[wd]cx. newval, ptr
7240 // st[wd]cx. dest, ptr
7243 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7244 .addReg(ptrA).addReg(ptrB);
7245 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7246 .addReg(oldval).addReg(dest);
7247 BuildMI(BB, dl, TII->get(PPC::BCC))
7248 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7249 BB->addSuccessor(loop2MBB);
7250 BB->addSuccessor(midMBB);
7253 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7254 .addReg(newval).addReg(ptrA).addReg(ptrB);
7255 BuildMI(BB, dl, TII->get(PPC::BCC))
7256 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7257 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7258 BB->addSuccessor(loop1MBB);
7259 BB->addSuccessor(exitMBB);
7262 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7263 .addReg(dest).addReg(ptrA).addReg(ptrB);
7264 BB->addSuccessor(exitMBB);
7269 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7270 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7271 // We must use 64-bit registers for addresses when targeting 64-bit,
7272 // since we're actually doing arithmetic on them. Other registers
7274 bool is64bit = Subtarget.isPPC64();
7275 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7277 unsigned dest = MI->getOperand(0).getReg();
7278 unsigned ptrA = MI->getOperand(1).getReg();
7279 unsigned ptrB = MI->getOperand(2).getReg();
7280 unsigned oldval = MI->getOperand(3).getReg();
7281 unsigned newval = MI->getOperand(4).getReg();
7282 DebugLoc dl = MI->getDebugLoc();
7284 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7285 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7286 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7287 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7288 F->insert(It, loop1MBB);
7289 F->insert(It, loop2MBB);
7290 F->insert(It, midMBB);
7291 F->insert(It, exitMBB);
7292 exitMBB->splice(exitMBB->begin(), BB,
7293 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7294 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7296 MachineRegisterInfo &RegInfo = F->getRegInfo();
7297 const TargetRegisterClass *RC =
7298 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7299 (const TargetRegisterClass *) &PPC::GPRCRegClass;
7300 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7301 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7302 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7303 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7304 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7305 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7306 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7307 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7308 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7309 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7310 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7311 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7312 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7314 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7315 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7318 // fallthrough --> loopMBB
7319 BB->addSuccessor(loop1MBB);
7321 // The 4-byte load must be aligned, while a char or short may be
7322 // anywhere in the word. Hence all this nasty bookkeeping code.
7323 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7324 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7325 // xori shift, shift1, 24 [16]
7326 // rlwinm ptr, ptr1, 0, 0, 29
7327 // slw newval2, newval, shift
7328 // slw oldval2, oldval,shift
7329 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7330 // slw mask, mask2, shift
7331 // and newval3, newval2, mask
7332 // and oldval3, oldval2, mask
7334 // lwarx tmpDest, ptr
7335 // and tmp, tmpDest, mask
7336 // cmpw tmp, oldval3
7339 // andc tmp2, tmpDest, mask
7340 // or tmp4, tmp2, newval3
7345 // stwcx. tmpDest, ptr
7347 // srw dest, tmpDest, shift
7348 if (ptrA != ZeroReg) {
7349 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7350 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7351 .addReg(ptrA).addReg(ptrB);
7355 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7356 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7357 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7358 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7360 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7361 .addReg(Ptr1Reg).addImm(0).addImm(61);
7363 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7364 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7365 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7366 .addReg(newval).addReg(ShiftReg);
7367 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7368 .addReg(oldval).addReg(ShiftReg);
7370 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7372 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7373 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7374 .addReg(Mask3Reg).addImm(65535);
7376 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7377 .addReg(Mask2Reg).addReg(ShiftReg);
7378 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7379 .addReg(NewVal2Reg).addReg(MaskReg);
7380 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7381 .addReg(OldVal2Reg).addReg(MaskReg);
7384 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7385 .addReg(ZeroReg).addReg(PtrReg);
7386 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7387 .addReg(TmpDestReg).addReg(MaskReg);
7388 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7389 .addReg(TmpReg).addReg(OldVal3Reg);
7390 BuildMI(BB, dl, TII->get(PPC::BCC))
7391 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7392 BB->addSuccessor(loop2MBB);
7393 BB->addSuccessor(midMBB);
7396 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7397 .addReg(TmpDestReg).addReg(MaskReg);
7398 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7399 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7400 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7401 .addReg(ZeroReg).addReg(PtrReg);
7402 BuildMI(BB, dl, TII->get(PPC::BCC))
7403 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7404 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7405 BB->addSuccessor(loop1MBB);
7406 BB->addSuccessor(exitMBB);
7409 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7410 .addReg(ZeroReg).addReg(PtrReg);
7411 BB->addSuccessor(exitMBB);
7416 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7418 } else if (MI->getOpcode() == PPC::FADDrtz) {
7419 // This pseudo performs an FADD with rounding mode temporarily forced
7420 // to round-to-zero. We emit this via custom inserter since the FPSCR
7421 // is not modeled at the SelectionDAG level.
7422 unsigned Dest = MI->getOperand(0).getReg();
7423 unsigned Src1 = MI->getOperand(1).getReg();
7424 unsigned Src2 = MI->getOperand(2).getReg();
7425 DebugLoc dl = MI->getDebugLoc();
7427 MachineRegisterInfo &RegInfo = F->getRegInfo();
7428 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7430 // Save FPSCR value.
7431 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7433 // Set rounding mode to round-to-zero.
7434 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7435 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7437 // Perform addition.
7438 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7440 // Restore FPSCR value.
7441 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7442 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7443 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7444 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7445 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7446 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7447 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7448 PPC::ANDIo8 : PPC::ANDIo;
7449 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7450 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7452 MachineRegisterInfo &RegInfo = F->getRegInfo();
7453 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7454 &PPC::GPRCRegClass :
7455 &PPC::G8RCRegClass);
7457 DebugLoc dl = MI->getDebugLoc();
7458 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7459 .addReg(MI->getOperand(1).getReg()).addImm(1);
7460 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7461 MI->getOperand(0).getReg())
7462 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7464 llvm_unreachable("Unexpected instr type to insert");
7467 MI->eraseFromParent(); // The pseudo instruction is gone now.
7471 //===----------------------------------------------------------------------===//
7472 // Target Optimization Hooks
7473 //===----------------------------------------------------------------------===//
7475 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7476 DAGCombinerInfo &DCI,
7477 unsigned &RefinementSteps,
7478 bool &UseOneConstNR) const {
7479 EVT VT = Operand.getValueType();
7480 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7481 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7482 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7483 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7484 // Convergence is quadratic, so we essentially double the number of digits
7485 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7486 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7487 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7488 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7489 if (VT.getScalarType() == MVT::f64)
7491 UseOneConstNR = true;
7492 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7497 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7498 DAGCombinerInfo &DCI,
7499 unsigned &RefinementSteps) const {
7500 EVT VT = Operand.getValueType();
7501 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7502 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7503 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7504 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7505 // Convergence is quadratic, so we essentially double the number of digits
7506 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7507 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7508 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7509 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7510 if (VT.getScalarType() == MVT::f64)
7512 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7517 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7518 unsigned Bytes, int Dist,
7519 SelectionDAG &DAG) {
7520 if (VT.getSizeInBits() / 8 != Bytes)
7523 SDValue BaseLoc = Base->getBasePtr();
7524 if (Loc.getOpcode() == ISD::FrameIndex) {
7525 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7527 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7528 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7529 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7530 int FS = MFI->getObjectSize(FI);
7531 int BFS = MFI->getObjectSize(BFI);
7532 if (FS != BFS || FS != (int)Bytes) return false;
7533 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7537 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7538 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7541 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7542 const GlobalValue *GV1 = nullptr;
7543 const GlobalValue *GV2 = nullptr;
7544 int64_t Offset1 = 0;
7545 int64_t Offset2 = 0;
7546 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7547 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7548 if (isGA1 && isGA2 && GV1 == GV2)
7549 return Offset1 == (Offset2 + Dist*Bytes);
7553 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7554 // not enforce equality of the chain operands.
7555 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7556 unsigned Bytes, int Dist,
7557 SelectionDAG &DAG) {
7558 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7559 EVT VT = LS->getMemoryVT();
7560 SDValue Loc = LS->getBasePtr();
7561 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7564 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7566 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7567 default: return false;
7568 case Intrinsic::ppc_altivec_lvx:
7569 case Intrinsic::ppc_altivec_lvxl:
7572 case Intrinsic::ppc_altivec_lvebx:
7575 case Intrinsic::ppc_altivec_lvehx:
7578 case Intrinsic::ppc_altivec_lvewx:
7583 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7586 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7588 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7589 default: return false;
7590 case Intrinsic::ppc_altivec_stvx:
7591 case Intrinsic::ppc_altivec_stvxl:
7594 case Intrinsic::ppc_altivec_stvebx:
7597 case Intrinsic::ppc_altivec_stvehx:
7600 case Intrinsic::ppc_altivec_stvewx:
7605 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7611 // Return true is there is a nearyby consecutive load to the one provided
7612 // (regardless of alignment). We search up and down the chain, looking though
7613 // token factors and other loads (but nothing else). As a result, a true result
7614 // indicates that it is safe to create a new consecutive load adjacent to the
7616 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7617 SDValue Chain = LD->getChain();
7618 EVT VT = LD->getMemoryVT();
7620 SmallSet<SDNode *, 16> LoadRoots;
7621 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7622 SmallSet<SDNode *, 16> Visited;
7624 // First, search up the chain, branching to follow all token-factor operands.
7625 // If we find a consecutive load, then we're done, otherwise, record all
7626 // nodes just above the top-level loads and token factors.
7627 while (!Queue.empty()) {
7628 SDNode *ChainNext = Queue.pop_back_val();
7629 if (!Visited.insert(ChainNext))
7632 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7633 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7636 if (!Visited.count(ChainLD->getChain().getNode()))
7637 Queue.push_back(ChainLD->getChain().getNode());
7638 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7639 for (const SDUse &O : ChainNext->ops())
7640 if (!Visited.count(O.getNode()))
7641 Queue.push_back(O.getNode());
7643 LoadRoots.insert(ChainNext);
7646 // Second, search down the chain, starting from the top-level nodes recorded
7647 // in the first phase. These top-level nodes are the nodes just above all
7648 // loads and token factors. Starting with their uses, recursively look though
7649 // all loads (just the chain uses) and token factors to find a consecutive
7654 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7655 IE = LoadRoots.end(); I != IE; ++I) {
7656 Queue.push_back(*I);
7658 while (!Queue.empty()) {
7659 SDNode *LoadRoot = Queue.pop_back_val();
7660 if (!Visited.insert(LoadRoot))
7663 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7664 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7667 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7668 UE = LoadRoot->use_end(); UI != UE; ++UI)
7669 if (((isa<MemSDNode>(*UI) &&
7670 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7671 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7672 Queue.push_back(*UI);
7679 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7680 DAGCombinerInfo &DCI) const {
7681 SelectionDAG &DAG = DCI.DAG;
7684 assert(Subtarget.useCRBits() &&
7685 "Expecting to be tracking CR bits");
7686 // If we're tracking CR bits, we need to be careful that we don't have:
7687 // trunc(binary-ops(zext(x), zext(y)))
7689 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7690 // such that we're unnecessarily moving things into GPRs when it would be
7691 // better to keep them in CR bits.
7693 // Note that trunc here can be an actual i1 trunc, or can be the effective
7694 // truncation that comes from a setcc or select_cc.
7695 if (N->getOpcode() == ISD::TRUNCATE &&
7696 N->getValueType(0) != MVT::i1)
7699 if (N->getOperand(0).getValueType() != MVT::i32 &&
7700 N->getOperand(0).getValueType() != MVT::i64)
7703 if (N->getOpcode() == ISD::SETCC ||
7704 N->getOpcode() == ISD::SELECT_CC) {
7705 // If we're looking at a comparison, then we need to make sure that the
7706 // high bits (all except for the first) don't matter the result.
7708 cast<CondCodeSDNode>(N->getOperand(
7709 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7710 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7712 if (ISD::isSignedIntSetCC(CC)) {
7713 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7714 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7716 } else if (ISD::isUnsignedIntSetCC(CC)) {
7717 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7718 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7719 !DAG.MaskedValueIsZero(N->getOperand(1),
7720 APInt::getHighBitsSet(OpBits, OpBits-1)))
7723 // This is neither a signed nor an unsigned comparison, just make sure
7724 // that the high bits are equal.
7725 APInt Op1Zero, Op1One;
7726 APInt Op2Zero, Op2One;
7727 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7728 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7730 // We don't really care about what is known about the first bit (if
7731 // anything), so clear it in all masks prior to comparing them.
7732 Op1Zero.clearBit(0); Op1One.clearBit(0);
7733 Op2Zero.clearBit(0); Op2One.clearBit(0);
7735 if (Op1Zero != Op2Zero || Op1One != Op2One)
7740 // We now know that the higher-order bits are irrelevant, we just need to
7741 // make sure that all of the intermediate operations are bit operations, and
7742 // all inputs are extensions.
7743 if (N->getOperand(0).getOpcode() != ISD::AND &&
7744 N->getOperand(0).getOpcode() != ISD::OR &&
7745 N->getOperand(0).getOpcode() != ISD::XOR &&
7746 N->getOperand(0).getOpcode() != ISD::SELECT &&
7747 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7748 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7749 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7750 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7751 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7754 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7755 N->getOperand(1).getOpcode() != ISD::AND &&
7756 N->getOperand(1).getOpcode() != ISD::OR &&
7757 N->getOperand(1).getOpcode() != ISD::XOR &&
7758 N->getOperand(1).getOpcode() != ISD::SELECT &&
7759 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7760 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7761 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7762 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7763 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7766 SmallVector<SDValue, 4> Inputs;
7767 SmallVector<SDValue, 8> BinOps, PromOps;
7768 SmallPtrSet<SDNode *, 16> Visited;
7770 for (unsigned i = 0; i < 2; ++i) {
7771 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7772 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7773 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7774 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7775 isa<ConstantSDNode>(N->getOperand(i)))
7776 Inputs.push_back(N->getOperand(i));
7778 BinOps.push_back(N->getOperand(i));
7780 if (N->getOpcode() == ISD::TRUNCATE)
7784 // Visit all inputs, collect all binary operations (and, or, xor and
7785 // select) that are all fed by extensions.
7786 while (!BinOps.empty()) {
7787 SDValue BinOp = BinOps.back();
7790 if (!Visited.insert(BinOp.getNode()))
7793 PromOps.push_back(BinOp);
7795 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7796 // The condition of the select is not promoted.
7797 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7799 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7802 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7803 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7804 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7805 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7806 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7807 Inputs.push_back(BinOp.getOperand(i));
7808 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7809 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7810 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7811 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7812 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7813 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7814 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7815 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7816 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7817 BinOps.push_back(BinOp.getOperand(i));
7819 // We have an input that is not an extension or another binary
7820 // operation; we'll abort this transformation.
7826 // Make sure that this is a self-contained cluster of operations (which
7827 // is not quite the same thing as saying that everything has only one
7829 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7830 if (isa<ConstantSDNode>(Inputs[i]))
7833 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7834 UE = Inputs[i].getNode()->use_end();
7837 if (User != N && !Visited.count(User))
7840 // Make sure that we're not going to promote the non-output-value
7841 // operand(s) or SELECT or SELECT_CC.
7842 // FIXME: Although we could sometimes handle this, and it does occur in
7843 // practice that one of the condition inputs to the select is also one of
7844 // the outputs, we currently can't deal with this.
7845 if (User->getOpcode() == ISD::SELECT) {
7846 if (User->getOperand(0) == Inputs[i])
7848 } else if (User->getOpcode() == ISD::SELECT_CC) {
7849 if (User->getOperand(0) == Inputs[i] ||
7850 User->getOperand(1) == Inputs[i])
7856 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7857 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7858 UE = PromOps[i].getNode()->use_end();
7861 if (User != N && !Visited.count(User))
7864 // Make sure that we're not going to promote the non-output-value
7865 // operand(s) or SELECT or SELECT_CC.
7866 // FIXME: Although we could sometimes handle this, and it does occur in
7867 // practice that one of the condition inputs to the select is also one of
7868 // the outputs, we currently can't deal with this.
7869 if (User->getOpcode() == ISD::SELECT) {
7870 if (User->getOperand(0) == PromOps[i])
7872 } else if (User->getOpcode() == ISD::SELECT_CC) {
7873 if (User->getOperand(0) == PromOps[i] ||
7874 User->getOperand(1) == PromOps[i])
7880 // Replace all inputs with the extension operand.
7881 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7882 // Constants may have users outside the cluster of to-be-promoted nodes,
7883 // and so we need to replace those as we do the promotions.
7884 if (isa<ConstantSDNode>(Inputs[i]))
7887 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7890 // Replace all operations (these are all the same, but have a different
7891 // (i1) return type). DAG.getNode will validate that the types of
7892 // a binary operator match, so go through the list in reverse so that
7893 // we've likely promoted both operands first. Any intermediate truncations or
7894 // extensions disappear.
7895 while (!PromOps.empty()) {
7896 SDValue PromOp = PromOps.back();
7899 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7900 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7901 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7902 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7903 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7904 PromOp.getOperand(0).getValueType() != MVT::i1) {
7905 // The operand is not yet ready (see comment below).
7906 PromOps.insert(PromOps.begin(), PromOp);
7910 SDValue RepValue = PromOp.getOperand(0);
7911 if (isa<ConstantSDNode>(RepValue))
7912 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7914 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7919 switch (PromOp.getOpcode()) {
7920 default: C = 0; break;
7921 case ISD::SELECT: C = 1; break;
7922 case ISD::SELECT_CC: C = 2; break;
7925 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7926 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7927 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7928 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7929 // The to-be-promoted operands of this node have not yet been
7930 // promoted (this should be rare because we're going through the
7931 // list backward, but if one of the operands has several users in
7932 // this cluster of to-be-promoted nodes, it is possible).
7933 PromOps.insert(PromOps.begin(), PromOp);
7937 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7938 PromOp.getNode()->op_end());
7940 // If there are any constant inputs, make sure they're replaced now.
7941 for (unsigned i = 0; i < 2; ++i)
7942 if (isa<ConstantSDNode>(Ops[C+i]))
7943 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7945 DAG.ReplaceAllUsesOfValueWith(PromOp,
7946 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7949 // Now we're left with the initial truncation itself.
7950 if (N->getOpcode() == ISD::TRUNCATE)
7951 return N->getOperand(0);
7953 // Otherwise, this is a comparison. The operands to be compared have just
7954 // changed type (to i1), but everything else is the same.
7955 return SDValue(N, 0);
7958 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7959 DAGCombinerInfo &DCI) const {
7960 SelectionDAG &DAG = DCI.DAG;
7963 // If we're tracking CR bits, we need to be careful that we don't have:
7964 // zext(binary-ops(trunc(x), trunc(y)))
7966 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7967 // such that we're unnecessarily moving things into CR bits that can more
7968 // efficiently stay in GPRs. Note that if we're not certain that the high
7969 // bits are set as required by the final extension, we still may need to do
7970 // some masking to get the proper behavior.
7972 // This same functionality is important on PPC64 when dealing with
7973 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7974 // the return values of functions. Because it is so similar, it is handled
7977 if (N->getValueType(0) != MVT::i32 &&
7978 N->getValueType(0) != MVT::i64)
7981 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7982 Subtarget.useCRBits()) ||
7983 (N->getOperand(0).getValueType() == MVT::i32 &&
7984 Subtarget.isPPC64())))
7987 if (N->getOperand(0).getOpcode() != ISD::AND &&
7988 N->getOperand(0).getOpcode() != ISD::OR &&
7989 N->getOperand(0).getOpcode() != ISD::XOR &&
7990 N->getOperand(0).getOpcode() != ISD::SELECT &&
7991 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7994 SmallVector<SDValue, 4> Inputs;
7995 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7996 SmallPtrSet<SDNode *, 16> Visited;
7998 // Visit all inputs, collect all binary operations (and, or, xor and
7999 // select) that are all fed by truncations.
8000 while (!BinOps.empty()) {
8001 SDValue BinOp = BinOps.back();
8004 if (!Visited.insert(BinOp.getNode()))
8007 PromOps.push_back(BinOp);
8009 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8010 // The condition of the select is not promoted.
8011 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8013 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8016 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8017 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8018 Inputs.push_back(BinOp.getOperand(i));
8019 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8020 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8021 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8022 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8023 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8024 BinOps.push_back(BinOp.getOperand(i));
8026 // We have an input that is not a truncation or another binary
8027 // operation; we'll abort this transformation.
8033 // Make sure that this is a self-contained cluster of operations (which
8034 // is not quite the same thing as saying that everything has only one
8036 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8037 if (isa<ConstantSDNode>(Inputs[i]))
8040 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8041 UE = Inputs[i].getNode()->use_end();
8044 if (User != N && !Visited.count(User))
8047 // Make sure that we're not going to promote the non-output-value
8048 // operand(s) or SELECT or SELECT_CC.
8049 // FIXME: Although we could sometimes handle this, and it does occur in
8050 // practice that one of the condition inputs to the select is also one of
8051 // the outputs, we currently can't deal with this.
8052 if (User->getOpcode() == ISD::SELECT) {
8053 if (User->getOperand(0) == Inputs[i])
8055 } else if (User->getOpcode() == ISD::SELECT_CC) {
8056 if (User->getOperand(0) == Inputs[i] ||
8057 User->getOperand(1) == Inputs[i])
8063 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8064 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8065 UE = PromOps[i].getNode()->use_end();
8068 if (User != N && !Visited.count(User))
8071 // Make sure that we're not going to promote the non-output-value
8072 // operand(s) or SELECT or SELECT_CC.
8073 // FIXME: Although we could sometimes handle this, and it does occur in
8074 // practice that one of the condition inputs to the select is also one of
8075 // the outputs, we currently can't deal with this.
8076 if (User->getOpcode() == ISD::SELECT) {
8077 if (User->getOperand(0) == PromOps[i])
8079 } else if (User->getOpcode() == ISD::SELECT_CC) {
8080 if (User->getOperand(0) == PromOps[i] ||
8081 User->getOperand(1) == PromOps[i])
8087 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8088 bool ReallyNeedsExt = false;
8089 if (N->getOpcode() != ISD::ANY_EXTEND) {
8090 // If all of the inputs are not already sign/zero extended, then
8091 // we'll still need to do that at the end.
8092 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8093 if (isa<ConstantSDNode>(Inputs[i]))
8097 Inputs[i].getOperand(0).getValueSizeInBits();
8098 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8100 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8101 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8102 APInt::getHighBitsSet(OpBits,
8103 OpBits-PromBits))) ||
8104 (N->getOpcode() == ISD::SIGN_EXTEND &&
8105 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8106 (OpBits-(PromBits-1)))) {
8107 ReallyNeedsExt = true;
8113 // Replace all inputs, either with the truncation operand, or a
8114 // truncation or extension to the final output type.
8115 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8116 // Constant inputs need to be replaced with the to-be-promoted nodes that
8117 // use them because they might have users outside of the cluster of
8119 if (isa<ConstantSDNode>(Inputs[i]))
8122 SDValue InSrc = Inputs[i].getOperand(0);
8123 if (Inputs[i].getValueType() == N->getValueType(0))
8124 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8125 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8126 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8127 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8128 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8129 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8130 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8132 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8133 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8136 // Replace all operations (these are all the same, but have a different
8137 // (promoted) return type). DAG.getNode will validate that the types of
8138 // a binary operator match, so go through the list in reverse so that
8139 // we've likely promoted both operands first.
8140 while (!PromOps.empty()) {
8141 SDValue PromOp = PromOps.back();
8145 switch (PromOp.getOpcode()) {
8146 default: C = 0; break;
8147 case ISD::SELECT: C = 1; break;
8148 case ISD::SELECT_CC: C = 2; break;
8151 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8152 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8153 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8154 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8155 // The to-be-promoted operands of this node have not yet been
8156 // promoted (this should be rare because we're going through the
8157 // list backward, but if one of the operands has several users in
8158 // this cluster of to-be-promoted nodes, it is possible).
8159 PromOps.insert(PromOps.begin(), PromOp);
8163 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8164 PromOp.getNode()->op_end());
8166 // If this node has constant inputs, then they'll need to be promoted here.
8167 for (unsigned i = 0; i < 2; ++i) {
8168 if (!isa<ConstantSDNode>(Ops[C+i]))
8170 if (Ops[C+i].getValueType() == N->getValueType(0))
8173 if (N->getOpcode() == ISD::SIGN_EXTEND)
8174 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8175 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8176 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8178 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8181 DAG.ReplaceAllUsesOfValueWith(PromOp,
8182 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8185 // Now we're left with the initial extension itself.
8186 if (!ReallyNeedsExt)
8187 return N->getOperand(0);
8189 // To zero extend, just mask off everything except for the first bit (in the
8191 if (N->getOpcode() == ISD::ZERO_EXTEND)
8192 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8193 DAG.getConstant(APInt::getLowBitsSet(
8194 N->getValueSizeInBits(0), PromBits),
8195 N->getValueType(0)));
8197 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8198 "Invalid extension type");
8199 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8201 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8202 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8203 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8204 N->getOperand(0), ShiftCst), ShiftCst);
8207 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8208 DAGCombinerInfo &DCI) const {
8209 const TargetMachine &TM = getTargetMachine();
8210 SelectionDAG &DAG = DCI.DAG;
8212 switch (N->getOpcode()) {
8215 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8216 if (C->isNullValue()) // 0 << V -> 0.
8217 return N->getOperand(0);
8221 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8222 if (C->isNullValue()) // 0 >>u V -> 0.
8223 return N->getOperand(0);
8227 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8228 if (C->isNullValue() || // 0 >>s V -> 0.
8229 C->isAllOnesValue()) // -1 >>s V -> -1.
8230 return N->getOperand(0);
8233 case ISD::SIGN_EXTEND:
8234 case ISD::ZERO_EXTEND:
8235 case ISD::ANY_EXTEND:
8236 return DAGCombineExtBoolTrunc(N, DCI);
8239 case ISD::SELECT_CC:
8240 return DAGCombineTruncBoolExt(N, DCI);
8241 case ISD::SINT_TO_FP:
8242 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8243 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8244 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8245 // We allow the src/dst to be either f32/f64, but the intermediate
8246 // type must be i64.
8247 if (N->getOperand(0).getValueType() == MVT::i64 &&
8248 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8249 SDValue Val = N->getOperand(0).getOperand(0);
8250 if (Val.getValueType() == MVT::f32) {
8251 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8252 DCI.AddToWorklist(Val.getNode());
8255 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8256 DCI.AddToWorklist(Val.getNode());
8257 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8258 DCI.AddToWorklist(Val.getNode());
8259 if (N->getValueType(0) == MVT::f32) {
8260 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8261 DAG.getIntPtrConstant(0));
8262 DCI.AddToWorklist(Val.getNode());
8265 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8266 // If the intermediate type is i32, we can avoid the load/store here
8273 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8274 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8275 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8276 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8277 N->getOperand(1).getValueType() == MVT::i32 &&
8278 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8279 SDValue Val = N->getOperand(1).getOperand(0);
8280 if (Val.getValueType() == MVT::f32) {
8281 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8282 DCI.AddToWorklist(Val.getNode());
8284 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8285 DCI.AddToWorklist(Val.getNode());
8288 N->getOperand(0), Val, N->getOperand(2),
8289 DAG.getValueType(N->getOperand(1).getValueType())
8292 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8293 DAG.getVTList(MVT::Other), Ops,
8294 cast<StoreSDNode>(N)->getMemoryVT(),
8295 cast<StoreSDNode>(N)->getMemOperand());
8296 DCI.AddToWorklist(Val.getNode());
8300 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8301 if (cast<StoreSDNode>(N)->isUnindexed() &&
8302 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8303 N->getOperand(1).getNode()->hasOneUse() &&
8304 (N->getOperand(1).getValueType() == MVT::i32 ||
8305 N->getOperand(1).getValueType() == MVT::i16 ||
8306 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8307 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8308 N->getOperand(1).getValueType() == MVT::i64))) {
8309 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8310 // Do an any-extend to 32-bits if this is a half-word input.
8311 if (BSwapOp.getValueType() == MVT::i16)
8312 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8315 N->getOperand(0), BSwapOp, N->getOperand(2),
8316 DAG.getValueType(N->getOperand(1).getValueType())
8319 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8320 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8321 cast<StoreSDNode>(N)->getMemOperand());
8325 LoadSDNode *LD = cast<LoadSDNode>(N);
8326 EVT VT = LD->getValueType(0);
8327 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8328 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8329 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8330 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8331 // P8 and later hardware should just use LOAD.
8332 !TM.getSubtarget<PPCSubtarget>().hasP8Vector() &&
8333 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8334 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8335 LD->getAlignment() < ABIAlignment) {
8336 // This is a type-legal unaligned Altivec load.
8337 SDValue Chain = LD->getChain();
8338 SDValue Ptr = LD->getBasePtr();
8339 bool isLittleEndian = Subtarget.isLittleEndian();
8341 // This implements the loading of unaligned vectors as described in
8342 // the venerable Apple Velocity Engine overview. Specifically:
8343 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8344 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8346 // The general idea is to expand a sequence of one or more unaligned
8347 // loads into an alignment-based permutation-control instruction (lvsl
8348 // or lvsr), a series of regular vector loads (which always truncate
8349 // their input address to an aligned address), and a series of
8350 // permutations. The results of these permutations are the requested
8351 // loaded values. The trick is that the last "extra" load is not taken
8352 // from the address you might suspect (sizeof(vector) bytes after the
8353 // last requested load), but rather sizeof(vector) - 1 bytes after the
8354 // last requested vector. The point of this is to avoid a page fault if
8355 // the base address happened to be aligned. This works because if the
8356 // base address is aligned, then adding less than a full vector length
8357 // will cause the last vector in the sequence to be (re)loaded.
8358 // Otherwise, the next vector will be fetched as you might suspect was
8361 // We might be able to reuse the permutation generation from
8362 // a different base address offset from this one by an aligned amount.
8363 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8364 // optimization later.
8365 Intrinsic::ID Intr = (isLittleEndian ?
8366 Intrinsic::ppc_altivec_lvsr :
8367 Intrinsic::ppc_altivec_lvsl);
8368 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8370 // Create the new MMO for the new base load. It is like the original MMO,
8371 // but represents an area in memory almost twice the vector size centered
8372 // on the original address. If the address is unaligned, we might start
8373 // reading up to (sizeof(vector)-1) bytes below the address of the
8374 // original unaligned load.
8375 MachineFunction &MF = DAG.getMachineFunction();
8376 MachineMemOperand *BaseMMO =
8377 MF.getMachineMemOperand(LD->getMemOperand(),
8378 -LD->getMemoryVT().getStoreSize()+1,
8379 2*LD->getMemoryVT().getStoreSize()-1);
8381 // Create the new base load.
8382 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8384 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8386 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8387 DAG.getVTList(MVT::v4i32, MVT::Other),
8388 BaseLoadOps, MVT::v4i32, BaseMMO);
8390 // Note that the value of IncOffset (which is provided to the next
8391 // load's pointer info offset value, and thus used to calculate the
8392 // alignment), and the value of IncValue (which is actually used to
8393 // increment the pointer value) are different! This is because we
8394 // require the next load to appear to be aligned, even though it
8395 // is actually offset from the base pointer by a lesser amount.
8396 int IncOffset = VT.getSizeInBits() / 8;
8397 int IncValue = IncOffset;
8399 // Walk (both up and down) the chain looking for another load at the real
8400 // (aligned) offset (the alignment of the other load does not matter in
8401 // this case). If found, then do not use the offset reduction trick, as
8402 // that will prevent the loads from being later combined (as they would
8403 // otherwise be duplicates).
8404 if (!findConsecutiveLoad(LD, DAG))
8407 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8408 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8410 MachineMemOperand *ExtraMMO =
8411 MF.getMachineMemOperand(LD->getMemOperand(),
8412 1, 2*LD->getMemoryVT().getStoreSize()-1);
8413 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8415 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8416 DAG.getVTList(MVT::v4i32, MVT::Other),
8417 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8419 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8420 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8422 // Because vperm has a big-endian bias, we must reverse the order
8423 // of the input vectors and complement the permute control vector
8424 // when generating little endian code. We have already handled the
8425 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8426 // and ExtraLoad here.
8429 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8430 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8432 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8433 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8435 if (VT != MVT::v4i32)
8436 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8438 // The output of the permutation is our loaded result, the TokenFactor is
8440 DCI.CombineTo(N, Perm, TF);
8441 return SDValue(N, 0);
8445 case ISD::INTRINSIC_WO_CHAIN: {
8446 bool isLittleEndian = Subtarget.isLittleEndian();
8447 Intrinsic::ID Intr = (isLittleEndian ?
8448 Intrinsic::ppc_altivec_lvsr :
8449 Intrinsic::ppc_altivec_lvsl);
8450 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8451 N->getOperand(1)->getOpcode() == ISD::ADD) {
8452 SDValue Add = N->getOperand(1);
8454 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8455 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8456 Add.getValueType().getScalarType().getSizeInBits()))) {
8457 SDNode *BasePtr = Add->getOperand(0).getNode();
8458 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8459 UE = BasePtr->use_end(); UI != UE; ++UI) {
8460 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8461 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8463 // We've found another LVSL/LVSR, and this address is an aligned
8464 // multiple of that one. The results will be the same, so use the
8465 // one we've just found instead.
8467 return SDValue(*UI, 0);
8476 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8477 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8478 N->getOperand(0).hasOneUse() &&
8479 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8480 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8481 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8482 N->getValueType(0) == MVT::i64))) {
8483 SDValue Load = N->getOperand(0);
8484 LoadSDNode *LD = cast<LoadSDNode>(Load);
8485 // Create the byte-swapping load.
8487 LD->getChain(), // Chain
8488 LD->getBasePtr(), // Ptr
8489 DAG.getValueType(N->getValueType(0)) // VT
8492 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8493 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8494 MVT::i64 : MVT::i32, MVT::Other),
8495 Ops, LD->getMemoryVT(), LD->getMemOperand());
8497 // If this is an i16 load, insert the truncate.
8498 SDValue ResVal = BSLoad;
8499 if (N->getValueType(0) == MVT::i16)
8500 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8502 // First, combine the bswap away. This makes the value produced by the
8504 DCI.CombineTo(N, ResVal);
8506 // Next, combine the load away, we give it a bogus result value but a real
8507 // chain result. The result value is dead because the bswap is dead.
8508 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8510 // Return N so it doesn't get rechecked!
8511 return SDValue(N, 0);
8515 case PPCISD::VCMP: {
8516 // If a VCMPo node already exists with exactly the same operands as this
8517 // node, use its result instead of this node (VCMPo computes both a CR6 and
8518 // a normal output).
8520 if (!N->getOperand(0).hasOneUse() &&
8521 !N->getOperand(1).hasOneUse() &&
8522 !N->getOperand(2).hasOneUse()) {
8524 // Scan all of the users of the LHS, looking for VCMPo's that match.
8525 SDNode *VCMPoNode = nullptr;
8527 SDNode *LHSN = N->getOperand(0).getNode();
8528 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8530 if (UI->getOpcode() == PPCISD::VCMPo &&
8531 UI->getOperand(1) == N->getOperand(1) &&
8532 UI->getOperand(2) == N->getOperand(2) &&
8533 UI->getOperand(0) == N->getOperand(0)) {
8538 // If there is no VCMPo node, or if the flag value has a single use, don't
8540 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8543 // Look at the (necessarily single) use of the flag value. If it has a
8544 // chain, this transformation is more complex. Note that multiple things
8545 // could use the value result, which we should ignore.
8546 SDNode *FlagUser = nullptr;
8547 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8548 FlagUser == nullptr; ++UI) {
8549 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8551 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8552 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8559 // If the user is a MFOCRF instruction, we know this is safe.
8560 // Otherwise we give up for right now.
8561 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8562 return SDValue(VCMPoNode, 0);
8567 SDValue Cond = N->getOperand(1);
8568 SDValue Target = N->getOperand(2);
8570 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8571 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8572 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8574 // We now need to make the intrinsic dead (it cannot be instruction
8576 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8577 assert(Cond.getNode()->hasOneUse() &&
8578 "Counter decrement has more than one use");
8580 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8581 N->getOperand(0), Target);
8586 // If this is a branch on an altivec predicate comparison, lower this so
8587 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8588 // lowering is done pre-legalize, because the legalizer lowers the predicate
8589 // compare down to code that is difficult to reassemble.
8590 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8591 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8593 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8594 // value. If so, pass-through the AND to get to the intrinsic.
8595 if (LHS.getOpcode() == ISD::AND &&
8596 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8597 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8598 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8599 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8600 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8602 LHS = LHS.getOperand(0);
8604 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8605 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8606 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8607 isa<ConstantSDNode>(RHS)) {
8608 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8609 "Counter decrement comparison is not EQ or NE");
8611 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8612 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8613 (CC == ISD::SETNE && !Val);
8615 // We now need to make the intrinsic dead (it cannot be instruction
8617 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8618 assert(LHS.getNode()->hasOneUse() &&
8619 "Counter decrement has more than one use");
8621 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8622 N->getOperand(0), N->getOperand(4));
8628 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8629 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8630 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8631 assert(isDot && "Can't compare against a vector result!");
8633 // If this is a comparison against something other than 0/1, then we know
8634 // that the condition is never/always true.
8635 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8636 if (Val != 0 && Val != 1) {
8637 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8638 return N->getOperand(0);
8639 // Always !=, turn it into an unconditional branch.
8640 return DAG.getNode(ISD::BR, dl, MVT::Other,
8641 N->getOperand(0), N->getOperand(4));
8644 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8646 // Create the PPCISD altivec 'dot' comparison node.
8648 LHS.getOperand(2), // LHS of compare
8649 LHS.getOperand(3), // RHS of compare
8650 DAG.getConstant(CompareOpc, MVT::i32)
8652 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8653 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8655 // Unpack the result based on how the target uses it.
8656 PPC::Predicate CompOpc;
8657 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8658 default: // Can't happen, don't crash on invalid number though.
8659 case 0: // Branch on the value of the EQ bit of CR6.
8660 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8662 case 1: // Branch on the inverted value of the EQ bit of CR6.
8663 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8665 case 2: // Branch on the value of the LT bit of CR6.
8666 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8668 case 3: // Branch on the inverted value of the LT bit of CR6.
8669 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8673 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8674 DAG.getConstant(CompOpc, MVT::i32),
8675 DAG.getRegister(PPC::CR6, MVT::i32),
8676 N->getOperand(4), CompNode.getValue(1));
8685 //===----------------------------------------------------------------------===//
8686 // Inline Assembly Support
8687 //===----------------------------------------------------------------------===//
8689 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8692 const SelectionDAG &DAG,
8693 unsigned Depth) const {
8694 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8695 switch (Op.getOpcode()) {
8697 case PPCISD::LBRX: {
8698 // lhbrx is known to have the top bits cleared out.
8699 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8700 KnownZero = 0xFFFF0000;
8703 case ISD::INTRINSIC_WO_CHAIN: {
8704 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8706 case Intrinsic::ppc_altivec_vcmpbfp_p:
8707 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8708 case Intrinsic::ppc_altivec_vcmpequb_p:
8709 case Intrinsic::ppc_altivec_vcmpequh_p:
8710 case Intrinsic::ppc_altivec_vcmpequw_p:
8711 case Intrinsic::ppc_altivec_vcmpgefp_p:
8712 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8713 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8714 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8715 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8716 case Intrinsic::ppc_altivec_vcmpgtub_p:
8717 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8718 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8719 KnownZero = ~1U; // All bits but the low one are known to be zero.
8727 /// getConstraintType - Given a constraint, return the type of
8728 /// constraint it is for this target.
8729 PPCTargetLowering::ConstraintType
8730 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8731 if (Constraint.size() == 1) {
8732 switch (Constraint[0]) {
8739 return C_RegisterClass;
8741 // FIXME: While Z does indicate a memory constraint, it specifically
8742 // indicates an r+r address (used in conjunction with the 'y' modifier
8743 // in the replacement string). Currently, we're forcing the base
8744 // register to be r0 in the asm printer (which is interpreted as zero)
8745 // and forming the complete address in the second register. This is
8749 } else if (Constraint == "wc") { // individual CR bits.
8750 return C_RegisterClass;
8751 } else if (Constraint == "wa" || Constraint == "wd" ||
8752 Constraint == "wf" || Constraint == "ws") {
8753 return C_RegisterClass; // VSX registers.
8755 return TargetLowering::getConstraintType(Constraint);
8758 /// Examine constraint type and operand type and determine a weight value.
8759 /// This object must already have been set up with the operand type
8760 /// and the current alternative constraint selected.
8761 TargetLowering::ConstraintWeight
8762 PPCTargetLowering::getSingleConstraintMatchWeight(
8763 AsmOperandInfo &info, const char *constraint) const {
8764 ConstraintWeight weight = CW_Invalid;
8765 Value *CallOperandVal = info.CallOperandVal;
8766 // If we don't have a value, we can't do a match,
8767 // but allow it at the lowest weight.
8768 if (!CallOperandVal)
8770 Type *type = CallOperandVal->getType();
8772 // Look at the constraint type.
8773 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8774 return CW_Register; // an individual CR bit.
8775 else if ((StringRef(constraint) == "wa" ||
8776 StringRef(constraint) == "wd" ||
8777 StringRef(constraint) == "wf") &&
8780 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8783 switch (*constraint) {
8785 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8788 if (type->isIntegerTy())
8789 weight = CW_Register;
8792 if (type->isFloatTy())
8793 weight = CW_Register;
8796 if (type->isDoubleTy())
8797 weight = CW_Register;
8800 if (type->isVectorTy())
8801 weight = CW_Register;
8804 weight = CW_Register;
8813 std::pair<unsigned, const TargetRegisterClass*>
8814 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8816 if (Constraint.size() == 1) {
8817 // GCC RS6000 Constraint Letters
8818 switch (Constraint[0]) {
8820 if (VT == MVT::i64 && Subtarget.isPPC64())
8821 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8822 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8824 if (VT == MVT::i64 && Subtarget.isPPC64())
8825 return std::make_pair(0U, &PPC::G8RCRegClass);
8826 return std::make_pair(0U, &PPC::GPRCRegClass);
8828 if (VT == MVT::f32 || VT == MVT::i32)
8829 return std::make_pair(0U, &PPC::F4RCRegClass);
8830 if (VT == MVT::f64 || VT == MVT::i64)
8831 return std::make_pair(0U, &PPC::F8RCRegClass);
8834 return std::make_pair(0U, &PPC::VRRCRegClass);
8836 return std::make_pair(0U, &PPC::CRRCRegClass);
8838 } else if (Constraint == "wc") { // an individual CR bit.
8839 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8840 } else if (Constraint == "wa" || Constraint == "wd" ||
8841 Constraint == "wf") {
8842 return std::make_pair(0U, &PPC::VSRCRegClass);
8843 } else if (Constraint == "ws") {
8844 return std::make_pair(0U, &PPC::VSFRCRegClass);
8847 std::pair<unsigned, const TargetRegisterClass*> R =
8848 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8850 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8851 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8852 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8854 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8855 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8856 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8857 PPC::GPRCRegClass.contains(R.first)) {
8858 const TargetRegisterInfo *TRI =
8859 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
8860 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8861 PPC::sub_32, &PPC::G8RCRegClass),
8862 &PPC::G8RCRegClass);
8869 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8870 /// vector. If it is invalid, don't add anything to Ops.
8871 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8872 std::string &Constraint,
8873 std::vector<SDValue>&Ops,
8874 SelectionDAG &DAG) const {
8877 // Only support length 1 constraints.
8878 if (Constraint.length() > 1) return;
8880 char Letter = Constraint[0];
8891 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8892 if (!CST) return; // Must be an immediate to match.
8893 unsigned Value = CST->getZExtValue();
8895 default: llvm_unreachable("Unknown constraint letter!");
8896 case 'I': // "I" is a signed 16-bit constant.
8897 if ((short)Value == (int)Value)
8898 Result = DAG.getTargetConstant(Value, Op.getValueType());
8900 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8901 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8902 if ((short)Value == 0)
8903 Result = DAG.getTargetConstant(Value, Op.getValueType());
8905 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8906 if ((Value >> 16) == 0)
8907 Result = DAG.getTargetConstant(Value, Op.getValueType());
8909 case 'M': // "M" is a constant that is greater than 31.
8911 Result = DAG.getTargetConstant(Value, Op.getValueType());
8913 case 'N': // "N" is a positive constant that is an exact power of two.
8914 if ((int)Value > 0 && isPowerOf2_32(Value))
8915 Result = DAG.getTargetConstant(Value, Op.getValueType());
8917 case 'O': // "O" is the constant zero.
8919 Result = DAG.getTargetConstant(Value, Op.getValueType());
8921 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8922 if ((short)-Value == (int)-Value)
8923 Result = DAG.getTargetConstant(Value, Op.getValueType());
8930 if (Result.getNode()) {
8931 Ops.push_back(Result);
8935 // Handle standard constraint letters.
8936 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8939 // isLegalAddressingMode - Return true if the addressing mode represented
8940 // by AM is legal for this target, for a load/store of the specified type.
8941 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8943 // FIXME: PPC does not allow r+i addressing modes for vectors!
8945 // PPC allows a sign-extended 16-bit immediate field.
8946 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8949 // No global is ever allowed as a base.
8953 // PPC only support r+r,
8955 case 0: // "r+i" or just "i", depending on HasBaseReg.
8958 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8960 // Otherwise we have r+r or r+i.
8963 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8965 // Allow 2*r as r+r.
8968 // No other scales are supported.
8975 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8976 SelectionDAG &DAG) const {
8977 MachineFunction &MF = DAG.getMachineFunction();
8978 MachineFrameInfo *MFI = MF.getFrameInfo();
8979 MFI->setReturnAddressIsTaken(true);
8981 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8985 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8987 // Make sure the function does not optimize away the store of the RA to
8989 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8990 FuncInfo->setLRStoreRequired();
8991 bool isPPC64 = Subtarget.isPPC64();
8992 bool isDarwinABI = Subtarget.isDarwinABI();
8995 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8998 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8999 isPPC64? MVT::i64 : MVT::i32);
9000 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9001 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9003 MachinePointerInfo(), false, false, false, 0);
9006 // Just load the return address off the stack.
9007 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9008 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9009 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9012 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9013 SelectionDAG &DAG) const {
9015 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9017 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9018 bool isPPC64 = PtrVT == MVT::i64;
9020 MachineFunction &MF = DAG.getMachineFunction();
9021 MachineFrameInfo *MFI = MF.getFrameInfo();
9022 MFI->setFrameAddressIsTaken(true);
9024 // Naked functions never have a frame pointer, and so we use r1. For all
9025 // other functions, this decision must be delayed until during PEI.
9027 if (MF.getFunction()->getAttributes().hasAttribute(
9028 AttributeSet::FunctionIndex, Attribute::Naked))
9029 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9031 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9033 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9036 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9037 FrameAddr, MachinePointerInfo(), false, false,
9042 // FIXME? Maybe this could be a TableGen attribute on some registers and
9043 // this table could be generated automatically from RegInfo.
9044 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9046 bool isPPC64 = Subtarget.isPPC64();
9047 bool isDarwinABI = Subtarget.isDarwinABI();
9049 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9050 (!isPPC64 && VT != MVT::i32))
9051 report_fatal_error("Invalid register global variable type");
9053 bool is64Bit = isPPC64 && VT == MVT::i64;
9054 unsigned Reg = StringSwitch<unsigned>(RegName)
9055 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9056 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9057 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9058 (is64Bit ? PPC::X13 : PPC::R13))
9063 report_fatal_error("Invalid register name global variable");
9067 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9068 // The PowerPC target isn't yet aware of offsets.
9072 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9074 unsigned Intrinsic) const {
9076 switch (Intrinsic) {
9077 case Intrinsic::ppc_altivec_lvx:
9078 case Intrinsic::ppc_altivec_lvxl:
9079 case Intrinsic::ppc_altivec_lvebx:
9080 case Intrinsic::ppc_altivec_lvehx:
9081 case Intrinsic::ppc_altivec_lvewx: {
9083 switch (Intrinsic) {
9084 case Intrinsic::ppc_altivec_lvebx:
9087 case Intrinsic::ppc_altivec_lvehx:
9090 case Intrinsic::ppc_altivec_lvewx:
9098 Info.opc = ISD::INTRINSIC_W_CHAIN;
9100 Info.ptrVal = I.getArgOperand(0);
9101 Info.offset = -VT.getStoreSize()+1;
9102 Info.size = 2*VT.getStoreSize()-1;
9105 Info.readMem = true;
9106 Info.writeMem = false;
9109 case Intrinsic::ppc_altivec_stvx:
9110 case Intrinsic::ppc_altivec_stvxl:
9111 case Intrinsic::ppc_altivec_stvebx:
9112 case Intrinsic::ppc_altivec_stvehx:
9113 case Intrinsic::ppc_altivec_stvewx: {
9115 switch (Intrinsic) {
9116 case Intrinsic::ppc_altivec_stvebx:
9119 case Intrinsic::ppc_altivec_stvehx:
9122 case Intrinsic::ppc_altivec_stvewx:
9130 Info.opc = ISD::INTRINSIC_VOID;
9132 Info.ptrVal = I.getArgOperand(1);
9133 Info.offset = -VT.getStoreSize()+1;
9134 Info.size = 2*VT.getStoreSize()-1;
9137 Info.readMem = false;
9138 Info.writeMem = true;
9148 /// getOptimalMemOpType - Returns the target specific optimal type for load
9149 /// and store operations as a result of memset, memcpy, and memmove
9150 /// lowering. If DstAlign is zero that means it's safe to destination
9151 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9152 /// means there isn't a need to check it against alignment requirement,
9153 /// probably because the source does not need to be loaded. If 'IsMemset' is
9154 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9155 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9156 /// source is constant so it does not need to be loaded.
9157 /// It returns EVT::Other if the type should be determined using generic
9158 /// target-independent logic.
9159 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9160 unsigned DstAlign, unsigned SrcAlign,
9161 bool IsMemset, bool ZeroMemset,
9163 MachineFunction &MF) const {
9164 if (Subtarget.isPPC64()) {
9171 /// \brief Returns true if it is beneficial to convert a load of a constant
9172 /// to just the constant itself.
9173 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9175 assert(Ty->isIntegerTy());
9177 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9178 if (BitSize == 0 || BitSize > 64)
9183 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9184 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9186 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9187 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9188 return NumBits1 == 64 && NumBits2 == 32;
9191 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9192 if (!VT1.isInteger() || !VT2.isInteger())
9194 unsigned NumBits1 = VT1.getSizeInBits();
9195 unsigned NumBits2 = VT2.getSizeInBits();
9196 return NumBits1 == 64 && NumBits2 == 32;
9199 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9200 return isInt<16>(Imm) || isUInt<16>(Imm);
9203 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9204 return isInt<16>(Imm) || isUInt<16>(Imm);
9207 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9211 if (DisablePPCUnaligned)
9214 // PowerPC supports unaligned memory access for simple non-vector types.
9215 // Although accessing unaligned addresses is not as efficient as accessing
9216 // aligned addresses, it is generally more efficient than manual expansion,
9217 // and generally only traps for software emulation when crossing page
9223 if (VT.getSimpleVT().isVector()) {
9224 if (Subtarget.hasVSX()) {
9225 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9226 VT != MVT::v4f32 && VT != MVT::v4i32)
9233 if (VT == MVT::ppcf128)
9242 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9243 VT = VT.getScalarType();
9248 switch (VT.getSimpleVT().SimpleTy) {
9260 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9261 EVT VT , unsigned DefinedValues) const {
9262 if (VT == MVT::v2i64)
9265 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9268 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9269 if (DisableILPPref || Subtarget.enableMachineScheduler())
9270 return TargetLowering::getSchedulingPreference(N);
9275 // Create a fast isel object.
9277 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9278 const TargetLibraryInfo *LibInfo) const {
9279 return PPC::createFastISel(FuncInfo, LibInfo);