1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
49 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
50 if (TM.getSubtargetImpl()->isDarwin())
51 return new TargetLoweringObjectFileMachO();
53 if (TM.getSubtargetImpl()->isSVR4ABI())
54 return new PPC64LinuxTargetObjectFile();
56 return new TargetLoweringObjectFileELF();
59 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
60 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
61 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
65 // Use _setjmp/_longjmp instead of setjmp/longjmp.
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
69 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
70 // arguments are at least 4/8 bytes aligned.
71 bool isPPC64 = Subtarget->isPPC64();
72 setMinStackArgumentAlignment(isPPC64 ? 8:4);
74 // Set up the register classes.
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
79 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 // This is used in the ppcf128->int sequence. Note it has different semantics
98 // from FP_ROUND: that rounds to nearest, this rounds to zero.
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
101 // We do not currently implement these libm ops for PowerPC.
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
109 // PowerPC has no SREM/UREM instructions
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
115 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
125 // We don't support sin/cos/sqrt/fmod/pow
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
141 // If we're enabling GP optimizations, use hardware square root
142 if (!Subtarget->hasFSQRT() &&
143 !(TM.Options.UnsafeFPMath &&
144 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
147 if (!Subtarget->hasFSQRT() &&
148 !(TM.Options.UnsafeFPMath &&
149 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 if (Subtarget->hasFCPSGN()) {
153 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
154 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
156 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
157 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
160 if (Subtarget->hasFPRND()) {
161 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
162 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
163 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
164 setOperationAction(ISD::FROUND, MVT::f64, Legal);
166 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
168 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
169 setOperationAction(ISD::FROUND, MVT::f32, Legal);
172 // PowerPC does not have BSWAP, CTPOP or CTTZ
173 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
174 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
175 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
176 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
177 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
178 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
179 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
180 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
182 if (Subtarget->hasPOPCNTD()) {
183 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
184 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
186 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
187 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
190 // PowerPC does not have ROTR
191 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
192 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
194 // PowerPC does not have Select
195 setOperationAction(ISD::SELECT, MVT::i32, Expand);
196 setOperationAction(ISD::SELECT, MVT::i64, Expand);
197 setOperationAction(ISD::SELECT, MVT::f32, Expand);
198 setOperationAction(ISD::SELECT, MVT::f64, Expand);
200 // PowerPC wants to turn select_cc of FP into fsel when possible.
201 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
202 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
204 // PowerPC wants to optimize integer setcc a bit
205 setOperationAction(ISD::SETCC, MVT::i32, Custom);
207 // PowerPC does not have BRCOND which requires SetCC
208 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
210 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
212 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
213 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
215 // PowerPC does not have [U|S]INT_TO_FP
216 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
217 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
219 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
220 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
221 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
222 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
224 // We cannot sextinreg(i1). Expand to shifts.
225 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
227 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
228 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
229 // support continuation, user-level threading, and etc.. As a result, no
230 // other SjLj exception interfaces are implemented and please don't build
231 // your own exception handling based on them.
232 // LLVM/Clang supports zero-cost DWARF exception handling.
233 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
234 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
236 // We want to legalize GlobalAddress and ConstantPool nodes into the
237 // appropriate instructions to materialize the address.
238 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
239 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
240 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
241 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
242 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
244 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
245 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
246 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
247 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
250 setOperationAction(ISD::TRAP, MVT::Other, Legal);
252 // TRAMPOLINE is custom lowered.
253 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
254 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
256 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
257 setOperationAction(ISD::VASTART , MVT::Other, Custom);
259 if (Subtarget->isSVR4ABI()) {
261 // VAARG always uses double-word chunks, so promote anything smaller.
262 setOperationAction(ISD::VAARG, MVT::i1, Promote);
263 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
264 setOperationAction(ISD::VAARG, MVT::i8, Promote);
265 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
266 setOperationAction(ISD::VAARG, MVT::i16, Promote);
267 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
268 setOperationAction(ISD::VAARG, MVT::i32, Promote);
269 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
270 setOperationAction(ISD::VAARG, MVT::Other, Expand);
272 // VAARG is custom lowered with the 32-bit SVR4 ABI.
273 setOperationAction(ISD::VAARG, MVT::Other, Custom);
274 setOperationAction(ISD::VAARG, MVT::i64, Custom);
277 setOperationAction(ISD::VAARG, MVT::Other, Expand);
279 if (Subtarget->isSVR4ABI() && !isPPC64)
280 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
281 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
283 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
285 // Use the default implementation.
286 setOperationAction(ISD::VAEND , MVT::Other, Expand);
287 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
288 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
289 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
290 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
292 // We want to custom lower some of our intrinsics.
293 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
295 // To handle counter-based loop conditions.
296 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
298 // Comparisons that require checking two conditions.
299 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
300 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
301 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
302 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
303 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
310 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
312 if (Subtarget->has64BitSupport()) {
313 // They also have instructions for converting between i64 and fp.
314 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
315 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
316 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
317 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
318 // This is just the low 32 bits of a (signed) fp->i64 conversion.
319 // We cannot do this with Promote because i64 is not a legal type.
320 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
322 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
323 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
325 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
326 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
329 // With the instructions enabled under FPCVT, we can do everything.
330 if (PPCSubTarget.hasFPCVT()) {
331 if (Subtarget->has64BitSupport()) {
332 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
334 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
335 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
338 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
339 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
340 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
341 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
344 if (Subtarget->use64BitRegs()) {
345 // 64-bit PowerPC implementations can support i64 types directly
346 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
347 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
348 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
349 // 64-bit PowerPC wants to expand i128 shifts itself.
350 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
351 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
352 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
354 // 32-bit PowerPC wants to expand i64 shifts itself.
355 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
356 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
357 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
360 if (Subtarget->hasAltivec()) {
361 // First set operation action for all vector types to expand. Then we
362 // will selectively turn on ones that can be effectively codegen'd.
363 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
364 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
365 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
367 // add/sub are legal for all supported vector VT's.
368 setOperationAction(ISD::ADD , VT, Legal);
369 setOperationAction(ISD::SUB , VT, Legal);
371 // We promote all shuffles to v16i8.
372 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
373 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
375 // We promote all non-typed operations to v4i32.
376 setOperationAction(ISD::AND , VT, Promote);
377 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
378 setOperationAction(ISD::OR , VT, Promote);
379 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
380 setOperationAction(ISD::XOR , VT, Promote);
381 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
382 setOperationAction(ISD::LOAD , VT, Promote);
383 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
384 setOperationAction(ISD::SELECT, VT, Promote);
385 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
386 setOperationAction(ISD::STORE, VT, Promote);
387 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
389 // No other operations are legal.
390 setOperationAction(ISD::MUL , VT, Expand);
391 setOperationAction(ISD::SDIV, VT, Expand);
392 setOperationAction(ISD::SREM, VT, Expand);
393 setOperationAction(ISD::UDIV, VT, Expand);
394 setOperationAction(ISD::UREM, VT, Expand);
395 setOperationAction(ISD::FDIV, VT, Expand);
396 setOperationAction(ISD::FREM, VT, Expand);
397 setOperationAction(ISD::FNEG, VT, Expand);
398 setOperationAction(ISD::FSQRT, VT, Expand);
399 setOperationAction(ISD::FLOG, VT, Expand);
400 setOperationAction(ISD::FLOG10, VT, Expand);
401 setOperationAction(ISD::FLOG2, VT, Expand);
402 setOperationAction(ISD::FEXP, VT, Expand);
403 setOperationAction(ISD::FEXP2, VT, Expand);
404 setOperationAction(ISD::FSIN, VT, Expand);
405 setOperationAction(ISD::FCOS, VT, Expand);
406 setOperationAction(ISD::FABS, VT, Expand);
407 setOperationAction(ISD::FPOWI, VT, Expand);
408 setOperationAction(ISD::FFLOOR, VT, Expand);
409 setOperationAction(ISD::FCEIL, VT, Expand);
410 setOperationAction(ISD::FTRUNC, VT, Expand);
411 setOperationAction(ISD::FRINT, VT, Expand);
412 setOperationAction(ISD::FNEARBYINT, VT, Expand);
413 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
414 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
415 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
416 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
417 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
418 setOperationAction(ISD::UDIVREM, VT, Expand);
419 setOperationAction(ISD::SDIVREM, VT, Expand);
420 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
421 setOperationAction(ISD::FPOW, VT, Expand);
422 setOperationAction(ISD::CTPOP, VT, Expand);
423 setOperationAction(ISD::CTLZ, VT, Expand);
424 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
425 setOperationAction(ISD::CTTZ, VT, Expand);
426 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
427 setOperationAction(ISD::VSELECT, VT, Expand);
428 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
430 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
431 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
432 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
433 setTruncStoreAction(VT, InnerVT, Expand);
435 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
436 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
437 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
440 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
441 // with merges, splats, etc.
442 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
444 setOperationAction(ISD::AND , MVT::v4i32, Legal);
445 setOperationAction(ISD::OR , MVT::v4i32, Legal);
446 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
447 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
448 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
449 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
450 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
451 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
452 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
453 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
454 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
455 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
456 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
457 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
459 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
460 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
461 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
462 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
464 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
465 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
467 if (TM.Options.UnsafeFPMath) {
468 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
469 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
472 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
473 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
474 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
476 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
477 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
479 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
480 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
481 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
482 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
484 // Altivec does not contain unordered floating-point compare instructions
485 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
486 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
487 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
488 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
489 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
490 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
492 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
493 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
496 if (Subtarget->has64BitSupport()) {
497 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
498 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
501 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
502 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
504 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
506 setBooleanContents(ZeroOrOneBooleanContent);
507 // Altivec instructions set fields to all zeros or all ones.
508 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
511 setStackPointerRegisterToSaveRestore(PPC::X1);
512 setExceptionPointerRegister(PPC::X3);
513 setExceptionSelectorRegister(PPC::X4);
515 setStackPointerRegisterToSaveRestore(PPC::R1);
516 setExceptionPointerRegister(PPC::R3);
517 setExceptionSelectorRegister(PPC::R4);
520 // We have target-specific dag combine patterns for the following nodes:
521 setTargetDAGCombine(ISD::SINT_TO_FP);
522 setTargetDAGCombine(ISD::LOAD);
523 setTargetDAGCombine(ISD::STORE);
524 setTargetDAGCombine(ISD::BR_CC);
525 setTargetDAGCombine(ISD::BSWAP);
526 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
528 // Use reciprocal estimates.
529 if (TM.Options.UnsafeFPMath) {
530 setTargetDAGCombine(ISD::FDIV);
531 setTargetDAGCombine(ISD::FSQRT);
534 // Darwin long double math library functions have $LDBL128 appended.
535 if (Subtarget->isDarwin()) {
536 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
537 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
538 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
539 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
540 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
541 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
542 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
543 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
544 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
545 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
548 setMinFunctionAlignment(2);
549 if (PPCSubTarget.isDarwin())
550 setPrefFunctionAlignment(4);
552 if (isPPC64 && Subtarget->isJITCodeModel())
553 // Temporary workaround for the inability of PPC64 JIT to handle jump
555 setSupportJumpTables(false);
557 setInsertFencesForAtomic(true);
559 setSchedulingPreference(Sched::Hybrid);
561 computeRegisterProperties();
563 // The Freescale cores does better with aggressive inlining of memcpy and
564 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
565 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
566 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
567 MaxStoresPerMemset = 32;
568 MaxStoresPerMemsetOptSize = 16;
569 MaxStoresPerMemcpy = 32;
570 MaxStoresPerMemcpyOptSize = 8;
571 MaxStoresPerMemmove = 32;
572 MaxStoresPerMemmoveOptSize = 8;
574 setPrefFunctionAlignment(4);
578 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
579 /// function arguments in the caller parameter area.
580 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
581 const TargetMachine &TM = getTargetMachine();
582 // Darwin passes everything on 4 byte boundary.
583 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
586 // 16byte and wider vectors are passed on 16byte boundary.
587 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
588 if (VTy->getBitWidth() >= 128)
591 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
592 if (PPCSubTarget.isPPC64())
598 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
601 case PPCISD::FSEL: return "PPCISD::FSEL";
602 case PPCISD::FCFID: return "PPCISD::FCFID";
603 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
604 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
605 case PPCISD::FRE: return "PPCISD::FRE";
606 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
607 case PPCISD::STFIWX: return "PPCISD::STFIWX";
608 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
609 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
610 case PPCISD::VPERM: return "PPCISD::VPERM";
611 case PPCISD::Hi: return "PPCISD::Hi";
612 case PPCISD::Lo: return "PPCISD::Lo";
613 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
614 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
615 case PPCISD::LOAD: return "PPCISD::LOAD";
616 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
617 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
618 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
619 case PPCISD::SRL: return "PPCISD::SRL";
620 case PPCISD::SRA: return "PPCISD::SRA";
621 case PPCISD::SHL: return "PPCISD::SHL";
622 case PPCISD::CALL: return "PPCISD::CALL";
623 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
624 case PPCISD::MTCTR: return "PPCISD::MTCTR";
625 case PPCISD::BCTRL: return "PPCISD::BCTRL";
626 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
627 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
628 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
629 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
630 case PPCISD::VCMP: return "PPCISD::VCMP";
631 case PPCISD::VCMPo: return "PPCISD::VCMPo";
632 case PPCISD::LBRX: return "PPCISD::LBRX";
633 case PPCISD::STBRX: return "PPCISD::STBRX";
634 case PPCISD::LARX: return "PPCISD::LARX";
635 case PPCISD::STCX: return "PPCISD::STCX";
636 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
637 case PPCISD::BDNZ: return "PPCISD::BDNZ";
638 case PPCISD::BDZ: return "PPCISD::BDZ";
639 case PPCISD::MFFS: return "PPCISD::MFFS";
640 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
641 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
642 case PPCISD::CR6SET: return "PPCISD::CR6SET";
643 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
644 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
645 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
646 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
647 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
648 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
649 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
650 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
651 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
652 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
653 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
654 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
655 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
656 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
657 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
658 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
659 case PPCISD::SC: return "PPCISD::SC";
663 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
666 return VT.changeVectorElementTypeToInteger();
669 //===----------------------------------------------------------------------===//
670 // Node matching predicates, for use by the tblgen matching code.
671 //===----------------------------------------------------------------------===//
673 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
674 static bool isFloatingPointZero(SDValue Op) {
675 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
676 return CFP->getValueAPF().isZero();
677 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
678 // Maybe this has already been legalized into the constant pool?
679 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
680 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
681 return CFP->getValueAPF().isZero();
686 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
687 /// true if Op is undef or if it matches the specified value.
688 static bool isConstantOrUndef(int Op, int Val) {
689 return Op < 0 || Op == Val;
692 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
693 /// VPKUHUM instruction.
694 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
696 for (unsigned i = 0; i != 16; ++i)
697 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
700 for (unsigned i = 0; i != 8; ++i)
701 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
702 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
708 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
709 /// VPKUWUM instruction.
710 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
712 for (unsigned i = 0; i != 16; i += 2)
713 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
714 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
717 for (unsigned i = 0; i != 8; i += 2)
718 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
719 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
720 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
721 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
727 /// isVMerge - Common function, used to match vmrg* shuffles.
729 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
730 unsigned LHSStart, unsigned RHSStart) {
731 assert(N->getValueType(0) == MVT::v16i8 &&
732 "PPC only supports shuffles by bytes!");
733 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
734 "Unsupported merge size!");
736 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
737 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
738 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
739 LHSStart+j+i*UnitSize) ||
740 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
741 RHSStart+j+i*UnitSize))
747 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
748 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
749 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
752 return isVMerge(N, UnitSize, 8, 24);
753 return isVMerge(N, UnitSize, 8, 8);
756 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
757 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
758 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
761 return isVMerge(N, UnitSize, 0, 16);
762 return isVMerge(N, UnitSize, 0, 0);
766 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
767 /// amount, otherwise return -1.
768 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
769 assert(N->getValueType(0) == MVT::v16i8 &&
770 "PPC only supports shuffles by bytes!");
772 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
774 // Find the first non-undef value in the shuffle mask.
776 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
779 if (i == 16) return -1; // all undef.
781 // Otherwise, check to see if the rest of the elements are consecutively
782 // numbered from this value.
783 unsigned ShiftAmt = SVOp->getMaskElt(i);
784 if (ShiftAmt < i) return -1;
788 // Check the rest of the elements to see if they are consecutive.
789 for (++i; i != 16; ++i)
790 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
793 // Check the rest of the elements to see if they are consecutive.
794 for (++i; i != 16; ++i)
795 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
801 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
802 /// specifies a splat of a single element that is suitable for input to
803 /// VSPLTB/VSPLTH/VSPLTW.
804 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
805 assert(N->getValueType(0) == MVT::v16i8 &&
806 (EltSize == 1 || EltSize == 2 || EltSize == 4));
808 // This is a splat operation if each element of the permute is the same, and
809 // if the value doesn't reference the second vector.
810 unsigned ElementBase = N->getMaskElt(0);
812 // FIXME: Handle UNDEF elements too!
813 if (ElementBase >= 16)
816 // Check that the indices are consecutive, in the case of a multi-byte element
817 // splatted with a v16i8 mask.
818 for (unsigned i = 1; i != EltSize; ++i)
819 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
822 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
823 if (N->getMaskElt(i) < 0) continue;
824 for (unsigned j = 0; j != EltSize; ++j)
825 if (N->getMaskElt(i+j) != N->getMaskElt(j))
831 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
833 bool PPC::isAllNegativeZeroVector(SDNode *N) {
834 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
836 APInt APVal, APUndef;
840 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
841 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
842 return CFP->getValueAPF().isNegZero();
847 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
848 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
849 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
850 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
851 assert(isSplatShuffleMask(SVOp, EltSize));
852 return SVOp->getMaskElt(0) / EltSize;
855 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
856 /// by using a vspltis[bhw] instruction of the specified element size, return
857 /// the constant being splatted. The ByteSize field indicates the number of
858 /// bytes of each element [124] -> [bhw].
859 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
862 // If ByteSize of the splat is bigger than the element size of the
863 // build_vector, then we have a case where we are checking for a splat where
864 // multiple elements of the buildvector are folded together into a single
865 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
866 unsigned EltSize = 16/N->getNumOperands();
867 if (EltSize < ByteSize) {
868 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
869 SDValue UniquedVals[4];
870 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
872 // See if all of the elements in the buildvector agree across.
873 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
874 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
875 // If the element isn't a constant, bail fully out.
876 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
879 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
880 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
881 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
882 return SDValue(); // no match.
885 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
886 // either constant or undef values that are identical for each chunk. See
887 // if these chunks can form into a larger vspltis*.
889 // Check to see if all of the leading entries are either 0 or -1. If
890 // neither, then this won't fit into the immediate field.
891 bool LeadingZero = true;
892 bool LeadingOnes = true;
893 for (unsigned i = 0; i != Multiple-1; ++i) {
894 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
896 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
897 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
899 // Finally, check the least significant entry.
901 if (UniquedVals[Multiple-1].getNode() == 0)
902 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
903 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
905 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
908 if (UniquedVals[Multiple-1].getNode() == 0)
909 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
910 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
911 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
912 return DAG.getTargetConstant(Val, MVT::i32);
918 // Check to see if this buildvec has a single non-undef value in its elements.
919 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
920 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
921 if (OpVal.getNode() == 0)
922 OpVal = N->getOperand(i);
923 else if (OpVal != N->getOperand(i))
927 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
929 unsigned ValSizeInBytes = EltSize;
931 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
932 Value = CN->getZExtValue();
933 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
934 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
935 Value = FloatToBits(CN->getValueAPF().convertToFloat());
938 // If the splat value is larger than the element value, then we can never do
939 // this splat. The only case that we could fit the replicated bits into our
940 // immediate field for would be zero, and we prefer to use vxor for it.
941 if (ValSizeInBytes < ByteSize) return SDValue();
943 // If the element value is larger than the splat value, cut it in half and
944 // check to see if the two halves are equal. Continue doing this until we
945 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
946 while (ValSizeInBytes > ByteSize) {
947 ValSizeInBytes >>= 1;
949 // If the top half equals the bottom half, we're still ok.
950 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
951 (Value & ((1 << (8*ValSizeInBytes))-1)))
955 // Properly sign extend the value.
956 int MaskVal = SignExtend32(Value, ByteSize * 8);
958 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
959 if (MaskVal == 0) return SDValue();
961 // Finally, if this value fits in a 5 bit sext field, return it
962 if (SignExtend32<5>(MaskVal) == MaskVal)
963 return DAG.getTargetConstant(MaskVal, MVT::i32);
967 //===----------------------------------------------------------------------===//
968 // Addressing Mode Selection
969 //===----------------------------------------------------------------------===//
971 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
972 /// or 64-bit immediate, and if the value can be accurately represented as a
973 /// sign extension from a 16-bit value. If so, this returns true and the
975 static bool isIntS16Immediate(SDNode *N, short &Imm) {
976 if (N->getOpcode() != ISD::Constant)
979 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
980 if (N->getValueType(0) == MVT::i32)
981 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
983 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
985 static bool isIntS16Immediate(SDValue Op, short &Imm) {
986 return isIntS16Immediate(Op.getNode(), Imm);
990 /// SelectAddressRegReg - Given the specified addressed, check to see if it
991 /// can be represented as an indexed [r+r] operation. Returns false if it
992 /// can be more efficiently represented with [r+imm].
993 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
995 SelectionDAG &DAG) const {
997 if (N.getOpcode() == ISD::ADD) {
998 if (isIntS16Immediate(N.getOperand(1), imm))
1000 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1001 return false; // r+i
1003 Base = N.getOperand(0);
1004 Index = N.getOperand(1);
1006 } else if (N.getOpcode() == ISD::OR) {
1007 if (isIntS16Immediate(N.getOperand(1), imm))
1008 return false; // r+i can fold it if we can.
1010 // If this is an or of disjoint bitfields, we can codegen this as an add
1011 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1013 APInt LHSKnownZero, LHSKnownOne;
1014 APInt RHSKnownZero, RHSKnownOne;
1015 DAG.ComputeMaskedBits(N.getOperand(0),
1016 LHSKnownZero, LHSKnownOne);
1018 if (LHSKnownZero.getBoolValue()) {
1019 DAG.ComputeMaskedBits(N.getOperand(1),
1020 RHSKnownZero, RHSKnownOne);
1021 // If all of the bits are known zero on the LHS or RHS, the add won't
1023 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1024 Base = N.getOperand(0);
1025 Index = N.getOperand(1);
1034 // If we happen to be doing an i64 load or store into a stack slot that has
1035 // less than a 4-byte alignment, then the frame-index elimination may need to
1036 // use an indexed load or store instruction (because the offset may not be a
1037 // multiple of 4). The extra register needed to hold the offset comes from the
1038 // register scavenger, and it is possible that the scavenger will need to use
1039 // an emergency spill slot. As a result, we need to make sure that a spill slot
1040 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1042 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1043 // FIXME: This does not handle the LWA case.
1047 // NOTE: We'll exclude negative FIs here, which come from argument
1048 // lowering, because there are no known test cases triggering this problem
1049 // using packed structures (or similar). We can remove this exclusion if
1050 // we find such a test case. The reason why this is so test-case driven is
1051 // because this entire 'fixup' is only to prevent crashes (from the
1052 // register scavenger) on not-really-valid inputs. For example, if we have:
1054 // %b = bitcast i1* %a to i64*
1055 // store i64* a, i64 b
1056 // then the store should really be marked as 'align 1', but is not. If it
1057 // were marked as 'align 1' then the indexed form would have been
1058 // instruction-selected initially, and the problem this 'fixup' is preventing
1059 // won't happen regardless.
1063 MachineFunction &MF = DAG.getMachineFunction();
1064 MachineFrameInfo *MFI = MF.getFrameInfo();
1066 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1070 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1071 FuncInfo->setHasNonRISpills();
1074 /// Returns true if the address N can be represented by a base register plus
1075 /// a signed 16-bit displacement [r+imm], and if it is not better
1076 /// represented as reg+reg. If Aligned is true, only accept displacements
1077 /// suitable for STD and friends, i.e. multiples of 4.
1078 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1081 bool Aligned) const {
1082 // FIXME dl should come from parent load or store, not from address
1084 // If this can be more profitably realized as r+r, fail.
1085 if (SelectAddressRegReg(N, Disp, Base, DAG))
1088 if (N.getOpcode() == ISD::ADD) {
1090 if (isIntS16Immediate(N.getOperand(1), imm) &&
1091 (!Aligned || (imm & 3) == 0)) {
1092 Disp = DAG.getTargetConstant(imm, N.getValueType());
1093 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1094 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1095 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1097 Base = N.getOperand(0);
1099 return true; // [r+i]
1100 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1101 // Match LOAD (ADD (X, Lo(G))).
1102 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1103 && "Cannot handle constant offsets yet!");
1104 Disp = N.getOperand(1).getOperand(0); // The global address.
1105 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1106 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1107 Disp.getOpcode() == ISD::TargetConstantPool ||
1108 Disp.getOpcode() == ISD::TargetJumpTable);
1109 Base = N.getOperand(0);
1110 return true; // [&g+r]
1112 } else if (N.getOpcode() == ISD::OR) {
1114 if (isIntS16Immediate(N.getOperand(1), imm) &&
1115 (!Aligned || (imm & 3) == 0)) {
1116 // If this is an or of disjoint bitfields, we can codegen this as an add
1117 // (for better address arithmetic) if the LHS and RHS of the OR are
1118 // provably disjoint.
1119 APInt LHSKnownZero, LHSKnownOne;
1120 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1122 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1123 // If all of the bits are known zero on the LHS or RHS, the add won't
1125 Base = N.getOperand(0);
1126 Disp = DAG.getTargetConstant(imm, N.getValueType());
1130 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1131 // Loading from a constant address.
1133 // If this address fits entirely in a 16-bit sext immediate field, codegen
1136 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1137 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1138 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1139 CN->getValueType(0));
1143 // Handle 32-bit sext immediates with LIS + addr mode.
1144 if ((CN->getValueType(0) == MVT::i32 ||
1145 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1146 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1147 int Addr = (int)CN->getZExtValue();
1149 // Otherwise, break this down into an LIS + disp.
1150 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1152 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1153 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1154 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1159 Disp = DAG.getTargetConstant(0, getPointerTy());
1160 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1161 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1162 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1165 return true; // [r+0]
1168 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1169 /// represented as an indexed [r+r] operation.
1170 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1172 SelectionDAG &DAG) const {
1173 // Check to see if we can easily represent this as an [r+r] address. This
1174 // will fail if it thinks that the address is more profitably represented as
1175 // reg+imm, e.g. where imm = 0.
1176 if (SelectAddressRegReg(N, Base, Index, DAG))
1179 // If the operand is an addition, always emit this as [r+r], since this is
1180 // better (for code size, and execution, as the memop does the add for free)
1181 // than emitting an explicit add.
1182 if (N.getOpcode() == ISD::ADD) {
1183 Base = N.getOperand(0);
1184 Index = N.getOperand(1);
1188 // Otherwise, do it the hard way, using R0 as the base register.
1189 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1195 /// getPreIndexedAddressParts - returns true by value, base pointer and
1196 /// offset pointer and addressing mode by reference if the node's address
1197 /// can be legally represented as pre-indexed load / store address.
1198 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1200 ISD::MemIndexedMode &AM,
1201 SelectionDAG &DAG) const {
1202 if (DisablePPCPreinc) return false;
1208 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1209 Ptr = LD->getBasePtr();
1210 VT = LD->getMemoryVT();
1211 Alignment = LD->getAlignment();
1212 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1213 Ptr = ST->getBasePtr();
1214 VT = ST->getMemoryVT();
1215 Alignment = ST->getAlignment();
1220 // PowerPC doesn't have preinc load/store instructions for vectors.
1224 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1226 // Common code will reject creating a pre-inc form if the base pointer
1227 // is a frame index, or if N is a store and the base pointer is either
1228 // the same as or a predecessor of the value being stored. Check for
1229 // those situations here, and try with swapped Base/Offset instead.
1232 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1235 SDValue Val = cast<StoreSDNode>(N)->getValue();
1236 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1241 std::swap(Base, Offset);
1247 // LDU/STU can only handle immediates that are a multiple of 4.
1248 if (VT != MVT::i64) {
1249 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1252 // LDU/STU need an address with at least 4-byte alignment.
1256 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1260 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1261 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1262 // sext i32 to i64 when addr mode is r+i.
1263 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1264 LD->getExtensionType() == ISD::SEXTLOAD &&
1265 isa<ConstantSDNode>(Offset))
1273 //===----------------------------------------------------------------------===//
1274 // LowerOperation implementation
1275 //===----------------------------------------------------------------------===//
1277 /// GetLabelAccessInfo - Return true if we should reference labels using a
1278 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1279 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1280 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1281 HiOpFlags = PPCII::MO_HA;
1282 LoOpFlags = PPCII::MO_LO;
1284 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1285 // non-darwin platform. We don't support PIC on other platforms yet.
1286 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1287 TM.getSubtarget<PPCSubtarget>().isDarwin();
1289 HiOpFlags |= PPCII::MO_PIC_FLAG;
1290 LoOpFlags |= PPCII::MO_PIC_FLAG;
1293 // If this is a reference to a global value that requires a non-lazy-ptr, make
1294 // sure that instruction lowering adds it.
1295 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1296 HiOpFlags |= PPCII::MO_NLP_FLAG;
1297 LoOpFlags |= PPCII::MO_NLP_FLAG;
1299 if (GV->hasHiddenVisibility()) {
1300 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1301 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1308 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1309 SelectionDAG &DAG) {
1310 EVT PtrVT = HiPart.getValueType();
1311 SDValue Zero = DAG.getConstant(0, PtrVT);
1314 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1315 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1317 // With PIC, the first instruction is actually "GR+hi(&G)".
1319 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1320 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1322 // Generate non-pic code that has direct accesses to the constant pool.
1323 // The address of the global is just (hi(&g)+lo(&g)).
1324 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1327 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1328 SelectionDAG &DAG) const {
1329 EVT PtrVT = Op.getValueType();
1330 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1331 const Constant *C = CP->getConstVal();
1333 // 64-bit SVR4 ABI code is always position-independent.
1334 // The actual address of the GlobalValue is stored in the TOC.
1335 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1336 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1337 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1338 DAG.getRegister(PPC::X2, MVT::i64));
1341 unsigned MOHiFlag, MOLoFlag;
1342 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1344 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1346 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1347 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1350 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1351 EVT PtrVT = Op.getValueType();
1352 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1354 // 64-bit SVR4 ABI code is always position-independent.
1355 // The actual address of the GlobalValue is stored in the TOC.
1356 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1357 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1358 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1359 DAG.getRegister(PPC::X2, MVT::i64));
1362 unsigned MOHiFlag, MOLoFlag;
1363 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1364 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1365 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1366 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1369 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1370 SelectionDAG &DAG) const {
1371 EVT PtrVT = Op.getValueType();
1373 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1375 unsigned MOHiFlag, MOLoFlag;
1376 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1377 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1378 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1379 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1382 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1383 SelectionDAG &DAG) const {
1385 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1387 const GlobalValue *GV = GA->getGlobal();
1388 EVT PtrVT = getPointerTy();
1389 bool is64bit = PPCSubTarget.isPPC64();
1391 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1393 if (Model == TLSModel::LocalExec) {
1394 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1395 PPCII::MO_TPREL_HA);
1396 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1397 PPCII::MO_TPREL_LO);
1398 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1399 is64bit ? MVT::i64 : MVT::i32);
1400 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1401 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1405 llvm_unreachable("only local-exec is currently supported for ppc32");
1407 if (Model == TLSModel::InitialExec) {
1408 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1409 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1411 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1412 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1413 PtrVT, GOTReg, TGA);
1414 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1415 PtrVT, TGA, TPOffsetHi);
1416 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1419 if (Model == TLSModel::GeneralDynamic) {
1420 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1421 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1422 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1424 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1427 // We need a chain node, and don't have one handy. The underlying
1428 // call has no side effects, so using the function entry node
1430 SDValue Chain = DAG.getEntryNode();
1431 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1432 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1433 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1434 PtrVT, ParmReg, TGA);
1435 // The return value from GET_TLS_ADDR really is in X3 already, but
1436 // some hacks are needed here to tie everything together. The extra
1437 // copies dissolve during subsequent transforms.
1438 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1439 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1442 if (Model == TLSModel::LocalDynamic) {
1443 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1444 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1445 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1447 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1450 // We need a chain node, and don't have one handy. The underlying
1451 // call has no side effects, so using the function entry node
1453 SDValue Chain = DAG.getEntryNode();
1454 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1455 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1456 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1457 PtrVT, ParmReg, TGA);
1458 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1459 // some hacks are needed here to tie everything together. The extra
1460 // copies dissolve during subsequent transforms.
1461 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1462 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1463 Chain, ParmReg, TGA);
1464 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1467 llvm_unreachable("Unknown TLS model!");
1470 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1471 SelectionDAG &DAG) const {
1472 EVT PtrVT = Op.getValueType();
1473 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1475 const GlobalValue *GV = GSDN->getGlobal();
1477 // 64-bit SVR4 ABI code is always position-independent.
1478 // The actual address of the GlobalValue is stored in the TOC.
1479 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1480 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1481 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1482 DAG.getRegister(PPC::X2, MVT::i64));
1485 unsigned MOHiFlag, MOLoFlag;
1486 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1489 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1491 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1493 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1495 // If the global reference is actually to a non-lazy-pointer, we have to do an
1496 // extra load to get the address of the global.
1497 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1498 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1499 false, false, false, 0);
1503 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1504 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1507 // If we're comparing for equality to zero, expose the fact that this is
1508 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1509 // fold the new nodes.
1510 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1511 if (C->isNullValue() && CC == ISD::SETEQ) {
1512 EVT VT = Op.getOperand(0).getValueType();
1513 SDValue Zext = Op.getOperand(0);
1514 if (VT.bitsLT(MVT::i32)) {
1516 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1518 unsigned Log2b = Log2_32(VT.getSizeInBits());
1519 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1520 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1521 DAG.getConstant(Log2b, MVT::i32));
1522 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1524 // Leave comparisons against 0 and -1 alone for now, since they're usually
1525 // optimized. FIXME: revisit this when we can custom lower all setcc
1527 if (C->isAllOnesValue() || C->isNullValue())
1531 // If we have an integer seteq/setne, turn it into a compare against zero
1532 // by xor'ing the rhs with the lhs, which is faster than setting a
1533 // condition register, reading it back out, and masking the correct bit. The
1534 // normal approach here uses sub to do this instead of xor. Using xor exposes
1535 // the result to other bit-twiddling opportunities.
1536 EVT LHSVT = Op.getOperand(0).getValueType();
1537 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1538 EVT VT = Op.getValueType();
1539 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1541 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1546 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1547 const PPCSubtarget &Subtarget) const {
1548 SDNode *Node = Op.getNode();
1549 EVT VT = Node->getValueType(0);
1550 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1551 SDValue InChain = Node->getOperand(0);
1552 SDValue VAListPtr = Node->getOperand(1);
1553 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1556 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1559 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1560 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1562 InChain = GprIndex.getValue(1);
1564 if (VT == MVT::i64) {
1565 // Check if GprIndex is even
1566 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1567 DAG.getConstant(1, MVT::i32));
1568 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1569 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1570 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1571 DAG.getConstant(1, MVT::i32));
1572 // Align GprIndex to be even if it isn't
1573 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1577 // fpr index is 1 byte after gpr
1578 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1579 DAG.getConstant(1, MVT::i32));
1582 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1583 FprPtr, MachinePointerInfo(SV), MVT::i8,
1585 InChain = FprIndex.getValue(1);
1587 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1588 DAG.getConstant(8, MVT::i32));
1590 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1591 DAG.getConstant(4, MVT::i32));
1594 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1595 MachinePointerInfo(), false, false,
1597 InChain = OverflowArea.getValue(1);
1599 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1600 MachinePointerInfo(), false, false,
1602 InChain = RegSaveArea.getValue(1);
1604 // select overflow_area if index > 8
1605 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1606 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1608 // adjustment constant gpr_index * 4/8
1609 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1610 VT.isInteger() ? GprIndex : FprIndex,
1611 DAG.getConstant(VT.isInteger() ? 4 : 8,
1614 // OurReg = RegSaveArea + RegConstant
1615 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1618 // Floating types are 32 bytes into RegSaveArea
1619 if (VT.isFloatingPoint())
1620 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1621 DAG.getConstant(32, MVT::i32));
1623 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1624 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1625 VT.isInteger() ? GprIndex : FprIndex,
1626 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1629 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1630 VT.isInteger() ? VAListPtr : FprPtr,
1631 MachinePointerInfo(SV),
1632 MVT::i8, false, false, 0);
1634 // determine if we should load from reg_save_area or overflow_area
1635 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1637 // increase overflow_area by 4/8 if gpr/fpr > 8
1638 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1639 DAG.getConstant(VT.isInteger() ? 4 : 8,
1642 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1645 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1647 MachinePointerInfo(),
1648 MVT::i32, false, false, 0);
1650 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1651 false, false, false, 0);
1654 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1655 const PPCSubtarget &Subtarget) const {
1656 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1658 // We have to copy the entire va_list struct:
1659 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1660 return DAG.getMemcpy(Op.getOperand(0), Op,
1661 Op.getOperand(1), Op.getOperand(2),
1662 DAG.getConstant(12, MVT::i32), 8, false, true,
1663 MachinePointerInfo(), MachinePointerInfo());
1666 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1667 SelectionDAG &DAG) const {
1668 return Op.getOperand(0);
1671 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1672 SelectionDAG &DAG) const {
1673 SDValue Chain = Op.getOperand(0);
1674 SDValue Trmp = Op.getOperand(1); // trampoline
1675 SDValue FPtr = Op.getOperand(2); // nested function
1676 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1679 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1680 bool isPPC64 = (PtrVT == MVT::i64);
1682 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1685 TargetLowering::ArgListTy Args;
1686 TargetLowering::ArgListEntry Entry;
1688 Entry.Ty = IntPtrTy;
1689 Entry.Node = Trmp; Args.push_back(Entry);
1691 // TrampSize == (isPPC64 ? 48 : 40);
1692 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1693 isPPC64 ? MVT::i64 : MVT::i32);
1694 Args.push_back(Entry);
1696 Entry.Node = FPtr; Args.push_back(Entry);
1697 Entry.Node = Nest; Args.push_back(Entry);
1699 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1700 TargetLowering::CallLoweringInfo CLI(Chain,
1701 Type::getVoidTy(*DAG.getContext()),
1702 false, false, false, false, 0,
1704 /*isTailCall=*/false,
1705 /*doesNotRet=*/false,
1706 /*isReturnValueUsed=*/true,
1707 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1709 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1711 return CallResult.second;
1714 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1715 const PPCSubtarget &Subtarget) const {
1716 MachineFunction &MF = DAG.getMachineFunction();
1717 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1721 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1722 // vastart just stores the address of the VarArgsFrameIndex slot into the
1723 // memory location argument.
1724 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1725 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1726 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1727 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1728 MachinePointerInfo(SV),
1732 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1733 // We suppose the given va_list is already allocated.
1736 // char gpr; /* index into the array of 8 GPRs
1737 // * stored in the register save area
1738 // * gpr=0 corresponds to r3,
1739 // * gpr=1 to r4, etc.
1741 // char fpr; /* index into the array of 8 FPRs
1742 // * stored in the register save area
1743 // * fpr=0 corresponds to f1,
1744 // * fpr=1 to f2, etc.
1746 // char *overflow_arg_area;
1747 // /* location on stack that holds
1748 // * the next overflow argument
1750 // char *reg_save_area;
1751 // /* where r3:r10 and f1:f8 (if saved)
1757 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1758 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1761 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1763 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1765 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1768 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1769 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1771 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1772 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1774 uint64_t FPROffset = 1;
1775 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1777 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1779 // Store first byte : number of int regs
1780 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1782 MachinePointerInfo(SV),
1783 MVT::i8, false, false, 0);
1784 uint64_t nextOffset = FPROffset;
1785 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1788 // Store second byte : number of float regs
1789 SDValue secondStore =
1790 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1791 MachinePointerInfo(SV, nextOffset), MVT::i8,
1793 nextOffset += StackOffset;
1794 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1796 // Store second word : arguments given on stack
1797 SDValue thirdStore =
1798 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1799 MachinePointerInfo(SV, nextOffset),
1801 nextOffset += FrameOffset;
1802 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1804 // Store third word : arguments given in registers
1805 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1806 MachinePointerInfo(SV, nextOffset),
1811 #include "PPCGenCallingConv.inc"
1813 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1814 CCValAssign::LocInfo &LocInfo,
1815 ISD::ArgFlagsTy &ArgFlags,
1820 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1822 CCValAssign::LocInfo &LocInfo,
1823 ISD::ArgFlagsTy &ArgFlags,
1825 static const uint16_t ArgRegs[] = {
1826 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1827 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1829 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1831 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1833 // Skip one register if the first unallocated register has an even register
1834 // number and there are still argument registers available which have not been
1835 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1836 // need to skip a register if RegNum is odd.
1837 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1838 State.AllocateReg(ArgRegs[RegNum]);
1841 // Always return false here, as this function only makes sure that the first
1842 // unallocated register has an odd register number and does not actually
1843 // allocate a register for the current argument.
1847 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1849 CCValAssign::LocInfo &LocInfo,
1850 ISD::ArgFlagsTy &ArgFlags,
1852 static const uint16_t ArgRegs[] = {
1853 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1857 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1859 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1861 // If there is only one Floating-point register left we need to put both f64
1862 // values of a split ppc_fp128 value on the stack.
1863 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1864 State.AllocateReg(ArgRegs[RegNum]);
1867 // Always return false here, as this function only makes sure that the two f64
1868 // values a ppc_fp128 value is split into are both passed in registers or both
1869 // passed on the stack and does not actually allocate a register for the
1870 // current argument.
1874 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1876 static const uint16_t *GetFPR() {
1877 static const uint16_t FPR[] = {
1878 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1879 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1885 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1887 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1888 unsigned PtrByteSize) {
1889 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1890 if (Flags.isByVal())
1891 ArgSize = Flags.getByValSize();
1892 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1898 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1899 CallingConv::ID CallConv, bool isVarArg,
1900 const SmallVectorImpl<ISD::InputArg>
1902 SDLoc dl, SelectionDAG &DAG,
1903 SmallVectorImpl<SDValue> &InVals)
1905 if (PPCSubTarget.isSVR4ABI()) {
1906 if (PPCSubTarget.isPPC64())
1907 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1910 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1913 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1919 PPCTargetLowering::LowerFormalArguments_32SVR4(
1921 CallingConv::ID CallConv, bool isVarArg,
1922 const SmallVectorImpl<ISD::InputArg>
1924 SDLoc dl, SelectionDAG &DAG,
1925 SmallVectorImpl<SDValue> &InVals) const {
1927 // 32-bit SVR4 ABI Stack Frame Layout:
1928 // +-----------------------------------+
1929 // +--> | Back chain |
1930 // | +-----------------------------------+
1931 // | | Floating-point register save area |
1932 // | +-----------------------------------+
1933 // | | General register save area |
1934 // | +-----------------------------------+
1935 // | | CR save word |
1936 // | +-----------------------------------+
1937 // | | VRSAVE save word |
1938 // | +-----------------------------------+
1939 // | | Alignment padding |
1940 // | +-----------------------------------+
1941 // | | Vector register save area |
1942 // | +-----------------------------------+
1943 // | | Local variable space |
1944 // | +-----------------------------------+
1945 // | | Parameter list area |
1946 // | +-----------------------------------+
1947 // | | LR save word |
1948 // | +-----------------------------------+
1949 // SP--> +--- | Back chain |
1950 // +-----------------------------------+
1953 // System V Application Binary Interface PowerPC Processor Supplement
1954 // AltiVec Technology Programming Interface Manual
1956 MachineFunction &MF = DAG.getMachineFunction();
1957 MachineFrameInfo *MFI = MF.getFrameInfo();
1958 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1960 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1961 // Potential tail calls could cause overwriting of argument stack slots.
1962 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1963 (CallConv == CallingConv::Fast));
1964 unsigned PtrByteSize = 4;
1966 // Assign locations to all of the incoming arguments.
1967 SmallVector<CCValAssign, 16> ArgLocs;
1968 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1969 getTargetMachine(), ArgLocs, *DAG.getContext());
1971 // Reserve space for the linkage area on the stack.
1972 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1974 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1976 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1977 CCValAssign &VA = ArgLocs[i];
1979 // Arguments stored in registers.
1980 if (VA.isRegLoc()) {
1981 const TargetRegisterClass *RC;
1982 EVT ValVT = VA.getValVT();
1984 switch (ValVT.getSimpleVT().SimpleTy) {
1986 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1988 RC = &PPC::GPRCRegClass;
1991 RC = &PPC::F4RCRegClass;
1994 RC = &PPC::F8RCRegClass;
2000 RC = &PPC::VRRCRegClass;
2004 // Transform the arguments stored in physical registers into virtual ones.
2005 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2006 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2008 InVals.push_back(ArgValue);
2010 // Argument stored in memory.
2011 assert(VA.isMemLoc());
2013 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2014 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2017 // Create load nodes to retrieve arguments from the stack.
2018 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2019 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2020 MachinePointerInfo(),
2021 false, false, false, 0));
2025 // Assign locations to all of the incoming aggregate by value arguments.
2026 // Aggregates passed by value are stored in the local variable space of the
2027 // caller's stack frame, right above the parameter list area.
2028 SmallVector<CCValAssign, 16> ByValArgLocs;
2029 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2030 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2032 // Reserve stack space for the allocations in CCInfo.
2033 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2035 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2037 // Area that is at least reserved in the caller of this function.
2038 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2040 // Set the size that is at least reserved in caller of this function. Tail
2041 // call optimized function's reserved stack space needs to be aligned so that
2042 // taking the difference between two stack areas will result in an aligned
2044 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2047 std::max(MinReservedArea,
2048 PPCFrameLowering::getMinCallFrameSize(false, false));
2050 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2051 getStackAlignment();
2052 unsigned AlignMask = TargetAlign-1;
2053 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2055 FI->setMinReservedArea(MinReservedArea);
2057 SmallVector<SDValue, 8> MemOps;
2059 // If the function takes variable number of arguments, make a frame index for
2060 // the start of the first vararg value... for expansion of llvm.va_start.
2062 static const uint16_t GPArgRegs[] = {
2063 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2064 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2066 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2068 static const uint16_t FPArgRegs[] = {
2069 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2072 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2074 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2076 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2079 // Make room for NumGPArgRegs and NumFPArgRegs.
2080 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2081 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2083 FuncInfo->setVarArgsStackOffset(
2084 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2085 CCInfo.getNextStackOffset(), true));
2087 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2088 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2090 // The fixed integer arguments of a variadic function are stored to the
2091 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2092 // the result of va_next.
2093 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2094 // Get an existing live-in vreg, or add a new one.
2095 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2097 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2099 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2100 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2101 MachinePointerInfo(), false, false, 0);
2102 MemOps.push_back(Store);
2103 // Increment the address by four for the next argument to store
2104 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2105 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2108 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2110 // The double arguments are stored to the VarArgsFrameIndex
2112 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2113 // Get an existing live-in vreg, or add a new one.
2114 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2116 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2118 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2119 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2120 MachinePointerInfo(), false, false, 0);
2121 MemOps.push_back(Store);
2122 // Increment the address by eight for the next argument to store
2123 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2125 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2129 if (!MemOps.empty())
2130 Chain = DAG.getNode(ISD::TokenFactor, dl,
2131 MVT::Other, &MemOps[0], MemOps.size());
2136 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2137 // value to MVT::i64 and then truncate to the correct register size.
2139 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2140 SelectionDAG &DAG, SDValue ArgVal,
2143 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2144 DAG.getValueType(ObjectVT));
2145 else if (Flags.isZExt())
2146 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2147 DAG.getValueType(ObjectVT));
2149 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2152 // Set the size that is at least reserved in caller of this function. Tail
2153 // call optimized functions' reserved stack space needs to be aligned so that
2154 // taking the difference between two stack areas will result in an aligned
2157 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2158 unsigned nAltivecParamsAtEnd,
2159 unsigned MinReservedArea,
2160 bool isPPC64) const {
2161 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2162 // Add the Altivec parameters at the end, if needed.
2163 if (nAltivecParamsAtEnd) {
2164 MinReservedArea = ((MinReservedArea+15)/16)*16;
2165 MinReservedArea += 16*nAltivecParamsAtEnd;
2168 std::max(MinReservedArea,
2169 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2170 unsigned TargetAlign
2171 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2172 getStackAlignment();
2173 unsigned AlignMask = TargetAlign-1;
2174 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2175 FI->setMinReservedArea(MinReservedArea);
2179 PPCTargetLowering::LowerFormalArguments_64SVR4(
2181 CallingConv::ID CallConv, bool isVarArg,
2182 const SmallVectorImpl<ISD::InputArg>
2184 SDLoc dl, SelectionDAG &DAG,
2185 SmallVectorImpl<SDValue> &InVals) const {
2186 // TODO: add description of PPC stack frame format, or at least some docs.
2188 MachineFunction &MF = DAG.getMachineFunction();
2189 MachineFrameInfo *MFI = MF.getFrameInfo();
2190 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2192 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2193 // Potential tail calls could cause overwriting of argument stack slots.
2194 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2195 (CallConv == CallingConv::Fast));
2196 unsigned PtrByteSize = 8;
2198 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2199 // Area that is at least reserved in caller of this function.
2200 unsigned MinReservedArea = ArgOffset;
2202 static const uint16_t GPR[] = {
2203 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2204 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2207 static const uint16_t *FPR = GetFPR();
2209 static const uint16_t VR[] = {
2210 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2211 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2214 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2215 const unsigned Num_FPR_Regs = 13;
2216 const unsigned Num_VR_Regs = array_lengthof(VR);
2218 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2220 // Add DAG nodes to load the arguments or copy them out of registers. On
2221 // entry to a function on PPC, the arguments start after the linkage area,
2222 // although the first ones are often in registers.
2224 SmallVector<SDValue, 8> MemOps;
2225 unsigned nAltivecParamsAtEnd = 0;
2226 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2227 unsigned CurArgIdx = 0;
2228 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2230 bool needsLoad = false;
2231 EVT ObjectVT = Ins[ArgNo].VT;
2232 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2233 unsigned ArgSize = ObjSize;
2234 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2235 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2236 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2238 unsigned CurArgOffset = ArgOffset;
2240 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2241 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2242 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2244 MinReservedArea = ((MinReservedArea+15)/16)*16;
2245 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2249 nAltivecParamsAtEnd++;
2251 // Calculate min reserved area.
2252 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2256 // FIXME the codegen can be much improved in some cases.
2257 // We do not have to keep everything in memory.
2258 if (Flags.isByVal()) {
2259 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2260 ObjSize = Flags.getByValSize();
2261 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2262 // Empty aggregate parameters do not take up registers. Examples:
2266 // etc. However, we have to provide a place-holder in InVals, so
2267 // pretend we have an 8-byte item at the current address for that
2270 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2271 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2272 InVals.push_back(FIN);
2275 // All aggregates smaller than 8 bytes must be passed right-justified.
2276 if (ObjSize < PtrByteSize)
2277 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2278 // The value of the object is its address.
2279 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2280 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2281 InVals.push_back(FIN);
2284 if (GPR_idx != Num_GPR_Regs) {
2285 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2286 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2289 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2290 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2291 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2292 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2293 MachinePointerInfo(FuncArg, CurArgOffset),
2294 ObjType, false, false, 0);
2296 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2297 // store the whole register as-is to the parameter save area
2298 // slot. The address of the parameter was already calculated
2299 // above (InVals.push_back(FIN)) to be the right-justified
2300 // offset within the slot. For this store, we need a new
2301 // frame index that points at the beginning of the slot.
2302 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2303 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2304 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2305 MachinePointerInfo(FuncArg, ArgOffset),
2309 MemOps.push_back(Store);
2312 // Whether we copied from a register or not, advance the offset
2313 // into the parameter save area by a full doubleword.
2314 ArgOffset += PtrByteSize;
2318 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2319 // Store whatever pieces of the object are in registers
2320 // to memory. ArgOffset will be the address of the beginning
2322 if (GPR_idx != Num_GPR_Regs) {
2324 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2325 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2326 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2327 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2328 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2329 MachinePointerInfo(FuncArg, ArgOffset),
2331 MemOps.push_back(Store);
2333 ArgOffset += PtrByteSize;
2335 ArgOffset += ArgSize - j;
2342 switch (ObjectVT.getSimpleVT().SimpleTy) {
2343 default: llvm_unreachable("Unhandled argument type!");
2346 if (GPR_idx != Num_GPR_Regs) {
2347 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2348 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2350 if (ObjectVT == MVT::i32)
2351 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2352 // value to MVT::i64 and then truncate to the correct register size.
2353 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2358 ArgSize = PtrByteSize;
2365 // Every 8 bytes of argument space consumes one of the GPRs available for
2366 // argument passing.
2367 if (GPR_idx != Num_GPR_Regs) {
2370 if (FPR_idx != Num_FPR_Regs) {
2373 if (ObjectVT == MVT::f32)
2374 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2376 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2378 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2382 ArgSize = PtrByteSize;
2391 // Note that vector arguments in registers don't reserve stack space,
2392 // except in varargs functions.
2393 if (VR_idx != Num_VR_Regs) {
2394 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2395 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2397 while ((ArgOffset % 16) != 0) {
2398 ArgOffset += PtrByteSize;
2399 if (GPR_idx != Num_GPR_Regs)
2403 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2407 // Vectors are aligned.
2408 ArgOffset = ((ArgOffset+15)/16)*16;
2409 CurArgOffset = ArgOffset;
2416 // We need to load the argument to a virtual register if we determined
2417 // above that we ran out of physical registers of the appropriate type.
2419 int FI = MFI->CreateFixedObject(ObjSize,
2420 CurArgOffset + (ArgSize - ObjSize),
2422 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2423 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2424 false, false, false, 0);
2427 InVals.push_back(ArgVal);
2430 // Set the size that is at least reserved in caller of this function. Tail
2431 // call optimized functions' reserved stack space needs to be aligned so that
2432 // taking the difference between two stack areas will result in an aligned
2434 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2436 // If the function takes variable number of arguments, make a frame index for
2437 // the start of the first vararg value... for expansion of llvm.va_start.
2439 int Depth = ArgOffset;
2441 FuncInfo->setVarArgsFrameIndex(
2442 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2443 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2445 // If this function is vararg, store any remaining integer argument regs
2446 // to their spots on the stack so that they may be loaded by deferencing the
2447 // result of va_next.
2448 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2449 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2450 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2451 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2452 MachinePointerInfo(), false, false, 0);
2453 MemOps.push_back(Store);
2454 // Increment the address by four for the next argument to store
2455 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2456 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2460 if (!MemOps.empty())
2461 Chain = DAG.getNode(ISD::TokenFactor, dl,
2462 MVT::Other, &MemOps[0], MemOps.size());
2468 PPCTargetLowering::LowerFormalArguments_Darwin(
2470 CallingConv::ID CallConv, bool isVarArg,
2471 const SmallVectorImpl<ISD::InputArg>
2473 SDLoc dl, SelectionDAG &DAG,
2474 SmallVectorImpl<SDValue> &InVals) const {
2475 // TODO: add description of PPC stack frame format, or at least some docs.
2477 MachineFunction &MF = DAG.getMachineFunction();
2478 MachineFrameInfo *MFI = MF.getFrameInfo();
2479 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2481 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2482 bool isPPC64 = PtrVT == MVT::i64;
2483 // Potential tail calls could cause overwriting of argument stack slots.
2484 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2485 (CallConv == CallingConv::Fast));
2486 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2488 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2489 // Area that is at least reserved in caller of this function.
2490 unsigned MinReservedArea = ArgOffset;
2492 static const uint16_t GPR_32[] = { // 32-bit registers.
2493 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2494 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2496 static const uint16_t GPR_64[] = { // 64-bit registers.
2497 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2498 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2501 static const uint16_t *FPR = GetFPR();
2503 static const uint16_t VR[] = {
2504 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2505 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2508 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2509 const unsigned Num_FPR_Regs = 13;
2510 const unsigned Num_VR_Regs = array_lengthof( VR);
2512 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2514 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2516 // In 32-bit non-varargs functions, the stack space for vectors is after the
2517 // stack space for non-vectors. We do not use this space unless we have
2518 // too many vectors to fit in registers, something that only occurs in
2519 // constructed examples:), but we have to walk the arglist to figure
2520 // that out...for the pathological case, compute VecArgOffset as the
2521 // start of the vector parameter area. Computing VecArgOffset is the
2522 // entire point of the following loop.
2523 unsigned VecArgOffset = ArgOffset;
2524 if (!isVarArg && !isPPC64) {
2525 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2527 EVT ObjectVT = Ins[ArgNo].VT;
2528 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2530 if (Flags.isByVal()) {
2531 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2532 unsigned ObjSize = Flags.getByValSize();
2534 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2535 VecArgOffset += ArgSize;
2539 switch(ObjectVT.getSimpleVT().SimpleTy) {
2540 default: llvm_unreachable("Unhandled argument type!");
2545 case MVT::i64: // PPC64
2547 // FIXME: We are guaranteed to be !isPPC64 at this point.
2548 // Does MVT::i64 apply?
2555 // Nothing to do, we're only looking at Nonvector args here.
2560 // We've found where the vector parameter area in memory is. Skip the
2561 // first 12 parameters; these don't use that memory.
2562 VecArgOffset = ((VecArgOffset+15)/16)*16;
2563 VecArgOffset += 12*16;
2565 // Add DAG nodes to load the arguments or copy them out of registers. On
2566 // entry to a function on PPC, the arguments start after the linkage area,
2567 // although the first ones are often in registers.
2569 SmallVector<SDValue, 8> MemOps;
2570 unsigned nAltivecParamsAtEnd = 0;
2571 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2572 unsigned CurArgIdx = 0;
2573 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2575 bool needsLoad = false;
2576 EVT ObjectVT = Ins[ArgNo].VT;
2577 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2578 unsigned ArgSize = ObjSize;
2579 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2580 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2581 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2583 unsigned CurArgOffset = ArgOffset;
2585 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2586 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2587 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2588 if (isVarArg || isPPC64) {
2589 MinReservedArea = ((MinReservedArea+15)/16)*16;
2590 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2593 } else nAltivecParamsAtEnd++;
2595 // Calculate min reserved area.
2596 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2600 // FIXME the codegen can be much improved in some cases.
2601 // We do not have to keep everything in memory.
2602 if (Flags.isByVal()) {
2603 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2604 ObjSize = Flags.getByValSize();
2605 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2606 // Objects of size 1 and 2 are right justified, everything else is
2607 // left justified. This means the memory address is adjusted forwards.
2608 if (ObjSize==1 || ObjSize==2) {
2609 CurArgOffset = CurArgOffset + (4 - ObjSize);
2611 // The value of the object is its address.
2612 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2613 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2614 InVals.push_back(FIN);
2615 if (ObjSize==1 || ObjSize==2) {
2616 if (GPR_idx != Num_GPR_Regs) {
2619 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2621 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2622 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2623 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2624 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2625 MachinePointerInfo(FuncArg,
2627 ObjType, false, false, 0);
2628 MemOps.push_back(Store);
2632 ArgOffset += PtrByteSize;
2636 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2637 // Store whatever pieces of the object are in registers
2638 // to memory. ArgOffset will be the address of the beginning
2640 if (GPR_idx != Num_GPR_Regs) {
2643 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2645 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2646 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2647 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2648 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2649 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2650 MachinePointerInfo(FuncArg, ArgOffset),
2652 MemOps.push_back(Store);
2654 ArgOffset += PtrByteSize;
2656 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2663 switch (ObjectVT.getSimpleVT().SimpleTy) {
2664 default: llvm_unreachable("Unhandled argument type!");
2667 if (GPR_idx != Num_GPR_Regs) {
2668 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2669 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2673 ArgSize = PtrByteSize;
2675 // All int arguments reserve stack space in the Darwin ABI.
2676 ArgOffset += PtrByteSize;
2680 case MVT::i64: // PPC64
2681 if (GPR_idx != Num_GPR_Regs) {
2682 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2683 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2685 if (ObjectVT == MVT::i32)
2686 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2687 // value to MVT::i64 and then truncate to the correct register size.
2688 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2693 ArgSize = PtrByteSize;
2695 // All int arguments reserve stack space in the Darwin ABI.
2701 // Every 4 bytes of argument space consumes one of the GPRs available for
2702 // argument passing.
2703 if (GPR_idx != Num_GPR_Regs) {
2705 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2708 if (FPR_idx != Num_FPR_Regs) {
2711 if (ObjectVT == MVT::f32)
2712 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2714 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2716 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2722 // All FP arguments reserve stack space in the Darwin ABI.
2723 ArgOffset += isPPC64 ? 8 : ObjSize;
2729 // Note that vector arguments in registers don't reserve stack space,
2730 // except in varargs functions.
2731 if (VR_idx != Num_VR_Regs) {
2732 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2733 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2735 while ((ArgOffset % 16) != 0) {
2736 ArgOffset += PtrByteSize;
2737 if (GPR_idx != Num_GPR_Regs)
2741 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2745 if (!isVarArg && !isPPC64) {
2746 // Vectors go after all the nonvectors.
2747 CurArgOffset = VecArgOffset;
2750 // Vectors are aligned.
2751 ArgOffset = ((ArgOffset+15)/16)*16;
2752 CurArgOffset = ArgOffset;
2760 // We need to load the argument to a virtual register if we determined above
2761 // that we ran out of physical registers of the appropriate type.
2763 int FI = MFI->CreateFixedObject(ObjSize,
2764 CurArgOffset + (ArgSize - ObjSize),
2766 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2767 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2768 false, false, false, 0);
2771 InVals.push_back(ArgVal);
2774 // Set the size that is at least reserved in caller of this function. Tail
2775 // call optimized functions' reserved stack space needs to be aligned so that
2776 // taking the difference between two stack areas will result in an aligned
2778 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2780 // If the function takes variable number of arguments, make a frame index for
2781 // the start of the first vararg value... for expansion of llvm.va_start.
2783 int Depth = ArgOffset;
2785 FuncInfo->setVarArgsFrameIndex(
2786 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2788 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2790 // If this function is vararg, store any remaining integer argument regs
2791 // to their spots on the stack so that they may be loaded by deferencing the
2792 // result of va_next.
2793 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2797 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2799 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2801 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2802 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2803 MachinePointerInfo(), false, false, 0);
2804 MemOps.push_back(Store);
2805 // Increment the address by four for the next argument to store
2806 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2807 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2811 if (!MemOps.empty())
2812 Chain = DAG.getNode(ISD::TokenFactor, dl,
2813 MVT::Other, &MemOps[0], MemOps.size());
2818 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2819 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2821 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2825 const SmallVectorImpl<ISD::OutputArg>
2827 const SmallVectorImpl<SDValue> &OutVals,
2828 unsigned &nAltivecParamsAtEnd) {
2829 // Count how many bytes are to be pushed on the stack, including the linkage
2830 // area, and parameter passing area. We start with 24/48 bytes, which is
2831 // prereserved space for [SP][CR][LR][3 x unused].
2832 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2833 unsigned NumOps = Outs.size();
2834 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2836 // Add up all the space actually used.
2837 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2838 // they all go in registers, but we must reserve stack space for them for
2839 // possible use by the caller. In varargs or 64-bit calls, parameters are
2840 // assigned stack space in order, with padding so Altivec parameters are
2842 nAltivecParamsAtEnd = 0;
2843 for (unsigned i = 0; i != NumOps; ++i) {
2844 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2845 EVT ArgVT = Outs[i].VT;
2846 // Varargs Altivec parameters are padded to a 16 byte boundary.
2847 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2848 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2849 if (!isVarArg && !isPPC64) {
2850 // Non-varargs Altivec parameters go after all the non-Altivec
2851 // parameters; handle those later so we know how much padding we need.
2852 nAltivecParamsAtEnd++;
2855 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2856 NumBytes = ((NumBytes+15)/16)*16;
2858 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2861 // Allow for Altivec parameters at the end, if needed.
2862 if (nAltivecParamsAtEnd) {
2863 NumBytes = ((NumBytes+15)/16)*16;
2864 NumBytes += 16*nAltivecParamsAtEnd;
2867 // The prolog code of the callee may store up to 8 GPR argument registers to
2868 // the stack, allowing va_start to index over them in memory if its varargs.
2869 // Because we cannot tell if this is needed on the caller side, we have to
2870 // conservatively assume that it is needed. As such, make sure we have at
2871 // least enough stack space for the caller to store the 8 GPRs.
2872 NumBytes = std::max(NumBytes,
2873 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2875 // Tail call needs the stack to be aligned.
2876 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2877 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2878 getFrameLowering()->getStackAlignment();
2879 unsigned AlignMask = TargetAlign-1;
2880 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2886 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2887 /// adjusted to accommodate the arguments for the tailcall.
2888 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2889 unsigned ParamSize) {
2891 if (!isTailCall) return 0;
2893 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2894 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2895 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2896 // Remember only if the new adjustement is bigger.
2897 if (SPDiff < FI->getTailCallSPDelta())
2898 FI->setTailCallSPDelta(SPDiff);
2903 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2904 /// for tail call optimization. Targets which want to do tail call
2905 /// optimization should implement this function.
2907 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2908 CallingConv::ID CalleeCC,
2910 const SmallVectorImpl<ISD::InputArg> &Ins,
2911 SelectionDAG& DAG) const {
2912 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2915 // Variable argument functions are not supported.
2919 MachineFunction &MF = DAG.getMachineFunction();
2920 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2921 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2922 // Functions containing by val parameters are not supported.
2923 for (unsigned i = 0; i != Ins.size(); i++) {
2924 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2925 if (Flags.isByVal()) return false;
2928 // Non PIC/GOT tail calls are supported.
2929 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2932 // At the moment we can only do local tail calls (in same module, hidden
2933 // or protected) if we are generating PIC.
2934 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2935 return G->getGlobal()->hasHiddenVisibility()
2936 || G->getGlobal()->hasProtectedVisibility();
2942 /// isCallCompatibleAddress - Return the immediate to use if the specified
2943 /// 32-bit value is representable in the immediate field of a BxA instruction.
2944 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2945 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2948 int Addr = C->getZExtValue();
2949 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2950 SignExtend32<26>(Addr) != Addr)
2951 return 0; // Top 6 bits have to be sext of immediate.
2953 return DAG.getConstant((int)C->getZExtValue() >> 2,
2954 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2959 struct TailCallArgumentInfo {
2964 TailCallArgumentInfo() : FrameIdx(0) {}
2969 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2971 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2973 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
2974 SmallVectorImpl<SDValue> &MemOpChains,
2976 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2977 SDValue Arg = TailCallArgs[i].Arg;
2978 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2979 int FI = TailCallArgs[i].FrameIdx;
2980 // Store relative to framepointer.
2981 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2982 MachinePointerInfo::getFixedStack(FI),
2987 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2988 /// the appropriate stack slot for the tail call optimized function call.
2989 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2990 MachineFunction &MF,
2999 // Calculate the new stack slot for the return address.
3000 int SlotSize = isPPC64 ? 8 : 4;
3001 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3003 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3004 NewRetAddrLoc, true);
3005 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3006 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3007 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3008 MachinePointerInfo::getFixedStack(NewRetAddr),
3011 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3012 // slot as the FP is never overwritten.
3015 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3016 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3018 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3019 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3020 MachinePointerInfo::getFixedStack(NewFPIdx),
3027 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3028 /// the position of the argument.
3030 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3031 SDValue Arg, int SPDiff, unsigned ArgOffset,
3032 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3033 int Offset = ArgOffset + SPDiff;
3034 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3035 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3036 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3037 SDValue FIN = DAG.getFrameIndex(FI, VT);
3038 TailCallArgumentInfo Info;
3040 Info.FrameIdxOp = FIN;
3042 TailCallArguments.push_back(Info);
3045 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3046 /// stack slot. Returns the chain as result and the loaded frame pointers in
3047 /// LROpOut/FPOpout. Used when tail calling.
3048 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3056 // Load the LR and FP stack slot for later adjusting.
3057 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3058 LROpOut = getReturnAddrFrameIndex(DAG);
3059 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3060 false, false, false, 0);
3061 Chain = SDValue(LROpOut.getNode(), 1);
3063 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3064 // slot as the FP is never overwritten.
3066 FPOpOut = getFramePointerFrameIndex(DAG);
3067 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3068 false, false, false, 0);
3069 Chain = SDValue(FPOpOut.getNode(), 1);
3075 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3076 /// by "Src" to address "Dst" of size "Size". Alignment information is
3077 /// specified by the specific parameter attribute. The copy will be passed as
3078 /// a byval function parameter.
3079 /// Sometimes what we are copying is the end of a larger object, the part that
3080 /// does not fit in registers.
3082 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3083 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3085 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3086 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3087 false, false, MachinePointerInfo(0),
3088 MachinePointerInfo(0));
3091 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3094 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3095 SDValue Arg, SDValue PtrOff, int SPDiff,
3096 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3097 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3098 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3100 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3105 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3107 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3108 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3109 DAG.getConstant(ArgOffset, PtrVT));
3111 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3112 MachinePointerInfo(), false, false, 0));
3113 // Calculate and remember argument location.
3114 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3119 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3120 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3121 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3122 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3123 MachineFunction &MF = DAG.getMachineFunction();
3125 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3126 // might overwrite each other in case of tail call optimization.
3127 SmallVector<SDValue, 8> MemOpChains2;
3128 // Do not flag preceding copytoreg stuff together with the following stuff.
3130 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3132 if (!MemOpChains2.empty())
3133 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3134 &MemOpChains2[0], MemOpChains2.size());
3136 // Store the return address to the appropriate stack slot.
3137 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3138 isPPC64, isDarwinABI, dl);
3140 // Emit callseq_end just before tailcall node.
3141 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3142 DAG.getIntPtrConstant(0, true), InFlag, dl);
3143 InFlag = Chain.getValue(1);
3147 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3148 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3149 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3150 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3151 const PPCSubtarget &PPCSubTarget) {
3153 bool isPPC64 = PPCSubTarget.isPPC64();
3154 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3156 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3157 NodeTys.push_back(MVT::Other); // Returns a chain
3158 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3160 unsigned CallOpc = PPCISD::CALL;
3162 bool needIndirectCall = true;
3163 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3164 // If this is an absolute destination address, use the munged value.
3165 Callee = SDValue(Dest, 0);
3166 needIndirectCall = false;
3169 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3170 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3171 // Use indirect calls for ALL functions calls in JIT mode, since the
3172 // far-call stubs may be outside relocation limits for a BL instruction.
3173 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3174 unsigned OpFlags = 0;
3175 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3176 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3177 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3178 (G->getGlobal()->isDeclaration() ||
3179 G->getGlobal()->isWeakForLinker())) {
3180 // PC-relative references to external symbols should go through $stub,
3181 // unless we're building with the leopard linker or later, which
3182 // automatically synthesizes these stubs.
3183 OpFlags = PPCII::MO_DARWIN_STUB;
3186 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3187 // every direct call is) turn it into a TargetGlobalAddress /
3188 // TargetExternalSymbol node so that legalize doesn't hack it.
3189 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3190 Callee.getValueType(),
3192 needIndirectCall = false;
3196 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3197 unsigned char OpFlags = 0;
3199 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3200 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3201 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3202 // PC-relative references to external symbols should go through $stub,
3203 // unless we're building with the leopard linker or later, which
3204 // automatically synthesizes these stubs.
3205 OpFlags = PPCII::MO_DARWIN_STUB;
3208 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3210 needIndirectCall = false;
3213 if (needIndirectCall) {
3214 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3215 // to do the call, we can't use PPCISD::CALL.
3216 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3218 if (isSVR4ABI && isPPC64) {
3219 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3220 // entry point, but to the function descriptor (the function entry point
3221 // address is part of the function descriptor though).
3222 // The function descriptor is a three doubleword structure with the
3223 // following fields: function entry point, TOC base address and
3224 // environment pointer.
3225 // Thus for a call through a function pointer, the following actions need
3227 // 1. Save the TOC of the caller in the TOC save area of its stack
3228 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3229 // 2. Load the address of the function entry point from the function
3231 // 3. Load the TOC of the callee from the function descriptor into r2.
3232 // 4. Load the environment pointer from the function descriptor into
3234 // 5. Branch to the function entry point address.
3235 // 6. On return of the callee, the TOC of the caller needs to be
3236 // restored (this is done in FinishCall()).
3238 // All those operations are flagged together to ensure that no other
3239 // operations can be scheduled in between. E.g. without flagging the
3240 // operations together, a TOC access in the caller could be scheduled
3241 // between the load of the callee TOC and the branch to the callee, which
3242 // results in the TOC access going through the TOC of the callee instead
3243 // of going through the TOC of the caller, which leads to incorrect code.
3245 // Load the address of the function entry point from the function
3247 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3248 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3249 InFlag.getNode() ? 3 : 2);
3250 Chain = LoadFuncPtr.getValue(1);
3251 InFlag = LoadFuncPtr.getValue(2);
3253 // Load environment pointer into r11.
3254 // Offset of the environment pointer within the function descriptor.
3255 SDValue PtrOff = DAG.getIntPtrConstant(16);
3257 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3258 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3260 Chain = LoadEnvPtr.getValue(1);
3261 InFlag = LoadEnvPtr.getValue(2);
3263 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3265 Chain = EnvVal.getValue(0);
3266 InFlag = EnvVal.getValue(1);
3268 // Load TOC of the callee into r2. We are using a target-specific load
3269 // with r2 hard coded, because the result of a target-independent load
3270 // would never go directly into r2, since r2 is a reserved register (which
3271 // prevents the register allocator from allocating it), resulting in an
3272 // additional register being allocated and an unnecessary move instruction
3274 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3275 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3277 Chain = LoadTOCPtr.getValue(0);
3278 InFlag = LoadTOCPtr.getValue(1);
3280 MTCTROps[0] = Chain;
3281 MTCTROps[1] = LoadFuncPtr;
3282 MTCTROps[2] = InFlag;
3285 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3286 2 + (InFlag.getNode() != 0));
3287 InFlag = Chain.getValue(1);
3290 NodeTys.push_back(MVT::Other);
3291 NodeTys.push_back(MVT::Glue);
3292 Ops.push_back(Chain);
3293 CallOpc = PPCISD::BCTRL;
3295 // Add use of X11 (holding environment pointer)
3296 if (isSVR4ABI && isPPC64)
3297 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3298 // Add CTR register as callee so a bctr can be emitted later.
3300 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3303 // If this is a direct call, pass the chain and the callee.
3304 if (Callee.getNode()) {
3305 Ops.push_back(Chain);
3306 Ops.push_back(Callee);
3308 // If this is a tail call add stack pointer delta.
3310 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3312 // Add argument registers to the end of the list so that they are known live
3314 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3315 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3316 RegsToPass[i].second.getValueType()));
3322 bool isLocalCall(const SDValue &Callee)
3324 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3325 return !G->getGlobal()->isDeclaration() &&
3326 !G->getGlobal()->isWeakForLinker();
3331 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3332 CallingConv::ID CallConv, bool isVarArg,
3333 const SmallVectorImpl<ISD::InputArg> &Ins,
3334 SDLoc dl, SelectionDAG &DAG,
3335 SmallVectorImpl<SDValue> &InVals) const {
3337 SmallVector<CCValAssign, 16> RVLocs;
3338 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3339 getTargetMachine(), RVLocs, *DAG.getContext());
3340 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3342 // Copy all of the result registers out of their specified physreg.
3343 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3344 CCValAssign &VA = RVLocs[i];
3345 assert(VA.isRegLoc() && "Can only return in registers!");
3347 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3348 VA.getLocReg(), VA.getLocVT(), InFlag);
3349 Chain = Val.getValue(1);
3350 InFlag = Val.getValue(2);
3352 switch (VA.getLocInfo()) {
3353 default: llvm_unreachable("Unknown loc info!");
3354 case CCValAssign::Full: break;
3355 case CCValAssign::AExt:
3356 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3358 case CCValAssign::ZExt:
3359 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3360 DAG.getValueType(VA.getValVT()));
3361 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3363 case CCValAssign::SExt:
3364 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3365 DAG.getValueType(VA.getValVT()));
3366 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3370 InVals.push_back(Val);
3377 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3378 bool isTailCall, bool isVarArg,
3380 SmallVector<std::pair<unsigned, SDValue>, 8>
3382 SDValue InFlag, SDValue Chain,
3384 int SPDiff, unsigned NumBytes,
3385 const SmallVectorImpl<ISD::InputArg> &Ins,
3386 SmallVectorImpl<SDValue> &InVals) const {
3387 std::vector<EVT> NodeTys;
3388 SmallVector<SDValue, 8> Ops;
3389 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3390 isTailCall, RegsToPass, Ops, NodeTys,
3393 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3394 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3395 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3397 // When performing tail call optimization the callee pops its arguments off
3398 // the stack. Account for this here so these bytes can be pushed back on in
3399 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3400 int BytesCalleePops =
3401 (CallConv == CallingConv::Fast &&
3402 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3404 // Add a register mask operand representing the call-preserved registers.
3405 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3406 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3407 assert(Mask && "Missing call preserved mask for calling convention");
3408 Ops.push_back(DAG.getRegisterMask(Mask));
3410 if (InFlag.getNode())
3411 Ops.push_back(InFlag);
3415 assert(((Callee.getOpcode() == ISD::Register &&
3416 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3417 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3418 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3419 isa<ConstantSDNode>(Callee)) &&
3420 "Expecting an global address, external symbol, absolute value or register");
3422 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3425 // Add a NOP immediately after the branch instruction when using the 64-bit
3426 // SVR4 ABI. At link time, if caller and callee are in a different module and
3427 // thus have a different TOC, the call will be replaced with a call to a stub
3428 // function which saves the current TOC, loads the TOC of the callee and
3429 // branches to the callee. The NOP will be replaced with a load instruction
3430 // which restores the TOC of the caller from the TOC save slot of the current
3431 // stack frame. If caller and callee belong to the same module (and have the
3432 // same TOC), the NOP will remain unchanged.
3434 bool needsTOCRestore = false;
3435 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3436 if (CallOpc == PPCISD::BCTRL) {
3437 // This is a call through a function pointer.
3438 // Restore the caller TOC from the save area into R2.
3439 // See PrepareCall() for more information about calls through function
3440 // pointers in the 64-bit SVR4 ABI.
3441 // We are using a target-specific load with r2 hard coded, because the
3442 // result of a target-independent load would never go directly into r2,
3443 // since r2 is a reserved register (which prevents the register allocator
3444 // from allocating it), resulting in an additional register being
3445 // allocated and an unnecessary move instruction being generated.
3446 needsTOCRestore = true;
3447 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3448 // Otherwise insert NOP for non-local calls.
3449 CallOpc = PPCISD::CALL_NOP;
3453 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3454 InFlag = Chain.getValue(1);
3456 if (needsTOCRestore) {
3457 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3458 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3459 InFlag = Chain.getValue(1);
3462 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3463 DAG.getIntPtrConstant(BytesCalleePops, true),
3466 InFlag = Chain.getValue(1);
3468 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3469 Ins, dl, DAG, InVals);
3473 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3474 SmallVectorImpl<SDValue> &InVals) const {
3475 SelectionDAG &DAG = CLI.DAG;
3477 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3478 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3479 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3480 SDValue Chain = CLI.Chain;
3481 SDValue Callee = CLI.Callee;
3482 bool &isTailCall = CLI.IsTailCall;
3483 CallingConv::ID CallConv = CLI.CallConv;
3484 bool isVarArg = CLI.IsVarArg;
3487 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3490 if (PPCSubTarget.isSVR4ABI()) {
3491 if (PPCSubTarget.isPPC64())
3492 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3493 isTailCall, Outs, OutVals, Ins,
3496 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3497 isTailCall, Outs, OutVals, Ins,
3501 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3502 isTailCall, Outs, OutVals, Ins,
3507 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3508 CallingConv::ID CallConv, bool isVarArg,
3510 const SmallVectorImpl<ISD::OutputArg> &Outs,
3511 const SmallVectorImpl<SDValue> &OutVals,
3512 const SmallVectorImpl<ISD::InputArg> &Ins,
3513 SDLoc dl, SelectionDAG &DAG,
3514 SmallVectorImpl<SDValue> &InVals) const {
3515 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3516 // of the 32-bit SVR4 ABI stack frame layout.
3518 assert((CallConv == CallingConv::C ||
3519 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3521 unsigned PtrByteSize = 4;
3523 MachineFunction &MF = DAG.getMachineFunction();
3525 // Mark this function as potentially containing a function that contains a
3526 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3527 // and restoring the callers stack pointer in this functions epilog. This is
3528 // done because by tail calling the called function might overwrite the value
3529 // in this function's (MF) stack pointer stack slot 0(SP).
3530 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3531 CallConv == CallingConv::Fast)
3532 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3534 // Count how many bytes are to be pushed on the stack, including the linkage
3535 // area, parameter list area and the part of the local variable space which
3536 // contains copies of aggregates which are passed by value.
3538 // Assign locations to all of the outgoing arguments.
3539 SmallVector<CCValAssign, 16> ArgLocs;
3540 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3541 getTargetMachine(), ArgLocs, *DAG.getContext());
3543 // Reserve space for the linkage area on the stack.
3544 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3547 // Handle fixed and variable vector arguments differently.
3548 // Fixed vector arguments go into registers as long as registers are
3549 // available. Variable vector arguments always go into memory.
3550 unsigned NumArgs = Outs.size();
3552 for (unsigned i = 0; i != NumArgs; ++i) {
3553 MVT ArgVT = Outs[i].VT;
3554 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3557 if (Outs[i].IsFixed) {
3558 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3561 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3567 errs() << "Call operand #" << i << " has unhandled type "
3568 << EVT(ArgVT).getEVTString() << "\n";
3570 llvm_unreachable(0);
3574 // All arguments are treated the same.
3575 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3578 // Assign locations to all of the outgoing aggregate by value arguments.
3579 SmallVector<CCValAssign, 16> ByValArgLocs;
3580 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3581 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3583 // Reserve stack space for the allocations in CCInfo.
3584 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3586 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3588 // Size of the linkage area, parameter list area and the part of the local
3589 // space variable where copies of aggregates which are passed by value are
3591 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3593 // Calculate by how many bytes the stack has to be adjusted in case of tail
3594 // call optimization.
3595 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3597 // Adjust the stack pointer for the new arguments...
3598 // These operations are automatically eliminated by the prolog/epilog pass
3599 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3601 SDValue CallSeqStart = Chain;
3603 // Load the return address and frame pointer so it can be moved somewhere else
3606 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3609 // Set up a copy of the stack pointer for use loading and storing any
3610 // arguments that may not fit in the registers available for argument
3612 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3614 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3615 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3616 SmallVector<SDValue, 8> MemOpChains;
3618 bool seenFloatArg = false;
3619 // Walk the register/memloc assignments, inserting copies/loads.
3620 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3623 CCValAssign &VA = ArgLocs[i];
3624 SDValue Arg = OutVals[i];
3625 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3627 if (Flags.isByVal()) {
3628 // Argument is an aggregate which is passed by value, thus we need to
3629 // create a copy of it in the local variable space of the current stack
3630 // frame (which is the stack frame of the caller) and pass the address of
3631 // this copy to the callee.
3632 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3633 CCValAssign &ByValVA = ByValArgLocs[j++];
3634 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3636 // Memory reserved in the local variable space of the callers stack frame.
3637 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3639 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3640 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3642 // Create a copy of the argument in the local area of the current
3644 SDValue MemcpyCall =
3645 CreateCopyOfByValArgument(Arg, PtrOff,
3646 CallSeqStart.getNode()->getOperand(0),
3649 // This must go outside the CALLSEQ_START..END.
3650 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3651 CallSeqStart.getNode()->getOperand(1),
3653 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3654 NewCallSeqStart.getNode());
3655 Chain = CallSeqStart = NewCallSeqStart;
3657 // Pass the address of the aggregate copy on the stack either in a
3658 // physical register or in the parameter list area of the current stack
3659 // frame to the callee.
3663 if (VA.isRegLoc()) {
3664 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3665 // Put argument in a physical register.
3666 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3668 // Put argument in the parameter list area of the current stack frame.
3669 assert(VA.isMemLoc());
3670 unsigned LocMemOffset = VA.getLocMemOffset();
3673 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3674 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3676 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3677 MachinePointerInfo(),
3680 // Calculate and remember argument location.
3681 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3687 if (!MemOpChains.empty())
3688 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3689 &MemOpChains[0], MemOpChains.size());
3691 // Build a sequence of copy-to-reg nodes chained together with token chain
3692 // and flag operands which copy the outgoing args into the appropriate regs.
3694 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3695 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3696 RegsToPass[i].second, InFlag);
3697 InFlag = Chain.getValue(1);
3700 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3703 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3704 SDValue Ops[] = { Chain, InFlag };
3706 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3707 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3709 InFlag = Chain.getValue(1);
3713 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3714 false, TailCallArguments);
3716 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3717 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3721 // Copy an argument into memory, being careful to do this outside the
3722 // call sequence for the call to which the argument belongs.
3724 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3725 SDValue CallSeqStart,
3726 ISD::ArgFlagsTy Flags,
3729 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3730 CallSeqStart.getNode()->getOperand(0),
3732 // The MEMCPY must go outside the CALLSEQ_START..END.
3733 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3734 CallSeqStart.getNode()->getOperand(1),
3736 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3737 NewCallSeqStart.getNode());
3738 return NewCallSeqStart;
3742 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3743 CallingConv::ID CallConv, bool isVarArg,
3745 const SmallVectorImpl<ISD::OutputArg> &Outs,
3746 const SmallVectorImpl<SDValue> &OutVals,
3747 const SmallVectorImpl<ISD::InputArg> &Ins,
3748 SDLoc dl, SelectionDAG &DAG,
3749 SmallVectorImpl<SDValue> &InVals) const {
3751 unsigned NumOps = Outs.size();
3753 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3754 unsigned PtrByteSize = 8;
3756 MachineFunction &MF = DAG.getMachineFunction();
3758 // Mark this function as potentially containing a function that contains a
3759 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3760 // and restoring the callers stack pointer in this functions epilog. This is
3761 // done because by tail calling the called function might overwrite the value
3762 // in this function's (MF) stack pointer stack slot 0(SP).
3763 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3764 CallConv == CallingConv::Fast)
3765 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3767 unsigned nAltivecParamsAtEnd = 0;
3769 // Count how many bytes are to be pushed on the stack, including the linkage
3770 // area, and parameter passing area. We start with at least 48 bytes, which
3771 // is reserved space for [SP][CR][LR][3 x unused].
3772 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3775 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3776 Outs, OutVals, nAltivecParamsAtEnd);
3778 // Calculate by how many bytes the stack has to be adjusted in case of tail
3779 // call optimization.
3780 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3782 // To protect arguments on the stack from being clobbered in a tail call,
3783 // force all the loads to happen before doing any other lowering.
3785 Chain = DAG.getStackArgumentTokenFactor(Chain);
3787 // Adjust the stack pointer for the new arguments...
3788 // These operations are automatically eliminated by the prolog/epilog pass
3789 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3791 SDValue CallSeqStart = Chain;
3793 // Load the return address and frame pointer so it can be move somewhere else
3796 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3799 // Set up a copy of the stack pointer for use loading and storing any
3800 // arguments that may not fit in the registers available for argument
3802 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3804 // Figure out which arguments are going to go in registers, and which in
3805 // memory. Also, if this is a vararg function, floating point operations
3806 // must be stored to our stack, and loaded into integer regs as well, if
3807 // any integer regs are available for argument passing.
3808 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3809 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3811 static const uint16_t GPR[] = {
3812 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3813 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3815 static const uint16_t *FPR = GetFPR();
3817 static const uint16_t VR[] = {
3818 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3819 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3821 const unsigned NumGPRs = array_lengthof(GPR);
3822 const unsigned NumFPRs = 13;
3823 const unsigned NumVRs = array_lengthof(VR);
3825 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3826 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3828 SmallVector<SDValue, 8> MemOpChains;
3829 for (unsigned i = 0; i != NumOps; ++i) {
3830 SDValue Arg = OutVals[i];
3831 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3833 // PtrOff will be used to store the current argument to the stack if a
3834 // register cannot be found for it.
3837 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3839 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3841 // Promote integers to 64-bit values.
3842 if (Arg.getValueType() == MVT::i32) {
3843 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3844 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3845 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3848 // FIXME memcpy is used way more than necessary. Correctness first.
3849 // Note: "by value" is code for passing a structure by value, not
3851 if (Flags.isByVal()) {
3852 // Note: Size includes alignment padding, so
3853 // struct x { short a; char b; }
3854 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3855 // These are the proper values we need for right-justifying the
3856 // aggregate in a parameter register.
3857 unsigned Size = Flags.getByValSize();
3859 // An empty aggregate parameter takes up no storage and no
3864 // All aggregates smaller than 8 bytes must be passed right-justified.
3865 if (Size==1 || Size==2 || Size==4) {
3866 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3867 if (GPR_idx != NumGPRs) {
3868 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3869 MachinePointerInfo(), VT,
3871 MemOpChains.push_back(Load.getValue(1));
3872 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3874 ArgOffset += PtrByteSize;
3879 if (GPR_idx == NumGPRs && Size < 8) {
3880 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3881 PtrOff.getValueType());
3882 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3883 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3886 ArgOffset += PtrByteSize;
3889 // Copy entire object into memory. There are cases where gcc-generated
3890 // code assumes it is there, even if it could be put entirely into
3891 // registers. (This is not what the doc says.)
3893 // FIXME: The above statement is likely due to a misunderstanding of the
3894 // documents. All arguments must be copied into the parameter area BY
3895 // THE CALLEE in the event that the callee takes the address of any
3896 // formal argument. That has not yet been implemented. However, it is
3897 // reasonable to use the stack area as a staging area for the register
3900 // Skip this for small aggregates, as we will use the same slot for a
3901 // right-justified copy, below.
3903 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3907 // When a register is available, pass a small aggregate right-justified.
3908 if (Size < 8 && GPR_idx != NumGPRs) {
3909 // The easiest way to get this right-justified in a register
3910 // is to copy the structure into the rightmost portion of a
3911 // local variable slot, then load the whole slot into the
3913 // FIXME: The memcpy seems to produce pretty awful code for
3914 // small aggregates, particularly for packed ones.
3915 // FIXME: It would be preferable to use the slot in the
3916 // parameter save area instead of a new local variable.
3917 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3918 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3919 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3923 // Load the slot into the register.
3924 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3925 MachinePointerInfo(),
3926 false, false, false, 0);
3927 MemOpChains.push_back(Load.getValue(1));
3928 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3930 // Done with this argument.
3931 ArgOffset += PtrByteSize;
3935 // For aggregates larger than PtrByteSize, copy the pieces of the
3936 // object that fit into registers from the parameter save area.
3937 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3938 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3939 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3940 if (GPR_idx != NumGPRs) {
3941 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3942 MachinePointerInfo(),
3943 false, false, false, 0);
3944 MemOpChains.push_back(Load.getValue(1));
3945 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3946 ArgOffset += PtrByteSize;
3948 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3955 switch (Arg.getSimpleValueType().SimpleTy) {
3956 default: llvm_unreachable("Unexpected ValueType for argument!");
3959 if (GPR_idx != NumGPRs) {
3960 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3962 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3963 true, isTailCall, false, MemOpChains,
3964 TailCallArguments, dl);
3966 ArgOffset += PtrByteSize;
3970 if (FPR_idx != NumFPRs) {
3971 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3974 // A single float or an aggregate containing only a single float
3975 // must be passed right-justified in the stack doubleword, and
3976 // in the GPR, if one is available.
3978 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
3979 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3980 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3984 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3985 MachinePointerInfo(), false, false, 0);
3986 MemOpChains.push_back(Store);
3988 // Float varargs are always shadowed in available integer registers
3989 if (GPR_idx != NumGPRs) {
3990 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3991 MachinePointerInfo(), false, false,
3993 MemOpChains.push_back(Load.getValue(1));
3994 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3996 } else if (GPR_idx != NumGPRs)
3997 // If we have any FPRs remaining, we may also have GPRs remaining.
4000 // Single-precision floating-point values are mapped to the
4001 // second (rightmost) word of the stack doubleword.
4002 if (Arg.getValueType() == MVT::f32) {
4003 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4004 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4007 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4008 true, isTailCall, false, MemOpChains,
4009 TailCallArguments, dl);
4018 // These go aligned on the stack, or in the corresponding R registers
4019 // when within range. The Darwin PPC ABI doc claims they also go in
4020 // V registers; in fact gcc does this only for arguments that are
4021 // prototyped, not for those that match the ... We do it for all
4022 // arguments, seems to work.
4023 while (ArgOffset % 16 !=0) {
4024 ArgOffset += PtrByteSize;
4025 if (GPR_idx != NumGPRs)
4028 // We could elide this store in the case where the object fits
4029 // entirely in R registers. Maybe later.
4030 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4031 DAG.getConstant(ArgOffset, PtrVT));
4032 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4033 MachinePointerInfo(), false, false, 0);
4034 MemOpChains.push_back(Store);
4035 if (VR_idx != NumVRs) {
4036 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4037 MachinePointerInfo(),
4038 false, false, false, 0);
4039 MemOpChains.push_back(Load.getValue(1));
4040 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4043 for (unsigned i=0; i<16; i+=PtrByteSize) {
4044 if (GPR_idx == NumGPRs)
4046 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4047 DAG.getConstant(i, PtrVT));
4048 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4049 false, false, false, 0);
4050 MemOpChains.push_back(Load.getValue(1));
4051 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4056 // Non-varargs Altivec params generally go in registers, but have
4057 // stack space allocated at the end.
4058 if (VR_idx != NumVRs) {
4059 // Doesn't have GPR space allocated.
4060 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4062 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4063 true, isTailCall, true, MemOpChains,
4064 TailCallArguments, dl);
4071 if (!MemOpChains.empty())
4072 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4073 &MemOpChains[0], MemOpChains.size());
4075 // Check if this is an indirect call (MTCTR/BCTRL).
4076 // See PrepareCall() for more information about calls through function
4077 // pointers in the 64-bit SVR4 ABI.
4079 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4080 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4081 !isBLACompatibleAddress(Callee, DAG)) {
4082 // Load r2 into a virtual register and store it to the TOC save area.
4083 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4084 // TOC save area offset.
4085 SDValue PtrOff = DAG.getIntPtrConstant(40);
4086 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4087 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4089 // R12 must contain the address of an indirect callee. This does not
4090 // mean the MTCTR instruction must use R12; it's easier to model this
4091 // as an extra parameter, so do that.
4092 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4095 // Build a sequence of copy-to-reg nodes chained together with token chain
4096 // and flag operands which copy the outgoing args into the appropriate regs.
4098 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4099 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4100 RegsToPass[i].second, InFlag);
4101 InFlag = Chain.getValue(1);
4105 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4106 FPOp, true, TailCallArguments);
4108 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4109 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4114 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4115 CallingConv::ID CallConv, bool isVarArg,
4117 const SmallVectorImpl<ISD::OutputArg> &Outs,
4118 const SmallVectorImpl<SDValue> &OutVals,
4119 const SmallVectorImpl<ISD::InputArg> &Ins,
4120 SDLoc dl, SelectionDAG &DAG,
4121 SmallVectorImpl<SDValue> &InVals) const {
4123 unsigned NumOps = Outs.size();
4125 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4126 bool isPPC64 = PtrVT == MVT::i64;
4127 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4129 MachineFunction &MF = DAG.getMachineFunction();
4131 // Mark this function as potentially containing a function that contains a
4132 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4133 // and restoring the callers stack pointer in this functions epilog. This is
4134 // done because by tail calling the called function might overwrite the value
4135 // in this function's (MF) stack pointer stack slot 0(SP).
4136 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4137 CallConv == CallingConv::Fast)
4138 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4140 unsigned nAltivecParamsAtEnd = 0;
4142 // Count how many bytes are to be pushed on the stack, including the linkage
4143 // area, and parameter passing area. We start with 24/48 bytes, which is
4144 // prereserved space for [SP][CR][LR][3 x unused].
4146 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4148 nAltivecParamsAtEnd);
4150 // Calculate by how many bytes the stack has to be adjusted in case of tail
4151 // call optimization.
4152 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4154 // To protect arguments on the stack from being clobbered in a tail call,
4155 // force all the loads to happen before doing any other lowering.
4157 Chain = DAG.getStackArgumentTokenFactor(Chain);
4159 // Adjust the stack pointer for the new arguments...
4160 // These operations are automatically eliminated by the prolog/epilog pass
4161 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4163 SDValue CallSeqStart = Chain;
4165 // Load the return address and frame pointer so it can be move somewhere else
4168 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4171 // Set up a copy of the stack pointer for use loading and storing any
4172 // arguments that may not fit in the registers available for argument
4176 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4178 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4180 // Figure out which arguments are going to go in registers, and which in
4181 // memory. Also, if this is a vararg function, floating point operations
4182 // must be stored to our stack, and loaded into integer regs as well, if
4183 // any integer regs are available for argument passing.
4184 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4185 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4187 static const uint16_t GPR_32[] = { // 32-bit registers.
4188 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4189 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4191 static const uint16_t GPR_64[] = { // 64-bit registers.
4192 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4193 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4195 static const uint16_t *FPR = GetFPR();
4197 static const uint16_t VR[] = {
4198 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4199 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4201 const unsigned NumGPRs = array_lengthof(GPR_32);
4202 const unsigned NumFPRs = 13;
4203 const unsigned NumVRs = array_lengthof(VR);
4205 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4207 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4208 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4210 SmallVector<SDValue, 8> MemOpChains;
4211 for (unsigned i = 0; i != NumOps; ++i) {
4212 SDValue Arg = OutVals[i];
4213 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4215 // PtrOff will be used to store the current argument to the stack if a
4216 // register cannot be found for it.
4219 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4221 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4223 // On PPC64, promote integers to 64-bit values.
4224 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4225 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4226 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4227 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4230 // FIXME memcpy is used way more than necessary. Correctness first.
4231 // Note: "by value" is code for passing a structure by value, not
4233 if (Flags.isByVal()) {
4234 unsigned Size = Flags.getByValSize();
4235 // Very small objects are passed right-justified. Everything else is
4236 // passed left-justified.
4237 if (Size==1 || Size==2) {
4238 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4239 if (GPR_idx != NumGPRs) {
4240 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4241 MachinePointerInfo(), VT,
4243 MemOpChains.push_back(Load.getValue(1));
4244 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4246 ArgOffset += PtrByteSize;
4248 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4249 PtrOff.getValueType());
4250 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4251 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4254 ArgOffset += PtrByteSize;
4258 // Copy entire object into memory. There are cases where gcc-generated
4259 // code assumes it is there, even if it could be put entirely into
4260 // registers. (This is not what the doc says.)
4261 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4265 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4266 // copy the pieces of the object that fit into registers from the
4267 // parameter save area.
4268 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4269 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4270 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4271 if (GPR_idx != NumGPRs) {
4272 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4273 MachinePointerInfo(),
4274 false, false, false, 0);
4275 MemOpChains.push_back(Load.getValue(1));
4276 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4277 ArgOffset += PtrByteSize;
4279 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4286 switch (Arg.getSimpleValueType().SimpleTy) {
4287 default: llvm_unreachable("Unexpected ValueType for argument!");
4290 if (GPR_idx != NumGPRs) {
4291 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4293 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4294 isPPC64, isTailCall, false, MemOpChains,
4295 TailCallArguments, dl);
4297 ArgOffset += PtrByteSize;
4301 if (FPR_idx != NumFPRs) {
4302 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4305 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4306 MachinePointerInfo(), false, false, 0);
4307 MemOpChains.push_back(Store);
4309 // Float varargs are always shadowed in available integer registers
4310 if (GPR_idx != NumGPRs) {
4311 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4312 MachinePointerInfo(), false, false,
4314 MemOpChains.push_back(Load.getValue(1));
4315 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4317 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4318 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4319 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4320 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4321 MachinePointerInfo(),
4322 false, false, false, 0);
4323 MemOpChains.push_back(Load.getValue(1));
4324 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4327 // If we have any FPRs remaining, we may also have GPRs remaining.
4328 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4330 if (GPR_idx != NumGPRs)
4332 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4333 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4337 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4338 isPPC64, isTailCall, false, MemOpChains,
4339 TailCallArguments, dl);
4343 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4350 // These go aligned on the stack, or in the corresponding R registers
4351 // when within range. The Darwin PPC ABI doc claims they also go in
4352 // V registers; in fact gcc does this only for arguments that are
4353 // prototyped, not for those that match the ... We do it for all
4354 // arguments, seems to work.
4355 while (ArgOffset % 16 !=0) {
4356 ArgOffset += PtrByteSize;
4357 if (GPR_idx != NumGPRs)
4360 // We could elide this store in the case where the object fits
4361 // entirely in R registers. Maybe later.
4362 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4363 DAG.getConstant(ArgOffset, PtrVT));
4364 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4365 MachinePointerInfo(), false, false, 0);
4366 MemOpChains.push_back(Store);
4367 if (VR_idx != NumVRs) {
4368 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4369 MachinePointerInfo(),
4370 false, false, false, 0);
4371 MemOpChains.push_back(Load.getValue(1));
4372 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4375 for (unsigned i=0; i<16; i+=PtrByteSize) {
4376 if (GPR_idx == NumGPRs)
4378 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4379 DAG.getConstant(i, PtrVT));
4380 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4381 false, false, false, 0);
4382 MemOpChains.push_back(Load.getValue(1));
4383 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4388 // Non-varargs Altivec params generally go in registers, but have
4389 // stack space allocated at the end.
4390 if (VR_idx != NumVRs) {
4391 // Doesn't have GPR space allocated.
4392 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4393 } else if (nAltivecParamsAtEnd==0) {
4394 // We are emitting Altivec params in order.
4395 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4396 isPPC64, isTailCall, true, MemOpChains,
4397 TailCallArguments, dl);
4403 // If all Altivec parameters fit in registers, as they usually do,
4404 // they get stack space following the non-Altivec parameters. We
4405 // don't track this here because nobody below needs it.
4406 // If there are more Altivec parameters than fit in registers emit
4408 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4410 // Offset is aligned; skip 1st 12 params which go in V registers.
4411 ArgOffset = ((ArgOffset+15)/16)*16;
4413 for (unsigned i = 0; i != NumOps; ++i) {
4414 SDValue Arg = OutVals[i];
4415 EVT ArgType = Outs[i].VT;
4416 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4417 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4420 // We are emitting Altivec params in order.
4421 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4422 isPPC64, isTailCall, true, MemOpChains,
4423 TailCallArguments, dl);
4430 if (!MemOpChains.empty())
4431 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4432 &MemOpChains[0], MemOpChains.size());
4434 // On Darwin, R12 must contain the address of an indirect callee. This does
4435 // not mean the MTCTR instruction must use R12; it's easier to model this as
4436 // an extra parameter, so do that.
4438 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4439 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4440 !isBLACompatibleAddress(Callee, DAG))
4441 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4442 PPC::R12), Callee));
4444 // Build a sequence of copy-to-reg nodes chained together with token chain
4445 // and flag operands which copy the outgoing args into the appropriate regs.
4447 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4448 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4449 RegsToPass[i].second, InFlag);
4450 InFlag = Chain.getValue(1);
4454 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4455 FPOp, true, TailCallArguments);
4457 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4458 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4463 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4464 MachineFunction &MF, bool isVarArg,
4465 const SmallVectorImpl<ISD::OutputArg> &Outs,
4466 LLVMContext &Context) const {
4467 SmallVector<CCValAssign, 16> RVLocs;
4468 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4470 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4474 PPCTargetLowering::LowerReturn(SDValue Chain,
4475 CallingConv::ID CallConv, bool isVarArg,
4476 const SmallVectorImpl<ISD::OutputArg> &Outs,
4477 const SmallVectorImpl<SDValue> &OutVals,
4478 SDLoc dl, SelectionDAG &DAG) const {
4480 SmallVector<CCValAssign, 16> RVLocs;
4481 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4482 getTargetMachine(), RVLocs, *DAG.getContext());
4483 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4486 SmallVector<SDValue, 4> RetOps(1, Chain);
4488 // Copy the result values into the output registers.
4489 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4490 CCValAssign &VA = RVLocs[i];
4491 assert(VA.isRegLoc() && "Can only return in registers!");
4493 SDValue Arg = OutVals[i];
4495 switch (VA.getLocInfo()) {
4496 default: llvm_unreachable("Unknown loc info!");
4497 case CCValAssign::Full: break;
4498 case CCValAssign::AExt:
4499 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4501 case CCValAssign::ZExt:
4502 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4504 case CCValAssign::SExt:
4505 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4509 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4510 Flag = Chain.getValue(1);
4511 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4514 RetOps[0] = Chain; // Update chain.
4516 // Add the flag if we have it.
4518 RetOps.push_back(Flag);
4520 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4521 &RetOps[0], RetOps.size());
4524 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4525 const PPCSubtarget &Subtarget) const {
4526 // When we pop the dynamic allocation we need to restore the SP link.
4529 // Get the corect type for pointers.
4530 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4532 // Construct the stack pointer operand.
4533 bool isPPC64 = Subtarget.isPPC64();
4534 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4535 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4537 // Get the operands for the STACKRESTORE.
4538 SDValue Chain = Op.getOperand(0);
4539 SDValue SaveSP = Op.getOperand(1);
4541 // Load the old link SP.
4542 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4543 MachinePointerInfo(),
4544 false, false, false, 0);
4546 // Restore the stack pointer.
4547 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4549 // Store the old link SP.
4550 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4557 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4558 MachineFunction &MF = DAG.getMachineFunction();
4559 bool isPPC64 = PPCSubTarget.isPPC64();
4560 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4561 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4563 // Get current frame pointer save index. The users of this index will be
4564 // primarily DYNALLOC instructions.
4565 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4566 int RASI = FI->getReturnAddrSaveIndex();
4568 // If the frame pointer save index hasn't been defined yet.
4570 // Find out what the fix offset of the frame pointer save area.
4571 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4572 // Allocate the frame index for frame pointer save area.
4573 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4575 FI->setReturnAddrSaveIndex(RASI);
4577 return DAG.getFrameIndex(RASI, PtrVT);
4581 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4582 MachineFunction &MF = DAG.getMachineFunction();
4583 bool isPPC64 = PPCSubTarget.isPPC64();
4584 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4585 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4587 // Get current frame pointer save index. The users of this index will be
4588 // primarily DYNALLOC instructions.
4589 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4590 int FPSI = FI->getFramePointerSaveIndex();
4592 // If the frame pointer save index hasn't been defined yet.
4594 // Find out what the fix offset of the frame pointer save area.
4595 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4598 // Allocate the frame index for frame pointer save area.
4599 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4601 FI->setFramePointerSaveIndex(FPSI);
4603 return DAG.getFrameIndex(FPSI, PtrVT);
4606 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4608 const PPCSubtarget &Subtarget) const {
4610 SDValue Chain = Op.getOperand(0);
4611 SDValue Size = Op.getOperand(1);
4614 // Get the corect type for pointers.
4615 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4617 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4618 DAG.getConstant(0, PtrVT), Size);
4619 // Construct a node for the frame pointer save index.
4620 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4621 // Build a DYNALLOC node.
4622 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4623 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4624 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4627 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4628 SelectionDAG &DAG) const {
4630 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4631 DAG.getVTList(MVT::i32, MVT::Other),
4632 Op.getOperand(0), Op.getOperand(1));
4635 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4636 SelectionDAG &DAG) const {
4638 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4639 Op.getOperand(0), Op.getOperand(1));
4642 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4644 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4645 // Not FP? Not a fsel.
4646 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4647 !Op.getOperand(2).getValueType().isFloatingPoint())
4650 // We might be able to do better than this under some circumstances, but in
4651 // general, fsel-based lowering of select is a finite-math-only optimization.
4652 // For more information, see section F.3 of the 2.06 ISA specification.
4653 if (!DAG.getTarget().Options.NoInfsFPMath ||
4654 !DAG.getTarget().Options.NoNaNsFPMath)
4657 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4659 EVT ResVT = Op.getValueType();
4660 EVT CmpVT = Op.getOperand(0).getValueType();
4661 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4662 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4665 // If the RHS of the comparison is a 0.0, we don't need to do the
4666 // subtraction at all.
4668 if (isFloatingPointZero(RHS))
4670 default: break; // SETUO etc aren't handled by fsel.
4674 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4675 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4676 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4677 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4678 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4679 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4680 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4683 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4686 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4687 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4688 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4691 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4694 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4695 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4696 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4697 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4702 default: break; // SETUO etc aren't handled by fsel.
4706 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4707 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4708 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4709 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4710 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4711 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4712 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4713 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4716 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4717 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4718 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4719 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4722 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4723 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4724 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4725 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4728 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4729 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4730 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4731 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4734 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4735 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4736 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4737 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4742 // FIXME: Split this code up when LegalizeDAGTypes lands.
4743 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4745 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4746 SDValue Src = Op.getOperand(0);
4747 if (Src.getValueType() == MVT::f32)
4748 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4751 switch (Op.getSimpleValueType().SimpleTy) {
4752 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4754 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4755 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4760 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4761 "i64 FP_TO_UINT is supported only with FPCVT");
4762 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4768 // Convert the FP value to an int value through memory.
4769 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4770 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4771 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4772 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4773 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4775 // Emit a store to the stack slot.
4778 MachineFunction &MF = DAG.getMachineFunction();
4779 MachineMemOperand *MMO =
4780 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4781 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4782 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4783 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4786 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4787 MPI, false, false, 0);
4789 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4791 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4792 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4793 DAG.getConstant(4, FIPtr.getValueType()));
4794 MPI = MachinePointerInfo();
4797 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4798 false, false, false, 0);
4801 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4802 SelectionDAG &DAG) const {
4804 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4805 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4808 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4809 "UINT_TO_FP is supported only with FPCVT");
4811 // If we have FCFIDS, then use it when converting to single-precision.
4812 // Otherwise, convert to double-precision and then round.
4813 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4814 (Op.getOpcode() == ISD::UINT_TO_FP ?
4815 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4816 (Op.getOpcode() == ISD::UINT_TO_FP ?
4817 PPCISD::FCFIDU : PPCISD::FCFID);
4818 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4819 MVT::f32 : MVT::f64;
4821 if (Op.getOperand(0).getValueType() == MVT::i64) {
4822 SDValue SINT = Op.getOperand(0);
4823 // When converting to single-precision, we actually need to convert
4824 // to double-precision first and then round to single-precision.
4825 // To avoid double-rounding effects during that operation, we have
4826 // to prepare the input operand. Bits that might be truncated when
4827 // converting to double-precision are replaced by a bit that won't
4828 // be lost at this stage, but is below the single-precision rounding
4831 // However, if -enable-unsafe-fp-math is in effect, accept double
4832 // rounding to avoid the extra overhead.
4833 if (Op.getValueType() == MVT::f32 &&
4834 !PPCSubTarget.hasFPCVT() &&
4835 !DAG.getTarget().Options.UnsafeFPMath) {
4837 // Twiddle input to make sure the low 11 bits are zero. (If this
4838 // is the case, we are guaranteed the value will fit into the 53 bit
4839 // mantissa of an IEEE double-precision value without rounding.)
4840 // If any of those low 11 bits were not zero originally, make sure
4841 // bit 12 (value 2048) is set instead, so that the final rounding
4842 // to single-precision gets the correct result.
4843 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4844 SINT, DAG.getConstant(2047, MVT::i64));
4845 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4846 Round, DAG.getConstant(2047, MVT::i64));
4847 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4848 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4849 Round, DAG.getConstant(-2048, MVT::i64));
4851 // However, we cannot use that value unconditionally: if the magnitude
4852 // of the input value is small, the bit-twiddling we did above might
4853 // end up visibly changing the output. Fortunately, in that case, we
4854 // don't need to twiddle bits since the original input will convert
4855 // exactly to double-precision floating-point already. Therefore,
4856 // construct a conditional to use the original value if the top 11
4857 // bits are all sign-bit copies, and use the rounded value computed
4859 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4860 SINT, DAG.getConstant(53, MVT::i32));
4861 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4862 Cond, DAG.getConstant(1, MVT::i64));
4863 Cond = DAG.getSetCC(dl, MVT::i32,
4864 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4866 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4869 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4870 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4872 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4873 FP = DAG.getNode(ISD::FP_ROUND, dl,
4874 MVT::f32, FP, DAG.getIntPtrConstant(0));
4878 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4879 "Unhandled INT_TO_FP type in custom expander!");
4880 // Since we only generate this in 64-bit mode, we can take advantage of
4881 // 64-bit registers. In particular, sign extend the input value into the
4882 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4883 // then lfd it and fcfid it.
4884 MachineFunction &MF = DAG.getMachineFunction();
4885 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4886 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4889 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4890 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4891 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4893 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4894 MachinePointerInfo::getFixedStack(FrameIdx),
4897 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4898 "Expected an i32 store");
4899 MachineMemOperand *MMO =
4900 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4901 MachineMemOperand::MOLoad, 4, 4);
4902 SDValue Ops[] = { Store, FIdx };
4903 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4904 PPCISD::LFIWZX : PPCISD::LFIWAX,
4905 dl, DAG.getVTList(MVT::f64, MVT::Other),
4906 Ops, 2, MVT::i32, MMO);
4908 assert(PPCSubTarget.isPPC64() &&
4909 "i32->FP without LFIWAX supported only on PPC64");
4911 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4912 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4914 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4917 // STD the extended value into the stack slot.
4918 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4919 MachinePointerInfo::getFixedStack(FrameIdx),
4922 // Load the value as a double.
4923 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4924 MachinePointerInfo::getFixedStack(FrameIdx),
4925 false, false, false, 0);
4928 // FCFID it and return it.
4929 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4930 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4931 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4935 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4936 SelectionDAG &DAG) const {
4939 The rounding mode is in bits 30:31 of FPSR, and has the following
4946 FLT_ROUNDS, on the other hand, expects the following:
4953 To perform the conversion, we do:
4954 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4957 MachineFunction &MF = DAG.getMachineFunction();
4958 EVT VT = Op.getValueType();
4959 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4960 SDValue MFFSreg, InFlag;
4962 // Save FP Control Word to register
4964 MVT::f64, // return register
4965 MVT::Glue // unused in this context
4967 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4969 // Save FP register to stack slot
4970 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4971 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4972 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4973 StackSlot, MachinePointerInfo(), false, false,0);
4975 // Load FP Control Word from low 32 bits of stack slot.
4976 SDValue Four = DAG.getConstant(4, PtrVT);
4977 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4978 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4979 false, false, false, 0);
4981 // Transform as necessary
4983 DAG.getNode(ISD::AND, dl, MVT::i32,
4984 CWD, DAG.getConstant(3, MVT::i32));
4986 DAG.getNode(ISD::SRL, dl, MVT::i32,
4987 DAG.getNode(ISD::AND, dl, MVT::i32,
4988 DAG.getNode(ISD::XOR, dl, MVT::i32,
4989 CWD, DAG.getConstant(3, MVT::i32)),
4990 DAG.getConstant(3, MVT::i32)),
4991 DAG.getConstant(1, MVT::i32));
4994 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4996 return DAG.getNode((VT.getSizeInBits() < 16 ?
4997 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5000 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5001 EVT VT = Op.getValueType();
5002 unsigned BitWidth = VT.getSizeInBits();
5004 assert(Op.getNumOperands() == 3 &&
5005 VT == Op.getOperand(1).getValueType() &&
5008 // Expand into a bunch of logical ops. Note that these ops
5009 // depend on the PPC behavior for oversized shift amounts.
5010 SDValue Lo = Op.getOperand(0);
5011 SDValue Hi = Op.getOperand(1);
5012 SDValue Amt = Op.getOperand(2);
5013 EVT AmtVT = Amt.getValueType();
5015 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5016 DAG.getConstant(BitWidth, AmtVT), Amt);
5017 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5018 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5019 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5020 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5021 DAG.getConstant(-BitWidth, AmtVT));
5022 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5023 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5024 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5025 SDValue OutOps[] = { OutLo, OutHi };
5026 return DAG.getMergeValues(OutOps, 2, dl);
5029 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5030 EVT VT = Op.getValueType();
5032 unsigned BitWidth = VT.getSizeInBits();
5033 assert(Op.getNumOperands() == 3 &&
5034 VT == Op.getOperand(1).getValueType() &&
5037 // Expand into a bunch of logical ops. Note that these ops
5038 // depend on the PPC behavior for oversized shift amounts.
5039 SDValue Lo = Op.getOperand(0);
5040 SDValue Hi = Op.getOperand(1);
5041 SDValue Amt = Op.getOperand(2);
5042 EVT AmtVT = Amt.getValueType();
5044 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5045 DAG.getConstant(BitWidth, AmtVT), Amt);
5046 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5047 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5048 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5049 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5050 DAG.getConstant(-BitWidth, AmtVT));
5051 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5052 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5053 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5054 SDValue OutOps[] = { OutLo, OutHi };
5055 return DAG.getMergeValues(OutOps, 2, dl);
5058 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5060 EVT VT = Op.getValueType();
5061 unsigned BitWidth = VT.getSizeInBits();
5062 assert(Op.getNumOperands() == 3 &&
5063 VT == Op.getOperand(1).getValueType() &&
5066 // Expand into a bunch of logical ops, followed by a select_cc.
5067 SDValue Lo = Op.getOperand(0);
5068 SDValue Hi = Op.getOperand(1);
5069 SDValue Amt = Op.getOperand(2);
5070 EVT AmtVT = Amt.getValueType();
5072 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5073 DAG.getConstant(BitWidth, AmtVT), Amt);
5074 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5075 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5076 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5077 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5078 DAG.getConstant(-BitWidth, AmtVT));
5079 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5080 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5081 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5082 Tmp4, Tmp6, ISD::SETLE);
5083 SDValue OutOps[] = { OutLo, OutHi };
5084 return DAG.getMergeValues(OutOps, 2, dl);
5087 //===----------------------------------------------------------------------===//
5088 // Vector related lowering.
5091 /// BuildSplatI - Build a canonical splati of Val with an element size of
5092 /// SplatSize. Cast the result to VT.
5093 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5094 SelectionDAG &DAG, SDLoc dl) {
5095 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5097 static const EVT VTys[] = { // canonical VT to use for each size.
5098 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5101 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5103 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5107 EVT CanonicalVT = VTys[SplatSize-1];
5109 // Build a canonical splat for this value.
5110 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5111 SmallVector<SDValue, 8> Ops;
5112 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5113 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5114 &Ops[0], Ops.size());
5115 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5118 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5119 /// specified intrinsic ID.
5120 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5121 SelectionDAG &DAG, SDLoc dl,
5122 EVT DestVT = MVT::Other) {
5123 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5124 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5125 DAG.getConstant(IID, MVT::i32), Op);
5128 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5129 /// specified intrinsic ID.
5130 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5131 SelectionDAG &DAG, SDLoc dl,
5132 EVT DestVT = MVT::Other) {
5133 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5134 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5135 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5138 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5139 /// specified intrinsic ID.
5140 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5141 SDValue Op2, SelectionDAG &DAG,
5142 SDLoc dl, EVT DestVT = MVT::Other) {
5143 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5144 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5145 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5149 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5150 /// amount. The result has the specified value type.
5151 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5152 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5153 // Force LHS/RHS to be the right type.
5154 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5155 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5158 for (unsigned i = 0; i != 16; ++i)
5160 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5161 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5164 // If this is a case we can't handle, return null and let the default
5165 // expansion code take care of it. If we CAN select this case, and if it
5166 // selects to a single instruction, return Op. Otherwise, if we can codegen
5167 // this case more efficiently than a constant pool load, lower it to the
5168 // sequence of ops that should be used.
5169 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5170 SelectionDAG &DAG) const {
5172 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5173 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5175 // Check if this is a splat of a constant value.
5176 APInt APSplatBits, APSplatUndef;
5177 unsigned SplatBitSize;
5179 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5180 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5183 unsigned SplatBits = APSplatBits.getZExtValue();
5184 unsigned SplatUndef = APSplatUndef.getZExtValue();
5185 unsigned SplatSize = SplatBitSize / 8;
5187 // First, handle single instruction cases.
5190 if (SplatBits == 0) {
5191 // Canonicalize all zero vectors to be v4i32.
5192 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5193 SDValue Z = DAG.getConstant(0, MVT::i32);
5194 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5195 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5200 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5201 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5203 if (SextVal >= -16 && SextVal <= 15)
5204 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5207 // Two instruction sequences.
5209 // If this value is in the range [-32,30] and is even, use:
5210 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5211 // If this value is in the range [17,31] and is odd, use:
5212 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5213 // If this value is in the range [-31,-17] and is odd, use:
5214 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5215 // Note the last two are three-instruction sequences.
5216 if (SextVal >= -32 && SextVal <= 31) {
5217 // To avoid having these optimizations undone by constant folding,
5218 // we convert to a pseudo that will be expanded later into one of
5220 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5221 EVT VT = Op.getValueType();
5222 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5223 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5224 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5227 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5228 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5230 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5231 // Make -1 and vspltisw -1:
5232 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5234 // Make the VSLW intrinsic, computing 0x8000_0000.
5235 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5238 // xor by OnesV to invert it.
5239 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5240 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5243 // Check to see if this is a wide variety of vsplti*, binop self cases.
5244 static const signed char SplatCsts[] = {
5245 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5246 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5249 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5250 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5251 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5252 int i = SplatCsts[idx];
5254 // Figure out what shift amount will be used by altivec if shifted by i in
5256 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5258 // vsplti + shl self.
5259 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5260 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5261 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5262 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5263 Intrinsic::ppc_altivec_vslw
5265 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5266 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5269 // vsplti + srl self.
5270 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5271 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5272 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5273 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5274 Intrinsic::ppc_altivec_vsrw
5276 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5277 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5280 // vsplti + sra self.
5281 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5282 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5283 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5284 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5285 Intrinsic::ppc_altivec_vsraw
5287 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5288 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5291 // vsplti + rol self.
5292 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5293 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5294 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5295 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5296 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5297 Intrinsic::ppc_altivec_vrlw
5299 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5300 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5303 // t = vsplti c, result = vsldoi t, t, 1
5304 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5305 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5306 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5308 // t = vsplti c, result = vsldoi t, t, 2
5309 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5310 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5311 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5313 // t = vsplti c, result = vsldoi t, t, 3
5314 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5315 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5316 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5323 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5324 /// the specified operations to build the shuffle.
5325 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5326 SDValue RHS, SelectionDAG &DAG,
5328 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5329 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5330 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5333 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5345 if (OpNum == OP_COPY) {
5346 if (LHSID == (1*9+2)*9+3) return LHS;
5347 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5351 SDValue OpLHS, OpRHS;
5352 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5353 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5357 default: llvm_unreachable("Unknown i32 permute!");
5359 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5360 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5361 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5362 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5365 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5366 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5367 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5368 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5371 for (unsigned i = 0; i != 16; ++i)
5372 ShufIdxs[i] = (i&3)+0;
5375 for (unsigned i = 0; i != 16; ++i)
5376 ShufIdxs[i] = (i&3)+4;
5379 for (unsigned i = 0; i != 16; ++i)
5380 ShufIdxs[i] = (i&3)+8;
5383 for (unsigned i = 0; i != 16; ++i)
5384 ShufIdxs[i] = (i&3)+12;
5387 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5389 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5391 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5393 EVT VT = OpLHS.getValueType();
5394 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5395 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5396 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5397 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5400 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5401 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5402 /// return the code it can be lowered into. Worst case, it can always be
5403 /// lowered into a vperm.
5404 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5405 SelectionDAG &DAG) const {
5407 SDValue V1 = Op.getOperand(0);
5408 SDValue V2 = Op.getOperand(1);
5409 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5410 EVT VT = Op.getValueType();
5412 // Cases that are handled by instructions that take permute immediates
5413 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5414 // selected by the instruction selector.
5415 if (V2.getOpcode() == ISD::UNDEF) {
5416 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5417 PPC::isSplatShuffleMask(SVOp, 2) ||
5418 PPC::isSplatShuffleMask(SVOp, 4) ||
5419 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5420 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5421 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5422 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5423 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5424 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5425 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5426 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5427 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5432 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5433 // and produce a fixed permutation. If any of these match, do not lower to
5435 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5436 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5437 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5438 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5439 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5440 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5441 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5442 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5443 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5446 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5447 // perfect shuffle table to emit an optimal matching sequence.
5448 ArrayRef<int> PermMask = SVOp->getMask();
5450 unsigned PFIndexes[4];
5451 bool isFourElementShuffle = true;
5452 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5453 unsigned EltNo = 8; // Start out undef.
5454 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5455 if (PermMask[i*4+j] < 0)
5456 continue; // Undef, ignore it.
5458 unsigned ByteSource = PermMask[i*4+j];
5459 if ((ByteSource & 3) != j) {
5460 isFourElementShuffle = false;
5465 EltNo = ByteSource/4;
5466 } else if (EltNo != ByteSource/4) {
5467 isFourElementShuffle = false;
5471 PFIndexes[i] = EltNo;
5474 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5475 // perfect shuffle vector to determine if it is cost effective to do this as
5476 // discrete instructions, or whether we should use a vperm.
5477 if (isFourElementShuffle) {
5478 // Compute the index in the perfect shuffle table.
5479 unsigned PFTableIndex =
5480 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5482 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5483 unsigned Cost = (PFEntry >> 30);
5485 // Determining when to avoid vperm is tricky. Many things affect the cost
5486 // of vperm, particularly how many times the perm mask needs to be computed.
5487 // For example, if the perm mask can be hoisted out of a loop or is already
5488 // used (perhaps because there are multiple permutes with the same shuffle
5489 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5490 // the loop requires an extra register.
5492 // As a compromise, we only emit discrete instructions if the shuffle can be
5493 // generated in 3 or fewer operations. When we have loop information
5494 // available, if this block is within a loop, we should avoid using vperm
5495 // for 3-operation perms and use a constant pool load instead.
5497 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5500 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5501 // vector that will get spilled to the constant pool.
5502 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5504 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5505 // that it is in input element units, not in bytes. Convert now.
5506 EVT EltVT = V1.getValueType().getVectorElementType();
5507 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5509 SmallVector<SDValue, 16> ResultMask;
5510 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5511 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5513 for (unsigned j = 0; j != BytesPerElement; ++j)
5514 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5518 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5519 &ResultMask[0], ResultMask.size());
5520 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5523 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5524 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5525 /// information about the intrinsic.
5526 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5528 unsigned IntrinsicID =
5529 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5532 switch (IntrinsicID) {
5533 default: return false;
5534 // Comparison predicates.
5535 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5536 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5537 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5538 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5539 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5540 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5541 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5542 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5543 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5544 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5545 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5546 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5547 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5549 // Normal Comparisons.
5550 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5551 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5552 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5553 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5554 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5555 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5556 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5557 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5558 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5559 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5560 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5561 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5562 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5567 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5568 /// lower, do it, otherwise return null.
5569 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5570 SelectionDAG &DAG) const {
5571 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5572 // opcode number of the comparison.
5576 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5577 return SDValue(); // Don't custom lower most intrinsics.
5579 // If this is a non-dot comparison, make the VCMP node and we are done.
5581 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5582 Op.getOperand(1), Op.getOperand(2),
5583 DAG.getConstant(CompareOpc, MVT::i32));
5584 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5587 // Create the PPCISD altivec 'dot' comparison node.
5589 Op.getOperand(2), // LHS
5590 Op.getOperand(3), // RHS
5591 DAG.getConstant(CompareOpc, MVT::i32)
5593 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5594 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5596 // Now that we have the comparison, emit a copy from the CR to a GPR.
5597 // This is flagged to the above dot comparison.
5598 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5599 DAG.getRegister(PPC::CR6, MVT::i32),
5600 CompNode.getValue(1));
5602 // Unpack the result based on how the target uses it.
5603 unsigned BitNo; // Bit # of CR6.
5604 bool InvertBit; // Invert result?
5605 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5606 default: // Can't happen, don't crash on invalid number though.
5607 case 0: // Return the value of the EQ bit of CR6.
5608 BitNo = 0; InvertBit = false;
5610 case 1: // Return the inverted value of the EQ bit of CR6.
5611 BitNo = 0; InvertBit = true;
5613 case 2: // Return the value of the LT bit of CR6.
5614 BitNo = 2; InvertBit = false;
5616 case 3: // Return the inverted value of the LT bit of CR6.
5617 BitNo = 2; InvertBit = true;
5621 // Shift the bit into the low position.
5622 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5623 DAG.getConstant(8-(3-BitNo), MVT::i32));
5625 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5626 DAG.getConstant(1, MVT::i32));
5628 // If we are supposed to, toggle the bit.
5630 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5631 DAG.getConstant(1, MVT::i32));
5635 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5636 SelectionDAG &DAG) const {
5638 // Create a stack slot that is 16-byte aligned.
5639 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5640 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5641 EVT PtrVT = getPointerTy();
5642 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5644 // Store the input value into Value#0 of the stack slot.
5645 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5646 Op.getOperand(0), FIdx, MachinePointerInfo(),
5649 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5650 false, false, false, 0);
5653 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5655 if (Op.getValueType() == MVT::v4i32) {
5656 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5658 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5659 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5661 SDValue RHSSwap = // = vrlw RHS, 16
5662 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5664 // Shrinkify inputs to v8i16.
5665 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5666 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5667 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5669 // Low parts multiplied together, generating 32-bit results (we ignore the
5671 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5672 LHS, RHS, DAG, dl, MVT::v4i32);
5674 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5675 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5676 // Shift the high parts up 16 bits.
5677 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5679 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5680 } else if (Op.getValueType() == MVT::v8i16) {
5681 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5683 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5685 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5686 LHS, RHS, Zero, DAG, dl);
5687 } else if (Op.getValueType() == MVT::v16i8) {
5688 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5690 // Multiply the even 8-bit parts, producing 16-bit sums.
5691 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5692 LHS, RHS, DAG, dl, MVT::v8i16);
5693 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5695 // Multiply the odd 8-bit parts, producing 16-bit sums.
5696 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5697 LHS, RHS, DAG, dl, MVT::v8i16);
5698 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5700 // Merge the results together.
5702 for (unsigned i = 0; i != 8; ++i) {
5704 Ops[i*2+1] = 2*i+1+16;
5706 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5708 llvm_unreachable("Unknown mul to lower!");
5712 /// LowerOperation - Provide custom lowering hooks for some operations.
5714 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5715 switch (Op.getOpcode()) {
5716 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5717 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5718 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5719 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5720 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5721 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5722 case ISD::SETCC: return LowerSETCC(Op, DAG);
5723 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5724 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5726 return LowerVASTART(Op, DAG, PPCSubTarget);
5729 return LowerVAARG(Op, DAG, PPCSubTarget);
5732 return LowerVACOPY(Op, DAG, PPCSubTarget);
5734 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5735 case ISD::DYNAMIC_STACKALLOC:
5736 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5738 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5739 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5741 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5742 case ISD::FP_TO_UINT:
5743 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5745 case ISD::UINT_TO_FP:
5746 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5747 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5749 // Lower 64-bit shifts.
5750 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5751 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5752 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5754 // Vector-related lowering.
5755 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5756 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5757 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5758 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5759 case ISD::MUL: return LowerMUL(Op, DAG);
5761 // For counter-based loop handling.
5762 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5764 // Frame & Return address.
5765 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5766 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5770 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5771 SmallVectorImpl<SDValue>&Results,
5772 SelectionDAG &DAG) const {
5773 const TargetMachine &TM = getTargetMachine();
5775 switch (N->getOpcode()) {
5777 llvm_unreachable("Do not know how to custom type legalize this operation!");
5778 case ISD::INTRINSIC_W_CHAIN: {
5779 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
5780 Intrinsic::ppc_is_decremented_ctr_nonzero)
5783 assert(N->getValueType(0) == MVT::i1 &&
5784 "Unexpected result type for CTR decrement intrinsic");
5785 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
5786 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5787 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
5790 Results.push_back(NewInt);
5791 Results.push_back(NewInt.getValue(1));
5795 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5796 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5799 EVT VT = N->getValueType(0);
5801 if (VT == MVT::i64) {
5802 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5804 Results.push_back(NewNode);
5805 Results.push_back(NewNode.getValue(1));
5809 case ISD::FP_ROUND_INREG: {
5810 assert(N->getValueType(0) == MVT::ppcf128);
5811 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5812 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5813 MVT::f64, N->getOperand(0),
5814 DAG.getIntPtrConstant(0));
5815 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5816 MVT::f64, N->getOperand(0),
5817 DAG.getIntPtrConstant(1));
5819 // Add the two halves of the long double in round-to-zero mode.
5820 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5822 // We know the low half is about to be thrown away, so just use something
5824 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5828 case ISD::FP_TO_SINT:
5829 // LowerFP_TO_INT() can only handle f32 and f64.
5830 if (N->getOperand(0).getValueType() == MVT::ppcf128)
5832 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5838 //===----------------------------------------------------------------------===//
5839 // Other Lowering Code
5840 //===----------------------------------------------------------------------===//
5843 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5844 bool is64bit, unsigned BinOpcode) const {
5845 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5846 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5848 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5849 MachineFunction *F = BB->getParent();
5850 MachineFunction::iterator It = BB;
5853 unsigned dest = MI->getOperand(0).getReg();
5854 unsigned ptrA = MI->getOperand(1).getReg();
5855 unsigned ptrB = MI->getOperand(2).getReg();
5856 unsigned incr = MI->getOperand(3).getReg();
5857 DebugLoc dl = MI->getDebugLoc();
5859 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5860 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5861 F->insert(It, loopMBB);
5862 F->insert(It, exitMBB);
5863 exitMBB->splice(exitMBB->begin(), BB,
5864 llvm::next(MachineBasicBlock::iterator(MI)),
5866 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5868 MachineRegisterInfo &RegInfo = F->getRegInfo();
5869 unsigned TmpReg = (!BinOpcode) ? incr :
5870 RegInfo.createVirtualRegister(
5871 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5872 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5876 // fallthrough --> loopMBB
5877 BB->addSuccessor(loopMBB);
5880 // l[wd]arx dest, ptr
5881 // add r0, dest, incr
5882 // st[wd]cx. r0, ptr
5884 // fallthrough --> exitMBB
5886 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5887 .addReg(ptrA).addReg(ptrB);
5889 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5890 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5891 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5892 BuildMI(BB, dl, TII->get(PPC::BCC))
5893 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5894 BB->addSuccessor(loopMBB);
5895 BB->addSuccessor(exitMBB);
5904 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5905 MachineBasicBlock *BB,
5906 bool is8bit, // operation
5907 unsigned BinOpcode) const {
5908 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5909 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5910 // In 64 bit mode we have to use 64 bits for addresses, even though the
5911 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5912 // registers without caring whether they're 32 or 64, but here we're
5913 // doing actual arithmetic on the addresses.
5914 bool is64bit = PPCSubTarget.isPPC64();
5915 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5917 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5918 MachineFunction *F = BB->getParent();
5919 MachineFunction::iterator It = BB;
5922 unsigned dest = MI->getOperand(0).getReg();
5923 unsigned ptrA = MI->getOperand(1).getReg();
5924 unsigned ptrB = MI->getOperand(2).getReg();
5925 unsigned incr = MI->getOperand(3).getReg();
5926 DebugLoc dl = MI->getDebugLoc();
5928 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5929 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5930 F->insert(It, loopMBB);
5931 F->insert(It, exitMBB);
5932 exitMBB->splice(exitMBB->begin(), BB,
5933 llvm::next(MachineBasicBlock::iterator(MI)),
5935 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5937 MachineRegisterInfo &RegInfo = F->getRegInfo();
5938 const TargetRegisterClass *RC =
5939 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5940 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5941 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5942 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5943 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5944 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5945 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5946 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5947 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5948 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5949 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5950 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5951 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5953 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5957 // fallthrough --> loopMBB
5958 BB->addSuccessor(loopMBB);
5960 // The 4-byte load must be aligned, while a char or short may be
5961 // anywhere in the word. Hence all this nasty bookkeeping code.
5962 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5963 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5964 // xori shift, shift1, 24 [16]
5965 // rlwinm ptr, ptr1, 0, 0, 29
5966 // slw incr2, incr, shift
5967 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5968 // slw mask, mask2, shift
5970 // lwarx tmpDest, ptr
5971 // add tmp, tmpDest, incr2
5972 // andc tmp2, tmpDest, mask
5973 // and tmp3, tmp, mask
5974 // or tmp4, tmp3, tmp2
5977 // fallthrough --> exitMBB
5978 // srw dest, tmpDest, shift
5979 if (ptrA != ZeroReg) {
5980 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5981 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5982 .addReg(ptrA).addReg(ptrB);
5986 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5987 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5988 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5989 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5991 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5992 .addReg(Ptr1Reg).addImm(0).addImm(61);
5994 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5995 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5996 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5997 .addReg(incr).addReg(ShiftReg);
5999 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6001 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6002 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6004 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6005 .addReg(Mask2Reg).addReg(ShiftReg);
6008 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6009 .addReg(ZeroReg).addReg(PtrReg);
6011 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6012 .addReg(Incr2Reg).addReg(TmpDestReg);
6013 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6014 .addReg(TmpDestReg).addReg(MaskReg);
6015 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6016 .addReg(TmpReg).addReg(MaskReg);
6017 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6018 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6019 BuildMI(BB, dl, TII->get(PPC::STWCX))
6020 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6021 BuildMI(BB, dl, TII->get(PPC::BCC))
6022 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6023 BB->addSuccessor(loopMBB);
6024 BB->addSuccessor(exitMBB);
6029 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6034 llvm::MachineBasicBlock*
6035 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6036 MachineBasicBlock *MBB) const {
6037 DebugLoc DL = MI->getDebugLoc();
6038 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6040 MachineFunction *MF = MBB->getParent();
6041 MachineRegisterInfo &MRI = MF->getRegInfo();
6043 const BasicBlock *BB = MBB->getBasicBlock();
6044 MachineFunction::iterator I = MBB;
6048 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6049 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6051 unsigned DstReg = MI->getOperand(0).getReg();
6052 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6053 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6054 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6055 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6057 MVT PVT = getPointerTy();
6058 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6059 "Invalid Pointer Size!");
6060 // For v = setjmp(buf), we generate
6063 // SjLjSetup mainMBB
6069 // buf[LabelOffset] = LR
6073 // v = phi(main, restore)
6076 MachineBasicBlock *thisMBB = MBB;
6077 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6078 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6079 MF->insert(I, mainMBB);
6080 MF->insert(I, sinkMBB);
6082 MachineInstrBuilder MIB;
6084 // Transfer the remainder of BB and its successor edges to sinkMBB.
6085 sinkMBB->splice(sinkMBB->begin(), MBB,
6086 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6087 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6089 // Note that the structure of the jmp_buf used here is not compatible
6090 // with that used by libc, and is not designed to be. Specifically, it
6091 // stores only those 'reserved' registers that LLVM does not otherwise
6092 // understand how to spill. Also, by convention, by the time this
6093 // intrinsic is called, Clang has already stored the frame address in the
6094 // first slot of the buffer and stack address in the third. Following the
6095 // X86 target code, we'll store the jump address in the second slot. We also
6096 // need to save the TOC pointer (R2) to handle jumps between shared
6097 // libraries, and that will be stored in the fourth slot. The thread
6098 // identifier (R13) is not affected.
6101 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6102 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6103 const int64_t BPOffset = 4 * PVT.getStoreSize();
6105 // Prepare IP either in reg.
6106 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6107 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6108 unsigned BufReg = MI->getOperand(1).getReg();
6110 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6111 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6115 MIB.setMemRefs(MMOBegin, MMOEnd);
6118 // Naked functions never have a base pointer, and so we use r1. For all
6119 // other functions, this decision must be delayed until during PEI.
6121 if (MF->getFunction()->getAttributes().hasAttribute(
6122 AttributeSet::FunctionIndex, Attribute::Naked))
6123 BaseReg = PPCSubTarget.isPPC64() ? PPC::X1 : PPC::R1;
6125 BaseReg = PPCSubTarget.isPPC64() ? PPC::BP8 : PPC::BP;
6127 MIB = BuildMI(*thisMBB, MI, DL,
6128 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6132 MIB.setMemRefs(MMOBegin, MMOEnd);
6135 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6136 const PPCRegisterInfo *TRI =
6137 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6138 MIB.addRegMask(TRI->getNoPreservedMask());
6140 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6142 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6144 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6146 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6147 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6151 MIB = BuildMI(mainMBB, DL,
6152 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6155 if (PPCSubTarget.isPPC64()) {
6156 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6158 .addImm(LabelOffset)
6161 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6163 .addImm(LabelOffset)
6167 MIB.setMemRefs(MMOBegin, MMOEnd);
6169 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6170 mainMBB->addSuccessor(sinkMBB);
6173 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6174 TII->get(PPC::PHI), DstReg)
6175 .addReg(mainDstReg).addMBB(mainMBB)
6176 .addReg(restoreDstReg).addMBB(thisMBB);
6178 MI->eraseFromParent();
6183 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6184 MachineBasicBlock *MBB) const {
6185 DebugLoc DL = MI->getDebugLoc();
6186 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6188 MachineFunction *MF = MBB->getParent();
6189 MachineRegisterInfo &MRI = MF->getRegInfo();
6192 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6193 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6195 MVT PVT = getPointerTy();
6196 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6197 "Invalid Pointer Size!");
6199 const TargetRegisterClass *RC =
6200 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6201 unsigned Tmp = MRI.createVirtualRegister(RC);
6202 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6203 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6204 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6205 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6207 MachineInstrBuilder MIB;
6209 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6210 const int64_t SPOffset = 2 * PVT.getStoreSize();
6211 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6212 const int64_t BPOffset = 4 * PVT.getStoreSize();
6214 unsigned BufReg = MI->getOperand(0).getReg();
6216 // Reload FP (the jumped-to function may not have had a
6217 // frame pointer, and if so, then its r31 will be restored
6219 if (PVT == MVT::i64) {
6220 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6224 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6228 MIB.setMemRefs(MMOBegin, MMOEnd);
6231 if (PVT == MVT::i64) {
6232 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6233 .addImm(LabelOffset)
6236 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6237 .addImm(LabelOffset)
6240 MIB.setMemRefs(MMOBegin, MMOEnd);
6243 if (PVT == MVT::i64) {
6244 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6248 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6252 MIB.setMemRefs(MMOBegin, MMOEnd);
6255 if (PVT == MVT::i64) {
6256 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6260 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6264 MIB.setMemRefs(MMOBegin, MMOEnd);
6267 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6268 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6272 MIB.setMemRefs(MMOBegin, MMOEnd);
6276 BuildMI(*MBB, MI, DL,
6277 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6278 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6280 MI->eraseFromParent();
6285 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6286 MachineBasicBlock *BB) const {
6287 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6288 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6289 return emitEHSjLjSetJmp(MI, BB);
6290 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6291 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6292 return emitEHSjLjLongJmp(MI, BB);
6295 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6297 // To "insert" these instructions we actually have to insert their
6298 // control-flow patterns.
6299 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6300 MachineFunction::iterator It = BB;
6303 MachineFunction *F = BB->getParent();
6305 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6306 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6307 SmallVector<MachineOperand, 2> Cond;
6308 Cond.push_back(MI->getOperand(4));
6309 Cond.push_back(MI->getOperand(1));
6311 DebugLoc dl = MI->getDebugLoc();
6312 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6313 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6314 Cond, MI->getOperand(2).getReg(),
6315 MI->getOperand(3).getReg());
6316 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6317 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6318 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6319 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6320 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6323 // The incoming instruction knows the destination vreg to set, the
6324 // condition code register to branch on, the true/false values to
6325 // select between, and a branch opcode to use.
6330 // cmpTY ccX, r1, r2
6332 // fallthrough --> copy0MBB
6333 MachineBasicBlock *thisMBB = BB;
6334 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6335 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6336 unsigned SelectPred = MI->getOperand(4).getImm();
6337 DebugLoc dl = MI->getDebugLoc();
6338 F->insert(It, copy0MBB);
6339 F->insert(It, sinkMBB);
6341 // Transfer the remainder of BB and its successor edges to sinkMBB.
6342 sinkMBB->splice(sinkMBB->begin(), BB,
6343 llvm::next(MachineBasicBlock::iterator(MI)),
6345 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6347 // Next, add the true and fallthrough blocks as its successors.
6348 BB->addSuccessor(copy0MBB);
6349 BB->addSuccessor(sinkMBB);
6351 BuildMI(BB, dl, TII->get(PPC::BCC))
6352 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6355 // %FalseValue = ...
6356 // # fallthrough to sinkMBB
6359 // Update machine-CFG edges
6360 BB->addSuccessor(sinkMBB);
6363 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6366 BuildMI(*BB, BB->begin(), dl,
6367 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6368 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6369 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6371 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6372 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6373 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6374 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6375 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6376 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6377 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6378 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6380 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6381 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6382 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6383 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6384 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6385 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6386 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6387 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6389 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6390 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6391 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6392 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6393 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6394 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6395 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6396 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6398 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6399 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6400 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6401 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6402 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6403 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6404 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6405 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6407 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6408 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6409 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6410 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6411 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6412 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6413 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6414 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6416 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6417 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6418 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6419 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6420 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6421 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6422 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6423 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6425 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6426 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6427 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6428 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6429 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6430 BB = EmitAtomicBinary(MI, BB, false, 0);
6431 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6432 BB = EmitAtomicBinary(MI, BB, true, 0);
6434 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6435 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6436 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6438 unsigned dest = MI->getOperand(0).getReg();
6439 unsigned ptrA = MI->getOperand(1).getReg();
6440 unsigned ptrB = MI->getOperand(2).getReg();
6441 unsigned oldval = MI->getOperand(3).getReg();
6442 unsigned newval = MI->getOperand(4).getReg();
6443 DebugLoc dl = MI->getDebugLoc();
6445 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6446 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6447 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6448 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6449 F->insert(It, loop1MBB);
6450 F->insert(It, loop2MBB);
6451 F->insert(It, midMBB);
6452 F->insert(It, exitMBB);
6453 exitMBB->splice(exitMBB->begin(), BB,
6454 llvm::next(MachineBasicBlock::iterator(MI)),
6456 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6460 // fallthrough --> loopMBB
6461 BB->addSuccessor(loop1MBB);
6464 // l[wd]arx dest, ptr
6465 // cmp[wd] dest, oldval
6468 // st[wd]cx. newval, ptr
6472 // st[wd]cx. dest, ptr
6475 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6476 .addReg(ptrA).addReg(ptrB);
6477 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6478 .addReg(oldval).addReg(dest);
6479 BuildMI(BB, dl, TII->get(PPC::BCC))
6480 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6481 BB->addSuccessor(loop2MBB);
6482 BB->addSuccessor(midMBB);
6485 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6486 .addReg(newval).addReg(ptrA).addReg(ptrB);
6487 BuildMI(BB, dl, TII->get(PPC::BCC))
6488 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6489 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6490 BB->addSuccessor(loop1MBB);
6491 BB->addSuccessor(exitMBB);
6494 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6495 .addReg(dest).addReg(ptrA).addReg(ptrB);
6496 BB->addSuccessor(exitMBB);
6501 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6502 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6503 // We must use 64-bit registers for addresses when targeting 64-bit,
6504 // since we're actually doing arithmetic on them. Other registers
6506 bool is64bit = PPCSubTarget.isPPC64();
6507 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6509 unsigned dest = MI->getOperand(0).getReg();
6510 unsigned ptrA = MI->getOperand(1).getReg();
6511 unsigned ptrB = MI->getOperand(2).getReg();
6512 unsigned oldval = MI->getOperand(3).getReg();
6513 unsigned newval = MI->getOperand(4).getReg();
6514 DebugLoc dl = MI->getDebugLoc();
6516 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6517 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6518 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6519 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6520 F->insert(It, loop1MBB);
6521 F->insert(It, loop2MBB);
6522 F->insert(It, midMBB);
6523 F->insert(It, exitMBB);
6524 exitMBB->splice(exitMBB->begin(), BB,
6525 llvm::next(MachineBasicBlock::iterator(MI)),
6527 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6529 MachineRegisterInfo &RegInfo = F->getRegInfo();
6530 const TargetRegisterClass *RC =
6531 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6532 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6533 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6534 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6535 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6536 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6537 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6538 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6539 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6540 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6541 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6542 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6543 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6544 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6545 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6547 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6548 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6551 // fallthrough --> loopMBB
6552 BB->addSuccessor(loop1MBB);
6554 // The 4-byte load must be aligned, while a char or short may be
6555 // anywhere in the word. Hence all this nasty bookkeeping code.
6556 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6557 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6558 // xori shift, shift1, 24 [16]
6559 // rlwinm ptr, ptr1, 0, 0, 29
6560 // slw newval2, newval, shift
6561 // slw oldval2, oldval,shift
6562 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6563 // slw mask, mask2, shift
6564 // and newval3, newval2, mask
6565 // and oldval3, oldval2, mask
6567 // lwarx tmpDest, ptr
6568 // and tmp, tmpDest, mask
6569 // cmpw tmp, oldval3
6572 // andc tmp2, tmpDest, mask
6573 // or tmp4, tmp2, newval3
6578 // stwcx. tmpDest, ptr
6580 // srw dest, tmpDest, shift
6581 if (ptrA != ZeroReg) {
6582 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6583 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6584 .addReg(ptrA).addReg(ptrB);
6588 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6589 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6590 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6591 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6593 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6594 .addReg(Ptr1Reg).addImm(0).addImm(61);
6596 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6597 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6598 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6599 .addReg(newval).addReg(ShiftReg);
6600 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6601 .addReg(oldval).addReg(ShiftReg);
6603 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6605 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6606 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6607 .addReg(Mask3Reg).addImm(65535);
6609 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6610 .addReg(Mask2Reg).addReg(ShiftReg);
6611 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6612 .addReg(NewVal2Reg).addReg(MaskReg);
6613 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6614 .addReg(OldVal2Reg).addReg(MaskReg);
6617 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6618 .addReg(ZeroReg).addReg(PtrReg);
6619 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6620 .addReg(TmpDestReg).addReg(MaskReg);
6621 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6622 .addReg(TmpReg).addReg(OldVal3Reg);
6623 BuildMI(BB, dl, TII->get(PPC::BCC))
6624 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6625 BB->addSuccessor(loop2MBB);
6626 BB->addSuccessor(midMBB);
6629 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6630 .addReg(TmpDestReg).addReg(MaskReg);
6631 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6632 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6633 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6634 .addReg(ZeroReg).addReg(PtrReg);
6635 BuildMI(BB, dl, TII->get(PPC::BCC))
6636 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6637 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6638 BB->addSuccessor(loop1MBB);
6639 BB->addSuccessor(exitMBB);
6642 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6643 .addReg(ZeroReg).addReg(PtrReg);
6644 BB->addSuccessor(exitMBB);
6649 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6651 } else if (MI->getOpcode() == PPC::FADDrtz) {
6652 // This pseudo performs an FADD with rounding mode temporarily forced
6653 // to round-to-zero. We emit this via custom inserter since the FPSCR
6654 // is not modeled at the SelectionDAG level.
6655 unsigned Dest = MI->getOperand(0).getReg();
6656 unsigned Src1 = MI->getOperand(1).getReg();
6657 unsigned Src2 = MI->getOperand(2).getReg();
6658 DebugLoc dl = MI->getDebugLoc();
6660 MachineRegisterInfo &RegInfo = F->getRegInfo();
6661 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6663 // Save FPSCR value.
6664 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6666 // Set rounding mode to round-to-zero.
6667 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6668 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6670 // Perform addition.
6671 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6673 // Restore FPSCR value.
6674 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6676 llvm_unreachable("Unexpected instr type to insert");
6679 MI->eraseFromParent(); // The pseudo instruction is gone now.
6683 //===----------------------------------------------------------------------===//
6684 // Target Optimization Hooks
6685 //===----------------------------------------------------------------------===//
6687 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6688 DAGCombinerInfo &DCI) const {
6689 if (DCI.isAfterLegalizeVectorOps())
6692 EVT VT = Op.getValueType();
6694 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6695 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6696 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6698 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6699 // For the reciprocal, we need to find the zero of the function:
6700 // F(X) = A X - 1 [which has a zero at X = 1/A]
6702 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6703 // does not require additional intermediate precision]
6705 // Convergence is quadratic, so we essentially double the number of digits
6706 // correct after every iteration. The minimum architected relative
6707 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6708 // 23 digits and double has 52 digits.
6709 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6710 if (VT.getScalarType() == MVT::f64)
6713 SelectionDAG &DAG = DCI.DAG;
6717 DAG.getConstantFP(1.0, VT.getScalarType());
6718 if (VT.isVector()) {
6719 assert(VT.getVectorNumElements() == 4 &&
6720 "Unknown vector type");
6721 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6722 FPOne, FPOne, FPOne, FPOne);
6725 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6726 DCI.AddToWorklist(Est.getNode());
6728 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6729 for (int i = 0; i < Iterations; ++i) {
6730 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6731 DCI.AddToWorklist(NewEst.getNode());
6733 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6734 DCI.AddToWorklist(NewEst.getNode());
6736 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6737 DCI.AddToWorklist(NewEst.getNode());
6739 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6740 DCI.AddToWorklist(Est.getNode());
6749 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6750 DAGCombinerInfo &DCI) const {
6751 if (DCI.isAfterLegalizeVectorOps())
6754 EVT VT = Op.getValueType();
6756 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6757 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6758 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6760 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6761 // For the reciprocal sqrt, we need to find the zero of the function:
6762 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6764 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6765 // As a result, we precompute A/2 prior to the iteration loop.
6767 // Convergence is quadratic, so we essentially double the number of digits
6768 // correct after every iteration. The minimum architected relative
6769 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6770 // 23 digits and double has 52 digits.
6771 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6772 if (VT.getScalarType() == MVT::f64)
6775 SelectionDAG &DAG = DCI.DAG;
6778 SDValue FPThreeHalves =
6779 DAG.getConstantFP(1.5, VT.getScalarType());
6780 if (VT.isVector()) {
6781 assert(VT.getVectorNumElements() == 4 &&
6782 "Unknown vector type");
6783 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6784 FPThreeHalves, FPThreeHalves,
6785 FPThreeHalves, FPThreeHalves);
6788 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6789 DCI.AddToWorklist(Est.getNode());
6791 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6792 // this entire sequence requires only one FP constant.
6793 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6794 DCI.AddToWorklist(HalfArg.getNode());
6796 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6797 DCI.AddToWorklist(HalfArg.getNode());
6799 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6800 for (int i = 0; i < Iterations; ++i) {
6801 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6802 DCI.AddToWorklist(NewEst.getNode());
6804 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6805 DCI.AddToWorklist(NewEst.getNode());
6807 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6808 DCI.AddToWorklist(NewEst.getNode());
6810 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6811 DCI.AddToWorklist(Est.getNode());
6820 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
6821 // not enforce equality of the chain operands.
6822 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
6823 unsigned Bytes, int Dist,
6824 SelectionDAG &DAG) {
6825 EVT VT = LS->getMemoryVT();
6826 if (VT.getSizeInBits() / 8 != Bytes)
6829 SDValue Loc = LS->getBasePtr();
6830 SDValue BaseLoc = Base->getBasePtr();
6831 if (Loc.getOpcode() == ISD::FrameIndex) {
6832 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6834 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6835 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
6836 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
6837 int FS = MFI->getObjectSize(FI);
6838 int BFS = MFI->getObjectSize(BFI);
6839 if (FS != BFS || FS != (int)Bytes) return false;
6840 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
6844 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
6845 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
6848 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6849 const GlobalValue *GV1 = NULL;
6850 const GlobalValue *GV2 = NULL;
6851 int64_t Offset1 = 0;
6852 int64_t Offset2 = 0;
6853 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
6854 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
6855 if (isGA1 && isGA2 && GV1 == GV2)
6856 return Offset1 == (Offset2 + Dist*Bytes);
6860 // Return true is there is a nearyby consecutive load to the one provided
6861 // (regardless of alignment). We search up and down the chain, looking though
6862 // token factors and other loads (but nothing else). As a result, a true
6863 // results indicates that it is safe to create a new consecutive load adjacent
6864 // to the load provided.
6865 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
6866 SDValue Chain = LD->getChain();
6867 EVT VT = LD->getMemoryVT();
6869 SmallSet<SDNode *, 16> LoadRoots;
6870 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
6871 SmallSet<SDNode *, 16> Visited;
6873 // First, search up the chain, branching to follow all token-factor operands.
6874 // If we find a consecutive load, then we're done, otherwise, record all
6875 // nodes just above the top-level loads and token factors.
6876 while (!Queue.empty()) {
6877 SDNode *ChainNext = Queue.pop_back_val();
6878 if (!Visited.insert(ChainNext))
6881 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
6882 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6885 if (!Visited.count(ChainLD->getChain().getNode()))
6886 Queue.push_back(ChainLD->getChain().getNode());
6887 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
6888 for (SDNode::op_iterator O = ChainNext->op_begin(),
6889 OE = ChainNext->op_end(); O != OE; ++O)
6890 if (!Visited.count(O->getNode()))
6891 Queue.push_back(O->getNode());
6893 LoadRoots.insert(ChainNext);
6896 // Second, search down the chain, starting from the top-level nodes recorded
6897 // in the first phase. These top-level nodes are the nodes just above all
6898 // loads and token factors. Starting with their uses, recursively look though
6899 // all loads (just the chain uses) and token factors to find a consecutive
6904 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
6905 IE = LoadRoots.end(); I != IE; ++I) {
6906 Queue.push_back(*I);
6908 while (!Queue.empty()) {
6909 SDNode *LoadRoot = Queue.pop_back_val();
6910 if (!Visited.insert(LoadRoot))
6913 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
6914 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6917 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
6918 UE = LoadRoot->use_end(); UI != UE; ++UI)
6919 if (((isa<LoadSDNode>(*UI) &&
6920 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
6921 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
6922 Queue.push_back(*UI);
6929 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6930 DAGCombinerInfo &DCI) const {
6931 const TargetMachine &TM = getTargetMachine();
6932 SelectionDAG &DAG = DCI.DAG;
6934 switch (N->getOpcode()) {
6937 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6938 if (C->isNullValue()) // 0 << V -> 0.
6939 return N->getOperand(0);
6943 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6944 if (C->isNullValue()) // 0 >>u V -> 0.
6945 return N->getOperand(0);
6949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6950 if (C->isNullValue() || // 0 >>s V -> 0.
6951 C->isAllOnesValue()) // -1 >>s V -> -1.
6952 return N->getOperand(0);
6956 assert(TM.Options.UnsafeFPMath &&
6957 "Reciprocal estimates require UnsafeFPMath");
6959 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
6961 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
6962 if (RV.getNode() != 0) {
6963 DCI.AddToWorklist(RV.getNode());
6964 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6965 N->getOperand(0), RV);
6967 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
6968 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6970 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6972 if (RV.getNode() != 0) {
6973 DCI.AddToWorklist(RV.getNode());
6974 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
6975 N->getValueType(0), RV);
6976 DCI.AddToWorklist(RV.getNode());
6977 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6978 N->getOperand(0), RV);
6980 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
6981 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6983 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6985 if (RV.getNode() != 0) {
6986 DCI.AddToWorklist(RV.getNode());
6987 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
6988 N->getValueType(0), RV,
6989 N->getOperand(1).getOperand(1));
6990 DCI.AddToWorklist(RV.getNode());
6991 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6992 N->getOperand(0), RV);
6996 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
6997 if (RV.getNode() != 0) {
6998 DCI.AddToWorklist(RV.getNode());
6999 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7000 N->getOperand(0), RV);
7006 assert(TM.Options.UnsafeFPMath &&
7007 "Reciprocal estimates require UnsafeFPMath");
7009 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7011 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7012 if (RV.getNode() != 0) {
7013 DCI.AddToWorklist(RV.getNode());
7014 RV = DAGCombineFastRecip(RV, DCI);
7015 if (RV.getNode() != 0)
7021 case ISD::SINT_TO_FP:
7022 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
7023 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7024 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
7025 // We allow the src/dst to be either f32/f64, but the intermediate
7026 // type must be i64.
7027 if (N->getOperand(0).getValueType() == MVT::i64 &&
7028 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7029 SDValue Val = N->getOperand(0).getOperand(0);
7030 if (Val.getValueType() == MVT::f32) {
7031 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7032 DCI.AddToWorklist(Val.getNode());
7035 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7036 DCI.AddToWorklist(Val.getNode());
7037 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7038 DCI.AddToWorklist(Val.getNode());
7039 if (N->getValueType(0) == MVT::f32) {
7040 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7041 DAG.getIntPtrConstant(0));
7042 DCI.AddToWorklist(Val.getNode());
7045 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7046 // If the intermediate type is i32, we can avoid the load/store here
7053 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7054 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7055 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7056 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7057 N->getOperand(1).getValueType() == MVT::i32 &&
7058 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7059 SDValue Val = N->getOperand(1).getOperand(0);
7060 if (Val.getValueType() == MVT::f32) {
7061 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7062 DCI.AddToWorklist(Val.getNode());
7064 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7065 DCI.AddToWorklist(Val.getNode());
7068 N->getOperand(0), Val, N->getOperand(2),
7069 DAG.getValueType(N->getOperand(1).getValueType())
7072 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
7073 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7074 cast<StoreSDNode>(N)->getMemoryVT(),
7075 cast<StoreSDNode>(N)->getMemOperand());
7076 DCI.AddToWorklist(Val.getNode());
7080 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
7081 if (cast<StoreSDNode>(N)->isUnindexed() &&
7082 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7083 N->getOperand(1).getNode()->hasOneUse() &&
7084 (N->getOperand(1).getValueType() == MVT::i32 ||
7085 N->getOperand(1).getValueType() == MVT::i16 ||
7086 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7087 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7088 N->getOperand(1).getValueType() == MVT::i64))) {
7089 SDValue BSwapOp = N->getOperand(1).getOperand(0);
7090 // Do an any-extend to 32-bits if this is a half-word input.
7091 if (BSwapOp.getValueType() == MVT::i16)
7092 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7095 N->getOperand(0), BSwapOp, N->getOperand(2),
7096 DAG.getValueType(N->getOperand(1).getValueType())
7099 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7100 Ops, array_lengthof(Ops),
7101 cast<StoreSDNode>(N)->getMemoryVT(),
7102 cast<StoreSDNode>(N)->getMemOperand());
7106 LoadSDNode *LD = cast<LoadSDNode>(N);
7107 EVT VT = LD->getValueType(0);
7108 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
7109 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
7110 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7111 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
7112 DCI.getDAGCombineLevel() == AfterLegalizeTypes &&
7113 LD->getAlignment() < ABIAlignment) {
7114 // This is a type-legal unaligned Altivec load.
7115 SDValue Chain = LD->getChain();
7116 SDValue Ptr = LD->getBasePtr();
7118 // This implements the loading of unaligned vectors as described in
7119 // the venerable Apple Velocity Engine overview. Specifically:
7120 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
7121 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
7123 // The general idea is to expand a sequence of one or more unaligned
7124 // loads into a alignment-based permutation-control instruction (lvsl),
7125 // a series of regular vector loads (which always truncate their
7126 // input address to an aligned address), and a series of permutations.
7127 // The results of these permutations are the requested loaded values.
7128 // The trick is that the last "extra" load is not taken from the address
7129 // you might suspect (sizeof(vector) bytes after the last requested
7130 // load), but rather sizeof(vector) - 1 bytes after the last
7131 // requested vector. The point of this is to avoid a page fault if the
7132 // base address happend to be aligned. This works because if the base
7133 // address is aligned, then adding less than a full vector length will
7134 // cause the last vector in the sequence to be (re)loaded. Otherwise,
7135 // the next vector will be fetched as you might suspect was necessary.
7137 // We might be able to reuse the permutation generation from
7138 // a different base address offset from this one by an aligned amount.
7139 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
7140 // optimization later.
7141 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
7142 DAG, dl, MVT::v16i8);
7144 // Refine the alignment of the original load (a "new" load created here
7145 // which was identical to the first except for the alignment would be
7146 // merged with the existing node regardless).
7147 MachineFunction &MF = DAG.getMachineFunction();
7148 MachineMemOperand *MMO =
7149 MF.getMachineMemOperand(LD->getPointerInfo(),
7150 LD->getMemOperand()->getFlags(),
7151 LD->getMemoryVT().getStoreSize(),
7153 LD->refineAlignment(MMO);
7154 SDValue BaseLoad = SDValue(LD, 0);
7156 // Note that the value of IncOffset (which is provided to the next
7157 // load's pointer info offset value, and thus used to calculate the
7158 // alignment), and the value of IncValue (which is actually used to
7159 // increment the pointer value) are different! This is because we
7160 // require the next load to appear to be aligned, even though it
7161 // is actually offset from the base pointer by a lesser amount.
7162 int IncOffset = VT.getSizeInBits() / 8;
7163 int IncValue = IncOffset;
7165 // Walk (both up and down) the chain looking for another load at the real
7166 // (aligned) offset (the alignment of the other load does not matter in
7167 // this case). If found, then do not use the offset reduction trick, as
7168 // that will prevent the loads from being later combined (as they would
7169 // otherwise be duplicates).
7170 if (!findConsecutiveLoad(LD, DAG))
7173 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
7174 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7177 DAG.getLoad(VT, dl, Chain, Ptr,
7178 LD->getPointerInfo().getWithOffset(IncOffset),
7179 LD->isVolatile(), LD->isNonTemporal(),
7180 LD->isInvariant(), ABIAlignment);
7182 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7183 BaseLoad.getValue(1), ExtraLoad.getValue(1));
7185 if (BaseLoad.getValueType() != MVT::v4i32)
7186 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7188 if (ExtraLoad.getValueType() != MVT::v4i32)
7189 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7191 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
7192 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
7194 if (VT != MVT::v4i32)
7195 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7197 // Now we need to be really careful about how we update the users of the
7198 // original load. We cannot just call DCI.CombineTo (or
7199 // DAG.ReplaceAllUsesWith for that matter), because the load still has
7200 // uses created here (the permutation for example) that need to stay.
7201 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7203 SDUse &Use = UI.getUse();
7205 // Note: BaseLoad is checked here because it might not be N, but a
7207 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
7208 User == TF.getNode() || Use.getResNo() > 1) {
7213 SDValue To = Use.getResNo() ? TF : Perm;
7216 SmallVector<SDValue, 8> Ops;
7217 for (SDNode::op_iterator O = User->op_begin(),
7218 OE = User->op_end(); O != OE; ++O) {
7225 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
7228 return SDValue(N, 0);
7232 case ISD::INTRINSIC_WO_CHAIN:
7233 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
7234 Intrinsic::ppc_altivec_lvsl &&
7235 N->getOperand(1)->getOpcode() == ISD::ADD) {
7236 SDValue Add = N->getOperand(1);
7238 if (DAG.MaskedValueIsZero(Add->getOperand(1),
7239 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
7240 Add.getValueType().getScalarType().getSizeInBits()))) {
7241 SDNode *BasePtr = Add->getOperand(0).getNode();
7242 for (SDNode::use_iterator UI = BasePtr->use_begin(),
7243 UE = BasePtr->use_end(); UI != UE; ++UI) {
7244 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7245 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
7246 Intrinsic::ppc_altivec_lvsl) {
7247 // We've found another LVSL, and this address if an aligned
7248 // multiple of that one. The results will be the same, so use the
7249 // one we've just found instead.
7251 return SDValue(*UI, 0);
7257 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7258 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7259 N->getOperand(0).hasOneUse() &&
7260 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7261 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7262 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7263 N->getValueType(0) == MVT::i64))) {
7264 SDValue Load = N->getOperand(0);
7265 LoadSDNode *LD = cast<LoadSDNode>(Load);
7266 // Create the byte-swapping load.
7268 LD->getChain(), // Chain
7269 LD->getBasePtr(), // Ptr
7270 DAG.getValueType(N->getValueType(0)) // VT
7273 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7274 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7275 MVT::i64 : MVT::i32, MVT::Other),
7276 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7278 // If this is an i16 load, insert the truncate.
7279 SDValue ResVal = BSLoad;
7280 if (N->getValueType(0) == MVT::i16)
7281 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7283 // First, combine the bswap away. This makes the value produced by the
7285 DCI.CombineTo(N, ResVal);
7287 // Next, combine the load away, we give it a bogus result value but a real
7288 // chain result. The result value is dead because the bswap is dead.
7289 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7291 // Return N so it doesn't get rechecked!
7292 return SDValue(N, 0);
7296 case PPCISD::VCMP: {
7297 // If a VCMPo node already exists with exactly the same operands as this
7298 // node, use its result instead of this node (VCMPo computes both a CR6 and
7299 // a normal output).
7301 if (!N->getOperand(0).hasOneUse() &&
7302 !N->getOperand(1).hasOneUse() &&
7303 !N->getOperand(2).hasOneUse()) {
7305 // Scan all of the users of the LHS, looking for VCMPo's that match.
7306 SDNode *VCMPoNode = 0;
7308 SDNode *LHSN = N->getOperand(0).getNode();
7309 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7311 if (UI->getOpcode() == PPCISD::VCMPo &&
7312 UI->getOperand(1) == N->getOperand(1) &&
7313 UI->getOperand(2) == N->getOperand(2) &&
7314 UI->getOperand(0) == N->getOperand(0)) {
7319 // If there is no VCMPo node, or if the flag value has a single use, don't
7321 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7324 // Look at the (necessarily single) use of the flag value. If it has a
7325 // chain, this transformation is more complex. Note that multiple things
7326 // could use the value result, which we should ignore.
7327 SDNode *FlagUser = 0;
7328 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7329 FlagUser == 0; ++UI) {
7330 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7332 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7333 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7340 // If the user is a MFOCRF instruction, we know this is safe.
7341 // Otherwise we give up for right now.
7342 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
7343 return SDValue(VCMPoNode, 0);
7348 // If this is a branch on an altivec predicate comparison, lower this so
7349 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
7350 // lowering is done pre-legalize, because the legalizer lowers the predicate
7351 // compare down to code that is difficult to reassemble.
7352 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7353 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7355 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
7356 // value. If so, pass-through the AND to get to the intrinsic.
7357 if (LHS.getOpcode() == ISD::AND &&
7358 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7359 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
7360 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7361 isa<ConstantSDNode>(LHS.getOperand(1)) &&
7362 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
7364 LHS = LHS.getOperand(0);
7366 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7367 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
7368 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7369 isa<ConstantSDNode>(RHS)) {
7370 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
7371 "Counter decrement comparison is not EQ or NE");
7373 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7374 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
7375 (CC == ISD::SETNE && !Val);
7377 // We now need to make the intrinsic dead (it cannot be instruction
7379 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
7380 assert(LHS.getNode()->hasOneUse() &&
7381 "Counter decrement has more than one use");
7383 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7384 N->getOperand(0), N->getOperand(4));
7390 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7391 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7392 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7393 assert(isDot && "Can't compare against a vector result!");
7395 // If this is a comparison against something other than 0/1, then we know
7396 // that the condition is never/always true.
7397 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7398 if (Val != 0 && Val != 1) {
7399 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7400 return N->getOperand(0);
7401 // Always !=, turn it into an unconditional branch.
7402 return DAG.getNode(ISD::BR, dl, MVT::Other,
7403 N->getOperand(0), N->getOperand(4));
7406 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7408 // Create the PPCISD altivec 'dot' comparison node.
7410 LHS.getOperand(2), // LHS of compare
7411 LHS.getOperand(3), // RHS of compare
7412 DAG.getConstant(CompareOpc, MVT::i32)
7414 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7415 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7417 // Unpack the result based on how the target uses it.
7418 PPC::Predicate CompOpc;
7419 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7420 default: // Can't happen, don't crash on invalid number though.
7421 case 0: // Branch on the value of the EQ bit of CR6.
7422 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7424 case 1: // Branch on the inverted value of the EQ bit of CR6.
7425 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7427 case 2: // Branch on the value of the LT bit of CR6.
7428 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7430 case 3: // Branch on the inverted value of the LT bit of CR6.
7431 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7435 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7436 DAG.getConstant(CompOpc, MVT::i32),
7437 DAG.getRegister(PPC::CR6, MVT::i32),
7438 N->getOperand(4), CompNode.getValue(1));
7447 //===----------------------------------------------------------------------===//
7448 // Inline Assembly Support
7449 //===----------------------------------------------------------------------===//
7451 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7454 const SelectionDAG &DAG,
7455 unsigned Depth) const {
7456 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7457 switch (Op.getOpcode()) {
7459 case PPCISD::LBRX: {
7460 // lhbrx is known to have the top bits cleared out.
7461 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7462 KnownZero = 0xFFFF0000;
7465 case ISD::INTRINSIC_WO_CHAIN: {
7466 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7468 case Intrinsic::ppc_altivec_vcmpbfp_p:
7469 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7470 case Intrinsic::ppc_altivec_vcmpequb_p:
7471 case Intrinsic::ppc_altivec_vcmpequh_p:
7472 case Intrinsic::ppc_altivec_vcmpequw_p:
7473 case Intrinsic::ppc_altivec_vcmpgefp_p:
7474 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7475 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7476 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7477 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7478 case Intrinsic::ppc_altivec_vcmpgtub_p:
7479 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7480 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7481 KnownZero = ~1U; // All bits but the low one are known to be zero.
7489 /// getConstraintType - Given a constraint, return the type of
7490 /// constraint it is for this target.
7491 PPCTargetLowering::ConstraintType
7492 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7493 if (Constraint.size() == 1) {
7494 switch (Constraint[0]) {
7501 return C_RegisterClass;
7503 // FIXME: While Z does indicate a memory constraint, it specifically
7504 // indicates an r+r address (used in conjunction with the 'y' modifier
7505 // in the replacement string). Currently, we're forcing the base
7506 // register to be r0 in the asm printer (which is interpreted as zero)
7507 // and forming the complete address in the second register. This is
7512 return TargetLowering::getConstraintType(Constraint);
7515 /// Examine constraint type and operand type and determine a weight value.
7516 /// This object must already have been set up with the operand type
7517 /// and the current alternative constraint selected.
7518 TargetLowering::ConstraintWeight
7519 PPCTargetLowering::getSingleConstraintMatchWeight(
7520 AsmOperandInfo &info, const char *constraint) const {
7521 ConstraintWeight weight = CW_Invalid;
7522 Value *CallOperandVal = info.CallOperandVal;
7523 // If we don't have a value, we can't do a match,
7524 // but allow it at the lowest weight.
7525 if (CallOperandVal == NULL)
7527 Type *type = CallOperandVal->getType();
7528 // Look at the constraint type.
7529 switch (*constraint) {
7531 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7534 if (type->isIntegerTy())
7535 weight = CW_Register;
7538 if (type->isFloatTy())
7539 weight = CW_Register;
7542 if (type->isDoubleTy())
7543 weight = CW_Register;
7546 if (type->isVectorTy())
7547 weight = CW_Register;
7550 weight = CW_Register;
7559 std::pair<unsigned, const TargetRegisterClass*>
7560 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7562 if (Constraint.size() == 1) {
7563 // GCC RS6000 Constraint Letters
7564 switch (Constraint[0]) {
7566 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7567 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7568 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7570 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7571 return std::make_pair(0U, &PPC::G8RCRegClass);
7572 return std::make_pair(0U, &PPC::GPRCRegClass);
7574 if (VT == MVT::f32 || VT == MVT::i32)
7575 return std::make_pair(0U, &PPC::F4RCRegClass);
7576 if (VT == MVT::f64 || VT == MVT::i64)
7577 return std::make_pair(0U, &PPC::F8RCRegClass);
7580 return std::make_pair(0U, &PPC::VRRCRegClass);
7582 return std::make_pair(0U, &PPC::CRRCRegClass);
7586 std::pair<unsigned, const TargetRegisterClass*> R =
7587 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7589 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
7590 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
7591 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
7593 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
7594 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
7595 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
7596 PPC::GPRCRegClass.contains(R.first)) {
7597 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
7598 return std::make_pair(TRI->getMatchingSuperReg(R.first,
7599 PPC::sub_32, &PPC::G8RCRegClass),
7600 &PPC::G8RCRegClass);
7607 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7608 /// vector. If it is invalid, don't add anything to Ops.
7609 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7610 std::string &Constraint,
7611 std::vector<SDValue>&Ops,
7612 SelectionDAG &DAG) const {
7613 SDValue Result(0,0);
7615 // Only support length 1 constraints.
7616 if (Constraint.length() > 1) return;
7618 char Letter = Constraint[0];
7629 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7630 if (!CST) return; // Must be an immediate to match.
7631 unsigned Value = CST->getZExtValue();
7633 default: llvm_unreachable("Unknown constraint letter!");
7634 case 'I': // "I" is a signed 16-bit constant.
7635 if ((short)Value == (int)Value)
7636 Result = DAG.getTargetConstant(Value, Op.getValueType());
7638 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7639 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7640 if ((short)Value == 0)
7641 Result = DAG.getTargetConstant(Value, Op.getValueType());
7643 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7644 if ((Value >> 16) == 0)
7645 Result = DAG.getTargetConstant(Value, Op.getValueType());
7647 case 'M': // "M" is a constant that is greater than 31.
7649 Result = DAG.getTargetConstant(Value, Op.getValueType());
7651 case 'N': // "N" is a positive constant that is an exact power of two.
7652 if ((int)Value > 0 && isPowerOf2_32(Value))
7653 Result = DAG.getTargetConstant(Value, Op.getValueType());
7655 case 'O': // "O" is the constant zero.
7657 Result = DAG.getTargetConstant(Value, Op.getValueType());
7659 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7660 if ((short)-Value == (int)-Value)
7661 Result = DAG.getTargetConstant(Value, Op.getValueType());
7668 if (Result.getNode()) {
7669 Ops.push_back(Result);
7673 // Handle standard constraint letters.
7674 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7677 // isLegalAddressingMode - Return true if the addressing mode represented
7678 // by AM is legal for this target, for a load/store of the specified type.
7679 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7681 // FIXME: PPC does not allow r+i addressing modes for vectors!
7683 // PPC allows a sign-extended 16-bit immediate field.
7684 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7687 // No global is ever allowed as a base.
7691 // PPC only support r+r,
7693 case 0: // "r+i" or just "i", depending on HasBaseReg.
7696 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7698 // Otherwise we have r+r or r+i.
7701 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7703 // Allow 2*r as r+r.
7706 // No other scales are supported.
7713 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7714 SelectionDAG &DAG) const {
7715 MachineFunction &MF = DAG.getMachineFunction();
7716 MachineFrameInfo *MFI = MF.getFrameInfo();
7717 MFI->setReturnAddressIsTaken(true);
7720 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7722 // Make sure the function does not optimize away the store of the RA to
7724 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7725 FuncInfo->setLRStoreRequired();
7726 bool isPPC64 = PPCSubTarget.isPPC64();
7727 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7730 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7733 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7734 isPPC64? MVT::i64 : MVT::i32);
7735 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7736 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7738 MachinePointerInfo(), false, false, false, 0);
7741 // Just load the return address off the stack.
7742 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7743 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7744 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7747 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7748 SelectionDAG &DAG) const {
7750 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7752 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7753 bool isPPC64 = PtrVT == MVT::i64;
7755 MachineFunction &MF = DAG.getMachineFunction();
7756 MachineFrameInfo *MFI = MF.getFrameInfo();
7757 MFI->setFrameAddressIsTaken(true);
7759 // Naked functions never have a frame pointer, and so we use r1. For all
7760 // other functions, this decision must be delayed until during PEI.
7762 if (MF.getFunction()->getAttributes().hasAttribute(
7763 AttributeSet::FunctionIndex, Attribute::Naked))
7764 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7766 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7768 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7771 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7772 FrameAddr, MachinePointerInfo(), false, false,
7778 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7779 // The PowerPC target isn't yet aware of offsets.
7783 /// getOptimalMemOpType - Returns the target specific optimal type for load
7784 /// and store operations as a result of memset, memcpy, and memmove
7785 /// lowering. If DstAlign is zero that means it's safe to destination
7786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7787 /// means there isn't a need to check it against alignment requirement,
7788 /// probably because the source does not need to be loaded. If 'IsMemset' is
7789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7791 /// source is constant so it does not need to be loaded.
7792 /// It returns EVT::Other if the type should be determined using generic
7793 /// target-independent logic.
7794 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7795 unsigned DstAlign, unsigned SrcAlign,
7796 bool IsMemset, bool ZeroMemset,
7798 MachineFunction &MF) const {
7799 if (this->PPCSubTarget.isPPC64()) {
7806 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7808 if (DisablePPCUnaligned)
7811 // PowerPC supports unaligned memory access for simple non-vector types.
7812 // Although accessing unaligned addresses is not as efficient as accessing
7813 // aligned addresses, it is generally more efficient than manual expansion,
7814 // and generally only traps for software emulation when crossing page
7820 if (VT.getSimpleVT().isVector())
7823 if (VT == MVT::ppcf128)
7832 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7833 VT = VT.getScalarType();
7838 switch (VT.getSimpleVT().SimpleTy) {
7849 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7851 return TargetLowering::getSchedulingPreference(N);
7856 // Create a fast isel object.
7858 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
7859 const TargetLibraryInfo *LibInfo) const {
7860 return PPC::createFastISel(FuncInfo, LibInfo);