1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 setStackPointerRegisterToSaveRestore(PPC::X1);
631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
634 setStackPointerRegisterToSaveRestore(PPC::R1);
635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
641 setTargetDAGCombine(ISD::LOAD);
642 setTargetDAGCombine(ISD::STORE);
643 setTargetDAGCombine(ISD::BR_CC);
644 if (Subtarget.useCRBits())
645 setTargetDAGCombine(ISD::BRCOND);
646 setTargetDAGCombine(ISD::BSWAP);
647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
653 if (Subtarget.useCRBits()) {
654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
665 // Darwin long double math library functions have $LDBL128 appended.
666 if (Subtarget.isDarwin()) {
667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
681 if (Subtarget.useCRBits())
682 setHasMultipleConditionRegisters();
684 setMinFunctionAlignment(2);
685 if (Subtarget.isDarwin())
686 setPrefFunctionAlignment(4);
688 if (isPPC64 && Subtarget.isJITCodeModel())
689 // Temporary workaround for the inability of PPC64 JIT to handle jump
691 setSupportJumpTables(false);
693 setInsertFencesForAtomic(true);
695 if (Subtarget.enableMachineScheduler())
696 setSchedulingPreference(Sched::Source);
698 setSchedulingPreference(Sched::Hybrid);
700 computeRegisterProperties();
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
704 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
713 setPrefFunctionAlignment(4);
717 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718 /// the desired ByVal argument alignment.
719 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
739 if (MaxAlign == MaxMaxAlign)
745 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746 /// function arguments in the caller parameter area.
747 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
748 // Darwin passes everything on 4 byte boundary.
749 if (Subtarget.isDarwin())
752 // 16byte and wider vectors are passed on 16byte boundary.
753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
754 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
756 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 default: return nullptr;
763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
776 case PPCISD::LOAD: return "PPCISD::LOAD";
777 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
778 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
779 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
780 case PPCISD::SRL: return "PPCISD::SRL";
781 case PPCISD::SRA: return "PPCISD::SRA";
782 case PPCISD::SHL: return "PPCISD::SHL";
783 case PPCISD::CALL: return "PPCISD::CALL";
784 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
785 case PPCISD::MTCTR: return "PPCISD::MTCTR";
786 case PPCISD::BCTRL: return "PPCISD::BCTRL";
787 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
788 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
789 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
790 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
791 case PPCISD::VCMP: return "PPCISD::VCMP";
792 case PPCISD::VCMPo: return "PPCISD::VCMPo";
793 case PPCISD::LBRX: return "PPCISD::LBRX";
794 case PPCISD::STBRX: return "PPCISD::STBRX";
795 case PPCISD::LARX: return "PPCISD::LARX";
796 case PPCISD::STCX: return "PPCISD::STCX";
797 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
798 case PPCISD::BDNZ: return "PPCISD::BDNZ";
799 case PPCISD::BDZ: return "PPCISD::BDZ";
800 case PPCISD::MFFS: return "PPCISD::MFFS";
801 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
802 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
803 case PPCISD::CR6SET: return "PPCISD::CR6SET";
804 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
805 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
806 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
807 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
808 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
809 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
810 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
811 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
812 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
813 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
814 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
815 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
816 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
817 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
818 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
819 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
820 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
821 case PPCISD::SC: return "PPCISD::SC";
825 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
827 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
828 return VT.changeVectorElementTypeToInteger();
831 //===----------------------------------------------------------------------===//
832 // Node matching predicates, for use by the tblgen matching code.
833 //===----------------------------------------------------------------------===//
835 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
836 static bool isFloatingPointZero(SDValue Op) {
837 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
838 return CFP->getValueAPF().isZero();
839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
840 // Maybe this has already been legalized into the constant pool?
841 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
842 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
843 return CFP->getValueAPF().isZero();
848 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
849 /// true if Op is undef or if it matches the specified value.
850 static bool isConstantOrUndef(int Op, int Val) {
851 return Op < 0 || Op == Val;
854 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
855 /// VPKUHUM instruction.
856 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
858 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
860 for (unsigned i = 0; i != 16; ++i)
861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
864 for (unsigned i = 0; i != 8; ++i)
865 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
866 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
872 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUWUM instruction.
874 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
877 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
885 for (unsigned i = 0; i != 16; i += 2)
886 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
887 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
890 for (unsigned i = 0; i != 8; i += 2)
891 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
892 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
893 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
900 /// isVMerge - Common function, used to match vmrg* shuffles.
902 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
903 unsigned LHSStart, unsigned RHSStart) {
904 if (N->getValueType(0) != MVT::v16i8)
906 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
907 "Unsupported merge size!");
909 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
910 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
911 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
912 LHSStart+j+i*UnitSize) ||
913 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
914 RHSStart+j+i*UnitSize))
920 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
921 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
922 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
923 bool isUnary, SelectionDAG &DAG) {
924 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
926 return isVMerge(N, UnitSize, 0, 16);
927 return isVMerge(N, UnitSize, 0, 0);
930 return isVMerge(N, UnitSize, 8, 24);
931 return isVMerge(N, UnitSize, 8, 8);
935 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
936 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
937 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
938 bool isUnary, SelectionDAG &DAG) {
939 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
941 return isVMerge(N, UnitSize, 8, 24);
942 return isVMerge(N, UnitSize, 8, 8);
945 return isVMerge(N, UnitSize, 0, 16);
946 return isVMerge(N, UnitSize, 0, 0);
951 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
952 /// amount, otherwise return -1.
953 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
954 if (N->getValueType(0) != MVT::v16i8)
957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
959 // Find the first non-undef value in the shuffle mask.
961 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
964 if (i == 16) return -1; // all undef.
966 // Otherwise, check to see if the rest of the elements are consecutively
967 // numbered from this value.
968 unsigned ShiftAmt = SVOp->getMaskElt(i);
969 if (ShiftAmt < i) return -1;
971 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
976 // Check the rest of the elements to see if they are consecutive.
977 for (++i; i != 16; ++i)
978 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
981 // Check the rest of the elements to see if they are consecutive.
982 for (++i; i != 16; ++i)
983 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
987 } else { // Big Endian
992 // Check the rest of the elements to see if they are consecutive.
993 for (++i; i != 16; ++i)
994 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
997 // Check the rest of the elements to see if they are consecutive.
998 for (++i; i != 16; ++i)
999 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1006 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1007 /// specifies a splat of a single element that is suitable for input to
1008 /// VSPLTB/VSPLTH/VSPLTW.
1009 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1010 assert(N->getValueType(0) == MVT::v16i8 &&
1011 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1013 // This is a splat operation if each element of the permute is the same, and
1014 // if the value doesn't reference the second vector.
1015 unsigned ElementBase = N->getMaskElt(0);
1017 // FIXME: Handle UNDEF elements too!
1018 if (ElementBase >= 16)
1021 // Check that the indices are consecutive, in the case of a multi-byte element
1022 // splatted with a v16i8 mask.
1023 for (unsigned i = 1; i != EltSize; ++i)
1024 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1027 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1028 if (N->getMaskElt(i) < 0) continue;
1029 for (unsigned j = 0; j != EltSize; ++j)
1030 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1036 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1038 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1039 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1041 APInt APVal, APUndef;
1045 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1047 return CFP->getValueAPF().isNegZero();
1052 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1053 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1054 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1055 SelectionDAG &DAG) {
1056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1057 assert(isSplatShuffleMask(SVOp, EltSize));
1058 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1059 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1061 return SVOp->getMaskElt(0) / EltSize;
1064 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1065 /// by using a vspltis[bhw] instruction of the specified element size, return
1066 /// the constant being splatted. The ByteSize field indicates the number of
1067 /// bytes of each element [124] -> [bhw].
1068 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1069 SDValue OpVal(nullptr, 0);
1071 // If ByteSize of the splat is bigger than the element size of the
1072 // build_vector, then we have a case where we are checking for a splat where
1073 // multiple elements of the buildvector are folded together into a single
1074 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1075 unsigned EltSize = 16/N->getNumOperands();
1076 if (EltSize < ByteSize) {
1077 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1078 SDValue UniquedVals[4];
1079 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1081 // See if all of the elements in the buildvector agree across.
1082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1083 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1084 // If the element isn't a constant, bail fully out.
1085 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1088 if (!UniquedVals[i&(Multiple-1)].getNode())
1089 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1090 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1091 return SDValue(); // no match.
1094 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1095 // either constant or undef values that are identical for each chunk. See
1096 // if these chunks can form into a larger vspltis*.
1098 // Check to see if all of the leading entries are either 0 or -1. If
1099 // neither, then this won't fit into the immediate field.
1100 bool LeadingZero = true;
1101 bool LeadingOnes = true;
1102 for (unsigned i = 0; i != Multiple-1; ++i) {
1103 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1105 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1106 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1108 // Finally, check the least significant entry.
1110 if (!UniquedVals[Multiple-1].getNode())
1111 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1112 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1114 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1117 if (!UniquedVals[Multiple-1].getNode())
1118 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1119 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1120 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1121 return DAG.getTargetConstant(Val, MVT::i32);
1127 // Check to see if this buildvec has a single non-undef value in its elements.
1128 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1129 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1130 if (!OpVal.getNode())
1131 OpVal = N->getOperand(i);
1132 else if (OpVal != N->getOperand(i))
1136 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1138 unsigned ValSizeInBytes = EltSize;
1140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1141 Value = CN->getZExtValue();
1142 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1143 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1144 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1147 // If the splat value is larger than the element value, then we can never do
1148 // this splat. The only case that we could fit the replicated bits into our
1149 // immediate field for would be zero, and we prefer to use vxor for it.
1150 if (ValSizeInBytes < ByteSize) return SDValue();
1152 // If the element value is larger than the splat value, cut it in half and
1153 // check to see if the two halves are equal. Continue doing this until we
1154 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1155 while (ValSizeInBytes > ByteSize) {
1156 ValSizeInBytes >>= 1;
1158 // If the top half equals the bottom half, we're still ok.
1159 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1160 (Value & ((1 << (8*ValSizeInBytes))-1)))
1164 // Properly sign extend the value.
1165 int MaskVal = SignExtend32(Value, ByteSize * 8);
1167 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1168 if (MaskVal == 0) return SDValue();
1170 // Finally, if this value fits in a 5 bit sext field, return it
1171 if (SignExtend32<5>(MaskVal) == MaskVal)
1172 return DAG.getTargetConstant(MaskVal, MVT::i32);
1176 //===----------------------------------------------------------------------===//
1177 // Addressing Mode Selection
1178 //===----------------------------------------------------------------------===//
1180 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1181 /// or 64-bit immediate, and if the value can be accurately represented as a
1182 /// sign extension from a 16-bit value. If so, this returns true and the
1184 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1185 if (!isa<ConstantSDNode>(N))
1188 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1189 if (N->getValueType(0) == MVT::i32)
1190 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1192 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1194 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1195 return isIntS16Immediate(Op.getNode(), Imm);
1199 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1200 /// can be represented as an indexed [r+r] operation. Returns false if it
1201 /// can be more efficiently represented with [r+imm].
1202 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1204 SelectionDAG &DAG) const {
1206 if (N.getOpcode() == ISD::ADD) {
1207 if (isIntS16Immediate(N.getOperand(1), imm))
1208 return false; // r+i
1209 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1210 return false; // r+i
1212 Base = N.getOperand(0);
1213 Index = N.getOperand(1);
1215 } else if (N.getOpcode() == ISD::OR) {
1216 if (isIntS16Immediate(N.getOperand(1), imm))
1217 return false; // r+i can fold it if we can.
1219 // If this is an or of disjoint bitfields, we can codegen this as an add
1220 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1222 APInt LHSKnownZero, LHSKnownOne;
1223 APInt RHSKnownZero, RHSKnownOne;
1224 DAG.computeKnownBits(N.getOperand(0),
1225 LHSKnownZero, LHSKnownOne);
1227 if (LHSKnownZero.getBoolValue()) {
1228 DAG.computeKnownBits(N.getOperand(1),
1229 RHSKnownZero, RHSKnownOne);
1230 // If all of the bits are known zero on the LHS or RHS, the add won't
1232 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1233 Base = N.getOperand(0);
1234 Index = N.getOperand(1);
1243 // If we happen to be doing an i64 load or store into a stack slot that has
1244 // less than a 4-byte alignment, then the frame-index elimination may need to
1245 // use an indexed load or store instruction (because the offset may not be a
1246 // multiple of 4). The extra register needed to hold the offset comes from the
1247 // register scavenger, and it is possible that the scavenger will need to use
1248 // an emergency spill slot. As a result, we need to make sure that a spill slot
1249 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1251 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1252 // FIXME: This does not handle the LWA case.
1256 // NOTE: We'll exclude negative FIs here, which come from argument
1257 // lowering, because there are no known test cases triggering this problem
1258 // using packed structures (or similar). We can remove this exclusion if
1259 // we find such a test case. The reason why this is so test-case driven is
1260 // because this entire 'fixup' is only to prevent crashes (from the
1261 // register scavenger) on not-really-valid inputs. For example, if we have:
1263 // %b = bitcast i1* %a to i64*
1264 // store i64* a, i64 b
1265 // then the store should really be marked as 'align 1', but is not. If it
1266 // were marked as 'align 1' then the indexed form would have been
1267 // instruction-selected initially, and the problem this 'fixup' is preventing
1268 // won't happen regardless.
1272 MachineFunction &MF = DAG.getMachineFunction();
1273 MachineFrameInfo *MFI = MF.getFrameInfo();
1275 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1279 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1280 FuncInfo->setHasNonRISpills();
1283 /// Returns true if the address N can be represented by a base register plus
1284 /// a signed 16-bit displacement [r+imm], and if it is not better
1285 /// represented as reg+reg. If Aligned is true, only accept displacements
1286 /// suitable for STD and friends, i.e. multiples of 4.
1287 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1290 bool Aligned) const {
1291 // FIXME dl should come from parent load or store, not from address
1293 // If this can be more profitably realized as r+r, fail.
1294 if (SelectAddressRegReg(N, Disp, Base, DAG))
1297 if (N.getOpcode() == ISD::ADD) {
1299 if (isIntS16Immediate(N.getOperand(1), imm) &&
1300 (!Aligned || (imm & 3) == 0)) {
1301 Disp = DAG.getTargetConstant(imm, N.getValueType());
1302 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1303 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1304 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1306 Base = N.getOperand(0);
1308 return true; // [r+i]
1309 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1310 // Match LOAD (ADD (X, Lo(G))).
1311 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1312 && "Cannot handle constant offsets yet!");
1313 Disp = N.getOperand(1).getOperand(0); // The global address.
1314 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1315 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1316 Disp.getOpcode() == ISD::TargetConstantPool ||
1317 Disp.getOpcode() == ISD::TargetJumpTable);
1318 Base = N.getOperand(0);
1319 return true; // [&g+r]
1321 } else if (N.getOpcode() == ISD::OR) {
1323 if (isIntS16Immediate(N.getOperand(1), imm) &&
1324 (!Aligned || (imm & 3) == 0)) {
1325 // If this is an or of disjoint bitfields, we can codegen this as an add
1326 // (for better address arithmetic) if the LHS and RHS of the OR are
1327 // provably disjoint.
1328 APInt LHSKnownZero, LHSKnownOne;
1329 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1331 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1332 // If all of the bits are known zero on the LHS or RHS, the add won't
1334 Base = N.getOperand(0);
1335 Disp = DAG.getTargetConstant(imm, N.getValueType());
1339 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1340 // Loading from a constant address.
1342 // If this address fits entirely in a 16-bit sext immediate field, codegen
1345 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1346 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1347 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1348 CN->getValueType(0));
1352 // Handle 32-bit sext immediates with LIS + addr mode.
1353 if ((CN->getValueType(0) == MVT::i32 ||
1354 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1355 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1356 int Addr = (int)CN->getZExtValue();
1358 // Otherwise, break this down into an LIS + disp.
1359 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1361 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1362 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1363 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1368 Disp = DAG.getTargetConstant(0, getPointerTy());
1369 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1370 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1371 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1374 return true; // [r+0]
1377 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1378 /// represented as an indexed [r+r] operation.
1379 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1381 SelectionDAG &DAG) const {
1382 // Check to see if we can easily represent this as an [r+r] address. This
1383 // will fail if it thinks that the address is more profitably represented as
1384 // reg+imm, e.g. where imm = 0.
1385 if (SelectAddressRegReg(N, Base, Index, DAG))
1388 // If the operand is an addition, always emit this as [r+r], since this is
1389 // better (for code size, and execution, as the memop does the add for free)
1390 // than emitting an explicit add.
1391 if (N.getOpcode() == ISD::ADD) {
1392 Base = N.getOperand(0);
1393 Index = N.getOperand(1);
1397 // Otherwise, do it the hard way, using R0 as the base register.
1398 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1404 /// getPreIndexedAddressParts - returns true by value, base pointer and
1405 /// offset pointer and addressing mode by reference if the node's address
1406 /// can be legally represented as pre-indexed load / store address.
1407 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1409 ISD::MemIndexedMode &AM,
1410 SelectionDAG &DAG) const {
1411 if (DisablePPCPreinc) return false;
1417 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1418 Ptr = LD->getBasePtr();
1419 VT = LD->getMemoryVT();
1420 Alignment = LD->getAlignment();
1421 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1422 Ptr = ST->getBasePtr();
1423 VT = ST->getMemoryVT();
1424 Alignment = ST->getAlignment();
1429 // PowerPC doesn't have preinc load/store instructions for vectors.
1433 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1435 // Common code will reject creating a pre-inc form if the base pointer
1436 // is a frame index, or if N is a store and the base pointer is either
1437 // the same as or a predecessor of the value being stored. Check for
1438 // those situations here, and try with swapped Base/Offset instead.
1441 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1444 SDValue Val = cast<StoreSDNode>(N)->getValue();
1445 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1450 std::swap(Base, Offset);
1456 // LDU/STU can only handle immediates that are a multiple of 4.
1457 if (VT != MVT::i64) {
1458 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1461 // LDU/STU need an address with at least 4-byte alignment.
1465 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1469 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1470 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1471 // sext i32 to i64 when addr mode is r+i.
1472 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1473 LD->getExtensionType() == ISD::SEXTLOAD &&
1474 isa<ConstantSDNode>(Offset))
1482 //===----------------------------------------------------------------------===//
1483 // LowerOperation implementation
1484 //===----------------------------------------------------------------------===//
1486 /// GetLabelAccessInfo - Return true if we should reference labels using a
1487 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1488 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1489 unsigned &LoOpFlags,
1490 const GlobalValue *GV = nullptr) {
1491 HiOpFlags = PPCII::MO_HA;
1492 LoOpFlags = PPCII::MO_LO;
1494 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1495 // non-darwin platform. We don't support PIC on other platforms yet.
1496 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1497 TM.getSubtarget<PPCSubtarget>().isDarwin();
1499 HiOpFlags |= PPCII::MO_PIC_FLAG;
1500 LoOpFlags |= PPCII::MO_PIC_FLAG;
1503 // If this is a reference to a global value that requires a non-lazy-ptr, make
1504 // sure that instruction lowering adds it.
1505 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1506 HiOpFlags |= PPCII::MO_NLP_FLAG;
1507 LoOpFlags |= PPCII::MO_NLP_FLAG;
1509 if (GV->hasHiddenVisibility()) {
1510 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1511 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1518 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1519 SelectionDAG &DAG) {
1520 EVT PtrVT = HiPart.getValueType();
1521 SDValue Zero = DAG.getConstant(0, PtrVT);
1524 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1525 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1527 // With PIC, the first instruction is actually "GR+hi(&G)".
1529 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1530 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1532 // Generate non-pic code that has direct accesses to the constant pool.
1533 // The address of the global is just (hi(&g)+lo(&g)).
1534 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1537 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1538 SelectionDAG &DAG) const {
1539 EVT PtrVT = Op.getValueType();
1540 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1541 const Constant *C = CP->getConstVal();
1543 // 64-bit SVR4 ABI code is always position-independent.
1544 // The actual address of the GlobalValue is stored in the TOC.
1545 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1546 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1547 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1548 DAG.getRegister(PPC::X2, MVT::i64));
1551 unsigned MOHiFlag, MOLoFlag;
1552 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1554 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1556 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1557 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1560 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1561 EVT PtrVT = Op.getValueType();
1562 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1564 // 64-bit SVR4 ABI code is always position-independent.
1565 // The actual address of the GlobalValue is stored in the TOC.
1566 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1567 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1568 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1569 DAG.getRegister(PPC::X2, MVT::i64));
1572 unsigned MOHiFlag, MOLoFlag;
1573 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1574 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1575 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1576 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1579 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1580 SelectionDAG &DAG) const {
1581 EVT PtrVT = Op.getValueType();
1583 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1585 unsigned MOHiFlag, MOLoFlag;
1586 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1587 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1588 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1589 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1592 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1593 SelectionDAG &DAG) const {
1595 // FIXME: TLS addresses currently use medium model code sequences,
1596 // which is the most useful form. Eventually support for small and
1597 // large models could be added if users need it, at the cost of
1598 // additional complexity.
1599 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1601 const GlobalValue *GV = GA->getGlobal();
1602 EVT PtrVT = getPointerTy();
1603 bool is64bit = Subtarget.isPPC64();
1605 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1607 if (Model == TLSModel::LocalExec) {
1608 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1609 PPCII::MO_TPREL_HA);
1610 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1611 PPCII::MO_TPREL_LO);
1612 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1613 is64bit ? MVT::i64 : MVT::i32);
1614 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1615 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1618 if (Model == TLSModel::InitialExec) {
1619 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1620 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1624 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1625 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1626 PtrVT, GOTReg, TGA);
1628 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1629 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1630 PtrVT, TGA, GOTPtr);
1631 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1634 if (Model == TLSModel::GeneralDynamic) {
1635 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1636 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1637 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1639 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1642 // We need a chain node, and don't have one handy. The underlying
1643 // call has no side effects, so using the function entry node
1645 SDValue Chain = DAG.getEntryNode();
1646 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1647 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1648 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1649 PtrVT, ParmReg, TGA);
1650 // The return value from GET_TLS_ADDR really is in X3 already, but
1651 // some hacks are needed here to tie everything together. The extra
1652 // copies dissolve during subsequent transforms.
1653 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1654 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1657 if (Model == TLSModel::LocalDynamic) {
1658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1659 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1660 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1662 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1665 // We need a chain node, and don't have one handy. The underlying
1666 // call has no side effects, so using the function entry node
1668 SDValue Chain = DAG.getEntryNode();
1669 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1670 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1671 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1672 PtrVT, ParmReg, TGA);
1673 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1674 // some hacks are needed here to tie everything together. The extra
1675 // copies dissolve during subsequent transforms.
1676 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1677 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1678 Chain, ParmReg, TGA);
1679 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1682 llvm_unreachable("Unknown TLS model!");
1685 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1686 SelectionDAG &DAG) const {
1687 EVT PtrVT = Op.getValueType();
1688 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1690 const GlobalValue *GV = GSDN->getGlobal();
1692 // 64-bit SVR4 ABI code is always position-independent.
1693 // The actual address of the GlobalValue is stored in the TOC.
1694 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1695 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1696 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1697 DAG.getRegister(PPC::X2, MVT::i64));
1700 unsigned MOHiFlag, MOLoFlag;
1701 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1704 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1706 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1708 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1710 // If the global reference is actually to a non-lazy-pointer, we have to do an
1711 // extra load to get the address of the global.
1712 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1713 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1714 false, false, false, 0);
1718 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1719 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1722 if (Op.getValueType() == MVT::v2i64) {
1723 // When the operands themselves are v2i64 values, we need to do something
1724 // special because VSX has no underlying comparison operations for these.
1725 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1726 // Equality can be handled by casting to the legal type for Altivec
1727 // comparisons, everything else needs to be expanded.
1728 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1729 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1730 DAG.getSetCC(dl, MVT::v4i32,
1731 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1732 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1739 // We handle most of these in the usual way.
1743 // If we're comparing for equality to zero, expose the fact that this is
1744 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1745 // fold the new nodes.
1746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1747 if (C->isNullValue() && CC == ISD::SETEQ) {
1748 EVT VT = Op.getOperand(0).getValueType();
1749 SDValue Zext = Op.getOperand(0);
1750 if (VT.bitsLT(MVT::i32)) {
1752 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1754 unsigned Log2b = Log2_32(VT.getSizeInBits());
1755 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1756 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1757 DAG.getConstant(Log2b, MVT::i32));
1758 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1760 // Leave comparisons against 0 and -1 alone for now, since they're usually
1761 // optimized. FIXME: revisit this when we can custom lower all setcc
1763 if (C->isAllOnesValue() || C->isNullValue())
1767 // If we have an integer seteq/setne, turn it into a compare against zero
1768 // by xor'ing the rhs with the lhs, which is faster than setting a
1769 // condition register, reading it back out, and masking the correct bit. The
1770 // normal approach here uses sub to do this instead of xor. Using xor exposes
1771 // the result to other bit-twiddling opportunities.
1772 EVT LHSVT = Op.getOperand(0).getValueType();
1773 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1774 EVT VT = Op.getValueType();
1775 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1777 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1782 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1783 const PPCSubtarget &Subtarget) const {
1784 SDNode *Node = Op.getNode();
1785 EVT VT = Node->getValueType(0);
1786 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1787 SDValue InChain = Node->getOperand(0);
1788 SDValue VAListPtr = Node->getOperand(1);
1789 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1792 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1795 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1796 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1798 InChain = GprIndex.getValue(1);
1800 if (VT == MVT::i64) {
1801 // Check if GprIndex is even
1802 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1803 DAG.getConstant(1, MVT::i32));
1804 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1805 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1806 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1807 DAG.getConstant(1, MVT::i32));
1808 // Align GprIndex to be even if it isn't
1809 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1813 // fpr index is 1 byte after gpr
1814 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1815 DAG.getConstant(1, MVT::i32));
1818 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1819 FprPtr, MachinePointerInfo(SV), MVT::i8,
1821 InChain = FprIndex.getValue(1);
1823 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1824 DAG.getConstant(8, MVT::i32));
1826 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1827 DAG.getConstant(4, MVT::i32));
1830 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1831 MachinePointerInfo(), false, false,
1833 InChain = OverflowArea.getValue(1);
1835 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1836 MachinePointerInfo(), false, false,
1838 InChain = RegSaveArea.getValue(1);
1840 // select overflow_area if index > 8
1841 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1842 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1844 // adjustment constant gpr_index * 4/8
1845 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1846 VT.isInteger() ? GprIndex : FprIndex,
1847 DAG.getConstant(VT.isInteger() ? 4 : 8,
1850 // OurReg = RegSaveArea + RegConstant
1851 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1854 // Floating types are 32 bytes into RegSaveArea
1855 if (VT.isFloatingPoint())
1856 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1857 DAG.getConstant(32, MVT::i32));
1859 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1860 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1861 VT.isInteger() ? GprIndex : FprIndex,
1862 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1865 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1866 VT.isInteger() ? VAListPtr : FprPtr,
1867 MachinePointerInfo(SV),
1868 MVT::i8, false, false, 0);
1870 // determine if we should load from reg_save_area or overflow_area
1871 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1873 // increase overflow_area by 4/8 if gpr/fpr > 8
1874 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1875 DAG.getConstant(VT.isInteger() ? 4 : 8,
1878 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1881 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1883 MachinePointerInfo(),
1884 MVT::i32, false, false, 0);
1886 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1887 false, false, false, 0);
1890 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1891 const PPCSubtarget &Subtarget) const {
1892 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1894 // We have to copy the entire va_list struct:
1895 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1896 return DAG.getMemcpy(Op.getOperand(0), Op,
1897 Op.getOperand(1), Op.getOperand(2),
1898 DAG.getConstant(12, MVT::i32), 8, false, true,
1899 MachinePointerInfo(), MachinePointerInfo());
1902 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1903 SelectionDAG &DAG) const {
1904 return Op.getOperand(0);
1907 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1908 SelectionDAG &DAG) const {
1909 SDValue Chain = Op.getOperand(0);
1910 SDValue Trmp = Op.getOperand(1); // trampoline
1911 SDValue FPtr = Op.getOperand(2); // nested function
1912 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1915 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1916 bool isPPC64 = (PtrVT == MVT::i64);
1918 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1921 TargetLowering::ArgListTy Args;
1922 TargetLowering::ArgListEntry Entry;
1924 Entry.Ty = IntPtrTy;
1925 Entry.Node = Trmp; Args.push_back(Entry);
1927 // TrampSize == (isPPC64 ? 48 : 40);
1928 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1929 isPPC64 ? MVT::i64 : MVT::i32);
1930 Args.push_back(Entry);
1932 Entry.Node = FPtr; Args.push_back(Entry);
1933 Entry.Node = Nest; Args.push_back(Entry);
1935 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1936 TargetLowering::CallLoweringInfo CLI(DAG);
1937 CLI.setDebugLoc(dl).setChain(Chain)
1938 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1939 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1940 std::move(Args), 0);
1942 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1943 return CallResult.second;
1946 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1947 const PPCSubtarget &Subtarget) const {
1948 MachineFunction &MF = DAG.getMachineFunction();
1949 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1953 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1954 // vastart just stores the address of the VarArgsFrameIndex slot into the
1955 // memory location argument.
1956 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1957 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1958 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1959 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1960 MachinePointerInfo(SV),
1964 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1965 // We suppose the given va_list is already allocated.
1968 // char gpr; /* index into the array of 8 GPRs
1969 // * stored in the register save area
1970 // * gpr=0 corresponds to r3,
1971 // * gpr=1 to r4, etc.
1973 // char fpr; /* index into the array of 8 FPRs
1974 // * stored in the register save area
1975 // * fpr=0 corresponds to f1,
1976 // * fpr=1 to f2, etc.
1978 // char *overflow_arg_area;
1979 // /* location on stack that holds
1980 // * the next overflow argument
1982 // char *reg_save_area;
1983 // /* where r3:r10 and f1:f8 (if saved)
1989 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1990 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1993 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1995 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1997 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2000 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2001 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2003 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2004 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2006 uint64_t FPROffset = 1;
2007 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2009 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2011 // Store first byte : number of int regs
2012 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2014 MachinePointerInfo(SV),
2015 MVT::i8, false, false, 0);
2016 uint64_t nextOffset = FPROffset;
2017 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2020 // Store second byte : number of float regs
2021 SDValue secondStore =
2022 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2023 MachinePointerInfo(SV, nextOffset), MVT::i8,
2025 nextOffset += StackOffset;
2026 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2028 // Store second word : arguments given on stack
2029 SDValue thirdStore =
2030 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2031 MachinePointerInfo(SV, nextOffset),
2033 nextOffset += FrameOffset;
2034 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2036 // Store third word : arguments given in registers
2037 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2038 MachinePointerInfo(SV, nextOffset),
2043 #include "PPCGenCallingConv.inc"
2045 // Function whose sole purpose is to kill compiler warnings
2046 // stemming from unused functions included from PPCGenCallingConv.inc.
2047 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2048 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2051 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2052 CCValAssign::LocInfo &LocInfo,
2053 ISD::ArgFlagsTy &ArgFlags,
2058 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2060 CCValAssign::LocInfo &LocInfo,
2061 ISD::ArgFlagsTy &ArgFlags,
2063 static const MCPhysReg ArgRegs[] = {
2064 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2065 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2067 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2069 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2071 // Skip one register if the first unallocated register has an even register
2072 // number and there are still argument registers available which have not been
2073 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2074 // need to skip a register if RegNum is odd.
2075 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2076 State.AllocateReg(ArgRegs[RegNum]);
2079 // Always return false here, as this function only makes sure that the first
2080 // unallocated register has an odd register number and does not actually
2081 // allocate a register for the current argument.
2085 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2087 CCValAssign::LocInfo &LocInfo,
2088 ISD::ArgFlagsTy &ArgFlags,
2090 static const MCPhysReg ArgRegs[] = {
2091 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2095 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2097 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2099 // If there is only one Floating-point register left we need to put both f64
2100 // values of a split ppc_fp128 value on the stack.
2101 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2102 State.AllocateReg(ArgRegs[RegNum]);
2105 // Always return false here, as this function only makes sure that the two f64
2106 // values a ppc_fp128 value is split into are both passed in registers or both
2107 // passed on the stack and does not actually allocate a register for the
2108 // current argument.
2112 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2114 static const MCPhysReg *GetFPR() {
2115 static const MCPhysReg FPR[] = {
2116 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2117 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2123 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2125 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2126 unsigned PtrByteSize) {
2127 unsigned ArgSize = ArgVT.getStoreSize();
2128 if (Flags.isByVal())
2129 ArgSize = Flags.getByValSize();
2130 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2134 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2135 /// ensure minimum alignment required for target.
2136 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2137 unsigned NumBytes) {
2138 unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment();
2139 unsigned AlignMask = TargetAlign - 1;
2140 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2145 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2146 CallingConv::ID CallConv, bool isVarArg,
2147 const SmallVectorImpl<ISD::InputArg>
2149 SDLoc dl, SelectionDAG &DAG,
2150 SmallVectorImpl<SDValue> &InVals)
2152 if (Subtarget.isSVR4ABI()) {
2153 if (Subtarget.isPPC64())
2154 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2157 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2160 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2166 PPCTargetLowering::LowerFormalArguments_32SVR4(
2168 CallingConv::ID CallConv, bool isVarArg,
2169 const SmallVectorImpl<ISD::InputArg>
2171 SDLoc dl, SelectionDAG &DAG,
2172 SmallVectorImpl<SDValue> &InVals) const {
2174 // 32-bit SVR4 ABI Stack Frame Layout:
2175 // +-----------------------------------+
2176 // +--> | Back chain |
2177 // | +-----------------------------------+
2178 // | | Floating-point register save area |
2179 // | +-----------------------------------+
2180 // | | General register save area |
2181 // | +-----------------------------------+
2182 // | | CR save word |
2183 // | +-----------------------------------+
2184 // | | VRSAVE save word |
2185 // | +-----------------------------------+
2186 // | | Alignment padding |
2187 // | +-----------------------------------+
2188 // | | Vector register save area |
2189 // | +-----------------------------------+
2190 // | | Local variable space |
2191 // | +-----------------------------------+
2192 // | | Parameter list area |
2193 // | +-----------------------------------+
2194 // | | LR save word |
2195 // | +-----------------------------------+
2196 // SP--> +--- | Back chain |
2197 // +-----------------------------------+
2200 // System V Application Binary Interface PowerPC Processor Supplement
2201 // AltiVec Technology Programming Interface Manual
2203 MachineFunction &MF = DAG.getMachineFunction();
2204 MachineFrameInfo *MFI = MF.getFrameInfo();
2205 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2207 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2208 // Potential tail calls could cause overwriting of argument stack slots.
2209 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2210 (CallConv == CallingConv::Fast));
2211 unsigned PtrByteSize = 4;
2213 // Assign locations to all of the incoming arguments.
2214 SmallVector<CCValAssign, 16> ArgLocs;
2215 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2216 getTargetMachine(), ArgLocs, *DAG.getContext());
2218 // Reserve space for the linkage area on the stack.
2219 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false);
2220 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2222 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2224 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2225 CCValAssign &VA = ArgLocs[i];
2227 // Arguments stored in registers.
2228 if (VA.isRegLoc()) {
2229 const TargetRegisterClass *RC;
2230 EVT ValVT = VA.getValVT();
2232 switch (ValVT.getSimpleVT().SimpleTy) {
2234 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2237 RC = &PPC::GPRCRegClass;
2240 RC = &PPC::F4RCRegClass;
2243 if (Subtarget.hasVSX())
2244 RC = &PPC::VSFRCRegClass;
2246 RC = &PPC::F8RCRegClass;
2252 RC = &PPC::VRRCRegClass;
2256 RC = &PPC::VSHRCRegClass;
2260 // Transform the arguments stored in physical registers into virtual ones.
2261 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2262 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2263 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2265 if (ValVT == MVT::i1)
2266 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2268 InVals.push_back(ArgValue);
2270 // Argument stored in memory.
2271 assert(VA.isMemLoc());
2273 unsigned ArgSize = VA.getLocVT().getStoreSize();
2274 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2277 // Create load nodes to retrieve arguments from the stack.
2278 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2279 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2280 MachinePointerInfo(),
2281 false, false, false, 0));
2285 // Assign locations to all of the incoming aggregate by value arguments.
2286 // Aggregates passed by value are stored in the local variable space of the
2287 // caller's stack frame, right above the parameter list area.
2288 SmallVector<CCValAssign, 16> ByValArgLocs;
2289 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2290 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2292 // Reserve stack space for the allocations in CCInfo.
2293 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2295 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2297 // Area that is at least reserved in the caller of this function.
2298 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2299 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2301 // Set the size that is at least reserved in caller of this function. Tail
2302 // call optimized function's reserved stack space needs to be aligned so that
2303 // taking the difference between two stack areas will result in an aligned
2305 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2306 FuncInfo->setMinReservedArea(MinReservedArea);
2308 SmallVector<SDValue, 8> MemOps;
2310 // If the function takes variable number of arguments, make a frame index for
2311 // the start of the first vararg value... for expansion of llvm.va_start.
2313 static const MCPhysReg GPArgRegs[] = {
2314 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2315 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2317 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2319 static const MCPhysReg FPArgRegs[] = {
2320 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2323 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2325 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2327 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2330 // Make room for NumGPArgRegs and NumFPArgRegs.
2331 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2332 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2334 FuncInfo->setVarArgsStackOffset(
2335 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2336 CCInfo.getNextStackOffset(), true));
2338 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2339 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2341 // The fixed integer arguments of a variadic function are stored to the
2342 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2343 // the result of va_next.
2344 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2345 // Get an existing live-in vreg, or add a new one.
2346 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2348 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2350 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2351 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2352 MachinePointerInfo(), false, false, 0);
2353 MemOps.push_back(Store);
2354 // Increment the address by four for the next argument to store
2355 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2356 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2359 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2361 // The double arguments are stored to the VarArgsFrameIndex
2363 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2364 // Get an existing live-in vreg, or add a new one.
2365 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2367 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2369 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2370 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2371 MachinePointerInfo(), false, false, 0);
2372 MemOps.push_back(Store);
2373 // Increment the address by eight for the next argument to store
2374 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2376 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2380 if (!MemOps.empty())
2381 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2386 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2387 // value to MVT::i64 and then truncate to the correct register size.
2389 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2390 SelectionDAG &DAG, SDValue ArgVal,
2393 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2394 DAG.getValueType(ObjectVT));
2395 else if (Flags.isZExt())
2396 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2397 DAG.getValueType(ObjectVT));
2399 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2403 PPCTargetLowering::LowerFormalArguments_64SVR4(
2405 CallingConv::ID CallConv, bool isVarArg,
2406 const SmallVectorImpl<ISD::InputArg>
2408 SDLoc dl, SelectionDAG &DAG,
2409 SmallVectorImpl<SDValue> &InVals) const {
2410 // TODO: add description of PPC stack frame format, or at least some docs.
2412 bool isLittleEndian = Subtarget.isLittleEndian();
2413 MachineFunction &MF = DAG.getMachineFunction();
2414 MachineFrameInfo *MFI = MF.getFrameInfo();
2415 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2417 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2418 // Potential tail calls could cause overwriting of argument stack slots.
2419 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2420 (CallConv == CallingConv::Fast));
2421 unsigned PtrByteSize = 8;
2423 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false);
2424 unsigned ArgOffset = LinkageSize;
2425 // Area that is at least reserved in caller of this function.
2426 unsigned MinReservedArea = ArgOffset;
2428 static const MCPhysReg GPR[] = {
2429 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2430 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2433 static const MCPhysReg *FPR = GetFPR();
2435 static const MCPhysReg VR[] = {
2436 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2437 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2439 static const MCPhysReg VSRH[] = {
2440 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2441 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2444 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2445 const unsigned Num_FPR_Regs = 13;
2446 const unsigned Num_VR_Regs = array_lengthof(VR);
2448 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2450 // Add DAG nodes to load the arguments or copy them out of registers. On
2451 // entry to a function on PPC, the arguments start after the linkage area,
2452 // although the first ones are often in registers.
2454 SmallVector<SDValue, 8> MemOps;
2455 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2456 unsigned CurArgIdx = 0;
2457 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2459 bool needsLoad = false;
2460 EVT ObjectVT = Ins[ArgNo].VT;
2461 unsigned ObjSize = ObjectVT.getStoreSize();
2462 unsigned ArgSize = ObjSize;
2463 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2464 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2465 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2467 unsigned CurArgOffset = ArgOffset;
2469 // Altivec parameters are padded to a 16 byte boundary.
2470 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2471 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8 ||
2472 ObjectVT==MVT::v2f64 || ObjectVT==MVT::v2i64)
2473 MinReservedArea = ((MinReservedArea+15)/16)*16;
2475 // Calculate min reserved area.
2476 MinReservedArea += CalculateStackSlotSize(ObjectVT, Flags, PtrByteSize);
2478 // FIXME the codegen can be much improved in some cases.
2479 // We do not have to keep everything in memory.
2480 if (Flags.isByVal()) {
2481 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2482 ObjSize = Flags.getByValSize();
2483 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2484 // Empty aggregate parameters do not take up registers. Examples:
2488 // etc. However, we have to provide a place-holder in InVals, so
2489 // pretend we have an 8-byte item at the current address for that
2492 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2493 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2494 InVals.push_back(FIN);
2498 unsigned BVAlign = Flags.getByValAlign();
2500 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2501 CurArgOffset = ArgOffset;
2504 // All aggregates smaller than 8 bytes must be passed right-justified.
2505 if (ObjSize < PtrByteSize && !isLittleEndian)
2506 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2507 // The value of the object is its address.
2508 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2509 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2510 InVals.push_back(FIN);
2513 if (GPR_idx != Num_GPR_Regs) {
2514 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2515 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2518 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2519 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2520 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2521 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2522 MachinePointerInfo(FuncArg),
2523 ObjType, false, false, 0);
2525 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2526 // store the whole register as-is to the parameter save area
2527 // slot. The address of the parameter was already calculated
2528 // above (InVals.push_back(FIN)) to be the right-justified
2529 // offset within the slot. For this store, we need a new
2530 // frame index that points at the beginning of the slot.
2531 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2532 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2533 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2534 MachinePointerInfo(FuncArg),
2538 MemOps.push_back(Store);
2541 // Whether we copied from a register or not, advance the offset
2542 // into the parameter save area by a full doubleword.
2543 ArgOffset += PtrByteSize;
2547 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2548 // Store whatever pieces of the object are in registers
2549 // to memory. ArgOffset will be the address of the beginning
2551 if (GPR_idx != Num_GPR_Regs) {
2553 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2554 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2555 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2556 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2557 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2558 MachinePointerInfo(FuncArg, j),
2560 MemOps.push_back(Store);
2562 ArgOffset += PtrByteSize;
2564 ArgOffset += ArgSize - j;
2571 switch (ObjectVT.getSimpleVT().SimpleTy) {
2572 default: llvm_unreachable("Unhandled argument type!");
2576 if (GPR_idx != Num_GPR_Regs) {
2577 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2578 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2580 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2581 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2582 // value to MVT::i64 and then truncate to the correct register size.
2583 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2588 ArgSize = PtrByteSize;
2595 // Every 8 bytes of argument space consumes one of the GPRs available for
2596 // argument passing.
2597 if (GPR_idx != Num_GPR_Regs) {
2600 if (FPR_idx != Num_FPR_Regs) {
2603 if (ObjectVT == MVT::f32)
2604 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2606 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2607 &PPC::VSFRCRegClass :
2608 &PPC::F8RCRegClass);
2610 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2614 ArgSize = PtrByteSize;
2625 // Vectors are aligned to a 16-byte boundary in the argument save area.
2626 while ((ArgOffset % 16) != 0) {
2627 ArgOffset += PtrByteSize;
2628 if (GPR_idx != Num_GPR_Regs)
2631 if (VR_idx != Num_VR_Regs) {
2632 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2633 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2634 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2635 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2638 CurArgOffset = ArgOffset;
2642 GPR_idx = std::min(GPR_idx + 2, Num_GPR_Regs);
2646 // We need to load the argument to a virtual register if we determined
2647 // above that we ran out of physical registers of the appropriate type.
2649 if (ObjSize < ArgSize && !isLittleEndian)
2650 CurArgOffset += ArgSize - ObjSize;
2651 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2652 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2653 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2654 false, false, false, 0);
2657 InVals.push_back(ArgVal);
2660 // Area that is at least reserved in the caller of this function.
2661 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
2663 // Set the size that is at least reserved in caller of this function. Tail
2664 // call optimized functions' reserved stack space needs to be aligned so that
2665 // taking the difference between two stack areas will result in an aligned
2667 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2668 FuncInfo->setMinReservedArea(MinReservedArea);
2670 // If the function takes variable number of arguments, make a frame index for
2671 // the start of the first vararg value... for expansion of llvm.va_start.
2673 int Depth = ArgOffset;
2675 FuncInfo->setVarArgsFrameIndex(
2676 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2677 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2679 // If this function is vararg, store any remaining integer argument regs
2680 // to their spots on the stack so that they may be loaded by deferencing the
2681 // result of va_next.
2682 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2683 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2684 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2685 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2686 MachinePointerInfo(), false, false, 0);
2687 MemOps.push_back(Store);
2688 // Increment the address by four for the next argument to store
2689 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2690 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2694 if (!MemOps.empty())
2695 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2701 PPCTargetLowering::LowerFormalArguments_Darwin(
2703 CallingConv::ID CallConv, bool isVarArg,
2704 const SmallVectorImpl<ISD::InputArg>
2706 SDLoc dl, SelectionDAG &DAG,
2707 SmallVectorImpl<SDValue> &InVals) const {
2708 // TODO: add description of PPC stack frame format, or at least some docs.
2710 MachineFunction &MF = DAG.getMachineFunction();
2711 MachineFrameInfo *MFI = MF.getFrameInfo();
2712 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2714 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2715 bool isPPC64 = PtrVT == MVT::i64;
2716 // Potential tail calls could cause overwriting of argument stack slots.
2717 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2718 (CallConv == CallingConv::Fast));
2719 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2721 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true);
2722 unsigned ArgOffset = LinkageSize;
2723 // Area that is at least reserved in caller of this function.
2724 unsigned MinReservedArea = ArgOffset;
2726 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2727 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2728 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2730 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2731 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2732 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2735 static const MCPhysReg *FPR = GetFPR();
2737 static const MCPhysReg VR[] = {
2738 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2739 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2742 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2743 const unsigned Num_FPR_Regs = 13;
2744 const unsigned Num_VR_Regs = array_lengthof( VR);
2746 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2748 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2750 // In 32-bit non-varargs functions, the stack space for vectors is after the
2751 // stack space for non-vectors. We do not use this space unless we have
2752 // too many vectors to fit in registers, something that only occurs in
2753 // constructed examples:), but we have to walk the arglist to figure
2754 // that out...for the pathological case, compute VecArgOffset as the
2755 // start of the vector parameter area. Computing VecArgOffset is the
2756 // entire point of the following loop.
2757 unsigned VecArgOffset = ArgOffset;
2758 if (!isVarArg && !isPPC64) {
2759 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2761 EVT ObjectVT = Ins[ArgNo].VT;
2762 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2764 if (Flags.isByVal()) {
2765 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2766 unsigned ObjSize = Flags.getByValSize();
2768 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2769 VecArgOffset += ArgSize;
2773 switch(ObjectVT.getSimpleVT().SimpleTy) {
2774 default: llvm_unreachable("Unhandled argument type!");
2780 case MVT::i64: // PPC64
2782 // FIXME: We are guaranteed to be !isPPC64 at this point.
2783 // Does MVT::i64 apply?
2790 // Nothing to do, we're only looking at Nonvector args here.
2795 // We've found where the vector parameter area in memory is. Skip the
2796 // first 12 parameters; these don't use that memory.
2797 VecArgOffset = ((VecArgOffset+15)/16)*16;
2798 VecArgOffset += 12*16;
2800 // Add DAG nodes to load the arguments or copy them out of registers. On
2801 // entry to a function on PPC, the arguments start after the linkage area,
2802 // although the first ones are often in registers.
2804 SmallVector<SDValue, 8> MemOps;
2805 unsigned nAltivecParamsAtEnd = 0;
2806 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2807 unsigned CurArgIdx = 0;
2808 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2810 bool needsLoad = false;
2811 EVT ObjectVT = Ins[ArgNo].VT;
2812 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2813 unsigned ArgSize = ObjSize;
2814 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2815 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2816 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2818 unsigned CurArgOffset = ArgOffset;
2820 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2821 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2822 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2823 if (isVarArg || isPPC64) {
2824 MinReservedArea = ((MinReservedArea+15)/16)*16;
2825 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2828 } else nAltivecParamsAtEnd++;
2830 // Calculate min reserved area.
2831 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2835 // FIXME the codegen can be much improved in some cases.
2836 // We do not have to keep everything in memory.
2837 if (Flags.isByVal()) {
2838 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2839 ObjSize = Flags.getByValSize();
2840 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2841 // Objects of size 1 and 2 are right justified, everything else is
2842 // left justified. This means the memory address is adjusted forwards.
2843 if (ObjSize==1 || ObjSize==2) {
2844 CurArgOffset = CurArgOffset + (4 - ObjSize);
2846 // The value of the object is its address.
2847 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2848 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2849 InVals.push_back(FIN);
2850 if (ObjSize==1 || ObjSize==2) {
2851 if (GPR_idx != Num_GPR_Regs) {
2854 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2856 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2857 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2858 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2859 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2860 MachinePointerInfo(FuncArg),
2861 ObjType, false, false, 0);
2862 MemOps.push_back(Store);
2866 ArgOffset += PtrByteSize;
2870 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2871 // Store whatever pieces of the object are in registers
2872 // to memory. ArgOffset will be the address of the beginning
2874 if (GPR_idx != Num_GPR_Regs) {
2877 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2879 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2880 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2881 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2882 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2883 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2884 MachinePointerInfo(FuncArg, j),
2886 MemOps.push_back(Store);
2888 ArgOffset += PtrByteSize;
2890 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2897 switch (ObjectVT.getSimpleVT().SimpleTy) {
2898 default: llvm_unreachable("Unhandled argument type!");
2902 if (GPR_idx != Num_GPR_Regs) {
2903 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2904 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2906 if (ObjectVT == MVT::i1)
2907 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2912 ArgSize = PtrByteSize;
2914 // All int arguments reserve stack space in the Darwin ABI.
2915 ArgOffset += PtrByteSize;
2919 case MVT::i64: // PPC64
2920 if (GPR_idx != Num_GPR_Regs) {
2921 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2922 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2924 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2925 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2926 // value to MVT::i64 and then truncate to the correct register size.
2927 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2932 ArgSize = PtrByteSize;
2934 // All int arguments reserve stack space in the Darwin ABI.
2940 // Every 4 bytes of argument space consumes one of the GPRs available for
2941 // argument passing.
2942 if (GPR_idx != Num_GPR_Regs) {
2944 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2947 if (FPR_idx != Num_FPR_Regs) {
2950 if (ObjectVT == MVT::f32)
2951 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2953 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2955 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2961 // All FP arguments reserve stack space in the Darwin ABI.
2962 ArgOffset += isPPC64 ? 8 : ObjSize;
2968 // Note that vector arguments in registers don't reserve stack space,
2969 // except in varargs functions.
2970 if (VR_idx != Num_VR_Regs) {
2971 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2972 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2974 while ((ArgOffset % 16) != 0) {
2975 ArgOffset += PtrByteSize;
2976 if (GPR_idx != Num_GPR_Regs)
2980 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2984 if (!isVarArg && !isPPC64) {
2985 // Vectors go after all the nonvectors.
2986 CurArgOffset = VecArgOffset;
2989 // Vectors are aligned.
2990 ArgOffset = ((ArgOffset+15)/16)*16;
2991 CurArgOffset = ArgOffset;
2999 // We need to load the argument to a virtual register if we determined above
3000 // that we ran out of physical registers of the appropriate type.
3002 int FI = MFI->CreateFixedObject(ObjSize,
3003 CurArgOffset + (ArgSize - ObjSize),
3005 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3006 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3007 false, false, false, 0);
3010 InVals.push_back(ArgVal);
3013 // Allow for Altivec parameters at the end, if needed.
3014 if (nAltivecParamsAtEnd) {
3015 MinReservedArea = ((MinReservedArea+15)/16)*16;
3016 MinReservedArea += 16*nAltivecParamsAtEnd;
3019 // Area that is at least reserved in the caller of this function.
3020 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3022 // Set the size that is at least reserved in caller of this function. Tail
3023 // call optimized functions' reserved stack space needs to be aligned so that
3024 // taking the difference between two stack areas will result in an aligned
3026 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3027 FuncInfo->setMinReservedArea(MinReservedArea);
3029 // If the function takes variable number of arguments, make a frame index for
3030 // the start of the first vararg value... for expansion of llvm.va_start.
3032 int Depth = ArgOffset;
3034 FuncInfo->setVarArgsFrameIndex(
3035 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3037 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3039 // If this function is vararg, store any remaining integer argument regs
3040 // to their spots on the stack so that they may be loaded by deferencing the
3041 // result of va_next.
3042 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3046 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3048 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3050 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3051 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3052 MachinePointerInfo(), false, false, 0);
3053 MemOps.push_back(Store);
3054 // Increment the address by four for the next argument to store
3055 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3056 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3060 if (!MemOps.empty())
3061 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3066 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3067 /// adjusted to accommodate the arguments for the tailcall.
3068 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3069 unsigned ParamSize) {
3071 if (!isTailCall) return 0;
3073 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3074 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3075 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3076 // Remember only if the new adjustement is bigger.
3077 if (SPDiff < FI->getTailCallSPDelta())
3078 FI->setTailCallSPDelta(SPDiff);
3083 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3084 /// for tail call optimization. Targets which want to do tail call
3085 /// optimization should implement this function.
3087 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3088 CallingConv::ID CalleeCC,
3090 const SmallVectorImpl<ISD::InputArg> &Ins,
3091 SelectionDAG& DAG) const {
3092 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3095 // Variable argument functions are not supported.
3099 MachineFunction &MF = DAG.getMachineFunction();
3100 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3101 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3102 // Functions containing by val parameters are not supported.
3103 for (unsigned i = 0; i != Ins.size(); i++) {
3104 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3105 if (Flags.isByVal()) return false;
3108 // Non-PIC/GOT tail calls are supported.
3109 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3112 // At the moment we can only do local tail calls (in same module, hidden
3113 // or protected) if we are generating PIC.
3114 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3115 return G->getGlobal()->hasHiddenVisibility()
3116 || G->getGlobal()->hasProtectedVisibility();
3122 /// isCallCompatibleAddress - Return the immediate to use if the specified
3123 /// 32-bit value is representable in the immediate field of a BxA instruction.
3124 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3125 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3126 if (!C) return nullptr;
3128 int Addr = C->getZExtValue();
3129 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3130 SignExtend32<26>(Addr) != Addr)
3131 return nullptr; // Top 6 bits have to be sext of immediate.
3133 return DAG.getConstant((int)C->getZExtValue() >> 2,
3134 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3139 struct TailCallArgumentInfo {
3144 TailCallArgumentInfo() : FrameIdx(0) {}
3149 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3151 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3153 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3154 SmallVectorImpl<SDValue> &MemOpChains,
3156 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3157 SDValue Arg = TailCallArgs[i].Arg;
3158 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3159 int FI = TailCallArgs[i].FrameIdx;
3160 // Store relative to framepointer.
3161 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3162 MachinePointerInfo::getFixedStack(FI),
3167 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3168 /// the appropriate stack slot for the tail call optimized function call.
3169 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3170 MachineFunction &MF,
3179 // Calculate the new stack slot for the return address.
3180 int SlotSize = isPPC64 ? 8 : 4;
3181 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3183 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3184 NewRetAddrLoc, true);
3185 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3186 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3187 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3188 MachinePointerInfo::getFixedStack(NewRetAddr),
3191 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3192 // slot as the FP is never overwritten.
3195 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3196 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3198 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3199 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3200 MachinePointerInfo::getFixedStack(NewFPIdx),
3207 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3208 /// the position of the argument.
3210 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3211 SDValue Arg, int SPDiff, unsigned ArgOffset,
3212 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3213 int Offset = ArgOffset + SPDiff;
3214 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3215 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3216 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3217 SDValue FIN = DAG.getFrameIndex(FI, VT);
3218 TailCallArgumentInfo Info;
3220 Info.FrameIdxOp = FIN;
3222 TailCallArguments.push_back(Info);
3225 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3226 /// stack slot. Returns the chain as result and the loaded frame pointers in
3227 /// LROpOut/FPOpout. Used when tail calling.
3228 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3236 // Load the LR and FP stack slot for later adjusting.
3237 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3238 LROpOut = getReturnAddrFrameIndex(DAG);
3239 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3240 false, false, false, 0);
3241 Chain = SDValue(LROpOut.getNode(), 1);
3243 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3244 // slot as the FP is never overwritten.
3246 FPOpOut = getFramePointerFrameIndex(DAG);
3247 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3248 false, false, false, 0);
3249 Chain = SDValue(FPOpOut.getNode(), 1);
3255 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3256 /// by "Src" to address "Dst" of size "Size". Alignment information is
3257 /// specified by the specific parameter attribute. The copy will be passed as
3258 /// a byval function parameter.
3259 /// Sometimes what we are copying is the end of a larger object, the part that
3260 /// does not fit in registers.
3262 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3263 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3265 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3266 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3267 false, false, MachinePointerInfo(),
3268 MachinePointerInfo());
3271 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3274 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3275 SDValue Arg, SDValue PtrOff, int SPDiff,
3276 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3277 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3278 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3280 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3285 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3287 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3288 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3289 DAG.getConstant(ArgOffset, PtrVT));
3291 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3292 MachinePointerInfo(), false, false, 0));
3293 // Calculate and remember argument location.
3294 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3299 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3300 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3301 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3302 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3303 MachineFunction &MF = DAG.getMachineFunction();
3305 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3306 // might overwrite each other in case of tail call optimization.
3307 SmallVector<SDValue, 8> MemOpChains2;
3308 // Do not flag preceding copytoreg stuff together with the following stuff.
3310 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3312 if (!MemOpChains2.empty())
3313 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3315 // Store the return address to the appropriate stack slot.
3316 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3317 isPPC64, isDarwinABI, dl);
3319 // Emit callseq_end just before tailcall node.
3320 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3321 DAG.getIntPtrConstant(0, true), InFlag, dl);
3322 InFlag = Chain.getValue(1);
3326 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3327 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3328 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3329 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3330 const PPCSubtarget &Subtarget) {
3332 bool isPPC64 = Subtarget.isPPC64();
3333 bool isSVR4ABI = Subtarget.isSVR4ABI();
3335 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3336 NodeTys.push_back(MVT::Other); // Returns a chain
3337 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3339 unsigned CallOpc = PPCISD::CALL;
3341 bool needIndirectCall = true;
3342 if (!isSVR4ABI || !isPPC64)
3343 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3344 // If this is an absolute destination address, use the munged value.
3345 Callee = SDValue(Dest, 0);
3346 needIndirectCall = false;
3349 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3350 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3351 // Use indirect calls for ALL functions calls in JIT mode, since the
3352 // far-call stubs may be outside relocation limits for a BL instruction.
3353 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3354 unsigned OpFlags = 0;
3355 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3356 (Subtarget.getTargetTriple().isMacOSX() &&
3357 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3358 (G->getGlobal()->isDeclaration() ||
3359 G->getGlobal()->isWeakForLinker())) {
3360 // PC-relative references to external symbols should go through $stub,
3361 // unless we're building with the leopard linker or later, which
3362 // automatically synthesizes these stubs.
3363 OpFlags = PPCII::MO_DARWIN_STUB;
3366 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3367 // every direct call is) turn it into a TargetGlobalAddress /
3368 // TargetExternalSymbol node so that legalize doesn't hack it.
3369 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3370 Callee.getValueType(),
3372 needIndirectCall = false;
3376 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3377 unsigned char OpFlags = 0;
3379 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3380 (Subtarget.getTargetTriple().isMacOSX() &&
3381 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3382 // PC-relative references to external symbols should go through $stub,
3383 // unless we're building with the leopard linker or later, which
3384 // automatically synthesizes these stubs.
3385 OpFlags = PPCII::MO_DARWIN_STUB;
3388 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3390 needIndirectCall = false;
3393 if (needIndirectCall) {
3394 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3395 // to do the call, we can't use PPCISD::CALL.
3396 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3398 if (isSVR4ABI && isPPC64) {
3399 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3400 // entry point, but to the function descriptor (the function entry point
3401 // address is part of the function descriptor though).
3402 // The function descriptor is a three doubleword structure with the
3403 // following fields: function entry point, TOC base address and
3404 // environment pointer.
3405 // Thus for a call through a function pointer, the following actions need
3407 // 1. Save the TOC of the caller in the TOC save area of its stack
3408 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3409 // 2. Load the address of the function entry point from the function
3411 // 3. Load the TOC of the callee from the function descriptor into r2.
3412 // 4. Load the environment pointer from the function descriptor into
3414 // 5. Branch to the function entry point address.
3415 // 6. On return of the callee, the TOC of the caller needs to be
3416 // restored (this is done in FinishCall()).
3418 // All those operations are flagged together to ensure that no other
3419 // operations can be scheduled in between. E.g. without flagging the
3420 // operations together, a TOC access in the caller could be scheduled
3421 // between the load of the callee TOC and the branch to the callee, which
3422 // results in the TOC access going through the TOC of the callee instead
3423 // of going through the TOC of the caller, which leads to incorrect code.
3425 // Load the address of the function entry point from the function
3427 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3428 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3429 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3430 Chain = LoadFuncPtr.getValue(1);
3431 InFlag = LoadFuncPtr.getValue(2);
3433 // Load environment pointer into r11.
3434 // Offset of the environment pointer within the function descriptor.
3435 SDValue PtrOff = DAG.getIntPtrConstant(16);
3437 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3438 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3440 Chain = LoadEnvPtr.getValue(1);
3441 InFlag = LoadEnvPtr.getValue(2);
3443 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3445 Chain = EnvVal.getValue(0);
3446 InFlag = EnvVal.getValue(1);
3448 // Load TOC of the callee into r2. We are using a target-specific load
3449 // with r2 hard coded, because the result of a target-independent load
3450 // would never go directly into r2, since r2 is a reserved register (which
3451 // prevents the register allocator from allocating it), resulting in an
3452 // additional register being allocated and an unnecessary move instruction
3454 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3455 SDValue TOCOff = DAG.getIntPtrConstant(8);
3456 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3457 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3459 Chain = LoadTOCPtr.getValue(0);
3460 InFlag = LoadTOCPtr.getValue(1);
3462 MTCTROps[0] = Chain;
3463 MTCTROps[1] = LoadFuncPtr;
3464 MTCTROps[2] = InFlag;
3467 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3468 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3469 InFlag = Chain.getValue(1);
3472 NodeTys.push_back(MVT::Other);
3473 NodeTys.push_back(MVT::Glue);
3474 Ops.push_back(Chain);
3475 CallOpc = PPCISD::BCTRL;
3476 Callee.setNode(nullptr);
3477 // Add use of X11 (holding environment pointer)
3478 if (isSVR4ABI && isPPC64)
3479 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3480 // Add CTR register as callee so a bctr can be emitted later.
3482 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3485 // If this is a direct call, pass the chain and the callee.
3486 if (Callee.getNode()) {
3487 Ops.push_back(Chain);
3488 Ops.push_back(Callee);
3490 // If this is a tail call add stack pointer delta.
3492 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3494 // Add argument registers to the end of the list so that they are known live
3496 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3497 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3498 RegsToPass[i].second.getValueType()));
3504 bool isLocalCall(const SDValue &Callee)
3506 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3507 return !G->getGlobal()->isDeclaration() &&
3508 !G->getGlobal()->isWeakForLinker();
3513 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3514 CallingConv::ID CallConv, bool isVarArg,
3515 const SmallVectorImpl<ISD::InputArg> &Ins,
3516 SDLoc dl, SelectionDAG &DAG,
3517 SmallVectorImpl<SDValue> &InVals) const {
3519 SmallVector<CCValAssign, 16> RVLocs;
3520 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3521 getTargetMachine(), RVLocs, *DAG.getContext());
3522 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3524 // Copy all of the result registers out of their specified physreg.
3525 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3526 CCValAssign &VA = RVLocs[i];
3527 assert(VA.isRegLoc() && "Can only return in registers!");
3529 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3530 VA.getLocReg(), VA.getLocVT(), InFlag);
3531 Chain = Val.getValue(1);
3532 InFlag = Val.getValue(2);
3534 switch (VA.getLocInfo()) {
3535 default: llvm_unreachable("Unknown loc info!");
3536 case CCValAssign::Full: break;
3537 case CCValAssign::AExt:
3538 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3540 case CCValAssign::ZExt:
3541 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3542 DAG.getValueType(VA.getValVT()));
3543 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3545 case CCValAssign::SExt:
3546 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3547 DAG.getValueType(VA.getValVT()));
3548 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3552 InVals.push_back(Val);
3559 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3560 bool isTailCall, bool isVarArg,
3562 SmallVector<std::pair<unsigned, SDValue>, 8>
3564 SDValue InFlag, SDValue Chain,
3566 int SPDiff, unsigned NumBytes,
3567 const SmallVectorImpl<ISD::InputArg> &Ins,
3568 SmallVectorImpl<SDValue> &InVals) const {
3569 std::vector<EVT> NodeTys;
3570 SmallVector<SDValue, 8> Ops;
3571 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3572 isTailCall, RegsToPass, Ops, NodeTys,
3575 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3576 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3577 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3579 // When performing tail call optimization the callee pops its arguments off
3580 // the stack. Account for this here so these bytes can be pushed back on in
3581 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3582 int BytesCalleePops =
3583 (CallConv == CallingConv::Fast &&
3584 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3586 // Add a register mask operand representing the call-preserved registers.
3587 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3588 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3589 assert(Mask && "Missing call preserved mask for calling convention");
3590 Ops.push_back(DAG.getRegisterMask(Mask));
3592 if (InFlag.getNode())
3593 Ops.push_back(InFlag);
3597 assert(((Callee.getOpcode() == ISD::Register &&
3598 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3599 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3600 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3601 isa<ConstantSDNode>(Callee)) &&
3602 "Expecting an global address, external symbol, absolute value or register");
3604 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3607 // Add a NOP immediately after the branch instruction when using the 64-bit
3608 // SVR4 ABI. At link time, if caller and callee are in a different module and
3609 // thus have a different TOC, the call will be replaced with a call to a stub
3610 // function which saves the current TOC, loads the TOC of the callee and
3611 // branches to the callee. The NOP will be replaced with a load instruction
3612 // which restores the TOC of the caller from the TOC save slot of the current
3613 // stack frame. If caller and callee belong to the same module (and have the
3614 // same TOC), the NOP will remain unchanged.
3616 bool needsTOCRestore = false;
3617 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3618 if (CallOpc == PPCISD::BCTRL) {
3619 // This is a call through a function pointer.
3620 // Restore the caller TOC from the save area into R2.
3621 // See PrepareCall() for more information about calls through function
3622 // pointers in the 64-bit SVR4 ABI.
3623 // We are using a target-specific load with r2 hard coded, because the
3624 // result of a target-independent load would never go directly into r2,
3625 // since r2 is a reserved register (which prevents the register allocator
3626 // from allocating it), resulting in an additional register being
3627 // allocated and an unnecessary move instruction being generated.
3628 needsTOCRestore = true;
3629 } else if ((CallOpc == PPCISD::CALL) &&
3630 (!isLocalCall(Callee) ||
3631 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3632 // Otherwise insert NOP for non-local calls.
3633 CallOpc = PPCISD::CALL_NOP;
3637 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3638 InFlag = Chain.getValue(1);
3640 if (needsTOCRestore) {
3641 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3642 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3643 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3644 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
3645 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3646 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3647 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3648 InFlag = Chain.getValue(1);
3651 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3652 DAG.getIntPtrConstant(BytesCalleePops, true),
3655 InFlag = Chain.getValue(1);
3657 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3658 Ins, dl, DAG, InVals);
3662 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3663 SmallVectorImpl<SDValue> &InVals) const {
3664 SelectionDAG &DAG = CLI.DAG;
3666 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3667 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3668 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3669 SDValue Chain = CLI.Chain;
3670 SDValue Callee = CLI.Callee;
3671 bool &isTailCall = CLI.IsTailCall;
3672 CallingConv::ID CallConv = CLI.CallConv;
3673 bool isVarArg = CLI.IsVarArg;
3676 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3679 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3680 report_fatal_error("failed to perform tail call elimination on a call "
3681 "site marked musttail");
3683 if (Subtarget.isSVR4ABI()) {
3684 if (Subtarget.isPPC64())
3685 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3686 isTailCall, Outs, OutVals, Ins,
3689 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3690 isTailCall, Outs, OutVals, Ins,
3694 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3695 isTailCall, Outs, OutVals, Ins,
3700 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3701 CallingConv::ID CallConv, bool isVarArg,
3703 const SmallVectorImpl<ISD::OutputArg> &Outs,
3704 const SmallVectorImpl<SDValue> &OutVals,
3705 const SmallVectorImpl<ISD::InputArg> &Ins,
3706 SDLoc dl, SelectionDAG &DAG,
3707 SmallVectorImpl<SDValue> &InVals) const {
3708 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3709 // of the 32-bit SVR4 ABI stack frame layout.
3711 assert((CallConv == CallingConv::C ||
3712 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3714 unsigned PtrByteSize = 4;
3716 MachineFunction &MF = DAG.getMachineFunction();
3718 // Mark this function as potentially containing a function that contains a
3719 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3720 // and restoring the callers stack pointer in this functions epilog. This is
3721 // done because by tail calling the called function might overwrite the value
3722 // in this function's (MF) stack pointer stack slot 0(SP).
3723 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3724 CallConv == CallingConv::Fast)
3725 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3727 // Count how many bytes are to be pushed on the stack, including the linkage
3728 // area, parameter list area and the part of the local variable space which
3729 // contains copies of aggregates which are passed by value.
3731 // Assign locations to all of the outgoing arguments.
3732 SmallVector<CCValAssign, 16> ArgLocs;
3733 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3734 getTargetMachine(), ArgLocs, *DAG.getContext());
3736 // Reserve space for the linkage area on the stack.
3737 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3740 // Handle fixed and variable vector arguments differently.
3741 // Fixed vector arguments go into registers as long as registers are
3742 // available. Variable vector arguments always go into memory.
3743 unsigned NumArgs = Outs.size();
3745 for (unsigned i = 0; i != NumArgs; ++i) {
3746 MVT ArgVT = Outs[i].VT;
3747 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3750 if (Outs[i].IsFixed) {
3751 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3754 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3760 errs() << "Call operand #" << i << " has unhandled type "
3761 << EVT(ArgVT).getEVTString() << "\n";
3763 llvm_unreachable(nullptr);
3767 // All arguments are treated the same.
3768 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3771 // Assign locations to all of the outgoing aggregate by value arguments.
3772 SmallVector<CCValAssign, 16> ByValArgLocs;
3773 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3774 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3776 // Reserve stack space for the allocations in CCInfo.
3777 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3779 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3781 // Size of the linkage area, parameter list area and the part of the local
3782 // space variable where copies of aggregates which are passed by value are
3784 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3786 // Calculate by how many bytes the stack has to be adjusted in case of tail
3787 // call optimization.
3788 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3790 // Adjust the stack pointer for the new arguments...
3791 // These operations are automatically eliminated by the prolog/epilog pass
3792 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3794 SDValue CallSeqStart = Chain;
3796 // Load the return address and frame pointer so it can be moved somewhere else
3799 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3802 // Set up a copy of the stack pointer for use loading and storing any
3803 // arguments that may not fit in the registers available for argument
3805 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3807 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3808 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3809 SmallVector<SDValue, 8> MemOpChains;
3811 bool seenFloatArg = false;
3812 // Walk the register/memloc assignments, inserting copies/loads.
3813 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3816 CCValAssign &VA = ArgLocs[i];
3817 SDValue Arg = OutVals[i];
3818 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3820 if (Flags.isByVal()) {
3821 // Argument is an aggregate which is passed by value, thus we need to
3822 // create a copy of it in the local variable space of the current stack
3823 // frame (which is the stack frame of the caller) and pass the address of
3824 // this copy to the callee.
3825 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3826 CCValAssign &ByValVA = ByValArgLocs[j++];
3827 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3829 // Memory reserved in the local variable space of the callers stack frame.
3830 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3832 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3833 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3835 // Create a copy of the argument in the local area of the current
3837 SDValue MemcpyCall =
3838 CreateCopyOfByValArgument(Arg, PtrOff,
3839 CallSeqStart.getNode()->getOperand(0),
3842 // This must go outside the CALLSEQ_START..END.
3843 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3844 CallSeqStart.getNode()->getOperand(1),
3846 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3847 NewCallSeqStart.getNode());
3848 Chain = CallSeqStart = NewCallSeqStart;
3850 // Pass the address of the aggregate copy on the stack either in a
3851 // physical register or in the parameter list area of the current stack
3852 // frame to the callee.
3856 if (VA.isRegLoc()) {
3857 if (Arg.getValueType() == MVT::i1)
3858 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3860 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3861 // Put argument in a physical register.
3862 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3864 // Put argument in the parameter list area of the current stack frame.
3865 assert(VA.isMemLoc());
3866 unsigned LocMemOffset = VA.getLocMemOffset();
3869 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3870 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3872 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3873 MachinePointerInfo(),
3876 // Calculate and remember argument location.
3877 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3883 if (!MemOpChains.empty())
3884 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3886 // Build a sequence of copy-to-reg nodes chained together with token chain
3887 // and flag operands which copy the outgoing args into the appropriate regs.
3889 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3890 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3891 RegsToPass[i].second, InFlag);
3892 InFlag = Chain.getValue(1);
3895 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3898 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3899 SDValue Ops[] = { Chain, InFlag };
3901 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3902 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
3904 InFlag = Chain.getValue(1);
3908 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3909 false, TailCallArguments);
3911 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3912 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3916 // Copy an argument into memory, being careful to do this outside the
3917 // call sequence for the call to which the argument belongs.
3919 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3920 SDValue CallSeqStart,
3921 ISD::ArgFlagsTy Flags,
3924 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3925 CallSeqStart.getNode()->getOperand(0),
3927 // The MEMCPY must go outside the CALLSEQ_START..END.
3928 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3929 CallSeqStart.getNode()->getOperand(1),
3931 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3932 NewCallSeqStart.getNode());
3933 return NewCallSeqStart;
3937 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3938 CallingConv::ID CallConv, bool isVarArg,
3940 const SmallVectorImpl<ISD::OutputArg> &Outs,
3941 const SmallVectorImpl<SDValue> &OutVals,
3942 const SmallVectorImpl<ISD::InputArg> &Ins,
3943 SDLoc dl, SelectionDAG &DAG,
3944 SmallVectorImpl<SDValue> &InVals) const {
3946 bool isLittleEndian = Subtarget.isLittleEndian();
3947 unsigned NumOps = Outs.size();
3949 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3950 unsigned PtrByteSize = 8;
3952 MachineFunction &MF = DAG.getMachineFunction();
3954 // Mark this function as potentially containing a function that contains a
3955 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3956 // and restoring the callers stack pointer in this functions epilog. This is
3957 // done because by tail calling the called function might overwrite the value
3958 // in this function's (MF) stack pointer stack slot 0(SP).
3959 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3960 CallConv == CallingConv::Fast)
3961 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3963 // Count how many bytes are to be pushed on the stack, including the linkage
3964 // area, and parameter passing area. We start with at least 48 bytes, which
3965 // is reserved space for [SP][CR][LR][3 x unused].
3966 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false);
3967 unsigned NumBytes = LinkageSize;
3969 // Add up all the space actually used.
3970 for (unsigned i = 0; i != NumOps; ++i) {
3971 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3972 EVT ArgVT = Outs[i].VT;
3974 // Altivec parameters are padded to a 16 byte boundary.
3975 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3976 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3977 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
3978 NumBytes = ((NumBytes+15)/16)*16;
3980 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3983 // The prolog code of the callee may store up to 8 GPR argument registers to
3984 // the stack, allowing va_start to index over them in memory if its varargs.
3985 // Because we cannot tell if this is needed on the caller side, we have to
3986 // conservatively assume that it is needed. As such, make sure we have at
3987 // least enough stack space for the caller to store the 8 GPRs.
3988 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
3990 // Tail call needs the stack to be aligned.
3991 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3992 CallConv == CallingConv::Fast)
3993 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
3995 // Calculate by how many bytes the stack has to be adjusted in case of tail
3996 // call optimization.
3997 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3999 // To protect arguments on the stack from being clobbered in a tail call,
4000 // force all the loads to happen before doing any other lowering.
4002 Chain = DAG.getStackArgumentTokenFactor(Chain);
4004 // Adjust the stack pointer for the new arguments...
4005 // These operations are automatically eliminated by the prolog/epilog pass
4006 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4008 SDValue CallSeqStart = Chain;
4010 // Load the return address and frame pointer so it can be move somewhere else
4013 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4016 // Set up a copy of the stack pointer for use loading and storing any
4017 // arguments that may not fit in the registers available for argument
4019 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4021 // Figure out which arguments are going to go in registers, and which in
4022 // memory. Also, if this is a vararg function, floating point operations
4023 // must be stored to our stack, and loaded into integer regs as well, if
4024 // any integer regs are available for argument passing.
4025 unsigned ArgOffset = LinkageSize;
4026 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4028 static const MCPhysReg GPR[] = {
4029 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4030 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4032 static const MCPhysReg *FPR = GetFPR();
4034 static const MCPhysReg VR[] = {
4035 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4036 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4038 static const MCPhysReg VSRH[] = {
4039 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4040 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4043 const unsigned NumGPRs = array_lengthof(GPR);
4044 const unsigned NumFPRs = 13;
4045 const unsigned NumVRs = array_lengthof(VR);
4047 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4048 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4050 SmallVector<SDValue, 8> MemOpChains;
4051 for (unsigned i = 0; i != NumOps; ++i) {
4052 SDValue Arg = OutVals[i];
4053 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4055 // PtrOff will be used to store the current argument to the stack if a
4056 // register cannot be found for it.
4059 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4061 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4063 // Promote integers to 64-bit values.
4064 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4065 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4066 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4067 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4070 // FIXME memcpy is used way more than necessary. Correctness first.
4071 // Note: "by value" is code for passing a structure by value, not
4073 if (Flags.isByVal()) {
4074 // Note: Size includes alignment padding, so
4075 // struct x { short a; char b; }
4076 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4077 // These are the proper values we need for right-justifying the
4078 // aggregate in a parameter register.
4079 unsigned Size = Flags.getByValSize();
4081 // An empty aggregate parameter takes up no storage and no
4086 unsigned BVAlign = Flags.getByValAlign();
4088 if (BVAlign % PtrByteSize != 0)
4090 "ByVal alignment is not a multiple of the pointer size");
4092 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
4095 // All aggregates smaller than 8 bytes must be passed right-justified.
4096 if (Size==1 || Size==2 || Size==4) {
4097 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4098 if (GPR_idx != NumGPRs) {
4099 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4100 MachinePointerInfo(), VT,
4102 MemOpChains.push_back(Load.getValue(1));
4103 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4105 ArgOffset += PtrByteSize;
4110 if (GPR_idx == NumGPRs && Size < 8) {
4111 SDValue AddPtr = PtrOff;
4112 if (!isLittleEndian) {
4113 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4114 PtrOff.getValueType());
4115 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4117 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4120 ArgOffset += PtrByteSize;
4123 // Copy entire object into memory. There are cases where gcc-generated
4124 // code assumes it is there, even if it could be put entirely into
4125 // registers. (This is not what the doc says.)
4127 // FIXME: The above statement is likely due to a misunderstanding of the
4128 // documents. All arguments must be copied into the parameter area BY
4129 // THE CALLEE in the event that the callee takes the address of any
4130 // formal argument. That has not yet been implemented. However, it is
4131 // reasonable to use the stack area as a staging area for the register
4134 // Skip this for small aggregates, as we will use the same slot for a
4135 // right-justified copy, below.
4137 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4141 // When a register is available, pass a small aggregate right-justified.
4142 if (Size < 8 && GPR_idx != NumGPRs) {
4143 // The easiest way to get this right-justified in a register
4144 // is to copy the structure into the rightmost portion of a
4145 // local variable slot, then load the whole slot into the
4147 // FIXME: The memcpy seems to produce pretty awful code for
4148 // small aggregates, particularly for packed ones.
4149 // FIXME: It would be preferable to use the slot in the
4150 // parameter save area instead of a new local variable.
4151 SDValue AddPtr = PtrOff;
4152 if (!isLittleEndian) {
4153 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4154 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4156 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4160 // Load the slot into the register.
4161 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4162 MachinePointerInfo(),
4163 false, false, false, 0);
4164 MemOpChains.push_back(Load.getValue(1));
4165 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4167 // Done with this argument.
4168 ArgOffset += PtrByteSize;
4172 // For aggregates larger than PtrByteSize, copy the pieces of the
4173 // object that fit into registers from the parameter save area.
4174 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4175 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4176 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4177 if (GPR_idx != NumGPRs) {
4178 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4179 MachinePointerInfo(),
4180 false, false, false, 0);
4181 MemOpChains.push_back(Load.getValue(1));
4182 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4183 ArgOffset += PtrByteSize;
4185 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4192 switch (Arg.getSimpleValueType().SimpleTy) {
4193 default: llvm_unreachable("Unexpected ValueType for argument!");
4197 if (GPR_idx != NumGPRs) {
4198 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4200 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4201 true, isTailCall, false, MemOpChains,
4202 TailCallArguments, dl);
4204 ArgOffset += PtrByteSize;
4208 if (FPR_idx != NumFPRs) {
4209 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4212 // A single float or an aggregate containing only a single float
4213 // must be passed right-justified in the stack doubleword, and
4214 // in the GPR, if one is available.
4216 if (Arg.getSimpleValueType().SimpleTy == MVT::f32 &&
4218 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4219 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4223 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4224 MachinePointerInfo(), false, false, 0);
4225 MemOpChains.push_back(Store);
4227 // Float varargs are always shadowed in available integer registers
4228 if (GPR_idx != NumGPRs) {
4229 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4230 MachinePointerInfo(), false, false,
4232 MemOpChains.push_back(Load.getValue(1));
4233 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4235 } else if (GPR_idx != NumGPRs)
4236 // If we have any FPRs remaining, we may also have GPRs remaining.
4239 // Single-precision floating-point values are mapped to the
4240 // second (rightmost) word of the stack doubleword.
4241 if (Arg.getValueType() == MVT::f32 && !isLittleEndian) {
4242 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4243 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4246 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4247 true, isTailCall, false, MemOpChains,
4248 TailCallArguments, dl);
4258 // Vectors are aligned to a 16-byte boundary in the argument save area.
4259 while (ArgOffset % 16 !=0) {
4260 ArgOffset += PtrByteSize;
4261 if (GPR_idx != NumGPRs)
4265 // For a varargs call, named arguments go into VRs or on the stack as
4266 // usual; unnamed arguments always go to the stack or the corresponding
4267 // GPRs when within range. For now, we always put the value in both
4268 // locations (or even all three).
4270 // We could elide this store in the case where the object fits
4271 // entirely in R registers. Maybe later.
4272 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4273 DAG.getConstant(ArgOffset, PtrVT));
4274 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4275 MachinePointerInfo(), false, false, 0);
4276 MemOpChains.push_back(Store);
4277 if (VR_idx != NumVRs) {
4278 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4279 MachinePointerInfo(),
4280 false, false, false, 0);
4281 MemOpChains.push_back(Load.getValue(1));
4283 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4284 Arg.getSimpleValueType() == MVT::v2i64) ?
4285 VSRH[VR_idx] : VR[VR_idx];
4288 RegsToPass.push_back(std::make_pair(VReg, Load));
4291 for (unsigned i=0; i<16; i+=PtrByteSize) {
4292 if (GPR_idx == NumGPRs)
4294 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4295 DAG.getConstant(i, PtrVT));
4296 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4297 false, false, false, 0);
4298 MemOpChains.push_back(Load.getValue(1));
4299 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4304 // Non-varargs Altivec params go into VRs or on the stack.
4305 if (VR_idx != NumVRs) {
4306 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4307 Arg.getSimpleValueType() == MVT::v2i64) ?
4308 VSRH[VR_idx] : VR[VR_idx];
4311 RegsToPass.push_back(std::make_pair(VReg, Arg));
4313 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4314 true, isTailCall, true, MemOpChains,
4315 TailCallArguments, dl);
4318 GPR_idx = std::min(GPR_idx + 2, NumGPRs);
4323 if (!MemOpChains.empty())
4324 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4326 // Check if this is an indirect call (MTCTR/BCTRL).
4327 // See PrepareCall() for more information about calls through function
4328 // pointers in the 64-bit SVR4 ABI.
4330 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4331 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4332 // Load r2 into a virtual register and store it to the TOC save area.
4333 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4334 // TOC save area offset.
4335 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
4336 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4337 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4338 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4342 // Build a sequence of copy-to-reg nodes chained together with token chain
4343 // and flag operands which copy the outgoing args into the appropriate regs.
4345 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4346 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4347 RegsToPass[i].second, InFlag);
4348 InFlag = Chain.getValue(1);
4352 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4353 FPOp, true, TailCallArguments);
4355 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4356 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4361 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4362 CallingConv::ID CallConv, bool isVarArg,
4364 const SmallVectorImpl<ISD::OutputArg> &Outs,
4365 const SmallVectorImpl<SDValue> &OutVals,
4366 const SmallVectorImpl<ISD::InputArg> &Ins,
4367 SDLoc dl, SelectionDAG &DAG,
4368 SmallVectorImpl<SDValue> &InVals) const {
4370 unsigned NumOps = Outs.size();
4372 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4373 bool isPPC64 = PtrVT == MVT::i64;
4374 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4376 MachineFunction &MF = DAG.getMachineFunction();
4378 // Mark this function as potentially containing a function that contains a
4379 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4380 // and restoring the callers stack pointer in this functions epilog. This is
4381 // done because by tail calling the called function might overwrite the value
4382 // in this function's (MF) stack pointer stack slot 0(SP).
4383 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4384 CallConv == CallingConv::Fast)
4385 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4387 // Count how many bytes are to be pushed on the stack, including the linkage
4388 // area, and parameter passing area. We start with 24/48 bytes, which is
4389 // prereserved space for [SP][CR][LR][3 x unused].
4390 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true);
4391 unsigned NumBytes = LinkageSize;
4393 // Add up all the space actually used.
4394 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4395 // they all go in registers, but we must reserve stack space for them for
4396 // possible use by the caller. In varargs or 64-bit calls, parameters are
4397 // assigned stack space in order, with padding so Altivec parameters are
4399 unsigned nAltivecParamsAtEnd = 0;
4400 for (unsigned i = 0; i != NumOps; ++i) {
4401 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4402 EVT ArgVT = Outs[i].VT;
4403 // Varargs Altivec parameters are padded to a 16 byte boundary.
4404 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4405 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4406 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4407 if (!isVarArg && !isPPC64) {
4408 // Non-varargs Altivec parameters go after all the non-Altivec
4409 // parameters; handle those later so we know how much padding we need.
4410 nAltivecParamsAtEnd++;
4413 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4414 NumBytes = ((NumBytes+15)/16)*16;
4416 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4419 // Allow for Altivec parameters at the end, if needed.
4420 if (nAltivecParamsAtEnd) {
4421 NumBytes = ((NumBytes+15)/16)*16;
4422 NumBytes += 16*nAltivecParamsAtEnd;
4425 // The prolog code of the callee may store up to 8 GPR argument registers to
4426 // the stack, allowing va_start to index over them in memory if its varargs.
4427 // Because we cannot tell if this is needed on the caller side, we have to
4428 // conservatively assume that it is needed. As such, make sure we have at
4429 // least enough stack space for the caller to store the 8 GPRs.
4430 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4432 // Tail call needs the stack to be aligned.
4433 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4434 CallConv == CallingConv::Fast)
4435 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4437 // Calculate by how many bytes the stack has to be adjusted in case of tail
4438 // call optimization.
4439 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4441 // To protect arguments on the stack from being clobbered in a tail call,
4442 // force all the loads to happen before doing any other lowering.
4444 Chain = DAG.getStackArgumentTokenFactor(Chain);
4446 // Adjust the stack pointer for the new arguments...
4447 // These operations are automatically eliminated by the prolog/epilog pass
4448 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4450 SDValue CallSeqStart = Chain;
4452 // Load the return address and frame pointer so it can be move somewhere else
4455 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4458 // Set up a copy of the stack pointer for use loading and storing any
4459 // arguments that may not fit in the registers available for argument
4463 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4465 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4467 // Figure out which arguments are going to go in registers, and which in
4468 // memory. Also, if this is a vararg function, floating point operations
4469 // must be stored to our stack, and loaded into integer regs as well, if
4470 // any integer regs are available for argument passing.
4471 unsigned ArgOffset = LinkageSize;
4472 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4474 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4475 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4476 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4478 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4479 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4480 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4482 static const MCPhysReg *FPR = GetFPR();
4484 static const MCPhysReg VR[] = {
4485 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4486 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4488 const unsigned NumGPRs = array_lengthof(GPR_32);
4489 const unsigned NumFPRs = 13;
4490 const unsigned NumVRs = array_lengthof(VR);
4492 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4494 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4495 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4497 SmallVector<SDValue, 8> MemOpChains;
4498 for (unsigned i = 0; i != NumOps; ++i) {
4499 SDValue Arg = OutVals[i];
4500 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4502 // PtrOff will be used to store the current argument to the stack if a
4503 // register cannot be found for it.
4506 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4508 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4510 // On PPC64, promote integers to 64-bit values.
4511 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4512 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4513 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4514 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4517 // FIXME memcpy is used way more than necessary. Correctness first.
4518 // Note: "by value" is code for passing a structure by value, not
4520 if (Flags.isByVal()) {
4521 unsigned Size = Flags.getByValSize();
4522 // Very small objects are passed right-justified. Everything else is
4523 // passed left-justified.
4524 if (Size==1 || Size==2) {
4525 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4526 if (GPR_idx != NumGPRs) {
4527 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4528 MachinePointerInfo(), VT,
4530 MemOpChains.push_back(Load.getValue(1));
4531 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4533 ArgOffset += PtrByteSize;
4535 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4536 PtrOff.getValueType());
4537 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4538 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4541 ArgOffset += PtrByteSize;
4545 // Copy entire object into memory. There are cases where gcc-generated
4546 // code assumes it is there, even if it could be put entirely into
4547 // registers. (This is not what the doc says.)
4548 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4552 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4553 // copy the pieces of the object that fit into registers from the
4554 // parameter save area.
4555 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4556 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4557 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4558 if (GPR_idx != NumGPRs) {
4559 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4560 MachinePointerInfo(),
4561 false, false, false, 0);
4562 MemOpChains.push_back(Load.getValue(1));
4563 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4564 ArgOffset += PtrByteSize;
4566 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4573 switch (Arg.getSimpleValueType().SimpleTy) {
4574 default: llvm_unreachable("Unexpected ValueType for argument!");
4578 if (GPR_idx != NumGPRs) {
4579 if (Arg.getValueType() == MVT::i1)
4580 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4582 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4584 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4585 isPPC64, isTailCall, false, MemOpChains,
4586 TailCallArguments, dl);
4588 ArgOffset += PtrByteSize;
4592 if (FPR_idx != NumFPRs) {
4593 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4596 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4597 MachinePointerInfo(), false, false, 0);
4598 MemOpChains.push_back(Store);
4600 // Float varargs are always shadowed in available integer registers
4601 if (GPR_idx != NumGPRs) {
4602 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4603 MachinePointerInfo(), false, false,
4605 MemOpChains.push_back(Load.getValue(1));
4606 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4608 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4609 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4610 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4611 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4612 MachinePointerInfo(),
4613 false, false, false, 0);
4614 MemOpChains.push_back(Load.getValue(1));
4615 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4618 // If we have any FPRs remaining, we may also have GPRs remaining.
4619 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4621 if (GPR_idx != NumGPRs)
4623 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4624 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4628 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4629 isPPC64, isTailCall, false, MemOpChains,
4630 TailCallArguments, dl);
4634 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4641 // These go aligned on the stack, or in the corresponding R registers
4642 // when within range. The Darwin PPC ABI doc claims they also go in
4643 // V registers; in fact gcc does this only for arguments that are
4644 // prototyped, not for those that match the ... We do it for all
4645 // arguments, seems to work.
4646 while (ArgOffset % 16 !=0) {
4647 ArgOffset += PtrByteSize;
4648 if (GPR_idx != NumGPRs)
4651 // We could elide this store in the case where the object fits
4652 // entirely in R registers. Maybe later.
4653 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4654 DAG.getConstant(ArgOffset, PtrVT));
4655 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4656 MachinePointerInfo(), false, false, 0);
4657 MemOpChains.push_back(Store);
4658 if (VR_idx != NumVRs) {
4659 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4660 MachinePointerInfo(),
4661 false, false, false, 0);
4662 MemOpChains.push_back(Load.getValue(1));
4663 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4666 for (unsigned i=0; i<16; i+=PtrByteSize) {
4667 if (GPR_idx == NumGPRs)
4669 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4670 DAG.getConstant(i, PtrVT));
4671 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4672 false, false, false, 0);
4673 MemOpChains.push_back(Load.getValue(1));
4674 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4679 // Non-varargs Altivec params generally go in registers, but have
4680 // stack space allocated at the end.
4681 if (VR_idx != NumVRs) {
4682 // Doesn't have GPR space allocated.
4683 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4684 } else if (nAltivecParamsAtEnd==0) {
4685 // We are emitting Altivec params in order.
4686 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4687 isPPC64, isTailCall, true, MemOpChains,
4688 TailCallArguments, dl);
4694 // If all Altivec parameters fit in registers, as they usually do,
4695 // they get stack space following the non-Altivec parameters. We
4696 // don't track this here because nobody below needs it.
4697 // If there are more Altivec parameters than fit in registers emit
4699 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4701 // Offset is aligned; skip 1st 12 params which go in V registers.
4702 ArgOffset = ((ArgOffset+15)/16)*16;
4704 for (unsigned i = 0; i != NumOps; ++i) {
4705 SDValue Arg = OutVals[i];
4706 EVT ArgType = Outs[i].VT;
4707 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4708 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4711 // We are emitting Altivec params in order.
4712 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4713 isPPC64, isTailCall, true, MemOpChains,
4714 TailCallArguments, dl);
4721 if (!MemOpChains.empty())
4722 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4724 // On Darwin, R12 must contain the address of an indirect callee. This does
4725 // not mean the MTCTR instruction must use R12; it's easier to model this as
4726 // an extra parameter, so do that.
4728 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4729 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4730 !isBLACompatibleAddress(Callee, DAG))
4731 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4732 PPC::R12), Callee));
4734 // Build a sequence of copy-to-reg nodes chained together with token chain
4735 // and flag operands which copy the outgoing args into the appropriate regs.
4737 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4738 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4739 RegsToPass[i].second, InFlag);
4740 InFlag = Chain.getValue(1);
4744 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4745 FPOp, true, TailCallArguments);
4747 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4748 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4753 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4754 MachineFunction &MF, bool isVarArg,
4755 const SmallVectorImpl<ISD::OutputArg> &Outs,
4756 LLVMContext &Context) const {
4757 SmallVector<CCValAssign, 16> RVLocs;
4758 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4760 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4764 PPCTargetLowering::LowerReturn(SDValue Chain,
4765 CallingConv::ID CallConv, bool isVarArg,
4766 const SmallVectorImpl<ISD::OutputArg> &Outs,
4767 const SmallVectorImpl<SDValue> &OutVals,
4768 SDLoc dl, SelectionDAG &DAG) const {
4770 SmallVector<CCValAssign, 16> RVLocs;
4771 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4772 getTargetMachine(), RVLocs, *DAG.getContext());
4773 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4776 SmallVector<SDValue, 4> RetOps(1, Chain);
4778 // Copy the result values into the output registers.
4779 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4780 CCValAssign &VA = RVLocs[i];
4781 assert(VA.isRegLoc() && "Can only return in registers!");
4783 SDValue Arg = OutVals[i];
4785 switch (VA.getLocInfo()) {
4786 default: llvm_unreachable("Unknown loc info!");
4787 case CCValAssign::Full: break;
4788 case CCValAssign::AExt:
4789 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4791 case CCValAssign::ZExt:
4792 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4794 case CCValAssign::SExt:
4795 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4799 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4800 Flag = Chain.getValue(1);
4801 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4804 RetOps[0] = Chain; // Update chain.
4806 // Add the flag if we have it.
4808 RetOps.push_back(Flag);
4810 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
4813 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4814 const PPCSubtarget &Subtarget) const {
4815 // When we pop the dynamic allocation we need to restore the SP link.
4818 // Get the corect type for pointers.
4819 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4821 // Construct the stack pointer operand.
4822 bool isPPC64 = Subtarget.isPPC64();
4823 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4824 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4826 // Get the operands for the STACKRESTORE.
4827 SDValue Chain = Op.getOperand(0);
4828 SDValue SaveSP = Op.getOperand(1);
4830 // Load the old link SP.
4831 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4832 MachinePointerInfo(),
4833 false, false, false, 0);
4835 // Restore the stack pointer.
4836 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4838 // Store the old link SP.
4839 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4846 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4847 MachineFunction &MF = DAG.getMachineFunction();
4848 bool isPPC64 = Subtarget.isPPC64();
4849 bool isDarwinABI = Subtarget.isDarwinABI();
4850 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4852 // Get current frame pointer save index. The users of this index will be
4853 // primarily DYNALLOC instructions.
4854 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4855 int RASI = FI->getReturnAddrSaveIndex();
4857 // If the frame pointer save index hasn't been defined yet.
4859 // Find out what the fix offset of the frame pointer save area.
4860 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4861 // Allocate the frame index for frame pointer save area.
4862 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4864 FI->setReturnAddrSaveIndex(RASI);
4866 return DAG.getFrameIndex(RASI, PtrVT);
4870 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4871 MachineFunction &MF = DAG.getMachineFunction();
4872 bool isPPC64 = Subtarget.isPPC64();
4873 bool isDarwinABI = Subtarget.isDarwinABI();
4874 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4876 // Get current frame pointer save index. The users of this index will be
4877 // primarily DYNALLOC instructions.
4878 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4879 int FPSI = FI->getFramePointerSaveIndex();
4881 // If the frame pointer save index hasn't been defined yet.
4883 // Find out what the fix offset of the frame pointer save area.
4884 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4887 // Allocate the frame index for frame pointer save area.
4888 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4890 FI->setFramePointerSaveIndex(FPSI);
4892 return DAG.getFrameIndex(FPSI, PtrVT);
4895 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4897 const PPCSubtarget &Subtarget) const {
4899 SDValue Chain = Op.getOperand(0);
4900 SDValue Size = Op.getOperand(1);
4903 // Get the corect type for pointers.
4904 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4906 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4907 DAG.getConstant(0, PtrVT), Size);
4908 // Construct a node for the frame pointer save index.
4909 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4910 // Build a DYNALLOC node.
4911 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4912 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4913 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
4916 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4917 SelectionDAG &DAG) const {
4919 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4920 DAG.getVTList(MVT::i32, MVT::Other),
4921 Op.getOperand(0), Op.getOperand(1));
4924 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4925 SelectionDAG &DAG) const {
4927 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4928 Op.getOperand(0), Op.getOperand(1));
4931 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4932 assert(Op.getValueType() == MVT::i1 &&
4933 "Custom lowering only for i1 loads");
4935 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4938 LoadSDNode *LD = cast<LoadSDNode>(Op);
4940 SDValue Chain = LD->getChain();
4941 SDValue BasePtr = LD->getBasePtr();
4942 MachineMemOperand *MMO = LD->getMemOperand();
4944 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4945 BasePtr, MVT::i8, MMO);
4946 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4948 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4949 return DAG.getMergeValues(Ops, dl);
4952 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4953 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4954 "Custom lowering only for i1 stores");
4956 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4959 StoreSDNode *ST = cast<StoreSDNode>(Op);
4961 SDValue Chain = ST->getChain();
4962 SDValue BasePtr = ST->getBasePtr();
4963 SDValue Value = ST->getValue();
4964 MachineMemOperand *MMO = ST->getMemOperand();
4966 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4967 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4970 // FIXME: Remove this once the ANDI glue bug is fixed:
4971 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4972 assert(Op.getValueType() == MVT::i1 &&
4973 "Custom lowering only for i1 results");
4976 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
4980 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4982 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4983 // Not FP? Not a fsel.
4984 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4985 !Op.getOperand(2).getValueType().isFloatingPoint())
4988 // We might be able to do better than this under some circumstances, but in
4989 // general, fsel-based lowering of select is a finite-math-only optimization.
4990 // For more information, see section F.3 of the 2.06 ISA specification.
4991 if (!DAG.getTarget().Options.NoInfsFPMath ||
4992 !DAG.getTarget().Options.NoNaNsFPMath)
4995 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4997 EVT ResVT = Op.getValueType();
4998 EVT CmpVT = Op.getOperand(0).getValueType();
4999 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5000 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5003 // If the RHS of the comparison is a 0.0, we don't need to do the
5004 // subtraction at all.
5006 if (isFloatingPointZero(RHS))
5008 default: break; // SETUO etc aren't handled by fsel.
5012 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5013 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5014 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5015 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5016 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5017 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5018 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5021 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5024 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5025 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5026 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5029 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5032 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5033 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5034 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5035 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5040 default: break; // SETUO etc aren't handled by fsel.
5044 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5045 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5046 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5047 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5048 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5049 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5050 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5051 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5054 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5055 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5056 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5057 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5060 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5061 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5062 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5063 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5066 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5067 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5068 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5069 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5072 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5073 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5074 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5075 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5080 // FIXME: Split this code up when LegalizeDAGTypes lands.
5081 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5083 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5084 SDValue Src = Op.getOperand(0);
5085 if (Src.getValueType() == MVT::f32)
5086 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5089 switch (Op.getSimpleValueType().SimpleTy) {
5090 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5092 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5093 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5098 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5099 "i64 FP_TO_UINT is supported only with FPCVT");
5100 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5106 // Convert the FP value to an int value through memory.
5107 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5108 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5109 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5110 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5111 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5113 // Emit a store to the stack slot.
5116 MachineFunction &MF = DAG.getMachineFunction();
5117 MachineMemOperand *MMO =
5118 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5119 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5120 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5121 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5123 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5124 MPI, false, false, 0);
5126 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5128 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5129 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5130 DAG.getConstant(4, FIPtr.getValueType()));
5131 MPI = MachinePointerInfo();
5134 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5135 false, false, false, 0);
5138 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5139 SelectionDAG &DAG) const {
5141 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5142 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5145 if (Op.getOperand(0).getValueType() == MVT::i1)
5146 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5147 DAG.getConstantFP(1.0, Op.getValueType()),
5148 DAG.getConstantFP(0.0, Op.getValueType()));
5150 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5151 "UINT_TO_FP is supported only with FPCVT");
5153 // If we have FCFIDS, then use it when converting to single-precision.
5154 // Otherwise, convert to double-precision and then round.
5155 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5156 (Op.getOpcode() == ISD::UINT_TO_FP ?
5157 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5158 (Op.getOpcode() == ISD::UINT_TO_FP ?
5159 PPCISD::FCFIDU : PPCISD::FCFID);
5160 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5161 MVT::f32 : MVT::f64;
5163 if (Op.getOperand(0).getValueType() == MVT::i64) {
5164 SDValue SINT = Op.getOperand(0);
5165 // When converting to single-precision, we actually need to convert
5166 // to double-precision first and then round to single-precision.
5167 // To avoid double-rounding effects during that operation, we have
5168 // to prepare the input operand. Bits that might be truncated when
5169 // converting to double-precision are replaced by a bit that won't
5170 // be lost at this stage, but is below the single-precision rounding
5173 // However, if -enable-unsafe-fp-math is in effect, accept double
5174 // rounding to avoid the extra overhead.
5175 if (Op.getValueType() == MVT::f32 &&
5176 !Subtarget.hasFPCVT() &&
5177 !DAG.getTarget().Options.UnsafeFPMath) {
5179 // Twiddle input to make sure the low 11 bits are zero. (If this
5180 // is the case, we are guaranteed the value will fit into the 53 bit
5181 // mantissa of an IEEE double-precision value without rounding.)
5182 // If any of those low 11 bits were not zero originally, make sure
5183 // bit 12 (value 2048) is set instead, so that the final rounding
5184 // to single-precision gets the correct result.
5185 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5186 SINT, DAG.getConstant(2047, MVT::i64));
5187 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5188 Round, DAG.getConstant(2047, MVT::i64));
5189 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5190 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5191 Round, DAG.getConstant(-2048, MVT::i64));
5193 // However, we cannot use that value unconditionally: if the magnitude
5194 // of the input value is small, the bit-twiddling we did above might
5195 // end up visibly changing the output. Fortunately, in that case, we
5196 // don't need to twiddle bits since the original input will convert
5197 // exactly to double-precision floating-point already. Therefore,
5198 // construct a conditional to use the original value if the top 11
5199 // bits are all sign-bit copies, and use the rounded value computed
5201 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5202 SINT, DAG.getConstant(53, MVT::i32));
5203 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5204 Cond, DAG.getConstant(1, MVT::i64));
5205 Cond = DAG.getSetCC(dl, MVT::i32,
5206 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5208 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5211 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5212 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5214 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5215 FP = DAG.getNode(ISD::FP_ROUND, dl,
5216 MVT::f32, FP, DAG.getIntPtrConstant(0));
5220 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5221 "Unhandled INT_TO_FP type in custom expander!");
5222 // Since we only generate this in 64-bit mode, we can take advantage of
5223 // 64-bit registers. In particular, sign extend the input value into the
5224 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5225 // then lfd it and fcfid it.
5226 MachineFunction &MF = DAG.getMachineFunction();
5227 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5228 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5231 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5232 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5233 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5235 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5236 MachinePointerInfo::getFixedStack(FrameIdx),
5239 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5240 "Expected an i32 store");
5241 MachineMemOperand *MMO =
5242 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5243 MachineMemOperand::MOLoad, 4, 4);
5244 SDValue Ops[] = { Store, FIdx };
5245 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5246 PPCISD::LFIWZX : PPCISD::LFIWAX,
5247 dl, DAG.getVTList(MVT::f64, MVT::Other),
5248 Ops, MVT::i32, MMO);
5250 assert(Subtarget.isPPC64() &&
5251 "i32->FP without LFIWAX supported only on PPC64");
5253 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5254 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5256 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5259 // STD the extended value into the stack slot.
5260 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5261 MachinePointerInfo::getFixedStack(FrameIdx),
5264 // Load the value as a double.
5265 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5266 MachinePointerInfo::getFixedStack(FrameIdx),
5267 false, false, false, 0);
5270 // FCFID it and return it.
5271 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5272 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5273 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5277 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5278 SelectionDAG &DAG) const {
5281 The rounding mode is in bits 30:31 of FPSR, and has the following
5288 FLT_ROUNDS, on the other hand, expects the following:
5295 To perform the conversion, we do:
5296 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5299 MachineFunction &MF = DAG.getMachineFunction();
5300 EVT VT = Op.getValueType();
5301 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5303 // Save FP Control Word to register
5305 MVT::f64, // return register
5306 MVT::Glue // unused in this context
5308 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5310 // Save FP register to stack slot
5311 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5312 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5313 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5314 StackSlot, MachinePointerInfo(), false, false,0);
5316 // Load FP Control Word from low 32 bits of stack slot.
5317 SDValue Four = DAG.getConstant(4, PtrVT);
5318 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5319 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5320 false, false, false, 0);
5322 // Transform as necessary
5324 DAG.getNode(ISD::AND, dl, MVT::i32,
5325 CWD, DAG.getConstant(3, MVT::i32));
5327 DAG.getNode(ISD::SRL, dl, MVT::i32,
5328 DAG.getNode(ISD::AND, dl, MVT::i32,
5329 DAG.getNode(ISD::XOR, dl, MVT::i32,
5330 CWD, DAG.getConstant(3, MVT::i32)),
5331 DAG.getConstant(3, MVT::i32)),
5332 DAG.getConstant(1, MVT::i32));
5335 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5337 return DAG.getNode((VT.getSizeInBits() < 16 ?
5338 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5341 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5342 EVT VT = Op.getValueType();
5343 unsigned BitWidth = VT.getSizeInBits();
5345 assert(Op.getNumOperands() == 3 &&
5346 VT == Op.getOperand(1).getValueType() &&
5349 // Expand into a bunch of logical ops. Note that these ops
5350 // depend on the PPC behavior for oversized shift amounts.
5351 SDValue Lo = Op.getOperand(0);
5352 SDValue Hi = Op.getOperand(1);
5353 SDValue Amt = Op.getOperand(2);
5354 EVT AmtVT = Amt.getValueType();
5356 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5357 DAG.getConstant(BitWidth, AmtVT), Amt);
5358 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5359 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5360 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5361 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5362 DAG.getConstant(-BitWidth, AmtVT));
5363 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5364 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5365 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5366 SDValue OutOps[] = { OutLo, OutHi };
5367 return DAG.getMergeValues(OutOps, dl);
5370 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5371 EVT VT = Op.getValueType();
5373 unsigned BitWidth = VT.getSizeInBits();
5374 assert(Op.getNumOperands() == 3 &&
5375 VT == Op.getOperand(1).getValueType() &&
5378 // Expand into a bunch of logical ops. Note that these ops
5379 // depend on the PPC behavior for oversized shift amounts.
5380 SDValue Lo = Op.getOperand(0);
5381 SDValue Hi = Op.getOperand(1);
5382 SDValue Amt = Op.getOperand(2);
5383 EVT AmtVT = Amt.getValueType();
5385 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5386 DAG.getConstant(BitWidth, AmtVT), Amt);
5387 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5388 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5389 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5390 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5391 DAG.getConstant(-BitWidth, AmtVT));
5392 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5393 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5394 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5395 SDValue OutOps[] = { OutLo, OutHi };
5396 return DAG.getMergeValues(OutOps, dl);
5399 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5401 EVT VT = Op.getValueType();
5402 unsigned BitWidth = VT.getSizeInBits();
5403 assert(Op.getNumOperands() == 3 &&
5404 VT == Op.getOperand(1).getValueType() &&
5407 // Expand into a bunch of logical ops, followed by a select_cc.
5408 SDValue Lo = Op.getOperand(0);
5409 SDValue Hi = Op.getOperand(1);
5410 SDValue Amt = Op.getOperand(2);
5411 EVT AmtVT = Amt.getValueType();
5413 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5414 DAG.getConstant(BitWidth, AmtVT), Amt);
5415 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5416 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5417 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5418 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5419 DAG.getConstant(-BitWidth, AmtVT));
5420 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5421 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5422 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5423 Tmp4, Tmp6, ISD::SETLE);
5424 SDValue OutOps[] = { OutLo, OutHi };
5425 return DAG.getMergeValues(OutOps, dl);
5428 //===----------------------------------------------------------------------===//
5429 // Vector related lowering.
5432 /// BuildSplatI - Build a canonical splati of Val with an element size of
5433 /// SplatSize. Cast the result to VT.
5434 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5435 SelectionDAG &DAG, SDLoc dl) {
5436 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5438 static const EVT VTys[] = { // canonical VT to use for each size.
5439 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5442 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5444 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5448 EVT CanonicalVT = VTys[SplatSize-1];
5450 // Build a canonical splat for this value.
5451 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5452 SmallVector<SDValue, 8> Ops;
5453 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5454 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5455 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5458 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5459 /// specified intrinsic ID.
5460 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5461 SelectionDAG &DAG, SDLoc dl,
5462 EVT DestVT = MVT::Other) {
5463 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5464 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5465 DAG.getConstant(IID, MVT::i32), Op);
5468 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5469 /// specified intrinsic ID.
5470 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5471 SelectionDAG &DAG, SDLoc dl,
5472 EVT DestVT = MVT::Other) {
5473 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5474 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5475 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5478 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5479 /// specified intrinsic ID.
5480 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5481 SDValue Op2, SelectionDAG &DAG,
5482 SDLoc dl, EVT DestVT = MVT::Other) {
5483 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5484 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5485 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5489 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5490 /// amount. The result has the specified value type.
5491 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5492 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5493 // Force LHS/RHS to be the right type.
5494 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5495 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5498 for (unsigned i = 0; i != 16; ++i)
5500 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5501 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5504 // If this is a case we can't handle, return null and let the default
5505 // expansion code take care of it. If we CAN select this case, and if it
5506 // selects to a single instruction, return Op. Otherwise, if we can codegen
5507 // this case more efficiently than a constant pool load, lower it to the
5508 // sequence of ops that should be used.
5509 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5510 SelectionDAG &DAG) const {
5512 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5513 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5515 // Check if this is a splat of a constant value.
5516 APInt APSplatBits, APSplatUndef;
5517 unsigned SplatBitSize;
5519 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5520 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5523 unsigned SplatBits = APSplatBits.getZExtValue();
5524 unsigned SplatUndef = APSplatUndef.getZExtValue();
5525 unsigned SplatSize = SplatBitSize / 8;
5527 // First, handle single instruction cases.
5530 if (SplatBits == 0) {
5531 // Canonicalize all zero vectors to be v4i32.
5532 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5533 SDValue Z = DAG.getConstant(0, MVT::i32);
5534 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5535 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5540 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5541 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5543 if (SextVal >= -16 && SextVal <= 15)
5544 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5547 // Two instruction sequences.
5549 // If this value is in the range [-32,30] and is even, use:
5550 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5551 // If this value is in the range [17,31] and is odd, use:
5552 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5553 // If this value is in the range [-31,-17] and is odd, use:
5554 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5555 // Note the last two are three-instruction sequences.
5556 if (SextVal >= -32 && SextVal <= 31) {
5557 // To avoid having these optimizations undone by constant folding,
5558 // we convert to a pseudo that will be expanded later into one of
5560 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5561 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5562 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5563 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5564 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5565 if (VT == Op.getValueType())
5568 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5571 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5572 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5574 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5575 // Make -1 and vspltisw -1:
5576 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5578 // Make the VSLW intrinsic, computing 0x8000_0000.
5579 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5582 // xor by OnesV to invert it.
5583 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5584 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5587 // The remaining cases assume either big endian element order or
5588 // a splat-size that equates to the element size of the vector
5589 // to be built. An example that doesn't work for little endian is
5590 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5591 // and a vector element size of 16 bits. The code below will
5592 // produce the vector in big endian element order, which for little
5593 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5595 // For now, just avoid these optimizations in that case.
5596 // FIXME: Develop correct optimizations for LE with mismatched
5597 // splat and element sizes.
5599 if (Subtarget.isLittleEndian() &&
5600 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5603 // Check to see if this is a wide variety of vsplti*, binop self cases.
5604 static const signed char SplatCsts[] = {
5605 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5606 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5609 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5610 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5611 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5612 int i = SplatCsts[idx];
5614 // Figure out what shift amount will be used by altivec if shifted by i in
5616 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5618 // vsplti + shl self.
5619 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5620 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5621 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5622 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5623 Intrinsic::ppc_altivec_vslw
5625 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5626 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5629 // vsplti + srl self.
5630 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5631 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5632 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5633 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5634 Intrinsic::ppc_altivec_vsrw
5636 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5637 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5640 // vsplti + sra self.
5641 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5642 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5643 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5644 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5645 Intrinsic::ppc_altivec_vsraw
5647 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5648 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5651 // vsplti + rol self.
5652 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5653 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5654 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5655 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5656 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5657 Intrinsic::ppc_altivec_vrlw
5659 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5660 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5663 // t = vsplti c, result = vsldoi t, t, 1
5664 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5665 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5666 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5668 // t = vsplti c, result = vsldoi t, t, 2
5669 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5670 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5671 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5673 // t = vsplti c, result = vsldoi t, t, 3
5674 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5675 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5676 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5683 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5684 /// the specified operations to build the shuffle.
5685 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5686 SDValue RHS, SelectionDAG &DAG,
5688 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5689 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5690 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5693 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5705 if (OpNum == OP_COPY) {
5706 if (LHSID == (1*9+2)*9+3) return LHS;
5707 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5711 SDValue OpLHS, OpRHS;
5712 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5713 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5717 default: llvm_unreachable("Unknown i32 permute!");
5719 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5720 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5721 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5722 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5725 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5726 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5727 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5728 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5731 for (unsigned i = 0; i != 16; ++i)
5732 ShufIdxs[i] = (i&3)+0;
5735 for (unsigned i = 0; i != 16; ++i)
5736 ShufIdxs[i] = (i&3)+4;
5739 for (unsigned i = 0; i != 16; ++i)
5740 ShufIdxs[i] = (i&3)+8;
5743 for (unsigned i = 0; i != 16; ++i)
5744 ShufIdxs[i] = (i&3)+12;
5747 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5749 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5751 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5753 EVT VT = OpLHS.getValueType();
5754 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5755 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5756 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5757 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5760 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5761 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5762 /// return the code it can be lowered into. Worst case, it can always be
5763 /// lowered into a vperm.
5764 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5765 SelectionDAG &DAG) const {
5767 SDValue V1 = Op.getOperand(0);
5768 SDValue V2 = Op.getOperand(1);
5769 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5770 EVT VT = Op.getValueType();
5771 bool isLittleEndian = Subtarget.isLittleEndian();
5773 // Cases that are handled by instructions that take permute immediates
5774 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5775 // selected by the instruction selector.
5776 if (V2.getOpcode() == ISD::UNDEF) {
5777 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5778 PPC::isSplatShuffleMask(SVOp, 2) ||
5779 PPC::isSplatShuffleMask(SVOp, 4) ||
5780 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
5781 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
5782 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
5783 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
5784 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
5785 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
5786 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
5787 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
5788 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
5793 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5794 // and produce a fixed permutation. If any of these match, do not lower to
5796 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
5797 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
5798 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
5799 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
5800 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
5801 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
5802 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
5803 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
5804 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
5807 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5808 // perfect shuffle table to emit an optimal matching sequence.
5809 ArrayRef<int> PermMask = SVOp->getMask();
5811 unsigned PFIndexes[4];
5812 bool isFourElementShuffle = true;
5813 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5814 unsigned EltNo = 8; // Start out undef.
5815 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5816 if (PermMask[i*4+j] < 0)
5817 continue; // Undef, ignore it.
5819 unsigned ByteSource = PermMask[i*4+j];
5820 if ((ByteSource & 3) != j) {
5821 isFourElementShuffle = false;
5826 EltNo = ByteSource/4;
5827 } else if (EltNo != ByteSource/4) {
5828 isFourElementShuffle = false;
5832 PFIndexes[i] = EltNo;
5835 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5836 // perfect shuffle vector to determine if it is cost effective to do this as
5837 // discrete instructions, or whether we should use a vperm.
5838 // For now, we skip this for little endian until such time as we have a
5839 // little-endian perfect shuffle table.
5840 if (isFourElementShuffle && !isLittleEndian) {
5841 // Compute the index in the perfect shuffle table.
5842 unsigned PFTableIndex =
5843 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5845 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5846 unsigned Cost = (PFEntry >> 30);
5848 // Determining when to avoid vperm is tricky. Many things affect the cost
5849 // of vperm, particularly how many times the perm mask needs to be computed.
5850 // For example, if the perm mask can be hoisted out of a loop or is already
5851 // used (perhaps because there are multiple permutes with the same shuffle
5852 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5853 // the loop requires an extra register.
5855 // As a compromise, we only emit discrete instructions if the shuffle can be
5856 // generated in 3 or fewer operations. When we have loop information
5857 // available, if this block is within a loop, we should avoid using vperm
5858 // for 3-operation perms and use a constant pool load instead.
5860 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5863 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5864 // vector that will get spilled to the constant pool.
5865 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5867 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5868 // that it is in input element units, not in bytes. Convert now.
5870 // For little endian, the order of the input vectors is reversed, and
5871 // the permutation mask is complemented with respect to 31. This is
5872 // necessary to produce proper semantics with the big-endian-biased vperm
5874 EVT EltVT = V1.getValueType().getVectorElementType();
5875 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5877 SmallVector<SDValue, 16> ResultMask;
5878 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5879 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5881 for (unsigned j = 0; j != BytesPerElement; ++j)
5883 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
5886 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5890 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5893 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5896 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5900 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5901 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5902 /// information about the intrinsic.
5903 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5905 unsigned IntrinsicID =
5906 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5909 switch (IntrinsicID) {
5910 default: return false;
5911 // Comparison predicates.
5912 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5913 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5914 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5915 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5916 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5917 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5918 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5919 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5920 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5921 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5922 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5923 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5924 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5926 // Normal Comparisons.
5927 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5928 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5929 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5930 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5931 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5932 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5933 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5934 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5935 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5936 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5937 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5938 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5939 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5944 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5945 /// lower, do it, otherwise return null.
5946 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5947 SelectionDAG &DAG) const {
5948 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5949 // opcode number of the comparison.
5953 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5954 return SDValue(); // Don't custom lower most intrinsics.
5956 // If this is a non-dot comparison, make the VCMP node and we are done.
5958 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5959 Op.getOperand(1), Op.getOperand(2),
5960 DAG.getConstant(CompareOpc, MVT::i32));
5961 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5964 // Create the PPCISD altivec 'dot' comparison node.
5966 Op.getOperand(2), // LHS
5967 Op.getOperand(3), // RHS
5968 DAG.getConstant(CompareOpc, MVT::i32)
5970 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5971 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
5973 // Now that we have the comparison, emit a copy from the CR to a GPR.
5974 // This is flagged to the above dot comparison.
5975 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5976 DAG.getRegister(PPC::CR6, MVT::i32),
5977 CompNode.getValue(1));
5979 // Unpack the result based on how the target uses it.
5980 unsigned BitNo; // Bit # of CR6.
5981 bool InvertBit; // Invert result?
5982 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5983 default: // Can't happen, don't crash on invalid number though.
5984 case 0: // Return the value of the EQ bit of CR6.
5985 BitNo = 0; InvertBit = false;
5987 case 1: // Return the inverted value of the EQ bit of CR6.
5988 BitNo = 0; InvertBit = true;
5990 case 2: // Return the value of the LT bit of CR6.
5991 BitNo = 2; InvertBit = false;
5993 case 3: // Return the inverted value of the LT bit of CR6.
5994 BitNo = 2; InvertBit = true;
5998 // Shift the bit into the low position.
5999 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6000 DAG.getConstant(8-(3-BitNo), MVT::i32));
6002 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6003 DAG.getConstant(1, MVT::i32));
6005 // If we are supposed to, toggle the bit.
6007 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6008 DAG.getConstant(1, MVT::i32));
6012 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6013 SelectionDAG &DAG) const {
6015 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6016 // instructions), but for smaller types, we need to first extend up to v2i32
6017 // before doing going farther.
6018 if (Op.getValueType() == MVT::v2i64) {
6019 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6020 if (ExtVT != MVT::v2i32) {
6021 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6022 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6023 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6024 ExtVT.getVectorElementType(), 4)));
6025 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6026 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6027 DAG.getValueType(MVT::v2i32));
6036 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6037 SelectionDAG &DAG) const {
6039 // Create a stack slot that is 16-byte aligned.
6040 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6041 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6042 EVT PtrVT = getPointerTy();
6043 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6045 // Store the input value into Value#0 of the stack slot.
6046 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6047 Op.getOperand(0), FIdx, MachinePointerInfo(),
6050 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6051 false, false, false, 0);
6054 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6056 if (Op.getValueType() == MVT::v4i32) {
6057 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6059 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6060 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6062 SDValue RHSSwap = // = vrlw RHS, 16
6063 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6065 // Shrinkify inputs to v8i16.
6066 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6067 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6068 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6070 // Low parts multiplied together, generating 32-bit results (we ignore the
6072 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6073 LHS, RHS, DAG, dl, MVT::v4i32);
6075 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6076 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6077 // Shift the high parts up 16 bits.
6078 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6080 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6081 } else if (Op.getValueType() == MVT::v8i16) {
6082 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6084 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6086 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6087 LHS, RHS, Zero, DAG, dl);
6088 } else if (Op.getValueType() == MVT::v16i8) {
6089 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6090 bool isLittleEndian = Subtarget.isLittleEndian();
6092 // Multiply the even 8-bit parts, producing 16-bit sums.
6093 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6094 LHS, RHS, DAG, dl, MVT::v8i16);
6095 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6097 // Multiply the odd 8-bit parts, producing 16-bit sums.
6098 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6099 LHS, RHS, DAG, dl, MVT::v8i16);
6100 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6102 // Merge the results together. Because vmuleub and vmuloub are
6103 // instructions with a big-endian bias, we must reverse the
6104 // element numbering and reverse the meaning of "odd" and "even"
6105 // when generating little endian code.
6107 for (unsigned i = 0; i != 8; ++i) {
6108 if (isLittleEndian) {
6110 Ops[i*2+1] = 2*i+16;
6113 Ops[i*2+1] = 2*i+1+16;
6117 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6119 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6121 llvm_unreachable("Unknown mul to lower!");
6125 /// LowerOperation - Provide custom lowering hooks for some operations.
6127 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6128 switch (Op.getOpcode()) {
6129 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6130 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6131 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6132 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6133 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6134 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6135 case ISD::SETCC: return LowerSETCC(Op, DAG);
6136 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6137 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6139 return LowerVASTART(Op, DAG, Subtarget);
6142 return LowerVAARG(Op, DAG, Subtarget);
6145 return LowerVACOPY(Op, DAG, Subtarget);
6147 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6148 case ISD::DYNAMIC_STACKALLOC:
6149 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6151 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6152 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6154 case ISD::LOAD: return LowerLOAD(Op, DAG);
6155 case ISD::STORE: return LowerSTORE(Op, DAG);
6156 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6157 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6158 case ISD::FP_TO_UINT:
6159 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6161 case ISD::UINT_TO_FP:
6162 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6163 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6165 // Lower 64-bit shifts.
6166 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6167 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6168 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6170 // Vector-related lowering.
6171 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6172 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6173 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6174 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6175 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6176 case ISD::MUL: return LowerMUL(Op, DAG);
6178 // For counter-based loop handling.
6179 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6181 // Frame & Return address.
6182 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6183 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6187 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6188 SmallVectorImpl<SDValue>&Results,
6189 SelectionDAG &DAG) const {
6190 const TargetMachine &TM = getTargetMachine();
6192 switch (N->getOpcode()) {
6194 llvm_unreachable("Do not know how to custom type legalize this operation!");
6195 case ISD::INTRINSIC_W_CHAIN: {
6196 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6197 Intrinsic::ppc_is_decremented_ctr_nonzero)
6200 assert(N->getValueType(0) == MVT::i1 &&
6201 "Unexpected result type for CTR decrement intrinsic");
6202 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6203 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6204 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6207 Results.push_back(NewInt);
6208 Results.push_back(NewInt.getValue(1));
6212 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6213 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6216 EVT VT = N->getValueType(0);
6218 if (VT == MVT::i64) {
6219 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6221 Results.push_back(NewNode);
6222 Results.push_back(NewNode.getValue(1));
6226 case ISD::FP_ROUND_INREG: {
6227 assert(N->getValueType(0) == MVT::ppcf128);
6228 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6229 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6230 MVT::f64, N->getOperand(0),
6231 DAG.getIntPtrConstant(0));
6232 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6233 MVT::f64, N->getOperand(0),
6234 DAG.getIntPtrConstant(1));
6236 // Add the two halves of the long double in round-to-zero mode.
6237 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6239 // We know the low half is about to be thrown away, so just use something
6241 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6245 case ISD::FP_TO_SINT:
6246 // LowerFP_TO_INT() can only handle f32 and f64.
6247 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6249 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6255 //===----------------------------------------------------------------------===//
6256 // Other Lowering Code
6257 //===----------------------------------------------------------------------===//
6260 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6261 bool is64bit, unsigned BinOpcode) const {
6262 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6263 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6265 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6266 MachineFunction *F = BB->getParent();
6267 MachineFunction::iterator It = BB;
6270 unsigned dest = MI->getOperand(0).getReg();
6271 unsigned ptrA = MI->getOperand(1).getReg();
6272 unsigned ptrB = MI->getOperand(2).getReg();
6273 unsigned incr = MI->getOperand(3).getReg();
6274 DebugLoc dl = MI->getDebugLoc();
6276 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6277 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6278 F->insert(It, loopMBB);
6279 F->insert(It, exitMBB);
6280 exitMBB->splice(exitMBB->begin(), BB,
6281 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6282 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6284 MachineRegisterInfo &RegInfo = F->getRegInfo();
6285 unsigned TmpReg = (!BinOpcode) ? incr :
6286 RegInfo.createVirtualRegister(
6287 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6288 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6292 // fallthrough --> loopMBB
6293 BB->addSuccessor(loopMBB);
6296 // l[wd]arx dest, ptr
6297 // add r0, dest, incr
6298 // st[wd]cx. r0, ptr
6300 // fallthrough --> exitMBB
6302 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6303 .addReg(ptrA).addReg(ptrB);
6305 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6306 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6307 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6308 BuildMI(BB, dl, TII->get(PPC::BCC))
6309 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6310 BB->addSuccessor(loopMBB);
6311 BB->addSuccessor(exitMBB);
6320 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6321 MachineBasicBlock *BB,
6322 bool is8bit, // operation
6323 unsigned BinOpcode) const {
6324 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6325 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6326 // In 64 bit mode we have to use 64 bits for addresses, even though the
6327 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6328 // registers without caring whether they're 32 or 64, but here we're
6329 // doing actual arithmetic on the addresses.
6330 bool is64bit = Subtarget.isPPC64();
6331 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6333 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6334 MachineFunction *F = BB->getParent();
6335 MachineFunction::iterator It = BB;
6338 unsigned dest = MI->getOperand(0).getReg();
6339 unsigned ptrA = MI->getOperand(1).getReg();
6340 unsigned ptrB = MI->getOperand(2).getReg();
6341 unsigned incr = MI->getOperand(3).getReg();
6342 DebugLoc dl = MI->getDebugLoc();
6344 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6345 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6346 F->insert(It, loopMBB);
6347 F->insert(It, exitMBB);
6348 exitMBB->splice(exitMBB->begin(), BB,
6349 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6350 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6352 MachineRegisterInfo &RegInfo = F->getRegInfo();
6353 const TargetRegisterClass *RC =
6354 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6355 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6356 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6357 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6358 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6359 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6360 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6361 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6362 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6363 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6364 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6365 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6366 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6368 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6372 // fallthrough --> loopMBB
6373 BB->addSuccessor(loopMBB);
6375 // The 4-byte load must be aligned, while a char or short may be
6376 // anywhere in the word. Hence all this nasty bookkeeping code.
6377 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6378 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6379 // xori shift, shift1, 24 [16]
6380 // rlwinm ptr, ptr1, 0, 0, 29
6381 // slw incr2, incr, shift
6382 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6383 // slw mask, mask2, shift
6385 // lwarx tmpDest, ptr
6386 // add tmp, tmpDest, incr2
6387 // andc tmp2, tmpDest, mask
6388 // and tmp3, tmp, mask
6389 // or tmp4, tmp3, tmp2
6392 // fallthrough --> exitMBB
6393 // srw dest, tmpDest, shift
6394 if (ptrA != ZeroReg) {
6395 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6396 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6397 .addReg(ptrA).addReg(ptrB);
6401 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6402 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6403 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6404 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6406 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6407 .addReg(Ptr1Reg).addImm(0).addImm(61);
6409 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6410 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6411 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6412 .addReg(incr).addReg(ShiftReg);
6414 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6416 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6417 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6419 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6420 .addReg(Mask2Reg).addReg(ShiftReg);
6423 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6424 .addReg(ZeroReg).addReg(PtrReg);
6426 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6427 .addReg(Incr2Reg).addReg(TmpDestReg);
6428 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6429 .addReg(TmpDestReg).addReg(MaskReg);
6430 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6431 .addReg(TmpReg).addReg(MaskReg);
6432 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6433 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6434 BuildMI(BB, dl, TII->get(PPC::STWCX))
6435 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6436 BuildMI(BB, dl, TII->get(PPC::BCC))
6437 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6438 BB->addSuccessor(loopMBB);
6439 BB->addSuccessor(exitMBB);
6444 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6449 llvm::MachineBasicBlock*
6450 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6451 MachineBasicBlock *MBB) const {
6452 DebugLoc DL = MI->getDebugLoc();
6453 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6455 MachineFunction *MF = MBB->getParent();
6456 MachineRegisterInfo &MRI = MF->getRegInfo();
6458 const BasicBlock *BB = MBB->getBasicBlock();
6459 MachineFunction::iterator I = MBB;
6463 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6464 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6466 unsigned DstReg = MI->getOperand(0).getReg();
6467 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6468 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6469 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6470 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6472 MVT PVT = getPointerTy();
6473 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6474 "Invalid Pointer Size!");
6475 // For v = setjmp(buf), we generate
6478 // SjLjSetup mainMBB
6484 // buf[LabelOffset] = LR
6488 // v = phi(main, restore)
6491 MachineBasicBlock *thisMBB = MBB;
6492 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6493 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6494 MF->insert(I, mainMBB);
6495 MF->insert(I, sinkMBB);
6497 MachineInstrBuilder MIB;
6499 // Transfer the remainder of BB and its successor edges to sinkMBB.
6500 sinkMBB->splice(sinkMBB->begin(), MBB,
6501 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6502 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6504 // Note that the structure of the jmp_buf used here is not compatible
6505 // with that used by libc, and is not designed to be. Specifically, it
6506 // stores only those 'reserved' registers that LLVM does not otherwise
6507 // understand how to spill. Also, by convention, by the time this
6508 // intrinsic is called, Clang has already stored the frame address in the
6509 // first slot of the buffer and stack address in the third. Following the
6510 // X86 target code, we'll store the jump address in the second slot. We also
6511 // need to save the TOC pointer (R2) to handle jumps between shared
6512 // libraries, and that will be stored in the fourth slot. The thread
6513 // identifier (R13) is not affected.
6516 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6517 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6518 const int64_t BPOffset = 4 * PVT.getStoreSize();
6520 // Prepare IP either in reg.
6521 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6522 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6523 unsigned BufReg = MI->getOperand(1).getReg();
6525 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6526 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6530 MIB.setMemRefs(MMOBegin, MMOEnd);
6533 // Naked functions never have a base pointer, and so we use r1. For all
6534 // other functions, this decision must be delayed until during PEI.
6536 if (MF->getFunction()->getAttributes().hasAttribute(
6537 AttributeSet::FunctionIndex, Attribute::Naked))
6538 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6540 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6542 MIB = BuildMI(*thisMBB, MI, DL,
6543 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6547 MIB.setMemRefs(MMOBegin, MMOEnd);
6550 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6551 const PPCRegisterInfo *TRI =
6552 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6553 MIB.addRegMask(TRI->getNoPreservedMask());
6555 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6557 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6559 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6561 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6562 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6566 MIB = BuildMI(mainMBB, DL,
6567 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6570 if (Subtarget.isPPC64()) {
6571 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6573 .addImm(LabelOffset)
6576 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6578 .addImm(LabelOffset)
6582 MIB.setMemRefs(MMOBegin, MMOEnd);
6584 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6585 mainMBB->addSuccessor(sinkMBB);
6588 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6589 TII->get(PPC::PHI), DstReg)
6590 .addReg(mainDstReg).addMBB(mainMBB)
6591 .addReg(restoreDstReg).addMBB(thisMBB);
6593 MI->eraseFromParent();
6598 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6599 MachineBasicBlock *MBB) const {
6600 DebugLoc DL = MI->getDebugLoc();
6601 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6603 MachineFunction *MF = MBB->getParent();
6604 MachineRegisterInfo &MRI = MF->getRegInfo();
6607 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6608 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6610 MVT PVT = getPointerTy();
6611 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6612 "Invalid Pointer Size!");
6614 const TargetRegisterClass *RC =
6615 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6616 unsigned Tmp = MRI.createVirtualRegister(RC);
6617 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6618 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6619 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6620 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6622 MachineInstrBuilder MIB;
6624 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6625 const int64_t SPOffset = 2 * PVT.getStoreSize();
6626 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6627 const int64_t BPOffset = 4 * PVT.getStoreSize();
6629 unsigned BufReg = MI->getOperand(0).getReg();
6631 // Reload FP (the jumped-to function may not have had a
6632 // frame pointer, and if so, then its r31 will be restored
6634 if (PVT == MVT::i64) {
6635 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6639 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6643 MIB.setMemRefs(MMOBegin, MMOEnd);
6646 if (PVT == MVT::i64) {
6647 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6648 .addImm(LabelOffset)
6651 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6652 .addImm(LabelOffset)
6655 MIB.setMemRefs(MMOBegin, MMOEnd);
6658 if (PVT == MVT::i64) {
6659 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6663 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6667 MIB.setMemRefs(MMOBegin, MMOEnd);
6670 if (PVT == MVT::i64) {
6671 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6675 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6679 MIB.setMemRefs(MMOBegin, MMOEnd);
6682 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6683 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6687 MIB.setMemRefs(MMOBegin, MMOEnd);
6691 BuildMI(*MBB, MI, DL,
6692 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6693 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6695 MI->eraseFromParent();
6700 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6701 MachineBasicBlock *BB) const {
6702 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6703 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6704 return emitEHSjLjSetJmp(MI, BB);
6705 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6706 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6707 return emitEHSjLjLongJmp(MI, BB);
6710 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6712 // To "insert" these instructions we actually have to insert their
6713 // control-flow patterns.
6714 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6715 MachineFunction::iterator It = BB;
6718 MachineFunction *F = BB->getParent();
6720 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6721 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6722 MI->getOpcode() == PPC::SELECT_I4 ||
6723 MI->getOpcode() == PPC::SELECT_I8)) {
6724 SmallVector<MachineOperand, 2> Cond;
6725 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6726 MI->getOpcode() == PPC::SELECT_CC_I8)
6727 Cond.push_back(MI->getOperand(4));
6729 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6730 Cond.push_back(MI->getOperand(1));
6732 DebugLoc dl = MI->getDebugLoc();
6733 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6734 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6735 Cond, MI->getOperand(2).getReg(),
6736 MI->getOperand(3).getReg());
6737 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6738 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6739 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6740 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6741 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6742 MI->getOpcode() == PPC::SELECT_I4 ||
6743 MI->getOpcode() == PPC::SELECT_I8 ||
6744 MI->getOpcode() == PPC::SELECT_F4 ||
6745 MI->getOpcode() == PPC::SELECT_F8 ||
6746 MI->getOpcode() == PPC::SELECT_VRRC) {
6747 // The incoming instruction knows the destination vreg to set, the
6748 // condition code register to branch on, the true/false values to
6749 // select between, and a branch opcode to use.
6754 // cmpTY ccX, r1, r2
6756 // fallthrough --> copy0MBB
6757 MachineBasicBlock *thisMBB = BB;
6758 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6759 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6760 DebugLoc dl = MI->getDebugLoc();
6761 F->insert(It, copy0MBB);
6762 F->insert(It, sinkMBB);
6764 // Transfer the remainder of BB and its successor edges to sinkMBB.
6765 sinkMBB->splice(sinkMBB->begin(), BB,
6766 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6767 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6769 // Next, add the true and fallthrough blocks as its successors.
6770 BB->addSuccessor(copy0MBB);
6771 BB->addSuccessor(sinkMBB);
6773 if (MI->getOpcode() == PPC::SELECT_I4 ||
6774 MI->getOpcode() == PPC::SELECT_I8 ||
6775 MI->getOpcode() == PPC::SELECT_F4 ||
6776 MI->getOpcode() == PPC::SELECT_F8 ||
6777 MI->getOpcode() == PPC::SELECT_VRRC) {
6778 BuildMI(BB, dl, TII->get(PPC::BC))
6779 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6781 unsigned SelectPred = MI->getOperand(4).getImm();
6782 BuildMI(BB, dl, TII->get(PPC::BCC))
6783 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6787 // %FalseValue = ...
6788 // # fallthrough to sinkMBB
6791 // Update machine-CFG edges
6792 BB->addSuccessor(sinkMBB);
6795 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6798 BuildMI(*BB, BB->begin(), dl,
6799 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6800 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6801 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6803 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6804 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6805 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6806 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6807 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6808 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6809 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6810 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6812 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6813 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6814 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6815 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6816 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6817 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6818 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6819 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6821 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6822 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6823 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6824 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6825 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6826 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6827 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6828 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6830 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6831 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6832 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6833 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6834 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6835 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6836 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6837 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6839 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6840 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6841 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6842 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6843 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6844 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6845 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6846 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6848 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6849 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6850 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6851 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6852 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6853 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6854 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6855 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6857 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6858 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6859 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6860 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6861 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6862 BB = EmitAtomicBinary(MI, BB, false, 0);
6863 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6864 BB = EmitAtomicBinary(MI, BB, true, 0);
6866 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6867 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6868 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6870 unsigned dest = MI->getOperand(0).getReg();
6871 unsigned ptrA = MI->getOperand(1).getReg();
6872 unsigned ptrB = MI->getOperand(2).getReg();
6873 unsigned oldval = MI->getOperand(3).getReg();
6874 unsigned newval = MI->getOperand(4).getReg();
6875 DebugLoc dl = MI->getDebugLoc();
6877 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6878 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6879 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6880 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6881 F->insert(It, loop1MBB);
6882 F->insert(It, loop2MBB);
6883 F->insert(It, midMBB);
6884 F->insert(It, exitMBB);
6885 exitMBB->splice(exitMBB->begin(), BB,
6886 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6887 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6891 // fallthrough --> loopMBB
6892 BB->addSuccessor(loop1MBB);
6895 // l[wd]arx dest, ptr
6896 // cmp[wd] dest, oldval
6899 // st[wd]cx. newval, ptr
6903 // st[wd]cx. dest, ptr
6906 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6907 .addReg(ptrA).addReg(ptrB);
6908 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6909 .addReg(oldval).addReg(dest);
6910 BuildMI(BB, dl, TII->get(PPC::BCC))
6911 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6912 BB->addSuccessor(loop2MBB);
6913 BB->addSuccessor(midMBB);
6916 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6917 .addReg(newval).addReg(ptrA).addReg(ptrB);
6918 BuildMI(BB, dl, TII->get(PPC::BCC))
6919 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6920 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6921 BB->addSuccessor(loop1MBB);
6922 BB->addSuccessor(exitMBB);
6925 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6926 .addReg(dest).addReg(ptrA).addReg(ptrB);
6927 BB->addSuccessor(exitMBB);
6932 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6933 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6934 // We must use 64-bit registers for addresses when targeting 64-bit,
6935 // since we're actually doing arithmetic on them. Other registers
6937 bool is64bit = Subtarget.isPPC64();
6938 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6940 unsigned dest = MI->getOperand(0).getReg();
6941 unsigned ptrA = MI->getOperand(1).getReg();
6942 unsigned ptrB = MI->getOperand(2).getReg();
6943 unsigned oldval = MI->getOperand(3).getReg();
6944 unsigned newval = MI->getOperand(4).getReg();
6945 DebugLoc dl = MI->getDebugLoc();
6947 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6948 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6949 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6950 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6951 F->insert(It, loop1MBB);
6952 F->insert(It, loop2MBB);
6953 F->insert(It, midMBB);
6954 F->insert(It, exitMBB);
6955 exitMBB->splice(exitMBB->begin(), BB,
6956 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6957 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6959 MachineRegisterInfo &RegInfo = F->getRegInfo();
6960 const TargetRegisterClass *RC =
6961 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6962 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6963 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6964 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6965 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6966 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6967 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6968 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6969 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6970 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6971 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6972 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6973 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6974 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6975 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6977 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6978 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6981 // fallthrough --> loopMBB
6982 BB->addSuccessor(loop1MBB);
6984 // The 4-byte load must be aligned, while a char or short may be
6985 // anywhere in the word. Hence all this nasty bookkeeping code.
6986 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6987 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6988 // xori shift, shift1, 24 [16]
6989 // rlwinm ptr, ptr1, 0, 0, 29
6990 // slw newval2, newval, shift
6991 // slw oldval2, oldval,shift
6992 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6993 // slw mask, mask2, shift
6994 // and newval3, newval2, mask
6995 // and oldval3, oldval2, mask
6997 // lwarx tmpDest, ptr
6998 // and tmp, tmpDest, mask
6999 // cmpw tmp, oldval3
7002 // andc tmp2, tmpDest, mask
7003 // or tmp4, tmp2, newval3
7008 // stwcx. tmpDest, ptr
7010 // srw dest, tmpDest, shift
7011 if (ptrA != ZeroReg) {
7012 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7013 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7014 .addReg(ptrA).addReg(ptrB);
7018 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7019 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7020 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7021 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7023 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7024 .addReg(Ptr1Reg).addImm(0).addImm(61);
7026 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7027 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7028 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7029 .addReg(newval).addReg(ShiftReg);
7030 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7031 .addReg(oldval).addReg(ShiftReg);
7033 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7035 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7036 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7037 .addReg(Mask3Reg).addImm(65535);
7039 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7040 .addReg(Mask2Reg).addReg(ShiftReg);
7041 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7042 .addReg(NewVal2Reg).addReg(MaskReg);
7043 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7044 .addReg(OldVal2Reg).addReg(MaskReg);
7047 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7048 .addReg(ZeroReg).addReg(PtrReg);
7049 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7050 .addReg(TmpDestReg).addReg(MaskReg);
7051 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7052 .addReg(TmpReg).addReg(OldVal3Reg);
7053 BuildMI(BB, dl, TII->get(PPC::BCC))
7054 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7055 BB->addSuccessor(loop2MBB);
7056 BB->addSuccessor(midMBB);
7059 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7060 .addReg(TmpDestReg).addReg(MaskReg);
7061 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7062 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7063 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7064 .addReg(ZeroReg).addReg(PtrReg);
7065 BuildMI(BB, dl, TII->get(PPC::BCC))
7066 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7067 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7068 BB->addSuccessor(loop1MBB);
7069 BB->addSuccessor(exitMBB);
7072 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7073 .addReg(ZeroReg).addReg(PtrReg);
7074 BB->addSuccessor(exitMBB);
7079 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7081 } else if (MI->getOpcode() == PPC::FADDrtz) {
7082 // This pseudo performs an FADD with rounding mode temporarily forced
7083 // to round-to-zero. We emit this via custom inserter since the FPSCR
7084 // is not modeled at the SelectionDAG level.
7085 unsigned Dest = MI->getOperand(0).getReg();
7086 unsigned Src1 = MI->getOperand(1).getReg();
7087 unsigned Src2 = MI->getOperand(2).getReg();
7088 DebugLoc dl = MI->getDebugLoc();
7090 MachineRegisterInfo &RegInfo = F->getRegInfo();
7091 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7093 // Save FPSCR value.
7094 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7096 // Set rounding mode to round-to-zero.
7097 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7098 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7100 // Perform addition.
7101 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7103 // Restore FPSCR value.
7104 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7105 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7106 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7107 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7108 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7109 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7110 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7111 PPC::ANDIo8 : PPC::ANDIo;
7112 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7113 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7115 MachineRegisterInfo &RegInfo = F->getRegInfo();
7116 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7117 &PPC::GPRCRegClass :
7118 &PPC::G8RCRegClass);
7120 DebugLoc dl = MI->getDebugLoc();
7121 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7122 .addReg(MI->getOperand(1).getReg()).addImm(1);
7123 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7124 MI->getOperand(0).getReg())
7125 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7127 llvm_unreachable("Unexpected instr type to insert");
7130 MI->eraseFromParent(); // The pseudo instruction is gone now.
7134 //===----------------------------------------------------------------------===//
7135 // Target Optimization Hooks
7136 //===----------------------------------------------------------------------===//
7138 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7139 DAGCombinerInfo &DCI) const {
7140 if (DCI.isAfterLegalizeVectorOps())
7143 EVT VT = Op.getValueType();
7145 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7146 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7147 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7148 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7150 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7151 // For the reciprocal, we need to find the zero of the function:
7152 // F(X) = A X - 1 [which has a zero at X = 1/A]
7154 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7155 // does not require additional intermediate precision]
7157 // Convergence is quadratic, so we essentially double the number of digits
7158 // correct after every iteration. The minimum architected relative
7159 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7160 // 23 digits and double has 52 digits.
7161 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7162 if (VT.getScalarType() == MVT::f64)
7165 SelectionDAG &DAG = DCI.DAG;
7169 DAG.getConstantFP(1.0, VT.getScalarType());
7170 if (VT.isVector()) {
7171 assert(VT.getVectorNumElements() == 4 &&
7172 "Unknown vector type");
7173 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7174 FPOne, FPOne, FPOne, FPOne);
7177 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7178 DCI.AddToWorklist(Est.getNode());
7180 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7181 for (int i = 0; i < Iterations; ++i) {
7182 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7183 DCI.AddToWorklist(NewEst.getNode());
7185 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7186 DCI.AddToWorklist(NewEst.getNode());
7188 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7189 DCI.AddToWorklist(NewEst.getNode());
7191 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7192 DCI.AddToWorklist(Est.getNode());
7201 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7202 DAGCombinerInfo &DCI) const {
7203 if (DCI.isAfterLegalizeVectorOps())
7206 EVT VT = Op.getValueType();
7208 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7209 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7210 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7211 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7213 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7214 // For the reciprocal sqrt, we need to find the zero of the function:
7215 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7217 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7218 // As a result, we precompute A/2 prior to the iteration loop.
7220 // Convergence is quadratic, so we essentially double the number of digits
7221 // correct after every iteration. The minimum architected relative
7222 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7223 // 23 digits and double has 52 digits.
7224 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7225 if (VT.getScalarType() == MVT::f64)
7228 SelectionDAG &DAG = DCI.DAG;
7231 SDValue FPThreeHalves =
7232 DAG.getConstantFP(1.5, VT.getScalarType());
7233 if (VT.isVector()) {
7234 assert(VT.getVectorNumElements() == 4 &&
7235 "Unknown vector type");
7236 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7237 FPThreeHalves, FPThreeHalves,
7238 FPThreeHalves, FPThreeHalves);
7241 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7242 DCI.AddToWorklist(Est.getNode());
7244 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7245 // this entire sequence requires only one FP constant.
7246 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7247 DCI.AddToWorklist(HalfArg.getNode());
7249 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7250 DCI.AddToWorklist(HalfArg.getNode());
7252 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7253 for (int i = 0; i < Iterations; ++i) {
7254 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7255 DCI.AddToWorklist(NewEst.getNode());
7257 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7258 DCI.AddToWorklist(NewEst.getNode());
7260 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7261 DCI.AddToWorklist(NewEst.getNode());
7263 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7264 DCI.AddToWorklist(Est.getNode());
7273 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7274 // not enforce equality of the chain operands.
7275 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7276 unsigned Bytes, int Dist,
7277 SelectionDAG &DAG) {
7278 EVT VT = LS->getMemoryVT();
7279 if (VT.getSizeInBits() / 8 != Bytes)
7282 SDValue Loc = LS->getBasePtr();
7283 SDValue BaseLoc = Base->getBasePtr();
7284 if (Loc.getOpcode() == ISD::FrameIndex) {
7285 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7287 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7288 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7289 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7290 int FS = MFI->getObjectSize(FI);
7291 int BFS = MFI->getObjectSize(BFI);
7292 if (FS != BFS || FS != (int)Bytes) return false;
7293 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7297 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7298 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7301 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7302 const GlobalValue *GV1 = nullptr;
7303 const GlobalValue *GV2 = nullptr;
7304 int64_t Offset1 = 0;
7305 int64_t Offset2 = 0;
7306 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7307 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7308 if (isGA1 && isGA2 && GV1 == GV2)
7309 return Offset1 == (Offset2 + Dist*Bytes);
7313 // Return true is there is a nearyby consecutive load to the one provided
7314 // (regardless of alignment). We search up and down the chain, looking though
7315 // token factors and other loads (but nothing else). As a result, a true
7316 // results indicates that it is safe to create a new consecutive load adjacent
7317 // to the load provided.
7318 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7319 SDValue Chain = LD->getChain();
7320 EVT VT = LD->getMemoryVT();
7322 SmallSet<SDNode *, 16> LoadRoots;
7323 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7324 SmallSet<SDNode *, 16> Visited;
7326 // First, search up the chain, branching to follow all token-factor operands.
7327 // If we find a consecutive load, then we're done, otherwise, record all
7328 // nodes just above the top-level loads and token factors.
7329 while (!Queue.empty()) {
7330 SDNode *ChainNext = Queue.pop_back_val();
7331 if (!Visited.insert(ChainNext))
7334 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7335 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7338 if (!Visited.count(ChainLD->getChain().getNode()))
7339 Queue.push_back(ChainLD->getChain().getNode());
7340 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7341 for (const SDUse &O : ChainNext->ops())
7342 if (!Visited.count(O.getNode()))
7343 Queue.push_back(O.getNode());
7345 LoadRoots.insert(ChainNext);
7348 // Second, search down the chain, starting from the top-level nodes recorded
7349 // in the first phase. These top-level nodes are the nodes just above all
7350 // loads and token factors. Starting with their uses, recursively look though
7351 // all loads (just the chain uses) and token factors to find a consecutive
7356 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7357 IE = LoadRoots.end(); I != IE; ++I) {
7358 Queue.push_back(*I);
7360 while (!Queue.empty()) {
7361 SDNode *LoadRoot = Queue.pop_back_val();
7362 if (!Visited.insert(LoadRoot))
7365 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7366 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7369 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7370 UE = LoadRoot->use_end(); UI != UE; ++UI)
7371 if (((isa<LoadSDNode>(*UI) &&
7372 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7373 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7374 Queue.push_back(*UI);
7381 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7382 DAGCombinerInfo &DCI) const {
7383 SelectionDAG &DAG = DCI.DAG;
7386 assert(Subtarget.useCRBits() &&
7387 "Expecting to be tracking CR bits");
7388 // If we're tracking CR bits, we need to be careful that we don't have:
7389 // trunc(binary-ops(zext(x), zext(y)))
7391 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7392 // such that we're unnecessarily moving things into GPRs when it would be
7393 // better to keep them in CR bits.
7395 // Note that trunc here can be an actual i1 trunc, or can be the effective
7396 // truncation that comes from a setcc or select_cc.
7397 if (N->getOpcode() == ISD::TRUNCATE &&
7398 N->getValueType(0) != MVT::i1)
7401 if (N->getOperand(0).getValueType() != MVT::i32 &&
7402 N->getOperand(0).getValueType() != MVT::i64)
7405 if (N->getOpcode() == ISD::SETCC ||
7406 N->getOpcode() == ISD::SELECT_CC) {
7407 // If we're looking at a comparison, then we need to make sure that the
7408 // high bits (all except for the first) don't matter the result.
7410 cast<CondCodeSDNode>(N->getOperand(
7411 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7412 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7414 if (ISD::isSignedIntSetCC(CC)) {
7415 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7416 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7418 } else if (ISD::isUnsignedIntSetCC(CC)) {
7419 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7420 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7421 !DAG.MaskedValueIsZero(N->getOperand(1),
7422 APInt::getHighBitsSet(OpBits, OpBits-1)))
7425 // This is neither a signed nor an unsigned comparison, just make sure
7426 // that the high bits are equal.
7427 APInt Op1Zero, Op1One;
7428 APInt Op2Zero, Op2One;
7429 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7430 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7432 // We don't really care about what is known about the first bit (if
7433 // anything), so clear it in all masks prior to comparing them.
7434 Op1Zero.clearBit(0); Op1One.clearBit(0);
7435 Op2Zero.clearBit(0); Op2One.clearBit(0);
7437 if (Op1Zero != Op2Zero || Op1One != Op2One)
7442 // We now know that the higher-order bits are irrelevant, we just need to
7443 // make sure that all of the intermediate operations are bit operations, and
7444 // all inputs are extensions.
7445 if (N->getOperand(0).getOpcode() != ISD::AND &&
7446 N->getOperand(0).getOpcode() != ISD::OR &&
7447 N->getOperand(0).getOpcode() != ISD::XOR &&
7448 N->getOperand(0).getOpcode() != ISD::SELECT &&
7449 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7450 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7451 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7452 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7453 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7456 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7457 N->getOperand(1).getOpcode() != ISD::AND &&
7458 N->getOperand(1).getOpcode() != ISD::OR &&
7459 N->getOperand(1).getOpcode() != ISD::XOR &&
7460 N->getOperand(1).getOpcode() != ISD::SELECT &&
7461 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7462 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7463 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7464 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7465 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7468 SmallVector<SDValue, 4> Inputs;
7469 SmallVector<SDValue, 8> BinOps, PromOps;
7470 SmallPtrSet<SDNode *, 16> Visited;
7472 for (unsigned i = 0; i < 2; ++i) {
7473 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7474 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7475 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7476 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7477 isa<ConstantSDNode>(N->getOperand(i)))
7478 Inputs.push_back(N->getOperand(i));
7480 BinOps.push_back(N->getOperand(i));
7482 if (N->getOpcode() == ISD::TRUNCATE)
7486 // Visit all inputs, collect all binary operations (and, or, xor and
7487 // select) that are all fed by extensions.
7488 while (!BinOps.empty()) {
7489 SDValue BinOp = BinOps.back();
7492 if (!Visited.insert(BinOp.getNode()))
7495 PromOps.push_back(BinOp);
7497 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7498 // The condition of the select is not promoted.
7499 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7501 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7504 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7505 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7506 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7507 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7508 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7509 Inputs.push_back(BinOp.getOperand(i));
7510 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7511 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7512 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7513 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7514 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7515 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7516 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7517 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7518 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7519 BinOps.push_back(BinOp.getOperand(i));
7521 // We have an input that is not an extension or another binary
7522 // operation; we'll abort this transformation.
7528 // Make sure that this is a self-contained cluster of operations (which
7529 // is not quite the same thing as saying that everything has only one
7531 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7532 if (isa<ConstantSDNode>(Inputs[i]))
7535 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7536 UE = Inputs[i].getNode()->use_end();
7539 if (User != N && !Visited.count(User))
7542 // Make sure that we're not going to promote the non-output-value
7543 // operand(s) or SELECT or SELECT_CC.
7544 // FIXME: Although we could sometimes handle this, and it does occur in
7545 // practice that one of the condition inputs to the select is also one of
7546 // the outputs, we currently can't deal with this.
7547 if (User->getOpcode() == ISD::SELECT) {
7548 if (User->getOperand(0) == Inputs[i])
7550 } else if (User->getOpcode() == ISD::SELECT_CC) {
7551 if (User->getOperand(0) == Inputs[i] ||
7552 User->getOperand(1) == Inputs[i])
7558 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7559 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7560 UE = PromOps[i].getNode()->use_end();
7563 if (User != N && !Visited.count(User))
7566 // Make sure that we're not going to promote the non-output-value
7567 // operand(s) or SELECT or SELECT_CC.
7568 // FIXME: Although we could sometimes handle this, and it does occur in
7569 // practice that one of the condition inputs to the select is also one of
7570 // the outputs, we currently can't deal with this.
7571 if (User->getOpcode() == ISD::SELECT) {
7572 if (User->getOperand(0) == PromOps[i])
7574 } else if (User->getOpcode() == ISD::SELECT_CC) {
7575 if (User->getOperand(0) == PromOps[i] ||
7576 User->getOperand(1) == PromOps[i])
7582 // Replace all inputs with the extension operand.
7583 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7584 // Constants may have users outside the cluster of to-be-promoted nodes,
7585 // and so we need to replace those as we do the promotions.
7586 if (isa<ConstantSDNode>(Inputs[i]))
7589 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7592 // Replace all operations (these are all the same, but have a different
7593 // (i1) return type). DAG.getNode will validate that the types of
7594 // a binary operator match, so go through the list in reverse so that
7595 // we've likely promoted both operands first. Any intermediate truncations or
7596 // extensions disappear.
7597 while (!PromOps.empty()) {
7598 SDValue PromOp = PromOps.back();
7601 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7602 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7603 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7604 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7605 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7606 PromOp.getOperand(0).getValueType() != MVT::i1) {
7607 // The operand is not yet ready (see comment below).
7608 PromOps.insert(PromOps.begin(), PromOp);
7612 SDValue RepValue = PromOp.getOperand(0);
7613 if (isa<ConstantSDNode>(RepValue))
7614 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7616 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7621 switch (PromOp.getOpcode()) {
7622 default: C = 0; break;
7623 case ISD::SELECT: C = 1; break;
7624 case ISD::SELECT_CC: C = 2; break;
7627 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7628 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7629 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7630 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7631 // The to-be-promoted operands of this node have not yet been
7632 // promoted (this should be rare because we're going through the
7633 // list backward, but if one of the operands has several users in
7634 // this cluster of to-be-promoted nodes, it is possible).
7635 PromOps.insert(PromOps.begin(), PromOp);
7639 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7640 PromOp.getNode()->op_end());
7642 // If there are any constant inputs, make sure they're replaced now.
7643 for (unsigned i = 0; i < 2; ++i)
7644 if (isa<ConstantSDNode>(Ops[C+i]))
7645 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7647 DAG.ReplaceAllUsesOfValueWith(PromOp,
7648 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7651 // Now we're left with the initial truncation itself.
7652 if (N->getOpcode() == ISD::TRUNCATE)
7653 return N->getOperand(0);
7655 // Otherwise, this is a comparison. The operands to be compared have just
7656 // changed type (to i1), but everything else is the same.
7657 return SDValue(N, 0);
7660 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7661 DAGCombinerInfo &DCI) const {
7662 SelectionDAG &DAG = DCI.DAG;
7665 // If we're tracking CR bits, we need to be careful that we don't have:
7666 // zext(binary-ops(trunc(x), trunc(y)))
7668 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7669 // such that we're unnecessarily moving things into CR bits that can more
7670 // efficiently stay in GPRs. Note that if we're not certain that the high
7671 // bits are set as required by the final extension, we still may need to do
7672 // some masking to get the proper behavior.
7674 // This same functionality is important on PPC64 when dealing with
7675 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7676 // the return values of functions. Because it is so similar, it is handled
7679 if (N->getValueType(0) != MVT::i32 &&
7680 N->getValueType(0) != MVT::i64)
7683 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7684 Subtarget.useCRBits()) ||
7685 (N->getOperand(0).getValueType() == MVT::i32 &&
7686 Subtarget.isPPC64())))
7689 if (N->getOperand(0).getOpcode() != ISD::AND &&
7690 N->getOperand(0).getOpcode() != ISD::OR &&
7691 N->getOperand(0).getOpcode() != ISD::XOR &&
7692 N->getOperand(0).getOpcode() != ISD::SELECT &&
7693 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7696 SmallVector<SDValue, 4> Inputs;
7697 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7698 SmallPtrSet<SDNode *, 16> Visited;
7700 // Visit all inputs, collect all binary operations (and, or, xor and
7701 // select) that are all fed by truncations.
7702 while (!BinOps.empty()) {
7703 SDValue BinOp = BinOps.back();
7706 if (!Visited.insert(BinOp.getNode()))
7709 PromOps.push_back(BinOp);
7711 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7712 // The condition of the select is not promoted.
7713 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7715 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7718 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7719 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7720 Inputs.push_back(BinOp.getOperand(i));
7721 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7722 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7723 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7724 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7725 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7726 BinOps.push_back(BinOp.getOperand(i));
7728 // We have an input that is not a truncation or another binary
7729 // operation; we'll abort this transformation.
7735 // Make sure that this is a self-contained cluster of operations (which
7736 // is not quite the same thing as saying that everything has only one
7738 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7739 if (isa<ConstantSDNode>(Inputs[i]))
7742 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7743 UE = Inputs[i].getNode()->use_end();
7746 if (User != N && !Visited.count(User))
7749 // Make sure that we're not going to promote the non-output-value
7750 // operand(s) or SELECT or SELECT_CC.
7751 // FIXME: Although we could sometimes handle this, and it does occur in
7752 // practice that one of the condition inputs to the select is also one of
7753 // the outputs, we currently can't deal with this.
7754 if (User->getOpcode() == ISD::SELECT) {
7755 if (User->getOperand(0) == Inputs[i])
7757 } else if (User->getOpcode() == ISD::SELECT_CC) {
7758 if (User->getOperand(0) == Inputs[i] ||
7759 User->getOperand(1) == Inputs[i])
7765 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7766 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7767 UE = PromOps[i].getNode()->use_end();
7770 if (User != N && !Visited.count(User))
7773 // Make sure that we're not going to promote the non-output-value
7774 // operand(s) or SELECT or SELECT_CC.
7775 // FIXME: Although we could sometimes handle this, and it does occur in
7776 // practice that one of the condition inputs to the select is also one of
7777 // the outputs, we currently can't deal with this.
7778 if (User->getOpcode() == ISD::SELECT) {
7779 if (User->getOperand(0) == PromOps[i])
7781 } else if (User->getOpcode() == ISD::SELECT_CC) {
7782 if (User->getOperand(0) == PromOps[i] ||
7783 User->getOperand(1) == PromOps[i])
7789 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7790 bool ReallyNeedsExt = false;
7791 if (N->getOpcode() != ISD::ANY_EXTEND) {
7792 // If all of the inputs are not already sign/zero extended, then
7793 // we'll still need to do that at the end.
7794 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7795 if (isa<ConstantSDNode>(Inputs[i]))
7799 Inputs[i].getOperand(0).getValueSizeInBits();
7800 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7802 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7803 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7804 APInt::getHighBitsSet(OpBits,
7805 OpBits-PromBits))) ||
7806 (N->getOpcode() == ISD::SIGN_EXTEND &&
7807 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7808 (OpBits-(PromBits-1)))) {
7809 ReallyNeedsExt = true;
7815 // Replace all inputs, either with the truncation operand, or a
7816 // truncation or extension to the final output type.
7817 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7818 // Constant inputs need to be replaced with the to-be-promoted nodes that
7819 // use them because they might have users outside of the cluster of
7821 if (isa<ConstantSDNode>(Inputs[i]))
7824 SDValue InSrc = Inputs[i].getOperand(0);
7825 if (Inputs[i].getValueType() == N->getValueType(0))
7826 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7827 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7828 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7829 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7830 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7831 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7832 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7834 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7835 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7838 // Replace all operations (these are all the same, but have a different
7839 // (promoted) return type). DAG.getNode will validate that the types of
7840 // a binary operator match, so go through the list in reverse so that
7841 // we've likely promoted both operands first.
7842 while (!PromOps.empty()) {
7843 SDValue PromOp = PromOps.back();
7847 switch (PromOp.getOpcode()) {
7848 default: C = 0; break;
7849 case ISD::SELECT: C = 1; break;
7850 case ISD::SELECT_CC: C = 2; break;
7853 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7854 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7855 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7856 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7857 // The to-be-promoted operands of this node have not yet been
7858 // promoted (this should be rare because we're going through the
7859 // list backward, but if one of the operands has several users in
7860 // this cluster of to-be-promoted nodes, it is possible).
7861 PromOps.insert(PromOps.begin(), PromOp);
7865 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7866 PromOp.getNode()->op_end());
7868 // If this node has constant inputs, then they'll need to be promoted here.
7869 for (unsigned i = 0; i < 2; ++i) {
7870 if (!isa<ConstantSDNode>(Ops[C+i]))
7872 if (Ops[C+i].getValueType() == N->getValueType(0))
7875 if (N->getOpcode() == ISD::SIGN_EXTEND)
7876 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7877 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7878 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7880 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7883 DAG.ReplaceAllUsesOfValueWith(PromOp,
7884 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
7887 // Now we're left with the initial extension itself.
7888 if (!ReallyNeedsExt)
7889 return N->getOperand(0);
7891 // To zero extend, just mask off everything except for the first bit (in the
7893 if (N->getOpcode() == ISD::ZERO_EXTEND)
7894 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7895 DAG.getConstant(APInt::getLowBitsSet(
7896 N->getValueSizeInBits(0), PromBits),
7897 N->getValueType(0)));
7899 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7900 "Invalid extension type");
7901 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7903 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7904 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7905 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7906 N->getOperand(0), ShiftCst), ShiftCst);
7909 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7910 DAGCombinerInfo &DCI) const {
7911 const TargetMachine &TM = getTargetMachine();
7912 SelectionDAG &DAG = DCI.DAG;
7914 switch (N->getOpcode()) {
7917 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7918 if (C->isNullValue()) // 0 << V -> 0.
7919 return N->getOperand(0);
7923 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7924 if (C->isNullValue()) // 0 >>u V -> 0.
7925 return N->getOperand(0);
7929 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7930 if (C->isNullValue() || // 0 >>s V -> 0.
7931 C->isAllOnesValue()) // -1 >>s V -> -1.
7932 return N->getOperand(0);
7935 case ISD::SIGN_EXTEND:
7936 case ISD::ZERO_EXTEND:
7937 case ISD::ANY_EXTEND:
7938 return DAGCombineExtBoolTrunc(N, DCI);
7941 case ISD::SELECT_CC:
7942 return DAGCombineTruncBoolExt(N, DCI);
7944 assert(TM.Options.UnsafeFPMath &&
7945 "Reciprocal estimates require UnsafeFPMath");
7947 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7949 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7951 DCI.AddToWorklist(RV.getNode());
7952 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7953 N->getOperand(0), RV);
7955 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7956 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7958 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7961 DCI.AddToWorklist(RV.getNode());
7962 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7963 N->getValueType(0), RV);
7964 DCI.AddToWorklist(RV.getNode());
7965 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7966 N->getOperand(0), RV);
7968 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7969 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7971 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7974 DCI.AddToWorklist(RV.getNode());
7975 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7976 N->getValueType(0), RV,
7977 N->getOperand(1).getOperand(1));
7978 DCI.AddToWorklist(RV.getNode());
7979 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7980 N->getOperand(0), RV);
7984 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7986 DCI.AddToWorklist(RV.getNode());
7987 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7988 N->getOperand(0), RV);
7994 assert(TM.Options.UnsafeFPMath &&
7995 "Reciprocal estimates require UnsafeFPMath");
7997 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7999 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8001 DCI.AddToWorklist(RV.getNode());
8002 RV = DAGCombineFastRecip(RV, DCI);
8004 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8005 // this case and force the answer to 0.
8007 EVT VT = RV.getValueType();
8009 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8010 if (VT.isVector()) {
8011 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8012 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8016 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8017 N->getOperand(0), Zero, ISD::SETEQ);
8018 DCI.AddToWorklist(ZeroCmp.getNode());
8019 DCI.AddToWorklist(RV.getNode());
8021 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8029 case ISD::SINT_TO_FP:
8030 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8031 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8032 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8033 // We allow the src/dst to be either f32/f64, but the intermediate
8034 // type must be i64.
8035 if (N->getOperand(0).getValueType() == MVT::i64 &&
8036 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8037 SDValue Val = N->getOperand(0).getOperand(0);
8038 if (Val.getValueType() == MVT::f32) {
8039 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8040 DCI.AddToWorklist(Val.getNode());
8043 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8044 DCI.AddToWorklist(Val.getNode());
8045 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8046 DCI.AddToWorklist(Val.getNode());
8047 if (N->getValueType(0) == MVT::f32) {
8048 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8049 DAG.getIntPtrConstant(0));
8050 DCI.AddToWorklist(Val.getNode());
8053 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8054 // If the intermediate type is i32, we can avoid the load/store here
8061 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8062 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8063 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8064 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8065 N->getOperand(1).getValueType() == MVT::i32 &&
8066 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8067 SDValue Val = N->getOperand(1).getOperand(0);
8068 if (Val.getValueType() == MVT::f32) {
8069 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8070 DCI.AddToWorklist(Val.getNode());
8072 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8073 DCI.AddToWorklist(Val.getNode());
8076 N->getOperand(0), Val, N->getOperand(2),
8077 DAG.getValueType(N->getOperand(1).getValueType())
8080 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8081 DAG.getVTList(MVT::Other), Ops,
8082 cast<StoreSDNode>(N)->getMemoryVT(),
8083 cast<StoreSDNode>(N)->getMemOperand());
8084 DCI.AddToWorklist(Val.getNode());
8088 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8089 if (cast<StoreSDNode>(N)->isUnindexed() &&
8090 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8091 N->getOperand(1).getNode()->hasOneUse() &&
8092 (N->getOperand(1).getValueType() == MVT::i32 ||
8093 N->getOperand(1).getValueType() == MVT::i16 ||
8094 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8095 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8096 N->getOperand(1).getValueType() == MVT::i64))) {
8097 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8098 // Do an any-extend to 32-bits if this is a half-word input.
8099 if (BSwapOp.getValueType() == MVT::i16)
8100 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8103 N->getOperand(0), BSwapOp, N->getOperand(2),
8104 DAG.getValueType(N->getOperand(1).getValueType())
8107 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8108 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8109 cast<StoreSDNode>(N)->getMemOperand());
8113 LoadSDNode *LD = cast<LoadSDNode>(N);
8114 EVT VT = LD->getValueType(0);
8115 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8116 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8117 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8118 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8119 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8120 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8121 LD->getAlignment() < ABIAlignment) {
8122 // This is a type-legal unaligned Altivec load.
8123 SDValue Chain = LD->getChain();
8124 SDValue Ptr = LD->getBasePtr();
8125 bool isLittleEndian = Subtarget.isLittleEndian();
8127 // This implements the loading of unaligned vectors as described in
8128 // the venerable Apple Velocity Engine overview. Specifically:
8129 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8130 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8132 // The general idea is to expand a sequence of one or more unaligned
8133 // loads into an alignment-based permutation-control instruction (lvsl
8134 // or lvsr), a series of regular vector loads (which always truncate
8135 // their input address to an aligned address), and a series of
8136 // permutations. The results of these permutations are the requested
8137 // loaded values. The trick is that the last "extra" load is not taken
8138 // from the address you might suspect (sizeof(vector) bytes after the
8139 // last requested load), but rather sizeof(vector) - 1 bytes after the
8140 // last requested vector. The point of this is to avoid a page fault if
8141 // the base address happened to be aligned. This works because if the
8142 // base address is aligned, then adding less than a full vector length
8143 // will cause the last vector in the sequence to be (re)loaded.
8144 // Otherwise, the next vector will be fetched as you might suspect was
8147 // We might be able to reuse the permutation generation from
8148 // a different base address offset from this one by an aligned amount.
8149 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8150 // optimization later.
8151 Intrinsic::ID Intr = (isLittleEndian ?
8152 Intrinsic::ppc_altivec_lvsr :
8153 Intrinsic::ppc_altivec_lvsl);
8154 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8156 // Refine the alignment of the original load (a "new" load created here
8157 // which was identical to the first except for the alignment would be
8158 // merged with the existing node regardless).
8159 MachineFunction &MF = DAG.getMachineFunction();
8160 MachineMemOperand *MMO =
8161 MF.getMachineMemOperand(LD->getPointerInfo(),
8162 LD->getMemOperand()->getFlags(),
8163 LD->getMemoryVT().getStoreSize(),
8165 LD->refineAlignment(MMO);
8166 SDValue BaseLoad = SDValue(LD, 0);
8168 // Note that the value of IncOffset (which is provided to the next
8169 // load's pointer info offset value, and thus used to calculate the
8170 // alignment), and the value of IncValue (which is actually used to
8171 // increment the pointer value) are different! This is because we
8172 // require the next load to appear to be aligned, even though it
8173 // is actually offset from the base pointer by a lesser amount.
8174 int IncOffset = VT.getSizeInBits() / 8;
8175 int IncValue = IncOffset;
8177 // Walk (both up and down) the chain looking for another load at the real
8178 // (aligned) offset (the alignment of the other load does not matter in
8179 // this case). If found, then do not use the offset reduction trick, as
8180 // that will prevent the loads from being later combined (as they would
8181 // otherwise be duplicates).
8182 if (!findConsecutiveLoad(LD, DAG))
8185 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8186 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8189 DAG.getLoad(VT, dl, Chain, Ptr,
8190 LD->getPointerInfo().getWithOffset(IncOffset),
8191 LD->isVolatile(), LD->isNonTemporal(),
8192 LD->isInvariant(), ABIAlignment);
8194 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8195 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8197 if (BaseLoad.getValueType() != MVT::v4i32)
8198 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8200 if (ExtraLoad.getValueType() != MVT::v4i32)
8201 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8203 // Because vperm has a big-endian bias, we must reverse the order
8204 // of the input vectors and complement the permute control vector
8205 // when generating little endian code. We have already handled the
8206 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8207 // and ExtraLoad here.
8210 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8211 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8213 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8214 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8216 if (VT != MVT::v4i32)
8217 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8219 // Now we need to be really careful about how we update the users of the
8220 // original load. We cannot just call DCI.CombineTo (or
8221 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8222 // uses created here (the permutation for example) that need to stay.
8223 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8225 SDUse &Use = UI.getUse();
8227 // Note: BaseLoad is checked here because it might not be N, but a
8229 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8230 User == TF.getNode() || Use.getResNo() > 1) {
8235 SDValue To = Use.getResNo() ? TF : Perm;
8238 SmallVector<SDValue, 8> Ops;
8239 for (const SDUse &O : User->ops()) {
8246 DAG.UpdateNodeOperands(User, Ops);
8249 return SDValue(N, 0);
8253 case ISD::INTRINSIC_WO_CHAIN: {
8254 bool isLittleEndian = Subtarget.isLittleEndian();
8255 Intrinsic::ID Intr = (isLittleEndian ?
8256 Intrinsic::ppc_altivec_lvsr :
8257 Intrinsic::ppc_altivec_lvsl);
8258 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8259 N->getOperand(1)->getOpcode() == ISD::ADD) {
8260 SDValue Add = N->getOperand(1);
8262 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8263 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8264 Add.getValueType().getScalarType().getSizeInBits()))) {
8265 SDNode *BasePtr = Add->getOperand(0).getNode();
8266 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8267 UE = BasePtr->use_end(); UI != UE; ++UI) {
8268 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8269 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8271 // We've found another LVSL/LVSR, and this address is an aligned
8272 // multiple of that one. The results will be the same, so use the
8273 // one we've just found instead.
8275 return SDValue(*UI, 0);
8284 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8285 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8286 N->getOperand(0).hasOneUse() &&
8287 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8288 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8289 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8290 N->getValueType(0) == MVT::i64))) {
8291 SDValue Load = N->getOperand(0);
8292 LoadSDNode *LD = cast<LoadSDNode>(Load);
8293 // Create the byte-swapping load.
8295 LD->getChain(), // Chain
8296 LD->getBasePtr(), // Ptr
8297 DAG.getValueType(N->getValueType(0)) // VT
8300 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8301 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8302 MVT::i64 : MVT::i32, MVT::Other),
8303 Ops, LD->getMemoryVT(), LD->getMemOperand());
8305 // If this is an i16 load, insert the truncate.
8306 SDValue ResVal = BSLoad;
8307 if (N->getValueType(0) == MVT::i16)
8308 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8310 // First, combine the bswap away. This makes the value produced by the
8312 DCI.CombineTo(N, ResVal);
8314 // Next, combine the load away, we give it a bogus result value but a real
8315 // chain result. The result value is dead because the bswap is dead.
8316 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8318 // Return N so it doesn't get rechecked!
8319 return SDValue(N, 0);
8323 case PPCISD::VCMP: {
8324 // If a VCMPo node already exists with exactly the same operands as this
8325 // node, use its result instead of this node (VCMPo computes both a CR6 and
8326 // a normal output).
8328 if (!N->getOperand(0).hasOneUse() &&
8329 !N->getOperand(1).hasOneUse() &&
8330 !N->getOperand(2).hasOneUse()) {
8332 // Scan all of the users of the LHS, looking for VCMPo's that match.
8333 SDNode *VCMPoNode = nullptr;
8335 SDNode *LHSN = N->getOperand(0).getNode();
8336 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8338 if (UI->getOpcode() == PPCISD::VCMPo &&
8339 UI->getOperand(1) == N->getOperand(1) &&
8340 UI->getOperand(2) == N->getOperand(2) &&
8341 UI->getOperand(0) == N->getOperand(0)) {
8346 // If there is no VCMPo node, or if the flag value has a single use, don't
8348 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8351 // Look at the (necessarily single) use of the flag value. If it has a
8352 // chain, this transformation is more complex. Note that multiple things
8353 // could use the value result, which we should ignore.
8354 SDNode *FlagUser = nullptr;
8355 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8356 FlagUser == nullptr; ++UI) {
8357 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8359 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8360 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8367 // If the user is a MFOCRF instruction, we know this is safe.
8368 // Otherwise we give up for right now.
8369 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8370 return SDValue(VCMPoNode, 0);
8375 SDValue Cond = N->getOperand(1);
8376 SDValue Target = N->getOperand(2);
8378 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8379 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8380 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8382 // We now need to make the intrinsic dead (it cannot be instruction
8384 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8385 assert(Cond.getNode()->hasOneUse() &&
8386 "Counter decrement has more than one use");
8388 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8389 N->getOperand(0), Target);
8394 // If this is a branch on an altivec predicate comparison, lower this so
8395 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8396 // lowering is done pre-legalize, because the legalizer lowers the predicate
8397 // compare down to code that is difficult to reassemble.
8398 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8399 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8401 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8402 // value. If so, pass-through the AND to get to the intrinsic.
8403 if (LHS.getOpcode() == ISD::AND &&
8404 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8405 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8406 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8407 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8408 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8410 LHS = LHS.getOperand(0);
8412 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8413 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8414 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8415 isa<ConstantSDNode>(RHS)) {
8416 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8417 "Counter decrement comparison is not EQ or NE");
8419 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8420 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8421 (CC == ISD::SETNE && !Val);
8423 // We now need to make the intrinsic dead (it cannot be instruction
8425 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8426 assert(LHS.getNode()->hasOneUse() &&
8427 "Counter decrement has more than one use");
8429 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8430 N->getOperand(0), N->getOperand(4));
8436 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8437 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8438 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8439 assert(isDot && "Can't compare against a vector result!");
8441 // If this is a comparison against something other than 0/1, then we know
8442 // that the condition is never/always true.
8443 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8444 if (Val != 0 && Val != 1) {
8445 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8446 return N->getOperand(0);
8447 // Always !=, turn it into an unconditional branch.
8448 return DAG.getNode(ISD::BR, dl, MVT::Other,
8449 N->getOperand(0), N->getOperand(4));
8452 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8454 // Create the PPCISD altivec 'dot' comparison node.
8456 LHS.getOperand(2), // LHS of compare
8457 LHS.getOperand(3), // RHS of compare
8458 DAG.getConstant(CompareOpc, MVT::i32)
8460 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8461 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8463 // Unpack the result based on how the target uses it.
8464 PPC::Predicate CompOpc;
8465 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8466 default: // Can't happen, don't crash on invalid number though.
8467 case 0: // Branch on the value of the EQ bit of CR6.
8468 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8470 case 1: // Branch on the inverted value of the EQ bit of CR6.
8471 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8473 case 2: // Branch on the value of the LT bit of CR6.
8474 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8476 case 3: // Branch on the inverted value of the LT bit of CR6.
8477 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8481 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8482 DAG.getConstant(CompOpc, MVT::i32),
8483 DAG.getRegister(PPC::CR6, MVT::i32),
8484 N->getOperand(4), CompNode.getValue(1));
8493 //===----------------------------------------------------------------------===//
8494 // Inline Assembly Support
8495 //===----------------------------------------------------------------------===//
8497 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8500 const SelectionDAG &DAG,
8501 unsigned Depth) const {
8502 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8503 switch (Op.getOpcode()) {
8505 case PPCISD::LBRX: {
8506 // lhbrx is known to have the top bits cleared out.
8507 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8508 KnownZero = 0xFFFF0000;
8511 case ISD::INTRINSIC_WO_CHAIN: {
8512 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8514 case Intrinsic::ppc_altivec_vcmpbfp_p:
8515 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8516 case Intrinsic::ppc_altivec_vcmpequb_p:
8517 case Intrinsic::ppc_altivec_vcmpequh_p:
8518 case Intrinsic::ppc_altivec_vcmpequw_p:
8519 case Intrinsic::ppc_altivec_vcmpgefp_p:
8520 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8521 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8522 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8523 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8524 case Intrinsic::ppc_altivec_vcmpgtub_p:
8525 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8526 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8527 KnownZero = ~1U; // All bits but the low one are known to be zero.
8535 /// getConstraintType - Given a constraint, return the type of
8536 /// constraint it is for this target.
8537 PPCTargetLowering::ConstraintType
8538 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8539 if (Constraint.size() == 1) {
8540 switch (Constraint[0]) {
8547 return C_RegisterClass;
8549 // FIXME: While Z does indicate a memory constraint, it specifically
8550 // indicates an r+r address (used in conjunction with the 'y' modifier
8551 // in the replacement string). Currently, we're forcing the base
8552 // register to be r0 in the asm printer (which is interpreted as zero)
8553 // and forming the complete address in the second register. This is
8557 } else if (Constraint == "wc") { // individual CR bits.
8558 return C_RegisterClass;
8559 } else if (Constraint == "wa" || Constraint == "wd" ||
8560 Constraint == "wf" || Constraint == "ws") {
8561 return C_RegisterClass; // VSX registers.
8563 return TargetLowering::getConstraintType(Constraint);
8566 /// Examine constraint type and operand type and determine a weight value.
8567 /// This object must already have been set up with the operand type
8568 /// and the current alternative constraint selected.
8569 TargetLowering::ConstraintWeight
8570 PPCTargetLowering::getSingleConstraintMatchWeight(
8571 AsmOperandInfo &info, const char *constraint) const {
8572 ConstraintWeight weight = CW_Invalid;
8573 Value *CallOperandVal = info.CallOperandVal;
8574 // If we don't have a value, we can't do a match,
8575 // but allow it at the lowest weight.
8576 if (!CallOperandVal)
8578 Type *type = CallOperandVal->getType();
8580 // Look at the constraint type.
8581 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8582 return CW_Register; // an individual CR bit.
8583 else if ((StringRef(constraint) == "wa" ||
8584 StringRef(constraint) == "wd" ||
8585 StringRef(constraint) == "wf") &&
8588 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8591 switch (*constraint) {
8593 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8596 if (type->isIntegerTy())
8597 weight = CW_Register;
8600 if (type->isFloatTy())
8601 weight = CW_Register;
8604 if (type->isDoubleTy())
8605 weight = CW_Register;
8608 if (type->isVectorTy())
8609 weight = CW_Register;
8612 weight = CW_Register;
8621 std::pair<unsigned, const TargetRegisterClass*>
8622 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8624 if (Constraint.size() == 1) {
8625 // GCC RS6000 Constraint Letters
8626 switch (Constraint[0]) {
8628 if (VT == MVT::i64 && Subtarget.isPPC64())
8629 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8630 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8632 if (VT == MVT::i64 && Subtarget.isPPC64())
8633 return std::make_pair(0U, &PPC::G8RCRegClass);
8634 return std::make_pair(0U, &PPC::GPRCRegClass);
8636 if (VT == MVT::f32 || VT == MVT::i32)
8637 return std::make_pair(0U, &PPC::F4RCRegClass);
8638 if (VT == MVT::f64 || VT == MVT::i64)
8639 return std::make_pair(0U, &PPC::F8RCRegClass);
8642 return std::make_pair(0U, &PPC::VRRCRegClass);
8644 return std::make_pair(0U, &PPC::CRRCRegClass);
8646 } else if (Constraint == "wc") { // an individual CR bit.
8647 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8648 } else if (Constraint == "wa" || Constraint == "wd" ||
8649 Constraint == "wf") {
8650 return std::make_pair(0U, &PPC::VSRCRegClass);
8651 } else if (Constraint == "ws") {
8652 return std::make_pair(0U, &PPC::VSFRCRegClass);
8655 std::pair<unsigned, const TargetRegisterClass*> R =
8656 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8658 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8659 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8660 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8662 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8663 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8664 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8665 PPC::GPRCRegClass.contains(R.first)) {
8666 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8667 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8668 PPC::sub_32, &PPC::G8RCRegClass),
8669 &PPC::G8RCRegClass);
8676 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8677 /// vector. If it is invalid, don't add anything to Ops.
8678 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8679 std::string &Constraint,
8680 std::vector<SDValue>&Ops,
8681 SelectionDAG &DAG) const {
8684 // Only support length 1 constraints.
8685 if (Constraint.length() > 1) return;
8687 char Letter = Constraint[0];
8698 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8699 if (!CST) return; // Must be an immediate to match.
8700 unsigned Value = CST->getZExtValue();
8702 default: llvm_unreachable("Unknown constraint letter!");
8703 case 'I': // "I" is a signed 16-bit constant.
8704 if ((short)Value == (int)Value)
8705 Result = DAG.getTargetConstant(Value, Op.getValueType());
8707 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8708 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8709 if ((short)Value == 0)
8710 Result = DAG.getTargetConstant(Value, Op.getValueType());
8712 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8713 if ((Value >> 16) == 0)
8714 Result = DAG.getTargetConstant(Value, Op.getValueType());
8716 case 'M': // "M" is a constant that is greater than 31.
8718 Result = DAG.getTargetConstant(Value, Op.getValueType());
8720 case 'N': // "N" is a positive constant that is an exact power of two.
8721 if ((int)Value > 0 && isPowerOf2_32(Value))
8722 Result = DAG.getTargetConstant(Value, Op.getValueType());
8724 case 'O': // "O" is the constant zero.
8726 Result = DAG.getTargetConstant(Value, Op.getValueType());
8728 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8729 if ((short)-Value == (int)-Value)
8730 Result = DAG.getTargetConstant(Value, Op.getValueType());
8737 if (Result.getNode()) {
8738 Ops.push_back(Result);
8742 // Handle standard constraint letters.
8743 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8746 // isLegalAddressingMode - Return true if the addressing mode represented
8747 // by AM is legal for this target, for a load/store of the specified type.
8748 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8750 // FIXME: PPC does not allow r+i addressing modes for vectors!
8752 // PPC allows a sign-extended 16-bit immediate field.
8753 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8756 // No global is ever allowed as a base.
8760 // PPC only support r+r,
8762 case 0: // "r+i" or just "i", depending on HasBaseReg.
8765 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8767 // Otherwise we have r+r or r+i.
8770 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8772 // Allow 2*r as r+r.
8775 // No other scales are supported.
8782 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8783 SelectionDAG &DAG) const {
8784 MachineFunction &MF = DAG.getMachineFunction();
8785 MachineFrameInfo *MFI = MF.getFrameInfo();
8786 MFI->setReturnAddressIsTaken(true);
8788 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8792 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8794 // Make sure the function does not optimize away the store of the RA to
8796 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8797 FuncInfo->setLRStoreRequired();
8798 bool isPPC64 = Subtarget.isPPC64();
8799 bool isDarwinABI = Subtarget.isDarwinABI();
8802 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8805 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8806 isPPC64? MVT::i64 : MVT::i32);
8807 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8808 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8810 MachinePointerInfo(), false, false, false, 0);
8813 // Just load the return address off the stack.
8814 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8815 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8816 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8819 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8820 SelectionDAG &DAG) const {
8822 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8824 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8825 bool isPPC64 = PtrVT == MVT::i64;
8827 MachineFunction &MF = DAG.getMachineFunction();
8828 MachineFrameInfo *MFI = MF.getFrameInfo();
8829 MFI->setFrameAddressIsTaken(true);
8831 // Naked functions never have a frame pointer, and so we use r1. For all
8832 // other functions, this decision must be delayed until during PEI.
8834 if (MF.getFunction()->getAttributes().hasAttribute(
8835 AttributeSet::FunctionIndex, Attribute::Naked))
8836 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8838 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8840 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8843 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8844 FrameAddr, MachinePointerInfo(), false, false,
8849 // FIXME? Maybe this could be a TableGen attribute on some registers and
8850 // this table could be generated automatically from RegInfo.
8851 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
8853 bool isPPC64 = Subtarget.isPPC64();
8854 bool isDarwinABI = Subtarget.isDarwinABI();
8856 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
8857 (!isPPC64 && VT != MVT::i32))
8858 report_fatal_error("Invalid register global variable type");
8860 bool is64Bit = isPPC64 && VT == MVT::i64;
8861 unsigned Reg = StringSwitch<unsigned>(RegName)
8862 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
8863 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
8864 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
8865 (is64Bit ? PPC::X13 : PPC::R13))
8870 report_fatal_error("Invalid register name global variable");
8874 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8875 // The PowerPC target isn't yet aware of offsets.
8879 /// getOptimalMemOpType - Returns the target specific optimal type for load
8880 /// and store operations as a result of memset, memcpy, and memmove
8881 /// lowering. If DstAlign is zero that means it's safe to destination
8882 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8883 /// means there isn't a need to check it against alignment requirement,
8884 /// probably because the source does not need to be loaded. If 'IsMemset' is
8885 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8886 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8887 /// source is constant so it does not need to be loaded.
8888 /// It returns EVT::Other if the type should be determined using generic
8889 /// target-independent logic.
8890 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8891 unsigned DstAlign, unsigned SrcAlign,
8892 bool IsMemset, bool ZeroMemset,
8894 MachineFunction &MF) const {
8895 if (Subtarget.isPPC64()) {
8902 /// \brief Returns true if it is beneficial to convert a load of a constant
8903 /// to just the constant itself.
8904 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
8906 assert(Ty->isIntegerTy());
8908 unsigned BitSize = Ty->getPrimitiveSizeInBits();
8909 if (BitSize == 0 || BitSize > 64)
8914 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
8915 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8917 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8918 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8919 return NumBits1 == 64 && NumBits2 == 32;
8922 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8923 if (!VT1.isInteger() || !VT2.isInteger())
8925 unsigned NumBits1 = VT1.getSizeInBits();
8926 unsigned NumBits2 = VT2.getSizeInBits();
8927 return NumBits1 == 64 && NumBits2 == 32;
8930 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8931 return isInt<16>(Imm) || isUInt<16>(Imm);
8934 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8935 return isInt<16>(Imm) || isUInt<16>(Imm);
8938 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8941 if (DisablePPCUnaligned)
8944 // PowerPC supports unaligned memory access for simple non-vector types.
8945 // Although accessing unaligned addresses is not as efficient as accessing
8946 // aligned addresses, it is generally more efficient than manual expansion,
8947 // and generally only traps for software emulation when crossing page
8953 if (VT.getSimpleVT().isVector()) {
8954 if (Subtarget.hasVSX()) {
8955 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8962 if (VT == MVT::ppcf128)
8971 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8972 VT = VT.getScalarType();
8977 switch (VT.getSimpleVT().SimpleTy) {
8989 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
8990 EVT VT , unsigned DefinedValues) const {
8991 if (VT == MVT::v2i64)
8994 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
8997 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
8998 if (DisableILPPref || Subtarget.enableMachineScheduler())
8999 return TargetLowering::getSchedulingPreference(N);
9004 // Create a fast isel object.
9006 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9007 const TargetLibraryInfo *LibInfo) const {
9008 return PPC::createFastISel(FuncInfo, LibInfo);