1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
46 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
48 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
49 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
51 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
52 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
54 // FIXME: Remove this once the bug has been fixed!
55 extern cl::opt<bool> ANDIGlueBug;
57 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
58 const PPCSubtarget &STI)
59 : TargetLowering(TM), Subtarget(STI) {
60 // Use _setjmp/_longjmp instead of setjmp/longjmp.
61 setUseUnderscoreSetJmp(true);
62 setUseUnderscoreLongJmp(true);
64 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
65 // arguments are at least 4/8 bytes aligned.
66 bool isPPC64 = Subtarget.isPPC64();
67 setMinStackArgumentAlignment(isPPC64 ? 8:4);
69 // Set up the register classes.
70 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
71 if (!Subtarget.useSoftFloat()) {
72 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
73 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
76 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
77 for (MVT VT : MVT::integer_valuetypes()) {
78 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
82 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
84 // PowerPC has pre-inc load and store's.
85 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 for (MVT VT : MVT::integer_valuetypes()) {
124 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
126 setTruncStoreAction(VT, MVT::i1, Expand);
129 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
132 // This is used in the ppcf128->int sequence. Note it has different semantics
133 // from FP_ROUND: that rounds to nearest, this rounds to zero.
134 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
136 // We do not currently implement these libm ops for PowerPC.
137 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
138 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
144 // PowerPC has no SREM/UREM instructions
145 setOperationAction(ISD::SREM, MVT::i32, Expand);
146 setOperationAction(ISD::UREM, MVT::i32, Expand);
147 setOperationAction(ISD::SREM, MVT::i64, Expand);
148 setOperationAction(ISD::UREM, MVT::i64, Expand);
150 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
151 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
152 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
156 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
160 // We don't support sin/cos/sqrt/fmod/pow
161 setOperationAction(ISD::FSIN , MVT::f64, Expand);
162 setOperationAction(ISD::FCOS , MVT::f64, Expand);
163 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
164 setOperationAction(ISD::FREM , MVT::f64, Expand);
165 setOperationAction(ISD::FPOW , MVT::f64, Expand);
166 setOperationAction(ISD::FMA , MVT::f64, Legal);
167 setOperationAction(ISD::FSIN , MVT::f32, Expand);
168 setOperationAction(ISD::FCOS , MVT::f32, Expand);
169 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
170 setOperationAction(ISD::FREM , MVT::f32, Expand);
171 setOperationAction(ISD::FPOW , MVT::f32, Expand);
172 setOperationAction(ISD::FMA , MVT::f32, Legal);
174 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
176 // If we're enabling GP optimizations, use hardware square root
177 if (!Subtarget.hasFSQRT() &&
178 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
180 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
182 if (!Subtarget.hasFSQRT() &&
183 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
184 Subtarget.hasFRES()))
185 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
187 if (Subtarget.hasFCPSGN()) {
188 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
189 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
195 if (Subtarget.hasFPRND()) {
196 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
197 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
198 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
199 setOperationAction(ISD::FROUND, MVT::f64, Legal);
201 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
202 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
203 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
204 setOperationAction(ISD::FROUND, MVT::f32, Legal);
207 // PowerPC does not have BSWAP, CTPOP or CTTZ
208 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
209 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
211 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
213 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
215 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
217 if (Subtarget.hasPOPCNTD()) {
218 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
219 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
222 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
225 // PowerPC does not have ROTR
226 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
227 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
229 if (!Subtarget.useCRBits()) {
230 // PowerPC does not have Select
231 setOperationAction(ISD::SELECT, MVT::i32, Expand);
232 setOperationAction(ISD::SELECT, MVT::i64, Expand);
233 setOperationAction(ISD::SELECT, MVT::f32, Expand);
234 setOperationAction(ISD::SELECT, MVT::f64, Expand);
237 // PowerPC wants to turn select_cc of FP into fsel when possible.
238 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
239 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
241 // PowerPC wants to optimize integer setcc a bit
242 if (!Subtarget.useCRBits())
243 setOperationAction(ISD::SETCC, MVT::i32, Custom);
245 // PowerPC does not have BRCOND which requires SetCC
246 if (!Subtarget.useCRBits())
247 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
249 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
251 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
252 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
254 // PowerPC does not have [U|S]INT_TO_FP
255 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
256 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
261 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
263 // We cannot sextinreg(i1). Expand to shifts.
264 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
266 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
267 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
268 // support continuation, user-level threading, and etc.. As a result, no
269 // other SjLj exception interfaces are implemented and please don't build
270 // your own exception handling based on them.
271 // LLVM/Clang supports zero-cost DWARF exception handling.
272 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
273 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
275 // We want to legalize GlobalAddress and ConstantPool nodes into the
276 // appropriate instructions to materialize the address.
277 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
278 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
279 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
280 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
281 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
282 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
283 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
284 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
285 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
286 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
289 setOperationAction(ISD::TRAP, MVT::Other, Legal);
291 // TRAMPOLINE is custom lowered.
292 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
293 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
295 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
296 setOperationAction(ISD::VASTART , MVT::Other, Custom);
298 if (Subtarget.isSVR4ABI()) {
300 // VAARG always uses double-word chunks, so promote anything smaller.
301 setOperationAction(ISD::VAARG, MVT::i1, Promote);
302 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
303 setOperationAction(ISD::VAARG, MVT::i8, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i16, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i32, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::Other, Expand);
311 // VAARG is custom lowered with the 32-bit SVR4 ABI.
312 setOperationAction(ISD::VAARG, MVT::Other, Custom);
313 setOperationAction(ISD::VAARG, MVT::i64, Custom);
316 setOperationAction(ISD::VAARG, MVT::Other, Expand);
318 if (Subtarget.isSVR4ABI() && !isPPC64)
319 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
320 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
322 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
324 // Use the default implementation.
325 setOperationAction(ISD::VAEND , MVT::Other, Expand);
326 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
327 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
328 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
330 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
331 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget.has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (Subtarget.hasFPCVT()) {
372 if (Subtarget.has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget.use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget.hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (MVT VT : MVT::vector_valuetypes()) {
405 // add/sub are legal for all supported vector VT's.
406 setOperationAction(ISD::ADD, VT, Legal);
407 setOperationAction(ISD::SUB, VT, Legal);
409 // Vector instructions introduced in P8
410 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
411 setOperationAction(ISD::CTPOP, VT, Legal);
412 setOperationAction(ISD::CTLZ, VT, Legal);
415 setOperationAction(ISD::CTPOP, VT, Expand);
416 setOperationAction(ISD::CTLZ, VT, Expand);
419 // We promote all shuffles to v16i8.
420 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
421 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
423 // We promote all non-typed operations to v4i32.
424 setOperationAction(ISD::AND , VT, Promote);
425 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 setOperationAction(ISD::OR , VT, Promote);
427 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 setOperationAction(ISD::XOR , VT, Promote);
429 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 setOperationAction(ISD::LOAD , VT, Promote);
431 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 setOperationAction(ISD::SELECT, VT, Promote);
433 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 setOperationAction(ISD::SELECT_CC, VT, Promote);
435 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
436 setOperationAction(ISD::STORE, VT, Promote);
437 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
439 // No other operations are legal.
440 setOperationAction(ISD::MUL , VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::SREM, VT, Expand);
443 setOperationAction(ISD::UDIV, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
445 setOperationAction(ISD::FDIV, VT, Expand);
446 setOperationAction(ISD::FREM, VT, Expand);
447 setOperationAction(ISD::FNEG, VT, Expand);
448 setOperationAction(ISD::FSQRT, VT, Expand);
449 setOperationAction(ISD::FLOG, VT, Expand);
450 setOperationAction(ISD::FLOG10, VT, Expand);
451 setOperationAction(ISD::FLOG2, VT, Expand);
452 setOperationAction(ISD::FEXP, VT, Expand);
453 setOperationAction(ISD::FEXP2, VT, Expand);
454 setOperationAction(ISD::FSIN, VT, Expand);
455 setOperationAction(ISD::FCOS, VT, Expand);
456 setOperationAction(ISD::FABS, VT, Expand);
457 setOperationAction(ISD::FPOWI, VT, Expand);
458 setOperationAction(ISD::FFLOOR, VT, Expand);
459 setOperationAction(ISD::FCEIL, VT, Expand);
460 setOperationAction(ISD::FTRUNC, VT, Expand);
461 setOperationAction(ISD::FRINT, VT, Expand);
462 setOperationAction(ISD::FNEARBYINT, VT, Expand);
463 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
464 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
465 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
466 setOperationAction(ISD::MULHU, VT, Expand);
467 setOperationAction(ISD::MULHS, VT, Expand);
468 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
469 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
470 setOperationAction(ISD::UDIVREM, VT, Expand);
471 setOperationAction(ISD::SDIVREM, VT, Expand);
472 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
473 setOperationAction(ISD::FPOW, VT, Expand);
474 setOperationAction(ISD::BSWAP, VT, Expand);
475 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
476 setOperationAction(ISD::CTTZ, VT, Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
478 setOperationAction(ISD::VSELECT, VT, Expand);
479 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
480 setOperationAction(ISD::ROTL, VT, Expand);
481 setOperationAction(ISD::ROTR, VT, Expand);
483 for (MVT InnerVT : MVT::vector_valuetypes()) {
484 setTruncStoreAction(VT, InnerVT, Expand);
485 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
486 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
487 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
491 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
492 // with merges, splats, etc.
493 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
495 setOperationAction(ISD::AND , MVT::v4i32, Legal);
496 setOperationAction(ISD::OR , MVT::v4i32, Legal);
497 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
498 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
499 setOperationAction(ISD::SELECT, MVT::v4i32,
500 Subtarget.useCRBits() ? Legal : Expand);
501 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
502 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
503 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
504 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
505 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
506 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
507 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
508 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
509 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
511 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
512 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
513 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
514 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
516 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
517 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
519 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
520 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
521 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
524 if (Subtarget.hasP8Altivec())
525 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
527 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
529 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
530 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
532 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
533 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
535 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
536 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
537 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
538 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
540 // Altivec does not contain unordered floating-point compare instructions
541 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
542 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
543 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
544 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
546 if (Subtarget.hasVSX()) {
547 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
548 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
549 if (Subtarget.hasP8Vector()) {
550 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
551 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
553 if (Subtarget.hasDirectMove()) {
554 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
555 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
556 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
557 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
558 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
559 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
560 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
561 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
563 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
565 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
566 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
567 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
568 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
569 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
571 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
573 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
574 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
576 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
577 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
579 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
580 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
581 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
582 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
583 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
585 // Share the Altivec comparison restrictions.
586 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
587 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
588 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
589 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
591 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
592 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
594 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
596 if (Subtarget.hasP8Vector())
597 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
599 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
601 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
602 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
603 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
605 if (Subtarget.hasP8Altivec()) {
606 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
607 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
608 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
610 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
613 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
614 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
615 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
617 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
619 // VSX v2i64 only supports non-arithmetic operations.
620 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
621 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
624 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
625 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
626 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
627 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
629 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
631 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
632 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
633 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
634 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
636 // Vector operation legalization checks the result type of
637 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
638 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
639 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
640 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
641 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
643 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
646 if (Subtarget.hasP8Altivec()) {
647 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
648 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
652 if (Subtarget.hasQPX()) {
653 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
654 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
655 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
656 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
658 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
659 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
661 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
662 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
664 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
665 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
667 if (!Subtarget.useCRBits())
668 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
669 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
671 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
672 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
673 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
674 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
675 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
676 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
677 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
679 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
680 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
682 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
683 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
684 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
686 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
687 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
688 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
689 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
690 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
691 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
692 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
693 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
694 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
695 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
696 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
698 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
699 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
701 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
702 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
704 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
706 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
707 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
708 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
709 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
711 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
712 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
714 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
715 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
717 if (!Subtarget.useCRBits())
718 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
719 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
721 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
722 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
723 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
724 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
725 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
726 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
727 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
729 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
730 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
732 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
733 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
734 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
735 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
736 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
737 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
738 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
739 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
740 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
741 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
742 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
744 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
745 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
747 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
748 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
750 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
752 setOperationAction(ISD::AND , MVT::v4i1, Legal);
753 setOperationAction(ISD::OR , MVT::v4i1, Legal);
754 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
756 if (!Subtarget.useCRBits())
757 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
758 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
760 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
761 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
763 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
764 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
765 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
766 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
767 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
768 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
769 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
771 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
772 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
774 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
776 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
777 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
778 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
779 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
781 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
782 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
783 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
784 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
786 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
787 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
789 // These need to set FE_INEXACT, and so cannot be vectorized here.
790 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
791 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
793 if (TM.Options.UnsafeFPMath) {
794 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
795 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
797 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
798 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
800 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
801 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
803 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
804 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
808 if (Subtarget.has64BitSupport())
809 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
811 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
814 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
815 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
818 setBooleanContents(ZeroOrOneBooleanContent);
820 if (Subtarget.hasAltivec()) {
821 // Altivec instructions set fields to all zeros or all ones.
822 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
826 // These libcalls are not available in 32-bit.
827 setLibcallName(RTLIB::SHL_I128, nullptr);
828 setLibcallName(RTLIB::SRL_I128, nullptr);
829 setLibcallName(RTLIB::SRA_I128, nullptr);
832 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
834 // We have target-specific dag combine patterns for the following nodes:
835 setTargetDAGCombine(ISD::SINT_TO_FP);
836 if (Subtarget.hasFPCVT())
837 setTargetDAGCombine(ISD::UINT_TO_FP);
838 setTargetDAGCombine(ISD::LOAD);
839 setTargetDAGCombine(ISD::STORE);
840 setTargetDAGCombine(ISD::BR_CC);
841 if (Subtarget.useCRBits())
842 setTargetDAGCombine(ISD::BRCOND);
843 setTargetDAGCombine(ISD::BSWAP);
844 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
845 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
846 setTargetDAGCombine(ISD::INTRINSIC_VOID);
848 setTargetDAGCombine(ISD::SIGN_EXTEND);
849 setTargetDAGCombine(ISD::ZERO_EXTEND);
850 setTargetDAGCombine(ISD::ANY_EXTEND);
852 if (Subtarget.useCRBits()) {
853 setTargetDAGCombine(ISD::TRUNCATE);
854 setTargetDAGCombine(ISD::SETCC);
855 setTargetDAGCombine(ISD::SELECT_CC);
858 // Use reciprocal estimates.
859 if (TM.Options.UnsafeFPMath) {
860 setTargetDAGCombine(ISD::FDIV);
861 setTargetDAGCombine(ISD::FSQRT);
864 // Darwin long double math library functions have $LDBL128 appended.
865 if (Subtarget.isDarwin()) {
866 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
867 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
868 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
869 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
870 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
871 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
872 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
873 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
874 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
875 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
878 // With 32 condition bits, we don't need to sink (and duplicate) compares
879 // aggressively in CodeGenPrep.
880 if (Subtarget.useCRBits()) {
881 setHasMultipleConditionRegisters();
882 setJumpIsExpensive();
885 setMinFunctionAlignment(2);
886 if (Subtarget.isDarwin())
887 setPrefFunctionAlignment(4);
889 switch (Subtarget.getDarwinDirective()) {
893 case PPC::DIR_E500mc:
902 setPrefFunctionAlignment(4);
903 setPrefLoopAlignment(4);
907 setInsertFencesForAtomic(true);
909 if (Subtarget.enableMachineScheduler())
910 setSchedulingPreference(Sched::Source);
912 setSchedulingPreference(Sched::Hybrid);
914 computeRegisterProperties(STI.getRegisterInfo());
916 // The Freescale cores do better with aggressive inlining of memcpy and
917 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
918 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
919 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
920 MaxStoresPerMemset = 32;
921 MaxStoresPerMemsetOptSize = 16;
922 MaxStoresPerMemcpy = 32;
923 MaxStoresPerMemcpyOptSize = 8;
924 MaxStoresPerMemmove = 32;
925 MaxStoresPerMemmoveOptSize = 8;
926 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
927 // The A2 also benefits from (very) aggressive inlining of memcpy and
928 // friends. The overhead of a the function call, even when warm, can be
929 // over one hundred cycles.
930 MaxStoresPerMemset = 128;
931 MaxStoresPerMemcpy = 128;
932 MaxStoresPerMemmove = 128;
936 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
937 /// the desired ByVal argument alignment.
938 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
939 unsigned MaxMaxAlign) {
940 if (MaxAlign == MaxMaxAlign)
942 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
943 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
945 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
947 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
948 unsigned EltAlign = 0;
949 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
950 if (EltAlign > MaxAlign)
952 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
953 for (auto *EltTy : STy->elements()) {
954 unsigned EltAlign = 0;
955 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
956 if (EltAlign > MaxAlign)
958 if (MaxAlign == MaxMaxAlign)
964 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
965 /// function arguments in the caller parameter area.
966 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
967 const DataLayout &DL) const {
968 // Darwin passes everything on 4 byte boundary.
969 if (Subtarget.isDarwin())
972 // 16byte and wider vectors are passed on 16byte boundary.
973 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
974 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
975 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
976 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
980 bool PPCTargetLowering::useSoftFloat() const {
981 return Subtarget.useSoftFloat();
984 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
985 switch ((PPCISD::NodeType)Opcode) {
986 case PPCISD::FIRST_NUMBER: break;
987 case PPCISD::FSEL: return "PPCISD::FSEL";
988 case PPCISD::FCFID: return "PPCISD::FCFID";
989 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
990 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
991 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
992 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
993 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
994 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
995 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
996 case PPCISD::FRE: return "PPCISD::FRE";
997 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
998 case PPCISD::STFIWX: return "PPCISD::STFIWX";
999 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
1000 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
1001 case PPCISD::VPERM: return "PPCISD::VPERM";
1002 case PPCISD::CMPB: return "PPCISD::CMPB";
1003 case PPCISD::Hi: return "PPCISD::Hi";
1004 case PPCISD::Lo: return "PPCISD::Lo";
1005 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1006 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1007 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1008 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1009 case PPCISD::SRL: return "PPCISD::SRL";
1010 case PPCISD::SRA: return "PPCISD::SRA";
1011 case PPCISD::SHL: return "PPCISD::SHL";
1012 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1013 case PPCISD::CALL: return "PPCISD::CALL";
1014 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1015 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1016 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1017 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1018 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1019 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1020 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1021 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1022 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1023 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1024 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1025 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1026 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1027 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1028 case PPCISD::VCMP: return "PPCISD::VCMP";
1029 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1030 case PPCISD::LBRX: return "PPCISD::LBRX";
1031 case PPCISD::STBRX: return "PPCISD::STBRX";
1032 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1033 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1034 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1035 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1036 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1037 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1038 case PPCISD::BDZ: return "PPCISD::BDZ";
1039 case PPCISD::MFFS: return "PPCISD::MFFS";
1040 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1041 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1042 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1043 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1044 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1045 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1046 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1047 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1048 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1049 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1050 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1051 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1052 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1053 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1054 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1055 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1056 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1057 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1058 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1059 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1060 case PPCISD::SC: return "PPCISD::SC";
1061 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1062 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1063 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1064 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1065 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1066 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1067 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1068 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1069 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1070 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1075 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1078 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1080 if (Subtarget.hasQPX())
1081 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1083 return VT.changeVectorElementTypeToInteger();
1086 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1087 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1091 //===----------------------------------------------------------------------===//
1092 // Node matching predicates, for use by the tblgen matching code.
1093 //===----------------------------------------------------------------------===//
1095 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1096 static bool isFloatingPointZero(SDValue Op) {
1097 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1098 return CFP->getValueAPF().isZero();
1099 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1100 // Maybe this has already been legalized into the constant pool?
1101 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1102 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1103 return CFP->getValueAPF().isZero();
1108 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1109 /// true if Op is undef or if it matches the specified value.
1110 static bool isConstantOrUndef(int Op, int Val) {
1111 return Op < 0 || Op == Val;
1114 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1115 /// VPKUHUM instruction.
1116 /// The ShuffleKind distinguishes between big-endian operations with
1117 /// two different inputs (0), either-endian operations with two identical
1118 /// inputs (1), and little-endian operations with two different inputs (2).
1119 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1120 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1121 SelectionDAG &DAG) {
1122 bool IsLE = DAG.getDataLayout().isLittleEndian();
1123 if (ShuffleKind == 0) {
1126 for (unsigned i = 0; i != 16; ++i)
1127 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1129 } else if (ShuffleKind == 2) {
1132 for (unsigned i = 0; i != 16; ++i)
1133 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1135 } else if (ShuffleKind == 1) {
1136 unsigned j = IsLE ? 0 : 1;
1137 for (unsigned i = 0; i != 8; ++i)
1138 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1139 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1145 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1146 /// VPKUWUM instruction.
1147 /// The ShuffleKind distinguishes between big-endian operations with
1148 /// two different inputs (0), either-endian operations with two identical
1149 /// inputs (1), and little-endian operations with two different inputs (2).
1150 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1151 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1152 SelectionDAG &DAG) {
1153 bool IsLE = DAG.getDataLayout().isLittleEndian();
1154 if (ShuffleKind == 0) {
1157 for (unsigned i = 0; i != 16; i += 2)
1158 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1159 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1161 } else if (ShuffleKind == 2) {
1164 for (unsigned i = 0; i != 16; i += 2)
1165 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1166 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1168 } else if (ShuffleKind == 1) {
1169 unsigned j = IsLE ? 0 : 2;
1170 for (unsigned i = 0; i != 8; i += 2)
1171 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1172 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1173 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1174 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1180 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1181 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1182 /// current subtarget.
1184 /// The ShuffleKind distinguishes between big-endian operations with
1185 /// two different inputs (0), either-endian operations with two identical
1186 /// inputs (1), and little-endian operations with two different inputs (2).
1187 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1188 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1189 SelectionDAG &DAG) {
1190 const PPCSubtarget& Subtarget =
1191 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1192 if (!Subtarget.hasP8Vector())
1195 bool IsLE = DAG.getDataLayout().isLittleEndian();
1196 if (ShuffleKind == 0) {
1199 for (unsigned i = 0; i != 16; i += 4)
1200 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1201 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1202 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1203 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1205 } else if (ShuffleKind == 2) {
1208 for (unsigned i = 0; i != 16; i += 4)
1209 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1210 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1211 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1212 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1214 } else if (ShuffleKind == 1) {
1215 unsigned j = IsLE ? 0 : 4;
1216 for (unsigned i = 0; i != 8; i += 4)
1217 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1218 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1219 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1220 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1221 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1222 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1223 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1224 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1230 /// isVMerge - Common function, used to match vmrg* shuffles.
1232 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1233 unsigned LHSStart, unsigned RHSStart) {
1234 if (N->getValueType(0) != MVT::v16i8)
1236 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1237 "Unsupported merge size!");
1239 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1240 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1241 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1242 LHSStart+j+i*UnitSize) ||
1243 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1244 RHSStart+j+i*UnitSize))
1250 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1251 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1252 /// The ShuffleKind distinguishes between big-endian merges with two
1253 /// different inputs (0), either-endian merges with two identical inputs (1),
1254 /// and little-endian merges with two different inputs (2). For the latter,
1255 /// the input operands are swapped (see PPCInstrAltivec.td).
1256 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1257 unsigned ShuffleKind, SelectionDAG &DAG) {
1258 if (DAG.getDataLayout().isLittleEndian()) {
1259 if (ShuffleKind == 1) // unary
1260 return isVMerge(N, UnitSize, 0, 0);
1261 else if (ShuffleKind == 2) // swapped
1262 return isVMerge(N, UnitSize, 0, 16);
1266 if (ShuffleKind == 1) // unary
1267 return isVMerge(N, UnitSize, 8, 8);
1268 else if (ShuffleKind == 0) // normal
1269 return isVMerge(N, UnitSize, 8, 24);
1275 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1276 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1277 /// The ShuffleKind distinguishes between big-endian merges with two
1278 /// different inputs (0), either-endian merges with two identical inputs (1),
1279 /// and little-endian merges with two different inputs (2). For the latter,
1280 /// the input operands are swapped (see PPCInstrAltivec.td).
1281 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1282 unsigned ShuffleKind, SelectionDAG &DAG) {
1283 if (DAG.getDataLayout().isLittleEndian()) {
1284 if (ShuffleKind == 1) // unary
1285 return isVMerge(N, UnitSize, 8, 8);
1286 else if (ShuffleKind == 2) // swapped
1287 return isVMerge(N, UnitSize, 8, 24);
1291 if (ShuffleKind == 1) // unary
1292 return isVMerge(N, UnitSize, 0, 0);
1293 else if (ShuffleKind == 0) // normal
1294 return isVMerge(N, UnitSize, 0, 16);
1301 * \brief Common function used to match vmrgew and vmrgow shuffles
1303 * The indexOffset determines whether to look for even or odd words in
1304 * the shuffle mask. This is based on the of the endianness of the target
1307 * - Use offset of 0 to check for odd elements
1308 * - Use offset of 4 to check for even elements
1310 * - Use offset of 0 to check for even elements
1311 * - Use offset of 4 to check for odd elements
1312 * A detailed description of the vector element ordering for little endian and
1313 * big endian can be found at
1314 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1315 * Targeting your applications - what little endian and big endian IBM XL C/C++
1316 * compiler differences mean to you
1318 * The mask to the shuffle vector instruction specifies the indices of the
1319 * elements from the two input vectors to place in the result. The elements are
1320 * numbered in array-access order, starting with the first vector. These vectors
1321 * are always of type v16i8, thus each vector will contain 16 elements of size
1322 * 8. More info on the shuffle vector can be found in the
1323 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1324 * Language Reference.
1326 * The RHSStartValue indicates whether the same input vectors are used (unary)
1327 * or two different input vectors are used, based on the following:
1328 * - If the instruction uses the same vector for both inputs, the range of the
1329 * indices will be 0 to 15. In this case, the RHSStart value passed should
1331 * - If the instruction has two different vectors then the range of the
1332 * indices will be 0 to 31. In this case, the RHSStart value passed should
1333 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1334 * to 31 specify elements in the second vector).
1336 * \param[in] N The shuffle vector SD Node to analyze
1337 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1338 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1339 * vector to the shuffle_vector instruction
1340 * \return true iff this shuffle vector represents an even or odd word merge
1342 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1343 unsigned RHSStartValue) {
1344 if (N->getValueType(0) != MVT::v16i8)
1347 for (unsigned i = 0; i < 2; ++i)
1348 for (unsigned j = 0; j < 4; ++j)
1349 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1350 i*RHSStartValue+j+IndexOffset) ||
1351 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1352 i*RHSStartValue+j+IndexOffset+8))
1358 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1359 * vmrgow instructions.
1361 * \param[in] N The shuffle vector SD Node to analyze
1362 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1363 * \param[in] ShuffleKind Identify the type of merge:
1364 * - 0 = big-endian merge with two different inputs;
1365 * - 1 = either-endian merge with two identical inputs;
1366 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1367 * little-endian merges).
1368 * \param[in] DAG The current SelectionDAG
1369 * \return true iff this shuffle mask
1371 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1372 unsigned ShuffleKind, SelectionDAG &DAG) {
1373 if (DAG.getDataLayout().isLittleEndian()) {
1374 unsigned indexOffset = CheckEven ? 4 : 0;
1375 if (ShuffleKind == 1) // Unary
1376 return isVMerge(N, indexOffset, 0);
1377 else if (ShuffleKind == 2) // swapped
1378 return isVMerge(N, indexOffset, 16);
1383 unsigned indexOffset = CheckEven ? 0 : 4;
1384 if (ShuffleKind == 1) // Unary
1385 return isVMerge(N, indexOffset, 0);
1386 else if (ShuffleKind == 0) // Normal
1387 return isVMerge(N, indexOffset, 16);
1394 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1395 /// amount, otherwise return -1.
1396 /// The ShuffleKind distinguishes between big-endian operations with two
1397 /// different inputs (0), either-endian operations with two identical inputs
1398 /// (1), and little-endian operations with two different inputs (2). For the
1399 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1400 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1401 SelectionDAG &DAG) {
1402 if (N->getValueType(0) != MVT::v16i8)
1405 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1407 // Find the first non-undef value in the shuffle mask.
1409 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1412 if (i == 16) return -1; // all undef.
1414 // Otherwise, check to see if the rest of the elements are consecutively
1415 // numbered from this value.
1416 unsigned ShiftAmt = SVOp->getMaskElt(i);
1417 if (ShiftAmt < i) return -1;
1420 bool isLE = DAG.getDataLayout().isLittleEndian();
1422 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1423 // Check the rest of the elements to see if they are consecutive.
1424 for (++i; i != 16; ++i)
1425 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1427 } else if (ShuffleKind == 1) {
1428 // Check the rest of the elements to see if they are consecutive.
1429 for (++i; i != 16; ++i)
1430 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1436 ShiftAmt = 16 - ShiftAmt;
1441 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1442 /// specifies a splat of a single element that is suitable for input to
1443 /// VSPLTB/VSPLTH/VSPLTW.
1444 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1445 assert(N->getValueType(0) == MVT::v16i8 &&
1446 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1448 // The consecutive indices need to specify an element, not part of two
1449 // different elements. So abandon ship early if this isn't the case.
1450 if (N->getMaskElt(0) % EltSize != 0)
1453 // This is a splat operation if each element of the permute is the same, and
1454 // if the value doesn't reference the second vector.
1455 unsigned ElementBase = N->getMaskElt(0);
1457 // FIXME: Handle UNDEF elements too!
1458 if (ElementBase >= 16)
1461 // Check that the indices are consecutive, in the case of a multi-byte element
1462 // splatted with a v16i8 mask.
1463 for (unsigned i = 1; i != EltSize; ++i)
1464 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1467 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1468 if (N->getMaskElt(i) < 0) continue;
1469 for (unsigned j = 0; j != EltSize; ++j)
1470 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1476 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1477 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1478 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1479 SelectionDAG &DAG) {
1480 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1481 assert(isSplatShuffleMask(SVOp, EltSize));
1482 if (DAG.getDataLayout().isLittleEndian())
1483 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1485 return SVOp->getMaskElt(0) / EltSize;
1488 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1489 /// by using a vspltis[bhw] instruction of the specified element size, return
1490 /// the constant being splatted. The ByteSize field indicates the number of
1491 /// bytes of each element [124] -> [bhw].
1492 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1493 SDValue OpVal(nullptr, 0);
1495 // If ByteSize of the splat is bigger than the element size of the
1496 // build_vector, then we have a case where we are checking for a splat where
1497 // multiple elements of the buildvector are folded together into a single
1498 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1499 unsigned EltSize = 16/N->getNumOperands();
1500 if (EltSize < ByteSize) {
1501 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1502 SDValue UniquedVals[4];
1503 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1505 // See if all of the elements in the buildvector agree across.
1506 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1507 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1508 // If the element isn't a constant, bail fully out.
1509 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1512 if (!UniquedVals[i&(Multiple-1)].getNode())
1513 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1514 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1515 return SDValue(); // no match.
1518 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1519 // either constant or undef values that are identical for each chunk. See
1520 // if these chunks can form into a larger vspltis*.
1522 // Check to see if all of the leading entries are either 0 or -1. If
1523 // neither, then this won't fit into the immediate field.
1524 bool LeadingZero = true;
1525 bool LeadingOnes = true;
1526 for (unsigned i = 0; i != Multiple-1; ++i) {
1527 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1529 LeadingZero &= isNullConstant(UniquedVals[i]);
1530 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
1532 // Finally, check the least significant entry.
1534 if (!UniquedVals[Multiple-1].getNode())
1535 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1536 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1537 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1538 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1541 if (!UniquedVals[Multiple-1].getNode())
1542 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1543 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1544 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1545 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1551 // Check to see if this buildvec has a single non-undef value in its elements.
1552 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1553 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1554 if (!OpVal.getNode())
1555 OpVal = N->getOperand(i);
1556 else if (OpVal != N->getOperand(i))
1560 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1562 unsigned ValSizeInBytes = EltSize;
1564 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1565 Value = CN->getZExtValue();
1566 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1567 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1568 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1571 // If the splat value is larger than the element value, then we can never do
1572 // this splat. The only case that we could fit the replicated bits into our
1573 // immediate field for would be zero, and we prefer to use vxor for it.
1574 if (ValSizeInBytes < ByteSize) return SDValue();
1576 // If the element value is larger than the splat value, check if it consists
1577 // of a repeated bit pattern of size ByteSize.
1578 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1581 // Properly sign extend the value.
1582 int MaskVal = SignExtend32(Value, ByteSize * 8);
1584 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1585 if (MaskVal == 0) return SDValue();
1587 // Finally, if this value fits in a 5 bit sext field, return it
1588 if (SignExtend32<5>(MaskVal) == MaskVal)
1589 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1593 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1594 /// amount, otherwise return -1.
1595 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1596 EVT VT = N->getValueType(0);
1597 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1600 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1602 // Find the first non-undef value in the shuffle mask.
1604 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1607 if (i == 4) return -1; // all undef.
1609 // Otherwise, check to see if the rest of the elements are consecutively
1610 // numbered from this value.
1611 unsigned ShiftAmt = SVOp->getMaskElt(i);
1612 if (ShiftAmt < i) return -1;
1615 // Check the rest of the elements to see if they are consecutive.
1616 for (++i; i != 4; ++i)
1617 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1623 //===----------------------------------------------------------------------===//
1624 // Addressing Mode Selection
1625 //===----------------------------------------------------------------------===//
1627 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1628 /// or 64-bit immediate, and if the value can be accurately represented as a
1629 /// sign extension from a 16-bit value. If so, this returns true and the
1631 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1632 if (!isa<ConstantSDNode>(N))
1635 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1636 if (N->getValueType(0) == MVT::i32)
1637 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1639 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1641 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1642 return isIntS16Immediate(Op.getNode(), Imm);
1645 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1646 /// can be represented as an indexed [r+r] operation. Returns false if it
1647 /// can be more efficiently represented with [r+imm].
1648 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1650 SelectionDAG &DAG) const {
1652 if (N.getOpcode() == ISD::ADD) {
1653 if (isIntS16Immediate(N.getOperand(1), imm))
1654 return false; // r+i
1655 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1656 return false; // r+i
1658 Base = N.getOperand(0);
1659 Index = N.getOperand(1);
1661 } else if (N.getOpcode() == ISD::OR) {
1662 if (isIntS16Immediate(N.getOperand(1), imm))
1663 return false; // r+i can fold it if we can.
1665 // If this is an or of disjoint bitfields, we can codegen this as an add
1666 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1668 APInt LHSKnownZero, LHSKnownOne;
1669 APInt RHSKnownZero, RHSKnownOne;
1670 DAG.computeKnownBits(N.getOperand(0),
1671 LHSKnownZero, LHSKnownOne);
1673 if (LHSKnownZero.getBoolValue()) {
1674 DAG.computeKnownBits(N.getOperand(1),
1675 RHSKnownZero, RHSKnownOne);
1676 // If all of the bits are known zero on the LHS or RHS, the add won't
1678 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1679 Base = N.getOperand(0);
1680 Index = N.getOperand(1);
1689 // If we happen to be doing an i64 load or store into a stack slot that has
1690 // less than a 4-byte alignment, then the frame-index elimination may need to
1691 // use an indexed load or store instruction (because the offset may not be a
1692 // multiple of 4). The extra register needed to hold the offset comes from the
1693 // register scavenger, and it is possible that the scavenger will need to use
1694 // an emergency spill slot. As a result, we need to make sure that a spill slot
1695 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1697 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1698 // FIXME: This does not handle the LWA case.
1702 // NOTE: We'll exclude negative FIs here, which come from argument
1703 // lowering, because there are no known test cases triggering this problem
1704 // using packed structures (or similar). We can remove this exclusion if
1705 // we find such a test case. The reason why this is so test-case driven is
1706 // because this entire 'fixup' is only to prevent crashes (from the
1707 // register scavenger) on not-really-valid inputs. For example, if we have:
1709 // %b = bitcast i1* %a to i64*
1710 // store i64* a, i64 b
1711 // then the store should really be marked as 'align 1', but is not. If it
1712 // were marked as 'align 1' then the indexed form would have been
1713 // instruction-selected initially, and the problem this 'fixup' is preventing
1714 // won't happen regardless.
1718 MachineFunction &MF = DAG.getMachineFunction();
1719 MachineFrameInfo *MFI = MF.getFrameInfo();
1721 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1725 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1726 FuncInfo->setHasNonRISpills();
1729 /// Returns true if the address N can be represented by a base register plus
1730 /// a signed 16-bit displacement [r+imm], and if it is not better
1731 /// represented as reg+reg. If Aligned is true, only accept displacements
1732 /// suitable for STD and friends, i.e. multiples of 4.
1733 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1736 bool Aligned) const {
1737 // FIXME dl should come from parent load or store, not from address
1739 // If this can be more profitably realized as r+r, fail.
1740 if (SelectAddressRegReg(N, Disp, Base, DAG))
1743 if (N.getOpcode() == ISD::ADD) {
1745 if (isIntS16Immediate(N.getOperand(1), imm) &&
1746 (!Aligned || (imm & 3) == 0)) {
1747 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1748 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1749 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1750 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1752 Base = N.getOperand(0);
1754 return true; // [r+i]
1755 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1756 // Match LOAD (ADD (X, Lo(G))).
1757 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1758 && "Cannot handle constant offsets yet!");
1759 Disp = N.getOperand(1).getOperand(0); // The global address.
1760 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1761 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1762 Disp.getOpcode() == ISD::TargetConstantPool ||
1763 Disp.getOpcode() == ISD::TargetJumpTable);
1764 Base = N.getOperand(0);
1765 return true; // [&g+r]
1767 } else if (N.getOpcode() == ISD::OR) {
1769 if (isIntS16Immediate(N.getOperand(1), imm) &&
1770 (!Aligned || (imm & 3) == 0)) {
1771 // If this is an or of disjoint bitfields, we can codegen this as an add
1772 // (for better address arithmetic) if the LHS and RHS of the OR are
1773 // provably disjoint.
1774 APInt LHSKnownZero, LHSKnownOne;
1775 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1777 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1778 // If all of the bits are known zero on the LHS or RHS, the add won't
1780 if (FrameIndexSDNode *FI =
1781 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1782 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1783 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1785 Base = N.getOperand(0);
1787 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1791 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1792 // Loading from a constant address.
1794 // If this address fits entirely in a 16-bit sext immediate field, codegen
1797 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1798 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1799 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1800 CN->getValueType(0));
1804 // Handle 32-bit sext immediates with LIS + addr mode.
1805 if ((CN->getValueType(0) == MVT::i32 ||
1806 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1807 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1808 int Addr = (int)CN->getZExtValue();
1810 // Otherwise, break this down into an LIS + disp.
1811 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1813 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1815 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1816 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1821 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
1822 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1823 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1824 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1827 return true; // [r+0]
1830 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1831 /// represented as an indexed [r+r] operation.
1832 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1834 SelectionDAG &DAG) const {
1835 // Check to see if we can easily represent this as an [r+r] address. This
1836 // will fail if it thinks that the address is more profitably represented as
1837 // reg+imm, e.g. where imm = 0.
1838 if (SelectAddressRegReg(N, Base, Index, DAG))
1841 // If the operand is an addition, always emit this as [r+r], since this is
1842 // better (for code size, and execution, as the memop does the add for free)
1843 // than emitting an explicit add.
1844 if (N.getOpcode() == ISD::ADD) {
1845 Base = N.getOperand(0);
1846 Index = N.getOperand(1);
1850 // Otherwise, do it the hard way, using R0 as the base register.
1851 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1857 /// getPreIndexedAddressParts - returns true by value, base pointer and
1858 /// offset pointer and addressing mode by reference if the node's address
1859 /// can be legally represented as pre-indexed load / store address.
1860 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1862 ISD::MemIndexedMode &AM,
1863 SelectionDAG &DAG) const {
1864 if (DisablePPCPreinc) return false;
1870 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1871 Ptr = LD->getBasePtr();
1872 VT = LD->getMemoryVT();
1873 Alignment = LD->getAlignment();
1874 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1875 Ptr = ST->getBasePtr();
1876 VT = ST->getMemoryVT();
1877 Alignment = ST->getAlignment();
1882 // PowerPC doesn't have preinc load/store instructions for vectors (except
1883 // for QPX, which does have preinc r+r forms).
1884 if (VT.isVector()) {
1885 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1887 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1893 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1895 // Common code will reject creating a pre-inc form if the base pointer
1896 // is a frame index, or if N is a store and the base pointer is either
1897 // the same as or a predecessor of the value being stored. Check for
1898 // those situations here, and try with swapped Base/Offset instead.
1901 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1904 SDValue Val = cast<StoreSDNode>(N)->getValue();
1905 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1910 std::swap(Base, Offset);
1916 // LDU/STU can only handle immediates that are a multiple of 4.
1917 if (VT != MVT::i64) {
1918 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1921 // LDU/STU need an address with at least 4-byte alignment.
1925 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1929 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1930 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1931 // sext i32 to i64 when addr mode is r+i.
1932 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1933 LD->getExtensionType() == ISD::SEXTLOAD &&
1934 isa<ConstantSDNode>(Offset))
1942 //===----------------------------------------------------------------------===//
1943 // LowerOperation implementation
1944 //===----------------------------------------------------------------------===//
1946 /// GetLabelAccessInfo - Return true if we should reference labels using a
1947 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1948 static bool GetLabelAccessInfo(const TargetMachine &TM,
1949 const PPCSubtarget &Subtarget,
1950 unsigned &HiOpFlags, unsigned &LoOpFlags,
1951 const GlobalValue *GV = nullptr) {
1952 HiOpFlags = PPCII::MO_HA;
1953 LoOpFlags = PPCII::MO_LO;
1955 // Don't use the pic base if not in PIC relocation model.
1956 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1959 HiOpFlags |= PPCII::MO_PIC_FLAG;
1960 LoOpFlags |= PPCII::MO_PIC_FLAG;
1963 // If this is a reference to a global value that requires a non-lazy-ptr, make
1964 // sure that instruction lowering adds it.
1965 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1966 HiOpFlags |= PPCII::MO_NLP_FLAG;
1967 LoOpFlags |= PPCII::MO_NLP_FLAG;
1969 if (GV->hasHiddenVisibility()) {
1970 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1971 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1978 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1979 SelectionDAG &DAG) {
1981 EVT PtrVT = HiPart.getValueType();
1982 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1984 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1985 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1987 // With PIC, the first instruction is actually "GR+hi(&G)".
1989 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1990 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1992 // Generate non-pic code that has direct accesses to the constant pool.
1993 // The address of the global is just (hi(&g)+lo(&g)).
1994 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1997 static void setUsesTOCBasePtr(MachineFunction &MF) {
1998 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1999 FuncInfo->setUsesTOCBasePtr();
2002 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2003 setUsesTOCBasePtr(DAG.getMachineFunction());
2006 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
2008 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2009 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2010 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2012 SDValue Ops[] = { GA, Reg };
2013 return DAG.getMemIntrinsicNode(
2014 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2015 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0, false, true,
2019 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2020 SelectionDAG &DAG) const {
2021 EVT PtrVT = Op.getValueType();
2022 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2023 const Constant *C = CP->getConstVal();
2025 // 64-bit SVR4 ABI code is always position-independent.
2026 // The actual address of the GlobalValue is stored in the TOC.
2027 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2028 setUsesTOCBasePtr(DAG);
2029 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2030 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2033 unsigned MOHiFlag, MOLoFlag;
2035 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2037 if (isPIC && Subtarget.isSVR4ABI()) {
2038 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2039 PPCII::MO_PIC_FLAG);
2040 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2044 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2046 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2047 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2050 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2051 EVT PtrVT = Op.getValueType();
2052 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2054 // 64-bit SVR4 ABI code is always position-independent.
2055 // The actual address of the GlobalValue is stored in the TOC.
2056 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2057 setUsesTOCBasePtr(DAG);
2058 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2059 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2062 unsigned MOHiFlag, MOLoFlag;
2064 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2066 if (isPIC && Subtarget.isSVR4ABI()) {
2067 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2068 PPCII::MO_PIC_FLAG);
2069 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2072 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2073 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2074 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2077 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2078 SelectionDAG &DAG) const {
2079 EVT PtrVT = Op.getValueType();
2080 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2081 const BlockAddress *BA = BASDN->getBlockAddress();
2083 // 64-bit SVR4 ABI code is always position-independent.
2084 // The actual BlockAddress is stored in the TOC.
2085 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2086 setUsesTOCBasePtr(DAG);
2087 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2088 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2091 unsigned MOHiFlag, MOLoFlag;
2093 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2094 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2095 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2096 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2099 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2100 SelectionDAG &DAG) const {
2102 // FIXME: TLS addresses currently use medium model code sequences,
2103 // which is the most useful form. Eventually support for small and
2104 // large models could be added if users need it, at the cost of
2105 // additional complexity.
2106 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2107 if (DAG.getTarget().Options.EmulatedTLS)
2108 return LowerToTLSEmulatedModel(GA, DAG);
2111 const GlobalValue *GV = GA->getGlobal();
2112 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2113 bool is64bit = Subtarget.isPPC64();
2114 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2115 PICLevel::Level picLevel = M->getPICLevel();
2117 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2119 if (Model == TLSModel::LocalExec) {
2120 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2121 PPCII::MO_TPREL_HA);
2122 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2123 PPCII::MO_TPREL_LO);
2124 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2125 is64bit ? MVT::i64 : MVT::i32);
2126 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2127 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2130 if (Model == TLSModel::InitialExec) {
2131 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2132 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2136 setUsesTOCBasePtr(DAG);
2137 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2138 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2139 PtrVT, GOTReg, TGA);
2141 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2142 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2143 PtrVT, TGA, GOTPtr);
2144 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2147 if (Model == TLSModel::GeneralDynamic) {
2148 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2151 setUsesTOCBasePtr(DAG);
2152 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2153 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2156 if (picLevel == PICLevel::Small)
2157 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2159 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2161 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2165 if (Model == TLSModel::LocalDynamic) {
2166 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2169 setUsesTOCBasePtr(DAG);
2170 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2171 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2174 if (picLevel == PICLevel::Small)
2175 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2177 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2179 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2180 PtrVT, GOTPtr, TGA, TGA);
2181 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2182 PtrVT, TLSAddr, TGA);
2183 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2186 llvm_unreachable("Unknown TLS model!");
2189 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2190 SelectionDAG &DAG) const {
2191 EVT PtrVT = Op.getValueType();
2192 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2194 const GlobalValue *GV = GSDN->getGlobal();
2196 // 64-bit SVR4 ABI code is always position-independent.
2197 // The actual address of the GlobalValue is stored in the TOC.
2198 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2199 setUsesTOCBasePtr(DAG);
2200 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2201 return getTOCEntry(DAG, DL, true, GA);
2204 unsigned MOHiFlag, MOLoFlag;
2206 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2208 if (isPIC && Subtarget.isSVR4ABI()) {
2209 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2211 PPCII::MO_PIC_FLAG);
2212 return getTOCEntry(DAG, DL, false, GA);
2216 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2218 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2220 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2222 // If the global reference is actually to a non-lazy-pointer, we have to do an
2223 // extra load to get the address of the global.
2224 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2225 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2226 false, false, false, 0);
2230 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2231 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2234 if (Op.getValueType() == MVT::v2i64) {
2235 // When the operands themselves are v2i64 values, we need to do something
2236 // special because VSX has no underlying comparison operations for these.
2237 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2238 // Equality can be handled by casting to the legal type for Altivec
2239 // comparisons, everything else needs to be expanded.
2240 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2241 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2242 DAG.getSetCC(dl, MVT::v4i32,
2243 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2244 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2251 // We handle most of these in the usual way.
2255 // If we're comparing for equality to zero, expose the fact that this is
2256 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2257 // fold the new nodes.
2258 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2259 if (C->isNullValue() && CC == ISD::SETEQ) {
2260 EVT VT = Op.getOperand(0).getValueType();
2261 SDValue Zext = Op.getOperand(0);
2262 if (VT.bitsLT(MVT::i32)) {
2264 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2266 unsigned Log2b = Log2_32(VT.getSizeInBits());
2267 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2268 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2269 DAG.getConstant(Log2b, dl, MVT::i32));
2270 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2272 // Leave comparisons against 0 and -1 alone for now, since they're usually
2273 // optimized. FIXME: revisit this when we can custom lower all setcc
2275 if (C->isAllOnesValue() || C->isNullValue())
2279 // If we have an integer seteq/setne, turn it into a compare against zero
2280 // by xor'ing the rhs with the lhs, which is faster than setting a
2281 // condition register, reading it back out, and masking the correct bit. The
2282 // normal approach here uses sub to do this instead of xor. Using xor exposes
2283 // the result to other bit-twiddling opportunities.
2284 EVT LHSVT = Op.getOperand(0).getValueType();
2285 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2286 EVT VT = Op.getValueType();
2287 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2289 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2294 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2295 const PPCSubtarget &Subtarget) const {
2296 SDNode *Node = Op.getNode();
2297 EVT VT = Node->getValueType(0);
2298 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2299 SDValue InChain = Node->getOperand(0);
2300 SDValue VAListPtr = Node->getOperand(1);
2301 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2304 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2307 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2308 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2309 false, false, false, 0);
2310 InChain = GprIndex.getValue(1);
2312 if (VT == MVT::i64) {
2313 // Check if GprIndex is even
2314 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2315 DAG.getConstant(1, dl, MVT::i32));
2316 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2317 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2318 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2319 DAG.getConstant(1, dl, MVT::i32));
2320 // Align GprIndex to be even if it isn't
2321 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2325 // fpr index is 1 byte after gpr
2326 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2327 DAG.getConstant(1, dl, MVT::i32));
2330 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2331 FprPtr, MachinePointerInfo(SV), MVT::i8,
2332 false, false, false, 0);
2333 InChain = FprIndex.getValue(1);
2335 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2336 DAG.getConstant(8, dl, MVT::i32));
2338 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2339 DAG.getConstant(4, dl, MVT::i32));
2342 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2343 MachinePointerInfo(), false, false,
2345 InChain = OverflowArea.getValue(1);
2347 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2348 MachinePointerInfo(), false, false,
2350 InChain = RegSaveArea.getValue(1);
2352 // select overflow_area if index > 8
2353 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2354 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2356 // adjustment constant gpr_index * 4/8
2357 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2358 VT.isInteger() ? GprIndex : FprIndex,
2359 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2362 // OurReg = RegSaveArea + RegConstant
2363 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2366 // Floating types are 32 bytes into RegSaveArea
2367 if (VT.isFloatingPoint())
2368 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2369 DAG.getConstant(32, dl, MVT::i32));
2371 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2372 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2373 VT.isInteger() ? GprIndex : FprIndex,
2374 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2377 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2378 VT.isInteger() ? VAListPtr : FprPtr,
2379 MachinePointerInfo(SV),
2380 MVT::i8, false, false, 0);
2382 // determine if we should load from reg_save_area or overflow_area
2383 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2385 // increase overflow_area by 4/8 if gpr/fpr > 8
2386 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2387 DAG.getConstant(VT.isInteger() ? 4 : 8,
2390 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2393 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2395 MachinePointerInfo(),
2396 MVT::i32, false, false, 0);
2398 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2399 false, false, false, 0);
2402 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2403 const PPCSubtarget &Subtarget) const {
2404 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2406 // We have to copy the entire va_list struct:
2407 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2408 return DAG.getMemcpy(Op.getOperand(0), Op,
2409 Op.getOperand(1), Op.getOperand(2),
2410 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2411 false, MachinePointerInfo(), MachinePointerInfo());
2414 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2415 SelectionDAG &DAG) const {
2416 return Op.getOperand(0);
2419 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2420 SelectionDAG &DAG) const {
2421 SDValue Chain = Op.getOperand(0);
2422 SDValue Trmp = Op.getOperand(1); // trampoline
2423 SDValue FPtr = Op.getOperand(2); // nested function
2424 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2427 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2428 bool isPPC64 = (PtrVT == MVT::i64);
2429 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2431 TargetLowering::ArgListTy Args;
2432 TargetLowering::ArgListEntry Entry;
2434 Entry.Ty = IntPtrTy;
2435 Entry.Node = Trmp; Args.push_back(Entry);
2437 // TrampSize == (isPPC64 ? 48 : 40);
2438 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2439 isPPC64 ? MVT::i64 : MVT::i32);
2440 Args.push_back(Entry);
2442 Entry.Node = FPtr; Args.push_back(Entry);
2443 Entry.Node = Nest; Args.push_back(Entry);
2445 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2446 TargetLowering::CallLoweringInfo CLI(DAG);
2447 CLI.setDebugLoc(dl).setChain(Chain)
2448 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2449 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2450 std::move(Args), 0);
2452 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2453 return CallResult.second;
2456 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2457 const PPCSubtarget &Subtarget) const {
2458 MachineFunction &MF = DAG.getMachineFunction();
2459 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2463 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2464 // vastart just stores the address of the VarArgsFrameIndex slot into the
2465 // memory location argument.
2466 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2467 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2468 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2469 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2470 MachinePointerInfo(SV),
2474 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2475 // We suppose the given va_list is already allocated.
2478 // char gpr; /* index into the array of 8 GPRs
2479 // * stored in the register save area
2480 // * gpr=0 corresponds to r3,
2481 // * gpr=1 to r4, etc.
2483 // char fpr; /* index into the array of 8 FPRs
2484 // * stored in the register save area
2485 // * fpr=0 corresponds to f1,
2486 // * fpr=1 to f2, etc.
2488 // char *overflow_arg_area;
2489 // /* location on stack that holds
2490 // * the next overflow argument
2492 // char *reg_save_area;
2493 // /* where r3:r10 and f1:f8 (if saved)
2498 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2499 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2501 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2503 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2505 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2508 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2509 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2511 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2512 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2514 uint64_t FPROffset = 1;
2515 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2517 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2519 // Store first byte : number of int regs
2520 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2522 MachinePointerInfo(SV),
2523 MVT::i8, false, false, 0);
2524 uint64_t nextOffset = FPROffset;
2525 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2528 // Store second byte : number of float regs
2529 SDValue secondStore =
2530 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2531 MachinePointerInfo(SV, nextOffset), MVT::i8,
2533 nextOffset += StackOffset;
2534 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2536 // Store second word : arguments given on stack
2537 SDValue thirdStore =
2538 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2539 MachinePointerInfo(SV, nextOffset),
2541 nextOffset += FrameOffset;
2542 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2544 // Store third word : arguments given in registers
2545 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2546 MachinePointerInfo(SV, nextOffset),
2551 #include "PPCGenCallingConv.inc"
2553 // Function whose sole purpose is to kill compiler warnings
2554 // stemming from unused functions included from PPCGenCallingConv.inc.
2555 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2556 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2559 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2560 CCValAssign::LocInfo &LocInfo,
2561 ISD::ArgFlagsTy &ArgFlags,
2566 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2568 CCValAssign::LocInfo &LocInfo,
2569 ISD::ArgFlagsTy &ArgFlags,
2571 static const MCPhysReg ArgRegs[] = {
2572 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2573 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2575 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2577 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2579 // Skip one register if the first unallocated register has an even register
2580 // number and there are still argument registers available which have not been
2581 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2582 // need to skip a register if RegNum is odd.
2583 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2584 State.AllocateReg(ArgRegs[RegNum]);
2587 // Always return false here, as this function only makes sure that the first
2588 // unallocated register has an odd register number and does not actually
2589 // allocate a register for the current argument.
2593 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2595 CCValAssign::LocInfo &LocInfo,
2596 ISD::ArgFlagsTy &ArgFlags,
2598 static const MCPhysReg ArgRegs[] = {
2599 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2603 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2605 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2607 // If there is only one Floating-point register left we need to put both f64
2608 // values of a split ppc_fp128 value on the stack.
2609 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2610 State.AllocateReg(ArgRegs[RegNum]);
2613 // Always return false here, as this function only makes sure that the two f64
2614 // values a ppc_fp128 value is split into are both passed in registers or both
2615 // passed on the stack and does not actually allocate a register for the
2616 // current argument.
2620 /// FPR - The set of FP registers that should be allocated for arguments,
2622 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2623 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2624 PPC::F11, PPC::F12, PPC::F13};
2626 /// QFPR - The set of QPX registers that should be allocated for arguments.
2627 static const MCPhysReg QFPR[] = {
2628 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2629 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2631 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2633 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2634 unsigned PtrByteSize) {
2635 unsigned ArgSize = ArgVT.getStoreSize();
2636 if (Flags.isByVal())
2637 ArgSize = Flags.getByValSize();
2639 // Round up to multiples of the pointer size, except for array members,
2640 // which are always packed.
2641 if (!Flags.isInConsecutiveRegs())
2642 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2647 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2649 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2650 ISD::ArgFlagsTy Flags,
2651 unsigned PtrByteSize) {
2652 unsigned Align = PtrByteSize;
2654 // Altivec parameters are padded to a 16 byte boundary.
2655 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2656 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2657 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2658 ArgVT == MVT::v1i128)
2660 // QPX vector types stored in double-precision are padded to a 32 byte
2662 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2665 // ByVal parameters are aligned as requested.
2666 if (Flags.isByVal()) {
2667 unsigned BVAlign = Flags.getByValAlign();
2668 if (BVAlign > PtrByteSize) {
2669 if (BVAlign % PtrByteSize != 0)
2671 "ByVal alignment is not a multiple of the pointer size");
2677 // Array members are always packed to their original alignment.
2678 if (Flags.isInConsecutiveRegs()) {
2679 // If the array member was split into multiple registers, the first
2680 // needs to be aligned to the size of the full type. (Except for
2681 // ppcf128, which is only aligned as its f64 components.)
2682 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2683 Align = OrigVT.getStoreSize();
2685 Align = ArgVT.getStoreSize();
2691 /// CalculateStackSlotUsed - Return whether this argument will use its
2692 /// stack slot (instead of being passed in registers). ArgOffset,
2693 /// AvailableFPRs, and AvailableVRs must hold the current argument
2694 /// position, and will be updated to account for this argument.
2695 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2696 ISD::ArgFlagsTy Flags,
2697 unsigned PtrByteSize,
2698 unsigned LinkageSize,
2699 unsigned ParamAreaSize,
2700 unsigned &ArgOffset,
2701 unsigned &AvailableFPRs,
2702 unsigned &AvailableVRs, bool HasQPX) {
2703 bool UseMemory = false;
2705 // Respect alignment of argument on the stack.
2707 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2708 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2709 // If there's no space left in the argument save area, we must
2710 // use memory (this check also catches zero-sized arguments).
2711 if (ArgOffset >= LinkageSize + ParamAreaSize)
2714 // Allocate argument on the stack.
2715 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2716 if (Flags.isInConsecutiveRegsLast())
2717 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2718 // If we overran the argument save area, we must use memory
2719 // (this check catches arguments passed partially in memory)
2720 if (ArgOffset > LinkageSize + ParamAreaSize)
2723 // However, if the argument is actually passed in an FPR or a VR,
2724 // we don't use memory after all.
2725 if (!Flags.isByVal()) {
2726 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2727 // QPX registers overlap with the scalar FP registers.
2728 (HasQPX && (ArgVT == MVT::v4f32 ||
2729 ArgVT == MVT::v4f64 ||
2730 ArgVT == MVT::v4i1)))
2731 if (AvailableFPRs > 0) {
2735 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2736 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2737 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2738 ArgVT == MVT::v1i128)
2739 if (AvailableVRs > 0) {
2748 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2749 /// ensure minimum alignment required for target.
2750 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2751 unsigned NumBytes) {
2752 unsigned TargetAlign = Lowering->getStackAlignment();
2753 unsigned AlignMask = TargetAlign - 1;
2754 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2759 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2760 CallingConv::ID CallConv, bool isVarArg,
2761 const SmallVectorImpl<ISD::InputArg>
2763 SDLoc dl, SelectionDAG &DAG,
2764 SmallVectorImpl<SDValue> &InVals)
2766 if (Subtarget.isSVR4ABI()) {
2767 if (Subtarget.isPPC64())
2768 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2771 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2774 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2780 PPCTargetLowering::LowerFormalArguments_32SVR4(
2782 CallingConv::ID CallConv, bool isVarArg,
2783 const SmallVectorImpl<ISD::InputArg>
2785 SDLoc dl, SelectionDAG &DAG,
2786 SmallVectorImpl<SDValue> &InVals) const {
2788 // 32-bit SVR4 ABI Stack Frame Layout:
2789 // +-----------------------------------+
2790 // +--> | Back chain |
2791 // | +-----------------------------------+
2792 // | | Floating-point register save area |
2793 // | +-----------------------------------+
2794 // | | General register save area |
2795 // | +-----------------------------------+
2796 // | | CR save word |
2797 // | +-----------------------------------+
2798 // | | VRSAVE save word |
2799 // | +-----------------------------------+
2800 // | | Alignment padding |
2801 // | +-----------------------------------+
2802 // | | Vector register save area |
2803 // | +-----------------------------------+
2804 // | | Local variable space |
2805 // | +-----------------------------------+
2806 // | | Parameter list area |
2807 // | +-----------------------------------+
2808 // | | LR save word |
2809 // | +-----------------------------------+
2810 // SP--> +--- | Back chain |
2811 // +-----------------------------------+
2814 // System V Application Binary Interface PowerPC Processor Supplement
2815 // AltiVec Technology Programming Interface Manual
2817 MachineFunction &MF = DAG.getMachineFunction();
2818 MachineFrameInfo *MFI = MF.getFrameInfo();
2819 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2821 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2822 // Potential tail calls could cause overwriting of argument stack slots.
2823 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2824 (CallConv == CallingConv::Fast));
2825 unsigned PtrByteSize = 4;
2827 // Assign locations to all of the incoming arguments.
2828 SmallVector<CCValAssign, 16> ArgLocs;
2829 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2832 // Reserve space for the linkage area on the stack.
2833 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2834 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2836 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2838 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2839 CCValAssign &VA = ArgLocs[i];
2841 // Arguments stored in registers.
2842 if (VA.isRegLoc()) {
2843 const TargetRegisterClass *RC;
2844 EVT ValVT = VA.getValVT();
2846 switch (ValVT.getSimpleVT().SimpleTy) {
2848 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2851 RC = &PPC::GPRCRegClass;
2854 if (Subtarget.hasP8Vector())
2855 RC = &PPC::VSSRCRegClass;
2857 RC = &PPC::F4RCRegClass;
2860 if (Subtarget.hasVSX())
2861 RC = &PPC::VSFRCRegClass;
2863 RC = &PPC::F8RCRegClass;
2868 RC = &PPC::VRRCRegClass;
2871 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2875 RC = &PPC::VSHRCRegClass;
2878 RC = &PPC::QFRCRegClass;
2881 RC = &PPC::QBRCRegClass;
2885 // Transform the arguments stored in physical registers into virtual ones.
2886 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2887 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2888 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2890 if (ValVT == MVT::i1)
2891 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2893 InVals.push_back(ArgValue);
2895 // Argument stored in memory.
2896 assert(VA.isMemLoc());
2898 unsigned ArgSize = VA.getLocVT().getStoreSize();
2899 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2902 // Create load nodes to retrieve arguments from the stack.
2903 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2904 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2905 MachinePointerInfo(),
2906 false, false, false, 0));
2910 // Assign locations to all of the incoming aggregate by value arguments.
2911 // Aggregates passed by value are stored in the local variable space of the
2912 // caller's stack frame, right above the parameter list area.
2913 SmallVector<CCValAssign, 16> ByValArgLocs;
2914 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2915 ByValArgLocs, *DAG.getContext());
2917 // Reserve stack space for the allocations in CCInfo.
2918 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2920 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2922 // Area that is at least reserved in the caller of this function.
2923 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2924 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2926 // Set the size that is at least reserved in caller of this function. Tail
2927 // call optimized function's reserved stack space needs to be aligned so that
2928 // taking the difference between two stack areas will result in an aligned
2931 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2932 FuncInfo->setMinReservedArea(MinReservedArea);
2934 SmallVector<SDValue, 8> MemOps;
2936 // If the function takes variable number of arguments, make a frame index for
2937 // the start of the first vararg value... for expansion of llvm.va_start.
2939 static const MCPhysReg GPArgRegs[] = {
2940 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2941 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2943 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2945 static const MCPhysReg FPArgRegs[] = {
2946 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2949 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2951 if (Subtarget.useSoftFloat())
2954 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2955 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2957 // Make room for NumGPArgRegs and NumFPArgRegs.
2958 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2959 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2961 FuncInfo->setVarArgsStackOffset(
2962 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2963 CCInfo.getNextStackOffset(), true));
2965 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2966 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2968 // The fixed integer arguments of a variadic function are stored to the
2969 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2970 // the result of va_next.
2971 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2972 // Get an existing live-in vreg, or add a new one.
2973 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2975 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2977 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2978 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2979 MachinePointerInfo(), false, false, 0);
2980 MemOps.push_back(Store);
2981 // Increment the address by four for the next argument to store
2982 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2983 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2986 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2988 // The double arguments are stored to the VarArgsFrameIndex
2990 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2991 // Get an existing live-in vreg, or add a new one.
2992 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2994 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2996 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2997 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2998 MachinePointerInfo(), false, false, 0);
2999 MemOps.push_back(Store);
3000 // Increment the address by eight for the next argument to store
3001 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3003 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3007 if (!MemOps.empty())
3008 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3013 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3014 // value to MVT::i64 and then truncate to the correct register size.
3016 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
3017 SelectionDAG &DAG, SDValue ArgVal,
3020 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3021 DAG.getValueType(ObjectVT));
3022 else if (Flags.isZExt())
3023 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3024 DAG.getValueType(ObjectVT));
3026 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3030 PPCTargetLowering::LowerFormalArguments_64SVR4(
3032 CallingConv::ID CallConv, bool isVarArg,
3033 const SmallVectorImpl<ISD::InputArg>
3035 SDLoc dl, SelectionDAG &DAG,
3036 SmallVectorImpl<SDValue> &InVals) const {
3037 // TODO: add description of PPC stack frame format, or at least some docs.
3039 bool isELFv2ABI = Subtarget.isELFv2ABI();
3040 bool isLittleEndian = Subtarget.isLittleEndian();
3041 MachineFunction &MF = DAG.getMachineFunction();
3042 MachineFrameInfo *MFI = MF.getFrameInfo();
3043 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3045 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3046 "fastcc not supported on varargs functions");
3048 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3049 // Potential tail calls could cause overwriting of argument stack slots.
3050 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3051 (CallConv == CallingConv::Fast));
3052 unsigned PtrByteSize = 8;
3053 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3055 static const MCPhysReg GPR[] = {
3056 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3057 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3059 static const MCPhysReg VR[] = {
3060 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3061 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3063 static const MCPhysReg VSRH[] = {
3064 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3065 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3068 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3069 const unsigned Num_FPR_Regs = 13;
3070 const unsigned Num_VR_Regs = array_lengthof(VR);
3071 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3073 // Do a first pass over the arguments to determine whether the ABI
3074 // guarantees that our caller has allocated the parameter save area
3075 // on its stack frame. In the ELFv1 ABI, this is always the case;
3076 // in the ELFv2 ABI, it is true if this is a vararg function or if
3077 // any parameter is located in a stack slot.
3079 bool HasParameterArea = !isELFv2ABI || isVarArg;
3080 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3081 unsigned NumBytes = LinkageSize;
3082 unsigned AvailableFPRs = Num_FPR_Regs;
3083 unsigned AvailableVRs = Num_VR_Regs;
3084 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3085 if (Ins[i].Flags.isNest())
3088 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3089 PtrByteSize, LinkageSize, ParamAreaSize,
3090 NumBytes, AvailableFPRs, AvailableVRs,
3091 Subtarget.hasQPX()))
3092 HasParameterArea = true;
3095 // Add DAG nodes to load the arguments or copy them out of registers. On
3096 // entry to a function on PPC, the arguments start after the linkage area,
3097 // although the first ones are often in registers.
3099 unsigned ArgOffset = LinkageSize;
3100 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3101 unsigned &QFPR_idx = FPR_idx;
3102 SmallVector<SDValue, 8> MemOps;
3103 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3104 unsigned CurArgIdx = 0;
3105 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3107 bool needsLoad = false;
3108 EVT ObjectVT = Ins[ArgNo].VT;
3109 EVT OrigVT = Ins[ArgNo].ArgVT;
3110 unsigned ObjSize = ObjectVT.getStoreSize();
3111 unsigned ArgSize = ObjSize;
3112 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3113 if (Ins[ArgNo].isOrigArg()) {
3114 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3115 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3117 // We re-align the argument offset for each argument, except when using the
3118 // fast calling convention, when we need to make sure we do that only when
3119 // we'll actually use a stack slot.
3120 unsigned CurArgOffset, Align;
3121 auto ComputeArgOffset = [&]() {
3122 /* Respect alignment of argument on the stack. */
3123 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3124 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3125 CurArgOffset = ArgOffset;
3128 if (CallConv != CallingConv::Fast) {
3131 /* Compute GPR index associated with argument offset. */
3132 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3133 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3136 // FIXME the codegen can be much improved in some cases.
3137 // We do not have to keep everything in memory.
3138 if (Flags.isByVal()) {
3139 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3141 if (CallConv == CallingConv::Fast)
3144 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3145 ObjSize = Flags.getByValSize();
3146 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3147 // Empty aggregate parameters do not take up registers. Examples:
3151 // etc. However, we have to provide a place-holder in InVals, so
3152 // pretend we have an 8-byte item at the current address for that
3155 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3156 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3157 InVals.push_back(FIN);
3161 // Create a stack object covering all stack doublewords occupied
3162 // by the argument. If the argument is (fully or partially) on
3163 // the stack, or if the argument is fully in registers but the
3164 // caller has allocated the parameter save anyway, we can refer
3165 // directly to the caller's stack frame. Otherwise, create a
3166 // local copy in our own frame.
3168 if (HasParameterArea ||
3169 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3170 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3172 FI = MFI->CreateStackObject(ArgSize, Align, false);
3173 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3175 // Handle aggregates smaller than 8 bytes.
3176 if (ObjSize < PtrByteSize) {
3177 // The value of the object is its address, which differs from the
3178 // address of the enclosing doubleword on big-endian systems.
3180 if (!isLittleEndian) {
3181 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3182 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3184 InVals.push_back(Arg);
3186 if (GPR_idx != Num_GPR_Regs) {
3187 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3188 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3191 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3192 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3193 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3194 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3195 MachinePointerInfo(&*FuncArg), ObjType,
3198 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3199 // store the whole register as-is to the parameter save area
3202 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3203 MachinePointerInfo(&*FuncArg), false, false, 0);
3206 MemOps.push_back(Store);
3208 // Whether we copied from a register or not, advance the offset
3209 // into the parameter save area by a full doubleword.
3210 ArgOffset += PtrByteSize;
3214 // The value of the object is its address, which is the address of
3215 // its first stack doubleword.
3216 InVals.push_back(FIN);
3218 // Store whatever pieces of the object are in registers to memory.
3219 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3220 if (GPR_idx == Num_GPR_Regs)
3223 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3224 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3227 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3228 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3231 DAG.getStore(Val.getValue(1), dl, Val, Addr,
3232 MachinePointerInfo(&*FuncArg, j), false, false, 0);
3233 MemOps.push_back(Store);
3236 ArgOffset += ArgSize;
3240 switch (ObjectVT.getSimpleVT().SimpleTy) {
3241 default: llvm_unreachable("Unhandled argument type!");
3245 if (Flags.isNest()) {
3246 // The 'nest' parameter, if any, is passed in R11.
3247 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3248 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3250 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3251 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3256 // These can be scalar arguments or elements of an integer array type
3257 // passed directly. Clang may use those instead of "byval" aggregate
3258 // types to avoid forcing arguments to memory unnecessarily.
3259 if (GPR_idx != Num_GPR_Regs) {
3260 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3261 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3263 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3264 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3265 // value to MVT::i64 and then truncate to the correct register size.
3266 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3268 if (CallConv == CallingConv::Fast)
3272 ArgSize = PtrByteSize;
3274 if (CallConv != CallingConv::Fast || needsLoad)
3280 // These can be scalar arguments or elements of a float array type
3281 // passed directly. The latter are used to implement ELFv2 homogenous
3282 // float aggregates.
3283 if (FPR_idx != Num_FPR_Regs) {
3286 if (ObjectVT == MVT::f32)
3287 VReg = MF.addLiveIn(FPR[FPR_idx],
3288 Subtarget.hasP8Vector()
3289 ? &PPC::VSSRCRegClass
3290 : &PPC::F4RCRegClass);
3292 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3293 ? &PPC::VSFRCRegClass
3294 : &PPC::F8RCRegClass);
3296 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3298 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3299 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3300 // once we support fp <-> gpr moves.
3302 // This can only ever happen in the presence of f32 array types,
3303 // since otherwise we never run out of FPRs before running out
3305 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3306 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3308 if (ObjectVT == MVT::f32) {
3309 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3310 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3311 DAG.getConstant(32, dl, MVT::i32));
3312 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3315 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3317 if (CallConv == CallingConv::Fast)
3323 // When passing an array of floats, the array occupies consecutive
3324 // space in the argument area; only round up to the next doubleword
3325 // at the end of the array. Otherwise, each float takes 8 bytes.
3326 if (CallConv != CallingConv::Fast || needsLoad) {
3327 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3328 ArgOffset += ArgSize;
3329 if (Flags.isInConsecutiveRegsLast())
3330 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3340 if (!Subtarget.hasQPX()) {
3341 // These can be scalar arguments or elements of a vector array type
3342 // passed directly. The latter are used to implement ELFv2 homogenous
3343 // vector aggregates.
3344 if (VR_idx != Num_VR_Regs) {
3345 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3346 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3347 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3348 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3351 if (CallConv == CallingConv::Fast)
3356 if (CallConv != CallingConv::Fast || needsLoad)
3361 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3362 "Invalid QPX parameter type");
3367 // QPX vectors are treated like their scalar floating-point subregisters
3368 // (except that they're larger).
3369 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3370 if (QFPR_idx != Num_QFPR_Regs) {
3371 const TargetRegisterClass *RC;
3372 switch (ObjectVT.getSimpleVT().SimpleTy) {
3373 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3374 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3375 default: RC = &PPC::QBRCRegClass; break;
3378 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3379 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3382 if (CallConv == CallingConv::Fast)
3386 if (CallConv != CallingConv::Fast || needsLoad)
3391 // We need to load the argument to a virtual register if we determined
3392 // above that we ran out of physical registers of the appropriate type.
3394 if (ObjSize < ArgSize && !isLittleEndian)
3395 CurArgOffset += ArgSize - ObjSize;
3396 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3397 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3398 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3399 false, false, false, 0);
3402 InVals.push_back(ArgVal);
3405 // Area that is at least reserved in the caller of this function.
3406 unsigned MinReservedArea;
3407 if (HasParameterArea)
3408 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3410 MinReservedArea = LinkageSize;
3412 // Set the size that is at least reserved in caller of this function. Tail
3413 // call optimized functions' reserved stack space needs to be aligned so that
3414 // taking the difference between two stack areas will result in an aligned
3417 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3418 FuncInfo->setMinReservedArea(MinReservedArea);
3420 // If the function takes variable number of arguments, make a frame index for
3421 // the start of the first vararg value... for expansion of llvm.va_start.
3423 int Depth = ArgOffset;
3425 FuncInfo->setVarArgsFrameIndex(
3426 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3427 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3429 // If this function is vararg, store any remaining integer argument regs
3430 // to their spots on the stack so that they may be loaded by deferencing the
3431 // result of va_next.
3432 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3433 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3434 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3435 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3436 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3437 MachinePointerInfo(), false, false, 0);
3438 MemOps.push_back(Store);
3439 // Increment the address by four for the next argument to store
3440 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3441 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3445 if (!MemOps.empty())
3446 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3452 PPCTargetLowering::LowerFormalArguments_Darwin(
3454 CallingConv::ID CallConv, bool isVarArg,
3455 const SmallVectorImpl<ISD::InputArg>
3457 SDLoc dl, SelectionDAG &DAG,
3458 SmallVectorImpl<SDValue> &InVals) const {
3459 // TODO: add description of PPC stack frame format, or at least some docs.
3461 MachineFunction &MF = DAG.getMachineFunction();
3462 MachineFrameInfo *MFI = MF.getFrameInfo();
3463 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3465 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3466 bool isPPC64 = PtrVT == MVT::i64;
3467 // Potential tail calls could cause overwriting of argument stack slots.
3468 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3469 (CallConv == CallingConv::Fast));
3470 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3471 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3472 unsigned ArgOffset = LinkageSize;
3473 // Area that is at least reserved in caller of this function.
3474 unsigned MinReservedArea = ArgOffset;
3476 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3477 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3478 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3480 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3481 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3482 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3484 static const MCPhysReg VR[] = {
3485 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3486 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3489 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3490 const unsigned Num_FPR_Regs = 13;
3491 const unsigned Num_VR_Regs = array_lengthof( VR);
3493 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3495 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3497 // In 32-bit non-varargs functions, the stack space for vectors is after the
3498 // stack space for non-vectors. We do not use this space unless we have
3499 // too many vectors to fit in registers, something that only occurs in
3500 // constructed examples:), but we have to walk the arglist to figure
3501 // that out...for the pathological case, compute VecArgOffset as the
3502 // start of the vector parameter area. Computing VecArgOffset is the
3503 // entire point of the following loop.
3504 unsigned VecArgOffset = ArgOffset;
3505 if (!isVarArg && !isPPC64) {
3506 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3508 EVT ObjectVT = Ins[ArgNo].VT;
3509 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3511 if (Flags.isByVal()) {
3512 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3513 unsigned ObjSize = Flags.getByValSize();
3515 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3516 VecArgOffset += ArgSize;
3520 switch(ObjectVT.getSimpleVT().SimpleTy) {
3521 default: llvm_unreachable("Unhandled argument type!");
3527 case MVT::i64: // PPC64
3529 // FIXME: We are guaranteed to be !isPPC64 at this point.
3530 // Does MVT::i64 apply?
3537 // Nothing to do, we're only looking at Nonvector args here.
3542 // We've found where the vector parameter area in memory is. Skip the
3543 // first 12 parameters; these don't use that memory.
3544 VecArgOffset = ((VecArgOffset+15)/16)*16;
3545 VecArgOffset += 12*16;
3547 // Add DAG nodes to load the arguments or copy them out of registers. On
3548 // entry to a function on PPC, the arguments start after the linkage area,
3549 // although the first ones are often in registers.
3551 SmallVector<SDValue, 8> MemOps;
3552 unsigned nAltivecParamsAtEnd = 0;
3553 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3554 unsigned CurArgIdx = 0;
3555 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3557 bool needsLoad = false;
3558 EVT ObjectVT = Ins[ArgNo].VT;
3559 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3560 unsigned ArgSize = ObjSize;
3561 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3562 if (Ins[ArgNo].isOrigArg()) {
3563 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3564 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3566 unsigned CurArgOffset = ArgOffset;
3568 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3569 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3570 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3571 if (isVarArg || isPPC64) {
3572 MinReservedArea = ((MinReservedArea+15)/16)*16;
3573 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3576 } else nAltivecParamsAtEnd++;
3578 // Calculate min reserved area.
3579 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3583 // FIXME the codegen can be much improved in some cases.
3584 // We do not have to keep everything in memory.
3585 if (Flags.isByVal()) {
3586 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3588 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3589 ObjSize = Flags.getByValSize();
3590 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3591 // Objects of size 1 and 2 are right justified, everything else is
3592 // left justified. This means the memory address is adjusted forwards.
3593 if (ObjSize==1 || ObjSize==2) {
3594 CurArgOffset = CurArgOffset + (4 - ObjSize);
3596 // The value of the object is its address.
3597 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3598 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3599 InVals.push_back(FIN);
3600 if (ObjSize==1 || ObjSize==2) {
3601 if (GPR_idx != Num_GPR_Regs) {
3604 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3606 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3607 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3608 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3609 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3610 MachinePointerInfo(&*FuncArg),
3611 ObjType, false, false, 0);
3612 MemOps.push_back(Store);
3616 ArgOffset += PtrByteSize;
3620 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3621 // Store whatever pieces of the object are in registers
3622 // to memory. ArgOffset will be the address of the beginning
3624 if (GPR_idx != Num_GPR_Regs) {
3627 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3629 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3630 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3631 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3632 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3634 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3635 MachinePointerInfo(&*FuncArg, j), false, false, 0);
3636 MemOps.push_back(Store);
3638 ArgOffset += PtrByteSize;
3640 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3647 switch (ObjectVT.getSimpleVT().SimpleTy) {
3648 default: llvm_unreachable("Unhandled argument type!");
3652 if (GPR_idx != Num_GPR_Regs) {
3653 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3654 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3656 if (ObjectVT == MVT::i1)
3657 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3662 ArgSize = PtrByteSize;
3664 // All int arguments reserve stack space in the Darwin ABI.
3665 ArgOffset += PtrByteSize;
3669 case MVT::i64: // PPC64
3670 if (GPR_idx != Num_GPR_Regs) {
3671 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3672 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3674 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3675 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3676 // value to MVT::i64 and then truncate to the correct register size.
3677 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3682 ArgSize = PtrByteSize;
3684 // All int arguments reserve stack space in the Darwin ABI.
3690 // Every 4 bytes of argument space consumes one of the GPRs available for
3691 // argument passing.
3692 if (GPR_idx != Num_GPR_Regs) {
3694 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3697 if (FPR_idx != Num_FPR_Regs) {
3700 if (ObjectVT == MVT::f32)
3701 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3703 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3705 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3711 // All FP arguments reserve stack space in the Darwin ABI.
3712 ArgOffset += isPPC64 ? 8 : ObjSize;
3718 // Note that vector arguments in registers don't reserve stack space,
3719 // except in varargs functions.
3720 if (VR_idx != Num_VR_Regs) {
3721 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3722 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3724 while ((ArgOffset % 16) != 0) {
3725 ArgOffset += PtrByteSize;
3726 if (GPR_idx != Num_GPR_Regs)
3730 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3734 if (!isVarArg && !isPPC64) {
3735 // Vectors go after all the nonvectors.
3736 CurArgOffset = VecArgOffset;
3739 // Vectors are aligned.
3740 ArgOffset = ((ArgOffset+15)/16)*16;
3741 CurArgOffset = ArgOffset;
3749 // We need to load the argument to a virtual register if we determined above
3750 // that we ran out of physical registers of the appropriate type.
3752 int FI = MFI->CreateFixedObject(ObjSize,
3753 CurArgOffset + (ArgSize - ObjSize),
3755 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3756 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3757 false, false, false, 0);
3760 InVals.push_back(ArgVal);
3763 // Allow for Altivec parameters at the end, if needed.
3764 if (nAltivecParamsAtEnd) {
3765 MinReservedArea = ((MinReservedArea+15)/16)*16;
3766 MinReservedArea += 16*nAltivecParamsAtEnd;
3769 // Area that is at least reserved in the caller of this function.
3770 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3772 // Set the size that is at least reserved in caller of this function. Tail
3773 // call optimized functions' reserved stack space needs to be aligned so that
3774 // taking the difference between two stack areas will result in an aligned
3777 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3778 FuncInfo->setMinReservedArea(MinReservedArea);
3780 // If the function takes variable number of arguments, make a frame index for
3781 // the start of the first vararg value... for expansion of llvm.va_start.
3783 int Depth = ArgOffset;
3785 FuncInfo->setVarArgsFrameIndex(
3786 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3788 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3790 // If this function is vararg, store any remaining integer argument regs
3791 // to their spots on the stack so that they may be loaded by deferencing the
3792 // result of va_next.
3793 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3797 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3799 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3801 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3802 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3803 MachinePointerInfo(), false, false, 0);
3804 MemOps.push_back(Store);
3805 // Increment the address by four for the next argument to store
3806 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3807 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3811 if (!MemOps.empty())
3812 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3817 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3818 /// adjusted to accommodate the arguments for the tailcall.
3819 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3820 unsigned ParamSize) {
3822 if (!isTailCall) return 0;
3824 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3825 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3826 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3827 // Remember only if the new adjustement is bigger.
3828 if (SPDiff < FI->getTailCallSPDelta())
3829 FI->setTailCallSPDelta(SPDiff);
3834 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3835 /// for tail call optimization. Targets which want to do tail call
3836 /// optimization should implement this function.
3838 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3839 CallingConv::ID CalleeCC,
3841 const SmallVectorImpl<ISD::InputArg> &Ins,
3842 SelectionDAG& DAG) const {
3843 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3846 // Variable argument functions are not supported.
3850 MachineFunction &MF = DAG.getMachineFunction();
3851 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3852 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3853 // Functions containing by val parameters are not supported.
3854 for (unsigned i = 0; i != Ins.size(); i++) {
3855 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3856 if (Flags.isByVal()) return false;
3859 // Non-PIC/GOT tail calls are supported.
3860 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3863 // At the moment we can only do local tail calls (in same module, hidden
3864 // or protected) if we are generating PIC.
3865 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3866 return G->getGlobal()->hasHiddenVisibility()
3867 || G->getGlobal()->hasProtectedVisibility();
3873 /// isCallCompatibleAddress - Return the immediate to use if the specified
3874 /// 32-bit value is representable in the immediate field of a BxA instruction.
3875 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3876 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3877 if (!C) return nullptr;
3879 int Addr = C->getZExtValue();
3880 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3881 SignExtend32<26>(Addr) != Addr)
3882 return nullptr; // Top 6 bits have to be sext of immediate.
3884 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3885 DAG.getTargetLoweringInfo().getPointerTy(
3886 DAG.getDataLayout())).getNode();
3891 struct TailCallArgumentInfo {
3896 TailCallArgumentInfo() : FrameIdx(0) {}
3900 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3902 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3904 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3905 SmallVectorImpl<SDValue> &MemOpChains,
3907 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3908 SDValue Arg = TailCallArgs[i].Arg;
3909 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3910 int FI = TailCallArgs[i].FrameIdx;
3911 // Store relative to framepointer.
3912 MemOpChains.push_back(DAG.getStore(
3913 Chain, dl, Arg, FIN,
3914 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
3919 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3920 /// the appropriate stack slot for the tail call optimized function call.
3921 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3922 MachineFunction &MF,
3931 // Calculate the new stack slot for the return address.
3932 int SlotSize = isPPC64 ? 8 : 4;
3933 const PPCFrameLowering *FL =
3934 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3935 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3936 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3937 NewRetAddrLoc, true);
3938 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3939 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3940 Chain = DAG.getStore(
3941 Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3942 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewRetAddr),
3945 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3946 // slot as the FP is never overwritten.
3948 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3949 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3951 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3952 Chain = DAG.getStore(
3953 Chain, dl, OldFP, NewFramePtrIdx,
3954 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewFPIdx),
3961 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3962 /// the position of the argument.
3964 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3965 SDValue Arg, int SPDiff, unsigned ArgOffset,
3966 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3967 int Offset = ArgOffset + SPDiff;
3968 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3969 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3970 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3971 SDValue FIN = DAG.getFrameIndex(FI, VT);
3972 TailCallArgumentInfo Info;
3974 Info.FrameIdxOp = FIN;
3976 TailCallArguments.push_back(Info);
3979 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3980 /// stack slot. Returns the chain as result and the loaded frame pointers in
3981 /// LROpOut/FPOpout. Used when tail calling.
3982 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3990 // Load the LR and FP stack slot for later adjusting.
3991 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3992 LROpOut = getReturnAddrFrameIndex(DAG);
3993 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3994 false, false, false, 0);
3995 Chain = SDValue(LROpOut.getNode(), 1);
3997 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3998 // slot as the FP is never overwritten.
4000 FPOpOut = getFramePointerFrameIndex(DAG);
4001 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
4002 false, false, false, 0);
4003 Chain = SDValue(FPOpOut.getNode(), 1);
4009 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4010 /// by "Src" to address "Dst" of size "Size". Alignment information is
4011 /// specified by the specific parameter attribute. The copy will be passed as
4012 /// a byval function parameter.
4013 /// Sometimes what we are copying is the end of a larger object, the part that
4014 /// does not fit in registers.
4016 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
4017 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
4019 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4020 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4021 false, false, false, MachinePointerInfo(),
4022 MachinePointerInfo());
4025 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4028 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
4029 SDValue Arg, SDValue PtrOff, int SPDiff,
4030 unsigned ArgOffset, bool isPPC64, bool isTailCall,
4031 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4032 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
4034 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4039 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4041 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4042 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4043 DAG.getConstant(ArgOffset, dl, PtrVT));
4045 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4046 MachinePointerInfo(), false, false, 0));
4047 // Calculate and remember argument location.
4048 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4053 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4054 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4055 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4056 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4057 MachineFunction &MF = DAG.getMachineFunction();
4059 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4060 // might overwrite each other in case of tail call optimization.
4061 SmallVector<SDValue, 8> MemOpChains2;
4062 // Do not flag preceding copytoreg stuff together with the following stuff.
4064 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4066 if (!MemOpChains2.empty())
4067 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4069 // Store the return address to the appropriate stack slot.
4070 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4071 isPPC64, isDarwinABI, dl);
4073 // Emit callseq_end just before tailcall node.
4074 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4075 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4076 InFlag = Chain.getValue(1);
4079 // Is this global address that of a function that can be called by name? (as
4080 // opposed to something that must hold a descriptor for an indirect call).
4081 static bool isFunctionGlobalAddress(SDValue Callee) {
4082 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4083 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4084 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4087 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4094 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4095 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4096 bool isTailCall, bool IsPatchPoint, bool hasNest,
4097 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4098 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4099 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4101 bool isPPC64 = Subtarget.isPPC64();
4102 bool isSVR4ABI = Subtarget.isSVR4ABI();
4103 bool isELFv2ABI = Subtarget.isELFv2ABI();
4105 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4106 NodeTys.push_back(MVT::Other); // Returns a chain
4107 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4109 unsigned CallOpc = PPCISD::CALL;
4111 bool needIndirectCall = true;
4112 if (!isSVR4ABI || !isPPC64)
4113 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4114 // If this is an absolute destination address, use the munged value.
4115 Callee = SDValue(Dest, 0);
4116 needIndirectCall = false;
4119 if (isFunctionGlobalAddress(Callee)) {
4120 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4121 // A call to a TLS address is actually an indirect call to a
4122 // thread-specific pointer.
4123 unsigned OpFlags = 0;
4124 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4125 (Subtarget.getTargetTriple().isMacOSX() &&
4126 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4127 !G->getGlobal()->isStrongDefinitionForLinker()) ||
4128 (Subtarget.isTargetELF() && !isPPC64 &&
4129 !G->getGlobal()->hasLocalLinkage() &&
4130 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4131 // PC-relative references to external symbols should go through $stub,
4132 // unless we're building with the leopard linker or later, which
4133 // automatically synthesizes these stubs.
4134 OpFlags = PPCII::MO_PLT_OR_STUB;
4137 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4138 // every direct call is) turn it into a TargetGlobalAddress /
4139 // TargetExternalSymbol node so that legalize doesn't hack it.
4140 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4141 Callee.getValueType(), 0, OpFlags);
4142 needIndirectCall = false;
4145 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4146 unsigned char OpFlags = 0;
4148 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4149 (Subtarget.getTargetTriple().isMacOSX() &&
4150 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4151 (Subtarget.isTargetELF() && !isPPC64 &&
4152 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4153 // PC-relative references to external symbols should go through $stub,
4154 // unless we're building with the leopard linker or later, which
4155 // automatically synthesizes these stubs.
4156 OpFlags = PPCII::MO_PLT_OR_STUB;
4159 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4161 needIndirectCall = false;
4165 // We'll form an invalid direct call when lowering a patchpoint; the full
4166 // sequence for an indirect call is complicated, and many of the
4167 // instructions introduced might have side effects (and, thus, can't be
4168 // removed later). The call itself will be removed as soon as the
4169 // argument/return lowering is complete, so the fact that it has the wrong
4170 // kind of operands should not really matter.
4171 needIndirectCall = false;
4174 if (needIndirectCall) {
4175 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4176 // to do the call, we can't use PPCISD::CALL.
4177 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4179 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4180 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4181 // entry point, but to the function descriptor (the function entry point
4182 // address is part of the function descriptor though).
4183 // The function descriptor is a three doubleword structure with the
4184 // following fields: function entry point, TOC base address and
4185 // environment pointer.
4186 // Thus for a call through a function pointer, the following actions need
4188 // 1. Save the TOC of the caller in the TOC save area of its stack
4189 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4190 // 2. Load the address of the function entry point from the function
4192 // 3. Load the TOC of the callee from the function descriptor into r2.
4193 // 4. Load the environment pointer from the function descriptor into
4195 // 5. Branch to the function entry point address.
4196 // 6. On return of the callee, the TOC of the caller needs to be
4197 // restored (this is done in FinishCall()).
4199 // The loads are scheduled at the beginning of the call sequence, and the
4200 // register copies are flagged together to ensure that no other
4201 // operations can be scheduled in between. E.g. without flagging the
4202 // copies together, a TOC access in the caller could be scheduled between
4203 // the assignment of the callee TOC and the branch to the callee, which
4204 // results in the TOC access going through the TOC of the callee instead
4205 // of going through the TOC of the caller, which leads to incorrect code.
4207 // Load the address of the function entry point from the function
4209 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4210 if (LDChain.getValueType() == MVT::Glue)
4211 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4213 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4215 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4216 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4217 false, false, LoadsInv, 8);
4219 // Load environment pointer into r11.
4220 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4221 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4222 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4223 MPI.getWithOffset(16), false, false,
4226 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4227 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4228 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4229 MPI.getWithOffset(8), false, false,
4232 setUsesTOCBasePtr(DAG);
4233 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4235 Chain = TOCVal.getValue(0);
4236 InFlag = TOCVal.getValue(1);
4238 // If the function call has an explicit 'nest' parameter, it takes the
4239 // place of the environment pointer.
4241 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4244 Chain = EnvVal.getValue(0);
4245 InFlag = EnvVal.getValue(1);
4248 MTCTROps[0] = Chain;
4249 MTCTROps[1] = LoadFuncPtr;
4250 MTCTROps[2] = InFlag;
4253 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4254 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4255 InFlag = Chain.getValue(1);
4258 NodeTys.push_back(MVT::Other);
4259 NodeTys.push_back(MVT::Glue);
4260 Ops.push_back(Chain);
4261 CallOpc = PPCISD::BCTRL;
4262 Callee.setNode(nullptr);
4263 // Add use of X11 (holding environment pointer)
4264 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4265 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4266 // Add CTR register as callee so a bctr can be emitted later.
4268 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4271 // If this is a direct call, pass the chain and the callee.
4272 if (Callee.getNode()) {
4273 Ops.push_back(Chain);
4274 Ops.push_back(Callee);
4276 // If this is a tail call add stack pointer delta.
4278 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4280 // Add argument registers to the end of the list so that they are known live
4282 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4283 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4284 RegsToPass[i].second.getValueType()));
4286 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4288 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4289 setUsesTOCBasePtr(DAG);
4290 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4297 bool isLocalCall(const SDValue &Callee)
4299 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4300 return G->getGlobal()->isStrongDefinitionForLinker();
4305 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4306 CallingConv::ID CallConv, bool isVarArg,
4307 const SmallVectorImpl<ISD::InputArg> &Ins,
4308 SDLoc dl, SelectionDAG &DAG,
4309 SmallVectorImpl<SDValue> &InVals) const {
4311 SmallVector<CCValAssign, 16> RVLocs;
4312 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4314 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4316 // Copy all of the result registers out of their specified physreg.
4317 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4318 CCValAssign &VA = RVLocs[i];
4319 assert(VA.isRegLoc() && "Can only return in registers!");
4321 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4322 VA.getLocReg(), VA.getLocVT(), InFlag);
4323 Chain = Val.getValue(1);
4324 InFlag = Val.getValue(2);
4326 switch (VA.getLocInfo()) {
4327 default: llvm_unreachable("Unknown loc info!");
4328 case CCValAssign::Full: break;
4329 case CCValAssign::AExt:
4330 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4332 case CCValAssign::ZExt:
4333 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4334 DAG.getValueType(VA.getValVT()));
4335 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4337 case CCValAssign::SExt:
4338 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4339 DAG.getValueType(VA.getValVT()));
4340 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4344 InVals.push_back(Val);
4351 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4352 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4353 bool hasNest, SelectionDAG &DAG,
4354 SmallVector<std::pair<unsigned, SDValue>, 8>
4356 SDValue InFlag, SDValue Chain,
4357 SDValue CallSeqStart, SDValue &Callee,
4358 int SPDiff, unsigned NumBytes,
4359 const SmallVectorImpl<ISD::InputArg> &Ins,
4360 SmallVectorImpl<SDValue> &InVals,
4361 ImmutableCallSite *CS) const {
4363 std::vector<EVT> NodeTys;
4364 SmallVector<SDValue, 8> Ops;
4365 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4366 SPDiff, isTailCall, IsPatchPoint, hasNest,
4367 RegsToPass, Ops, NodeTys, CS, Subtarget);
4369 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4370 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4371 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4373 // When performing tail call optimization the callee pops its arguments off
4374 // the stack. Account for this here so these bytes can be pushed back on in
4375 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4376 int BytesCalleePops =
4377 (CallConv == CallingConv::Fast &&
4378 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4380 // Add a register mask operand representing the call-preserved registers.
4381 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4382 const uint32_t *Mask =
4383 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4384 assert(Mask && "Missing call preserved mask for calling convention");
4385 Ops.push_back(DAG.getRegisterMask(Mask));
4387 if (InFlag.getNode())
4388 Ops.push_back(InFlag);
4392 assert(((Callee.getOpcode() == ISD::Register &&
4393 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4394 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4395 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4396 isa<ConstantSDNode>(Callee)) &&
4397 "Expecting an global address, external symbol, absolute value or register");
4399 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4400 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4403 // Add a NOP immediately after the branch instruction when using the 64-bit
4404 // SVR4 ABI. At link time, if caller and callee are in a different module and
4405 // thus have a different TOC, the call will be replaced with a call to a stub
4406 // function which saves the current TOC, loads the TOC of the callee and
4407 // branches to the callee. The NOP will be replaced with a load instruction
4408 // which restores the TOC of the caller from the TOC save slot of the current
4409 // stack frame. If caller and callee belong to the same module (and have the
4410 // same TOC), the NOP will remain unchanged.
4412 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4414 if (CallOpc == PPCISD::BCTRL) {
4415 // This is a call through a function pointer.
4416 // Restore the caller TOC from the save area into R2.
4417 // See PrepareCall() for more information about calls through function
4418 // pointers in the 64-bit SVR4 ABI.
4419 // We are using a target-specific load with r2 hard coded, because the
4420 // result of a target-independent load would never go directly into r2,
4421 // since r2 is a reserved register (which prevents the register allocator
4422 // from allocating it), resulting in an additional register being
4423 // allocated and an unnecessary move instruction being generated.
4424 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4426 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4427 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4428 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4429 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4430 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4432 // The address needs to go after the chain input but before the flag (or
4433 // any other variadic arguments).
4434 Ops.insert(std::next(Ops.begin()), AddTOC);
4435 } else if ((CallOpc == PPCISD::CALL) &&
4436 (!isLocalCall(Callee) ||
4437 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4438 // Otherwise insert NOP for non-local calls.
4439 CallOpc = PPCISD::CALL_NOP;
4442 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4443 InFlag = Chain.getValue(1);
4445 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4446 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4449 InFlag = Chain.getValue(1);
4451 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4452 Ins, dl, DAG, InVals);
4456 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4457 SmallVectorImpl<SDValue> &InVals) const {
4458 SelectionDAG &DAG = CLI.DAG;
4460 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4461 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4462 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4463 SDValue Chain = CLI.Chain;
4464 SDValue Callee = CLI.Callee;
4465 bool &isTailCall = CLI.IsTailCall;
4466 CallingConv::ID CallConv = CLI.CallConv;
4467 bool isVarArg = CLI.IsVarArg;
4468 bool IsPatchPoint = CLI.IsPatchPoint;
4469 ImmutableCallSite *CS = CLI.CS;
4472 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4475 if (!isTailCall && CS && CS->isMustTailCall())
4476 report_fatal_error("failed to perform tail call elimination on a call "
4477 "site marked musttail");
4479 if (Subtarget.isSVR4ABI()) {
4480 if (Subtarget.isPPC64())
4481 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4482 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4483 dl, DAG, InVals, CS);
4485 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4486 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4487 dl, DAG, InVals, CS);
4490 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4491 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4492 dl, DAG, InVals, CS);
4496 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4497 CallingConv::ID CallConv, bool isVarArg,
4498 bool isTailCall, bool IsPatchPoint,
4499 const SmallVectorImpl<ISD::OutputArg> &Outs,
4500 const SmallVectorImpl<SDValue> &OutVals,
4501 const SmallVectorImpl<ISD::InputArg> &Ins,
4502 SDLoc dl, SelectionDAG &DAG,
4503 SmallVectorImpl<SDValue> &InVals,
4504 ImmutableCallSite *CS) const {
4505 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4506 // of the 32-bit SVR4 ABI stack frame layout.
4508 assert((CallConv == CallingConv::C ||
4509 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4511 unsigned PtrByteSize = 4;
4513 MachineFunction &MF = DAG.getMachineFunction();
4515 // Mark this function as potentially containing a function that contains a
4516 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4517 // and restoring the callers stack pointer in this functions epilog. This is
4518 // done because by tail calling the called function might overwrite the value
4519 // in this function's (MF) stack pointer stack slot 0(SP).
4520 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4521 CallConv == CallingConv::Fast)
4522 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4524 // Count how many bytes are to be pushed on the stack, including the linkage
4525 // area, parameter list area and the part of the local variable space which
4526 // contains copies of aggregates which are passed by value.
4528 // Assign locations to all of the outgoing arguments.
4529 SmallVector<CCValAssign, 16> ArgLocs;
4530 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4533 // Reserve space for the linkage area on the stack.
4534 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4538 // Handle fixed and variable vector arguments differently.
4539 // Fixed vector arguments go into registers as long as registers are
4540 // available. Variable vector arguments always go into memory.
4541 unsigned NumArgs = Outs.size();
4543 for (unsigned i = 0; i != NumArgs; ++i) {
4544 MVT ArgVT = Outs[i].VT;
4545 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4548 if (Outs[i].IsFixed) {
4549 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4552 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4558 errs() << "Call operand #" << i << " has unhandled type "
4559 << EVT(ArgVT).getEVTString() << "\n";
4561 llvm_unreachable(nullptr);
4565 // All arguments are treated the same.
4566 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4569 // Assign locations to all of the outgoing aggregate by value arguments.
4570 SmallVector<CCValAssign, 16> ByValArgLocs;
4571 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4572 ByValArgLocs, *DAG.getContext());
4574 // Reserve stack space for the allocations in CCInfo.
4575 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4577 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4579 // Size of the linkage area, parameter list area and the part of the local
4580 // space variable where copies of aggregates which are passed by value are
4582 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4584 // Calculate by how many bytes the stack has to be adjusted in case of tail
4585 // call optimization.
4586 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4588 // Adjust the stack pointer for the new arguments...
4589 // These operations are automatically eliminated by the prolog/epilog pass
4590 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4592 SDValue CallSeqStart = Chain;
4594 // Load the return address and frame pointer so it can be moved somewhere else
4597 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4600 // Set up a copy of the stack pointer for use loading and storing any
4601 // arguments that may not fit in the registers available for argument
4603 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4605 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4606 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4607 SmallVector<SDValue, 8> MemOpChains;
4609 bool seenFloatArg = false;
4610 // Walk the register/memloc assignments, inserting copies/loads.
4611 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4614 CCValAssign &VA = ArgLocs[i];
4615 SDValue Arg = OutVals[i];
4616 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4618 if (Flags.isByVal()) {
4619 // Argument is an aggregate which is passed by value, thus we need to
4620 // create a copy of it in the local variable space of the current stack
4621 // frame (which is the stack frame of the caller) and pass the address of
4622 // this copy to the callee.
4623 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4624 CCValAssign &ByValVA = ByValArgLocs[j++];
4625 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4627 // Memory reserved in the local variable space of the callers stack frame.
4628 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4630 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4631 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4634 // Create a copy of the argument in the local area of the current
4636 SDValue MemcpyCall =
4637 CreateCopyOfByValArgument(Arg, PtrOff,
4638 CallSeqStart.getNode()->getOperand(0),
4641 // This must go outside the CALLSEQ_START..END.
4642 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4643 CallSeqStart.getNode()->getOperand(1),
4645 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4646 NewCallSeqStart.getNode());
4647 Chain = CallSeqStart = NewCallSeqStart;
4649 // Pass the address of the aggregate copy on the stack either in a
4650 // physical register or in the parameter list area of the current stack
4651 // frame to the callee.
4655 if (VA.isRegLoc()) {
4656 if (Arg.getValueType() == MVT::i1)
4657 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4659 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4660 // Put argument in a physical register.
4661 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4663 // Put argument in the parameter list area of the current stack frame.
4664 assert(VA.isMemLoc());
4665 unsigned LocMemOffset = VA.getLocMemOffset();
4668 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4669 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4672 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4673 MachinePointerInfo(),
4676 // Calculate and remember argument location.
4677 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4683 if (!MemOpChains.empty())
4684 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4686 // Build a sequence of copy-to-reg nodes chained together with token chain
4687 // and flag operands which copy the outgoing args into the appropriate regs.
4689 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4690 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4691 RegsToPass[i].second, InFlag);
4692 InFlag = Chain.getValue(1);
4695 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4698 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4699 SDValue Ops[] = { Chain, InFlag };
4701 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4702 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4704 InFlag = Chain.getValue(1);
4708 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4709 false, TailCallArguments);
4711 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
4712 /* unused except on PPC64 ELFv1 */ false, DAG,
4713 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4714 NumBytes, Ins, InVals, CS);
4717 // Copy an argument into memory, being careful to do this outside the
4718 // call sequence for the call to which the argument belongs.
4720 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4721 SDValue CallSeqStart,
4722 ISD::ArgFlagsTy Flags,
4725 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4726 CallSeqStart.getNode()->getOperand(0),
4728 // The MEMCPY must go outside the CALLSEQ_START..END.
4729 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4730 CallSeqStart.getNode()->getOperand(1),
4732 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4733 NewCallSeqStart.getNode());
4734 return NewCallSeqStart;
4738 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4739 CallingConv::ID CallConv, bool isVarArg,
4740 bool isTailCall, bool IsPatchPoint,
4741 const SmallVectorImpl<ISD::OutputArg> &Outs,
4742 const SmallVectorImpl<SDValue> &OutVals,
4743 const SmallVectorImpl<ISD::InputArg> &Ins,
4744 SDLoc dl, SelectionDAG &DAG,
4745 SmallVectorImpl<SDValue> &InVals,
4746 ImmutableCallSite *CS) const {
4748 bool isELFv2ABI = Subtarget.isELFv2ABI();
4749 bool isLittleEndian = Subtarget.isLittleEndian();
4750 unsigned NumOps = Outs.size();
4751 bool hasNest = false;
4753 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4754 unsigned PtrByteSize = 8;
4756 MachineFunction &MF = DAG.getMachineFunction();
4758 // Mark this function as potentially containing a function that contains a
4759 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4760 // and restoring the callers stack pointer in this functions epilog. This is
4761 // done because by tail calling the called function might overwrite the value
4762 // in this function's (MF) stack pointer stack slot 0(SP).
4763 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4764 CallConv == CallingConv::Fast)
4765 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4767 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4768 "fastcc not supported on varargs functions");
4770 // Count how many bytes are to be pushed on the stack, including the linkage
4771 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4772 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4773 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4774 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4775 unsigned NumBytes = LinkageSize;
4776 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4777 unsigned &QFPR_idx = FPR_idx;
4779 static const MCPhysReg GPR[] = {
4780 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4781 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4783 static const MCPhysReg VR[] = {
4784 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4785 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4787 static const MCPhysReg VSRH[] = {
4788 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4789 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4792 const unsigned NumGPRs = array_lengthof(GPR);
4793 const unsigned NumFPRs = 13;
4794 const unsigned NumVRs = array_lengthof(VR);
4795 const unsigned NumQFPRs = NumFPRs;
4797 // When using the fast calling convention, we don't provide backing for
4798 // arguments that will be in registers.
4799 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4801 // Add up all the space actually used.
4802 for (unsigned i = 0; i != NumOps; ++i) {
4803 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4804 EVT ArgVT = Outs[i].VT;
4805 EVT OrigVT = Outs[i].ArgVT;
4810 if (CallConv == CallingConv::Fast) {
4811 if (Flags.isByVal())
4812 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4814 switch (ArgVT.getSimpleVT().SimpleTy) {
4815 default: llvm_unreachable("Unexpected ValueType for argument!");
4819 if (++NumGPRsUsed <= NumGPRs)
4828 if (++NumVRsUsed <= NumVRs)
4832 // When using QPX, this is handled like a FP register, otherwise, it
4833 // is an Altivec register.
4834 if (Subtarget.hasQPX()) {
4835 if (++NumFPRsUsed <= NumFPRs)
4838 if (++NumVRsUsed <= NumVRs)
4844 case MVT::v4f64: // QPX
4845 case MVT::v4i1: // QPX
4846 if (++NumFPRsUsed <= NumFPRs)
4852 /* Respect alignment of argument on the stack. */
4854 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4855 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4857 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4858 if (Flags.isInConsecutiveRegsLast())
4859 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4862 unsigned NumBytesActuallyUsed = NumBytes;
4864 // The prolog code of the callee may store up to 8 GPR argument registers to
4865 // the stack, allowing va_start to index over them in memory if its varargs.
4866 // Because we cannot tell if this is needed on the caller side, we have to
4867 // conservatively assume that it is needed. As such, make sure we have at
4868 // least enough stack space for the caller to store the 8 GPRs.
4869 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4870 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4872 // Tail call needs the stack to be aligned.
4873 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4874 CallConv == CallingConv::Fast)
4875 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4877 // Calculate by how many bytes the stack has to be adjusted in case of tail
4878 // call optimization.
4879 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4881 // To protect arguments on the stack from being clobbered in a tail call,
4882 // force all the loads to happen before doing any other lowering.
4884 Chain = DAG.getStackArgumentTokenFactor(Chain);
4886 // Adjust the stack pointer for the new arguments...
4887 // These operations are automatically eliminated by the prolog/epilog pass
4888 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4890 SDValue CallSeqStart = Chain;
4892 // Load the return address and frame pointer so it can be move somewhere else
4895 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4898 // Set up a copy of the stack pointer for use loading and storing any
4899 // arguments that may not fit in the registers available for argument
4901 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4903 // Figure out which arguments are going to go in registers, and which in
4904 // memory. Also, if this is a vararg function, floating point operations
4905 // must be stored to our stack, and loaded into integer regs as well, if
4906 // any integer regs are available for argument passing.
4907 unsigned ArgOffset = LinkageSize;
4909 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4910 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4912 SmallVector<SDValue, 8> MemOpChains;
4913 for (unsigned i = 0; i != NumOps; ++i) {
4914 SDValue Arg = OutVals[i];
4915 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4916 EVT ArgVT = Outs[i].VT;
4917 EVT OrigVT = Outs[i].ArgVT;
4919 // PtrOff will be used to store the current argument to the stack if a
4920 // register cannot be found for it.
4923 // We re-align the argument offset for each argument, except when using the
4924 // fast calling convention, when we need to make sure we do that only when
4925 // we'll actually use a stack slot.
4926 auto ComputePtrOff = [&]() {
4927 /* Respect alignment of argument on the stack. */
4929 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4930 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4932 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4934 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4937 if (CallConv != CallingConv::Fast) {
4940 /* Compute GPR index associated with argument offset. */
4941 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4942 GPR_idx = std::min(GPR_idx, NumGPRs);
4945 // Promote integers to 64-bit values.
4946 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4947 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4948 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4949 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4952 // FIXME memcpy is used way more than necessary. Correctness first.
4953 // Note: "by value" is code for passing a structure by value, not
4955 if (Flags.isByVal()) {
4956 // Note: Size includes alignment padding, so
4957 // struct x { short a; char b; }
4958 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4959 // These are the proper values we need for right-justifying the
4960 // aggregate in a parameter register.
4961 unsigned Size = Flags.getByValSize();
4963 // An empty aggregate parameter takes up no storage and no
4968 if (CallConv == CallingConv::Fast)
4971 // All aggregates smaller than 8 bytes must be passed right-justified.
4972 if (Size==1 || Size==2 || Size==4) {
4973 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4974 if (GPR_idx != NumGPRs) {
4975 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4976 MachinePointerInfo(), VT,
4977 false, false, false, 0);
4978 MemOpChains.push_back(Load.getValue(1));
4979 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4981 ArgOffset += PtrByteSize;
4986 if (GPR_idx == NumGPRs && Size < 8) {
4987 SDValue AddPtr = PtrOff;
4988 if (!isLittleEndian) {
4989 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4990 PtrOff.getValueType());
4991 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4993 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4996 ArgOffset += PtrByteSize;
4999 // Copy entire object into memory. There are cases where gcc-generated
5000 // code assumes it is there, even if it could be put entirely into
5001 // registers. (This is not what the doc says.)
5003 // FIXME: The above statement is likely due to a misunderstanding of the
5004 // documents. All arguments must be copied into the parameter area BY
5005 // THE CALLEE in the event that the callee takes the address of any
5006 // formal argument. That has not yet been implemented. However, it is
5007 // reasonable to use the stack area as a staging area for the register
5010 // Skip this for small aggregates, as we will use the same slot for a
5011 // right-justified copy, below.
5013 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5017 // When a register is available, pass a small aggregate right-justified.
5018 if (Size < 8 && GPR_idx != NumGPRs) {
5019 // The easiest way to get this right-justified in a register
5020 // is to copy the structure into the rightmost portion of a
5021 // local variable slot, then load the whole slot into the
5023 // FIXME: The memcpy seems to produce pretty awful code for
5024 // small aggregates, particularly for packed ones.
5025 // FIXME: It would be preferable to use the slot in the
5026 // parameter save area instead of a new local variable.
5027 SDValue AddPtr = PtrOff;
5028 if (!isLittleEndian) {
5029 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5030 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5032 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5036 // Load the slot into the register.
5037 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
5038 MachinePointerInfo(),
5039 false, false, false, 0);
5040 MemOpChains.push_back(Load.getValue(1));
5041 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5043 // Done with this argument.
5044 ArgOffset += PtrByteSize;
5048 // For aggregates larger than PtrByteSize, copy the pieces of the
5049 // object that fit into registers from the parameter save area.
5050 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5051 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5052 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5053 if (GPR_idx != NumGPRs) {
5054 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5055 MachinePointerInfo(),
5056 false, false, false, 0);
5057 MemOpChains.push_back(Load.getValue(1));
5058 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5059 ArgOffset += PtrByteSize;
5061 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5068 switch (Arg.getSimpleValueType().SimpleTy) {
5069 default: llvm_unreachable("Unexpected ValueType for argument!");
5073 if (Flags.isNest()) {
5074 // The 'nest' parameter, if any, is passed in R11.
5075 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5080 // These can be scalar arguments or elements of an integer array type
5081 // passed directly. Clang may use those instead of "byval" aggregate
5082 // types to avoid forcing arguments to memory unnecessarily.
5083 if (GPR_idx != NumGPRs) {
5084 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5086 if (CallConv == CallingConv::Fast)
5089 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5090 true, isTailCall, false, MemOpChains,
5091 TailCallArguments, dl);
5092 if (CallConv == CallingConv::Fast)
5093 ArgOffset += PtrByteSize;
5095 if (CallConv != CallingConv::Fast)
5096 ArgOffset += PtrByteSize;
5100 // These can be scalar arguments or elements of a float array type
5101 // passed directly. The latter are used to implement ELFv2 homogenous
5102 // float aggregates.
5104 // Named arguments go into FPRs first, and once they overflow, the
5105 // remaining arguments go into GPRs and then the parameter save area.
5106 // Unnamed arguments for vararg functions always go to GPRs and
5107 // then the parameter save area. For now, put all arguments to vararg
5108 // routines always in both locations (FPR *and* GPR or stack slot).
5109 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5110 bool NeededLoad = false;
5112 // First load the argument into the next available FPR.
5113 if (FPR_idx != NumFPRs)
5114 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5116 // Next, load the argument into GPR or stack slot if needed.
5117 if (!NeedGPROrStack)
5119 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5120 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5121 // once we support fp <-> gpr moves.
5123 // In the non-vararg case, this can only ever happen in the
5124 // presence of f32 array types, since otherwise we never run
5125 // out of FPRs before running out of GPRs.
5128 // Double values are always passed in a single GPR.
5129 if (Arg.getValueType() != MVT::f32) {
5130 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5132 // Non-array float values are extended and passed in a GPR.
5133 } else if (!Flags.isInConsecutiveRegs()) {
5134 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5135 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5137 // If we have an array of floats, we collect every odd element
5138 // together with its predecessor into one GPR.
5139 } else if (ArgOffset % PtrByteSize != 0) {
5141 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5142 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5143 if (!isLittleEndian)
5145 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5147 // The final element, if even, goes into the first half of a GPR.
5148 } else if (Flags.isInConsecutiveRegsLast()) {
5149 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5150 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5151 if (!isLittleEndian)
5152 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5153 DAG.getConstant(32, dl, MVT::i32));
5155 // Non-final even elements are skipped; they will be handled
5156 // together the with subsequent argument on the next go-around.
5160 if (ArgVal.getNode())
5161 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5163 if (CallConv == CallingConv::Fast)
5166 // Single-precision floating-point values are mapped to the
5167 // second (rightmost) word of the stack doubleword.
5168 if (Arg.getValueType() == MVT::f32 &&
5169 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5170 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5171 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5174 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5175 true, isTailCall, false, MemOpChains,
5176 TailCallArguments, dl);
5180 // When passing an array of floats, the array occupies consecutive
5181 // space in the argument area; only round up to the next doubleword
5182 // at the end of the array. Otherwise, each float takes 8 bytes.
5183 if (CallConv != CallingConv::Fast || NeededLoad) {
5184 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5185 Flags.isInConsecutiveRegs()) ? 4 : 8;
5186 if (Flags.isInConsecutiveRegsLast())
5187 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5198 if (!Subtarget.hasQPX()) {
5199 // These can be scalar arguments or elements of a vector array type
5200 // passed directly. The latter are used to implement ELFv2 homogenous
5201 // vector aggregates.
5203 // For a varargs call, named arguments go into VRs or on the stack as
5204 // usual; unnamed arguments always go to the stack or the corresponding
5205 // GPRs when within range. For now, we always put the value in both
5206 // locations (or even all three).
5208 // We could elide this store in the case where the object fits
5209 // entirely in R registers. Maybe later.
5210 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5211 MachinePointerInfo(), false, false, 0);
5212 MemOpChains.push_back(Store);
5213 if (VR_idx != NumVRs) {
5214 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5215 MachinePointerInfo(),
5216 false, false, false, 0);
5217 MemOpChains.push_back(Load.getValue(1));
5219 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5220 Arg.getSimpleValueType() == MVT::v2i64) ?
5221 VSRH[VR_idx] : VR[VR_idx];
5224 RegsToPass.push_back(std::make_pair(VReg, Load));
5227 for (unsigned i=0; i<16; i+=PtrByteSize) {
5228 if (GPR_idx == NumGPRs)
5230 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5231 DAG.getConstant(i, dl, PtrVT));
5232 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5233 false, false, false, 0);
5234 MemOpChains.push_back(Load.getValue(1));
5235 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5240 // Non-varargs Altivec params go into VRs or on the stack.
5241 if (VR_idx != NumVRs) {
5242 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5243 Arg.getSimpleValueType() == MVT::v2i64) ?
5244 VSRH[VR_idx] : VR[VR_idx];
5247 RegsToPass.push_back(std::make_pair(VReg, Arg));
5249 if (CallConv == CallingConv::Fast)
5252 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5253 true, isTailCall, true, MemOpChains,
5254 TailCallArguments, dl);
5255 if (CallConv == CallingConv::Fast)
5259 if (CallConv != CallingConv::Fast)
5264 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5265 "Invalid QPX parameter type");
5270 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5272 // We could elide this store in the case where the object fits
5273 // entirely in R registers. Maybe later.
5274 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5275 MachinePointerInfo(), false, false, 0);
5276 MemOpChains.push_back(Store);
5277 if (QFPR_idx != NumQFPRs) {
5278 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5279 Store, PtrOff, MachinePointerInfo(),
5280 false, false, false, 0);
5281 MemOpChains.push_back(Load.getValue(1));
5282 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5284 ArgOffset += (IsF32 ? 16 : 32);
5285 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5286 if (GPR_idx == NumGPRs)
5288 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5289 DAG.getConstant(i, dl, PtrVT));
5290 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5291 false, false, false, 0);
5292 MemOpChains.push_back(Load.getValue(1));
5293 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5298 // Non-varargs QPX params go into registers or on the stack.
5299 if (QFPR_idx != NumQFPRs) {
5300 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5302 if (CallConv == CallingConv::Fast)
5305 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5306 true, isTailCall, true, MemOpChains,
5307 TailCallArguments, dl);
5308 if (CallConv == CallingConv::Fast)
5309 ArgOffset += (IsF32 ? 16 : 32);
5312 if (CallConv != CallingConv::Fast)
5313 ArgOffset += (IsF32 ? 16 : 32);
5319 assert(NumBytesActuallyUsed == ArgOffset);
5320 (void)NumBytesActuallyUsed;
5322 if (!MemOpChains.empty())
5323 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5325 // Check if this is an indirect call (MTCTR/BCTRL).
5326 // See PrepareCall() for more information about calls through function
5327 // pointers in the 64-bit SVR4 ABI.
5328 if (!isTailCall && !IsPatchPoint &&
5329 !isFunctionGlobalAddress(Callee) &&
5330 !isa<ExternalSymbolSDNode>(Callee)) {
5331 // Load r2 into a virtual register and store it to the TOC save area.
5332 setUsesTOCBasePtr(DAG);
5333 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5334 // TOC save area offset.
5335 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5336 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5337 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5338 Chain = DAG.getStore(
5339 Val.getValue(1), dl, Val, AddPtr,
5340 MachinePointerInfo::getStack(DAG.getMachineFunction(), TOCSaveOffset),
5342 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5343 // This does not mean the MTCTR instruction must use R12; it's easier
5344 // to model this as an extra parameter, so do that.
5345 if (isELFv2ABI && !IsPatchPoint)
5346 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5349 // Build a sequence of copy-to-reg nodes chained together with token chain
5350 // and flag operands which copy the outgoing args into the appropriate regs.
5352 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5353 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5354 RegsToPass[i].second, InFlag);
5355 InFlag = Chain.getValue(1);
5359 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5360 FPOp, true, TailCallArguments);
5362 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, hasNest,
5363 DAG, RegsToPass, InFlag, Chain, CallSeqStart, Callee,
5364 SPDiff, NumBytes, Ins, InVals, CS);
5368 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5369 CallingConv::ID CallConv, bool isVarArg,
5370 bool isTailCall, bool IsPatchPoint,
5371 const SmallVectorImpl<ISD::OutputArg> &Outs,
5372 const SmallVectorImpl<SDValue> &OutVals,
5373 const SmallVectorImpl<ISD::InputArg> &Ins,
5374 SDLoc dl, SelectionDAG &DAG,
5375 SmallVectorImpl<SDValue> &InVals,
5376 ImmutableCallSite *CS) const {
5378 unsigned NumOps = Outs.size();
5380 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5381 bool isPPC64 = PtrVT == MVT::i64;
5382 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5384 MachineFunction &MF = DAG.getMachineFunction();
5386 // Mark this function as potentially containing a function that contains a
5387 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5388 // and restoring the callers stack pointer in this functions epilog. This is
5389 // done because by tail calling the called function might overwrite the value
5390 // in this function's (MF) stack pointer stack slot 0(SP).
5391 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5392 CallConv == CallingConv::Fast)
5393 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5395 // Count how many bytes are to be pushed on the stack, including the linkage
5396 // area, and parameter passing area. We start with 24/48 bytes, which is
5397 // prereserved space for [SP][CR][LR][3 x unused].
5398 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5399 unsigned NumBytes = LinkageSize;
5401 // Add up all the space actually used.
5402 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5403 // they all go in registers, but we must reserve stack space for them for
5404 // possible use by the caller. In varargs or 64-bit calls, parameters are
5405 // assigned stack space in order, with padding so Altivec parameters are
5407 unsigned nAltivecParamsAtEnd = 0;
5408 for (unsigned i = 0; i != NumOps; ++i) {
5409 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5410 EVT ArgVT = Outs[i].VT;
5411 // Varargs Altivec parameters are padded to a 16 byte boundary.
5412 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5413 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5414 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5415 if (!isVarArg && !isPPC64) {
5416 // Non-varargs Altivec parameters go after all the non-Altivec
5417 // parameters; handle those later so we know how much padding we need.
5418 nAltivecParamsAtEnd++;
5421 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5422 NumBytes = ((NumBytes+15)/16)*16;
5424 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5427 // Allow for Altivec parameters at the end, if needed.
5428 if (nAltivecParamsAtEnd) {
5429 NumBytes = ((NumBytes+15)/16)*16;
5430 NumBytes += 16*nAltivecParamsAtEnd;
5433 // The prolog code of the callee may store up to 8 GPR argument registers to
5434 // the stack, allowing va_start to index over them in memory if its varargs.
5435 // Because we cannot tell if this is needed on the caller side, we have to
5436 // conservatively assume that it is needed. As such, make sure we have at
5437 // least enough stack space for the caller to store the 8 GPRs.
5438 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5440 // Tail call needs the stack to be aligned.
5441 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5442 CallConv == CallingConv::Fast)
5443 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5445 // Calculate by how many bytes the stack has to be adjusted in case of tail
5446 // call optimization.
5447 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5449 // To protect arguments on the stack from being clobbered in a tail call,
5450 // force all the loads to happen before doing any other lowering.
5452 Chain = DAG.getStackArgumentTokenFactor(Chain);
5454 // Adjust the stack pointer for the new arguments...
5455 // These operations are automatically eliminated by the prolog/epilog pass
5456 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5458 SDValue CallSeqStart = Chain;
5460 // Load the return address and frame pointer so it can be move somewhere else
5463 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5466 // Set up a copy of the stack pointer for use loading and storing any
5467 // arguments that may not fit in the registers available for argument
5471 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5473 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5475 // Figure out which arguments are going to go in registers, and which in
5476 // memory. Also, if this is a vararg function, floating point operations
5477 // must be stored to our stack, and loaded into integer regs as well, if
5478 // any integer regs are available for argument passing.
5479 unsigned ArgOffset = LinkageSize;
5480 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5482 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5483 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5484 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5486 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5487 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5488 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5490 static const MCPhysReg VR[] = {
5491 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5492 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5494 const unsigned NumGPRs = array_lengthof(GPR_32);
5495 const unsigned NumFPRs = 13;
5496 const unsigned NumVRs = array_lengthof(VR);
5498 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5500 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5501 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5503 SmallVector<SDValue, 8> MemOpChains;
5504 for (unsigned i = 0; i != NumOps; ++i) {
5505 SDValue Arg = OutVals[i];
5506 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5508 // PtrOff will be used to store the current argument to the stack if a
5509 // register cannot be found for it.
5512 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5514 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5516 // On PPC64, promote integers to 64-bit values.
5517 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5518 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5519 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5520 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5523 // FIXME memcpy is used way more than necessary. Correctness first.
5524 // Note: "by value" is code for passing a structure by value, not
5526 if (Flags.isByVal()) {
5527 unsigned Size = Flags.getByValSize();
5528 // Very small objects are passed right-justified. Everything else is
5529 // passed left-justified.
5530 if (Size==1 || Size==2) {
5531 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5532 if (GPR_idx != NumGPRs) {
5533 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5534 MachinePointerInfo(), VT,
5535 false, false, false, 0);
5536 MemOpChains.push_back(Load.getValue(1));
5537 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5539 ArgOffset += PtrByteSize;
5541 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5542 PtrOff.getValueType());
5543 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5544 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5547 ArgOffset += PtrByteSize;
5551 // Copy entire object into memory. There are cases where gcc-generated
5552 // code assumes it is there, even if it could be put entirely into
5553 // registers. (This is not what the doc says.)
5554 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5558 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5559 // copy the pieces of the object that fit into registers from the
5560 // parameter save area.
5561 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5562 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5563 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5564 if (GPR_idx != NumGPRs) {
5565 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5566 MachinePointerInfo(),
5567 false, false, false, 0);
5568 MemOpChains.push_back(Load.getValue(1));
5569 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5570 ArgOffset += PtrByteSize;
5572 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5579 switch (Arg.getSimpleValueType().SimpleTy) {
5580 default: llvm_unreachable("Unexpected ValueType for argument!");
5584 if (GPR_idx != NumGPRs) {
5585 if (Arg.getValueType() == MVT::i1)
5586 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5588 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5590 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5591 isPPC64, isTailCall, false, MemOpChains,
5592 TailCallArguments, dl);
5594 ArgOffset += PtrByteSize;
5598 if (FPR_idx != NumFPRs) {
5599 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5602 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5603 MachinePointerInfo(), false, false, 0);
5604 MemOpChains.push_back(Store);
5606 // Float varargs are always shadowed in available integer registers
5607 if (GPR_idx != NumGPRs) {
5608 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5609 MachinePointerInfo(), false, false,
5611 MemOpChains.push_back(Load.getValue(1));
5612 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5614 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5615 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5616 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5617 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5618 MachinePointerInfo(),
5619 false, false, false, 0);
5620 MemOpChains.push_back(Load.getValue(1));
5621 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5624 // If we have any FPRs remaining, we may also have GPRs remaining.
5625 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5627 if (GPR_idx != NumGPRs)
5629 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5630 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5634 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5635 isPPC64, isTailCall, false, MemOpChains,
5636 TailCallArguments, dl);
5640 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5647 // These go aligned on the stack, or in the corresponding R registers
5648 // when within range. The Darwin PPC ABI doc claims they also go in
5649 // V registers; in fact gcc does this only for arguments that are
5650 // prototyped, not for those that match the ... We do it for all
5651 // arguments, seems to work.
5652 while (ArgOffset % 16 !=0) {
5653 ArgOffset += PtrByteSize;
5654 if (GPR_idx != NumGPRs)
5657 // We could elide this store in the case where the object fits
5658 // entirely in R registers. Maybe later.
5659 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5660 DAG.getConstant(ArgOffset, dl, PtrVT));
5661 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5662 MachinePointerInfo(), false, false, 0);
5663 MemOpChains.push_back(Store);
5664 if (VR_idx != NumVRs) {
5665 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5666 MachinePointerInfo(),
5667 false, false, false, 0);
5668 MemOpChains.push_back(Load.getValue(1));
5669 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5672 for (unsigned i=0; i<16; i+=PtrByteSize) {
5673 if (GPR_idx == NumGPRs)
5675 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5676 DAG.getConstant(i, dl, PtrVT));
5677 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5678 false, false, false, 0);
5679 MemOpChains.push_back(Load.getValue(1));
5680 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5685 // Non-varargs Altivec params generally go in registers, but have
5686 // stack space allocated at the end.
5687 if (VR_idx != NumVRs) {
5688 // Doesn't have GPR space allocated.
5689 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5690 } else if (nAltivecParamsAtEnd==0) {
5691 // We are emitting Altivec params in order.
5692 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5693 isPPC64, isTailCall, true, MemOpChains,
5694 TailCallArguments, dl);
5700 // If all Altivec parameters fit in registers, as they usually do,
5701 // they get stack space following the non-Altivec parameters. We
5702 // don't track this here because nobody below needs it.
5703 // If there are more Altivec parameters than fit in registers emit
5705 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5707 // Offset is aligned; skip 1st 12 params which go in V registers.
5708 ArgOffset = ((ArgOffset+15)/16)*16;
5710 for (unsigned i = 0; i != NumOps; ++i) {
5711 SDValue Arg = OutVals[i];
5712 EVT ArgType = Outs[i].VT;
5713 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5714 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5717 // We are emitting Altivec params in order.
5718 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5719 isPPC64, isTailCall, true, MemOpChains,
5720 TailCallArguments, dl);
5727 if (!MemOpChains.empty())
5728 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5730 // On Darwin, R12 must contain the address of an indirect callee. This does
5731 // not mean the MTCTR instruction must use R12; it's easier to model this as
5732 // an extra parameter, so do that.
5734 !isFunctionGlobalAddress(Callee) &&
5735 !isa<ExternalSymbolSDNode>(Callee) &&
5736 !isBLACompatibleAddress(Callee, DAG))
5737 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5738 PPC::R12), Callee));
5740 // Build a sequence of copy-to-reg nodes chained together with token chain
5741 // and flag operands which copy the outgoing args into the appropriate regs.
5743 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5744 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5745 RegsToPass[i].second, InFlag);
5746 InFlag = Chain.getValue(1);
5750 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5751 FPOp, true, TailCallArguments);
5753 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5754 /* unused except on PPC64 ELFv1 */ false, DAG,
5755 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5756 NumBytes, Ins, InVals, CS);
5760 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5761 MachineFunction &MF, bool isVarArg,
5762 const SmallVectorImpl<ISD::OutputArg> &Outs,
5763 LLVMContext &Context) const {
5764 SmallVector<CCValAssign, 16> RVLocs;
5765 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5766 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5770 PPCTargetLowering::LowerReturn(SDValue Chain,
5771 CallingConv::ID CallConv, bool isVarArg,
5772 const SmallVectorImpl<ISD::OutputArg> &Outs,
5773 const SmallVectorImpl<SDValue> &OutVals,
5774 SDLoc dl, SelectionDAG &DAG) const {
5776 SmallVector<CCValAssign, 16> RVLocs;
5777 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5779 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5782 SmallVector<SDValue, 4> RetOps(1, Chain);
5784 // Copy the result values into the output registers.
5785 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5786 CCValAssign &VA = RVLocs[i];
5787 assert(VA.isRegLoc() && "Can only return in registers!");
5789 SDValue Arg = OutVals[i];
5791 switch (VA.getLocInfo()) {
5792 default: llvm_unreachable("Unknown loc info!");
5793 case CCValAssign::Full: break;
5794 case CCValAssign::AExt:
5795 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5797 case CCValAssign::ZExt:
5798 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5800 case CCValAssign::SExt:
5801 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5805 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5806 Flag = Chain.getValue(1);
5807 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5810 RetOps[0] = Chain; // Update chain.
5812 // Add the flag if we have it.
5814 RetOps.push_back(Flag);
5816 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5819 SDValue PPCTargetLowering::LowerGET_DYNAMIC_AREA_OFFSET(
5820 SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const {
5823 // Get the corect type for integers.
5824 EVT IntVT = Op.getValueType();
5827 SDValue Chain = Op.getOperand(0);
5828 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5829 // Build a DYNAREAOFFSET node.
5830 SDValue Ops[2] = {Chain, FPSIdx};
5831 SDVTList VTs = DAG.getVTList(IntVT);
5832 return DAG.getNode(PPCISD::DYNAREAOFFSET, dl, VTs, Ops);
5835 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5836 const PPCSubtarget &Subtarget) const {
5837 // When we pop the dynamic allocation we need to restore the SP link.
5840 // Get the corect type for pointers.
5841 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5843 // Construct the stack pointer operand.
5844 bool isPPC64 = Subtarget.isPPC64();
5845 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5846 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5848 // Get the operands for the STACKRESTORE.
5849 SDValue Chain = Op.getOperand(0);
5850 SDValue SaveSP = Op.getOperand(1);
5852 // Load the old link SP.
5853 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5854 MachinePointerInfo(),
5855 false, false, false, 0);
5857 // Restore the stack pointer.
5858 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5860 // Store the old link SP.
5861 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5865 SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG &DAG) const {
5866 MachineFunction &MF = DAG.getMachineFunction();
5867 bool isPPC64 = Subtarget.isPPC64();
5868 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5870 // Get current frame pointer save index. The users of this index will be
5871 // primarily DYNALLOC instructions.
5872 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5873 int RASI = FI->getReturnAddrSaveIndex();
5875 // If the frame pointer save index hasn't been defined yet.
5877 // Find out what the fix offset of the frame pointer save area.
5878 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5879 // Allocate the frame index for frame pointer save area.
5880 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5882 FI->setReturnAddrSaveIndex(RASI);
5884 return DAG.getFrameIndex(RASI, PtrVT);
5888 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5889 MachineFunction &MF = DAG.getMachineFunction();
5890 bool isPPC64 = Subtarget.isPPC64();
5891 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5893 // Get current frame pointer save index. The users of this index will be
5894 // primarily DYNALLOC instructions.
5895 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5896 int FPSI = FI->getFramePointerSaveIndex();
5898 // If the frame pointer save index hasn't been defined yet.
5900 // Find out what the fix offset of the frame pointer save area.
5901 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5902 // Allocate the frame index for frame pointer save area.
5903 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5905 FI->setFramePointerSaveIndex(FPSI);
5907 return DAG.getFrameIndex(FPSI, PtrVT);
5910 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5912 const PPCSubtarget &Subtarget) const {
5914 SDValue Chain = Op.getOperand(0);
5915 SDValue Size = Op.getOperand(1);
5918 // Get the corect type for pointers.
5919 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5921 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5922 DAG.getConstant(0, dl, PtrVT), Size);
5923 // Construct a node for the frame pointer save index.
5924 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5925 // Build a DYNALLOC node.
5926 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5927 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5928 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5931 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5932 SelectionDAG &DAG) const {
5934 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5935 DAG.getVTList(MVT::i32, MVT::Other),
5936 Op.getOperand(0), Op.getOperand(1));
5939 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5940 SelectionDAG &DAG) const {
5942 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5943 Op.getOperand(0), Op.getOperand(1));
5946 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5947 if (Op.getValueType().isVector())
5948 return LowerVectorLoad(Op, DAG);
5950 assert(Op.getValueType() == MVT::i1 &&
5951 "Custom lowering only for i1 loads");
5953 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5956 LoadSDNode *LD = cast<LoadSDNode>(Op);
5958 SDValue Chain = LD->getChain();
5959 SDValue BasePtr = LD->getBasePtr();
5960 MachineMemOperand *MMO = LD->getMemOperand();
5963 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
5964 BasePtr, MVT::i8, MMO);
5965 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5967 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5968 return DAG.getMergeValues(Ops, dl);
5971 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5972 if (Op.getOperand(1).getValueType().isVector())
5973 return LowerVectorStore(Op, DAG);
5975 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5976 "Custom lowering only for i1 stores");
5978 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5981 StoreSDNode *ST = cast<StoreSDNode>(Op);
5983 SDValue Chain = ST->getChain();
5984 SDValue BasePtr = ST->getBasePtr();
5985 SDValue Value = ST->getValue();
5986 MachineMemOperand *MMO = ST->getMemOperand();
5988 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
5990 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5993 // FIXME: Remove this once the ANDI glue bug is fixed:
5994 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5995 assert(Op.getValueType() == MVT::i1 &&
5996 "Custom lowering only for i1 results");
5999 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
6003 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
6005 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
6006 // Not FP? Not a fsel.
6007 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
6008 !Op.getOperand(2).getValueType().isFloatingPoint())
6011 // We might be able to do better than this under some circumstances, but in
6012 // general, fsel-based lowering of select is a finite-math-only optimization.
6013 // For more information, see section F.3 of the 2.06 ISA specification.
6014 if (!DAG.getTarget().Options.NoInfsFPMath ||
6015 !DAG.getTarget().Options.NoNaNsFPMath)
6017 // TODO: Propagate flags from the select rather than global settings.
6019 Flags.setNoInfs(true);
6020 Flags.setNoNaNs(true);
6022 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
6024 EVT ResVT = Op.getValueType();
6025 EVT CmpVT = Op.getOperand(0).getValueType();
6026 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6027 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
6030 // If the RHS of the comparison is a 0.0, we don't need to do the
6031 // subtraction at all.
6033 if (isFloatingPointZero(RHS))
6035 default: break; // SETUO etc aren't handled by fsel.
6039 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6040 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6041 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6042 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6043 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6044 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6045 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
6048 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6051 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6052 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6053 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6056 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6059 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6060 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6061 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6062 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
6067 default: break; // SETUO etc aren't handled by fsel.
6071 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6072 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6073 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6074 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6075 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6076 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6077 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6078 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6081 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6082 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6083 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6084 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6087 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6088 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6089 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6090 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6093 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6094 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6095 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6096 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6099 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6100 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6101 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6102 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6107 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6110 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6111 SDValue Src = Op.getOperand(0);
6112 if (Src.getValueType() == MVT::f32)
6113 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6116 switch (Op.getSimpleValueType().SimpleTy) {
6117 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6120 Op.getOpcode() == ISD::FP_TO_SINT
6122 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6126 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6127 "i64 FP_TO_UINT is supported only with FPCVT");
6128 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6134 // Convert the FP value to an int value through memory.
6135 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6136 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6137 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6138 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6139 MachinePointerInfo MPI =
6140 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
6142 // Emit a store to the stack slot.
6145 MachineFunction &MF = DAG.getMachineFunction();
6146 MachineMemOperand *MMO =
6147 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6148 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6149 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6150 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6152 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6153 MPI, false, false, 0);
6155 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6157 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6158 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6159 DAG.getConstant(4, dl, FIPtr.getValueType()));
6160 MPI = MPI.getWithOffset(4);
6168 /// \brief Custom lowers floating point to integer conversions to use
6169 /// the direct move instructions available in ISA 2.07 to avoid the
6170 /// need for load/store combinations.
6171 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6174 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6175 SDValue Src = Op.getOperand(0);
6177 if (Src.getValueType() == MVT::f32)
6178 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6181 switch (Op.getSimpleValueType().SimpleTy) {
6182 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6185 Op.getOpcode() == ISD::FP_TO_SINT
6187 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6189 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6192 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6193 "i64 FP_TO_UINT is supported only with FPCVT");
6194 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6197 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6203 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6205 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6206 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6209 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6211 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6212 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6216 // We're trying to insert a regular store, S, and then a load, L. If the
6217 // incoming value, O, is a load, we might just be able to have our load use the
6218 // address used by O. However, we don't know if anything else will store to
6219 // that address before we can load from it. To prevent this situation, we need
6220 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6221 // the same chain operand as O, we create a token factor from the chain results
6222 // of O and L, and we replace all uses of O's chain result with that token
6223 // factor (see spliceIntoChain below for this last part).
6224 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6227 ISD::LoadExtType ET) const {
6229 if (ET == ISD::NON_EXTLOAD &&
6230 (Op.getOpcode() == ISD::FP_TO_UINT ||
6231 Op.getOpcode() == ISD::FP_TO_SINT) &&
6232 isOperationLegalOrCustom(Op.getOpcode(),
6233 Op.getOperand(0).getValueType())) {
6235 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6239 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6240 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6241 LD->isNonTemporal())
6243 if (LD->getMemoryVT() != MemVT)
6246 RLI.Ptr = LD->getBasePtr();
6247 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6248 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6249 "Non-pre-inc AM on PPC?");
6250 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6254 RLI.Chain = LD->getChain();
6255 RLI.MPI = LD->getPointerInfo();
6256 RLI.IsInvariant = LD->isInvariant();
6257 RLI.Alignment = LD->getAlignment();
6258 RLI.AAInfo = LD->getAAInfo();
6259 RLI.Ranges = LD->getRanges();
6261 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6265 // Given the head of the old chain, ResChain, insert a token factor containing
6266 // it and NewResChain, and make users of ResChain now be users of that token
6268 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6269 SDValue NewResChain,
6270 SelectionDAG &DAG) const {
6274 SDLoc dl(NewResChain);
6276 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6277 NewResChain, DAG.getUNDEF(MVT::Other));
6278 assert(TF.getNode() != NewResChain.getNode() &&
6279 "A new TF really is required here");
6281 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6282 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6285 /// \brief Custom lowers integer to floating point conversions to use
6286 /// the direct move instructions available in ISA 2.07 to avoid the
6287 /// need for load/store combinations.
6288 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6291 assert((Op.getValueType() == MVT::f32 ||
6292 Op.getValueType() == MVT::f64) &&
6293 "Invalid floating point type as target of conversion");
6294 assert(Subtarget.hasFPCVT() &&
6295 "Int to FP conversions with direct moves require FPCVT");
6297 SDValue Src = Op.getOperand(0);
6298 bool SinglePrec = Op.getValueType() == MVT::f32;
6299 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6300 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6301 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6302 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6305 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6307 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6310 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6311 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6317 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6318 SelectionDAG &DAG) const {
6321 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6322 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6325 SDValue Value = Op.getOperand(0);
6326 // The values are now known to be -1 (false) or 1 (true). To convert this
6327 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6328 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6329 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6331 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6332 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, FPHalfs, FPHalfs,
6335 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6337 if (Op.getValueType() != MVT::v4f64)
6338 Value = DAG.getNode(ISD::FP_ROUND, dl,
6339 Op.getValueType(), Value,
6340 DAG.getIntPtrConstant(1, dl));
6344 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6345 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6348 if (Op.getOperand(0).getValueType() == MVT::i1)
6349 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6350 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6351 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6353 // If we have direct moves, we can do all the conversion, skip the store/load
6354 // however, without FPCVT we can't do most conversions.
6355 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6356 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6358 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6359 "UINT_TO_FP is supported only with FPCVT");
6361 // If we have FCFIDS, then use it when converting to single-precision.
6362 // Otherwise, convert to double-precision and then round.
6363 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6364 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6366 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6368 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6372 if (Op.getOperand(0).getValueType() == MVT::i64) {
6373 SDValue SINT = Op.getOperand(0);
6374 // When converting to single-precision, we actually need to convert
6375 // to double-precision first and then round to single-precision.
6376 // To avoid double-rounding effects during that operation, we have
6377 // to prepare the input operand. Bits that might be truncated when
6378 // converting to double-precision are replaced by a bit that won't
6379 // be lost at this stage, but is below the single-precision rounding
6382 // However, if -enable-unsafe-fp-math is in effect, accept double
6383 // rounding to avoid the extra overhead.
6384 if (Op.getValueType() == MVT::f32 &&
6385 !Subtarget.hasFPCVT() &&
6386 !DAG.getTarget().Options.UnsafeFPMath) {
6388 // Twiddle input to make sure the low 11 bits are zero. (If this
6389 // is the case, we are guaranteed the value will fit into the 53 bit
6390 // mantissa of an IEEE double-precision value without rounding.)
6391 // If any of those low 11 bits were not zero originally, make sure
6392 // bit 12 (value 2048) is set instead, so that the final rounding
6393 // to single-precision gets the correct result.
6394 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6395 SINT, DAG.getConstant(2047, dl, MVT::i64));
6396 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6397 Round, DAG.getConstant(2047, dl, MVT::i64));
6398 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6399 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6400 Round, DAG.getConstant(-2048, dl, MVT::i64));
6402 // However, we cannot use that value unconditionally: if the magnitude
6403 // of the input value is small, the bit-twiddling we did above might
6404 // end up visibly changing the output. Fortunately, in that case, we
6405 // don't need to twiddle bits since the original input will convert
6406 // exactly to double-precision floating-point already. Therefore,
6407 // construct a conditional to use the original value if the top 11
6408 // bits are all sign-bit copies, and use the rounded value computed
6410 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6411 SINT, DAG.getConstant(53, dl, MVT::i32));
6412 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6413 Cond, DAG.getConstant(1, dl, MVT::i64));
6414 Cond = DAG.getSetCC(dl, MVT::i32,
6415 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6417 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6423 MachineFunction &MF = DAG.getMachineFunction();
6424 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6425 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6426 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6428 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6429 } else if (Subtarget.hasLFIWAX() &&
6430 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6431 MachineMemOperand *MMO =
6432 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6433 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6434 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6435 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6436 DAG.getVTList(MVT::f64, MVT::Other),
6437 Ops, MVT::i32, MMO);
6438 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6439 } else if (Subtarget.hasFPCVT() &&
6440 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6441 MachineMemOperand *MMO =
6442 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6443 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6444 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6445 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6446 DAG.getVTList(MVT::f64, MVT::Other),
6447 Ops, MVT::i32, MMO);
6448 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6449 } else if (((Subtarget.hasLFIWAX() &&
6450 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6451 (Subtarget.hasFPCVT() &&
6452 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6453 SINT.getOperand(0).getValueType() == MVT::i32) {
6454 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6455 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
6457 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6458 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6460 SDValue Store = DAG.getStore(
6461 DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6462 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6465 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6466 "Expected an i32 store");
6471 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6474 MachineMemOperand *MMO =
6475 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6476 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6477 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6478 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6479 PPCISD::LFIWZX : PPCISD::LFIWAX,
6480 dl, DAG.getVTList(MVT::f64, MVT::Other),
6481 Ops, MVT::i32, MMO);
6483 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6485 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6487 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6488 FP = DAG.getNode(ISD::FP_ROUND, dl,
6489 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6493 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6494 "Unhandled INT_TO_FP type in custom expander!");
6495 // Since we only generate this in 64-bit mode, we can take advantage of
6496 // 64-bit registers. In particular, sign extend the input value into the
6497 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6498 // then lfd it and fcfid it.
6499 MachineFunction &MF = DAG.getMachineFunction();
6500 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6501 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6504 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6507 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6509 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6510 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6512 SDValue Store = DAG.getStore(
6513 DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6514 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6517 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6518 "Expected an i32 store");
6523 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6527 MachineMemOperand *MMO =
6528 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6529 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6530 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6531 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6532 PPCISD::LFIWZX : PPCISD::LFIWAX,
6533 dl, DAG.getVTList(MVT::f64, MVT::Other),
6534 Ops, MVT::i32, MMO);
6536 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6538 assert(Subtarget.isPPC64() &&
6539 "i32->FP without LFIWAX supported only on PPC64");
6541 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6542 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6544 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6547 // STD the extended value into the stack slot.
6548 SDValue Store = DAG.getStore(
6549 DAG.getEntryNode(), dl, Ext64, FIdx,
6550 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6553 // Load the value as a double.
6555 MVT::f64, dl, Store, FIdx,
6556 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6557 false, false, false, 0);
6560 // FCFID it and return it.
6561 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6562 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6563 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6564 DAG.getIntPtrConstant(0, dl));
6568 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6569 SelectionDAG &DAG) const {
6572 The rounding mode is in bits 30:31 of FPSR, and has the following
6579 FLT_ROUNDS, on the other hand, expects the following:
6586 To perform the conversion, we do:
6587 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6590 MachineFunction &MF = DAG.getMachineFunction();
6591 EVT VT = Op.getValueType();
6592 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6594 // Save FP Control Word to register
6596 MVT::f64, // return register
6597 MVT::Glue // unused in this context
6599 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6601 // Save FP register to stack slot
6602 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6603 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6604 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6605 StackSlot, MachinePointerInfo(), false, false,0);
6607 // Load FP Control Word from low 32 bits of stack slot.
6608 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6609 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6610 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6611 false, false, false, 0);
6613 // Transform as necessary
6615 DAG.getNode(ISD::AND, dl, MVT::i32,
6616 CWD, DAG.getConstant(3, dl, MVT::i32));
6618 DAG.getNode(ISD::SRL, dl, MVT::i32,
6619 DAG.getNode(ISD::AND, dl, MVT::i32,
6620 DAG.getNode(ISD::XOR, dl, MVT::i32,
6621 CWD, DAG.getConstant(3, dl, MVT::i32)),
6622 DAG.getConstant(3, dl, MVT::i32)),
6623 DAG.getConstant(1, dl, MVT::i32));
6626 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6628 return DAG.getNode((VT.getSizeInBits() < 16 ?
6629 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6632 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6633 EVT VT = Op.getValueType();
6634 unsigned BitWidth = VT.getSizeInBits();
6636 assert(Op.getNumOperands() == 3 &&
6637 VT == Op.getOperand(1).getValueType() &&
6640 // Expand into a bunch of logical ops. Note that these ops
6641 // depend on the PPC behavior for oversized shift amounts.
6642 SDValue Lo = Op.getOperand(0);
6643 SDValue Hi = Op.getOperand(1);
6644 SDValue Amt = Op.getOperand(2);
6645 EVT AmtVT = Amt.getValueType();
6647 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6648 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6649 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6650 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6651 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6652 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6653 DAG.getConstant(-BitWidth, dl, AmtVT));
6654 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6655 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6656 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6657 SDValue OutOps[] = { OutLo, OutHi };
6658 return DAG.getMergeValues(OutOps, dl);
6661 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6662 EVT VT = Op.getValueType();
6664 unsigned BitWidth = VT.getSizeInBits();
6665 assert(Op.getNumOperands() == 3 &&
6666 VT == Op.getOperand(1).getValueType() &&
6669 // Expand into a bunch of logical ops. Note that these ops
6670 // depend on the PPC behavior for oversized shift amounts.
6671 SDValue Lo = Op.getOperand(0);
6672 SDValue Hi = Op.getOperand(1);
6673 SDValue Amt = Op.getOperand(2);
6674 EVT AmtVT = Amt.getValueType();
6676 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6677 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6678 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6679 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6680 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6681 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6682 DAG.getConstant(-BitWidth, dl, AmtVT));
6683 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6684 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6685 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6686 SDValue OutOps[] = { OutLo, OutHi };
6687 return DAG.getMergeValues(OutOps, dl);
6690 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6692 EVT VT = Op.getValueType();
6693 unsigned BitWidth = VT.getSizeInBits();
6694 assert(Op.getNumOperands() == 3 &&
6695 VT == Op.getOperand(1).getValueType() &&
6698 // Expand into a bunch of logical ops, followed by a select_cc.
6699 SDValue Lo = Op.getOperand(0);
6700 SDValue Hi = Op.getOperand(1);
6701 SDValue Amt = Op.getOperand(2);
6702 EVT AmtVT = Amt.getValueType();
6704 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6705 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6706 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6707 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6708 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6709 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6710 DAG.getConstant(-BitWidth, dl, AmtVT));
6711 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6712 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6713 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6714 Tmp4, Tmp6, ISD::SETLE);
6715 SDValue OutOps[] = { OutLo, OutHi };
6716 return DAG.getMergeValues(OutOps, dl);
6719 //===----------------------------------------------------------------------===//
6720 // Vector related lowering.
6723 /// BuildSplatI - Build a canonical splati of Val with an element size of
6724 /// SplatSize. Cast the result to VT.
6725 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6726 SelectionDAG &DAG, SDLoc dl) {
6727 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6729 static const MVT VTys[] = { // canonical VT to use for each size.
6730 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6733 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6735 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6739 EVT CanonicalVT = VTys[SplatSize-1];
6741 // Build a canonical splat for this value.
6742 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6743 SmallVector<SDValue, 8> Ops;
6744 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6745 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6746 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6749 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6750 /// specified intrinsic ID.
6751 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6752 SelectionDAG &DAG, SDLoc dl,
6753 EVT DestVT = MVT::Other) {
6754 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6755 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6756 DAG.getConstant(IID, dl, MVT::i32), Op);
6759 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6760 /// specified intrinsic ID.
6761 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6762 SelectionDAG &DAG, SDLoc dl,
6763 EVT DestVT = MVT::Other) {
6764 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6765 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6766 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6769 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6770 /// specified intrinsic ID.
6771 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6772 SDValue Op2, SelectionDAG &DAG,
6773 SDLoc dl, EVT DestVT = MVT::Other) {
6774 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6775 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6776 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6779 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6780 /// amount. The result has the specified value type.
6781 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6782 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6783 // Force LHS/RHS to be the right type.
6784 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6785 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6788 for (unsigned i = 0; i != 16; ++i)
6790 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6791 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6794 // If this is a case we can't handle, return null and let the default
6795 // expansion code take care of it. If we CAN select this case, and if it
6796 // selects to a single instruction, return Op. Otherwise, if we can codegen
6797 // this case more efficiently than a constant pool load, lower it to the
6798 // sequence of ops that should be used.
6799 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6800 SelectionDAG &DAG) const {
6802 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6803 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6805 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6806 // We first build an i32 vector, load it into a QPX register,
6807 // then convert it to a floating-point vector and compare it
6808 // to a zero vector to get the boolean result.
6809 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6810 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6811 MachinePointerInfo PtrInfo =
6812 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6813 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6814 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6816 assert(BVN->getNumOperands() == 4 &&
6817 "BUILD_VECTOR for v4i1 does not have 4 operands");
6819 bool IsConst = true;
6820 for (unsigned i = 0; i < 4; ++i) {
6821 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6822 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6830 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6832 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6834 SmallVector<Constant*, 4> CV(4, NegOne);
6835 for (unsigned i = 0; i < 4; ++i) {
6836 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6837 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6838 else if (isNullConstant(BVN->getOperand(i)))
6844 Constant *CP = ConstantVector::get(CV);
6845 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
6846 16 /* alignment */);
6848 SmallVector<SDValue, 2> Ops;
6849 Ops.push_back(DAG.getEntryNode());
6850 Ops.push_back(CPIdx);
6852 SmallVector<EVT, 2> ValueVTs;
6853 ValueVTs.push_back(MVT::v4i1);
6854 ValueVTs.push_back(MVT::Other); // chain
6855 SDVTList VTs = DAG.getVTList(ValueVTs);
6857 return DAG.getMemIntrinsicNode(
6858 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
6859 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
6862 SmallVector<SDValue, 4> Stores;
6863 for (unsigned i = 0; i < 4; ++i) {
6864 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6866 unsigned Offset = 4*i;
6867 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6868 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6870 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6871 if (StoreSize > 4) {
6872 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6873 BVN->getOperand(i), Idx,
6874 PtrInfo.getWithOffset(Offset),
6875 MVT::i32, false, false, 0));
6877 SDValue StoreValue = BVN->getOperand(i);
6879 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6881 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6883 PtrInfo.getWithOffset(Offset),
6889 if (!Stores.empty())
6890 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6892 StoreChain = DAG.getEntryNode();
6894 // Now load from v4i32 into the QPX register; this will extend it to
6895 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6896 // is typed as v4f64 because the QPX register integer states are not
6897 // explicitly represented.
6899 SmallVector<SDValue, 2> Ops;
6900 Ops.push_back(StoreChain);
6901 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6902 Ops.push_back(FIdx);
6904 SmallVector<EVT, 2> ValueVTs;
6905 ValueVTs.push_back(MVT::v4f64);
6906 ValueVTs.push_back(MVT::Other); // chain
6907 SDVTList VTs = DAG.getVTList(ValueVTs);
6909 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6910 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6911 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6912 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6915 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6916 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6917 FPZeros, FPZeros, FPZeros, FPZeros);
6919 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6922 // All other QPX vectors are handled by generic code.
6923 if (Subtarget.hasQPX())
6926 // Check if this is a splat of a constant value.
6927 APInt APSplatBits, APSplatUndef;
6928 unsigned SplatBitSize;
6930 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6931 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6935 unsigned SplatBits = APSplatBits.getZExtValue();
6936 unsigned SplatUndef = APSplatUndef.getZExtValue();
6937 unsigned SplatSize = SplatBitSize / 8;
6939 // First, handle single instruction cases.
6942 if (SplatBits == 0) {
6943 // Canonicalize all zero vectors to be v4i32.
6944 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6945 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6946 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6947 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6952 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6953 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6955 if (SextVal >= -16 && SextVal <= 15)
6956 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6958 // Two instruction sequences.
6960 // If this value is in the range [-32,30] and is even, use:
6961 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6962 // If this value is in the range [17,31] and is odd, use:
6963 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6964 // If this value is in the range [-31,-17] and is odd, use:
6965 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6966 // Note the last two are three-instruction sequences.
6967 if (SextVal >= -32 && SextVal <= 31) {
6968 // To avoid having these optimizations undone by constant folding,
6969 // we convert to a pseudo that will be expanded later into one of
6971 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6972 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6973 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6974 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6975 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6976 if (VT == Op.getValueType())
6979 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6982 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6983 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6985 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6986 // Make -1 and vspltisw -1:
6987 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6989 // Make the VSLW intrinsic, computing 0x8000_0000.
6990 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6993 // xor by OnesV to invert it.
6994 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6995 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6998 // Check to see if this is a wide variety of vsplti*, binop self cases.
6999 static const signed char SplatCsts[] = {
7000 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
7001 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
7004 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
7005 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
7006 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
7007 int i = SplatCsts[idx];
7009 // Figure out what shift amount will be used by altivec if shifted by i in
7011 unsigned TypeShiftAmt = i & (SplatBitSize-1);
7013 // vsplti + shl self.
7014 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
7015 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7016 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7017 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
7018 Intrinsic::ppc_altivec_vslw
7020 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7021 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7024 // vsplti + srl self.
7025 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7026 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7027 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7028 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
7029 Intrinsic::ppc_altivec_vsrw
7031 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7032 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7035 // vsplti + sra self.
7036 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7037 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7038 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7039 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
7040 Intrinsic::ppc_altivec_vsraw
7042 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7043 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7046 // vsplti + rol self.
7047 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
7048 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
7049 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7050 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7051 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
7052 Intrinsic::ppc_altivec_vrlw
7054 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7055 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7058 // t = vsplti c, result = vsldoi t, t, 1
7059 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
7060 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7061 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1;
7062 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7064 // t = vsplti c, result = vsldoi t, t, 2
7065 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
7066 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7067 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2;
7068 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7070 // t = vsplti c, result = vsldoi t, t, 3
7071 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
7072 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7073 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3;
7074 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7081 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7082 /// the specified operations to build the shuffle.
7083 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7084 SDValue RHS, SelectionDAG &DAG,
7086 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7087 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7088 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7091 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7103 if (OpNum == OP_COPY) {
7104 if (LHSID == (1*9+2)*9+3) return LHS;
7105 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7109 SDValue OpLHS, OpRHS;
7110 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7111 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7115 default: llvm_unreachable("Unknown i32 permute!");
7117 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7118 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7119 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7120 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7123 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7124 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7125 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7126 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7129 for (unsigned i = 0; i != 16; ++i)
7130 ShufIdxs[i] = (i&3)+0;
7133 for (unsigned i = 0; i != 16; ++i)
7134 ShufIdxs[i] = (i&3)+4;
7137 for (unsigned i = 0; i != 16; ++i)
7138 ShufIdxs[i] = (i&3)+8;
7141 for (unsigned i = 0; i != 16; ++i)
7142 ShufIdxs[i] = (i&3)+12;
7145 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7147 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7149 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7151 EVT VT = OpLHS.getValueType();
7152 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7153 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7154 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7155 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7158 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7159 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7160 /// return the code it can be lowered into. Worst case, it can always be
7161 /// lowered into a vperm.
7162 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7163 SelectionDAG &DAG) const {
7165 SDValue V1 = Op.getOperand(0);
7166 SDValue V2 = Op.getOperand(1);
7167 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7168 EVT VT = Op.getValueType();
7169 bool isLittleEndian = Subtarget.isLittleEndian();
7171 if (Subtarget.hasQPX()) {
7172 if (VT.getVectorNumElements() != 4)
7175 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7177 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7178 if (AlignIdx != -1) {
7179 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7180 DAG.getConstant(AlignIdx, dl, MVT::i32));
7181 } else if (SVOp->isSplat()) {
7182 int SplatIdx = SVOp->getSplatIndex();
7183 if (SplatIdx >= 4) {
7188 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7191 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7192 DAG.getConstant(SplatIdx, dl, MVT::i32));
7195 // Lower this into a qvgpci/qvfperm pair.
7197 // Compute the qvgpci literal
7199 for (unsigned i = 0; i < 4; ++i) {
7200 int m = SVOp->getMaskElt(i);
7201 unsigned mm = m >= 0 ? (unsigned) m : i;
7202 idx |= mm << (3-i)*3;
7205 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7206 DAG.getConstant(idx, dl, MVT::i32));
7207 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7210 // Cases that are handled by instructions that take permute immediates
7211 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7212 // selected by the instruction selector.
7213 if (V2.getOpcode() == ISD::UNDEF) {
7214 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7215 PPC::isSplatShuffleMask(SVOp, 2) ||
7216 PPC::isSplatShuffleMask(SVOp, 4) ||
7217 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7218 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7219 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7220 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7221 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7222 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7223 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7224 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7225 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7226 (Subtarget.hasP8Altivec() && (
7227 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7228 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7229 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
7234 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7235 // and produce a fixed permutation. If any of these match, do not lower to
7237 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7238 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7239 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7240 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7241 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7242 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7243 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7244 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7245 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7246 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7247 (Subtarget.hasP8Altivec() && (
7248 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7249 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7250 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
7253 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7254 // perfect shuffle table to emit an optimal matching sequence.
7255 ArrayRef<int> PermMask = SVOp->getMask();
7257 unsigned PFIndexes[4];
7258 bool isFourElementShuffle = true;
7259 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7260 unsigned EltNo = 8; // Start out undef.
7261 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7262 if (PermMask[i*4+j] < 0)
7263 continue; // Undef, ignore it.
7265 unsigned ByteSource = PermMask[i*4+j];
7266 if ((ByteSource & 3) != j) {
7267 isFourElementShuffle = false;
7272 EltNo = ByteSource/4;
7273 } else if (EltNo != ByteSource/4) {
7274 isFourElementShuffle = false;
7278 PFIndexes[i] = EltNo;
7281 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7282 // perfect shuffle vector to determine if it is cost effective to do this as
7283 // discrete instructions, or whether we should use a vperm.
7284 // For now, we skip this for little endian until such time as we have a
7285 // little-endian perfect shuffle table.
7286 if (isFourElementShuffle && !isLittleEndian) {
7287 // Compute the index in the perfect shuffle table.
7288 unsigned PFTableIndex =
7289 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7291 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7292 unsigned Cost = (PFEntry >> 30);
7294 // Determining when to avoid vperm is tricky. Many things affect the cost
7295 // of vperm, particularly how many times the perm mask needs to be computed.
7296 // For example, if the perm mask can be hoisted out of a loop or is already
7297 // used (perhaps because there are multiple permutes with the same shuffle
7298 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7299 // the loop requires an extra register.
7301 // As a compromise, we only emit discrete instructions if the shuffle can be
7302 // generated in 3 or fewer operations. When we have loop information
7303 // available, if this block is within a loop, we should avoid using vperm
7304 // for 3-operation perms and use a constant pool load instead.
7306 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7309 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7310 // vector that will get spilled to the constant pool.
7311 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7313 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7314 // that it is in input element units, not in bytes. Convert now.
7316 // For little endian, the order of the input vectors is reversed, and
7317 // the permutation mask is complemented with respect to 31. This is
7318 // necessary to produce proper semantics with the big-endian-biased vperm
7320 EVT EltVT = V1.getValueType().getVectorElementType();
7321 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7323 SmallVector<SDValue, 16> ResultMask;
7324 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7325 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7327 for (unsigned j = 0; j != BytesPerElement; ++j)
7329 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7332 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7336 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7339 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7342 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7346 /// getVectorCompareInfo - Given an intrinsic, return false if it is not a
7347 /// vector comparison. If it is, return true and fill in Opc/isDot with
7348 /// information about the intrinsic.
7349 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
7350 bool &isDot, const PPCSubtarget &Subtarget) {
7351 unsigned IntrinsicID =
7352 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7355 switch (IntrinsicID) {
7356 default: return false;
7357 // Comparison predicates.
7358 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7359 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7360 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7361 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7362 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7363 case Intrinsic::ppc_altivec_vcmpequd_p:
7364 if (Subtarget.hasP8Altivec()) {
7371 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7372 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7373 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7374 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7375 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7376 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7377 if (Subtarget.hasP8Altivec()) {
7384 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7385 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7386 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7387 case Intrinsic::ppc_altivec_vcmpgtud_p:
7388 if (Subtarget.hasP8Altivec()) {
7395 // VSX predicate comparisons use the same infrastructure
7396 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
7397 case Intrinsic::ppc_vsx_xvcmpgedp_p:
7398 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
7399 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
7400 case Intrinsic::ppc_vsx_xvcmpgesp_p:
7401 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
7402 if (Subtarget.hasVSX()) {
7403 switch (IntrinsicID) {
7404 case Intrinsic::ppc_vsx_xvcmpeqdp_p: CompareOpc = 99; break;
7405 case Intrinsic::ppc_vsx_xvcmpgedp_p: CompareOpc = 115; break;
7406 case Intrinsic::ppc_vsx_xvcmpgtdp_p: CompareOpc = 107; break;
7407 case Intrinsic::ppc_vsx_xvcmpeqsp_p: CompareOpc = 67; break;
7408 case Intrinsic::ppc_vsx_xvcmpgesp_p: CompareOpc = 83; break;
7409 case Intrinsic::ppc_vsx_xvcmpgtsp_p: CompareOpc = 75; break;
7418 // Normal Comparisons.
7419 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7420 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7421 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7422 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7423 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7424 case Intrinsic::ppc_altivec_vcmpequd:
7425 if (Subtarget.hasP8Altivec()) {
7432 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7433 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7434 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7435 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7436 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7437 case Intrinsic::ppc_altivec_vcmpgtsd:
7438 if (Subtarget.hasP8Altivec()) {
7445 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7446 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7447 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7448 case Intrinsic::ppc_altivec_vcmpgtud:
7449 if (Subtarget.hasP8Altivec()) {
7460 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7461 /// lower, do it, otherwise return null.
7462 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7463 SelectionDAG &DAG) const {
7464 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7465 // opcode number of the comparison.
7469 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget))
7470 return SDValue(); // Don't custom lower most intrinsics.
7472 // If this is a non-dot comparison, make the VCMP node and we are done.
7474 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7475 Op.getOperand(1), Op.getOperand(2),
7476 DAG.getConstant(CompareOpc, dl, MVT::i32));
7477 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7480 // Create the PPCISD altivec 'dot' comparison node.
7482 Op.getOperand(2), // LHS
7483 Op.getOperand(3), // RHS
7484 DAG.getConstant(CompareOpc, dl, MVT::i32)
7486 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7487 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7489 // Now that we have the comparison, emit a copy from the CR to a GPR.
7490 // This is flagged to the above dot comparison.
7491 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7492 DAG.getRegister(PPC::CR6, MVT::i32),
7493 CompNode.getValue(1));
7495 // Unpack the result based on how the target uses it.
7496 unsigned BitNo; // Bit # of CR6.
7497 bool InvertBit; // Invert result?
7498 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7499 default: // Can't happen, don't crash on invalid number though.
7500 case 0: // Return the value of the EQ bit of CR6.
7501 BitNo = 0; InvertBit = false;
7503 case 1: // Return the inverted value of the EQ bit of CR6.
7504 BitNo = 0; InvertBit = true;
7506 case 2: // Return the value of the LT bit of CR6.
7507 BitNo = 2; InvertBit = false;
7509 case 3: // Return the inverted value of the LT bit of CR6.
7510 BitNo = 2; InvertBit = true;
7514 // Shift the bit into the low position.
7515 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7516 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7518 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7519 DAG.getConstant(1, dl, MVT::i32));
7521 // If we are supposed to, toggle the bit.
7523 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7524 DAG.getConstant(1, dl, MVT::i32));
7528 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7529 SelectionDAG &DAG) const {
7531 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7532 // instructions), but for smaller types, we need to first extend up to v2i32
7533 // before doing going farther.
7534 if (Op.getValueType() == MVT::v2i64) {
7535 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7536 if (ExtVT != MVT::v2i32) {
7537 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7538 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7539 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7540 ExtVT.getVectorElementType(), 4)));
7541 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7542 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7543 DAG.getValueType(MVT::v2i32));
7552 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7553 SelectionDAG &DAG) const {
7555 // Create a stack slot that is 16-byte aligned.
7556 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7557 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7558 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7559 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7561 // Store the input value into Value#0 of the stack slot.
7562 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7563 Op.getOperand(0), FIdx, MachinePointerInfo(),
7566 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7567 false, false, false, 0);
7570 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7571 SelectionDAG &DAG) const {
7573 SDNode *N = Op.getNode();
7575 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7576 "Unknown extract_vector_elt type");
7578 SDValue Value = N->getOperand(0);
7580 // The first part of this is like the store lowering except that we don't
7581 // need to track the chain.
7583 // The values are now known to be -1 (false) or 1 (true). To convert this
7584 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7585 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7586 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7588 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7589 // understand how to form the extending load.
7590 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7591 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7592 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7594 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7596 // Now convert to an integer and store.
7597 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7598 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7601 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7602 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7603 MachinePointerInfo PtrInfo =
7604 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7605 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7606 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7608 SDValue StoreChain = DAG.getEntryNode();
7609 SmallVector<SDValue, 2> Ops;
7610 Ops.push_back(StoreChain);
7611 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7612 Ops.push_back(Value);
7613 Ops.push_back(FIdx);
7615 SmallVector<EVT, 2> ValueVTs;
7616 ValueVTs.push_back(MVT::Other); // chain
7617 SDVTList VTs = DAG.getVTList(ValueVTs);
7619 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7620 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7622 // Extract the value requested.
7623 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7624 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7625 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7627 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7628 PtrInfo.getWithOffset(Offset),
7629 false, false, false, 0);
7631 if (!Subtarget.useCRBits())
7634 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7637 /// Lowering for QPX v4i1 loads
7638 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7639 SelectionDAG &DAG) const {
7641 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7642 SDValue LoadChain = LN->getChain();
7643 SDValue BasePtr = LN->getBasePtr();
7645 if (Op.getValueType() == MVT::v4f64 ||
7646 Op.getValueType() == MVT::v4f32) {
7647 EVT MemVT = LN->getMemoryVT();
7648 unsigned Alignment = LN->getAlignment();
7650 // If this load is properly aligned, then it is legal.
7651 if (Alignment >= MemVT.getStoreSize())
7654 EVT ScalarVT = Op.getValueType().getScalarType(),
7655 ScalarMemVT = MemVT.getScalarType();
7656 unsigned Stride = ScalarMemVT.getStoreSize();
7658 SmallVector<SDValue, 8> Vals, LoadChains;
7659 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7661 if (ScalarVT != ScalarMemVT)
7663 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7665 LN->getPointerInfo().getWithOffset(Idx*Stride),
7666 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7667 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7671 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7672 LN->getPointerInfo().getWithOffset(Idx*Stride),
7673 LN->isVolatile(), LN->isNonTemporal(),
7674 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7677 if (Idx == 0 && LN->isIndexed()) {
7678 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7679 "Unknown addressing mode on vector load");
7680 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7681 LN->getAddressingMode());
7684 Vals.push_back(Load);
7685 LoadChains.push_back(Load.getValue(1));
7687 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7688 DAG.getConstant(Stride, dl,
7689 BasePtr.getValueType()));
7692 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7693 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7694 Op.getValueType(), Vals);
7696 if (LN->isIndexed()) {
7697 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7698 return DAG.getMergeValues(RetOps, dl);
7701 SDValue RetOps[] = { Value, TF };
7702 return DAG.getMergeValues(RetOps, dl);
7705 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7706 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7708 // To lower v4i1 from a byte array, we load the byte elements of the
7709 // vector and then reuse the BUILD_VECTOR logic.
7711 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7712 for (unsigned i = 0; i < 4; ++i) {
7713 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7714 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7716 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7717 dl, MVT::i32, LoadChain, Idx,
7718 LN->getPointerInfo().getWithOffset(i),
7719 MVT::i8 /* memory type */,
7720 LN->isVolatile(), LN->isNonTemporal(),
7722 1 /* alignment */, LN->getAAInfo()));
7723 VectElmtChains.push_back(VectElmts[i].getValue(1));
7726 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7727 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7729 SDValue RVals[] = { Value, LoadChain };
7730 return DAG.getMergeValues(RVals, dl);
7733 /// Lowering for QPX v4i1 stores
7734 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7735 SelectionDAG &DAG) const {
7737 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7738 SDValue StoreChain = SN->getChain();
7739 SDValue BasePtr = SN->getBasePtr();
7740 SDValue Value = SN->getValue();
7742 if (Value.getValueType() == MVT::v4f64 ||
7743 Value.getValueType() == MVT::v4f32) {
7744 EVT MemVT = SN->getMemoryVT();
7745 unsigned Alignment = SN->getAlignment();
7747 // If this store is properly aligned, then it is legal.
7748 if (Alignment >= MemVT.getStoreSize())
7751 EVT ScalarVT = Value.getValueType().getScalarType(),
7752 ScalarMemVT = MemVT.getScalarType();
7753 unsigned Stride = ScalarMemVT.getStoreSize();
7755 SmallVector<SDValue, 8> Stores;
7756 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7757 SDValue Ex = DAG.getNode(
7758 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7759 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
7761 if (ScalarVT != ScalarMemVT)
7763 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7764 SN->getPointerInfo().getWithOffset(Idx*Stride),
7765 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7766 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7769 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7770 SN->getPointerInfo().getWithOffset(Idx*Stride),
7771 SN->isVolatile(), SN->isNonTemporal(),
7772 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7774 if (Idx == 0 && SN->isIndexed()) {
7775 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7776 "Unknown addressing mode on vector store");
7777 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7778 SN->getAddressingMode());
7781 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7782 DAG.getConstant(Stride, dl,
7783 BasePtr.getValueType()));
7784 Stores.push_back(Store);
7787 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7789 if (SN->isIndexed()) {
7790 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7791 return DAG.getMergeValues(RetOps, dl);
7797 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7798 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7800 // The values are now known to be -1 (false) or 1 (true). To convert this
7801 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7802 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7803 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7805 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7806 // understand how to form the extending load.
7807 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7808 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7809 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7811 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7813 // Now convert to an integer and store.
7814 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7815 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7818 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7819 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7820 MachinePointerInfo PtrInfo =
7821 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7822 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7823 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7825 SmallVector<SDValue, 2> Ops;
7826 Ops.push_back(StoreChain);
7827 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7828 Ops.push_back(Value);
7829 Ops.push_back(FIdx);
7831 SmallVector<EVT, 2> ValueVTs;
7832 ValueVTs.push_back(MVT::Other); // chain
7833 SDVTList VTs = DAG.getVTList(ValueVTs);
7835 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7836 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7838 // Move data into the byte array.
7839 SmallVector<SDValue, 4> Loads, LoadChains;
7840 for (unsigned i = 0; i < 4; ++i) {
7841 unsigned Offset = 4*i;
7842 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7843 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7845 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7846 PtrInfo.getWithOffset(Offset),
7847 false, false, false, 0));
7848 LoadChains.push_back(Loads[i].getValue(1));
7851 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7853 SmallVector<SDValue, 4> Stores;
7854 for (unsigned i = 0; i < 4; ++i) {
7855 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7856 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7858 Stores.push_back(DAG.getTruncStore(
7859 StoreChain, dl, Loads[i], Idx, SN->getPointerInfo().getWithOffset(i),
7860 MVT::i8 /* memory type */, SN->isNonTemporal(), SN->isVolatile(),
7861 1 /* alignment */, SN->getAAInfo()));
7864 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7869 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7871 if (Op.getValueType() == MVT::v4i32) {
7872 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7874 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7875 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7877 SDValue RHSSwap = // = vrlw RHS, 16
7878 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7880 // Shrinkify inputs to v8i16.
7881 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7882 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7883 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7885 // Low parts multiplied together, generating 32-bit results (we ignore the
7887 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7888 LHS, RHS, DAG, dl, MVT::v4i32);
7890 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7891 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7892 // Shift the high parts up 16 bits.
7893 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7895 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7896 } else if (Op.getValueType() == MVT::v8i16) {
7897 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7899 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7901 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7902 LHS, RHS, Zero, DAG, dl);
7903 } else if (Op.getValueType() == MVT::v16i8) {
7904 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7905 bool isLittleEndian = Subtarget.isLittleEndian();
7907 // Multiply the even 8-bit parts, producing 16-bit sums.
7908 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7909 LHS, RHS, DAG, dl, MVT::v8i16);
7910 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7912 // Multiply the odd 8-bit parts, producing 16-bit sums.
7913 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7914 LHS, RHS, DAG, dl, MVT::v8i16);
7915 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7917 // Merge the results together. Because vmuleub and vmuloub are
7918 // instructions with a big-endian bias, we must reverse the
7919 // element numbering and reverse the meaning of "odd" and "even"
7920 // when generating little endian code.
7922 for (unsigned i = 0; i != 8; ++i) {
7923 if (isLittleEndian) {
7925 Ops[i*2+1] = 2*i+16;
7928 Ops[i*2+1] = 2*i+1+16;
7932 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7934 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7936 llvm_unreachable("Unknown mul to lower!");
7940 /// LowerOperation - Provide custom lowering hooks for some operations.
7942 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7943 switch (Op.getOpcode()) {
7944 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7945 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7946 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7947 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7948 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7949 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7950 case ISD::SETCC: return LowerSETCC(Op, DAG);
7951 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7952 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7954 return LowerVASTART(Op, DAG, Subtarget);
7957 return LowerVAARG(Op, DAG, Subtarget);
7960 return LowerVACOPY(Op, DAG, Subtarget);
7962 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7963 case ISD::DYNAMIC_STACKALLOC:
7964 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7965 case ISD::GET_DYNAMIC_AREA_OFFSET: return LowerGET_DYNAMIC_AREA_OFFSET(Op, DAG, Subtarget);
7967 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7968 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7970 case ISD::LOAD: return LowerLOAD(Op, DAG);
7971 case ISD::STORE: return LowerSTORE(Op, DAG);
7972 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7973 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7974 case ISD::FP_TO_UINT:
7975 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7977 case ISD::UINT_TO_FP:
7978 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7979 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7981 // Lower 64-bit shifts.
7982 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7983 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7984 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7986 // Vector-related lowering.
7987 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7988 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7989 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7990 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7991 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7992 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7993 case ISD::MUL: return LowerMUL(Op, DAG);
7995 // For counter-based loop handling.
7996 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7998 // Frame & Return address.
7999 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8000 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8004 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
8005 SmallVectorImpl<SDValue>&Results,
8006 SelectionDAG &DAG) const {
8008 switch (N->getOpcode()) {
8010 llvm_unreachable("Do not know how to custom type legalize this operation!");
8011 case ISD::READCYCLECOUNTER: {
8012 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8013 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
8015 Results.push_back(RTB);
8016 Results.push_back(RTB.getValue(1));
8017 Results.push_back(RTB.getValue(2));
8020 case ISD::INTRINSIC_W_CHAIN: {
8021 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
8022 Intrinsic::ppc_is_decremented_ctr_nonzero)
8025 assert(N->getValueType(0) == MVT::i1 &&
8026 "Unexpected result type for CTR decrement intrinsic");
8027 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
8028 N->getValueType(0));
8029 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
8030 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
8033 Results.push_back(NewInt);
8034 Results.push_back(NewInt.getValue(1));
8038 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
8041 EVT VT = N->getValueType(0);
8043 if (VT == MVT::i64) {
8044 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
8046 Results.push_back(NewNode);
8047 Results.push_back(NewNode.getValue(1));
8051 case ISD::FP_ROUND_INREG: {
8052 assert(N->getValueType(0) == MVT::ppcf128);
8053 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
8054 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8055 MVT::f64, N->getOperand(0),
8056 DAG.getIntPtrConstant(0, dl));
8057 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8058 MVT::f64, N->getOperand(0),
8059 DAG.getIntPtrConstant(1, dl));
8061 // Add the two halves of the long double in round-to-zero mode.
8062 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
8064 // We know the low half is about to be thrown away, so just use something
8066 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
8070 case ISD::FP_TO_SINT:
8071 case ISD::FP_TO_UINT:
8072 // LowerFP_TO_INT() can only handle f32 and f64.
8073 if (N->getOperand(0).getValueType() == MVT::ppcf128)
8075 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
8080 //===----------------------------------------------------------------------===//
8081 // Other Lowering Code
8082 //===----------------------------------------------------------------------===//
8084 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
8085 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8086 Function *Func = Intrinsic::getDeclaration(M, Id);
8087 return Builder.CreateCall(Func, {});
8090 // The mappings for emitLeading/TrailingFence is taken from
8091 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
8092 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
8093 AtomicOrdering Ord, bool IsStore,
8094 bool IsLoad) const {
8095 if (Ord == SequentiallyConsistent)
8096 return callIntrinsic(Builder, Intrinsic::ppc_sync);
8097 if (isAtLeastRelease(Ord))
8098 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8102 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
8103 AtomicOrdering Ord, bool IsStore,
8104 bool IsLoad) const {
8105 if (IsLoad && isAtLeastAcquire(Ord))
8106 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8107 // FIXME: this is too conservative, a dependent branch + isync is enough.
8108 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8109 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8110 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8115 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8116 unsigned AtomicSize,
8117 unsigned BinOpcode) const {
8118 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8119 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8121 auto LoadMnemonic = PPC::LDARX;
8122 auto StoreMnemonic = PPC::STDCX;
8123 switch (AtomicSize) {
8125 llvm_unreachable("Unexpected size of atomic entity");
8127 LoadMnemonic = PPC::LBARX;
8128 StoreMnemonic = PPC::STBCX;
8129 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8132 LoadMnemonic = PPC::LHARX;
8133 StoreMnemonic = PPC::STHCX;
8134 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8137 LoadMnemonic = PPC::LWARX;
8138 StoreMnemonic = PPC::STWCX;
8141 LoadMnemonic = PPC::LDARX;
8142 StoreMnemonic = PPC::STDCX;
8146 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8147 MachineFunction *F = BB->getParent();
8148 MachineFunction::iterator It = ++BB->getIterator();
8150 unsigned dest = MI->getOperand(0).getReg();
8151 unsigned ptrA = MI->getOperand(1).getReg();
8152 unsigned ptrB = MI->getOperand(2).getReg();
8153 unsigned incr = MI->getOperand(3).getReg();
8154 DebugLoc dl = MI->getDebugLoc();
8156 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8157 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8158 F->insert(It, loopMBB);
8159 F->insert(It, exitMBB);
8160 exitMBB->splice(exitMBB->begin(), BB,
8161 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8162 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8164 MachineRegisterInfo &RegInfo = F->getRegInfo();
8165 unsigned TmpReg = (!BinOpcode) ? incr :
8166 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8167 : &PPC::GPRCRegClass);
8171 // fallthrough --> loopMBB
8172 BB->addSuccessor(loopMBB);
8175 // l[wd]arx dest, ptr
8176 // add r0, dest, incr
8177 // st[wd]cx. r0, ptr
8179 // fallthrough --> exitMBB
8181 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8182 .addReg(ptrA).addReg(ptrB);
8184 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8185 BuildMI(BB, dl, TII->get(StoreMnemonic))
8186 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8187 BuildMI(BB, dl, TII->get(PPC::BCC))
8188 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8189 BB->addSuccessor(loopMBB);
8190 BB->addSuccessor(exitMBB);
8199 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8200 MachineBasicBlock *BB,
8201 bool is8bit, // operation
8202 unsigned BinOpcode) const {
8203 // If we support part-word atomic mnemonics, just use them
8204 if (Subtarget.hasPartwordAtomics())
8205 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8207 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8208 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8209 // In 64 bit mode we have to use 64 bits for addresses, even though the
8210 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8211 // registers without caring whether they're 32 or 64, but here we're
8212 // doing actual arithmetic on the addresses.
8213 bool is64bit = Subtarget.isPPC64();
8214 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8216 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8217 MachineFunction *F = BB->getParent();
8218 MachineFunction::iterator It = ++BB->getIterator();
8220 unsigned dest = MI->getOperand(0).getReg();
8221 unsigned ptrA = MI->getOperand(1).getReg();
8222 unsigned ptrB = MI->getOperand(2).getReg();
8223 unsigned incr = MI->getOperand(3).getReg();
8224 DebugLoc dl = MI->getDebugLoc();
8226 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8227 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8228 F->insert(It, loopMBB);
8229 F->insert(It, exitMBB);
8230 exitMBB->splice(exitMBB->begin(), BB,
8231 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8232 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8234 MachineRegisterInfo &RegInfo = F->getRegInfo();
8235 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8236 : &PPC::GPRCRegClass;
8237 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8238 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8239 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8240 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8241 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8242 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8243 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8244 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8245 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8246 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8247 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8249 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8253 // fallthrough --> loopMBB
8254 BB->addSuccessor(loopMBB);
8256 // The 4-byte load must be aligned, while a char or short may be
8257 // anywhere in the word. Hence all this nasty bookkeeping code.
8258 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8259 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8260 // xori shift, shift1, 24 [16]
8261 // rlwinm ptr, ptr1, 0, 0, 29
8262 // slw incr2, incr, shift
8263 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8264 // slw mask, mask2, shift
8266 // lwarx tmpDest, ptr
8267 // add tmp, tmpDest, incr2
8268 // andc tmp2, tmpDest, mask
8269 // and tmp3, tmp, mask
8270 // or tmp4, tmp3, tmp2
8273 // fallthrough --> exitMBB
8274 // srw dest, tmpDest, shift
8275 if (ptrA != ZeroReg) {
8276 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8277 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8278 .addReg(ptrA).addReg(ptrB);
8282 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8283 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8284 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8285 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8287 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8288 .addReg(Ptr1Reg).addImm(0).addImm(61);
8290 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8291 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8292 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8293 .addReg(incr).addReg(ShiftReg);
8295 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8297 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8298 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8300 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8301 .addReg(Mask2Reg).addReg(ShiftReg);
8304 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8305 .addReg(ZeroReg).addReg(PtrReg);
8307 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8308 .addReg(Incr2Reg).addReg(TmpDestReg);
8309 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8310 .addReg(TmpDestReg).addReg(MaskReg);
8311 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8312 .addReg(TmpReg).addReg(MaskReg);
8313 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8314 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8315 BuildMI(BB, dl, TII->get(PPC::STWCX))
8316 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8317 BuildMI(BB, dl, TII->get(PPC::BCC))
8318 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8319 BB->addSuccessor(loopMBB);
8320 BB->addSuccessor(exitMBB);
8325 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8330 llvm::MachineBasicBlock*
8331 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8332 MachineBasicBlock *MBB) const {
8333 DebugLoc DL = MI->getDebugLoc();
8334 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8336 MachineFunction *MF = MBB->getParent();
8337 MachineRegisterInfo &MRI = MF->getRegInfo();
8339 const BasicBlock *BB = MBB->getBasicBlock();
8340 MachineFunction::iterator I = ++MBB->getIterator();
8343 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8344 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8346 unsigned DstReg = MI->getOperand(0).getReg();
8347 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8348 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8349 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8350 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8352 MVT PVT = getPointerTy(MF->getDataLayout());
8353 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8354 "Invalid Pointer Size!");
8355 // For v = setjmp(buf), we generate
8358 // SjLjSetup mainMBB
8364 // buf[LabelOffset] = LR
8368 // v = phi(main, restore)
8371 MachineBasicBlock *thisMBB = MBB;
8372 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8373 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8374 MF->insert(I, mainMBB);
8375 MF->insert(I, sinkMBB);
8377 MachineInstrBuilder MIB;
8379 // Transfer the remainder of BB and its successor edges to sinkMBB.
8380 sinkMBB->splice(sinkMBB->begin(), MBB,
8381 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8382 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8384 // Note that the structure of the jmp_buf used here is not compatible
8385 // with that used by libc, and is not designed to be. Specifically, it
8386 // stores only those 'reserved' registers that LLVM does not otherwise
8387 // understand how to spill. Also, by convention, by the time this
8388 // intrinsic is called, Clang has already stored the frame address in the
8389 // first slot of the buffer and stack address in the third. Following the
8390 // X86 target code, we'll store the jump address in the second slot. We also
8391 // need to save the TOC pointer (R2) to handle jumps between shared
8392 // libraries, and that will be stored in the fourth slot. The thread
8393 // identifier (R13) is not affected.
8396 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8397 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8398 const int64_t BPOffset = 4 * PVT.getStoreSize();
8400 // Prepare IP either in reg.
8401 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8402 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8403 unsigned BufReg = MI->getOperand(1).getReg();
8405 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8406 setUsesTOCBasePtr(*MBB->getParent());
8407 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8411 MIB.setMemRefs(MMOBegin, MMOEnd);
8414 // Naked functions never have a base pointer, and so we use r1. For all
8415 // other functions, this decision must be delayed until during PEI.
8417 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8418 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8420 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8422 MIB = BuildMI(*thisMBB, MI, DL,
8423 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8427 MIB.setMemRefs(MMOBegin, MMOEnd);
8430 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8431 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8432 MIB.addRegMask(TRI->getNoPreservedMask());
8434 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8436 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8438 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8440 thisMBB->addSuccessor(mainMBB, BranchProbability::getZero());
8441 thisMBB->addSuccessor(sinkMBB, BranchProbability::getOne());
8446 BuildMI(mainMBB, DL,
8447 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8450 if (Subtarget.isPPC64()) {
8451 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8453 .addImm(LabelOffset)
8456 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8458 .addImm(LabelOffset)
8462 MIB.setMemRefs(MMOBegin, MMOEnd);
8464 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8465 mainMBB->addSuccessor(sinkMBB);
8468 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8469 TII->get(PPC::PHI), DstReg)
8470 .addReg(mainDstReg).addMBB(mainMBB)
8471 .addReg(restoreDstReg).addMBB(thisMBB);
8473 MI->eraseFromParent();
8478 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8479 MachineBasicBlock *MBB) const {
8480 DebugLoc DL = MI->getDebugLoc();
8481 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8483 MachineFunction *MF = MBB->getParent();
8484 MachineRegisterInfo &MRI = MF->getRegInfo();
8487 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8488 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8490 MVT PVT = getPointerTy(MF->getDataLayout());
8491 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8492 "Invalid Pointer Size!");
8494 const TargetRegisterClass *RC =
8495 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8496 unsigned Tmp = MRI.createVirtualRegister(RC);
8497 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8498 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8499 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8503 : (Subtarget.isSVR4ABI() &&
8504 MF->getTarget().getRelocationModel() == Reloc::PIC_
8508 MachineInstrBuilder MIB;
8510 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8511 const int64_t SPOffset = 2 * PVT.getStoreSize();
8512 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8513 const int64_t BPOffset = 4 * PVT.getStoreSize();
8515 unsigned BufReg = MI->getOperand(0).getReg();
8517 // Reload FP (the jumped-to function may not have had a
8518 // frame pointer, and if so, then its r31 will be restored
8520 if (PVT == MVT::i64) {
8521 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8525 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8529 MIB.setMemRefs(MMOBegin, MMOEnd);
8532 if (PVT == MVT::i64) {
8533 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8534 .addImm(LabelOffset)
8537 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8538 .addImm(LabelOffset)
8541 MIB.setMemRefs(MMOBegin, MMOEnd);
8544 if (PVT == MVT::i64) {
8545 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8549 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8553 MIB.setMemRefs(MMOBegin, MMOEnd);
8556 if (PVT == MVT::i64) {
8557 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8561 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8565 MIB.setMemRefs(MMOBegin, MMOEnd);
8568 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8569 setUsesTOCBasePtr(*MBB->getParent());
8570 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8574 MIB.setMemRefs(MMOBegin, MMOEnd);
8578 BuildMI(*MBB, MI, DL,
8579 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8580 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8582 MI->eraseFromParent();
8587 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8588 MachineBasicBlock *BB) const {
8589 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8590 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8591 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8592 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8593 // Call lowering should have added an r2 operand to indicate a dependence
8594 // on the TOC base pointer value. It can't however, because there is no
8595 // way to mark the dependence as implicit there, and so the stackmap code
8596 // will confuse it with a regular operand. Instead, add the dependence
8598 setUsesTOCBasePtr(*BB->getParent());
8599 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8602 return emitPatchPoint(MI, BB);
8605 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8606 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8607 return emitEHSjLjSetJmp(MI, BB);
8608 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8609 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8610 return emitEHSjLjLongJmp(MI, BB);
8613 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8615 // To "insert" these instructions we actually have to insert their
8616 // control-flow patterns.
8617 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8618 MachineFunction::iterator It = ++BB->getIterator();
8620 MachineFunction *F = BB->getParent();
8622 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8623 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8624 MI->getOpcode() == PPC::SELECT_I4 ||
8625 MI->getOpcode() == PPC::SELECT_I8)) {
8626 SmallVector<MachineOperand, 2> Cond;
8627 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8628 MI->getOpcode() == PPC::SELECT_CC_I8)
8629 Cond.push_back(MI->getOperand(4));
8631 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8632 Cond.push_back(MI->getOperand(1));
8634 DebugLoc dl = MI->getDebugLoc();
8635 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8636 Cond, MI->getOperand(2).getReg(),
8637 MI->getOperand(3).getReg());
8638 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8639 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8640 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8641 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8642 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8643 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8644 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8645 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8646 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8647 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8648 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8649 MI->getOpcode() == PPC::SELECT_I4 ||
8650 MI->getOpcode() == PPC::SELECT_I8 ||
8651 MI->getOpcode() == PPC::SELECT_F4 ||
8652 MI->getOpcode() == PPC::SELECT_F8 ||
8653 MI->getOpcode() == PPC::SELECT_QFRC ||
8654 MI->getOpcode() == PPC::SELECT_QSRC ||
8655 MI->getOpcode() == PPC::SELECT_QBRC ||
8656 MI->getOpcode() == PPC::SELECT_VRRC ||
8657 MI->getOpcode() == PPC::SELECT_VSFRC ||
8658 MI->getOpcode() == PPC::SELECT_VSSRC ||
8659 MI->getOpcode() == PPC::SELECT_VSRC) {
8660 // The incoming instruction knows the destination vreg to set, the
8661 // condition code register to branch on, the true/false values to
8662 // select between, and a branch opcode to use.
8667 // cmpTY ccX, r1, r2
8669 // fallthrough --> copy0MBB
8670 MachineBasicBlock *thisMBB = BB;
8671 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8672 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8673 DebugLoc dl = MI->getDebugLoc();
8674 F->insert(It, copy0MBB);
8675 F->insert(It, sinkMBB);
8677 // Transfer the remainder of BB and its successor edges to sinkMBB.
8678 sinkMBB->splice(sinkMBB->begin(), BB,
8679 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8680 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8682 // Next, add the true and fallthrough blocks as its successors.
8683 BB->addSuccessor(copy0MBB);
8684 BB->addSuccessor(sinkMBB);
8686 if (MI->getOpcode() == PPC::SELECT_I4 ||
8687 MI->getOpcode() == PPC::SELECT_I8 ||
8688 MI->getOpcode() == PPC::SELECT_F4 ||
8689 MI->getOpcode() == PPC::SELECT_F8 ||
8690 MI->getOpcode() == PPC::SELECT_QFRC ||
8691 MI->getOpcode() == PPC::SELECT_QSRC ||
8692 MI->getOpcode() == PPC::SELECT_QBRC ||
8693 MI->getOpcode() == PPC::SELECT_VRRC ||
8694 MI->getOpcode() == PPC::SELECT_VSFRC ||
8695 MI->getOpcode() == PPC::SELECT_VSSRC ||
8696 MI->getOpcode() == PPC::SELECT_VSRC) {
8697 BuildMI(BB, dl, TII->get(PPC::BC))
8698 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8700 unsigned SelectPred = MI->getOperand(4).getImm();
8701 BuildMI(BB, dl, TII->get(PPC::BCC))
8702 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8706 // %FalseValue = ...
8707 // # fallthrough to sinkMBB
8710 // Update machine-CFG edges
8711 BB->addSuccessor(sinkMBB);
8714 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8717 BuildMI(*BB, BB->begin(), dl,
8718 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8719 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8720 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8721 } else if (MI->getOpcode() == PPC::ReadTB) {
8722 // To read the 64-bit time-base register on a 32-bit target, we read the
8723 // two halves. Should the counter have wrapped while it was being read, we
8724 // need to try again.
8727 // mfspr Rx,TBU # load from TBU
8728 // mfspr Ry,TB # load from TB
8729 // mfspr Rz,TBU # load from TBU
8730 // cmpw crX,Rx,Rz # check if 'old'='new'
8731 // bne readLoop # branch if they're not equal
8734 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8735 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8736 DebugLoc dl = MI->getDebugLoc();
8737 F->insert(It, readMBB);
8738 F->insert(It, sinkMBB);
8740 // Transfer the remainder of BB and its successor edges to sinkMBB.
8741 sinkMBB->splice(sinkMBB->begin(), BB,
8742 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8743 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8745 BB->addSuccessor(readMBB);
8748 MachineRegisterInfo &RegInfo = F->getRegInfo();
8749 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8750 unsigned LoReg = MI->getOperand(0).getReg();
8751 unsigned HiReg = MI->getOperand(1).getReg();
8753 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8754 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8755 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8757 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8759 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8760 .addReg(HiReg).addReg(ReadAgainReg);
8761 BuildMI(BB, dl, TII->get(PPC::BCC))
8762 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8764 BB->addSuccessor(readMBB);
8765 BB->addSuccessor(sinkMBB);
8767 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8768 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8769 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8770 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8772 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8774 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8776 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8777 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8778 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8779 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8781 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8783 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8785 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8786 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8787 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8788 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8789 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8790 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8791 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8792 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8794 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8795 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8796 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8797 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8798 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8799 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8800 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8801 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8803 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8804 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8805 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8806 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8807 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8808 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8809 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8810 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8812 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8813 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8814 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8815 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8816 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8817 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8818 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8819 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8821 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8822 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8823 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8824 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8825 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8826 BB = EmitAtomicBinary(MI, BB, 4, 0);
8827 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8828 BB = EmitAtomicBinary(MI, BB, 8, 0);
8830 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8831 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8832 (Subtarget.hasPartwordAtomics() &&
8833 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8834 (Subtarget.hasPartwordAtomics() &&
8835 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8836 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8838 auto LoadMnemonic = PPC::LDARX;
8839 auto StoreMnemonic = PPC::STDCX;
8840 switch(MI->getOpcode()) {
8842 llvm_unreachable("Compare and swap of unknown size");
8843 case PPC::ATOMIC_CMP_SWAP_I8:
8844 LoadMnemonic = PPC::LBARX;
8845 StoreMnemonic = PPC::STBCX;
8846 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8848 case PPC::ATOMIC_CMP_SWAP_I16:
8849 LoadMnemonic = PPC::LHARX;
8850 StoreMnemonic = PPC::STHCX;
8851 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8853 case PPC::ATOMIC_CMP_SWAP_I32:
8854 LoadMnemonic = PPC::LWARX;
8855 StoreMnemonic = PPC::STWCX;
8857 case PPC::ATOMIC_CMP_SWAP_I64:
8858 LoadMnemonic = PPC::LDARX;
8859 StoreMnemonic = PPC::STDCX;
8862 unsigned dest = MI->getOperand(0).getReg();
8863 unsigned ptrA = MI->getOperand(1).getReg();
8864 unsigned ptrB = MI->getOperand(2).getReg();
8865 unsigned oldval = MI->getOperand(3).getReg();
8866 unsigned newval = MI->getOperand(4).getReg();
8867 DebugLoc dl = MI->getDebugLoc();
8869 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8870 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8871 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8872 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8873 F->insert(It, loop1MBB);
8874 F->insert(It, loop2MBB);
8875 F->insert(It, midMBB);
8876 F->insert(It, exitMBB);
8877 exitMBB->splice(exitMBB->begin(), BB,
8878 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8879 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8883 // fallthrough --> loopMBB
8884 BB->addSuccessor(loop1MBB);
8887 // l[bhwd]arx dest, ptr
8888 // cmp[wd] dest, oldval
8891 // st[bhwd]cx. newval, ptr
8895 // st[bhwd]cx. dest, ptr
8898 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8899 .addReg(ptrA).addReg(ptrB);
8900 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8901 .addReg(oldval).addReg(dest);
8902 BuildMI(BB, dl, TII->get(PPC::BCC))
8903 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8904 BB->addSuccessor(loop2MBB);
8905 BB->addSuccessor(midMBB);
8908 BuildMI(BB, dl, TII->get(StoreMnemonic))
8909 .addReg(newval).addReg(ptrA).addReg(ptrB);
8910 BuildMI(BB, dl, TII->get(PPC::BCC))
8911 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8912 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8913 BB->addSuccessor(loop1MBB);
8914 BB->addSuccessor(exitMBB);
8917 BuildMI(BB, dl, TII->get(StoreMnemonic))
8918 .addReg(dest).addReg(ptrA).addReg(ptrB);
8919 BB->addSuccessor(exitMBB);
8924 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8925 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8926 // We must use 64-bit registers for addresses when targeting 64-bit,
8927 // since we're actually doing arithmetic on them. Other registers
8929 bool is64bit = Subtarget.isPPC64();
8930 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8932 unsigned dest = MI->getOperand(0).getReg();
8933 unsigned ptrA = MI->getOperand(1).getReg();
8934 unsigned ptrB = MI->getOperand(2).getReg();
8935 unsigned oldval = MI->getOperand(3).getReg();
8936 unsigned newval = MI->getOperand(4).getReg();
8937 DebugLoc dl = MI->getDebugLoc();
8939 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8940 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8941 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8942 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8943 F->insert(It, loop1MBB);
8944 F->insert(It, loop2MBB);
8945 F->insert(It, midMBB);
8946 F->insert(It, exitMBB);
8947 exitMBB->splice(exitMBB->begin(), BB,
8948 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8949 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8951 MachineRegisterInfo &RegInfo = F->getRegInfo();
8952 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8953 : &PPC::GPRCRegClass;
8954 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8955 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8956 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8957 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8958 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8959 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8960 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8961 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8962 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8963 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8964 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8965 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8966 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8968 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8969 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8972 // fallthrough --> loopMBB
8973 BB->addSuccessor(loop1MBB);
8975 // The 4-byte load must be aligned, while a char or short may be
8976 // anywhere in the word. Hence all this nasty bookkeeping code.
8977 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8978 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8979 // xori shift, shift1, 24 [16]
8980 // rlwinm ptr, ptr1, 0, 0, 29
8981 // slw newval2, newval, shift
8982 // slw oldval2, oldval,shift
8983 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8984 // slw mask, mask2, shift
8985 // and newval3, newval2, mask
8986 // and oldval3, oldval2, mask
8988 // lwarx tmpDest, ptr
8989 // and tmp, tmpDest, mask
8990 // cmpw tmp, oldval3
8993 // andc tmp2, tmpDest, mask
8994 // or tmp4, tmp2, newval3
8999 // stwcx. tmpDest, ptr
9001 // srw dest, tmpDest, shift
9002 if (ptrA != ZeroReg) {
9003 Ptr1Reg = RegInfo.createVirtualRegister(RC);
9004 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
9005 .addReg(ptrA).addReg(ptrB);
9009 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
9010 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
9011 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
9012 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
9014 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
9015 .addReg(Ptr1Reg).addImm(0).addImm(61);
9017 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
9018 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
9019 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
9020 .addReg(newval).addReg(ShiftReg);
9021 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
9022 .addReg(oldval).addReg(ShiftReg);
9024 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
9026 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
9027 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
9028 .addReg(Mask3Reg).addImm(65535);
9030 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
9031 .addReg(Mask2Reg).addReg(ShiftReg);
9032 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
9033 .addReg(NewVal2Reg).addReg(MaskReg);
9034 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
9035 .addReg(OldVal2Reg).addReg(MaskReg);
9038 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
9039 .addReg(ZeroReg).addReg(PtrReg);
9040 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
9041 .addReg(TmpDestReg).addReg(MaskReg);
9042 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
9043 .addReg(TmpReg).addReg(OldVal3Reg);
9044 BuildMI(BB, dl, TII->get(PPC::BCC))
9045 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
9046 BB->addSuccessor(loop2MBB);
9047 BB->addSuccessor(midMBB);
9050 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
9051 .addReg(TmpDestReg).addReg(MaskReg);
9052 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
9053 .addReg(Tmp2Reg).addReg(NewVal3Reg);
9054 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
9055 .addReg(ZeroReg).addReg(PtrReg);
9056 BuildMI(BB, dl, TII->get(PPC::BCC))
9057 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
9058 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
9059 BB->addSuccessor(loop1MBB);
9060 BB->addSuccessor(exitMBB);
9063 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
9064 .addReg(ZeroReg).addReg(PtrReg);
9065 BB->addSuccessor(exitMBB);
9070 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
9072 } else if (MI->getOpcode() == PPC::FADDrtz) {
9073 // This pseudo performs an FADD with rounding mode temporarily forced
9074 // to round-to-zero. We emit this via custom inserter since the FPSCR
9075 // is not modeled at the SelectionDAG level.
9076 unsigned Dest = MI->getOperand(0).getReg();
9077 unsigned Src1 = MI->getOperand(1).getReg();
9078 unsigned Src2 = MI->getOperand(2).getReg();
9079 DebugLoc dl = MI->getDebugLoc();
9081 MachineRegisterInfo &RegInfo = F->getRegInfo();
9082 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
9084 // Save FPSCR value.
9085 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
9087 // Set rounding mode to round-to-zero.
9088 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
9089 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
9091 // Perform addition.
9092 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
9094 // Restore FPSCR value.
9095 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
9096 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9097 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
9098 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9099 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9100 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9101 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9102 PPC::ANDIo8 : PPC::ANDIo;
9103 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9104 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9106 MachineRegisterInfo &RegInfo = F->getRegInfo();
9107 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9108 &PPC::GPRCRegClass :
9109 &PPC::G8RCRegClass);
9111 DebugLoc dl = MI->getDebugLoc();
9112 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9113 .addReg(MI->getOperand(1).getReg()).addImm(1);
9114 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9115 MI->getOperand(0).getReg())
9116 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9117 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9118 DebugLoc Dl = MI->getDebugLoc();
9119 MachineRegisterInfo &RegInfo = F->getRegInfo();
9120 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9121 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9124 llvm_unreachable("Unexpected instr type to insert");
9127 MI->eraseFromParent(); // The pseudo instruction is gone now.
9131 //===----------------------------------------------------------------------===//
9132 // Target Optimization Hooks
9133 //===----------------------------------------------------------------------===//
9135 static std::string getRecipOp(const char *Base, EVT VT) {
9136 std::string RecipOp(Base);
9137 if (VT.getScalarType() == MVT::f64)
9143 RecipOp = "vec-" + RecipOp;
9148 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9149 DAGCombinerInfo &DCI,
9150 unsigned &RefinementSteps,
9151 bool &UseOneConstNR) const {
9152 EVT VT = Operand.getValueType();
9153 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9154 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9155 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9156 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9157 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9158 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9159 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9160 std::string RecipOp = getRecipOp("sqrt", VT);
9161 if (!Recips.isEnabled(RecipOp))
9164 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9165 UseOneConstNR = true;
9166 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9171 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9172 DAGCombinerInfo &DCI,
9173 unsigned &RefinementSteps) const {
9174 EVT VT = Operand.getValueType();
9175 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9176 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9177 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9178 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9179 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9180 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9181 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9182 std::string RecipOp = getRecipOp("div", VT);
9183 if (!Recips.isEnabled(RecipOp))
9186 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9187 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9192 unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
9193 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9194 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9195 // enabled for division), this functionality is redundant with the default
9196 // combiner logic (once the division -> reciprocal/multiply transformation
9197 // has taken place). As a result, this matters more for older cores than for
9200 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9201 // reciprocal if there are two or more FDIVs (for embedded cores with only
9202 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9203 switch (Subtarget.getDarwinDirective()) {
9208 case PPC::DIR_E500mc:
9209 case PPC::DIR_E5500:
9214 // isConsecutiveLSLoc needs to work even if all adds have not yet been
9215 // collapsed, and so we need to look through chains of them.
9216 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
9217 int64_t& Offset, SelectionDAG &DAG) {
9218 if (DAG.isBaseWithConstantOffset(Loc)) {
9219 Base = Loc.getOperand(0);
9220 Offset += cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
9222 // The base might itself be a base plus an offset, and if so, accumulate
9224 getBaseWithConstantOffset(Loc.getOperand(0), Base, Offset, DAG);
9228 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9229 unsigned Bytes, int Dist,
9230 SelectionDAG &DAG) {
9231 if (VT.getSizeInBits() / 8 != Bytes)
9234 SDValue BaseLoc = Base->getBasePtr();
9235 if (Loc.getOpcode() == ISD::FrameIndex) {
9236 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9238 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9239 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9240 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9241 int FS = MFI->getObjectSize(FI);
9242 int BFS = MFI->getObjectSize(BFI);
9243 if (FS != BFS || FS != (int)Bytes) return false;
9244 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9247 SDValue Base1 = Loc, Base2 = BaseLoc;
9248 int64_t Offset1 = 0, Offset2 = 0;
9249 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG);
9250 getBaseWithConstantOffset(BaseLoc, Base2, Offset2, DAG);
9251 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes))
9254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9255 const GlobalValue *GV1 = nullptr;
9256 const GlobalValue *GV2 = nullptr;
9259 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9260 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9261 if (isGA1 && isGA2 && GV1 == GV2)
9262 return Offset1 == (Offset2 + Dist*Bytes);
9266 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9267 // not enforce equality of the chain operands.
9268 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9269 unsigned Bytes, int Dist,
9270 SelectionDAG &DAG) {
9271 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9272 EVT VT = LS->getMemoryVT();
9273 SDValue Loc = LS->getBasePtr();
9274 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9277 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9279 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9280 default: return false;
9281 case Intrinsic::ppc_qpx_qvlfd:
9282 case Intrinsic::ppc_qpx_qvlfda:
9285 case Intrinsic::ppc_qpx_qvlfs:
9286 case Intrinsic::ppc_qpx_qvlfsa:
9289 case Intrinsic::ppc_qpx_qvlfcd:
9290 case Intrinsic::ppc_qpx_qvlfcda:
9293 case Intrinsic::ppc_qpx_qvlfcs:
9294 case Intrinsic::ppc_qpx_qvlfcsa:
9297 case Intrinsic::ppc_qpx_qvlfiwa:
9298 case Intrinsic::ppc_qpx_qvlfiwz:
9299 case Intrinsic::ppc_altivec_lvx:
9300 case Intrinsic::ppc_altivec_lvxl:
9301 case Intrinsic::ppc_vsx_lxvw4x:
9304 case Intrinsic::ppc_vsx_lxvd2x:
9307 case Intrinsic::ppc_altivec_lvebx:
9310 case Intrinsic::ppc_altivec_lvehx:
9313 case Intrinsic::ppc_altivec_lvewx:
9318 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9321 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9323 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9324 default: return false;
9325 case Intrinsic::ppc_qpx_qvstfd:
9326 case Intrinsic::ppc_qpx_qvstfda:
9329 case Intrinsic::ppc_qpx_qvstfs:
9330 case Intrinsic::ppc_qpx_qvstfsa:
9333 case Intrinsic::ppc_qpx_qvstfcd:
9334 case Intrinsic::ppc_qpx_qvstfcda:
9337 case Intrinsic::ppc_qpx_qvstfcs:
9338 case Intrinsic::ppc_qpx_qvstfcsa:
9341 case Intrinsic::ppc_qpx_qvstfiw:
9342 case Intrinsic::ppc_qpx_qvstfiwa:
9343 case Intrinsic::ppc_altivec_stvx:
9344 case Intrinsic::ppc_altivec_stvxl:
9345 case Intrinsic::ppc_vsx_stxvw4x:
9348 case Intrinsic::ppc_vsx_stxvd2x:
9351 case Intrinsic::ppc_altivec_stvebx:
9354 case Intrinsic::ppc_altivec_stvehx:
9357 case Intrinsic::ppc_altivec_stvewx:
9362 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9368 // Return true is there is a nearyby consecutive load to the one provided
9369 // (regardless of alignment). We search up and down the chain, looking though
9370 // token factors and other loads (but nothing else). As a result, a true result
9371 // indicates that it is safe to create a new consecutive load adjacent to the
9373 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9374 SDValue Chain = LD->getChain();
9375 EVT VT = LD->getMemoryVT();
9377 SmallSet<SDNode *, 16> LoadRoots;
9378 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9379 SmallSet<SDNode *, 16> Visited;
9381 // First, search up the chain, branching to follow all token-factor operands.
9382 // If we find a consecutive load, then we're done, otherwise, record all
9383 // nodes just above the top-level loads and token factors.
9384 while (!Queue.empty()) {
9385 SDNode *ChainNext = Queue.pop_back_val();
9386 if (!Visited.insert(ChainNext).second)
9389 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9390 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9393 if (!Visited.count(ChainLD->getChain().getNode()))
9394 Queue.push_back(ChainLD->getChain().getNode());
9395 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9396 for (const SDUse &O : ChainNext->ops())
9397 if (!Visited.count(O.getNode()))
9398 Queue.push_back(O.getNode());
9400 LoadRoots.insert(ChainNext);
9403 // Second, search down the chain, starting from the top-level nodes recorded
9404 // in the first phase. These top-level nodes are the nodes just above all
9405 // loads and token factors. Starting with their uses, recursively look though
9406 // all loads (just the chain uses) and token factors to find a consecutive
9411 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9412 IE = LoadRoots.end(); I != IE; ++I) {
9413 Queue.push_back(*I);
9415 while (!Queue.empty()) {
9416 SDNode *LoadRoot = Queue.pop_back_val();
9417 if (!Visited.insert(LoadRoot).second)
9420 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9421 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9424 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9425 UE = LoadRoot->use_end(); UI != UE; ++UI)
9426 if (((isa<MemSDNode>(*UI) &&
9427 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9428 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9429 Queue.push_back(*UI);
9436 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9437 DAGCombinerInfo &DCI) const {
9438 SelectionDAG &DAG = DCI.DAG;
9441 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9442 // If we're tracking CR bits, we need to be careful that we don't have:
9443 // trunc(binary-ops(zext(x), zext(y)))
9445 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9446 // such that we're unnecessarily moving things into GPRs when it would be
9447 // better to keep them in CR bits.
9449 // Note that trunc here can be an actual i1 trunc, or can be the effective
9450 // truncation that comes from a setcc or select_cc.
9451 if (N->getOpcode() == ISD::TRUNCATE &&
9452 N->getValueType(0) != MVT::i1)
9455 if (N->getOperand(0).getValueType() != MVT::i32 &&
9456 N->getOperand(0).getValueType() != MVT::i64)
9459 if (N->getOpcode() == ISD::SETCC ||
9460 N->getOpcode() == ISD::SELECT_CC) {
9461 // If we're looking at a comparison, then we need to make sure that the
9462 // high bits (all except for the first) don't matter the result.
9464 cast<CondCodeSDNode>(N->getOperand(
9465 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9466 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9468 if (ISD::isSignedIntSetCC(CC)) {
9469 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9470 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9472 } else if (ISD::isUnsignedIntSetCC(CC)) {
9473 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9474 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9475 !DAG.MaskedValueIsZero(N->getOperand(1),
9476 APInt::getHighBitsSet(OpBits, OpBits-1)))
9479 // This is neither a signed nor an unsigned comparison, just make sure
9480 // that the high bits are equal.
9481 APInt Op1Zero, Op1One;
9482 APInt Op2Zero, Op2One;
9483 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9484 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9486 // We don't really care about what is known about the first bit (if
9487 // anything), so clear it in all masks prior to comparing them.
9488 Op1Zero.clearBit(0); Op1One.clearBit(0);
9489 Op2Zero.clearBit(0); Op2One.clearBit(0);
9491 if (Op1Zero != Op2Zero || Op1One != Op2One)
9496 // We now know that the higher-order bits are irrelevant, we just need to
9497 // make sure that all of the intermediate operations are bit operations, and
9498 // all inputs are extensions.
9499 if (N->getOperand(0).getOpcode() != ISD::AND &&
9500 N->getOperand(0).getOpcode() != ISD::OR &&
9501 N->getOperand(0).getOpcode() != ISD::XOR &&
9502 N->getOperand(0).getOpcode() != ISD::SELECT &&
9503 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9504 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9505 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9506 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9507 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9510 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9511 N->getOperand(1).getOpcode() != ISD::AND &&
9512 N->getOperand(1).getOpcode() != ISD::OR &&
9513 N->getOperand(1).getOpcode() != ISD::XOR &&
9514 N->getOperand(1).getOpcode() != ISD::SELECT &&
9515 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9516 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9517 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9518 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9519 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9522 SmallVector<SDValue, 4> Inputs;
9523 SmallVector<SDValue, 8> BinOps, PromOps;
9524 SmallPtrSet<SDNode *, 16> Visited;
9526 for (unsigned i = 0; i < 2; ++i) {
9527 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9528 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9529 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9530 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9531 isa<ConstantSDNode>(N->getOperand(i)))
9532 Inputs.push_back(N->getOperand(i));
9534 BinOps.push_back(N->getOperand(i));
9536 if (N->getOpcode() == ISD::TRUNCATE)
9540 // Visit all inputs, collect all binary operations (and, or, xor and
9541 // select) that are all fed by extensions.
9542 while (!BinOps.empty()) {
9543 SDValue BinOp = BinOps.back();
9546 if (!Visited.insert(BinOp.getNode()).second)
9549 PromOps.push_back(BinOp);
9551 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9552 // The condition of the select is not promoted.
9553 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9555 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9558 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9559 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9560 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9561 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9562 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9563 Inputs.push_back(BinOp.getOperand(i));
9564 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9565 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9566 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9567 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9568 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9569 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9570 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9571 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9572 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9573 BinOps.push_back(BinOp.getOperand(i));
9575 // We have an input that is not an extension or another binary
9576 // operation; we'll abort this transformation.
9582 // Make sure that this is a self-contained cluster of operations (which
9583 // is not quite the same thing as saying that everything has only one
9585 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9586 if (isa<ConstantSDNode>(Inputs[i]))
9589 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9590 UE = Inputs[i].getNode()->use_end();
9593 if (User != N && !Visited.count(User))
9596 // Make sure that we're not going to promote the non-output-value
9597 // operand(s) or SELECT or SELECT_CC.
9598 // FIXME: Although we could sometimes handle this, and it does occur in
9599 // practice that one of the condition inputs to the select is also one of
9600 // the outputs, we currently can't deal with this.
9601 if (User->getOpcode() == ISD::SELECT) {
9602 if (User->getOperand(0) == Inputs[i])
9604 } else if (User->getOpcode() == ISD::SELECT_CC) {
9605 if (User->getOperand(0) == Inputs[i] ||
9606 User->getOperand(1) == Inputs[i])
9612 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9613 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9614 UE = PromOps[i].getNode()->use_end();
9617 if (User != N && !Visited.count(User))
9620 // Make sure that we're not going to promote the non-output-value
9621 // operand(s) or SELECT or SELECT_CC.
9622 // FIXME: Although we could sometimes handle this, and it does occur in
9623 // practice that one of the condition inputs to the select is also one of
9624 // the outputs, we currently can't deal with this.
9625 if (User->getOpcode() == ISD::SELECT) {
9626 if (User->getOperand(0) == PromOps[i])
9628 } else if (User->getOpcode() == ISD::SELECT_CC) {
9629 if (User->getOperand(0) == PromOps[i] ||
9630 User->getOperand(1) == PromOps[i])
9636 // Replace all inputs with the extension operand.
9637 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9638 // Constants may have users outside the cluster of to-be-promoted nodes,
9639 // and so we need to replace those as we do the promotions.
9640 if (isa<ConstantSDNode>(Inputs[i]))
9643 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9646 // Replace all operations (these are all the same, but have a different
9647 // (i1) return type). DAG.getNode will validate that the types of
9648 // a binary operator match, so go through the list in reverse so that
9649 // we've likely promoted both operands first. Any intermediate truncations or
9650 // extensions disappear.
9651 while (!PromOps.empty()) {
9652 SDValue PromOp = PromOps.back();
9655 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9656 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9657 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9658 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9659 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9660 PromOp.getOperand(0).getValueType() != MVT::i1) {
9661 // The operand is not yet ready (see comment below).
9662 PromOps.insert(PromOps.begin(), PromOp);
9666 SDValue RepValue = PromOp.getOperand(0);
9667 if (isa<ConstantSDNode>(RepValue))
9668 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9670 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9675 switch (PromOp.getOpcode()) {
9676 default: C = 0; break;
9677 case ISD::SELECT: C = 1; break;
9678 case ISD::SELECT_CC: C = 2; break;
9681 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9682 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9683 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9684 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9685 // The to-be-promoted operands of this node have not yet been
9686 // promoted (this should be rare because we're going through the
9687 // list backward, but if one of the operands has several users in
9688 // this cluster of to-be-promoted nodes, it is possible).
9689 PromOps.insert(PromOps.begin(), PromOp);
9693 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9694 PromOp.getNode()->op_end());
9696 // If there are any constant inputs, make sure they're replaced now.
9697 for (unsigned i = 0; i < 2; ++i)
9698 if (isa<ConstantSDNode>(Ops[C+i]))
9699 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9701 DAG.ReplaceAllUsesOfValueWith(PromOp,
9702 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9705 // Now we're left with the initial truncation itself.
9706 if (N->getOpcode() == ISD::TRUNCATE)
9707 return N->getOperand(0);
9709 // Otherwise, this is a comparison. The operands to be compared have just
9710 // changed type (to i1), but everything else is the same.
9711 return SDValue(N, 0);
9714 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9715 DAGCombinerInfo &DCI) const {
9716 SelectionDAG &DAG = DCI.DAG;
9719 // If we're tracking CR bits, we need to be careful that we don't have:
9720 // zext(binary-ops(trunc(x), trunc(y)))
9722 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9723 // such that we're unnecessarily moving things into CR bits that can more
9724 // efficiently stay in GPRs. Note that if we're not certain that the high
9725 // bits are set as required by the final extension, we still may need to do
9726 // some masking to get the proper behavior.
9728 // This same functionality is important on PPC64 when dealing with
9729 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9730 // the return values of functions. Because it is so similar, it is handled
9733 if (N->getValueType(0) != MVT::i32 &&
9734 N->getValueType(0) != MVT::i64)
9737 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9738 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9741 if (N->getOperand(0).getOpcode() != ISD::AND &&
9742 N->getOperand(0).getOpcode() != ISD::OR &&
9743 N->getOperand(0).getOpcode() != ISD::XOR &&
9744 N->getOperand(0).getOpcode() != ISD::SELECT &&
9745 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9748 SmallVector<SDValue, 4> Inputs;
9749 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9750 SmallPtrSet<SDNode *, 16> Visited;
9752 // Visit all inputs, collect all binary operations (and, or, xor and
9753 // select) that are all fed by truncations.
9754 while (!BinOps.empty()) {
9755 SDValue BinOp = BinOps.back();
9758 if (!Visited.insert(BinOp.getNode()).second)
9761 PromOps.push_back(BinOp);
9763 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9764 // The condition of the select is not promoted.
9765 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9767 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9770 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9771 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9772 Inputs.push_back(BinOp.getOperand(i));
9773 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9774 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9775 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9776 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9777 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9778 BinOps.push_back(BinOp.getOperand(i));
9780 // We have an input that is not a truncation or another binary
9781 // operation; we'll abort this transformation.
9787 // The operands of a select that must be truncated when the select is
9788 // promoted because the operand is actually part of the to-be-promoted set.
9789 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9791 // Make sure that this is a self-contained cluster of operations (which
9792 // is not quite the same thing as saying that everything has only one
9794 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9795 if (isa<ConstantSDNode>(Inputs[i]))
9798 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9799 UE = Inputs[i].getNode()->use_end();
9802 if (User != N && !Visited.count(User))
9805 // If we're going to promote the non-output-value operand(s) or SELECT or
9806 // SELECT_CC, record them for truncation.
9807 if (User->getOpcode() == ISD::SELECT) {
9808 if (User->getOperand(0) == Inputs[i])
9809 SelectTruncOp[0].insert(std::make_pair(User,
9810 User->getOperand(0).getValueType()));
9811 } else if (User->getOpcode() == ISD::SELECT_CC) {
9812 if (User->getOperand(0) == Inputs[i])
9813 SelectTruncOp[0].insert(std::make_pair(User,
9814 User->getOperand(0).getValueType()));
9815 if (User->getOperand(1) == Inputs[i])
9816 SelectTruncOp[1].insert(std::make_pair(User,
9817 User->getOperand(1).getValueType()));
9822 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9823 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9824 UE = PromOps[i].getNode()->use_end();
9827 if (User != N && !Visited.count(User))
9830 // If we're going to promote the non-output-value operand(s) or SELECT or
9831 // SELECT_CC, record them for truncation.
9832 if (User->getOpcode() == ISD::SELECT) {
9833 if (User->getOperand(0) == PromOps[i])
9834 SelectTruncOp[0].insert(std::make_pair(User,
9835 User->getOperand(0).getValueType()));
9836 } else if (User->getOpcode() == ISD::SELECT_CC) {
9837 if (User->getOperand(0) == PromOps[i])
9838 SelectTruncOp[0].insert(std::make_pair(User,
9839 User->getOperand(0).getValueType()));
9840 if (User->getOperand(1) == PromOps[i])
9841 SelectTruncOp[1].insert(std::make_pair(User,
9842 User->getOperand(1).getValueType()));
9847 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9848 bool ReallyNeedsExt = false;
9849 if (N->getOpcode() != ISD::ANY_EXTEND) {
9850 // If all of the inputs are not already sign/zero extended, then
9851 // we'll still need to do that at the end.
9852 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9853 if (isa<ConstantSDNode>(Inputs[i]))
9857 Inputs[i].getOperand(0).getValueSizeInBits();
9858 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9860 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9861 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9862 APInt::getHighBitsSet(OpBits,
9863 OpBits-PromBits))) ||
9864 (N->getOpcode() == ISD::SIGN_EXTEND &&
9865 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9866 (OpBits-(PromBits-1)))) {
9867 ReallyNeedsExt = true;
9873 // Replace all inputs, either with the truncation operand, or a
9874 // truncation or extension to the final output type.
9875 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9876 // Constant inputs need to be replaced with the to-be-promoted nodes that
9877 // use them because they might have users outside of the cluster of
9879 if (isa<ConstantSDNode>(Inputs[i]))
9882 SDValue InSrc = Inputs[i].getOperand(0);
9883 if (Inputs[i].getValueType() == N->getValueType(0))
9884 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9885 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9886 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9887 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9888 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9889 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9890 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9892 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9893 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9896 // Replace all operations (these are all the same, but have a different
9897 // (promoted) return type). DAG.getNode will validate that the types of
9898 // a binary operator match, so go through the list in reverse so that
9899 // we've likely promoted both operands first.
9900 while (!PromOps.empty()) {
9901 SDValue PromOp = PromOps.back();
9905 switch (PromOp.getOpcode()) {
9906 default: C = 0; break;
9907 case ISD::SELECT: C = 1; break;
9908 case ISD::SELECT_CC: C = 2; break;
9911 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9912 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9913 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9914 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9915 // The to-be-promoted operands of this node have not yet been
9916 // promoted (this should be rare because we're going through the
9917 // list backward, but if one of the operands has several users in
9918 // this cluster of to-be-promoted nodes, it is possible).
9919 PromOps.insert(PromOps.begin(), PromOp);
9923 // For SELECT and SELECT_CC nodes, we do a similar check for any
9924 // to-be-promoted comparison inputs.
9925 if (PromOp.getOpcode() == ISD::SELECT ||
9926 PromOp.getOpcode() == ISD::SELECT_CC) {
9927 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9928 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9929 (SelectTruncOp[1].count(PromOp.getNode()) &&
9930 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9931 PromOps.insert(PromOps.begin(), PromOp);
9936 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9937 PromOp.getNode()->op_end());
9939 // If this node has constant inputs, then they'll need to be promoted here.
9940 for (unsigned i = 0; i < 2; ++i) {
9941 if (!isa<ConstantSDNode>(Ops[C+i]))
9943 if (Ops[C+i].getValueType() == N->getValueType(0))
9946 if (N->getOpcode() == ISD::SIGN_EXTEND)
9947 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9948 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9949 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9951 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9954 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9955 // truncate them again to the original value type.
9956 if (PromOp.getOpcode() == ISD::SELECT ||
9957 PromOp.getOpcode() == ISD::SELECT_CC) {
9958 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9959 if (SI0 != SelectTruncOp[0].end())
9960 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9961 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9962 if (SI1 != SelectTruncOp[1].end())
9963 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9966 DAG.ReplaceAllUsesOfValueWith(PromOp,
9967 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9970 // Now we're left with the initial extension itself.
9971 if (!ReallyNeedsExt)
9972 return N->getOperand(0);
9974 // To zero extend, just mask off everything except for the first bit (in the
9976 if (N->getOpcode() == ISD::ZERO_EXTEND)
9977 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9978 DAG.getConstant(APInt::getLowBitsSet(
9979 N->getValueSizeInBits(0), PromBits),
9980 dl, N->getValueType(0)));
9982 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9983 "Invalid extension type");
9984 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
9986 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9988 ISD::SRA, dl, N->getValueType(0),
9989 DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst),
9993 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9994 DAGCombinerInfo &DCI) const {
9995 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9996 N->getOpcode() == ISD::UINT_TO_FP) &&
9997 "Need an int -> FP conversion node here");
9999 if (!Subtarget.has64BitSupport())
10002 SelectionDAG &DAG = DCI.DAG;
10006 // Don't handle ppc_fp128 here or i1 conversions.
10007 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
10009 if (Op.getOperand(0).getValueType() == MVT::i1)
10012 // For i32 intermediate values, unfortunately, the conversion functions
10013 // leave the upper 32 bits of the value are undefined. Within the set of
10014 // scalar instructions, we have no method for zero- or sign-extending the
10015 // value. Thus, we cannot handle i32 intermediate values here.
10016 if (Op.getOperand(0).getValueType() == MVT::i32)
10019 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
10020 "UINT_TO_FP is supported only with FPCVT");
10022 // If we have FCFIDS, then use it when converting to single-precision.
10023 // Otherwise, convert to double-precision and then round.
10024 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10025 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
10027 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
10029 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10033 // If we're converting from a float, to an int, and back to a float again,
10034 // then we don't need the store/load pair at all.
10035 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
10036 Subtarget.hasFPCVT()) ||
10037 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
10038 SDValue Src = Op.getOperand(0).getOperand(0);
10039 if (Src.getValueType() == MVT::f32) {
10040 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
10041 DCI.AddToWorklist(Src.getNode());
10042 } else if (Src.getValueType() != MVT::f64) {
10043 // Make sure that we don't pick up a ppc_fp128 source value.
10048 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
10051 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
10052 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
10054 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
10055 FP = DAG.getNode(ISD::FP_ROUND, dl,
10056 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
10057 DCI.AddToWorklist(FP.getNode());
10066 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
10067 // builtins) into loads with swaps.
10068 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
10069 DAGCombinerInfo &DCI) const {
10070 SelectionDAG &DAG = DCI.DAG;
10074 MachineMemOperand *MMO;
10076 switch (N->getOpcode()) {
10078 llvm_unreachable("Unexpected opcode for little endian VSX load");
10080 LoadSDNode *LD = cast<LoadSDNode>(N);
10081 Chain = LD->getChain();
10082 Base = LD->getBasePtr();
10083 MMO = LD->getMemOperand();
10084 // If the MMO suggests this isn't a load of a full vector, leave
10085 // things alone. For a built-in, we have to make the change for
10086 // correctness, so if there is a size problem that will be a bug.
10087 if (MMO->getSize() < 16)
10091 case ISD::INTRINSIC_W_CHAIN: {
10092 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10093 Chain = Intrin->getChain();
10094 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
10095 // us what we want. Get operand 2 instead.
10096 Base = Intrin->getOperand(2);
10097 MMO = Intrin->getMemOperand();
10102 MVT VecTy = N->getValueType(0).getSimpleVT();
10103 SDValue LoadOps[] = { Chain, Base };
10104 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
10105 DAG.getVTList(VecTy, MVT::Other),
10106 LoadOps, VecTy, MMO);
10107 DCI.AddToWorklist(Load.getNode());
10108 Chain = Load.getValue(1);
10109 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10110 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
10111 DCI.AddToWorklist(Swap.getNode());
10115 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
10116 // builtins) into stores with swaps.
10117 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
10118 DAGCombinerInfo &DCI) const {
10119 SelectionDAG &DAG = DCI.DAG;
10124 MachineMemOperand *MMO;
10126 switch (N->getOpcode()) {
10128 llvm_unreachable("Unexpected opcode for little endian VSX store");
10130 StoreSDNode *ST = cast<StoreSDNode>(N);
10131 Chain = ST->getChain();
10132 Base = ST->getBasePtr();
10133 MMO = ST->getMemOperand();
10135 // If the MMO suggests this isn't a store of a full vector, leave
10136 // things alone. For a built-in, we have to make the change for
10137 // correctness, so if there is a size problem that will be a bug.
10138 if (MMO->getSize() < 16)
10142 case ISD::INTRINSIC_VOID: {
10143 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10144 Chain = Intrin->getChain();
10145 // Intrin->getBasePtr() oddly does not get what we want.
10146 Base = Intrin->getOperand(3);
10147 MMO = Intrin->getMemOperand();
10153 SDValue Src = N->getOperand(SrcOpnd);
10154 MVT VecTy = Src.getValueType().getSimpleVT();
10155 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10156 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10157 DCI.AddToWorklist(Swap.getNode());
10158 Chain = Swap.getValue(1);
10159 SDValue StoreOps[] = { Chain, Swap, Base };
10160 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10161 DAG.getVTList(MVT::Other),
10162 StoreOps, VecTy, MMO);
10163 DCI.AddToWorklist(Store.getNode());
10167 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10168 DAGCombinerInfo &DCI) const {
10169 SelectionDAG &DAG = DCI.DAG;
10171 switch (N->getOpcode()) {
10174 if (isNullConstant(N->getOperand(0))) // 0 << V -> 0.
10175 return N->getOperand(0);
10178 if (isNullConstant(N->getOperand(0))) // 0 >>u V -> 0.
10179 return N->getOperand(0);
10182 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10183 if (C->isNullValue() || // 0 >>s V -> 0.
10184 C->isAllOnesValue()) // -1 >>s V -> -1.
10185 return N->getOperand(0);
10188 case ISD::SIGN_EXTEND:
10189 case ISD::ZERO_EXTEND:
10190 case ISD::ANY_EXTEND:
10191 return DAGCombineExtBoolTrunc(N, DCI);
10192 case ISD::TRUNCATE:
10194 case ISD::SELECT_CC:
10195 return DAGCombineTruncBoolExt(N, DCI);
10196 case ISD::SINT_TO_FP:
10197 case ISD::UINT_TO_FP:
10198 return combineFPToIntToFP(N, DCI);
10200 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10201 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10202 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10203 N->getOperand(1).getValueType() == MVT::i32 &&
10204 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10205 SDValue Val = N->getOperand(1).getOperand(0);
10206 if (Val.getValueType() == MVT::f32) {
10207 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10208 DCI.AddToWorklist(Val.getNode());
10210 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10211 DCI.AddToWorklist(Val.getNode());
10214 N->getOperand(0), Val, N->getOperand(2),
10215 DAG.getValueType(N->getOperand(1).getValueType())
10218 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10219 DAG.getVTList(MVT::Other), Ops,
10220 cast<StoreSDNode>(N)->getMemoryVT(),
10221 cast<StoreSDNode>(N)->getMemOperand());
10222 DCI.AddToWorklist(Val.getNode());
10226 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10227 if (cast<StoreSDNode>(N)->isUnindexed() &&
10228 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10229 N->getOperand(1).getNode()->hasOneUse() &&
10230 (N->getOperand(1).getValueType() == MVT::i32 ||
10231 N->getOperand(1).getValueType() == MVT::i16 ||
10232 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10233 N->getOperand(1).getValueType() == MVT::i64))) {
10234 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10235 // Do an any-extend to 32-bits if this is a half-word input.
10236 if (BSwapOp.getValueType() == MVT::i16)
10237 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10240 N->getOperand(0), BSwapOp, N->getOperand(2),
10241 DAG.getValueType(N->getOperand(1).getValueType())
10244 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10245 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10246 cast<StoreSDNode>(N)->getMemOperand());
10249 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10250 EVT VT = N->getOperand(1).getValueType();
10251 if (VT.isSimple()) {
10252 MVT StoreVT = VT.getSimpleVT();
10253 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10254 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10255 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10256 return expandVSXStoreForLE(N, DCI);
10261 LoadSDNode *LD = cast<LoadSDNode>(N);
10262 EVT VT = LD->getValueType(0);
10264 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10265 if (VT.isSimple()) {
10266 MVT LoadVT = VT.getSimpleVT();
10267 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10268 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10269 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10270 return expandVSXLoadForLE(N, DCI);
10273 EVT MemVT = LD->getMemoryVT();
10274 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10275 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
10276 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10277 unsigned ScalarABIAlignment = DAG.getDataLayout().getABITypeAlignment(STy);
10278 if (LD->isUnindexed() && VT.isVector() &&
10279 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10280 // P8 and later hardware should just use LOAD.
10281 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10282 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10283 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10284 LD->getAlignment() >= ScalarABIAlignment)) &&
10285 LD->getAlignment() < ABIAlignment) {
10286 // This is a type-legal unaligned Altivec or QPX load.
10287 SDValue Chain = LD->getChain();
10288 SDValue Ptr = LD->getBasePtr();
10289 bool isLittleEndian = Subtarget.isLittleEndian();
10291 // This implements the loading of unaligned vectors as described in
10292 // the venerable Apple Velocity Engine overview. Specifically:
10293 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10294 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10296 // The general idea is to expand a sequence of one or more unaligned
10297 // loads into an alignment-based permutation-control instruction (lvsl
10298 // or lvsr), a series of regular vector loads (which always truncate
10299 // their input address to an aligned address), and a series of
10300 // permutations. The results of these permutations are the requested
10301 // loaded values. The trick is that the last "extra" load is not taken
10302 // from the address you might suspect (sizeof(vector) bytes after the
10303 // last requested load), but rather sizeof(vector) - 1 bytes after the
10304 // last requested vector. The point of this is to avoid a page fault if
10305 // the base address happened to be aligned. This works because if the
10306 // base address is aligned, then adding less than a full vector length
10307 // will cause the last vector in the sequence to be (re)loaded.
10308 // Otherwise, the next vector will be fetched as you might suspect was
10311 // We might be able to reuse the permutation generation from
10312 // a different base address offset from this one by an aligned amount.
10313 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10314 // optimization later.
10315 Intrinsic::ID Intr, IntrLD, IntrPerm;
10316 MVT PermCntlTy, PermTy, LDTy;
10317 if (Subtarget.hasAltivec()) {
10318 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10319 Intrinsic::ppc_altivec_lvsl;
10320 IntrLD = Intrinsic::ppc_altivec_lvx;
10321 IntrPerm = Intrinsic::ppc_altivec_vperm;
10322 PermCntlTy = MVT::v16i8;
10323 PermTy = MVT::v4i32;
10326 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10327 Intrinsic::ppc_qpx_qvlpcls;
10328 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10329 Intrinsic::ppc_qpx_qvlfs;
10330 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10331 PermCntlTy = MVT::v4f64;
10332 PermTy = MVT::v4f64;
10333 LDTy = MemVT.getSimpleVT();
10336 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10338 // Create the new MMO for the new base load. It is like the original MMO,
10339 // but represents an area in memory almost twice the vector size centered
10340 // on the original address. If the address is unaligned, we might start
10341 // reading up to (sizeof(vector)-1) bytes below the address of the
10342 // original unaligned load.
10343 MachineFunction &MF = DAG.getMachineFunction();
10344 MachineMemOperand *BaseMMO =
10345 MF.getMachineMemOperand(LD->getMemOperand(),
10346 -(long)MemVT.getStoreSize()+1,
10347 2*MemVT.getStoreSize()-1);
10349 // Create the new base load.
10351 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
10352 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10354 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10355 DAG.getVTList(PermTy, MVT::Other),
10356 BaseLoadOps, LDTy, BaseMMO);
10358 // Note that the value of IncOffset (which is provided to the next
10359 // load's pointer info offset value, and thus used to calculate the
10360 // alignment), and the value of IncValue (which is actually used to
10361 // increment the pointer value) are different! This is because we
10362 // require the next load to appear to be aligned, even though it
10363 // is actually offset from the base pointer by a lesser amount.
10364 int IncOffset = VT.getSizeInBits() / 8;
10365 int IncValue = IncOffset;
10367 // Walk (both up and down) the chain looking for another load at the real
10368 // (aligned) offset (the alignment of the other load does not matter in
10369 // this case). If found, then do not use the offset reduction trick, as
10370 // that will prevent the loads from being later combined (as they would
10371 // otherwise be duplicates).
10372 if (!findConsecutiveLoad(LD, DAG))
10375 SDValue Increment =
10376 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
10377 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10379 MachineMemOperand *ExtraMMO =
10380 MF.getMachineMemOperand(LD->getMemOperand(),
10381 1, 2*MemVT.getStoreSize()-1);
10382 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10383 SDValue ExtraLoad =
10384 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10385 DAG.getVTList(PermTy, MVT::Other),
10386 ExtraLoadOps, LDTy, ExtraMMO);
10388 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10389 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10391 // Because vperm has a big-endian bias, we must reverse the order
10392 // of the input vectors and complement the permute control vector
10393 // when generating little endian code. We have already handled the
10394 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10395 // and ExtraLoad here.
10397 if (isLittleEndian)
10398 Perm = BuildIntrinsicOp(IntrPerm,
10399 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10401 Perm = BuildIntrinsicOp(IntrPerm,
10402 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10405 Perm = Subtarget.hasAltivec() ?
10406 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10407 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10408 DAG.getTargetConstant(1, dl, MVT::i64));
10409 // second argument is 1 because this rounding
10410 // is always exact.
10412 // The output of the permutation is our loaded result, the TokenFactor is
10414 DCI.CombineTo(N, Perm, TF);
10415 return SDValue(N, 0);
10419 case ISD::INTRINSIC_WO_CHAIN: {
10420 bool isLittleEndian = Subtarget.isLittleEndian();
10421 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10422 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10423 : Intrinsic::ppc_altivec_lvsl);
10424 if ((IID == Intr ||
10425 IID == Intrinsic::ppc_qpx_qvlpcld ||
10426 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10427 N->getOperand(1)->getOpcode() == ISD::ADD) {
10428 SDValue Add = N->getOperand(1);
10430 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10431 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10433 if (DAG.MaskedValueIsZero(
10434 Add->getOperand(1),
10435 APInt::getAllOnesValue(Bits /* alignment */)
10437 Add.getValueType().getScalarType().getSizeInBits()))) {
10438 SDNode *BasePtr = Add->getOperand(0).getNode();
10439 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10440 UE = BasePtr->use_end();
10442 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10443 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10444 // We've found another LVSL/LVSR, and this address is an aligned
10445 // multiple of that one. The results will be the same, so use the
10446 // one we've just found instead.
10448 return SDValue(*UI, 0);
10453 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10454 SDNode *BasePtr = Add->getOperand(0).getNode();
10455 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10456 UE = BasePtr->use_end(); UI != UE; ++UI) {
10457 if (UI->getOpcode() == ISD::ADD &&
10458 isa<ConstantSDNode>(UI->getOperand(1)) &&
10459 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10460 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10461 (1ULL << Bits) == 0) {
10462 SDNode *OtherAdd = *UI;
10463 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10464 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10465 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10466 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10467 return SDValue(*VI, 0);
10477 case ISD::INTRINSIC_W_CHAIN: {
10478 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10479 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10480 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10483 case Intrinsic::ppc_vsx_lxvw4x:
10484 case Intrinsic::ppc_vsx_lxvd2x:
10485 return expandVSXLoadForLE(N, DCI);
10490 case ISD::INTRINSIC_VOID: {
10491 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10492 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10493 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10496 case Intrinsic::ppc_vsx_stxvw4x:
10497 case Intrinsic::ppc_vsx_stxvd2x:
10498 return expandVSXStoreForLE(N, DCI);
10504 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10505 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10506 N->getOperand(0).hasOneUse() &&
10507 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10508 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10509 N->getValueType(0) == MVT::i64))) {
10510 SDValue Load = N->getOperand(0);
10511 LoadSDNode *LD = cast<LoadSDNode>(Load);
10512 // Create the byte-swapping load.
10514 LD->getChain(), // Chain
10515 LD->getBasePtr(), // Ptr
10516 DAG.getValueType(N->getValueType(0)) // VT
10519 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10520 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10521 MVT::i64 : MVT::i32, MVT::Other),
10522 Ops, LD->getMemoryVT(), LD->getMemOperand());
10524 // If this is an i16 load, insert the truncate.
10525 SDValue ResVal = BSLoad;
10526 if (N->getValueType(0) == MVT::i16)
10527 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10529 // First, combine the bswap away. This makes the value produced by the
10531 DCI.CombineTo(N, ResVal);
10533 // Next, combine the load away, we give it a bogus result value but a real
10534 // chain result. The result value is dead because the bswap is dead.
10535 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10537 // Return N so it doesn't get rechecked!
10538 return SDValue(N, 0);
10542 case PPCISD::VCMP: {
10543 // If a VCMPo node already exists with exactly the same operands as this
10544 // node, use its result instead of this node (VCMPo computes both a CR6 and
10545 // a normal output).
10547 if (!N->getOperand(0).hasOneUse() &&
10548 !N->getOperand(1).hasOneUse() &&
10549 !N->getOperand(2).hasOneUse()) {
10551 // Scan all of the users of the LHS, looking for VCMPo's that match.
10552 SDNode *VCMPoNode = nullptr;
10554 SDNode *LHSN = N->getOperand(0).getNode();
10555 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10557 if (UI->getOpcode() == PPCISD::VCMPo &&
10558 UI->getOperand(1) == N->getOperand(1) &&
10559 UI->getOperand(2) == N->getOperand(2) &&
10560 UI->getOperand(0) == N->getOperand(0)) {
10565 // If there is no VCMPo node, or if the flag value has a single use, don't
10567 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10570 // Look at the (necessarily single) use of the flag value. If it has a
10571 // chain, this transformation is more complex. Note that multiple things
10572 // could use the value result, which we should ignore.
10573 SDNode *FlagUser = nullptr;
10574 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10575 FlagUser == nullptr; ++UI) {
10576 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10577 SDNode *User = *UI;
10578 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10579 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10586 // If the user is a MFOCRF instruction, we know this is safe.
10587 // Otherwise we give up for right now.
10588 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10589 return SDValue(VCMPoNode, 0);
10593 case ISD::BRCOND: {
10594 SDValue Cond = N->getOperand(1);
10595 SDValue Target = N->getOperand(2);
10597 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10598 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10599 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10601 // We now need to make the intrinsic dead (it cannot be instruction
10603 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10604 assert(Cond.getNode()->hasOneUse() &&
10605 "Counter decrement has more than one use");
10607 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10608 N->getOperand(0), Target);
10613 // If this is a branch on an altivec predicate comparison, lower this so
10614 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10615 // lowering is done pre-legalize, because the legalizer lowers the predicate
10616 // compare down to code that is difficult to reassemble.
10617 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10618 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10620 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10621 // value. If so, pass-through the AND to get to the intrinsic.
10622 if (LHS.getOpcode() == ISD::AND &&
10623 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10624 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10625 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10626 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10627 !isNullConstant(LHS.getOperand(1)))
10628 LHS = LHS.getOperand(0);
10630 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10631 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10632 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10633 isa<ConstantSDNode>(RHS)) {
10634 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10635 "Counter decrement comparison is not EQ or NE");
10637 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10638 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10639 (CC == ISD::SETNE && !Val);
10641 // We now need to make the intrinsic dead (it cannot be instruction
10643 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10644 assert(LHS.getNode()->hasOneUse() &&
10645 "Counter decrement has more than one use");
10647 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10648 N->getOperand(0), N->getOperand(4));
10654 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10655 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10656 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10657 assert(isDot && "Can't compare against a vector result!");
10659 // If this is a comparison against something other than 0/1, then we know
10660 // that the condition is never/always true.
10661 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10662 if (Val != 0 && Val != 1) {
10663 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10664 return N->getOperand(0);
10665 // Always !=, turn it into an unconditional branch.
10666 return DAG.getNode(ISD::BR, dl, MVT::Other,
10667 N->getOperand(0), N->getOperand(4));
10670 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10672 // Create the PPCISD altivec 'dot' comparison node.
10674 LHS.getOperand(2), // LHS of compare
10675 LHS.getOperand(3), // RHS of compare
10676 DAG.getConstant(CompareOpc, dl, MVT::i32)
10678 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10679 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10681 // Unpack the result based on how the target uses it.
10682 PPC::Predicate CompOpc;
10683 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10684 default: // Can't happen, don't crash on invalid number though.
10685 case 0: // Branch on the value of the EQ bit of CR6.
10686 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10688 case 1: // Branch on the inverted value of the EQ bit of CR6.
10689 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10691 case 2: // Branch on the value of the LT bit of CR6.
10692 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10694 case 3: // Branch on the inverted value of the LT bit of CR6.
10695 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10699 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10700 DAG.getConstant(CompOpc, dl, MVT::i32),
10701 DAG.getRegister(PPC::CR6, MVT::i32),
10702 N->getOperand(4), CompNode.getValue(1));
10712 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10714 std::vector<SDNode *> *Created) const {
10715 // fold (sdiv X, pow2)
10716 EVT VT = N->getValueType(0);
10717 if (VT == MVT::i64 && !Subtarget.isPPC64())
10719 if ((VT != MVT::i32 && VT != MVT::i64) ||
10720 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10724 SDValue N0 = N->getOperand(0);
10726 bool IsNegPow2 = (-Divisor).isPowerOf2();
10727 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10728 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10730 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10732 Created->push_back(Op.getNode());
10735 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10737 Created->push_back(Op.getNode());
10743 //===----------------------------------------------------------------------===//
10744 // Inline Assembly Support
10745 //===----------------------------------------------------------------------===//
10747 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10750 const SelectionDAG &DAG,
10751 unsigned Depth) const {
10752 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10753 switch (Op.getOpcode()) {
10755 case PPCISD::LBRX: {
10756 // lhbrx is known to have the top bits cleared out.
10757 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10758 KnownZero = 0xFFFF0000;
10761 case ISD::INTRINSIC_WO_CHAIN: {
10762 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10764 case Intrinsic::ppc_altivec_vcmpbfp_p:
10765 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10766 case Intrinsic::ppc_altivec_vcmpequb_p:
10767 case Intrinsic::ppc_altivec_vcmpequh_p:
10768 case Intrinsic::ppc_altivec_vcmpequw_p:
10769 case Intrinsic::ppc_altivec_vcmpequd_p:
10770 case Intrinsic::ppc_altivec_vcmpgefp_p:
10771 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10772 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10773 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10774 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10775 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10776 case Intrinsic::ppc_altivec_vcmpgtub_p:
10777 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10778 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10779 case Intrinsic::ppc_altivec_vcmpgtud_p:
10780 KnownZero = ~1U; // All bits but the low one are known to be zero.
10787 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10788 switch (Subtarget.getDarwinDirective()) {
10791 case PPC::DIR_PWR4:
10792 case PPC::DIR_PWR5:
10793 case PPC::DIR_PWR5X:
10794 case PPC::DIR_PWR6:
10795 case PPC::DIR_PWR6X:
10796 case PPC::DIR_PWR7:
10797 case PPC::DIR_PWR8: {
10801 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10803 // For small loops (between 5 and 8 instructions), align to a 32-byte
10804 // boundary so that the entire loop fits in one instruction-cache line.
10805 uint64_t LoopSize = 0;
10806 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10807 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J) {
10808 LoopSize += TII->GetInstSizeInBytes(J);
10813 if (LoopSize > 16 && LoopSize <= 32)
10820 return TargetLowering::getPrefLoopAlignment(ML);
10823 /// getConstraintType - Given a constraint, return the type of
10824 /// constraint it is for this target.
10825 PPCTargetLowering::ConstraintType
10826 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10827 if (Constraint.size() == 1) {
10828 switch (Constraint[0]) {
10835 return C_RegisterClass;
10837 // FIXME: While Z does indicate a memory constraint, it specifically
10838 // indicates an r+r address (used in conjunction with the 'y' modifier
10839 // in the replacement string). Currently, we're forcing the base
10840 // register to be r0 in the asm printer (which is interpreted as zero)
10841 // and forming the complete address in the second register. This is
10845 } else if (Constraint == "wc") { // individual CR bits.
10846 return C_RegisterClass;
10847 } else if (Constraint == "wa" || Constraint == "wd" ||
10848 Constraint == "wf" || Constraint == "ws") {
10849 return C_RegisterClass; // VSX registers.
10851 return TargetLowering::getConstraintType(Constraint);
10854 /// Examine constraint type and operand type and determine a weight value.
10855 /// This object must already have been set up with the operand type
10856 /// and the current alternative constraint selected.
10857 TargetLowering::ConstraintWeight
10858 PPCTargetLowering::getSingleConstraintMatchWeight(
10859 AsmOperandInfo &info, const char *constraint) const {
10860 ConstraintWeight weight = CW_Invalid;
10861 Value *CallOperandVal = info.CallOperandVal;
10862 // If we don't have a value, we can't do a match,
10863 // but allow it at the lowest weight.
10864 if (!CallOperandVal)
10866 Type *type = CallOperandVal->getType();
10868 // Look at the constraint type.
10869 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10870 return CW_Register; // an individual CR bit.
10871 else if ((StringRef(constraint) == "wa" ||
10872 StringRef(constraint) == "wd" ||
10873 StringRef(constraint) == "wf") &&
10874 type->isVectorTy())
10875 return CW_Register;
10876 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10877 return CW_Register;
10879 switch (*constraint) {
10881 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10884 if (type->isIntegerTy())
10885 weight = CW_Register;
10888 if (type->isFloatTy())
10889 weight = CW_Register;
10892 if (type->isDoubleTy())
10893 weight = CW_Register;
10896 if (type->isVectorTy())
10897 weight = CW_Register;
10900 weight = CW_Register;
10903 weight = CW_Memory;
10909 std::pair<unsigned, const TargetRegisterClass *>
10910 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10911 StringRef Constraint,
10913 if (Constraint.size() == 1) {
10914 // GCC RS6000 Constraint Letters
10915 switch (Constraint[0]) {
10916 case 'b': // R1-R31
10917 if (VT == MVT::i64 && Subtarget.isPPC64())
10918 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10919 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10920 case 'r': // R0-R31
10921 if (VT == MVT::i64 && Subtarget.isPPC64())
10922 return std::make_pair(0U, &PPC::G8RCRegClass);
10923 return std::make_pair(0U, &PPC::GPRCRegClass);
10925 if (VT == MVT::f32 || VT == MVT::i32)
10926 return std::make_pair(0U, &PPC::F4RCRegClass);
10927 if (VT == MVT::f64 || VT == MVT::i64)
10928 return std::make_pair(0U, &PPC::F8RCRegClass);
10929 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10930 return std::make_pair(0U, &PPC::QFRCRegClass);
10931 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10932 return std::make_pair(0U, &PPC::QSRCRegClass);
10935 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10936 return std::make_pair(0U, &PPC::QFRCRegClass);
10937 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10938 return std::make_pair(0U, &PPC::QSRCRegClass);
10939 if (Subtarget.hasAltivec())
10940 return std::make_pair(0U, &PPC::VRRCRegClass);
10942 return std::make_pair(0U, &PPC::CRRCRegClass);
10944 } else if (Constraint == "wc" && Subtarget.useCRBits()) {
10945 // An individual CR bit.
10946 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10947 } else if ((Constraint == "wa" || Constraint == "wd" ||
10948 Constraint == "wf") && Subtarget.hasVSX()) {
10949 return std::make_pair(0U, &PPC::VSRCRegClass);
10950 } else if (Constraint == "ws" && Subtarget.hasVSX()) {
10951 if (VT == MVT::f32 && Subtarget.hasP8Vector())
10952 return std::make_pair(0U, &PPC::VSSRCRegClass);
10954 return std::make_pair(0U, &PPC::VSFRCRegClass);
10957 std::pair<unsigned, const TargetRegisterClass *> R =
10958 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10960 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10961 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10962 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10964 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10965 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10966 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10967 PPC::GPRCRegClass.contains(R.first))
10968 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10969 PPC::sub_32, &PPC::G8RCRegClass),
10970 &PPC::G8RCRegClass);
10972 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10973 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10974 R.first = PPC::CR0;
10975 R.second = &PPC::CRRCRegClass;
10981 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10982 /// vector. If it is invalid, don't add anything to Ops.
10983 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10984 std::string &Constraint,
10985 std::vector<SDValue>&Ops,
10986 SelectionDAG &DAG) const {
10989 // Only support length 1 constraints.
10990 if (Constraint.length() > 1) return;
10992 char Letter = Constraint[0];
11003 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
11004 if (!CST) return; // Must be an immediate to match.
11006 int64_t Value = CST->getSExtValue();
11007 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
11008 // numbers are printed as such.
11010 default: llvm_unreachable("Unknown constraint letter!");
11011 case 'I': // "I" is a signed 16-bit constant.
11012 if (isInt<16>(Value))
11013 Result = DAG.getTargetConstant(Value, dl, TCVT);
11015 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
11016 if (isShiftedUInt<16, 16>(Value))
11017 Result = DAG.getTargetConstant(Value, dl, TCVT);
11019 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
11020 if (isShiftedInt<16, 16>(Value))
11021 Result = DAG.getTargetConstant(Value, dl, TCVT);
11023 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
11024 if (isUInt<16>(Value))
11025 Result = DAG.getTargetConstant(Value, dl, TCVT);
11027 case 'M': // "M" is a constant that is greater than 31.
11029 Result = DAG.getTargetConstant(Value, dl, TCVT);
11031 case 'N': // "N" is a positive constant that is an exact power of two.
11032 if (Value > 0 && isPowerOf2_64(Value))
11033 Result = DAG.getTargetConstant(Value, dl, TCVT);
11035 case 'O': // "O" is the constant zero.
11037 Result = DAG.getTargetConstant(Value, dl, TCVT);
11039 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
11040 if (isInt<16>(-Value))
11041 Result = DAG.getTargetConstant(Value, dl, TCVT);
11048 if (Result.getNode()) {
11049 Ops.push_back(Result);
11053 // Handle standard constraint letters.
11054 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11057 // isLegalAddressingMode - Return true if the addressing mode represented
11058 // by AM is legal for this target, for a load/store of the specified type.
11059 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
11060 const AddrMode &AM, Type *Ty,
11061 unsigned AS) const {
11062 // PPC does not allow r+i addressing modes for vectors!
11063 if (Ty->isVectorTy() && AM.BaseOffs != 0)
11066 // PPC allows a sign-extended 16-bit immediate field.
11067 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
11070 // No global is ever allowed as a base.
11074 // PPC only support r+r,
11075 switch (AM.Scale) {
11076 case 0: // "r+i" or just "i", depending on HasBaseReg.
11079 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
11081 // Otherwise we have r+r or r+i.
11084 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
11086 // Allow 2*r as r+r.
11089 // No other scales are supported.
11096 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
11097 SelectionDAG &DAG) const {
11098 MachineFunction &MF = DAG.getMachineFunction();
11099 MachineFrameInfo *MFI = MF.getFrameInfo();
11100 MFI->setReturnAddressIsTaken(true);
11102 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
11106 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11108 // Make sure the function does not optimize away the store of the RA to
11110 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
11111 FuncInfo->setLRStoreRequired();
11112 bool isPPC64 = Subtarget.isPPC64();
11113 auto PtrVT = getPointerTy(MF.getDataLayout());
11116 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11118 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
11119 isPPC64 ? MVT::i64 : MVT::i32);
11120 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11121 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
11122 MachinePointerInfo(), false, false, false, 0);
11125 // Just load the return address off the stack.
11126 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
11127 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
11128 MachinePointerInfo(), false, false, false, 0);
11131 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
11132 SelectionDAG &DAG) const {
11134 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11136 MachineFunction &MF = DAG.getMachineFunction();
11137 MachineFrameInfo *MFI = MF.getFrameInfo();
11138 MFI->setFrameAddressIsTaken(true);
11140 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
11141 bool isPPC64 = PtrVT == MVT::i64;
11143 // Naked functions never have a frame pointer, and so we use r1. For all
11144 // other functions, this decision must be delayed until during PEI.
11146 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11147 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11149 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11151 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11154 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11155 FrameAddr, MachinePointerInfo(), false, false,
11160 // FIXME? Maybe this could be a TableGen attribute on some registers and
11161 // this table could be generated automatically from RegInfo.
11162 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
11163 SelectionDAG &DAG) const {
11164 bool isPPC64 = Subtarget.isPPC64();
11165 bool isDarwinABI = Subtarget.isDarwinABI();
11167 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11168 (!isPPC64 && VT != MVT::i32))
11169 report_fatal_error("Invalid register global variable type");
11171 bool is64Bit = isPPC64 && VT == MVT::i64;
11172 unsigned Reg = StringSwitch<unsigned>(RegName)
11173 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11174 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11175 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11176 (is64Bit ? PPC::X13 : PPC::R13))
11181 report_fatal_error("Invalid register name global variable");
11185 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11186 // The PowerPC target isn't yet aware of offsets.
11190 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11192 unsigned Intrinsic) const {
11194 switch (Intrinsic) {
11195 case Intrinsic::ppc_qpx_qvlfd:
11196 case Intrinsic::ppc_qpx_qvlfs:
11197 case Intrinsic::ppc_qpx_qvlfcd:
11198 case Intrinsic::ppc_qpx_qvlfcs:
11199 case Intrinsic::ppc_qpx_qvlfiwa:
11200 case Intrinsic::ppc_qpx_qvlfiwz:
11201 case Intrinsic::ppc_altivec_lvx:
11202 case Intrinsic::ppc_altivec_lvxl:
11203 case Intrinsic::ppc_altivec_lvebx:
11204 case Intrinsic::ppc_altivec_lvehx:
11205 case Intrinsic::ppc_altivec_lvewx:
11206 case Intrinsic::ppc_vsx_lxvd2x:
11207 case Intrinsic::ppc_vsx_lxvw4x: {
11209 switch (Intrinsic) {
11210 case Intrinsic::ppc_altivec_lvebx:
11213 case Intrinsic::ppc_altivec_lvehx:
11216 case Intrinsic::ppc_altivec_lvewx:
11219 case Intrinsic::ppc_vsx_lxvd2x:
11222 case Intrinsic::ppc_qpx_qvlfd:
11225 case Intrinsic::ppc_qpx_qvlfs:
11228 case Intrinsic::ppc_qpx_qvlfcd:
11231 case Intrinsic::ppc_qpx_qvlfcs:
11239 Info.opc = ISD::INTRINSIC_W_CHAIN;
11241 Info.ptrVal = I.getArgOperand(0);
11242 Info.offset = -VT.getStoreSize()+1;
11243 Info.size = 2*VT.getStoreSize()-1;
11246 Info.readMem = true;
11247 Info.writeMem = false;
11250 case Intrinsic::ppc_qpx_qvlfda:
11251 case Intrinsic::ppc_qpx_qvlfsa:
11252 case Intrinsic::ppc_qpx_qvlfcda:
11253 case Intrinsic::ppc_qpx_qvlfcsa:
11254 case Intrinsic::ppc_qpx_qvlfiwaa:
11255 case Intrinsic::ppc_qpx_qvlfiwza: {
11257 switch (Intrinsic) {
11258 case Intrinsic::ppc_qpx_qvlfda:
11261 case Intrinsic::ppc_qpx_qvlfsa:
11264 case Intrinsic::ppc_qpx_qvlfcda:
11267 case Intrinsic::ppc_qpx_qvlfcsa:
11275 Info.opc = ISD::INTRINSIC_W_CHAIN;
11277 Info.ptrVal = I.getArgOperand(0);
11279 Info.size = VT.getStoreSize();
11282 Info.readMem = true;
11283 Info.writeMem = false;
11286 case Intrinsic::ppc_qpx_qvstfd:
11287 case Intrinsic::ppc_qpx_qvstfs:
11288 case Intrinsic::ppc_qpx_qvstfcd:
11289 case Intrinsic::ppc_qpx_qvstfcs:
11290 case Intrinsic::ppc_qpx_qvstfiw:
11291 case Intrinsic::ppc_altivec_stvx:
11292 case Intrinsic::ppc_altivec_stvxl:
11293 case Intrinsic::ppc_altivec_stvebx:
11294 case Intrinsic::ppc_altivec_stvehx:
11295 case Intrinsic::ppc_altivec_stvewx:
11296 case Intrinsic::ppc_vsx_stxvd2x:
11297 case Intrinsic::ppc_vsx_stxvw4x: {
11299 switch (Intrinsic) {
11300 case Intrinsic::ppc_altivec_stvebx:
11303 case Intrinsic::ppc_altivec_stvehx:
11306 case Intrinsic::ppc_altivec_stvewx:
11309 case Intrinsic::ppc_vsx_stxvd2x:
11312 case Intrinsic::ppc_qpx_qvstfd:
11315 case Intrinsic::ppc_qpx_qvstfs:
11318 case Intrinsic::ppc_qpx_qvstfcd:
11321 case Intrinsic::ppc_qpx_qvstfcs:
11329 Info.opc = ISD::INTRINSIC_VOID;
11331 Info.ptrVal = I.getArgOperand(1);
11332 Info.offset = -VT.getStoreSize()+1;
11333 Info.size = 2*VT.getStoreSize()-1;
11336 Info.readMem = false;
11337 Info.writeMem = true;
11340 case Intrinsic::ppc_qpx_qvstfda:
11341 case Intrinsic::ppc_qpx_qvstfsa:
11342 case Intrinsic::ppc_qpx_qvstfcda:
11343 case Intrinsic::ppc_qpx_qvstfcsa:
11344 case Intrinsic::ppc_qpx_qvstfiwa: {
11346 switch (Intrinsic) {
11347 case Intrinsic::ppc_qpx_qvstfda:
11350 case Intrinsic::ppc_qpx_qvstfsa:
11353 case Intrinsic::ppc_qpx_qvstfcda:
11356 case Intrinsic::ppc_qpx_qvstfcsa:
11364 Info.opc = ISD::INTRINSIC_VOID;
11366 Info.ptrVal = I.getArgOperand(1);
11368 Info.size = VT.getStoreSize();
11371 Info.readMem = false;
11372 Info.writeMem = true;
11382 /// getOptimalMemOpType - Returns the target specific optimal type for load
11383 /// and store operations as a result of memset, memcpy, and memmove
11384 /// lowering. If DstAlign is zero that means it's safe to destination
11385 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11386 /// means there isn't a need to check it against alignment requirement,
11387 /// probably because the source does not need to be loaded. If 'IsMemset' is
11388 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11389 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11390 /// source is constant so it does not need to be loaded.
11391 /// It returns EVT::Other if the type should be determined using generic
11392 /// target-independent logic.
11393 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11394 unsigned DstAlign, unsigned SrcAlign,
11395 bool IsMemset, bool ZeroMemset,
11397 MachineFunction &MF) const {
11398 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11399 const Function *F = MF.getFunction();
11400 // When expanding a memset, require at least two QPX instructions to cover
11401 // the cost of loading the value to be stored from the constant pool.
11402 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11403 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11404 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11408 // We should use Altivec/VSX loads and stores when available. For unaligned
11409 // addresses, unaligned VSX loads are only fast starting with the P8.
11410 if (Subtarget.hasAltivec() && Size >= 16 &&
11411 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11412 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11416 if (Subtarget.isPPC64()) {
11423 /// \brief Returns true if it is beneficial to convert a load of a constant
11424 /// to just the constant itself.
11425 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11427 assert(Ty->isIntegerTy());
11429 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11430 if (BitSize == 0 || BitSize > 64)
11435 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11436 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11438 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11439 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11440 return NumBits1 == 64 && NumBits2 == 32;
11443 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11444 if (!VT1.isInteger() || !VT2.isInteger())
11446 unsigned NumBits1 = VT1.getSizeInBits();
11447 unsigned NumBits2 = VT2.getSizeInBits();
11448 return NumBits1 == 64 && NumBits2 == 32;
11451 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11452 // Generally speaking, zexts are not free, but they are free when they can be
11453 // folded with other operations.
11454 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11455 EVT MemVT = LD->getMemoryVT();
11456 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11457 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11458 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11459 LD->getExtensionType() == ISD::ZEXTLOAD))
11463 // FIXME: Add other cases...
11464 // - 32-bit shifts with a zext to i64
11465 // - zext after ctlz, bswap, etc.
11466 // - zext after and by a constant mask
11468 return TargetLowering::isZExtFree(Val, VT2);
11471 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11472 assert(VT.isFloatingPoint());
11476 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11477 return isInt<16>(Imm) || isUInt<16>(Imm);
11480 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11481 return isInt<16>(Imm) || isUInt<16>(Imm);
11484 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11487 bool *Fast) const {
11488 if (DisablePPCUnaligned)
11491 // PowerPC supports unaligned memory access for simple non-vector types.
11492 // Although accessing unaligned addresses is not as efficient as accessing
11493 // aligned addresses, it is generally more efficient than manual expansion,
11494 // and generally only traps for software emulation when crossing page
11497 if (!VT.isSimple())
11500 if (VT.getSimpleVT().isVector()) {
11501 if (Subtarget.hasVSX()) {
11502 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11503 VT != MVT::v4f32 && VT != MVT::v4i32)
11510 if (VT == MVT::ppcf128)
11519 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11520 VT = VT.getScalarType();
11522 if (!VT.isSimple())
11525 switch (VT.getSimpleVT().SimpleTy) {
11537 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11538 // LR is a callee-save register, but we must treat it as clobbered by any call
11539 // site. Hence we include LR in the scratch registers, which are in turn added
11540 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11541 // to CTR, which is used by any indirect call.
11542 static const MCPhysReg ScratchRegs[] = {
11543 PPC::X12, PPC::LR8, PPC::CTR8, 0
11546 return ScratchRegs;
11549 unsigned PPCTargetLowering::getExceptionPointerRegister(
11550 const Constant *PersonalityFn) const {
11551 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3;
11554 unsigned PPCTargetLowering::getExceptionSelectorRegister(
11555 const Constant *PersonalityFn) const {
11556 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4;
11560 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11561 EVT VT , unsigned DefinedValues) const {
11562 if (VT == MVT::v2i64)
11563 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
11565 if (Subtarget.hasQPX()) {
11566 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11570 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11573 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11574 if (DisableILPPref || Subtarget.enableMachineScheduler())
11575 return TargetLowering::getSchedulingPreference(N);
11580 // Create a fast isel object.
11582 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11583 const TargetLibraryInfo *LibInfo) const {
11584 return PPC::createFastISel(FuncInfo, LibInfo);