1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
44 // FIXME: Remove this once soft-float is supported.
45 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
46 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
51 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
52 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
54 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
57 // FIXME: Remove this once the bug has been fixed!
58 extern cl::opt<bool> ANDIGlueBug;
60 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
61 const PPCSubtarget &STI)
62 : TargetLowering(TM), Subtarget(STI) {
63 // Use _setjmp/_longjmp instead of setjmp/longjmp.
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
67 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
68 // arguments are at least 4/8 bytes aligned.
69 bool isPPC64 = Subtarget.isPPC64();
70 setMinStackArgumentAlignment(isPPC64 ? 8:4);
72 // Set up the register classes.
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
77 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
78 for (MVT VT : MVT::integer_valuetypes()) {
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
101 if (Subtarget.useCRBits()) {
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
104 if (isPPC64 || Subtarget.hasFPCVT()) {
105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
106 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
107 isPPC64 ? MVT::i64 : MVT::i32);
108 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
109 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
110 isPPC64 ? MVT::i64 : MVT::i32);
112 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
113 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
116 // PowerPC does not support direct load / store of condition registers
117 setOperationAction(ISD::LOAD, MVT::i1, Custom);
118 setOperationAction(ISD::STORE, MVT::i1, Custom);
120 // FIXME: Remove this once the ANDI glue bug is fixed:
122 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
124 for (MVT VT : MVT::integer_valuetypes()) {
125 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
127 setTruncStoreAction(VT, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
185 Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (MVT VT : MVT::vector_valuetypes()) {
404 // add/sub are legal for all supported vector VT's.
405 setOperationAction(ISD::ADD , VT, Legal);
406 setOperationAction(ISD::SUB , VT, Legal);
408 // Vector instructions introduced in P8
409 if (Subtarget.hasP8Altivec()) {
410 setOperationAction(ISD::CTPOP, VT, Legal);
411 setOperationAction(ISD::CTLZ, VT, Legal);
414 setOperationAction(ISD::CTPOP, VT, Expand);
415 setOperationAction(ISD::CTLZ, VT, Expand);
418 // We promote all shuffles to v16i8.
419 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
420 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
422 // We promote all non-typed operations to v4i32.
423 setOperationAction(ISD::AND , VT, Promote);
424 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
425 setOperationAction(ISD::OR , VT, Promote);
426 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
427 setOperationAction(ISD::XOR , VT, Promote);
428 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
429 setOperationAction(ISD::LOAD , VT, Promote);
430 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
431 setOperationAction(ISD::SELECT, VT, Promote);
432 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
433 setOperationAction(ISD::STORE, VT, Promote);
434 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
436 // No other operations are legal.
437 setOperationAction(ISD::MUL , VT, Expand);
438 setOperationAction(ISD::SDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UDIV, VT, Expand);
441 setOperationAction(ISD::UREM, VT, Expand);
442 setOperationAction(ISD::FDIV, VT, Expand);
443 setOperationAction(ISD::FREM, VT, Expand);
444 setOperationAction(ISD::FNEG, VT, Expand);
445 setOperationAction(ISD::FSQRT, VT, Expand);
446 setOperationAction(ISD::FLOG, VT, Expand);
447 setOperationAction(ISD::FLOG10, VT, Expand);
448 setOperationAction(ISD::FLOG2, VT, Expand);
449 setOperationAction(ISD::FEXP, VT, Expand);
450 setOperationAction(ISD::FEXP2, VT, Expand);
451 setOperationAction(ISD::FSIN, VT, Expand);
452 setOperationAction(ISD::FCOS, VT, Expand);
453 setOperationAction(ISD::FABS, VT, Expand);
454 setOperationAction(ISD::FPOWI, VT, Expand);
455 setOperationAction(ISD::FFLOOR, VT, Expand);
456 setOperationAction(ISD::FCEIL, VT, Expand);
457 setOperationAction(ISD::FTRUNC, VT, Expand);
458 setOperationAction(ISD::FRINT, VT, Expand);
459 setOperationAction(ISD::FNEARBYINT, VT, Expand);
460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
461 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
462 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
463 setOperationAction(ISD::MULHU, VT, Expand);
464 setOperationAction(ISD::MULHS, VT, Expand);
465 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
466 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
467 setOperationAction(ISD::UDIVREM, VT, Expand);
468 setOperationAction(ISD::SDIVREM, VT, Expand);
469 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
470 setOperationAction(ISD::FPOW, VT, Expand);
471 setOperationAction(ISD::BSWAP, VT, Expand);
472 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
473 setOperationAction(ISD::CTTZ, VT, Expand);
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
475 setOperationAction(ISD::VSELECT, VT, Expand);
476 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
478 for (MVT InnerVT : MVT::vector_valuetypes()) {
479 setTruncStoreAction(VT, InnerVT, Expand);
480 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
481 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
482 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
486 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
487 // with merges, splats, etc.
488 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
490 setOperationAction(ISD::AND , MVT::v4i32, Legal);
491 setOperationAction(ISD::OR , MVT::v4i32, Legal);
492 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
493 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
494 setOperationAction(ISD::SELECT, MVT::v4i32,
495 Subtarget.useCRBits() ? Legal : Expand);
496 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
497 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
500 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
501 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
502 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
503 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
504 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
506 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
507 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
508 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
509 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
511 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
512 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
514 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
515 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
516 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
520 if (Subtarget.hasP8Altivec())
521 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
523 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
525 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
526 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
528 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
529 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
531 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
532 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
536 // Altivec does not contain unordered floating-point compare instructions
537 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
538 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
539 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
540 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
542 if (Subtarget.hasVSX()) {
543 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
544 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
546 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
547 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
548 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
549 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
550 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
552 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
554 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
555 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
557 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
558 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
560 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
561 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
562 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
563 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
564 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
566 // Share the Altivec comparison restrictions.
567 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
568 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 if (Subtarget.hasP8Altivec()) {
583 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
584 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
585 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
587 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
590 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
591 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
592 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
594 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
596 // VSX v2i64 only supports non-arithmetic operations.
597 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
598 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
601 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
602 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
603 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
604 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
606 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
608 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
609 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
610 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
611 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
613 // Vector operation legalization checks the result type of
614 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
615 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
616 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
617 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
618 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
620 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
623 if (Subtarget.hasP8Altivec())
624 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
627 if (Subtarget.hasQPX()) {
628 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
629 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
630 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
631 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
633 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
634 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
636 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
637 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
639 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
640 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
642 if (!Subtarget.useCRBits())
643 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
644 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
646 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
647 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
648 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
649 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
650 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
652 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
654 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
655 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
657 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
658 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
659 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
661 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
662 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
663 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
664 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
665 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
666 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
667 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
668 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
669 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
670 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
671 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
673 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
674 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
676 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
677 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
679 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
681 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
682 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
683 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
684 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
686 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
687 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
689 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
690 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
692 if (!Subtarget.useCRBits())
693 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
694 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
696 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
697 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
698 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
699 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
700 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
701 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
702 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
704 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
705 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
707 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
708 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
709 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
710 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
711 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
712 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
713 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
714 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
715 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
716 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
717 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
719 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
720 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
722 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
723 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
725 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
727 setOperationAction(ISD::AND , MVT::v4i1, Legal);
728 setOperationAction(ISD::OR , MVT::v4i1, Legal);
729 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
731 if (!Subtarget.useCRBits())
732 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
733 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
735 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
736 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
738 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
739 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
740 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
741 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
742 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
743 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
744 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
746 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
747 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
749 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
751 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
752 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
753 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
754 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
756 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
757 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
758 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
759 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
761 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
762 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
764 // These need to set FE_INEXACT, and so cannot be vectorized here.
765 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
766 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
768 if (TM.Options.UnsafeFPMath) {
769 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
770 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
772 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
773 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
775 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
776 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
778 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
779 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
783 if (Subtarget.has64BitSupport())
784 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
786 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
789 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
790 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
793 setBooleanContents(ZeroOrOneBooleanContent);
795 if (Subtarget.hasAltivec()) {
796 // Altivec instructions set fields to all zeros or all ones.
797 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
801 // These libcalls are not available in 32-bit.
802 setLibcallName(RTLIB::SHL_I128, nullptr);
803 setLibcallName(RTLIB::SRL_I128, nullptr);
804 setLibcallName(RTLIB::SRA_I128, nullptr);
808 setStackPointerRegisterToSaveRestore(PPC::X1);
809 setExceptionPointerRegister(PPC::X3);
810 setExceptionSelectorRegister(PPC::X4);
812 setStackPointerRegisterToSaveRestore(PPC::R1);
813 setExceptionPointerRegister(PPC::R3);
814 setExceptionSelectorRegister(PPC::R4);
817 // We have target-specific dag combine patterns for the following nodes:
818 setTargetDAGCombine(ISD::SINT_TO_FP);
819 if (Subtarget.hasFPCVT())
820 setTargetDAGCombine(ISD::UINT_TO_FP);
821 setTargetDAGCombine(ISD::LOAD);
822 setTargetDAGCombine(ISD::STORE);
823 setTargetDAGCombine(ISD::BR_CC);
824 if (Subtarget.useCRBits())
825 setTargetDAGCombine(ISD::BRCOND);
826 setTargetDAGCombine(ISD::BSWAP);
827 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
828 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
829 setTargetDAGCombine(ISD::INTRINSIC_VOID);
831 setTargetDAGCombine(ISD::SIGN_EXTEND);
832 setTargetDAGCombine(ISD::ZERO_EXTEND);
833 setTargetDAGCombine(ISD::ANY_EXTEND);
835 if (Subtarget.useCRBits()) {
836 setTargetDAGCombine(ISD::TRUNCATE);
837 setTargetDAGCombine(ISD::SETCC);
838 setTargetDAGCombine(ISD::SELECT_CC);
841 // Use reciprocal estimates.
842 if (TM.Options.UnsafeFPMath) {
843 setTargetDAGCombine(ISD::FDIV);
844 setTargetDAGCombine(ISD::FSQRT);
847 // Darwin long double math library functions have $LDBL128 appended.
848 if (Subtarget.isDarwin()) {
849 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
850 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
851 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
852 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
853 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
854 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
855 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
856 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
857 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
858 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
861 // With 32 condition bits, we don't need to sink (and duplicate) compares
862 // aggressively in CodeGenPrep.
863 if (Subtarget.useCRBits()) {
864 setHasMultipleConditionRegisters();
865 setJumpIsExpensive();
868 setMinFunctionAlignment(2);
869 if (Subtarget.isDarwin())
870 setPrefFunctionAlignment(4);
872 switch (Subtarget.getDarwinDirective()) {
876 case PPC::DIR_E500mc:
885 setPrefFunctionAlignment(4);
886 setPrefLoopAlignment(4);
890 setInsertFencesForAtomic(true);
892 if (Subtarget.enableMachineScheduler())
893 setSchedulingPreference(Sched::Source);
895 setSchedulingPreference(Sched::Hybrid);
897 computeRegisterProperties(STI.getRegisterInfo());
899 // The Freescale cores do better with aggressive inlining of memcpy and
900 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
901 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
902 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
903 MaxStoresPerMemset = 32;
904 MaxStoresPerMemsetOptSize = 16;
905 MaxStoresPerMemcpy = 32;
906 MaxStoresPerMemcpyOptSize = 8;
907 MaxStoresPerMemmove = 32;
908 MaxStoresPerMemmoveOptSize = 8;
909 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
910 // The A2 also benefits from (very) aggressive inlining of memcpy and
911 // friends. The overhead of a the function call, even when warm, can be
912 // over one hundred cycles.
913 MaxStoresPerMemset = 128;
914 MaxStoresPerMemcpy = 128;
915 MaxStoresPerMemmove = 128;
919 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
920 /// the desired ByVal argument alignment.
921 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
922 unsigned MaxMaxAlign) {
923 if (MaxAlign == MaxMaxAlign)
925 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
926 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
928 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
930 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
931 unsigned EltAlign = 0;
932 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
933 if (EltAlign > MaxAlign)
935 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
936 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
937 unsigned EltAlign = 0;
938 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
939 if (EltAlign > MaxAlign)
941 if (MaxAlign == MaxMaxAlign)
947 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
948 /// function arguments in the caller parameter area.
949 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
950 // Darwin passes everything on 4 byte boundary.
951 if (Subtarget.isDarwin())
954 // 16byte and wider vectors are passed on 16byte boundary.
955 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
956 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
957 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
958 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
962 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
964 default: return nullptr;
965 case PPCISD::FSEL: return "PPCISD::FSEL";
966 case PPCISD::FCFID: return "PPCISD::FCFID";
967 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
968 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
969 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
970 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
971 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
972 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
973 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
974 case PPCISD::FRE: return "PPCISD::FRE";
975 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
976 case PPCISD::STFIWX: return "PPCISD::STFIWX";
977 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
978 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
979 case PPCISD::VPERM: return "PPCISD::VPERM";
980 case PPCISD::CMPB: return "PPCISD::CMPB";
981 case PPCISD::Hi: return "PPCISD::Hi";
982 case PPCISD::Lo: return "PPCISD::Lo";
983 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
984 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
985 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
986 case PPCISD::SRL: return "PPCISD::SRL";
987 case PPCISD::SRA: return "PPCISD::SRA";
988 case PPCISD::SHL: return "PPCISD::SHL";
989 case PPCISD::CALL: return "PPCISD::CALL";
990 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
991 case PPCISD::MTCTR: return "PPCISD::MTCTR";
992 case PPCISD::BCTRL: return "PPCISD::BCTRL";
993 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
994 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
995 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
996 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
997 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
998 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
999 case PPCISD::VCMP: return "PPCISD::VCMP";
1000 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1001 case PPCISD::LBRX: return "PPCISD::LBRX";
1002 case PPCISD::STBRX: return "PPCISD::STBRX";
1003 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1004 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1005 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1006 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1007 case PPCISD::BDZ: return "PPCISD::BDZ";
1008 case PPCISD::MFFS: return "PPCISD::MFFS";
1009 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1010 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1011 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1012 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1013 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1014 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1015 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1016 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1017 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1018 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1019 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1020 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1021 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1022 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1023 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1024 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1025 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1026 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1027 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1028 case PPCISD::SC: return "PPCISD::SC";
1029 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1030 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1031 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1032 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1033 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1034 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1038 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &C, EVT VT) const {
1040 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1042 if (Subtarget.hasQPX())
1043 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1045 return VT.changeVectorElementTypeToInteger();
1048 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1049 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1053 //===----------------------------------------------------------------------===//
1054 // Node matching predicates, for use by the tblgen matching code.
1055 //===----------------------------------------------------------------------===//
1057 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1058 static bool isFloatingPointZero(SDValue Op) {
1059 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1060 return CFP->getValueAPF().isZero();
1061 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1062 // Maybe this has already been legalized into the constant pool?
1063 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1064 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1065 return CFP->getValueAPF().isZero();
1070 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1071 /// true if Op is undef or if it matches the specified value.
1072 static bool isConstantOrUndef(int Op, int Val) {
1073 return Op < 0 || Op == Val;
1076 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1077 /// VPKUHUM instruction.
1078 /// The ShuffleKind distinguishes between big-endian operations with
1079 /// two different inputs (0), either-endian operations with two identical
1080 /// inputs (1), and little-endian operantion with two different inputs (2).
1081 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1082 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1083 SelectionDAG &DAG) {
1084 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1085 if (ShuffleKind == 0) {
1088 for (unsigned i = 0; i != 16; ++i)
1089 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1091 } else if (ShuffleKind == 2) {
1094 for (unsigned i = 0; i != 16; ++i)
1095 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1097 } else if (ShuffleKind == 1) {
1098 unsigned j = IsLE ? 0 : 1;
1099 for (unsigned i = 0; i != 8; ++i)
1100 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1101 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1107 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1108 /// VPKUWUM instruction.
1109 /// The ShuffleKind distinguishes between big-endian operations with
1110 /// two different inputs (0), either-endian operations with two identical
1111 /// inputs (1), and little-endian operantion with two different inputs (2).
1112 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1113 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1114 SelectionDAG &DAG) {
1115 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1116 if (ShuffleKind == 0) {
1119 for (unsigned i = 0; i != 16; i += 2)
1120 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1121 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1123 } else if (ShuffleKind == 2) {
1126 for (unsigned i = 0; i != 16; i += 2)
1127 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1128 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1130 } else if (ShuffleKind == 1) {
1131 unsigned j = IsLE ? 0 : 2;
1132 for (unsigned i = 0; i != 8; i += 2)
1133 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1134 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1135 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1136 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1142 /// isVMerge - Common function, used to match vmrg* shuffles.
1144 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1145 unsigned LHSStart, unsigned RHSStart) {
1146 if (N->getValueType(0) != MVT::v16i8)
1148 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1149 "Unsupported merge size!");
1151 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1152 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1153 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1154 LHSStart+j+i*UnitSize) ||
1155 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1156 RHSStart+j+i*UnitSize))
1162 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1163 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1164 /// The ShuffleKind distinguishes between big-endian merges with two
1165 /// different inputs (0), either-endian merges with two identical inputs (1),
1166 /// and little-endian merges with two different inputs (2). For the latter,
1167 /// the input operands are swapped (see PPCInstrAltivec.td).
1168 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1169 unsigned ShuffleKind, SelectionDAG &DAG) {
1170 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1171 if (ShuffleKind == 1) // unary
1172 return isVMerge(N, UnitSize, 0, 0);
1173 else if (ShuffleKind == 2) // swapped
1174 return isVMerge(N, UnitSize, 0, 16);
1178 if (ShuffleKind == 1) // unary
1179 return isVMerge(N, UnitSize, 8, 8);
1180 else if (ShuffleKind == 0) // normal
1181 return isVMerge(N, UnitSize, 8, 24);
1187 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1188 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1189 /// The ShuffleKind distinguishes between big-endian merges with two
1190 /// different inputs (0), either-endian merges with two identical inputs (1),
1191 /// and little-endian merges with two different inputs (2). For the latter,
1192 /// the input operands are swapped (see PPCInstrAltivec.td).
1193 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1194 unsigned ShuffleKind, SelectionDAG &DAG) {
1195 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1196 if (ShuffleKind == 1) // unary
1197 return isVMerge(N, UnitSize, 8, 8);
1198 else if (ShuffleKind == 2) // swapped
1199 return isVMerge(N, UnitSize, 8, 24);
1203 if (ShuffleKind == 1) // unary
1204 return isVMerge(N, UnitSize, 0, 0);
1205 else if (ShuffleKind == 0) // normal
1206 return isVMerge(N, UnitSize, 0, 16);
1213 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1214 /// amount, otherwise return -1.
1215 /// The ShuffleKind distinguishes between big-endian operations with two
1216 /// different inputs (0), either-endian operations with two identical inputs
1217 /// (1), and little-endian operations with two different inputs (2). For the
1218 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1219 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1220 SelectionDAG &DAG) {
1221 if (N->getValueType(0) != MVT::v16i8)
1224 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1226 // Find the first non-undef value in the shuffle mask.
1228 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1231 if (i == 16) return -1; // all undef.
1233 // Otherwise, check to see if the rest of the elements are consecutively
1234 // numbered from this value.
1235 unsigned ShiftAmt = SVOp->getMaskElt(i);
1236 if (ShiftAmt < i) return -1;
1239 bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1241 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1242 // Check the rest of the elements to see if they are consecutive.
1243 for (++i; i != 16; ++i)
1244 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1246 } else if (ShuffleKind == 1) {
1247 // Check the rest of the elements to see if they are consecutive.
1248 for (++i; i != 16; ++i)
1249 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1254 if (ShuffleKind == 2 && isLE)
1255 ShiftAmt = 16 - ShiftAmt;
1260 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1261 /// specifies a splat of a single element that is suitable for input to
1262 /// VSPLTB/VSPLTH/VSPLTW.
1263 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1264 assert(N->getValueType(0) == MVT::v16i8 &&
1265 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1267 // This is a splat operation if each element of the permute is the same, and
1268 // if the value doesn't reference the second vector.
1269 unsigned ElementBase = N->getMaskElt(0);
1271 // FIXME: Handle UNDEF elements too!
1272 if (ElementBase >= 16)
1275 // Check that the indices are consecutive, in the case of a multi-byte element
1276 // splatted with a v16i8 mask.
1277 for (unsigned i = 1; i != EltSize; ++i)
1278 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1281 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1282 if (N->getMaskElt(i) < 0) continue;
1283 for (unsigned j = 0; j != EltSize; ++j)
1284 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1290 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1292 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1293 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1295 APInt APVal, APUndef;
1299 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1300 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1301 return CFP->getValueAPF().isNegZero();
1306 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1307 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1308 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1309 SelectionDAG &DAG) {
1310 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1311 assert(isSplatShuffleMask(SVOp, EltSize));
1312 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1313 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1315 return SVOp->getMaskElt(0) / EltSize;
1318 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1319 /// by using a vspltis[bhw] instruction of the specified element size, return
1320 /// the constant being splatted. The ByteSize field indicates the number of
1321 /// bytes of each element [124] -> [bhw].
1322 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1323 SDValue OpVal(nullptr, 0);
1325 // If ByteSize of the splat is bigger than the element size of the
1326 // build_vector, then we have a case where we are checking for a splat where
1327 // multiple elements of the buildvector are folded together into a single
1328 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1329 unsigned EltSize = 16/N->getNumOperands();
1330 if (EltSize < ByteSize) {
1331 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1332 SDValue UniquedVals[4];
1333 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1335 // See if all of the elements in the buildvector agree across.
1336 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1337 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1338 // If the element isn't a constant, bail fully out.
1339 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1342 if (!UniquedVals[i&(Multiple-1)].getNode())
1343 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1344 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1345 return SDValue(); // no match.
1348 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1349 // either constant or undef values that are identical for each chunk. See
1350 // if these chunks can form into a larger vspltis*.
1352 // Check to see if all of the leading entries are either 0 or -1. If
1353 // neither, then this won't fit into the immediate field.
1354 bool LeadingZero = true;
1355 bool LeadingOnes = true;
1356 for (unsigned i = 0; i != Multiple-1; ++i) {
1357 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1359 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1360 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1362 // Finally, check the least significant entry.
1364 if (!UniquedVals[Multiple-1].getNode())
1365 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1366 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1368 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1371 if (!UniquedVals[Multiple-1].getNode())
1372 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1373 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1374 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1375 return DAG.getTargetConstant(Val, MVT::i32);
1381 // Check to see if this buildvec has a single non-undef value in its elements.
1382 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1383 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1384 if (!OpVal.getNode())
1385 OpVal = N->getOperand(i);
1386 else if (OpVal != N->getOperand(i))
1390 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1392 unsigned ValSizeInBytes = EltSize;
1394 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1395 Value = CN->getZExtValue();
1396 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1397 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1398 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1401 // If the splat value is larger than the element value, then we can never do
1402 // this splat. The only case that we could fit the replicated bits into our
1403 // immediate field for would be zero, and we prefer to use vxor for it.
1404 if (ValSizeInBytes < ByteSize) return SDValue();
1406 // If the element value is larger than the splat value, check if it consists
1407 // of a repeated bit pattern of size ByteSize.
1408 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1411 // Properly sign extend the value.
1412 int MaskVal = SignExtend32(Value, ByteSize * 8);
1414 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1415 if (MaskVal == 0) return SDValue();
1417 // Finally, if this value fits in a 5 bit sext field, return it
1418 if (SignExtend32<5>(MaskVal) == MaskVal)
1419 return DAG.getTargetConstant(MaskVal, MVT::i32);
1423 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1424 /// amount, otherwise return -1.
1425 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1426 EVT VT = N->getValueType(0);
1427 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1430 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1432 // Find the first non-undef value in the shuffle mask.
1434 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1437 if (i == 4) return -1; // all undef.
1439 // Otherwise, check to see if the rest of the elements are consecutively
1440 // numbered from this value.
1441 unsigned ShiftAmt = SVOp->getMaskElt(i);
1442 if (ShiftAmt < i) return -1;
1445 // Check the rest of the elements to see if they are consecutive.
1446 for (++i; i != 4; ++i)
1447 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1453 //===----------------------------------------------------------------------===//
1454 // Addressing Mode Selection
1455 //===----------------------------------------------------------------------===//
1457 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1458 /// or 64-bit immediate, and if the value can be accurately represented as a
1459 /// sign extension from a 16-bit value. If so, this returns true and the
1461 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1462 if (!isa<ConstantSDNode>(N))
1465 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1466 if (N->getValueType(0) == MVT::i32)
1467 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1469 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1471 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1472 return isIntS16Immediate(Op.getNode(), Imm);
1476 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1477 /// can be represented as an indexed [r+r] operation. Returns false if it
1478 /// can be more efficiently represented with [r+imm].
1479 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1481 SelectionDAG &DAG) const {
1483 if (N.getOpcode() == ISD::ADD) {
1484 if (isIntS16Immediate(N.getOperand(1), imm))
1485 return false; // r+i
1486 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1487 return false; // r+i
1489 Base = N.getOperand(0);
1490 Index = N.getOperand(1);
1492 } else if (N.getOpcode() == ISD::OR) {
1493 if (isIntS16Immediate(N.getOperand(1), imm))
1494 return false; // r+i can fold it if we can.
1496 // If this is an or of disjoint bitfields, we can codegen this as an add
1497 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1499 APInt LHSKnownZero, LHSKnownOne;
1500 APInt RHSKnownZero, RHSKnownOne;
1501 DAG.computeKnownBits(N.getOperand(0),
1502 LHSKnownZero, LHSKnownOne);
1504 if (LHSKnownZero.getBoolValue()) {
1505 DAG.computeKnownBits(N.getOperand(1),
1506 RHSKnownZero, RHSKnownOne);
1507 // If all of the bits are known zero on the LHS or RHS, the add won't
1509 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1510 Base = N.getOperand(0);
1511 Index = N.getOperand(1);
1520 // If we happen to be doing an i64 load or store into a stack slot that has
1521 // less than a 4-byte alignment, then the frame-index elimination may need to
1522 // use an indexed load or store instruction (because the offset may not be a
1523 // multiple of 4). The extra register needed to hold the offset comes from the
1524 // register scavenger, and it is possible that the scavenger will need to use
1525 // an emergency spill slot. As a result, we need to make sure that a spill slot
1526 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1528 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1529 // FIXME: This does not handle the LWA case.
1533 // NOTE: We'll exclude negative FIs here, which come from argument
1534 // lowering, because there are no known test cases triggering this problem
1535 // using packed structures (or similar). We can remove this exclusion if
1536 // we find such a test case. The reason why this is so test-case driven is
1537 // because this entire 'fixup' is only to prevent crashes (from the
1538 // register scavenger) on not-really-valid inputs. For example, if we have:
1540 // %b = bitcast i1* %a to i64*
1541 // store i64* a, i64 b
1542 // then the store should really be marked as 'align 1', but is not. If it
1543 // were marked as 'align 1' then the indexed form would have been
1544 // instruction-selected initially, and the problem this 'fixup' is preventing
1545 // won't happen regardless.
1549 MachineFunction &MF = DAG.getMachineFunction();
1550 MachineFrameInfo *MFI = MF.getFrameInfo();
1552 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1556 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1557 FuncInfo->setHasNonRISpills();
1560 /// Returns true if the address N can be represented by a base register plus
1561 /// a signed 16-bit displacement [r+imm], and if it is not better
1562 /// represented as reg+reg. If Aligned is true, only accept displacements
1563 /// suitable for STD and friends, i.e. multiples of 4.
1564 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1567 bool Aligned) const {
1568 // FIXME dl should come from parent load or store, not from address
1570 // If this can be more profitably realized as r+r, fail.
1571 if (SelectAddressRegReg(N, Disp, Base, DAG))
1574 if (N.getOpcode() == ISD::ADD) {
1576 if (isIntS16Immediate(N.getOperand(1), imm) &&
1577 (!Aligned || (imm & 3) == 0)) {
1578 Disp = DAG.getTargetConstant(imm, N.getValueType());
1579 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1580 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1581 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1583 Base = N.getOperand(0);
1585 return true; // [r+i]
1586 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1587 // Match LOAD (ADD (X, Lo(G))).
1588 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1589 && "Cannot handle constant offsets yet!");
1590 Disp = N.getOperand(1).getOperand(0); // The global address.
1591 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1592 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1593 Disp.getOpcode() == ISD::TargetConstantPool ||
1594 Disp.getOpcode() == ISD::TargetJumpTable);
1595 Base = N.getOperand(0);
1596 return true; // [&g+r]
1598 } else if (N.getOpcode() == ISD::OR) {
1600 if (isIntS16Immediate(N.getOperand(1), imm) &&
1601 (!Aligned || (imm & 3) == 0)) {
1602 // If this is an or of disjoint bitfields, we can codegen this as an add
1603 // (for better address arithmetic) if the LHS and RHS of the OR are
1604 // provably disjoint.
1605 APInt LHSKnownZero, LHSKnownOne;
1606 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1608 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1609 // If all of the bits are known zero on the LHS or RHS, the add won't
1611 if (FrameIndexSDNode *FI =
1612 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1613 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1614 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1616 Base = N.getOperand(0);
1618 Disp = DAG.getTargetConstant(imm, N.getValueType());
1622 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1623 // Loading from a constant address.
1625 // If this address fits entirely in a 16-bit sext immediate field, codegen
1628 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1629 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1630 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1631 CN->getValueType(0));
1635 // Handle 32-bit sext immediates with LIS + addr mode.
1636 if ((CN->getValueType(0) == MVT::i32 ||
1637 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1638 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1639 int Addr = (int)CN->getZExtValue();
1641 // Otherwise, break this down into an LIS + disp.
1642 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1644 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1645 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1646 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1651 Disp = DAG.getTargetConstant(0, getPointerTy());
1652 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1653 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1654 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1657 return true; // [r+0]
1660 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1661 /// represented as an indexed [r+r] operation.
1662 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1664 SelectionDAG &DAG) const {
1665 // Check to see if we can easily represent this as an [r+r] address. This
1666 // will fail if it thinks that the address is more profitably represented as
1667 // reg+imm, e.g. where imm = 0.
1668 if (SelectAddressRegReg(N, Base, Index, DAG))
1671 // If the operand is an addition, always emit this as [r+r], since this is
1672 // better (for code size, and execution, as the memop does the add for free)
1673 // than emitting an explicit add.
1674 if (N.getOpcode() == ISD::ADD) {
1675 Base = N.getOperand(0);
1676 Index = N.getOperand(1);
1680 // Otherwise, do it the hard way, using R0 as the base register.
1681 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1687 /// getPreIndexedAddressParts - returns true by value, base pointer and
1688 /// offset pointer and addressing mode by reference if the node's address
1689 /// can be legally represented as pre-indexed load / store address.
1690 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1692 ISD::MemIndexedMode &AM,
1693 SelectionDAG &DAG) const {
1694 if (DisablePPCPreinc) return false;
1700 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1701 Ptr = LD->getBasePtr();
1702 VT = LD->getMemoryVT();
1703 Alignment = LD->getAlignment();
1704 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1705 Ptr = ST->getBasePtr();
1706 VT = ST->getMemoryVT();
1707 Alignment = ST->getAlignment();
1712 // PowerPC doesn't have preinc load/store instructions for vectors (except
1713 // for QPX, which does have preinc r+r forms).
1714 if (VT.isVector()) {
1715 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1717 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1723 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1725 // Common code will reject creating a pre-inc form if the base pointer
1726 // is a frame index, or if N is a store and the base pointer is either
1727 // the same as or a predecessor of the value being stored. Check for
1728 // those situations here, and try with swapped Base/Offset instead.
1731 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1734 SDValue Val = cast<StoreSDNode>(N)->getValue();
1735 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1740 std::swap(Base, Offset);
1746 // LDU/STU can only handle immediates that are a multiple of 4.
1747 if (VT != MVT::i64) {
1748 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1751 // LDU/STU need an address with at least 4-byte alignment.
1755 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1759 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1760 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1761 // sext i32 to i64 when addr mode is r+i.
1762 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1763 LD->getExtensionType() == ISD::SEXTLOAD &&
1764 isa<ConstantSDNode>(Offset))
1772 //===----------------------------------------------------------------------===//
1773 // LowerOperation implementation
1774 //===----------------------------------------------------------------------===//
1776 /// GetLabelAccessInfo - Return true if we should reference labels using a
1777 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1778 static bool GetLabelAccessInfo(const TargetMachine &TM,
1779 const PPCSubtarget &Subtarget,
1780 unsigned &HiOpFlags, unsigned &LoOpFlags,
1781 const GlobalValue *GV = nullptr) {
1782 HiOpFlags = PPCII::MO_HA;
1783 LoOpFlags = PPCII::MO_LO;
1785 // Don't use the pic base if not in PIC relocation model.
1786 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1789 HiOpFlags |= PPCII::MO_PIC_FLAG;
1790 LoOpFlags |= PPCII::MO_PIC_FLAG;
1793 // If this is a reference to a global value that requires a non-lazy-ptr, make
1794 // sure that instruction lowering adds it.
1795 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1796 HiOpFlags |= PPCII::MO_NLP_FLAG;
1797 LoOpFlags |= PPCII::MO_NLP_FLAG;
1799 if (GV->hasHiddenVisibility()) {
1800 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1801 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1808 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1809 SelectionDAG &DAG) {
1810 EVT PtrVT = HiPart.getValueType();
1811 SDValue Zero = DAG.getConstant(0, PtrVT);
1814 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1815 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1817 // With PIC, the first instruction is actually "GR+hi(&G)".
1819 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1820 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1822 // Generate non-pic code that has direct accesses to the constant pool.
1823 // The address of the global is just (hi(&g)+lo(&g)).
1824 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1827 static void setUsesTOCBasePtr(MachineFunction &MF) {
1828 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1829 FuncInfo->setUsesTOCBasePtr();
1832 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1833 setUsesTOCBasePtr(DAG.getMachineFunction());
1836 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
1838 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1839 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
1840 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
1842 SDValue Ops[] = { GA, Reg };
1843 return DAG.getMemIntrinsicNode(PPCISD::TOC_ENTRY, dl,
1844 DAG.getVTList(VT, MVT::Other), Ops, VT,
1845 MachinePointerInfo::getGOT(), 0, false, true,
1849 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1850 SelectionDAG &DAG) const {
1851 EVT PtrVT = Op.getValueType();
1852 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1853 const Constant *C = CP->getConstVal();
1855 // 64-bit SVR4 ABI code is always position-independent.
1856 // The actual address of the GlobalValue is stored in the TOC.
1857 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1858 setUsesTOCBasePtr(DAG);
1859 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1860 return getTOCEntry(DAG, SDLoc(CP), true, GA);
1863 unsigned MOHiFlag, MOLoFlag;
1865 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1867 if (isPIC && Subtarget.isSVR4ABI()) {
1868 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1869 PPCII::MO_PIC_FLAG);
1870 return getTOCEntry(DAG, SDLoc(CP), false, GA);
1874 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1876 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1877 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1880 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1881 EVT PtrVT = Op.getValueType();
1882 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1884 // 64-bit SVR4 ABI code is always position-independent.
1885 // The actual address of the GlobalValue is stored in the TOC.
1886 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1887 setUsesTOCBasePtr(DAG);
1888 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1889 return getTOCEntry(DAG, SDLoc(JT), true, GA);
1892 unsigned MOHiFlag, MOLoFlag;
1894 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1896 if (isPIC && Subtarget.isSVR4ABI()) {
1897 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1898 PPCII::MO_PIC_FLAG);
1899 return getTOCEntry(DAG, SDLoc(GA), false, GA);
1902 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1903 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1904 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1907 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1908 SelectionDAG &DAG) const {
1909 EVT PtrVT = Op.getValueType();
1910 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1911 const BlockAddress *BA = BASDN->getBlockAddress();
1913 // 64-bit SVR4 ABI code is always position-independent.
1914 // The actual BlockAddress is stored in the TOC.
1915 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1916 setUsesTOCBasePtr(DAG);
1917 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1918 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
1921 unsigned MOHiFlag, MOLoFlag;
1923 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1924 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1925 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1926 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1929 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1930 SelectionDAG &DAG) const {
1932 // FIXME: TLS addresses currently use medium model code sequences,
1933 // which is the most useful form. Eventually support for small and
1934 // large models could be added if users need it, at the cost of
1935 // additional complexity.
1936 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1938 const GlobalValue *GV = GA->getGlobal();
1939 EVT PtrVT = getPointerTy();
1940 bool is64bit = Subtarget.isPPC64();
1941 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1942 PICLevel::Level picLevel = M->getPICLevel();
1944 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1946 if (Model == TLSModel::LocalExec) {
1947 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1948 PPCII::MO_TPREL_HA);
1949 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1950 PPCII::MO_TPREL_LO);
1951 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1952 is64bit ? MVT::i64 : MVT::i32);
1953 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1954 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1957 if (Model == TLSModel::InitialExec) {
1958 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1959 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1963 setUsesTOCBasePtr(DAG);
1964 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1965 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1966 PtrVT, GOTReg, TGA);
1968 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1969 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1970 PtrVT, TGA, GOTPtr);
1971 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1974 if (Model == TLSModel::GeneralDynamic) {
1975 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1978 setUsesTOCBasePtr(DAG);
1979 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1980 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1983 if (picLevel == PICLevel::Small)
1984 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1986 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1988 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
1992 if (Model == TLSModel::LocalDynamic) {
1993 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1996 setUsesTOCBasePtr(DAG);
1997 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1998 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2001 if (picLevel == PICLevel::Small)
2002 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2004 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2006 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2007 PtrVT, GOTPtr, TGA, TGA);
2008 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2009 PtrVT, TLSAddr, TGA);
2010 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2013 llvm_unreachable("Unknown TLS model!");
2016 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2017 SelectionDAG &DAG) const {
2018 EVT PtrVT = Op.getValueType();
2019 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2021 const GlobalValue *GV = GSDN->getGlobal();
2023 // 64-bit SVR4 ABI code is always position-independent.
2024 // The actual address of the GlobalValue is stored in the TOC.
2025 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2026 setUsesTOCBasePtr(DAG);
2027 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2028 return getTOCEntry(DAG, DL, true, GA);
2031 unsigned MOHiFlag, MOLoFlag;
2033 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2035 if (isPIC && Subtarget.isSVR4ABI()) {
2036 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2038 PPCII::MO_PIC_FLAG);
2039 return getTOCEntry(DAG, DL, false, GA);
2043 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2045 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2047 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2049 // If the global reference is actually to a non-lazy-pointer, we have to do an
2050 // extra load to get the address of the global.
2051 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2052 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2053 false, false, false, 0);
2057 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2058 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2061 if (Op.getValueType() == MVT::v2i64) {
2062 // When the operands themselves are v2i64 values, we need to do something
2063 // special because VSX has no underlying comparison operations for these.
2064 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2065 // Equality can be handled by casting to the legal type for Altivec
2066 // comparisons, everything else needs to be expanded.
2067 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2068 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2069 DAG.getSetCC(dl, MVT::v4i32,
2070 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2071 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2078 // We handle most of these in the usual way.
2082 // If we're comparing for equality to zero, expose the fact that this is
2083 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2084 // fold the new nodes.
2085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2086 if (C->isNullValue() && CC == ISD::SETEQ) {
2087 EVT VT = Op.getOperand(0).getValueType();
2088 SDValue Zext = Op.getOperand(0);
2089 if (VT.bitsLT(MVT::i32)) {
2091 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2093 unsigned Log2b = Log2_32(VT.getSizeInBits());
2094 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2095 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2096 DAG.getConstant(Log2b, MVT::i32));
2097 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2099 // Leave comparisons against 0 and -1 alone for now, since they're usually
2100 // optimized. FIXME: revisit this when we can custom lower all setcc
2102 if (C->isAllOnesValue() || C->isNullValue())
2106 // If we have an integer seteq/setne, turn it into a compare against zero
2107 // by xor'ing the rhs with the lhs, which is faster than setting a
2108 // condition register, reading it back out, and masking the correct bit. The
2109 // normal approach here uses sub to do this instead of xor. Using xor exposes
2110 // the result to other bit-twiddling opportunities.
2111 EVT LHSVT = Op.getOperand(0).getValueType();
2112 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2113 EVT VT = Op.getValueType();
2114 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2116 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
2121 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2122 const PPCSubtarget &Subtarget) const {
2123 SDNode *Node = Op.getNode();
2124 EVT VT = Node->getValueType(0);
2125 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2126 SDValue InChain = Node->getOperand(0);
2127 SDValue VAListPtr = Node->getOperand(1);
2128 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2131 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2134 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2135 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2136 false, false, false, 0);
2137 InChain = GprIndex.getValue(1);
2139 if (VT == MVT::i64) {
2140 // Check if GprIndex is even
2141 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2142 DAG.getConstant(1, MVT::i32));
2143 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2144 DAG.getConstant(0, MVT::i32), ISD::SETNE);
2145 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2146 DAG.getConstant(1, MVT::i32));
2147 // Align GprIndex to be even if it isn't
2148 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2152 // fpr index is 1 byte after gpr
2153 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2154 DAG.getConstant(1, MVT::i32));
2157 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2158 FprPtr, MachinePointerInfo(SV), MVT::i8,
2159 false, false, false, 0);
2160 InChain = FprIndex.getValue(1);
2162 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2163 DAG.getConstant(8, MVT::i32));
2165 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2166 DAG.getConstant(4, MVT::i32));
2169 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2170 MachinePointerInfo(), false, false,
2172 InChain = OverflowArea.getValue(1);
2174 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2175 MachinePointerInfo(), false, false,
2177 InChain = RegSaveArea.getValue(1);
2179 // select overflow_area if index > 8
2180 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2181 DAG.getConstant(8, MVT::i32), ISD::SETLT);
2183 // adjustment constant gpr_index * 4/8
2184 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2185 VT.isInteger() ? GprIndex : FprIndex,
2186 DAG.getConstant(VT.isInteger() ? 4 : 8,
2189 // OurReg = RegSaveArea + RegConstant
2190 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2193 // Floating types are 32 bytes into RegSaveArea
2194 if (VT.isFloatingPoint())
2195 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2196 DAG.getConstant(32, MVT::i32));
2198 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2199 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2200 VT.isInteger() ? GprIndex : FprIndex,
2201 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
2204 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2205 VT.isInteger() ? VAListPtr : FprPtr,
2206 MachinePointerInfo(SV),
2207 MVT::i8, false, false, 0);
2209 // determine if we should load from reg_save_area or overflow_area
2210 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2212 // increase overflow_area by 4/8 if gpr/fpr > 8
2213 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2214 DAG.getConstant(VT.isInteger() ? 4 : 8,
2217 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2220 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2222 MachinePointerInfo(),
2223 MVT::i32, false, false, 0);
2225 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2226 false, false, false, 0);
2229 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2230 const PPCSubtarget &Subtarget) const {
2231 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2233 // We have to copy the entire va_list struct:
2234 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2235 return DAG.getMemcpy(Op.getOperand(0), Op,
2236 Op.getOperand(1), Op.getOperand(2),
2237 DAG.getConstant(12, MVT::i32), 8, false, true,
2238 MachinePointerInfo(), MachinePointerInfo());
2241 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2242 SelectionDAG &DAG) const {
2243 return Op.getOperand(0);
2246 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2247 SelectionDAG &DAG) const {
2248 SDValue Chain = Op.getOperand(0);
2249 SDValue Trmp = Op.getOperand(1); // trampoline
2250 SDValue FPtr = Op.getOperand(2); // nested function
2251 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2254 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2255 bool isPPC64 = (PtrVT == MVT::i64);
2257 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2260 TargetLowering::ArgListTy Args;
2261 TargetLowering::ArgListEntry Entry;
2263 Entry.Ty = IntPtrTy;
2264 Entry.Node = Trmp; Args.push_back(Entry);
2266 // TrampSize == (isPPC64 ? 48 : 40);
2267 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2268 isPPC64 ? MVT::i64 : MVT::i32);
2269 Args.push_back(Entry);
2271 Entry.Node = FPtr; Args.push_back(Entry);
2272 Entry.Node = Nest; Args.push_back(Entry);
2274 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2275 TargetLowering::CallLoweringInfo CLI(DAG);
2276 CLI.setDebugLoc(dl).setChain(Chain)
2277 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2278 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2279 std::move(Args), 0);
2281 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2282 return CallResult.second;
2285 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2286 const PPCSubtarget &Subtarget) const {
2287 MachineFunction &MF = DAG.getMachineFunction();
2288 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2292 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2293 // vastart just stores the address of the VarArgsFrameIndex slot into the
2294 // memory location argument.
2295 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2296 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2297 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2298 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2299 MachinePointerInfo(SV),
2303 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2304 // We suppose the given va_list is already allocated.
2307 // char gpr; /* index into the array of 8 GPRs
2308 // * stored in the register save area
2309 // * gpr=0 corresponds to r3,
2310 // * gpr=1 to r4, etc.
2312 // char fpr; /* index into the array of 8 FPRs
2313 // * stored in the register save area
2314 // * fpr=0 corresponds to f1,
2315 // * fpr=1 to f2, etc.
2317 // char *overflow_arg_area;
2318 // /* location on stack that holds
2319 // * the next overflow argument
2321 // char *reg_save_area;
2322 // /* where r3:r10 and f1:f8 (if saved)
2328 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2329 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2332 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2334 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2336 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2339 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2340 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2342 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2343 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2345 uint64_t FPROffset = 1;
2346 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2348 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2350 // Store first byte : number of int regs
2351 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2353 MachinePointerInfo(SV),
2354 MVT::i8, false, false, 0);
2355 uint64_t nextOffset = FPROffset;
2356 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2359 // Store second byte : number of float regs
2360 SDValue secondStore =
2361 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2362 MachinePointerInfo(SV, nextOffset), MVT::i8,
2364 nextOffset += StackOffset;
2365 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2367 // Store second word : arguments given on stack
2368 SDValue thirdStore =
2369 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2370 MachinePointerInfo(SV, nextOffset),
2372 nextOffset += FrameOffset;
2373 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2375 // Store third word : arguments given in registers
2376 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2377 MachinePointerInfo(SV, nextOffset),
2382 #include "PPCGenCallingConv.inc"
2384 // Function whose sole purpose is to kill compiler warnings
2385 // stemming from unused functions included from PPCGenCallingConv.inc.
2386 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2387 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2390 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2391 CCValAssign::LocInfo &LocInfo,
2392 ISD::ArgFlagsTy &ArgFlags,
2397 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2399 CCValAssign::LocInfo &LocInfo,
2400 ISD::ArgFlagsTy &ArgFlags,
2402 static const MCPhysReg ArgRegs[] = {
2403 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2404 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2406 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2408 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2410 // Skip one register if the first unallocated register has an even register
2411 // number and there are still argument registers available which have not been
2412 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2413 // need to skip a register if RegNum is odd.
2414 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2415 State.AllocateReg(ArgRegs[RegNum]);
2418 // Always return false here, as this function only makes sure that the first
2419 // unallocated register has an odd register number and does not actually
2420 // allocate a register for the current argument.
2424 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2426 CCValAssign::LocInfo &LocInfo,
2427 ISD::ArgFlagsTy &ArgFlags,
2429 static const MCPhysReg ArgRegs[] = {
2430 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2434 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2436 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2438 // If there is only one Floating-point register left we need to put both f64
2439 // values of a split ppc_fp128 value on the stack.
2440 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2441 State.AllocateReg(ArgRegs[RegNum]);
2444 // Always return false here, as this function only makes sure that the two f64
2445 // values a ppc_fp128 value is split into are both passed in registers or both
2446 // passed on the stack and does not actually allocate a register for the
2447 // current argument.
2451 /// FPR - The set of FP registers that should be allocated for arguments,
2453 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2454 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2455 PPC::F11, PPC::F12, PPC::F13};
2457 /// QFPR - The set of QPX registers that should be allocated for arguments.
2458 static const MCPhysReg QFPR[] = {
2459 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2460 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2462 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2464 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2465 unsigned PtrByteSize) {
2466 unsigned ArgSize = ArgVT.getStoreSize();
2467 if (Flags.isByVal())
2468 ArgSize = Flags.getByValSize();
2470 // Round up to multiples of the pointer size, except for array members,
2471 // which are always packed.
2472 if (!Flags.isInConsecutiveRegs())
2473 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2478 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2480 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2481 ISD::ArgFlagsTy Flags,
2482 unsigned PtrByteSize) {
2483 unsigned Align = PtrByteSize;
2485 // Altivec parameters are padded to a 16 byte boundary.
2486 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2487 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2488 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2490 // QPX vector types stored in double-precision are padded to a 32 byte
2492 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2495 // ByVal parameters are aligned as requested.
2496 if (Flags.isByVal()) {
2497 unsigned BVAlign = Flags.getByValAlign();
2498 if (BVAlign > PtrByteSize) {
2499 if (BVAlign % PtrByteSize != 0)
2501 "ByVal alignment is not a multiple of the pointer size");
2507 // Array members are always packed to their original alignment.
2508 if (Flags.isInConsecutiveRegs()) {
2509 // If the array member was split into multiple registers, the first
2510 // needs to be aligned to the size of the full type. (Except for
2511 // ppcf128, which is only aligned as its f64 components.)
2512 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2513 Align = OrigVT.getStoreSize();
2515 Align = ArgVT.getStoreSize();
2521 /// CalculateStackSlotUsed - Return whether this argument will use its
2522 /// stack slot (instead of being passed in registers). ArgOffset,
2523 /// AvailableFPRs, and AvailableVRs must hold the current argument
2524 /// position, and will be updated to account for this argument.
2525 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2526 ISD::ArgFlagsTy Flags,
2527 unsigned PtrByteSize,
2528 unsigned LinkageSize,
2529 unsigned ParamAreaSize,
2530 unsigned &ArgOffset,
2531 unsigned &AvailableFPRs,
2532 unsigned &AvailableVRs, bool HasQPX) {
2533 bool UseMemory = false;
2535 // Respect alignment of argument on the stack.
2537 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2538 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2539 // If there's no space left in the argument save area, we must
2540 // use memory (this check also catches zero-sized arguments).
2541 if (ArgOffset >= LinkageSize + ParamAreaSize)
2544 // Allocate argument on the stack.
2545 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2546 if (Flags.isInConsecutiveRegsLast())
2547 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2548 // If we overran the argument save area, we must use memory
2549 // (this check catches arguments passed partially in memory)
2550 if (ArgOffset > LinkageSize + ParamAreaSize)
2553 // However, if the argument is actually passed in an FPR or a VR,
2554 // we don't use memory after all.
2555 if (!Flags.isByVal()) {
2556 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2557 // QPX registers overlap with the scalar FP registers.
2558 (HasQPX && (ArgVT == MVT::v4f32 ||
2559 ArgVT == MVT::v4f64 ||
2560 ArgVT == MVT::v4i1)))
2561 if (AvailableFPRs > 0) {
2565 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2566 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2567 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2568 if (AvailableVRs > 0) {
2577 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2578 /// ensure minimum alignment required for target.
2579 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2580 unsigned NumBytes) {
2581 unsigned TargetAlign = Lowering->getStackAlignment();
2582 unsigned AlignMask = TargetAlign - 1;
2583 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2588 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2589 CallingConv::ID CallConv, bool isVarArg,
2590 const SmallVectorImpl<ISD::InputArg>
2592 SDLoc dl, SelectionDAG &DAG,
2593 SmallVectorImpl<SDValue> &InVals)
2595 if (Subtarget.isSVR4ABI()) {
2596 if (Subtarget.isPPC64())
2597 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2600 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2603 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2609 PPCTargetLowering::LowerFormalArguments_32SVR4(
2611 CallingConv::ID CallConv, bool isVarArg,
2612 const SmallVectorImpl<ISD::InputArg>
2614 SDLoc dl, SelectionDAG &DAG,
2615 SmallVectorImpl<SDValue> &InVals) const {
2617 // 32-bit SVR4 ABI Stack Frame Layout:
2618 // +-----------------------------------+
2619 // +--> | Back chain |
2620 // | +-----------------------------------+
2621 // | | Floating-point register save area |
2622 // | +-----------------------------------+
2623 // | | General register save area |
2624 // | +-----------------------------------+
2625 // | | CR save word |
2626 // | +-----------------------------------+
2627 // | | VRSAVE save word |
2628 // | +-----------------------------------+
2629 // | | Alignment padding |
2630 // | +-----------------------------------+
2631 // | | Vector register save area |
2632 // | +-----------------------------------+
2633 // | | Local variable space |
2634 // | +-----------------------------------+
2635 // | | Parameter list area |
2636 // | +-----------------------------------+
2637 // | | LR save word |
2638 // | +-----------------------------------+
2639 // SP--> +--- | Back chain |
2640 // +-----------------------------------+
2643 // System V Application Binary Interface PowerPC Processor Supplement
2644 // AltiVec Technology Programming Interface Manual
2646 MachineFunction &MF = DAG.getMachineFunction();
2647 MachineFrameInfo *MFI = MF.getFrameInfo();
2648 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2650 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2651 // Potential tail calls could cause overwriting of argument stack slots.
2652 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2653 (CallConv == CallingConv::Fast));
2654 unsigned PtrByteSize = 4;
2656 // Assign locations to all of the incoming arguments.
2657 SmallVector<CCValAssign, 16> ArgLocs;
2658 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2661 // Reserve space for the linkage area on the stack.
2662 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2663 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2665 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2667 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2668 CCValAssign &VA = ArgLocs[i];
2670 // Arguments stored in registers.
2671 if (VA.isRegLoc()) {
2672 const TargetRegisterClass *RC;
2673 EVT ValVT = VA.getValVT();
2675 switch (ValVT.getSimpleVT().SimpleTy) {
2677 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2680 RC = &PPC::GPRCRegClass;
2683 RC = &PPC::F4RCRegClass;
2686 if (Subtarget.hasVSX())
2687 RC = &PPC::VSFRCRegClass;
2689 RC = &PPC::F8RCRegClass;
2694 RC = &PPC::VRRCRegClass;
2697 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2701 RC = &PPC::VSHRCRegClass;
2704 RC = &PPC::QFRCRegClass;
2707 RC = &PPC::QBRCRegClass;
2711 // Transform the arguments stored in physical registers into virtual ones.
2712 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2713 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2714 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2716 if (ValVT == MVT::i1)
2717 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2719 InVals.push_back(ArgValue);
2721 // Argument stored in memory.
2722 assert(VA.isMemLoc());
2724 unsigned ArgSize = VA.getLocVT().getStoreSize();
2725 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2728 // Create load nodes to retrieve arguments from the stack.
2729 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2730 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2731 MachinePointerInfo(),
2732 false, false, false, 0));
2736 // Assign locations to all of the incoming aggregate by value arguments.
2737 // Aggregates passed by value are stored in the local variable space of the
2738 // caller's stack frame, right above the parameter list area.
2739 SmallVector<CCValAssign, 16> ByValArgLocs;
2740 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2741 ByValArgLocs, *DAG.getContext());
2743 // Reserve stack space for the allocations in CCInfo.
2744 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2746 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2748 // Area that is at least reserved in the caller of this function.
2749 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2750 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2752 // Set the size that is at least reserved in caller of this function. Tail
2753 // call optimized function's reserved stack space needs to be aligned so that
2754 // taking the difference between two stack areas will result in an aligned
2757 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2758 FuncInfo->setMinReservedArea(MinReservedArea);
2760 SmallVector<SDValue, 8> MemOps;
2762 // If the function takes variable number of arguments, make a frame index for
2763 // the start of the first vararg value... for expansion of llvm.va_start.
2765 static const MCPhysReg GPArgRegs[] = {
2766 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2767 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2769 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2771 static const MCPhysReg FPArgRegs[] = {
2772 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2775 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2776 if (DisablePPCFloatInVariadic)
2779 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2780 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2782 // Make room for NumGPArgRegs and NumFPArgRegs.
2783 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2784 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2786 FuncInfo->setVarArgsStackOffset(
2787 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2788 CCInfo.getNextStackOffset(), true));
2790 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2791 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2793 // The fixed integer arguments of a variadic function are stored to the
2794 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2795 // the result of va_next.
2796 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2797 // Get an existing live-in vreg, or add a new one.
2798 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2800 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2802 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2803 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2804 MachinePointerInfo(), false, false, 0);
2805 MemOps.push_back(Store);
2806 // Increment the address by four for the next argument to store
2807 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2808 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2811 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2813 // The double arguments are stored to the VarArgsFrameIndex
2815 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2816 // Get an existing live-in vreg, or add a new one.
2817 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2819 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2821 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2822 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2823 MachinePointerInfo(), false, false, 0);
2824 MemOps.push_back(Store);
2825 // Increment the address by eight for the next argument to store
2826 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2828 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2832 if (!MemOps.empty())
2833 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2838 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2839 // value to MVT::i64 and then truncate to the correct register size.
2841 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2842 SelectionDAG &DAG, SDValue ArgVal,
2845 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2846 DAG.getValueType(ObjectVT));
2847 else if (Flags.isZExt())
2848 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2849 DAG.getValueType(ObjectVT));
2851 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2855 PPCTargetLowering::LowerFormalArguments_64SVR4(
2857 CallingConv::ID CallConv, bool isVarArg,
2858 const SmallVectorImpl<ISD::InputArg>
2860 SDLoc dl, SelectionDAG &DAG,
2861 SmallVectorImpl<SDValue> &InVals) const {
2862 // TODO: add description of PPC stack frame format, or at least some docs.
2864 bool isELFv2ABI = Subtarget.isELFv2ABI();
2865 bool isLittleEndian = Subtarget.isLittleEndian();
2866 MachineFunction &MF = DAG.getMachineFunction();
2867 MachineFrameInfo *MFI = MF.getFrameInfo();
2868 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2870 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
2871 "fastcc not supported on varargs functions");
2873 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2874 // Potential tail calls could cause overwriting of argument stack slots.
2875 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2876 (CallConv == CallingConv::Fast));
2877 unsigned PtrByteSize = 8;
2878 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2880 static const MCPhysReg GPR[] = {
2881 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2882 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2884 static const MCPhysReg VR[] = {
2885 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2886 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2888 static const MCPhysReg VSRH[] = {
2889 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2890 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2893 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2894 const unsigned Num_FPR_Regs = 13;
2895 const unsigned Num_VR_Regs = array_lengthof(VR);
2896 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
2898 // Do a first pass over the arguments to determine whether the ABI
2899 // guarantees that our caller has allocated the parameter save area
2900 // on its stack frame. In the ELFv1 ABI, this is always the case;
2901 // in the ELFv2 ABI, it is true if this is a vararg function or if
2902 // any parameter is located in a stack slot.
2904 bool HasParameterArea = !isELFv2ABI || isVarArg;
2905 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2906 unsigned NumBytes = LinkageSize;
2907 unsigned AvailableFPRs = Num_FPR_Regs;
2908 unsigned AvailableVRs = Num_VR_Regs;
2909 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2910 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2911 PtrByteSize, LinkageSize, ParamAreaSize,
2912 NumBytes, AvailableFPRs, AvailableVRs,
2913 Subtarget.hasQPX()))
2914 HasParameterArea = true;
2916 // Add DAG nodes to load the arguments or copy them out of registers. On
2917 // entry to a function on PPC, the arguments start after the linkage area,
2918 // although the first ones are often in registers.
2920 unsigned ArgOffset = LinkageSize;
2921 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2922 unsigned &QFPR_idx = FPR_idx;
2923 SmallVector<SDValue, 8> MemOps;
2924 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2925 unsigned CurArgIdx = 0;
2926 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2928 bool needsLoad = false;
2929 EVT ObjectVT = Ins[ArgNo].VT;
2930 EVT OrigVT = Ins[ArgNo].ArgVT;
2931 unsigned ObjSize = ObjectVT.getStoreSize();
2932 unsigned ArgSize = ObjSize;
2933 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2934 if (Ins[ArgNo].isOrigArg()) {
2935 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
2936 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
2938 // We re-align the argument offset for each argument, except when using the
2939 // fast calling convention, when we need to make sure we do that only when
2940 // we'll actually use a stack slot.
2941 unsigned CurArgOffset, Align;
2942 auto ComputeArgOffset = [&]() {
2943 /* Respect alignment of argument on the stack. */
2944 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2945 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2946 CurArgOffset = ArgOffset;
2949 if (CallConv != CallingConv::Fast) {
2952 /* Compute GPR index associated with argument offset. */
2953 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2954 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2957 // FIXME the codegen can be much improved in some cases.
2958 // We do not have to keep everything in memory.
2959 if (Flags.isByVal()) {
2960 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
2962 if (CallConv == CallingConv::Fast)
2965 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2966 ObjSize = Flags.getByValSize();
2967 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2968 // Empty aggregate parameters do not take up registers. Examples:
2972 // etc. However, we have to provide a place-holder in InVals, so
2973 // pretend we have an 8-byte item at the current address for that
2976 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2977 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2978 InVals.push_back(FIN);
2982 // Create a stack object covering all stack doublewords occupied
2983 // by the argument. If the argument is (fully or partially) on
2984 // the stack, or if the argument is fully in registers but the
2985 // caller has allocated the parameter save anyway, we can refer
2986 // directly to the caller's stack frame. Otherwise, create a
2987 // local copy in our own frame.
2989 if (HasParameterArea ||
2990 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2991 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2993 FI = MFI->CreateStackObject(ArgSize, Align, false);
2994 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2996 // Handle aggregates smaller than 8 bytes.
2997 if (ObjSize < PtrByteSize) {
2998 // The value of the object is its address, which differs from the
2999 // address of the enclosing doubleword on big-endian systems.
3001 if (!isLittleEndian) {
3002 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
3003 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3005 InVals.push_back(Arg);
3007 if (GPR_idx != Num_GPR_Regs) {
3008 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3009 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3012 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3013 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3014 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3015 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3016 MachinePointerInfo(FuncArg),
3017 ObjType, false, false, 0);
3019 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3020 // store the whole register as-is to the parameter save area
3022 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3023 MachinePointerInfo(FuncArg),
3027 MemOps.push_back(Store);
3029 // Whether we copied from a register or not, advance the offset
3030 // into the parameter save area by a full doubleword.
3031 ArgOffset += PtrByteSize;
3035 // The value of the object is its address, which is the address of
3036 // its first stack doubleword.
3037 InVals.push_back(FIN);
3039 // Store whatever pieces of the object are in registers to memory.
3040 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3041 if (GPR_idx == Num_GPR_Regs)
3044 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3045 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3048 SDValue Off = DAG.getConstant(j, PtrVT);
3049 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3051 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3052 MachinePointerInfo(FuncArg, j),
3054 MemOps.push_back(Store);
3057 ArgOffset += ArgSize;
3061 switch (ObjectVT.getSimpleVT().SimpleTy) {
3062 default: llvm_unreachable("Unhandled argument type!");
3066 // These can be scalar arguments or elements of an integer array type
3067 // passed directly. Clang may use those instead of "byval" aggregate
3068 // types to avoid forcing arguments to memory unnecessarily.
3069 if (GPR_idx != Num_GPR_Regs) {
3070 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3071 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3073 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3074 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3075 // value to MVT::i64 and then truncate to the correct register size.
3076 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3078 if (CallConv == CallingConv::Fast)
3082 ArgSize = PtrByteSize;
3084 if (CallConv != CallingConv::Fast || needsLoad)
3090 // These can be scalar arguments or elements of a float array type
3091 // passed directly. The latter are used to implement ELFv2 homogenous
3092 // float aggregates.
3093 if (FPR_idx != Num_FPR_Regs) {
3096 if (ObjectVT == MVT::f32)
3097 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3099 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3100 ? &PPC::VSFRCRegClass
3101 : &PPC::F8RCRegClass);
3103 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3105 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3106 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3107 // once we support fp <-> gpr moves.
3109 // This can only ever happen in the presence of f32 array types,
3110 // since otherwise we never run out of FPRs before running out
3112 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3113 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3115 if (ObjectVT == MVT::f32) {
3116 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3117 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3118 DAG.getConstant(32, MVT::i32));
3119 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3122 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3124 if (CallConv == CallingConv::Fast)
3130 // When passing an array of floats, the array occupies consecutive
3131 // space in the argument area; only round up to the next doubleword
3132 // at the end of the array. Otherwise, each float takes 8 bytes.
3133 if (CallConv != CallingConv::Fast || needsLoad) {
3134 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3135 ArgOffset += ArgSize;
3136 if (Flags.isInConsecutiveRegsLast())
3137 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3146 if (!Subtarget.hasQPX()) {
3147 // These can be scalar arguments or elements of a vector array type
3148 // passed directly. The latter are used to implement ELFv2 homogenous
3149 // vector aggregates.
3150 if (VR_idx != Num_VR_Regs) {
3151 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3152 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3153 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3154 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3157 if (CallConv == CallingConv::Fast)
3162 if (CallConv != CallingConv::Fast || needsLoad)
3167 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3168 "Invalid QPX parameter type");
3173 // QPX vectors are treated like their scalar floating-point subregisters
3174 // (except that they're larger).
3175 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3176 if (QFPR_idx != Num_QFPR_Regs) {
3177 const TargetRegisterClass *RC;
3178 switch (ObjectVT.getSimpleVT().SimpleTy) {
3179 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3180 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3181 default: RC = &PPC::QBRCRegClass; break;
3184 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3185 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3188 if (CallConv == CallingConv::Fast)
3192 if (CallConv != CallingConv::Fast || needsLoad)
3197 // We need to load the argument to a virtual register if we determined
3198 // above that we ran out of physical registers of the appropriate type.
3200 if (ObjSize < ArgSize && !isLittleEndian)
3201 CurArgOffset += ArgSize - ObjSize;
3202 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3203 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3204 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3205 false, false, false, 0);
3208 InVals.push_back(ArgVal);
3211 // Area that is at least reserved in the caller of this function.
3212 unsigned MinReservedArea;
3213 if (HasParameterArea)
3214 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3216 MinReservedArea = LinkageSize;
3218 // Set the size that is at least reserved in caller of this function. Tail
3219 // call optimized functions' reserved stack space needs to be aligned so that
3220 // taking the difference between two stack areas will result in an aligned
3223 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3224 FuncInfo->setMinReservedArea(MinReservedArea);
3226 // If the function takes variable number of arguments, make a frame index for
3227 // the start of the first vararg value... for expansion of llvm.va_start.
3229 int Depth = ArgOffset;
3231 FuncInfo->setVarArgsFrameIndex(
3232 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3233 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3235 // If this function is vararg, store any remaining integer argument regs
3236 // to their spots on the stack so that they may be loaded by deferencing the
3237 // result of va_next.
3238 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3239 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3240 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3241 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3242 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3243 MachinePointerInfo(), false, false, 0);
3244 MemOps.push_back(Store);
3245 // Increment the address by four for the next argument to store
3246 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
3247 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3251 if (!MemOps.empty())
3252 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3258 PPCTargetLowering::LowerFormalArguments_Darwin(
3260 CallingConv::ID CallConv, bool isVarArg,
3261 const SmallVectorImpl<ISD::InputArg>
3263 SDLoc dl, SelectionDAG &DAG,
3264 SmallVectorImpl<SDValue> &InVals) const {
3265 // TODO: add description of PPC stack frame format, or at least some docs.
3267 MachineFunction &MF = DAG.getMachineFunction();
3268 MachineFrameInfo *MFI = MF.getFrameInfo();
3269 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3271 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3272 bool isPPC64 = PtrVT == MVT::i64;
3273 // Potential tail calls could cause overwriting of argument stack slots.
3274 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3275 (CallConv == CallingConv::Fast));
3276 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3277 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3278 unsigned ArgOffset = LinkageSize;
3279 // Area that is at least reserved in caller of this function.
3280 unsigned MinReservedArea = ArgOffset;
3282 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3283 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3284 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3286 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3287 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3288 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3290 static const MCPhysReg VR[] = {
3291 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3292 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3295 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3296 const unsigned Num_FPR_Regs = 13;
3297 const unsigned Num_VR_Regs = array_lengthof( VR);
3299 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3301 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3303 // In 32-bit non-varargs functions, the stack space for vectors is after the
3304 // stack space for non-vectors. We do not use this space unless we have
3305 // too many vectors to fit in registers, something that only occurs in
3306 // constructed examples:), but we have to walk the arglist to figure
3307 // that out...for the pathological case, compute VecArgOffset as the
3308 // start of the vector parameter area. Computing VecArgOffset is the
3309 // entire point of the following loop.
3310 unsigned VecArgOffset = ArgOffset;
3311 if (!isVarArg && !isPPC64) {
3312 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3314 EVT ObjectVT = Ins[ArgNo].VT;
3315 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3317 if (Flags.isByVal()) {
3318 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3319 unsigned ObjSize = Flags.getByValSize();
3321 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3322 VecArgOffset += ArgSize;
3326 switch(ObjectVT.getSimpleVT().SimpleTy) {
3327 default: llvm_unreachable("Unhandled argument type!");
3333 case MVT::i64: // PPC64
3335 // FIXME: We are guaranteed to be !isPPC64 at this point.
3336 // Does MVT::i64 apply?
3343 // Nothing to do, we're only looking at Nonvector args here.
3348 // We've found where the vector parameter area in memory is. Skip the
3349 // first 12 parameters; these don't use that memory.
3350 VecArgOffset = ((VecArgOffset+15)/16)*16;
3351 VecArgOffset += 12*16;
3353 // Add DAG nodes to load the arguments or copy them out of registers. On
3354 // entry to a function on PPC, the arguments start after the linkage area,
3355 // although the first ones are often in registers.
3357 SmallVector<SDValue, 8> MemOps;
3358 unsigned nAltivecParamsAtEnd = 0;
3359 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3360 unsigned CurArgIdx = 0;
3361 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3363 bool needsLoad = false;
3364 EVT ObjectVT = Ins[ArgNo].VT;
3365 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3366 unsigned ArgSize = ObjSize;
3367 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3368 if (Ins[ArgNo].isOrigArg()) {
3369 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3370 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3372 unsigned CurArgOffset = ArgOffset;
3374 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3375 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3376 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3377 if (isVarArg || isPPC64) {
3378 MinReservedArea = ((MinReservedArea+15)/16)*16;
3379 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3382 } else nAltivecParamsAtEnd++;
3384 // Calculate min reserved area.
3385 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3389 // FIXME the codegen can be much improved in some cases.
3390 // We do not have to keep everything in memory.
3391 if (Flags.isByVal()) {
3392 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3394 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3395 ObjSize = Flags.getByValSize();
3396 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3397 // Objects of size 1 and 2 are right justified, everything else is
3398 // left justified. This means the memory address is adjusted forwards.
3399 if (ObjSize==1 || ObjSize==2) {
3400 CurArgOffset = CurArgOffset + (4 - ObjSize);
3402 // The value of the object is its address.
3403 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3404 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3405 InVals.push_back(FIN);
3406 if (ObjSize==1 || ObjSize==2) {
3407 if (GPR_idx != Num_GPR_Regs) {
3410 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3412 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3413 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3414 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3415 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3416 MachinePointerInfo(FuncArg),
3417 ObjType, false, false, 0);
3418 MemOps.push_back(Store);
3422 ArgOffset += PtrByteSize;
3426 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3427 // Store whatever pieces of the object are in registers
3428 // to memory. ArgOffset will be the address of the beginning
3430 if (GPR_idx != Num_GPR_Regs) {
3433 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3435 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3436 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3437 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3438 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3439 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3440 MachinePointerInfo(FuncArg, j),
3442 MemOps.push_back(Store);
3444 ArgOffset += PtrByteSize;
3446 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3453 switch (ObjectVT.getSimpleVT().SimpleTy) {
3454 default: llvm_unreachable("Unhandled argument type!");
3458 if (GPR_idx != Num_GPR_Regs) {
3459 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3460 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3462 if (ObjectVT == MVT::i1)
3463 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3468 ArgSize = PtrByteSize;
3470 // All int arguments reserve stack space in the Darwin ABI.
3471 ArgOffset += PtrByteSize;
3475 case MVT::i64: // PPC64
3476 if (GPR_idx != Num_GPR_Regs) {
3477 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3478 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3480 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3481 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3482 // value to MVT::i64 and then truncate to the correct register size.
3483 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3488 ArgSize = PtrByteSize;
3490 // All int arguments reserve stack space in the Darwin ABI.
3496 // Every 4 bytes of argument space consumes one of the GPRs available for
3497 // argument passing.
3498 if (GPR_idx != Num_GPR_Regs) {
3500 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3503 if (FPR_idx != Num_FPR_Regs) {
3506 if (ObjectVT == MVT::f32)
3507 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3509 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3511 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3517 // All FP arguments reserve stack space in the Darwin ABI.
3518 ArgOffset += isPPC64 ? 8 : ObjSize;
3524 // Note that vector arguments in registers don't reserve stack space,
3525 // except in varargs functions.
3526 if (VR_idx != Num_VR_Regs) {
3527 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3528 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3530 while ((ArgOffset % 16) != 0) {
3531 ArgOffset += PtrByteSize;
3532 if (GPR_idx != Num_GPR_Regs)
3536 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3540 if (!isVarArg && !isPPC64) {
3541 // Vectors go after all the nonvectors.
3542 CurArgOffset = VecArgOffset;
3545 // Vectors are aligned.
3546 ArgOffset = ((ArgOffset+15)/16)*16;
3547 CurArgOffset = ArgOffset;
3555 // We need to load the argument to a virtual register if we determined above
3556 // that we ran out of physical registers of the appropriate type.
3558 int FI = MFI->CreateFixedObject(ObjSize,
3559 CurArgOffset + (ArgSize - ObjSize),
3561 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3562 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3563 false, false, false, 0);
3566 InVals.push_back(ArgVal);
3569 // Allow for Altivec parameters at the end, if needed.
3570 if (nAltivecParamsAtEnd) {
3571 MinReservedArea = ((MinReservedArea+15)/16)*16;
3572 MinReservedArea += 16*nAltivecParamsAtEnd;
3575 // Area that is at least reserved in the caller of this function.
3576 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3578 // Set the size that is at least reserved in caller of this function. Tail
3579 // call optimized functions' reserved stack space needs to be aligned so that
3580 // taking the difference between two stack areas will result in an aligned
3583 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3584 FuncInfo->setMinReservedArea(MinReservedArea);
3586 // If the function takes variable number of arguments, make a frame index for
3587 // the start of the first vararg value... for expansion of llvm.va_start.
3589 int Depth = ArgOffset;
3591 FuncInfo->setVarArgsFrameIndex(
3592 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3594 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3596 // If this function is vararg, store any remaining integer argument regs
3597 // to their spots on the stack so that they may be loaded by deferencing the
3598 // result of va_next.
3599 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3603 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3605 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3607 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3608 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3609 MachinePointerInfo(), false, false, 0);
3610 MemOps.push_back(Store);
3611 // Increment the address by four for the next argument to store
3612 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3613 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3617 if (!MemOps.empty())
3618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3623 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3624 /// adjusted to accommodate the arguments for the tailcall.
3625 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3626 unsigned ParamSize) {
3628 if (!isTailCall) return 0;
3630 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3631 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3632 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3633 // Remember only if the new adjustement is bigger.
3634 if (SPDiff < FI->getTailCallSPDelta())
3635 FI->setTailCallSPDelta(SPDiff);
3640 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3641 /// for tail call optimization. Targets which want to do tail call
3642 /// optimization should implement this function.
3644 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3645 CallingConv::ID CalleeCC,
3647 const SmallVectorImpl<ISD::InputArg> &Ins,
3648 SelectionDAG& DAG) const {
3649 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3652 // Variable argument functions are not supported.
3656 MachineFunction &MF = DAG.getMachineFunction();
3657 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3658 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3659 // Functions containing by val parameters are not supported.
3660 for (unsigned i = 0; i != Ins.size(); i++) {
3661 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3662 if (Flags.isByVal()) return false;
3665 // Non-PIC/GOT tail calls are supported.
3666 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3669 // At the moment we can only do local tail calls (in same module, hidden
3670 // or protected) if we are generating PIC.
3671 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3672 return G->getGlobal()->hasHiddenVisibility()
3673 || G->getGlobal()->hasProtectedVisibility();
3679 /// isCallCompatibleAddress - Return the immediate to use if the specified
3680 /// 32-bit value is representable in the immediate field of a BxA instruction.
3681 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3682 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3683 if (!C) return nullptr;
3685 int Addr = C->getZExtValue();
3686 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3687 SignExtend32<26>(Addr) != Addr)
3688 return nullptr; // Top 6 bits have to be sext of immediate.
3690 return DAG.getConstant((int)C->getZExtValue() >> 2,
3691 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3696 struct TailCallArgumentInfo {
3701 TailCallArgumentInfo() : FrameIdx(0) {}
3706 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3708 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3710 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3711 SmallVectorImpl<SDValue> &MemOpChains,
3713 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3714 SDValue Arg = TailCallArgs[i].Arg;
3715 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3716 int FI = TailCallArgs[i].FrameIdx;
3717 // Store relative to framepointer.
3718 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3719 MachinePointerInfo::getFixedStack(FI),
3724 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3725 /// the appropriate stack slot for the tail call optimized function call.
3726 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3727 MachineFunction &MF,
3736 // Calculate the new stack slot for the return address.
3737 int SlotSize = isPPC64 ? 8 : 4;
3738 const PPCFrameLowering *FL =
3739 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3740 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3741 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3742 NewRetAddrLoc, true);
3743 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3744 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3745 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3746 MachinePointerInfo::getFixedStack(NewRetAddr),
3749 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3750 // slot as the FP is never overwritten.
3752 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3753 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3755 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3756 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3757 MachinePointerInfo::getFixedStack(NewFPIdx),
3764 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3765 /// the position of the argument.
3767 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3768 SDValue Arg, int SPDiff, unsigned ArgOffset,
3769 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3770 int Offset = ArgOffset + SPDiff;
3771 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3772 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3773 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3774 SDValue FIN = DAG.getFrameIndex(FI, VT);
3775 TailCallArgumentInfo Info;
3777 Info.FrameIdxOp = FIN;
3779 TailCallArguments.push_back(Info);
3782 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3783 /// stack slot. Returns the chain as result and the loaded frame pointers in
3784 /// LROpOut/FPOpout. Used when tail calling.
3785 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3793 // Load the LR and FP stack slot for later adjusting.
3794 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3795 LROpOut = getReturnAddrFrameIndex(DAG);
3796 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3797 false, false, false, 0);
3798 Chain = SDValue(LROpOut.getNode(), 1);
3800 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3801 // slot as the FP is never overwritten.
3803 FPOpOut = getFramePointerFrameIndex(DAG);
3804 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3805 false, false, false, 0);
3806 Chain = SDValue(FPOpOut.getNode(), 1);
3812 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3813 /// by "Src" to address "Dst" of size "Size". Alignment information is
3814 /// specified by the specific parameter attribute. The copy will be passed as
3815 /// a byval function parameter.
3816 /// Sometimes what we are copying is the end of a larger object, the part that
3817 /// does not fit in registers.
3819 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3820 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3822 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3823 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3824 false, false, MachinePointerInfo(),
3825 MachinePointerInfo());
3828 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3831 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3832 SDValue Arg, SDValue PtrOff, int SPDiff,
3833 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3834 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3835 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3837 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3842 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3844 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3845 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3846 DAG.getConstant(ArgOffset, PtrVT));
3848 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3849 MachinePointerInfo(), false, false, 0));
3850 // Calculate and remember argument location.
3851 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3856 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3857 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3858 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3859 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3860 MachineFunction &MF = DAG.getMachineFunction();
3862 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3863 // might overwrite each other in case of tail call optimization.
3864 SmallVector<SDValue, 8> MemOpChains2;
3865 // Do not flag preceding copytoreg stuff together with the following stuff.
3867 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3869 if (!MemOpChains2.empty())
3870 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3872 // Store the return address to the appropriate stack slot.
3873 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3874 isPPC64, isDarwinABI, dl);
3876 // Emit callseq_end just before tailcall node.
3877 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3878 DAG.getIntPtrConstant(0, true), InFlag, dl);
3879 InFlag = Chain.getValue(1);
3882 // Is this global address that of a function that can be called by name? (as
3883 // opposed to something that must hold a descriptor for an indirect call).
3884 static bool isFunctionGlobalAddress(SDValue Callee) {
3885 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3886 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
3887 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
3890 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
3897 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3898 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
3899 bool isTailCall, bool IsPatchPoint,
3900 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3901 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3902 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
3904 bool isPPC64 = Subtarget.isPPC64();
3905 bool isSVR4ABI = Subtarget.isSVR4ABI();
3906 bool isELFv2ABI = Subtarget.isELFv2ABI();
3908 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3909 NodeTys.push_back(MVT::Other); // Returns a chain
3910 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3912 unsigned CallOpc = PPCISD::CALL;
3914 bool needIndirectCall = true;
3915 if (!isSVR4ABI || !isPPC64)
3916 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3917 // If this is an absolute destination address, use the munged value.
3918 Callee = SDValue(Dest, 0);
3919 needIndirectCall = false;
3922 if (isFunctionGlobalAddress(Callee)) {
3923 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
3924 // A call to a TLS address is actually an indirect call to a
3925 // thread-specific pointer.
3926 unsigned OpFlags = 0;
3927 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3928 (Subtarget.getTargetTriple().isMacOSX() &&
3929 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3930 (G->getGlobal()->isDeclaration() ||
3931 G->getGlobal()->isWeakForLinker())) ||
3932 (Subtarget.isTargetELF() && !isPPC64 &&
3933 !G->getGlobal()->hasLocalLinkage() &&
3934 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3935 // PC-relative references to external symbols should go through $stub,
3936 // unless we're building with the leopard linker or later, which
3937 // automatically synthesizes these stubs.
3938 OpFlags = PPCII::MO_PLT_OR_STUB;
3941 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3942 // every direct call is) turn it into a TargetGlobalAddress /
3943 // TargetExternalSymbol node so that legalize doesn't hack it.
3944 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3945 Callee.getValueType(), 0, OpFlags);
3946 needIndirectCall = false;
3949 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3950 unsigned char OpFlags = 0;
3952 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3953 (Subtarget.getTargetTriple().isMacOSX() &&
3954 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3955 (Subtarget.isTargetELF() && !isPPC64 &&
3956 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3957 // PC-relative references to external symbols should go through $stub,
3958 // unless we're building with the leopard linker or later, which
3959 // automatically synthesizes these stubs.
3960 OpFlags = PPCII::MO_PLT_OR_STUB;
3963 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3965 needIndirectCall = false;
3969 // We'll form an invalid direct call when lowering a patchpoint; the full
3970 // sequence for an indirect call is complicated, and many of the
3971 // instructions introduced might have side effects (and, thus, can't be
3972 // removed later). The call itself will be removed as soon as the
3973 // argument/return lowering is complete, so the fact that it has the wrong
3974 // kind of operands should not really matter.
3975 needIndirectCall = false;
3978 if (needIndirectCall) {
3979 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3980 // to do the call, we can't use PPCISD::CALL.
3981 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3983 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3984 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3985 // entry point, but to the function descriptor (the function entry point
3986 // address is part of the function descriptor though).
3987 // The function descriptor is a three doubleword structure with the
3988 // following fields: function entry point, TOC base address and
3989 // environment pointer.
3990 // Thus for a call through a function pointer, the following actions need
3992 // 1. Save the TOC of the caller in the TOC save area of its stack
3993 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3994 // 2. Load the address of the function entry point from the function
3996 // 3. Load the TOC of the callee from the function descriptor into r2.
3997 // 4. Load the environment pointer from the function descriptor into
3999 // 5. Branch to the function entry point address.
4000 // 6. On return of the callee, the TOC of the caller needs to be
4001 // restored (this is done in FinishCall()).
4003 // The loads are scheduled at the beginning of the call sequence, and the
4004 // register copies are flagged together to ensure that no other
4005 // operations can be scheduled in between. E.g. without flagging the
4006 // copies together, a TOC access in the caller could be scheduled between
4007 // the assignment of the callee TOC and the branch to the callee, which
4008 // results in the TOC access going through the TOC of the callee instead
4009 // of going through the TOC of the caller, which leads to incorrect code.
4011 // Load the address of the function entry point from the function
4013 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4014 if (LDChain.getValueType() == MVT::Glue)
4015 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4017 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4019 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4020 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4021 false, false, LoadsInv, 8);
4023 // Load environment pointer into r11.
4024 SDValue PtrOff = DAG.getIntPtrConstant(16);
4025 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4026 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4027 MPI.getWithOffset(16), false, false,
4030 SDValue TOCOff = DAG.getIntPtrConstant(8);
4031 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4032 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4033 MPI.getWithOffset(8), false, false,
4036 setUsesTOCBasePtr(DAG);
4037 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4039 Chain = TOCVal.getValue(0);
4040 InFlag = TOCVal.getValue(1);
4042 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4045 Chain = EnvVal.getValue(0);
4046 InFlag = EnvVal.getValue(1);
4048 MTCTROps[0] = Chain;
4049 MTCTROps[1] = LoadFuncPtr;
4050 MTCTROps[2] = InFlag;
4053 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4054 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4055 InFlag = Chain.getValue(1);
4058 NodeTys.push_back(MVT::Other);
4059 NodeTys.push_back(MVT::Glue);
4060 Ops.push_back(Chain);
4061 CallOpc = PPCISD::BCTRL;
4062 Callee.setNode(nullptr);
4063 // Add use of X11 (holding environment pointer)
4064 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
4065 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4066 // Add CTR register as callee so a bctr can be emitted later.
4068 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4071 // If this is a direct call, pass the chain and the callee.
4072 if (Callee.getNode()) {
4073 Ops.push_back(Chain);
4074 Ops.push_back(Callee);
4076 // If this is a tail call add stack pointer delta.
4078 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
4080 // Add argument registers to the end of the list so that they are known live
4082 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4083 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4084 RegsToPass[i].second.getValueType()));
4086 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4088 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4089 setUsesTOCBasePtr(DAG);
4090 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4097 bool isLocalCall(const SDValue &Callee)
4099 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4100 return !G->getGlobal()->isDeclaration() &&
4101 !G->getGlobal()->isWeakForLinker();
4106 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4107 CallingConv::ID CallConv, bool isVarArg,
4108 const SmallVectorImpl<ISD::InputArg> &Ins,
4109 SDLoc dl, SelectionDAG &DAG,
4110 SmallVectorImpl<SDValue> &InVals) const {
4112 SmallVector<CCValAssign, 16> RVLocs;
4113 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4115 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4117 // Copy all of the result registers out of their specified physreg.
4118 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4119 CCValAssign &VA = RVLocs[i];
4120 assert(VA.isRegLoc() && "Can only return in registers!");
4122 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4123 VA.getLocReg(), VA.getLocVT(), InFlag);
4124 Chain = Val.getValue(1);
4125 InFlag = Val.getValue(2);
4127 switch (VA.getLocInfo()) {
4128 default: llvm_unreachable("Unknown loc info!");
4129 case CCValAssign::Full: break;
4130 case CCValAssign::AExt:
4131 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4133 case CCValAssign::ZExt:
4134 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4135 DAG.getValueType(VA.getValVT()));
4136 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4138 case CCValAssign::SExt:
4139 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4140 DAG.getValueType(VA.getValVT()));
4141 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4145 InVals.push_back(Val);
4152 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4153 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4155 SmallVector<std::pair<unsigned, SDValue>, 8>
4157 SDValue InFlag, SDValue Chain,
4158 SDValue CallSeqStart, SDValue &Callee,
4159 int SPDiff, unsigned NumBytes,
4160 const SmallVectorImpl<ISD::InputArg> &Ins,
4161 SmallVectorImpl<SDValue> &InVals,
4162 ImmutableCallSite *CS) const {
4164 std::vector<EVT> NodeTys;
4165 SmallVector<SDValue, 8> Ops;
4166 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4167 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
4168 Ops, NodeTys, CS, Subtarget);
4170 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4171 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4172 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4174 // When performing tail call optimization the callee pops its arguments off
4175 // the stack. Account for this here so these bytes can be pushed back on in
4176 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4177 int BytesCalleePops =
4178 (CallConv == CallingConv::Fast &&
4179 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4181 // Add a register mask operand representing the call-preserved registers.
4182 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4183 const uint32_t *Mask =
4184 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4185 assert(Mask && "Missing call preserved mask for calling convention");
4186 Ops.push_back(DAG.getRegisterMask(Mask));
4188 if (InFlag.getNode())
4189 Ops.push_back(InFlag);
4193 assert(((Callee.getOpcode() == ISD::Register &&
4194 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4195 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4196 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4197 isa<ConstantSDNode>(Callee)) &&
4198 "Expecting an global address, external symbol, absolute value or register");
4200 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4203 // Add a NOP immediately after the branch instruction when using the 64-bit
4204 // SVR4 ABI. At link time, if caller and callee are in a different module and
4205 // thus have a different TOC, the call will be replaced with a call to a stub
4206 // function which saves the current TOC, loads the TOC of the callee and
4207 // branches to the callee. The NOP will be replaced with a load instruction
4208 // which restores the TOC of the caller from the TOC save slot of the current
4209 // stack frame. If caller and callee belong to the same module (and have the
4210 // same TOC), the NOP will remain unchanged.
4212 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4214 if (CallOpc == PPCISD::BCTRL) {
4215 // This is a call through a function pointer.
4216 // Restore the caller TOC from the save area into R2.
4217 // See PrepareCall() for more information about calls through function
4218 // pointers in the 64-bit SVR4 ABI.
4219 // We are using a target-specific load with r2 hard coded, because the
4220 // result of a target-independent load would never go directly into r2,
4221 // since r2 is a reserved register (which prevents the register allocator
4222 // from allocating it), resulting in an additional register being
4223 // allocated and an unnecessary move instruction being generated.
4224 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4226 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4227 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4228 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4229 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
4230 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4232 // The address needs to go after the chain input but before the flag (or
4233 // any other variadic arguments).
4234 Ops.insert(std::next(Ops.begin()), AddTOC);
4235 } else if ((CallOpc == PPCISD::CALL) &&
4236 (!isLocalCall(Callee) ||
4237 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4238 // Otherwise insert NOP for non-local calls.
4239 CallOpc = PPCISD::CALL_NOP;
4242 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4243 InFlag = Chain.getValue(1);
4245 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
4246 DAG.getIntPtrConstant(BytesCalleePops, true),
4249 InFlag = Chain.getValue(1);
4251 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4252 Ins, dl, DAG, InVals);
4256 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4257 SmallVectorImpl<SDValue> &InVals) const {
4258 SelectionDAG &DAG = CLI.DAG;
4260 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4261 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4262 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4263 SDValue Chain = CLI.Chain;
4264 SDValue Callee = CLI.Callee;
4265 bool &isTailCall = CLI.IsTailCall;
4266 CallingConv::ID CallConv = CLI.CallConv;
4267 bool isVarArg = CLI.IsVarArg;
4268 bool IsPatchPoint = CLI.IsPatchPoint;
4269 ImmutableCallSite *CS = CLI.CS;
4272 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4275 if (!isTailCall && CS && CS->isMustTailCall())
4276 report_fatal_error("failed to perform tail call elimination on a call "
4277 "site marked musttail");
4279 if (Subtarget.isSVR4ABI()) {
4280 if (Subtarget.isPPC64())
4281 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4282 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4283 dl, DAG, InVals, CS);
4285 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4286 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4287 dl, DAG, InVals, CS);
4290 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4291 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4292 dl, DAG, InVals, CS);
4296 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4297 CallingConv::ID CallConv, bool isVarArg,
4298 bool isTailCall, bool IsPatchPoint,
4299 const SmallVectorImpl<ISD::OutputArg> &Outs,
4300 const SmallVectorImpl<SDValue> &OutVals,
4301 const SmallVectorImpl<ISD::InputArg> &Ins,
4302 SDLoc dl, SelectionDAG &DAG,
4303 SmallVectorImpl<SDValue> &InVals,
4304 ImmutableCallSite *CS) const {
4305 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4306 // of the 32-bit SVR4 ABI stack frame layout.
4308 assert((CallConv == CallingConv::C ||
4309 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4311 unsigned PtrByteSize = 4;
4313 MachineFunction &MF = DAG.getMachineFunction();
4315 // Mark this function as potentially containing a function that contains a
4316 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4317 // and restoring the callers stack pointer in this functions epilog. This is
4318 // done because by tail calling the called function might overwrite the value
4319 // in this function's (MF) stack pointer stack slot 0(SP).
4320 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4321 CallConv == CallingConv::Fast)
4322 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4324 // Count how many bytes are to be pushed on the stack, including the linkage
4325 // area, parameter list area and the part of the local variable space which
4326 // contains copies of aggregates which are passed by value.
4328 // Assign locations to all of the outgoing arguments.
4329 SmallVector<CCValAssign, 16> ArgLocs;
4330 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4333 // Reserve space for the linkage area on the stack.
4334 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4338 // Handle fixed and variable vector arguments differently.
4339 // Fixed vector arguments go into registers as long as registers are
4340 // available. Variable vector arguments always go into memory.
4341 unsigned NumArgs = Outs.size();
4343 for (unsigned i = 0; i != NumArgs; ++i) {
4344 MVT ArgVT = Outs[i].VT;
4345 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4348 if (Outs[i].IsFixed) {
4349 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4352 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4358 errs() << "Call operand #" << i << " has unhandled type "
4359 << EVT(ArgVT).getEVTString() << "\n";
4361 llvm_unreachable(nullptr);
4365 // All arguments are treated the same.
4366 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4369 // Assign locations to all of the outgoing aggregate by value arguments.
4370 SmallVector<CCValAssign, 16> ByValArgLocs;
4371 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4372 ByValArgLocs, *DAG.getContext());
4374 // Reserve stack space for the allocations in CCInfo.
4375 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4377 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4379 // Size of the linkage area, parameter list area and the part of the local
4380 // space variable where copies of aggregates which are passed by value are
4382 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4384 // Calculate by how many bytes the stack has to be adjusted in case of tail
4385 // call optimization.
4386 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4388 // Adjust the stack pointer for the new arguments...
4389 // These operations are automatically eliminated by the prolog/epilog pass
4390 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4392 SDValue CallSeqStart = Chain;
4394 // Load the return address and frame pointer so it can be moved somewhere else
4397 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4400 // Set up a copy of the stack pointer for use loading and storing any
4401 // arguments that may not fit in the registers available for argument
4403 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4405 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4406 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4407 SmallVector<SDValue, 8> MemOpChains;
4409 bool seenFloatArg = false;
4410 // Walk the register/memloc assignments, inserting copies/loads.
4411 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4414 CCValAssign &VA = ArgLocs[i];
4415 SDValue Arg = OutVals[i];
4416 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4418 if (Flags.isByVal()) {
4419 // Argument is an aggregate which is passed by value, thus we need to
4420 // create a copy of it in the local variable space of the current stack
4421 // frame (which is the stack frame of the caller) and pass the address of
4422 // this copy to the callee.
4423 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4424 CCValAssign &ByValVA = ByValArgLocs[j++];
4425 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4427 // Memory reserved in the local variable space of the callers stack frame.
4428 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4430 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4431 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4433 // Create a copy of the argument in the local area of the current
4435 SDValue MemcpyCall =
4436 CreateCopyOfByValArgument(Arg, PtrOff,
4437 CallSeqStart.getNode()->getOperand(0),
4440 // This must go outside the CALLSEQ_START..END.
4441 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4442 CallSeqStart.getNode()->getOperand(1),
4444 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4445 NewCallSeqStart.getNode());
4446 Chain = CallSeqStart = NewCallSeqStart;
4448 // Pass the address of the aggregate copy on the stack either in a
4449 // physical register or in the parameter list area of the current stack
4450 // frame to the callee.
4454 if (VA.isRegLoc()) {
4455 if (Arg.getValueType() == MVT::i1)
4456 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4458 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4459 // Put argument in a physical register.
4460 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4462 // Put argument in the parameter list area of the current stack frame.
4463 assert(VA.isMemLoc());
4464 unsigned LocMemOffset = VA.getLocMemOffset();
4467 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4468 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4470 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4471 MachinePointerInfo(),
4474 // Calculate and remember argument location.
4475 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4481 if (!MemOpChains.empty())
4482 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4484 // Build a sequence of copy-to-reg nodes chained together with token chain
4485 // and flag operands which copy the outgoing args into the appropriate regs.
4487 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4488 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4489 RegsToPass[i].second, InFlag);
4490 InFlag = Chain.getValue(1);
4493 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4496 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4497 SDValue Ops[] = { Chain, InFlag };
4499 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4500 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4502 InFlag = Chain.getValue(1);
4506 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4507 false, TailCallArguments);
4509 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4510 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4511 NumBytes, Ins, InVals, CS);
4514 // Copy an argument into memory, being careful to do this outside the
4515 // call sequence for the call to which the argument belongs.
4517 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4518 SDValue CallSeqStart,
4519 ISD::ArgFlagsTy Flags,
4522 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4523 CallSeqStart.getNode()->getOperand(0),
4525 // The MEMCPY must go outside the CALLSEQ_START..END.
4526 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4527 CallSeqStart.getNode()->getOperand(1),
4529 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4530 NewCallSeqStart.getNode());
4531 return NewCallSeqStart;
4535 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4536 CallingConv::ID CallConv, bool isVarArg,
4537 bool isTailCall, bool IsPatchPoint,
4538 const SmallVectorImpl<ISD::OutputArg> &Outs,
4539 const SmallVectorImpl<SDValue> &OutVals,
4540 const SmallVectorImpl<ISD::InputArg> &Ins,
4541 SDLoc dl, SelectionDAG &DAG,
4542 SmallVectorImpl<SDValue> &InVals,
4543 ImmutableCallSite *CS) const {
4545 bool isELFv2ABI = Subtarget.isELFv2ABI();
4546 bool isLittleEndian = Subtarget.isLittleEndian();
4547 unsigned NumOps = Outs.size();
4549 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4550 unsigned PtrByteSize = 8;
4552 MachineFunction &MF = DAG.getMachineFunction();
4554 // Mark this function as potentially containing a function that contains a
4555 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4556 // and restoring the callers stack pointer in this functions epilog. This is
4557 // done because by tail calling the called function might overwrite the value
4558 // in this function's (MF) stack pointer stack slot 0(SP).
4559 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4560 CallConv == CallingConv::Fast)
4561 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4563 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4564 "fastcc not supported on varargs functions");
4566 // Count how many bytes are to be pushed on the stack, including the linkage
4567 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4568 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4569 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4570 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4571 unsigned NumBytes = LinkageSize;
4572 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4573 unsigned &QFPR_idx = FPR_idx;
4575 static const MCPhysReg GPR[] = {
4576 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4577 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4579 static const MCPhysReg VR[] = {
4580 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4581 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4583 static const MCPhysReg VSRH[] = {
4584 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4585 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4588 const unsigned NumGPRs = array_lengthof(GPR);
4589 const unsigned NumFPRs = 13;
4590 const unsigned NumVRs = array_lengthof(VR);
4591 const unsigned NumQFPRs = NumFPRs;
4593 // When using the fast calling convention, we don't provide backing for
4594 // arguments that will be in registers.
4595 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4597 // Add up all the space actually used.
4598 for (unsigned i = 0; i != NumOps; ++i) {
4599 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4600 EVT ArgVT = Outs[i].VT;
4601 EVT OrigVT = Outs[i].ArgVT;
4603 if (CallConv == CallingConv::Fast) {
4604 if (Flags.isByVal())
4605 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4607 switch (ArgVT.getSimpleVT().SimpleTy) {
4608 default: llvm_unreachable("Unexpected ValueType for argument!");
4612 if (++NumGPRsUsed <= NumGPRs)
4620 if (++NumVRsUsed <= NumVRs)
4624 // When using QPX, this is handled like a FP register, otherwise, it
4625 // is an Altivec register.
4626 if (Subtarget.hasQPX()) {
4627 if (++NumFPRsUsed <= NumFPRs)
4630 if (++NumVRsUsed <= NumVRs)
4636 case MVT::v4f64: // QPX
4637 case MVT::v4i1: // QPX
4638 if (++NumFPRsUsed <= NumFPRs)
4644 /* Respect alignment of argument on the stack. */
4646 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4647 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4649 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4650 if (Flags.isInConsecutiveRegsLast())
4651 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4654 unsigned NumBytesActuallyUsed = NumBytes;
4656 // The prolog code of the callee may store up to 8 GPR argument registers to
4657 // the stack, allowing va_start to index over them in memory if its varargs.
4658 // Because we cannot tell if this is needed on the caller side, we have to
4659 // conservatively assume that it is needed. As such, make sure we have at
4660 // least enough stack space for the caller to store the 8 GPRs.
4661 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4662 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4664 // Tail call needs the stack to be aligned.
4665 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4666 CallConv == CallingConv::Fast)
4667 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4669 // Calculate by how many bytes the stack has to be adjusted in case of tail
4670 // call optimization.
4671 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4673 // To protect arguments on the stack from being clobbered in a tail call,
4674 // force all the loads to happen before doing any other lowering.
4676 Chain = DAG.getStackArgumentTokenFactor(Chain);
4678 // Adjust the stack pointer for the new arguments...
4679 // These operations are automatically eliminated by the prolog/epilog pass
4680 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4682 SDValue CallSeqStart = Chain;
4684 // Load the return address and frame pointer so it can be move somewhere else
4687 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4690 // Set up a copy of the stack pointer for use loading and storing any
4691 // arguments that may not fit in the registers available for argument
4693 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4695 // Figure out which arguments are going to go in registers, and which in
4696 // memory. Also, if this is a vararg function, floating point operations
4697 // must be stored to our stack, and loaded into integer regs as well, if
4698 // any integer regs are available for argument passing.
4699 unsigned ArgOffset = LinkageSize;
4701 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4702 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4704 SmallVector<SDValue, 8> MemOpChains;
4705 for (unsigned i = 0; i != NumOps; ++i) {
4706 SDValue Arg = OutVals[i];
4707 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4708 EVT ArgVT = Outs[i].VT;
4709 EVT OrigVT = Outs[i].ArgVT;
4711 // PtrOff will be used to store the current argument to the stack if a
4712 // register cannot be found for it.
4715 // We re-align the argument offset for each argument, except when using the
4716 // fast calling convention, when we need to make sure we do that only when
4717 // we'll actually use a stack slot.
4718 auto ComputePtrOff = [&]() {
4719 /* Respect alignment of argument on the stack. */
4721 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4722 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4724 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4726 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4729 if (CallConv != CallingConv::Fast) {
4732 /* Compute GPR index associated with argument offset. */
4733 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4734 GPR_idx = std::min(GPR_idx, NumGPRs);
4737 // Promote integers to 64-bit values.
4738 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4739 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4740 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4741 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4744 // FIXME memcpy is used way more than necessary. Correctness first.
4745 // Note: "by value" is code for passing a structure by value, not
4747 if (Flags.isByVal()) {
4748 // Note: Size includes alignment padding, so
4749 // struct x { short a; char b; }
4750 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4751 // These are the proper values we need for right-justifying the
4752 // aggregate in a parameter register.
4753 unsigned Size = Flags.getByValSize();
4755 // An empty aggregate parameter takes up no storage and no
4760 if (CallConv == CallingConv::Fast)
4763 // All aggregates smaller than 8 bytes must be passed right-justified.
4764 if (Size==1 || Size==2 || Size==4) {
4765 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4766 if (GPR_idx != NumGPRs) {
4767 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4768 MachinePointerInfo(), VT,
4769 false, false, false, 0);
4770 MemOpChains.push_back(Load.getValue(1));
4771 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4773 ArgOffset += PtrByteSize;
4778 if (GPR_idx == NumGPRs && Size < 8) {
4779 SDValue AddPtr = PtrOff;
4780 if (!isLittleEndian) {
4781 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4782 PtrOff.getValueType());
4783 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4785 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4788 ArgOffset += PtrByteSize;
4791 // Copy entire object into memory. There are cases where gcc-generated
4792 // code assumes it is there, even if it could be put entirely into
4793 // registers. (This is not what the doc says.)
4795 // FIXME: The above statement is likely due to a misunderstanding of the
4796 // documents. All arguments must be copied into the parameter area BY
4797 // THE CALLEE in the event that the callee takes the address of any
4798 // formal argument. That has not yet been implemented. However, it is
4799 // reasonable to use the stack area as a staging area for the register
4802 // Skip this for small aggregates, as we will use the same slot for a
4803 // right-justified copy, below.
4805 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4809 // When a register is available, pass a small aggregate right-justified.
4810 if (Size < 8 && GPR_idx != NumGPRs) {
4811 // The easiest way to get this right-justified in a register
4812 // is to copy the structure into the rightmost portion of a
4813 // local variable slot, then load the whole slot into the
4815 // FIXME: The memcpy seems to produce pretty awful code for
4816 // small aggregates, particularly for packed ones.
4817 // FIXME: It would be preferable to use the slot in the
4818 // parameter save area instead of a new local variable.
4819 SDValue AddPtr = PtrOff;
4820 if (!isLittleEndian) {
4821 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4822 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4824 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4828 // Load the slot into the register.
4829 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4830 MachinePointerInfo(),
4831 false, false, false, 0);
4832 MemOpChains.push_back(Load.getValue(1));
4833 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4835 // Done with this argument.
4836 ArgOffset += PtrByteSize;
4840 // For aggregates larger than PtrByteSize, copy the pieces of the
4841 // object that fit into registers from the parameter save area.
4842 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4843 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4844 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4845 if (GPR_idx != NumGPRs) {
4846 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4847 MachinePointerInfo(),
4848 false, false, false, 0);
4849 MemOpChains.push_back(Load.getValue(1));
4850 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4851 ArgOffset += PtrByteSize;
4853 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4860 switch (Arg.getSimpleValueType().SimpleTy) {
4861 default: llvm_unreachable("Unexpected ValueType for argument!");
4865 // These can be scalar arguments or elements of an integer array type
4866 // passed directly. Clang may use those instead of "byval" aggregate
4867 // types to avoid forcing arguments to memory unnecessarily.
4868 if (GPR_idx != NumGPRs) {
4869 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4871 if (CallConv == CallingConv::Fast)
4874 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4875 true, isTailCall, false, MemOpChains,
4876 TailCallArguments, dl);
4877 if (CallConv == CallingConv::Fast)
4878 ArgOffset += PtrByteSize;
4880 if (CallConv != CallingConv::Fast)
4881 ArgOffset += PtrByteSize;
4885 // These can be scalar arguments or elements of a float array type
4886 // passed directly. The latter are used to implement ELFv2 homogenous
4887 // float aggregates.
4889 // Named arguments go into FPRs first, and once they overflow, the
4890 // remaining arguments go into GPRs and then the parameter save area.
4891 // Unnamed arguments for vararg functions always go to GPRs and
4892 // then the parameter save area. For now, put all arguments to vararg
4893 // routines always in both locations (FPR *and* GPR or stack slot).
4894 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4895 bool NeededLoad = false;
4897 // First load the argument into the next available FPR.
4898 if (FPR_idx != NumFPRs)
4899 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4901 // Next, load the argument into GPR or stack slot if needed.
4902 if (!NeedGPROrStack)
4904 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
4905 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4906 // once we support fp <-> gpr moves.
4908 // In the non-vararg case, this can only ever happen in the
4909 // presence of f32 array types, since otherwise we never run
4910 // out of FPRs before running out of GPRs.
4913 // Double values are always passed in a single GPR.
4914 if (Arg.getValueType() != MVT::f32) {
4915 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4917 // Non-array float values are extended and passed in a GPR.
4918 } else if (!Flags.isInConsecutiveRegs()) {
4919 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4920 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4922 // If we have an array of floats, we collect every odd element
4923 // together with its predecessor into one GPR.
4924 } else if (ArgOffset % PtrByteSize != 0) {
4926 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4927 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4928 if (!isLittleEndian)
4930 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4932 // The final element, if even, goes into the first half of a GPR.
4933 } else if (Flags.isInConsecutiveRegsLast()) {
4934 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4935 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4936 if (!isLittleEndian)
4937 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4938 DAG.getConstant(32, MVT::i32));
4940 // Non-final even elements are skipped; they will be handled
4941 // together the with subsequent argument on the next go-around.
4945 if (ArgVal.getNode())
4946 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
4948 if (CallConv == CallingConv::Fast)
4951 // Single-precision floating-point values are mapped to the
4952 // second (rightmost) word of the stack doubleword.
4953 if (Arg.getValueType() == MVT::f32 &&
4954 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4955 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4956 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4959 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4960 true, isTailCall, false, MemOpChains,
4961 TailCallArguments, dl);
4965 // When passing an array of floats, the array occupies consecutive
4966 // space in the argument area; only round up to the next doubleword
4967 // at the end of the array. Otherwise, each float takes 8 bytes.
4968 if (CallConv != CallingConv::Fast || NeededLoad) {
4969 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4970 Flags.isInConsecutiveRegs()) ? 4 : 8;
4971 if (Flags.isInConsecutiveRegsLast())
4972 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4982 if (!Subtarget.hasQPX()) {
4983 // These can be scalar arguments or elements of a vector array type
4984 // passed directly. The latter are used to implement ELFv2 homogenous
4985 // vector aggregates.
4987 // For a varargs call, named arguments go into VRs or on the stack as
4988 // usual; unnamed arguments always go to the stack or the corresponding
4989 // GPRs when within range. For now, we always put the value in both
4990 // locations (or even all three).
4992 // We could elide this store in the case where the object fits
4993 // entirely in R registers. Maybe later.
4994 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4995 MachinePointerInfo(), false, false, 0);
4996 MemOpChains.push_back(Store);
4997 if (VR_idx != NumVRs) {
4998 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4999 MachinePointerInfo(),
5000 false, false, false, 0);
5001 MemOpChains.push_back(Load.getValue(1));
5003 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5004 Arg.getSimpleValueType() == MVT::v2i64) ?
5005 VSRH[VR_idx] : VR[VR_idx];
5008 RegsToPass.push_back(std::make_pair(VReg, Load));
5011 for (unsigned i=0; i<16; i+=PtrByteSize) {
5012 if (GPR_idx == NumGPRs)
5014 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5015 DAG.getConstant(i, PtrVT));
5016 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5017 false, false, false, 0);
5018 MemOpChains.push_back(Load.getValue(1));
5019 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5024 // Non-varargs Altivec params go into VRs or on the stack.
5025 if (VR_idx != NumVRs) {
5026 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5027 Arg.getSimpleValueType() == MVT::v2i64) ?
5028 VSRH[VR_idx] : VR[VR_idx];
5031 RegsToPass.push_back(std::make_pair(VReg, Arg));
5033 if (CallConv == CallingConv::Fast)
5036 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5037 true, isTailCall, true, MemOpChains,
5038 TailCallArguments, dl);
5039 if (CallConv == CallingConv::Fast)
5043 if (CallConv != CallingConv::Fast)
5048 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5049 "Invalid QPX parameter type");
5054 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5056 // We could elide this store in the case where the object fits
5057 // entirely in R registers. Maybe later.
5058 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5059 MachinePointerInfo(), false, false, 0);
5060 MemOpChains.push_back(Store);
5061 if (QFPR_idx != NumQFPRs) {
5062 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5063 Store, PtrOff, MachinePointerInfo(),
5064 false, false, false, 0);
5065 MemOpChains.push_back(Load.getValue(1));
5066 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5068 ArgOffset += (IsF32 ? 16 : 32);
5069 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5070 if (GPR_idx == NumGPRs)
5072 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5073 DAG.getConstant(i, PtrVT));
5074 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5075 false, false, false, 0);
5076 MemOpChains.push_back(Load.getValue(1));
5077 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5082 // Non-varargs QPX params go into registers or on the stack.
5083 if (QFPR_idx != NumQFPRs) {
5084 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5086 if (CallConv == CallingConv::Fast)
5089 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5090 true, isTailCall, true, MemOpChains,
5091 TailCallArguments, dl);
5092 if (CallConv == CallingConv::Fast)
5093 ArgOffset += (IsF32 ? 16 : 32);
5096 if (CallConv != CallingConv::Fast)
5097 ArgOffset += (IsF32 ? 16 : 32);
5103 assert(NumBytesActuallyUsed == ArgOffset);
5104 (void)NumBytesActuallyUsed;
5106 if (!MemOpChains.empty())
5107 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5109 // Check if this is an indirect call (MTCTR/BCTRL).
5110 // See PrepareCall() for more information about calls through function
5111 // pointers in the 64-bit SVR4 ABI.
5112 if (!isTailCall && !IsPatchPoint &&
5113 !isFunctionGlobalAddress(Callee) &&
5114 !isa<ExternalSymbolSDNode>(Callee)) {
5115 // Load r2 into a virtual register and store it to the TOC save area.
5116 setUsesTOCBasePtr(DAG);
5117 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5118 // TOC save area offset.
5119 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5120 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
5121 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5122 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
5123 MachinePointerInfo::getStack(TOCSaveOffset),
5125 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5126 // This does not mean the MTCTR instruction must use R12; it's easier
5127 // to model this as an extra parameter, so do that.
5128 if (isELFv2ABI && !IsPatchPoint)
5129 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5132 // Build a sequence of copy-to-reg nodes chained together with token chain
5133 // and flag operands which copy the outgoing args into the appropriate regs.
5135 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5136 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5137 RegsToPass[i].second, InFlag);
5138 InFlag = Chain.getValue(1);
5142 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5143 FPOp, true, TailCallArguments);
5145 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5146 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5147 NumBytes, Ins, InVals, CS);
5151 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5152 CallingConv::ID CallConv, bool isVarArg,
5153 bool isTailCall, bool IsPatchPoint,
5154 const SmallVectorImpl<ISD::OutputArg> &Outs,
5155 const SmallVectorImpl<SDValue> &OutVals,
5156 const SmallVectorImpl<ISD::InputArg> &Ins,
5157 SDLoc dl, SelectionDAG &DAG,
5158 SmallVectorImpl<SDValue> &InVals,
5159 ImmutableCallSite *CS) const {
5161 unsigned NumOps = Outs.size();
5163 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5164 bool isPPC64 = PtrVT == MVT::i64;
5165 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5167 MachineFunction &MF = DAG.getMachineFunction();
5169 // Mark this function as potentially containing a function that contains a
5170 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5171 // and restoring the callers stack pointer in this functions epilog. This is
5172 // done because by tail calling the called function might overwrite the value
5173 // in this function's (MF) stack pointer stack slot 0(SP).
5174 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5175 CallConv == CallingConv::Fast)
5176 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5178 // Count how many bytes are to be pushed on the stack, including the linkage
5179 // area, and parameter passing area. We start with 24/48 bytes, which is
5180 // prereserved space for [SP][CR][LR][3 x unused].
5181 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5182 unsigned NumBytes = LinkageSize;
5184 // Add up all the space actually used.
5185 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5186 // they all go in registers, but we must reserve stack space for them for
5187 // possible use by the caller. In varargs or 64-bit calls, parameters are
5188 // assigned stack space in order, with padding so Altivec parameters are
5190 unsigned nAltivecParamsAtEnd = 0;
5191 for (unsigned i = 0; i != NumOps; ++i) {
5192 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5193 EVT ArgVT = Outs[i].VT;
5194 // Varargs Altivec parameters are padded to a 16 byte boundary.
5195 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5196 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5197 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5198 if (!isVarArg && !isPPC64) {
5199 // Non-varargs Altivec parameters go after all the non-Altivec
5200 // parameters; handle those later so we know how much padding we need.
5201 nAltivecParamsAtEnd++;
5204 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5205 NumBytes = ((NumBytes+15)/16)*16;
5207 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5210 // Allow for Altivec parameters at the end, if needed.
5211 if (nAltivecParamsAtEnd) {
5212 NumBytes = ((NumBytes+15)/16)*16;
5213 NumBytes += 16*nAltivecParamsAtEnd;
5216 // The prolog code of the callee may store up to 8 GPR argument registers to
5217 // the stack, allowing va_start to index over them in memory if its varargs.
5218 // Because we cannot tell if this is needed on the caller side, we have to
5219 // conservatively assume that it is needed. As such, make sure we have at
5220 // least enough stack space for the caller to store the 8 GPRs.
5221 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5223 // Tail call needs the stack to be aligned.
5224 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5225 CallConv == CallingConv::Fast)
5226 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5228 // Calculate by how many bytes the stack has to be adjusted in case of tail
5229 // call optimization.
5230 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5232 // To protect arguments on the stack from being clobbered in a tail call,
5233 // force all the loads to happen before doing any other lowering.
5235 Chain = DAG.getStackArgumentTokenFactor(Chain);
5237 // Adjust the stack pointer for the new arguments...
5238 // These operations are automatically eliminated by the prolog/epilog pass
5239 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
5241 SDValue CallSeqStart = Chain;
5243 // Load the return address and frame pointer so it can be move somewhere else
5246 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5249 // Set up a copy of the stack pointer for use loading and storing any
5250 // arguments that may not fit in the registers available for argument
5254 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5256 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5258 // Figure out which arguments are going to go in registers, and which in
5259 // memory. Also, if this is a vararg function, floating point operations
5260 // must be stored to our stack, and loaded into integer regs as well, if
5261 // any integer regs are available for argument passing.
5262 unsigned ArgOffset = LinkageSize;
5263 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5265 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5266 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5267 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5269 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5270 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5271 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5273 static const MCPhysReg VR[] = {
5274 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5275 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5277 const unsigned NumGPRs = array_lengthof(GPR_32);
5278 const unsigned NumFPRs = 13;
5279 const unsigned NumVRs = array_lengthof(VR);
5281 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5283 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5284 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5286 SmallVector<SDValue, 8> MemOpChains;
5287 for (unsigned i = 0; i != NumOps; ++i) {
5288 SDValue Arg = OutVals[i];
5289 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5291 // PtrOff will be used to store the current argument to the stack if a
5292 // register cannot be found for it.
5295 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
5297 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5299 // On PPC64, promote integers to 64-bit values.
5300 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5301 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5302 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5303 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5306 // FIXME memcpy is used way more than necessary. Correctness first.
5307 // Note: "by value" is code for passing a structure by value, not
5309 if (Flags.isByVal()) {
5310 unsigned Size = Flags.getByValSize();
5311 // Very small objects are passed right-justified. Everything else is
5312 // passed left-justified.
5313 if (Size==1 || Size==2) {
5314 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5315 if (GPR_idx != NumGPRs) {
5316 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5317 MachinePointerInfo(), VT,
5318 false, false, false, 0);
5319 MemOpChains.push_back(Load.getValue(1));
5320 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5322 ArgOffset += PtrByteSize;
5324 SDValue Const = DAG.getConstant(PtrByteSize - Size,
5325 PtrOff.getValueType());
5326 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5327 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5330 ArgOffset += PtrByteSize;
5334 // Copy entire object into memory. There are cases where gcc-generated
5335 // code assumes it is there, even if it could be put entirely into
5336 // registers. (This is not what the doc says.)
5337 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5341 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5342 // copy the pieces of the object that fit into registers from the
5343 // parameter save area.
5344 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5345 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
5346 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5347 if (GPR_idx != NumGPRs) {
5348 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5349 MachinePointerInfo(),
5350 false, false, false, 0);
5351 MemOpChains.push_back(Load.getValue(1));
5352 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5353 ArgOffset += PtrByteSize;
5355 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5362 switch (Arg.getSimpleValueType().SimpleTy) {
5363 default: llvm_unreachable("Unexpected ValueType for argument!");
5367 if (GPR_idx != NumGPRs) {
5368 if (Arg.getValueType() == MVT::i1)
5369 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5371 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5373 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5374 isPPC64, isTailCall, false, MemOpChains,
5375 TailCallArguments, dl);
5377 ArgOffset += PtrByteSize;
5381 if (FPR_idx != NumFPRs) {
5382 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5385 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5386 MachinePointerInfo(), false, false, 0);
5387 MemOpChains.push_back(Store);
5389 // Float varargs are always shadowed in available integer registers
5390 if (GPR_idx != NumGPRs) {
5391 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5392 MachinePointerInfo(), false, false,
5394 MemOpChains.push_back(Load.getValue(1));
5395 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5397 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5398 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
5399 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5400 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5401 MachinePointerInfo(),
5402 false, false, false, 0);
5403 MemOpChains.push_back(Load.getValue(1));
5404 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5407 // If we have any FPRs remaining, we may also have GPRs remaining.
5408 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5410 if (GPR_idx != NumGPRs)
5412 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5413 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5417 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5418 isPPC64, isTailCall, false, MemOpChains,
5419 TailCallArguments, dl);
5423 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5430 // These go aligned on the stack, or in the corresponding R registers
5431 // when within range. The Darwin PPC ABI doc claims they also go in
5432 // V registers; in fact gcc does this only for arguments that are
5433 // prototyped, not for those that match the ... We do it for all
5434 // arguments, seems to work.
5435 while (ArgOffset % 16 !=0) {
5436 ArgOffset += PtrByteSize;
5437 if (GPR_idx != NumGPRs)
5440 // We could elide this store in the case where the object fits
5441 // entirely in R registers. Maybe later.
5442 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5443 DAG.getConstant(ArgOffset, PtrVT));
5444 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5445 MachinePointerInfo(), false, false, 0);
5446 MemOpChains.push_back(Store);
5447 if (VR_idx != NumVRs) {
5448 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5449 MachinePointerInfo(),
5450 false, false, false, 0);
5451 MemOpChains.push_back(Load.getValue(1));
5452 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5455 for (unsigned i=0; i<16; i+=PtrByteSize) {
5456 if (GPR_idx == NumGPRs)
5458 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5459 DAG.getConstant(i, PtrVT));
5460 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5461 false, false, false, 0);
5462 MemOpChains.push_back(Load.getValue(1));
5463 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5468 // Non-varargs Altivec params generally go in registers, but have
5469 // stack space allocated at the end.
5470 if (VR_idx != NumVRs) {
5471 // Doesn't have GPR space allocated.
5472 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5473 } else if (nAltivecParamsAtEnd==0) {
5474 // We are emitting Altivec params in order.
5475 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5476 isPPC64, isTailCall, true, MemOpChains,
5477 TailCallArguments, dl);
5483 // If all Altivec parameters fit in registers, as they usually do,
5484 // they get stack space following the non-Altivec parameters. We
5485 // don't track this here because nobody below needs it.
5486 // If there are more Altivec parameters than fit in registers emit
5488 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5490 // Offset is aligned; skip 1st 12 params which go in V registers.
5491 ArgOffset = ((ArgOffset+15)/16)*16;
5493 for (unsigned i = 0; i != NumOps; ++i) {
5494 SDValue Arg = OutVals[i];
5495 EVT ArgType = Outs[i].VT;
5496 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5497 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5500 // We are emitting Altivec params in order.
5501 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5502 isPPC64, isTailCall, true, MemOpChains,
5503 TailCallArguments, dl);
5510 if (!MemOpChains.empty())
5511 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5513 // On Darwin, R12 must contain the address of an indirect callee. This does
5514 // not mean the MTCTR instruction must use R12; it's easier to model this as
5515 // an extra parameter, so do that.
5517 !isFunctionGlobalAddress(Callee) &&
5518 !isa<ExternalSymbolSDNode>(Callee) &&
5519 !isBLACompatibleAddress(Callee, DAG))
5520 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5521 PPC::R12), Callee));
5523 // Build a sequence of copy-to-reg nodes chained together with token chain
5524 // and flag operands which copy the outgoing args into the appropriate regs.
5526 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5527 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5528 RegsToPass[i].second, InFlag);
5529 InFlag = Chain.getValue(1);
5533 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5534 FPOp, true, TailCallArguments);
5536 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5537 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5538 NumBytes, Ins, InVals, CS);
5542 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5543 MachineFunction &MF, bool isVarArg,
5544 const SmallVectorImpl<ISD::OutputArg> &Outs,
5545 LLVMContext &Context) const {
5546 SmallVector<CCValAssign, 16> RVLocs;
5547 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5548 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5552 PPCTargetLowering::LowerReturn(SDValue Chain,
5553 CallingConv::ID CallConv, bool isVarArg,
5554 const SmallVectorImpl<ISD::OutputArg> &Outs,
5555 const SmallVectorImpl<SDValue> &OutVals,
5556 SDLoc dl, SelectionDAG &DAG) const {
5558 SmallVector<CCValAssign, 16> RVLocs;
5559 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5561 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5564 SmallVector<SDValue, 4> RetOps(1, Chain);
5566 // Copy the result values into the output registers.
5567 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5568 CCValAssign &VA = RVLocs[i];
5569 assert(VA.isRegLoc() && "Can only return in registers!");
5571 SDValue Arg = OutVals[i];
5573 switch (VA.getLocInfo()) {
5574 default: llvm_unreachable("Unknown loc info!");
5575 case CCValAssign::Full: break;
5576 case CCValAssign::AExt:
5577 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5579 case CCValAssign::ZExt:
5580 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5582 case CCValAssign::SExt:
5583 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5587 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5588 Flag = Chain.getValue(1);
5589 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5592 RetOps[0] = Chain; // Update chain.
5594 // Add the flag if we have it.
5596 RetOps.push_back(Flag);
5598 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5601 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5602 const PPCSubtarget &Subtarget) const {
5603 // When we pop the dynamic allocation we need to restore the SP link.
5606 // Get the corect type for pointers.
5607 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5609 // Construct the stack pointer operand.
5610 bool isPPC64 = Subtarget.isPPC64();
5611 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5612 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5614 // Get the operands for the STACKRESTORE.
5615 SDValue Chain = Op.getOperand(0);
5616 SDValue SaveSP = Op.getOperand(1);
5618 // Load the old link SP.
5619 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5620 MachinePointerInfo(),
5621 false, false, false, 0);
5623 // Restore the stack pointer.
5624 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5626 // Store the old link SP.
5627 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5634 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5635 MachineFunction &MF = DAG.getMachineFunction();
5636 bool isPPC64 = Subtarget.isPPC64();
5637 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5639 // Get current frame pointer save index. The users of this index will be
5640 // primarily DYNALLOC instructions.
5641 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5642 int RASI = FI->getReturnAddrSaveIndex();
5644 // If the frame pointer save index hasn't been defined yet.
5646 // Find out what the fix offset of the frame pointer save area.
5647 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5648 // Allocate the frame index for frame pointer save area.
5649 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5651 FI->setReturnAddrSaveIndex(RASI);
5653 return DAG.getFrameIndex(RASI, PtrVT);
5657 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5658 MachineFunction &MF = DAG.getMachineFunction();
5659 bool isPPC64 = Subtarget.isPPC64();
5660 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5662 // Get current frame pointer save index. The users of this index will be
5663 // primarily DYNALLOC instructions.
5664 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5665 int FPSI = FI->getFramePointerSaveIndex();
5667 // If the frame pointer save index hasn't been defined yet.
5669 // Find out what the fix offset of the frame pointer save area.
5670 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5671 // Allocate the frame index for frame pointer save area.
5672 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5674 FI->setFramePointerSaveIndex(FPSI);
5676 return DAG.getFrameIndex(FPSI, PtrVT);
5679 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5681 const PPCSubtarget &Subtarget) const {
5683 SDValue Chain = Op.getOperand(0);
5684 SDValue Size = Op.getOperand(1);
5687 // Get the corect type for pointers.
5688 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5690 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5691 DAG.getConstant(0, PtrVT), Size);
5692 // Construct a node for the frame pointer save index.
5693 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5694 // Build a DYNALLOC node.
5695 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5696 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5697 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5700 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5701 SelectionDAG &DAG) const {
5703 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5704 DAG.getVTList(MVT::i32, MVT::Other),
5705 Op.getOperand(0), Op.getOperand(1));
5708 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5709 SelectionDAG &DAG) const {
5711 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5712 Op.getOperand(0), Op.getOperand(1));
5715 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5716 if (Op.getValueType().isVector())
5717 return LowerVectorLoad(Op, DAG);
5719 assert(Op.getValueType() == MVT::i1 &&
5720 "Custom lowering only for i1 loads");
5722 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5725 LoadSDNode *LD = cast<LoadSDNode>(Op);
5727 SDValue Chain = LD->getChain();
5728 SDValue BasePtr = LD->getBasePtr();
5729 MachineMemOperand *MMO = LD->getMemOperand();
5731 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5732 BasePtr, MVT::i8, MMO);
5733 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5735 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5736 return DAG.getMergeValues(Ops, dl);
5739 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5740 if (Op.getOperand(1).getValueType().isVector())
5741 return LowerVectorStore(Op, DAG);
5743 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5744 "Custom lowering only for i1 stores");
5746 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5749 StoreSDNode *ST = cast<StoreSDNode>(Op);
5751 SDValue Chain = ST->getChain();
5752 SDValue BasePtr = ST->getBasePtr();
5753 SDValue Value = ST->getValue();
5754 MachineMemOperand *MMO = ST->getMemOperand();
5756 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5757 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5760 // FIXME: Remove this once the ANDI glue bug is fixed:
5761 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5762 assert(Op.getValueType() == MVT::i1 &&
5763 "Custom lowering only for i1 results");
5766 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5770 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5772 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5773 // Not FP? Not a fsel.
5774 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5775 !Op.getOperand(2).getValueType().isFloatingPoint())
5778 // We might be able to do better than this under some circumstances, but in
5779 // general, fsel-based lowering of select is a finite-math-only optimization.
5780 // For more information, see section F.3 of the 2.06 ISA specification.
5781 if (!DAG.getTarget().Options.NoInfsFPMath ||
5782 !DAG.getTarget().Options.NoNaNsFPMath)
5785 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5787 EVT ResVT = Op.getValueType();
5788 EVT CmpVT = Op.getOperand(0).getValueType();
5789 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5790 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5793 // If the RHS of the comparison is a 0.0, we don't need to do the
5794 // subtraction at all.
5796 if (isFloatingPointZero(RHS))
5798 default: break; // SETUO etc aren't handled by fsel.
5802 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5803 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5804 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5805 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5806 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5807 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5808 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5811 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5814 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5815 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5816 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5819 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5822 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5823 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5824 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5825 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5830 default: break; // SETUO etc aren't handled by fsel.
5834 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5835 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5836 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5837 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5838 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5839 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5840 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5841 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5844 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5845 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5846 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5847 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5850 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5851 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5852 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5853 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5856 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5857 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5858 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5859 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5862 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5863 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5864 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5865 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5870 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5873 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5874 SDValue Src = Op.getOperand(0);
5875 if (Src.getValueType() == MVT::f32)
5876 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5879 switch (Op.getSimpleValueType().SimpleTy) {
5880 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5883 Op.getOpcode() == ISD::FP_TO_SINT
5885 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
5889 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5890 "i64 FP_TO_UINT is supported only with FPCVT");
5891 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5897 // Convert the FP value to an int value through memory.
5898 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5899 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5900 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5901 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5902 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5904 // Emit a store to the stack slot.
5907 MachineFunction &MF = DAG.getMachineFunction();
5908 MachineMemOperand *MMO =
5909 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5910 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5911 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5912 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5914 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5915 MPI, false, false, 0);
5917 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5919 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5920 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5921 DAG.getConstant(4, FIPtr.getValueType()));
5922 MPI = MPI.getWithOffset(4);
5930 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5933 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5935 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5936 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5940 // We're trying to insert a regular store, S, and then a load, L. If the
5941 // incoming value, O, is a load, we might just be able to have our load use the
5942 // address used by O. However, we don't know if anything else will store to
5943 // that address before we can load from it. To prevent this situation, we need
5944 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5945 // the same chain operand as O, we create a token factor from the chain results
5946 // of O and L, and we replace all uses of O's chain result with that token
5947 // factor (see spliceIntoChain below for this last part).
5948 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5951 ISD::LoadExtType ET) const {
5953 if (ET == ISD::NON_EXTLOAD &&
5954 (Op.getOpcode() == ISD::FP_TO_UINT ||
5955 Op.getOpcode() == ISD::FP_TO_SINT) &&
5956 isOperationLegalOrCustom(Op.getOpcode(),
5957 Op.getOperand(0).getValueType())) {
5959 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5963 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5964 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
5965 LD->isNonTemporal())
5967 if (LD->getMemoryVT() != MemVT)
5970 RLI.Ptr = LD->getBasePtr();
5971 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5972 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5973 "Non-pre-inc AM on PPC?");
5974 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5978 RLI.Chain = LD->getChain();
5979 RLI.MPI = LD->getPointerInfo();
5980 RLI.IsInvariant = LD->isInvariant();
5981 RLI.Alignment = LD->getAlignment();
5982 RLI.AAInfo = LD->getAAInfo();
5983 RLI.Ranges = LD->getRanges();
5985 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
5989 // Given the head of the old chain, ResChain, insert a token factor containing
5990 // it and NewResChain, and make users of ResChain now be users of that token
5992 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
5993 SDValue NewResChain,
5994 SelectionDAG &DAG) const {
5998 SDLoc dl(NewResChain);
6000 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6001 NewResChain, DAG.getUNDEF(MVT::Other));
6002 assert(TF.getNode() != NewResChain.getNode() &&
6003 "A new TF really is required here");
6005 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6006 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6009 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6010 SelectionDAG &DAG) const {
6013 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6014 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6017 SDValue Value = Op.getOperand(0);
6018 // The values are now known to be -1 (false) or 1 (true). To convert this
6019 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6020 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6021 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6023 SDValue FPHalfs = DAG.getConstantFP(0.5, MVT::f64);
6024 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6025 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
6027 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6029 if (Op.getValueType() != MVT::v4f64)
6030 Value = DAG.getNode(ISD::FP_ROUND, dl,
6031 Op.getValueType(), Value, DAG.getIntPtrConstant(1));
6035 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6036 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6039 if (Op.getOperand(0).getValueType() == MVT::i1)
6040 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6041 DAG.getConstantFP(1.0, Op.getValueType()),
6042 DAG.getConstantFP(0.0, Op.getValueType()));
6044 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6045 "UINT_TO_FP is supported only with FPCVT");
6047 // If we have FCFIDS, then use it when converting to single-precision.
6048 // Otherwise, convert to double-precision and then round.
6049 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6050 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6052 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6054 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6058 if (Op.getOperand(0).getValueType() == MVT::i64) {
6059 SDValue SINT = Op.getOperand(0);
6060 // When converting to single-precision, we actually need to convert
6061 // to double-precision first and then round to single-precision.
6062 // To avoid double-rounding effects during that operation, we have
6063 // to prepare the input operand. Bits that might be truncated when
6064 // converting to double-precision are replaced by a bit that won't
6065 // be lost at this stage, but is below the single-precision rounding
6068 // However, if -enable-unsafe-fp-math is in effect, accept double
6069 // rounding to avoid the extra overhead.
6070 if (Op.getValueType() == MVT::f32 &&
6071 !Subtarget.hasFPCVT() &&
6072 !DAG.getTarget().Options.UnsafeFPMath) {
6074 // Twiddle input to make sure the low 11 bits are zero. (If this
6075 // is the case, we are guaranteed the value will fit into the 53 bit
6076 // mantissa of an IEEE double-precision value without rounding.)
6077 // If any of those low 11 bits were not zero originally, make sure
6078 // bit 12 (value 2048) is set instead, so that the final rounding
6079 // to single-precision gets the correct result.
6080 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6081 SINT, DAG.getConstant(2047, MVT::i64));
6082 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6083 Round, DAG.getConstant(2047, MVT::i64));
6084 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6085 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6086 Round, DAG.getConstant(-2048, MVT::i64));
6088 // However, we cannot use that value unconditionally: if the magnitude
6089 // of the input value is small, the bit-twiddling we did above might
6090 // end up visibly changing the output. Fortunately, in that case, we
6091 // don't need to twiddle bits since the original input will convert
6092 // exactly to double-precision floating-point already. Therefore,
6093 // construct a conditional to use the original value if the top 11
6094 // bits are all sign-bit copies, and use the rounded value computed
6096 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6097 SINT, DAG.getConstant(53, MVT::i32));
6098 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6099 Cond, DAG.getConstant(1, MVT::i64));
6100 Cond = DAG.getSetCC(dl, MVT::i32,
6101 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
6103 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6109 MachineFunction &MF = DAG.getMachineFunction();
6110 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6111 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6112 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6114 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6115 } else if (Subtarget.hasLFIWAX() &&
6116 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6117 MachineMemOperand *MMO =
6118 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6119 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6120 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6121 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6122 DAG.getVTList(MVT::f64, MVT::Other),
6123 Ops, MVT::i32, MMO);
6124 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6125 } else if (Subtarget.hasFPCVT() &&
6126 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6127 MachineMemOperand *MMO =
6128 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6129 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6130 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6131 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6132 DAG.getVTList(MVT::f64, MVT::Other),
6133 Ops, MVT::i32, MMO);
6134 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6135 } else if (((Subtarget.hasLFIWAX() &&
6136 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6137 (Subtarget.hasFPCVT() &&
6138 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6139 SINT.getOperand(0).getValueType() == MVT::i32) {
6140 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6141 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6143 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6144 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6147 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6148 MachinePointerInfo::getFixedStack(FrameIdx),
6151 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6152 "Expected an i32 store");
6156 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6159 MachineMemOperand *MMO =
6160 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6161 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6162 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6163 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6164 PPCISD::LFIWZX : PPCISD::LFIWAX,
6165 dl, DAG.getVTList(MVT::f64, MVT::Other),
6166 Ops, MVT::i32, MMO);
6168 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6170 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6172 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6173 FP = DAG.getNode(ISD::FP_ROUND, dl,
6174 MVT::f32, FP, DAG.getIntPtrConstant(0));
6178 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6179 "Unhandled INT_TO_FP type in custom expander!");
6180 // Since we only generate this in 64-bit mode, we can take advantage of
6181 // 64-bit registers. In particular, sign extend the input value into the
6182 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6183 // then lfd it and fcfid it.
6184 MachineFunction &MF = DAG.getMachineFunction();
6185 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6186 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6189 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6192 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6194 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6195 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6197 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6198 MachinePointerInfo::getFixedStack(FrameIdx),
6201 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6202 "Expected an i32 store");
6206 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6210 MachineMemOperand *MMO =
6211 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6212 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6213 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6214 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6215 PPCISD::LFIWZX : PPCISD::LFIWAX,
6216 dl, DAG.getVTList(MVT::f64, MVT::Other),
6217 Ops, MVT::i32, MMO);
6219 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6221 assert(Subtarget.isPPC64() &&
6222 "i32->FP without LFIWAX supported only on PPC64");
6224 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6225 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6227 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6230 // STD the extended value into the stack slot.
6231 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
6232 MachinePointerInfo::getFixedStack(FrameIdx),
6235 // Load the value as a double.
6236 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
6237 MachinePointerInfo::getFixedStack(FrameIdx),
6238 false, false, false, 0);
6241 // FCFID it and return it.
6242 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6243 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6244 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
6248 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6249 SelectionDAG &DAG) const {
6252 The rounding mode is in bits 30:31 of FPSR, and has the following
6259 FLT_ROUNDS, on the other hand, expects the following:
6266 To perform the conversion, we do:
6267 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6270 MachineFunction &MF = DAG.getMachineFunction();
6271 EVT VT = Op.getValueType();
6272 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6274 // Save FP Control Word to register
6276 MVT::f64, // return register
6277 MVT::Glue // unused in this context
6279 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6281 // Save FP register to stack slot
6282 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6283 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6284 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6285 StackSlot, MachinePointerInfo(), false, false,0);
6287 // Load FP Control Word from low 32 bits of stack slot.
6288 SDValue Four = DAG.getConstant(4, PtrVT);
6289 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6290 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6291 false, false, false, 0);
6293 // Transform as necessary
6295 DAG.getNode(ISD::AND, dl, MVT::i32,
6296 CWD, DAG.getConstant(3, MVT::i32));
6298 DAG.getNode(ISD::SRL, dl, MVT::i32,
6299 DAG.getNode(ISD::AND, dl, MVT::i32,
6300 DAG.getNode(ISD::XOR, dl, MVT::i32,
6301 CWD, DAG.getConstant(3, MVT::i32)),
6302 DAG.getConstant(3, MVT::i32)),
6303 DAG.getConstant(1, MVT::i32));
6306 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6308 return DAG.getNode((VT.getSizeInBits() < 16 ?
6309 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6312 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6313 EVT VT = Op.getValueType();
6314 unsigned BitWidth = VT.getSizeInBits();
6316 assert(Op.getNumOperands() == 3 &&
6317 VT == Op.getOperand(1).getValueType() &&
6320 // Expand into a bunch of logical ops. Note that these ops
6321 // depend on the PPC behavior for oversized shift amounts.
6322 SDValue Lo = Op.getOperand(0);
6323 SDValue Hi = Op.getOperand(1);
6324 SDValue Amt = Op.getOperand(2);
6325 EVT AmtVT = Amt.getValueType();
6327 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6328 DAG.getConstant(BitWidth, AmtVT), Amt);
6329 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6330 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6331 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6332 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6333 DAG.getConstant(-BitWidth, AmtVT));
6334 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6335 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6336 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6337 SDValue OutOps[] = { OutLo, OutHi };
6338 return DAG.getMergeValues(OutOps, dl);
6341 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6342 EVT VT = Op.getValueType();
6344 unsigned BitWidth = VT.getSizeInBits();
6345 assert(Op.getNumOperands() == 3 &&
6346 VT == Op.getOperand(1).getValueType() &&
6349 // Expand into a bunch of logical ops. Note that these ops
6350 // depend on the PPC behavior for oversized shift amounts.
6351 SDValue Lo = Op.getOperand(0);
6352 SDValue Hi = Op.getOperand(1);
6353 SDValue Amt = Op.getOperand(2);
6354 EVT AmtVT = Amt.getValueType();
6356 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6357 DAG.getConstant(BitWidth, AmtVT), Amt);
6358 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6359 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6360 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6361 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6362 DAG.getConstant(-BitWidth, AmtVT));
6363 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6364 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6365 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6366 SDValue OutOps[] = { OutLo, OutHi };
6367 return DAG.getMergeValues(OutOps, dl);
6370 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6372 EVT VT = Op.getValueType();
6373 unsigned BitWidth = VT.getSizeInBits();
6374 assert(Op.getNumOperands() == 3 &&
6375 VT == Op.getOperand(1).getValueType() &&
6378 // Expand into a bunch of logical ops, followed by a select_cc.
6379 SDValue Lo = Op.getOperand(0);
6380 SDValue Hi = Op.getOperand(1);
6381 SDValue Amt = Op.getOperand(2);
6382 EVT AmtVT = Amt.getValueType();
6384 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6385 DAG.getConstant(BitWidth, AmtVT), Amt);
6386 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6387 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6388 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6389 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6390 DAG.getConstant(-BitWidth, AmtVT));
6391 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6392 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6393 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
6394 Tmp4, Tmp6, ISD::SETLE);
6395 SDValue OutOps[] = { OutLo, OutHi };
6396 return DAG.getMergeValues(OutOps, dl);
6399 //===----------------------------------------------------------------------===//
6400 // Vector related lowering.
6403 /// BuildSplatI - Build a canonical splati of Val with an element size of
6404 /// SplatSize. Cast the result to VT.
6405 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6406 SelectionDAG &DAG, SDLoc dl) {
6407 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6409 static const MVT VTys[] = { // canonical VT to use for each size.
6410 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6413 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6415 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6419 EVT CanonicalVT = VTys[SplatSize-1];
6421 // Build a canonical splat for this value.
6422 SDValue Elt = DAG.getConstant(Val, MVT::i32);
6423 SmallVector<SDValue, 8> Ops;
6424 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6425 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6426 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6429 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6430 /// specified intrinsic ID.
6431 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6432 SelectionDAG &DAG, SDLoc dl,
6433 EVT DestVT = MVT::Other) {
6434 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6435 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6436 DAG.getConstant(IID, MVT::i32), Op);
6439 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6440 /// specified intrinsic ID.
6441 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6442 SelectionDAG &DAG, SDLoc dl,
6443 EVT DestVT = MVT::Other) {
6444 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6445 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6446 DAG.getConstant(IID, MVT::i32), LHS, RHS);
6449 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6450 /// specified intrinsic ID.
6451 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6452 SDValue Op2, SelectionDAG &DAG,
6453 SDLoc dl, EVT DestVT = MVT::Other) {
6454 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6455 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6456 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
6460 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6461 /// amount. The result has the specified value type.
6462 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6463 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6464 // Force LHS/RHS to be the right type.
6465 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6466 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6469 for (unsigned i = 0; i != 16; ++i)
6471 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6472 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6475 // If this is a case we can't handle, return null and let the default
6476 // expansion code take care of it. If we CAN select this case, and if it
6477 // selects to a single instruction, return Op. Otherwise, if we can codegen
6478 // this case more efficiently than a constant pool load, lower it to the
6479 // sequence of ops that should be used.
6480 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6481 SelectionDAG &DAG) const {
6483 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6484 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6486 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6487 // We first build an i32 vector, load it into a QPX register,
6488 // then convert it to a floating-point vector and compare it
6489 // to a zero vector to get the boolean result.
6490 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6491 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6492 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
6493 EVT PtrVT = getPointerTy();
6494 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6496 assert(BVN->getNumOperands() == 4 &&
6497 "BUILD_VECTOR for v4i1 does not have 4 operands");
6499 bool IsConst = true;
6500 for (unsigned i = 0; i < 4; ++i) {
6501 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6502 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6510 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6512 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6514 SmallVector<Constant*, 4> CV(4, NegOne);
6515 for (unsigned i = 0; i < 4; ++i) {
6516 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6517 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6518 else if (cast<ConstantSDNode>(BVN->getOperand(i))->
6519 getConstantIntValue()->isZero())
6525 Constant *CP = ConstantVector::get(CV);
6526 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(),
6527 16 /* alignment */);
6529 SmallVector<SDValue, 2> Ops;
6530 Ops.push_back(DAG.getEntryNode());
6531 Ops.push_back(CPIdx);
6533 SmallVector<EVT, 2> ValueVTs;
6534 ValueVTs.push_back(MVT::v4i1);
6535 ValueVTs.push_back(MVT::Other); // chain
6536 SDVTList VTs = DAG.getVTList(ValueVTs);
6538 return DAG.getMemIntrinsicNode(PPCISD::QVLFSb,
6539 dl, VTs, Ops, MVT::v4f32,
6540 MachinePointerInfo::getConstantPool());
6543 SmallVector<SDValue, 4> Stores;
6544 for (unsigned i = 0; i < 4; ++i) {
6545 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6547 unsigned Offset = 4*i;
6548 SDValue Idx = DAG.getConstant(Offset, FIdx.getValueType());
6549 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6551 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6552 if (StoreSize > 4) {
6553 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6554 BVN->getOperand(i), Idx,
6555 PtrInfo.getWithOffset(Offset),
6556 MVT::i32, false, false, 0));
6558 SDValue StoreValue = BVN->getOperand(i);
6560 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6562 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6564 PtrInfo.getWithOffset(Offset),
6570 if (!Stores.empty())
6571 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6573 StoreChain = DAG.getEntryNode();
6575 // Now load from v4i32 into the QPX register; this will extend it to
6576 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6577 // is typed as v4f64 because the QPX register integer states are not
6578 // explicitly represented.
6580 SmallVector<SDValue, 2> Ops;
6581 Ops.push_back(StoreChain);
6582 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, MVT::i32));
6583 Ops.push_back(FIdx);
6585 SmallVector<EVT, 2> ValueVTs;
6586 ValueVTs.push_back(MVT::v4f64);
6587 ValueVTs.push_back(MVT::Other); // chain
6588 SDVTList VTs = DAG.getVTList(ValueVTs);
6590 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6591 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6592 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6593 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, MVT::i32),
6596 SDValue FPZeros = DAG.getConstantFP(0.0, MVT::f64);
6597 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6598 FPZeros, FPZeros, FPZeros, FPZeros);
6600 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6603 // All other QPX vectors are handled by generic code.
6604 if (Subtarget.hasQPX())
6607 // Check if this is a splat of a constant value.
6608 APInt APSplatBits, APSplatUndef;
6609 unsigned SplatBitSize;
6611 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6612 HasAnyUndefs, 0, true) || SplatBitSize > 32)
6615 unsigned SplatBits = APSplatBits.getZExtValue();
6616 unsigned SplatUndef = APSplatUndef.getZExtValue();
6617 unsigned SplatSize = SplatBitSize / 8;
6619 // First, handle single instruction cases.
6622 if (SplatBits == 0) {
6623 // Canonicalize all zero vectors to be v4i32.
6624 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6625 SDValue Z = DAG.getConstant(0, MVT::i32);
6626 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6627 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6632 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6633 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6635 if (SextVal >= -16 && SextVal <= 15)
6636 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6639 // Two instruction sequences.
6641 // If this value is in the range [-32,30] and is even, use:
6642 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6643 // If this value is in the range [17,31] and is odd, use:
6644 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6645 // If this value is in the range [-31,-17] and is odd, use:
6646 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6647 // Note the last two are three-instruction sequences.
6648 if (SextVal >= -32 && SextVal <= 31) {
6649 // To avoid having these optimizations undone by constant folding,
6650 // we convert to a pseudo that will be expanded later into one of
6652 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
6653 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6654 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6655 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
6656 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6657 if (VT == Op.getValueType())
6660 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6663 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6664 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6666 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6667 // Make -1 and vspltisw -1:
6668 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6670 // Make the VSLW intrinsic, computing 0x8000_0000.
6671 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6674 // xor by OnesV to invert it.
6675 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6676 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6679 // The remaining cases assume either big endian element order or
6680 // a splat-size that equates to the element size of the vector
6681 // to be built. An example that doesn't work for little endian is
6682 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6683 // and a vector element size of 16 bits. The code below will
6684 // produce the vector in big endian element order, which for little
6685 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6687 // For now, just avoid these optimizations in that case.
6688 // FIXME: Develop correct optimizations for LE with mismatched
6689 // splat and element sizes.
6691 if (Subtarget.isLittleEndian() &&
6692 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6695 // Check to see if this is a wide variety of vsplti*, binop self cases.
6696 static const signed char SplatCsts[] = {
6697 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6698 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6701 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6702 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6703 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6704 int i = SplatCsts[idx];
6706 // Figure out what shift amount will be used by altivec if shifted by i in
6708 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6710 // vsplti + shl self.
6711 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6712 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6713 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6714 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6715 Intrinsic::ppc_altivec_vslw
6717 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6718 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6721 // vsplti + srl self.
6722 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6723 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6724 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6725 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6726 Intrinsic::ppc_altivec_vsrw
6728 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6729 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6732 // vsplti + sra self.
6733 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6734 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6735 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6736 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6737 Intrinsic::ppc_altivec_vsraw
6739 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6740 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6743 // vsplti + rol self.
6744 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6745 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6746 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6747 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6748 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6749 Intrinsic::ppc_altivec_vrlw
6751 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6752 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6755 // t = vsplti c, result = vsldoi t, t, 1
6756 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6757 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6758 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6760 // t = vsplti c, result = vsldoi t, t, 2
6761 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6762 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6763 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6765 // t = vsplti c, result = vsldoi t, t, 3
6766 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6767 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6768 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6775 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6776 /// the specified operations to build the shuffle.
6777 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6778 SDValue RHS, SelectionDAG &DAG,
6780 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6781 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6782 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6785 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6797 if (OpNum == OP_COPY) {
6798 if (LHSID == (1*9+2)*9+3) return LHS;
6799 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6803 SDValue OpLHS, OpRHS;
6804 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6805 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6809 default: llvm_unreachable("Unknown i32 permute!");
6811 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6812 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6813 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6814 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6817 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6818 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6819 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6820 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6823 for (unsigned i = 0; i != 16; ++i)
6824 ShufIdxs[i] = (i&3)+0;
6827 for (unsigned i = 0; i != 16; ++i)
6828 ShufIdxs[i] = (i&3)+4;
6831 for (unsigned i = 0; i != 16; ++i)
6832 ShufIdxs[i] = (i&3)+8;
6835 for (unsigned i = 0; i != 16; ++i)
6836 ShufIdxs[i] = (i&3)+12;
6839 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6841 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6843 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6845 EVT VT = OpLHS.getValueType();
6846 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6847 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6848 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6849 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6852 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6853 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6854 /// return the code it can be lowered into. Worst case, it can always be
6855 /// lowered into a vperm.
6856 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6857 SelectionDAG &DAG) const {
6859 SDValue V1 = Op.getOperand(0);
6860 SDValue V2 = Op.getOperand(1);
6861 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6862 EVT VT = Op.getValueType();
6863 bool isLittleEndian = Subtarget.isLittleEndian();
6865 if (Subtarget.hasQPX()) {
6866 if (VT.getVectorNumElements() != 4)
6869 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6871 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
6872 if (AlignIdx != -1) {
6873 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
6874 DAG.getConstant(AlignIdx, MVT::i32));
6875 } else if (SVOp->isSplat()) {
6876 int SplatIdx = SVOp->getSplatIndex();
6877 if (SplatIdx >= 4) {
6882 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
6885 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
6886 DAG.getConstant(SplatIdx, MVT::i32));
6889 // Lower this into a qvgpci/qvfperm pair.
6891 // Compute the qvgpci literal
6893 for (unsigned i = 0; i < 4; ++i) {
6894 int m = SVOp->getMaskElt(i);
6895 unsigned mm = m >= 0 ? (unsigned) m : i;
6896 idx |= mm << (3-i)*3;
6899 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
6900 DAG.getConstant(idx, MVT::i32));
6901 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
6904 // Cases that are handled by instructions that take permute immediates
6905 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6906 // selected by the instruction selector.
6907 if (V2.getOpcode() == ISD::UNDEF) {
6908 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6909 PPC::isSplatShuffleMask(SVOp, 2) ||
6910 PPC::isSplatShuffleMask(SVOp, 4) ||
6911 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6912 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6913 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6914 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6915 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6916 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6917 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6918 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6919 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6924 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6925 // and produce a fixed permutation. If any of these match, do not lower to
6927 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6928 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6929 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6930 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6931 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6932 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6933 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6934 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6935 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6936 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6939 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6940 // perfect shuffle table to emit an optimal matching sequence.
6941 ArrayRef<int> PermMask = SVOp->getMask();
6943 unsigned PFIndexes[4];
6944 bool isFourElementShuffle = true;
6945 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6946 unsigned EltNo = 8; // Start out undef.
6947 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6948 if (PermMask[i*4+j] < 0)
6949 continue; // Undef, ignore it.
6951 unsigned ByteSource = PermMask[i*4+j];
6952 if ((ByteSource & 3) != j) {
6953 isFourElementShuffle = false;
6958 EltNo = ByteSource/4;
6959 } else if (EltNo != ByteSource/4) {
6960 isFourElementShuffle = false;
6964 PFIndexes[i] = EltNo;
6967 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6968 // perfect shuffle vector to determine if it is cost effective to do this as
6969 // discrete instructions, or whether we should use a vperm.
6970 // For now, we skip this for little endian until such time as we have a
6971 // little-endian perfect shuffle table.
6972 if (isFourElementShuffle && !isLittleEndian) {
6973 // Compute the index in the perfect shuffle table.
6974 unsigned PFTableIndex =
6975 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6977 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6978 unsigned Cost = (PFEntry >> 30);
6980 // Determining when to avoid vperm is tricky. Many things affect the cost
6981 // of vperm, particularly how many times the perm mask needs to be computed.
6982 // For example, if the perm mask can be hoisted out of a loop or is already
6983 // used (perhaps because there are multiple permutes with the same shuffle
6984 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6985 // the loop requires an extra register.
6987 // As a compromise, we only emit discrete instructions if the shuffle can be
6988 // generated in 3 or fewer operations. When we have loop information
6989 // available, if this block is within a loop, we should avoid using vperm
6990 // for 3-operation perms and use a constant pool load instead.
6992 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6995 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6996 // vector that will get spilled to the constant pool.
6997 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6999 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7000 // that it is in input element units, not in bytes. Convert now.
7002 // For little endian, the order of the input vectors is reversed, and
7003 // the permutation mask is complemented with respect to 31. This is
7004 // necessary to produce proper semantics with the big-endian-biased vperm
7006 EVT EltVT = V1.getValueType().getVectorElementType();
7007 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7009 SmallVector<SDValue, 16> ResultMask;
7010 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7011 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7013 for (unsigned j = 0; j != BytesPerElement; ++j)
7015 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
7018 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
7022 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7025 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7028 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7032 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
7033 /// altivec comparison. If it is, return true and fill in Opc/isDot with
7034 /// information about the intrinsic.
7035 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
7036 bool &isDot, const PPCSubtarget &Subtarget) {
7037 unsigned IntrinsicID =
7038 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7041 switch (IntrinsicID) {
7042 default: return false;
7043 // Comparison predicates.
7044 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7045 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7046 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7047 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7048 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7049 case Intrinsic::ppc_altivec_vcmpequd_p:
7050 if (Subtarget.hasP8Altivec()) {
7058 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7059 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7060 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7061 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7062 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7063 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7064 if (Subtarget.hasP8Altivec()) {
7072 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7073 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7074 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7075 case Intrinsic::ppc_altivec_vcmpgtud_p:
7076 if (Subtarget.hasP8Altivec()) {
7085 // Normal Comparisons.
7086 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7087 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7088 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7089 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7090 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7091 case Intrinsic::ppc_altivec_vcmpequd:
7092 if (Subtarget.hasP8Altivec()) {
7100 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7101 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7102 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7103 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7104 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7105 case Intrinsic::ppc_altivec_vcmpgtsd:
7106 if (Subtarget.hasP8Altivec()) {
7114 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7115 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7116 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7117 case Intrinsic::ppc_altivec_vcmpgtud:
7118 if (Subtarget.hasP8Altivec()) {
7130 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7131 /// lower, do it, otherwise return null.
7132 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7133 SelectionDAG &DAG) const {
7134 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7135 // opcode number of the comparison.
7139 if (!getAltivecCompareInfo(Op, CompareOpc, isDot, Subtarget))
7140 return SDValue(); // Don't custom lower most intrinsics.
7142 // If this is a non-dot comparison, make the VCMP node and we are done.
7144 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7145 Op.getOperand(1), Op.getOperand(2),
7146 DAG.getConstant(CompareOpc, MVT::i32));
7147 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7150 // Create the PPCISD altivec 'dot' comparison node.
7152 Op.getOperand(2), // LHS
7153 Op.getOperand(3), // RHS
7154 DAG.getConstant(CompareOpc, MVT::i32)
7156 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7157 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7159 // Now that we have the comparison, emit a copy from the CR to a GPR.
7160 // This is flagged to the above dot comparison.
7161 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7162 DAG.getRegister(PPC::CR6, MVT::i32),
7163 CompNode.getValue(1));
7165 // Unpack the result based on how the target uses it.
7166 unsigned BitNo; // Bit # of CR6.
7167 bool InvertBit; // Invert result?
7168 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7169 default: // Can't happen, don't crash on invalid number though.
7170 case 0: // Return the value of the EQ bit of CR6.
7171 BitNo = 0; InvertBit = false;
7173 case 1: // Return the inverted value of the EQ bit of CR6.
7174 BitNo = 0; InvertBit = true;
7176 case 2: // Return the value of the LT bit of CR6.
7177 BitNo = 2; InvertBit = false;
7179 case 3: // Return the inverted value of the LT bit of CR6.
7180 BitNo = 2; InvertBit = true;
7184 // Shift the bit into the low position.
7185 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7186 DAG.getConstant(8-(3-BitNo), MVT::i32));
7188 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7189 DAG.getConstant(1, MVT::i32));
7191 // If we are supposed to, toggle the bit.
7193 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7194 DAG.getConstant(1, MVT::i32));
7198 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7199 SelectionDAG &DAG) const {
7201 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7202 // instructions), but for smaller types, we need to first extend up to v2i32
7203 // before doing going farther.
7204 if (Op.getValueType() == MVT::v2i64) {
7205 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7206 if (ExtVT != MVT::v2i32) {
7207 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7208 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7209 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7210 ExtVT.getVectorElementType(), 4)));
7211 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7212 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7213 DAG.getValueType(MVT::v2i32));
7222 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7223 SelectionDAG &DAG) const {
7225 // Create a stack slot that is 16-byte aligned.
7226 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7227 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7228 EVT PtrVT = getPointerTy();
7229 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7231 // Store the input value into Value#0 of the stack slot.
7232 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7233 Op.getOperand(0), FIdx, MachinePointerInfo(),
7236 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7237 false, false, false, 0);
7240 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7241 SelectionDAG &DAG) const {
7243 SDNode *N = Op.getNode();
7245 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7246 "Unknown extract_vector_elt type");
7248 SDValue Value = N->getOperand(0);
7250 // The first part of this is like the store lowering except that we don't
7251 // need to track the chain.
7253 // The values are now known to be -1 (false) or 1 (true). To convert this
7254 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7255 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7256 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7258 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7259 // understand how to form the extending load.
7260 SDValue FPHalfs = DAG.getConstantFP(0.5, MVT::f64);
7261 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7262 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7264 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7266 // Now convert to an integer and store.
7267 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7268 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, MVT::i32),
7271 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7272 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7273 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7274 EVT PtrVT = getPointerTy();
7275 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7277 SDValue StoreChain = DAG.getEntryNode();
7278 SmallVector<SDValue, 2> Ops;
7279 Ops.push_back(StoreChain);
7280 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, MVT::i32));
7281 Ops.push_back(Value);
7282 Ops.push_back(FIdx);
7284 SmallVector<EVT, 2> ValueVTs;
7285 ValueVTs.push_back(MVT::Other); // chain
7286 SDVTList VTs = DAG.getVTList(ValueVTs);
7288 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7289 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7291 // Extract the value requested.
7292 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7293 SDValue Idx = DAG.getConstant(Offset, FIdx.getValueType());
7294 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7296 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7297 PtrInfo.getWithOffset(Offset),
7298 false, false, false, 0);
7300 if (!Subtarget.useCRBits())
7303 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7306 /// Lowering for QPX v4i1 loads
7307 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7308 SelectionDAG &DAG) const {
7310 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7311 SDValue LoadChain = LN->getChain();
7312 SDValue BasePtr = LN->getBasePtr();
7314 if (Op.getValueType() == MVT::v4f64 ||
7315 Op.getValueType() == MVT::v4f32) {
7316 EVT MemVT = LN->getMemoryVT();
7317 unsigned Alignment = LN->getAlignment();
7319 // If this load is properly aligned, then it is legal.
7320 if (Alignment >= MemVT.getStoreSize())
7323 EVT ScalarVT = Op.getValueType().getScalarType(),
7324 ScalarMemVT = MemVT.getScalarType();
7325 unsigned Stride = ScalarMemVT.getStoreSize();
7327 SmallVector<SDValue, 8> Vals, LoadChains;
7328 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7330 if (ScalarVT != ScalarMemVT)
7332 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7334 LN->getPointerInfo().getWithOffset(Idx*Stride),
7335 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7336 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7340 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7341 LN->getPointerInfo().getWithOffset(Idx*Stride),
7342 LN->isVolatile(), LN->isNonTemporal(),
7343 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7346 if (Idx == 0 && LN->isIndexed()) {
7347 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7348 "Unknown addressing mode on vector load");
7349 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7350 LN->getAddressingMode());
7353 Vals.push_back(Load);
7354 LoadChains.push_back(Load.getValue(1));
7356 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7357 DAG.getConstant(Stride, BasePtr.getValueType()));
7360 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7361 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7362 Op.getValueType(), Vals);
7364 if (LN->isIndexed()) {
7365 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7366 return DAG.getMergeValues(RetOps, dl);
7369 SDValue RetOps[] = { Value, TF };
7370 return DAG.getMergeValues(RetOps, dl);
7373 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7374 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7376 // To lower v4i1 from a byte array, we load the byte elements of the
7377 // vector and then reuse the BUILD_VECTOR logic.
7379 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7380 for (unsigned i = 0; i < 4; ++i) {
7381 SDValue Idx = DAG.getConstant(i, BasePtr.getValueType());
7382 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7384 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7385 dl, MVT::i32, LoadChain, Idx,
7386 LN->getPointerInfo().getWithOffset(i),
7387 MVT::i8 /* memory type */,
7388 LN->isVolatile(), LN->isNonTemporal(),
7390 1 /* alignment */, LN->getAAInfo()));
7391 VectElmtChains.push_back(VectElmts[i].getValue(1));
7394 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7395 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7397 SDValue RVals[] = { Value, LoadChain };
7398 return DAG.getMergeValues(RVals, dl);
7401 /// Lowering for QPX v4i1 stores
7402 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7403 SelectionDAG &DAG) const {
7405 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7406 SDValue StoreChain = SN->getChain();
7407 SDValue BasePtr = SN->getBasePtr();
7408 SDValue Value = SN->getValue();
7410 if (Value.getValueType() == MVT::v4f64 ||
7411 Value.getValueType() == MVT::v4f32) {
7412 EVT MemVT = SN->getMemoryVT();
7413 unsigned Alignment = SN->getAlignment();
7415 // If this store is properly aligned, then it is legal.
7416 if (Alignment >= MemVT.getStoreSize())
7419 EVT ScalarVT = Value.getValueType().getScalarType(),
7420 ScalarMemVT = MemVT.getScalarType();
7421 unsigned Stride = ScalarMemVT.getStoreSize();
7423 SmallVector<SDValue, 8> Stores;
7424 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7426 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7427 DAG.getConstant(Idx, getVectorIdxTy()));
7429 if (ScalarVT != ScalarMemVT)
7431 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7432 SN->getPointerInfo().getWithOffset(Idx*Stride),
7433 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7434 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7437 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7438 SN->getPointerInfo().getWithOffset(Idx*Stride),
7439 SN->isVolatile(), SN->isNonTemporal(),
7440 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7442 if (Idx == 0 && SN->isIndexed()) {
7443 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7444 "Unknown addressing mode on vector store");
7445 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7446 SN->getAddressingMode());
7449 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7450 DAG.getConstant(Stride, BasePtr.getValueType()));
7451 Stores.push_back(Store);
7454 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7456 if (SN->isIndexed()) {
7457 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7458 return DAG.getMergeValues(RetOps, dl);
7464 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7465 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7467 // The values are now known to be -1 (false) or 1 (true). To convert this
7468 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7469 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7470 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7472 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7473 // understand how to form the extending load.
7474 SDValue FPHalfs = DAG.getConstantFP(0.5, MVT::f64);
7475 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7476 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7478 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7480 // Now convert to an integer and store.
7481 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7482 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, MVT::i32),
7485 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7486 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7487 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7488 EVT PtrVT = getPointerTy();
7489 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7491 SmallVector<SDValue, 2> Ops;
7492 Ops.push_back(StoreChain);
7493 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, MVT::i32));
7494 Ops.push_back(Value);
7495 Ops.push_back(FIdx);
7497 SmallVector<EVT, 2> ValueVTs;
7498 ValueVTs.push_back(MVT::Other); // chain
7499 SDVTList VTs = DAG.getVTList(ValueVTs);
7501 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7502 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7504 // Move data into the byte array.
7505 SmallVector<SDValue, 4> Loads, LoadChains;
7506 for (unsigned i = 0; i < 4; ++i) {
7507 unsigned Offset = 4*i;
7508 SDValue Idx = DAG.getConstant(Offset, FIdx.getValueType());
7509 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7511 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7512 PtrInfo.getWithOffset(Offset),
7513 false, false, false, 0));
7514 LoadChains.push_back(Loads[i].getValue(1));
7517 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7519 SmallVector<SDValue, 4> Stores;
7520 for (unsigned i = 0; i < 4; ++i) {
7521 SDValue Idx = DAG.getConstant(i, BasePtr.getValueType());
7522 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7524 Stores.push_back(DAG.getTruncStore(StoreChain, dl, Loads[i], Idx,
7525 SN->getPointerInfo().getWithOffset(i),
7526 MVT::i8 /* memory type */,
7527 SN->isNonTemporal(), SN->isVolatile(),
7528 1 /* alignment */, SN->getAAInfo()));
7531 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7536 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7538 if (Op.getValueType() == MVT::v4i32) {
7539 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7541 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7542 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7544 SDValue RHSSwap = // = vrlw RHS, 16
7545 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7547 // Shrinkify inputs to v8i16.
7548 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7549 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7550 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7552 // Low parts multiplied together, generating 32-bit results (we ignore the
7554 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7555 LHS, RHS, DAG, dl, MVT::v4i32);
7557 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7558 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7559 // Shift the high parts up 16 bits.
7560 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7562 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7563 } else if (Op.getValueType() == MVT::v8i16) {
7564 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7566 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7568 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7569 LHS, RHS, Zero, DAG, dl);
7570 } else if (Op.getValueType() == MVT::v16i8) {
7571 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7572 bool isLittleEndian = Subtarget.isLittleEndian();
7574 // Multiply the even 8-bit parts, producing 16-bit sums.
7575 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7576 LHS, RHS, DAG, dl, MVT::v8i16);
7577 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7579 // Multiply the odd 8-bit parts, producing 16-bit sums.
7580 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7581 LHS, RHS, DAG, dl, MVT::v8i16);
7582 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7584 // Merge the results together. Because vmuleub and vmuloub are
7585 // instructions with a big-endian bias, we must reverse the
7586 // element numbering and reverse the meaning of "odd" and "even"
7587 // when generating little endian code.
7589 for (unsigned i = 0; i != 8; ++i) {
7590 if (isLittleEndian) {
7592 Ops[i*2+1] = 2*i+16;
7595 Ops[i*2+1] = 2*i+1+16;
7599 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7601 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7603 llvm_unreachable("Unknown mul to lower!");
7607 /// LowerOperation - Provide custom lowering hooks for some operations.
7609 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7610 switch (Op.getOpcode()) {
7611 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7612 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7613 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7614 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7615 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7616 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7617 case ISD::SETCC: return LowerSETCC(Op, DAG);
7618 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7619 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7621 return LowerVASTART(Op, DAG, Subtarget);
7624 return LowerVAARG(Op, DAG, Subtarget);
7627 return LowerVACOPY(Op, DAG, Subtarget);
7629 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7630 case ISD::DYNAMIC_STACKALLOC:
7631 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7633 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7634 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7636 case ISD::LOAD: return LowerLOAD(Op, DAG);
7637 case ISD::STORE: return LowerSTORE(Op, DAG);
7638 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7639 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7640 case ISD::FP_TO_UINT:
7641 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7643 case ISD::UINT_TO_FP:
7644 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7645 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7647 // Lower 64-bit shifts.
7648 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7649 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7650 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7652 // Vector-related lowering.
7653 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7654 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7655 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7656 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7657 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7658 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7659 case ISD::MUL: return LowerMUL(Op, DAG);
7661 // For counter-based loop handling.
7662 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7664 // Frame & Return address.
7665 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7666 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7670 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7671 SmallVectorImpl<SDValue>&Results,
7672 SelectionDAG &DAG) const {
7674 switch (N->getOpcode()) {
7676 llvm_unreachable("Do not know how to custom type legalize this operation!");
7677 case ISD::READCYCLECOUNTER: {
7678 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7679 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
7681 Results.push_back(RTB);
7682 Results.push_back(RTB.getValue(1));
7683 Results.push_back(RTB.getValue(2));
7686 case ISD::INTRINSIC_W_CHAIN: {
7687 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
7688 Intrinsic::ppc_is_decremented_ctr_nonzero)
7691 assert(N->getValueType(0) == MVT::i1 &&
7692 "Unexpected result type for CTR decrement intrinsic");
7693 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
7694 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
7695 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
7698 Results.push_back(NewInt);
7699 Results.push_back(NewInt.getValue(1));
7703 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
7706 EVT VT = N->getValueType(0);
7708 if (VT == MVT::i64) {
7709 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
7711 Results.push_back(NewNode);
7712 Results.push_back(NewNode.getValue(1));
7716 case ISD::FP_ROUND_INREG: {
7717 assert(N->getValueType(0) == MVT::ppcf128);
7718 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
7719 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7720 MVT::f64, N->getOperand(0),
7721 DAG.getIntPtrConstant(0));
7722 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7723 MVT::f64, N->getOperand(0),
7724 DAG.getIntPtrConstant(1));
7726 // Add the two halves of the long double in round-to-zero mode.
7727 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
7729 // We know the low half is about to be thrown away, so just use something
7731 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
7735 case ISD::FP_TO_SINT:
7736 // LowerFP_TO_INT() can only handle f32 and f64.
7737 if (N->getOperand(0).getValueType() == MVT::ppcf128)
7739 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
7745 //===----------------------------------------------------------------------===//
7746 // Other Lowering Code
7747 //===----------------------------------------------------------------------===//
7749 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
7750 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7751 Function *Func = Intrinsic::getDeclaration(M, Id);
7752 return Builder.CreateCall(Func);
7755 // The mappings for emitLeading/TrailingFence is taken from
7756 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
7757 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
7758 AtomicOrdering Ord, bool IsStore,
7759 bool IsLoad) const {
7760 if (Ord == SequentiallyConsistent)
7761 return callIntrinsic(Builder, Intrinsic::ppc_sync);
7762 else if (isAtLeastRelease(Ord))
7763 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
7768 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
7769 AtomicOrdering Ord, bool IsStore,
7770 bool IsLoad) const {
7771 if (IsLoad && isAtLeastAcquire(Ord))
7772 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
7773 // FIXME: this is too conservative, a dependent branch + isync is enough.
7774 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
7775 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
7776 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
7782 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
7783 unsigned AtomicSize,
7784 unsigned BinOpcode) const {
7785 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
7786 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7788 auto LoadMnemonic = PPC::LDARX;
7789 auto StoreMnemonic = PPC::STDCX;
7790 switch (AtomicSize) {
7792 llvm_unreachable("Unexpected size of atomic entity");
7794 LoadMnemonic = PPC::LBARX;
7795 StoreMnemonic = PPC::STBCX;
7796 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
7799 LoadMnemonic = PPC::LHARX;
7800 StoreMnemonic = PPC::STHCX;
7801 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
7804 LoadMnemonic = PPC::LWARX;
7805 StoreMnemonic = PPC::STWCX;
7808 LoadMnemonic = PPC::LDARX;
7809 StoreMnemonic = PPC::STDCX;
7813 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7814 MachineFunction *F = BB->getParent();
7815 MachineFunction::iterator It = BB;
7818 unsigned dest = MI->getOperand(0).getReg();
7819 unsigned ptrA = MI->getOperand(1).getReg();
7820 unsigned ptrB = MI->getOperand(2).getReg();
7821 unsigned incr = MI->getOperand(3).getReg();
7822 DebugLoc dl = MI->getDebugLoc();
7824 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
7825 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7826 F->insert(It, loopMBB);
7827 F->insert(It, exitMBB);
7828 exitMBB->splice(exitMBB->begin(), BB,
7829 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7830 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7832 MachineRegisterInfo &RegInfo = F->getRegInfo();
7833 unsigned TmpReg = (!BinOpcode) ? incr :
7834 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
7835 : &PPC::GPRCRegClass);
7839 // fallthrough --> loopMBB
7840 BB->addSuccessor(loopMBB);
7843 // l[wd]arx dest, ptr
7844 // add r0, dest, incr
7845 // st[wd]cx. r0, ptr
7847 // fallthrough --> exitMBB
7849 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
7850 .addReg(ptrA).addReg(ptrB);
7852 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
7853 BuildMI(BB, dl, TII->get(StoreMnemonic))
7854 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
7855 BuildMI(BB, dl, TII->get(PPC::BCC))
7856 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
7857 BB->addSuccessor(loopMBB);
7858 BB->addSuccessor(exitMBB);
7867 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
7868 MachineBasicBlock *BB,
7869 bool is8bit, // operation
7870 unsigned BinOpcode) const {
7871 // If we support part-word atomic mnemonics, just use them
7872 if (Subtarget.hasPartwordAtomics())
7873 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
7875 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
7876 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7877 // In 64 bit mode we have to use 64 bits for addresses, even though the
7878 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
7879 // registers without caring whether they're 32 or 64, but here we're
7880 // doing actual arithmetic on the addresses.
7881 bool is64bit = Subtarget.isPPC64();
7882 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7884 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7885 MachineFunction *F = BB->getParent();
7886 MachineFunction::iterator It = BB;
7889 unsigned dest = MI->getOperand(0).getReg();
7890 unsigned ptrA = MI->getOperand(1).getReg();
7891 unsigned ptrB = MI->getOperand(2).getReg();
7892 unsigned incr = MI->getOperand(3).getReg();
7893 DebugLoc dl = MI->getDebugLoc();
7895 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
7896 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7897 F->insert(It, loopMBB);
7898 F->insert(It, exitMBB);
7899 exitMBB->splice(exitMBB->begin(), BB,
7900 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7901 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7903 MachineRegisterInfo &RegInfo = F->getRegInfo();
7904 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7905 : &PPC::GPRCRegClass;
7906 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7907 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7908 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7909 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
7910 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7911 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7912 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7913 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7914 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
7915 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7916 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7918 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
7922 // fallthrough --> loopMBB
7923 BB->addSuccessor(loopMBB);
7925 // The 4-byte load must be aligned, while a char or short may be
7926 // anywhere in the word. Hence all this nasty bookkeeping code.
7927 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7928 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7929 // xori shift, shift1, 24 [16]
7930 // rlwinm ptr, ptr1, 0, 0, 29
7931 // slw incr2, incr, shift
7932 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7933 // slw mask, mask2, shift
7935 // lwarx tmpDest, ptr
7936 // add tmp, tmpDest, incr2
7937 // andc tmp2, tmpDest, mask
7938 // and tmp3, tmp, mask
7939 // or tmp4, tmp3, tmp2
7942 // fallthrough --> exitMBB
7943 // srw dest, tmpDest, shift
7944 if (ptrA != ZeroReg) {
7945 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7946 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7947 .addReg(ptrA).addReg(ptrB);
7951 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7952 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7953 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7954 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7956 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7957 .addReg(Ptr1Reg).addImm(0).addImm(61);
7959 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7960 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7961 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
7962 .addReg(incr).addReg(ShiftReg);
7964 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7966 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7967 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
7969 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7970 .addReg(Mask2Reg).addReg(ShiftReg);
7973 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7974 .addReg(ZeroReg).addReg(PtrReg);
7976 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
7977 .addReg(Incr2Reg).addReg(TmpDestReg);
7978 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
7979 .addReg(TmpDestReg).addReg(MaskReg);
7980 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
7981 .addReg(TmpReg).addReg(MaskReg);
7982 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
7983 .addReg(Tmp3Reg).addReg(Tmp2Reg);
7984 BuildMI(BB, dl, TII->get(PPC::STWCX))
7985 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
7986 BuildMI(BB, dl, TII->get(PPC::BCC))
7987 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
7988 BB->addSuccessor(loopMBB);
7989 BB->addSuccessor(exitMBB);
7994 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
7999 llvm::MachineBasicBlock*
8000 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8001 MachineBasicBlock *MBB) const {
8002 DebugLoc DL = MI->getDebugLoc();
8003 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8005 MachineFunction *MF = MBB->getParent();
8006 MachineRegisterInfo &MRI = MF->getRegInfo();
8008 const BasicBlock *BB = MBB->getBasicBlock();
8009 MachineFunction::iterator I = MBB;
8013 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8014 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8016 unsigned DstReg = MI->getOperand(0).getReg();
8017 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8018 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8019 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8020 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8022 MVT PVT = getPointerTy();
8023 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8024 "Invalid Pointer Size!");
8025 // For v = setjmp(buf), we generate
8028 // SjLjSetup mainMBB
8034 // buf[LabelOffset] = LR
8038 // v = phi(main, restore)
8041 MachineBasicBlock *thisMBB = MBB;
8042 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8043 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8044 MF->insert(I, mainMBB);
8045 MF->insert(I, sinkMBB);
8047 MachineInstrBuilder MIB;
8049 // Transfer the remainder of BB and its successor edges to sinkMBB.
8050 sinkMBB->splice(sinkMBB->begin(), MBB,
8051 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8052 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8054 // Note that the structure of the jmp_buf used here is not compatible
8055 // with that used by libc, and is not designed to be. Specifically, it
8056 // stores only those 'reserved' registers that LLVM does not otherwise
8057 // understand how to spill. Also, by convention, by the time this
8058 // intrinsic is called, Clang has already stored the frame address in the
8059 // first slot of the buffer and stack address in the third. Following the
8060 // X86 target code, we'll store the jump address in the second slot. We also
8061 // need to save the TOC pointer (R2) to handle jumps between shared
8062 // libraries, and that will be stored in the fourth slot. The thread
8063 // identifier (R13) is not affected.
8066 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8067 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8068 const int64_t BPOffset = 4 * PVT.getStoreSize();
8070 // Prepare IP either in reg.
8071 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8072 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8073 unsigned BufReg = MI->getOperand(1).getReg();
8075 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8076 setUsesTOCBasePtr(*MBB->getParent());
8077 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8081 MIB.setMemRefs(MMOBegin, MMOEnd);
8084 // Naked functions never have a base pointer, and so we use r1. For all
8085 // other functions, this decision must be delayed until during PEI.
8087 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8088 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8090 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8092 MIB = BuildMI(*thisMBB, MI, DL,
8093 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8097 MIB.setMemRefs(MMOBegin, MMOEnd);
8100 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8101 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8102 MIB.addRegMask(TRI->getNoPreservedMask());
8104 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8106 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8108 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8110 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
8111 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
8116 BuildMI(mainMBB, DL,
8117 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8120 if (Subtarget.isPPC64()) {
8121 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8123 .addImm(LabelOffset)
8126 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8128 .addImm(LabelOffset)
8132 MIB.setMemRefs(MMOBegin, MMOEnd);
8134 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8135 mainMBB->addSuccessor(sinkMBB);
8138 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8139 TII->get(PPC::PHI), DstReg)
8140 .addReg(mainDstReg).addMBB(mainMBB)
8141 .addReg(restoreDstReg).addMBB(thisMBB);
8143 MI->eraseFromParent();
8148 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8149 MachineBasicBlock *MBB) const {
8150 DebugLoc DL = MI->getDebugLoc();
8151 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8153 MachineFunction *MF = MBB->getParent();
8154 MachineRegisterInfo &MRI = MF->getRegInfo();
8157 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8158 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8160 MVT PVT = getPointerTy();
8161 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8162 "Invalid Pointer Size!");
8164 const TargetRegisterClass *RC =
8165 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8166 unsigned Tmp = MRI.createVirtualRegister(RC);
8167 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8168 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8169 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8173 : (Subtarget.isSVR4ABI() &&
8174 MF->getTarget().getRelocationModel() == Reloc::PIC_
8178 MachineInstrBuilder MIB;
8180 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8181 const int64_t SPOffset = 2 * PVT.getStoreSize();
8182 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8183 const int64_t BPOffset = 4 * PVT.getStoreSize();
8185 unsigned BufReg = MI->getOperand(0).getReg();
8187 // Reload FP (the jumped-to function may not have had a
8188 // frame pointer, and if so, then its r31 will be restored
8190 if (PVT == MVT::i64) {
8191 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8195 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8199 MIB.setMemRefs(MMOBegin, MMOEnd);
8202 if (PVT == MVT::i64) {
8203 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8204 .addImm(LabelOffset)
8207 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8208 .addImm(LabelOffset)
8211 MIB.setMemRefs(MMOBegin, MMOEnd);
8214 if (PVT == MVT::i64) {
8215 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8219 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8223 MIB.setMemRefs(MMOBegin, MMOEnd);
8226 if (PVT == MVT::i64) {
8227 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8231 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8235 MIB.setMemRefs(MMOBegin, MMOEnd);
8238 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8239 setUsesTOCBasePtr(*MBB->getParent());
8240 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8244 MIB.setMemRefs(MMOBegin, MMOEnd);
8248 BuildMI(*MBB, MI, DL,
8249 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8250 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8252 MI->eraseFromParent();
8257 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8258 MachineBasicBlock *BB) const {
8259 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8260 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8261 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8262 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8263 // Call lowering should have added an r2 operand to indicate a dependence
8264 // on the TOC base pointer value. It can't however, because there is no
8265 // way to mark the dependence as implicit there, and so the stackmap code
8266 // will confuse it with a regular operand. Instead, add the dependence
8268 setUsesTOCBasePtr(*BB->getParent());
8269 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8272 return emitPatchPoint(MI, BB);
8275 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8276 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8277 return emitEHSjLjSetJmp(MI, BB);
8278 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8279 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8280 return emitEHSjLjLongJmp(MI, BB);
8283 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8285 // To "insert" these instructions we actually have to insert their
8286 // control-flow patterns.
8287 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8288 MachineFunction::iterator It = BB;
8291 MachineFunction *F = BB->getParent();
8293 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8294 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8295 MI->getOpcode() == PPC::SELECT_I4 ||
8296 MI->getOpcode() == PPC::SELECT_I8)) {
8297 SmallVector<MachineOperand, 2> Cond;
8298 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8299 MI->getOpcode() == PPC::SELECT_CC_I8)
8300 Cond.push_back(MI->getOperand(4));
8302 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8303 Cond.push_back(MI->getOperand(1));
8305 DebugLoc dl = MI->getDebugLoc();
8306 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8307 Cond, MI->getOperand(2).getReg(),
8308 MI->getOperand(3).getReg());
8309 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8310 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8311 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8312 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8313 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8314 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8315 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8316 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8317 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8318 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8319 MI->getOpcode() == PPC::SELECT_I4 ||
8320 MI->getOpcode() == PPC::SELECT_I8 ||
8321 MI->getOpcode() == PPC::SELECT_F4 ||
8322 MI->getOpcode() == PPC::SELECT_F8 ||
8323 MI->getOpcode() == PPC::SELECT_QFRC ||
8324 MI->getOpcode() == PPC::SELECT_QSRC ||
8325 MI->getOpcode() == PPC::SELECT_QBRC ||
8326 MI->getOpcode() == PPC::SELECT_VRRC ||
8327 MI->getOpcode() == PPC::SELECT_VSFRC ||
8328 MI->getOpcode() == PPC::SELECT_VSRC) {
8329 // The incoming instruction knows the destination vreg to set, the
8330 // condition code register to branch on, the true/false values to
8331 // select between, and a branch opcode to use.
8336 // cmpTY ccX, r1, r2
8338 // fallthrough --> copy0MBB
8339 MachineBasicBlock *thisMBB = BB;
8340 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8341 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8342 DebugLoc dl = MI->getDebugLoc();
8343 F->insert(It, copy0MBB);
8344 F->insert(It, sinkMBB);
8346 // Transfer the remainder of BB and its successor edges to sinkMBB.
8347 sinkMBB->splice(sinkMBB->begin(), BB,
8348 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8349 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8351 // Next, add the true and fallthrough blocks as its successors.
8352 BB->addSuccessor(copy0MBB);
8353 BB->addSuccessor(sinkMBB);
8355 if (MI->getOpcode() == PPC::SELECT_I4 ||
8356 MI->getOpcode() == PPC::SELECT_I8 ||
8357 MI->getOpcode() == PPC::SELECT_F4 ||
8358 MI->getOpcode() == PPC::SELECT_F8 ||
8359 MI->getOpcode() == PPC::SELECT_QFRC ||
8360 MI->getOpcode() == PPC::SELECT_QSRC ||
8361 MI->getOpcode() == PPC::SELECT_QBRC ||
8362 MI->getOpcode() == PPC::SELECT_VRRC ||
8363 MI->getOpcode() == PPC::SELECT_VSFRC ||
8364 MI->getOpcode() == PPC::SELECT_VSRC) {
8365 BuildMI(BB, dl, TII->get(PPC::BC))
8366 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8368 unsigned SelectPred = MI->getOperand(4).getImm();
8369 BuildMI(BB, dl, TII->get(PPC::BCC))
8370 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8374 // %FalseValue = ...
8375 // # fallthrough to sinkMBB
8378 // Update machine-CFG edges
8379 BB->addSuccessor(sinkMBB);
8382 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8385 BuildMI(*BB, BB->begin(), dl,
8386 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8387 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8388 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8389 } else if (MI->getOpcode() == PPC::ReadTB) {
8390 // To read the 64-bit time-base register on a 32-bit target, we read the
8391 // two halves. Should the counter have wrapped while it was being read, we
8392 // need to try again.
8395 // mfspr Rx,TBU # load from TBU
8396 // mfspr Ry,TB # load from TB
8397 // mfspr Rz,TBU # load from TBU
8398 // cmpw crX,Rx,Rz # check if ‘old’=’new’
8399 // bne readLoop # branch if they're not equal
8402 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8403 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8404 DebugLoc dl = MI->getDebugLoc();
8405 F->insert(It, readMBB);
8406 F->insert(It, sinkMBB);
8408 // Transfer the remainder of BB and its successor edges to sinkMBB.
8409 sinkMBB->splice(sinkMBB->begin(), BB,
8410 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8411 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8413 BB->addSuccessor(readMBB);
8416 MachineRegisterInfo &RegInfo = F->getRegInfo();
8417 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8418 unsigned LoReg = MI->getOperand(0).getReg();
8419 unsigned HiReg = MI->getOperand(1).getReg();
8421 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8422 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8423 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8425 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8427 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8428 .addReg(HiReg).addReg(ReadAgainReg);
8429 BuildMI(BB, dl, TII->get(PPC::BCC))
8430 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8432 BB->addSuccessor(readMBB);
8433 BB->addSuccessor(sinkMBB);
8435 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8436 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8437 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8438 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8439 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8440 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8441 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8442 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8444 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8445 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8446 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8447 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8448 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8449 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8450 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8451 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8453 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8454 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8455 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8456 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8457 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8458 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8459 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8460 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8462 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8463 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8464 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8465 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8466 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8467 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8468 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8469 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8471 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8472 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8473 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8474 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8475 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8476 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8477 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8478 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8480 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8481 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8482 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8483 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8484 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8485 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8486 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8487 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8489 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8490 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8491 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8492 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8493 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8494 BB = EmitAtomicBinary(MI, BB, 4, 0);
8495 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8496 BB = EmitAtomicBinary(MI, BB, 8, 0);
8498 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8499 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8500 (Subtarget.hasPartwordAtomics() &&
8501 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8502 (Subtarget.hasPartwordAtomics() &&
8503 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8504 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8506 auto LoadMnemonic = PPC::LDARX;
8507 auto StoreMnemonic = PPC::STDCX;
8508 switch(MI->getOpcode()) {
8510 llvm_unreachable("Compare and swap of unknown size");
8511 case PPC::ATOMIC_CMP_SWAP_I8:
8512 LoadMnemonic = PPC::LBARX;
8513 StoreMnemonic = PPC::STBCX;
8514 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8516 case PPC::ATOMIC_CMP_SWAP_I16:
8517 LoadMnemonic = PPC::LHARX;
8518 StoreMnemonic = PPC::STHCX;
8519 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8521 case PPC::ATOMIC_CMP_SWAP_I32:
8522 LoadMnemonic = PPC::LWARX;
8523 StoreMnemonic = PPC::STWCX;
8525 case PPC::ATOMIC_CMP_SWAP_I64:
8526 LoadMnemonic = PPC::LDARX;
8527 StoreMnemonic = PPC::STDCX;
8530 unsigned dest = MI->getOperand(0).getReg();
8531 unsigned ptrA = MI->getOperand(1).getReg();
8532 unsigned ptrB = MI->getOperand(2).getReg();
8533 unsigned oldval = MI->getOperand(3).getReg();
8534 unsigned newval = MI->getOperand(4).getReg();
8535 DebugLoc dl = MI->getDebugLoc();
8537 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8538 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8539 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8540 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8541 F->insert(It, loop1MBB);
8542 F->insert(It, loop2MBB);
8543 F->insert(It, midMBB);
8544 F->insert(It, exitMBB);
8545 exitMBB->splice(exitMBB->begin(), BB,
8546 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8547 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8551 // fallthrough --> loopMBB
8552 BB->addSuccessor(loop1MBB);
8555 // l[bhwd]arx dest, ptr
8556 // cmp[wd] dest, oldval
8559 // st[bhwd]cx. newval, ptr
8563 // st[bhwd]cx. dest, ptr
8566 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8567 .addReg(ptrA).addReg(ptrB);
8568 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8569 .addReg(oldval).addReg(dest);
8570 BuildMI(BB, dl, TII->get(PPC::BCC))
8571 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8572 BB->addSuccessor(loop2MBB);
8573 BB->addSuccessor(midMBB);
8576 BuildMI(BB, dl, TII->get(StoreMnemonic))
8577 .addReg(newval).addReg(ptrA).addReg(ptrB);
8578 BuildMI(BB, dl, TII->get(PPC::BCC))
8579 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8580 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8581 BB->addSuccessor(loop1MBB);
8582 BB->addSuccessor(exitMBB);
8585 BuildMI(BB, dl, TII->get(StoreMnemonic))
8586 .addReg(dest).addReg(ptrA).addReg(ptrB);
8587 BB->addSuccessor(exitMBB);
8592 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8593 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8594 // We must use 64-bit registers for addresses when targeting 64-bit,
8595 // since we're actually doing arithmetic on them. Other registers
8597 bool is64bit = Subtarget.isPPC64();
8598 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8600 unsigned dest = MI->getOperand(0).getReg();
8601 unsigned ptrA = MI->getOperand(1).getReg();
8602 unsigned ptrB = MI->getOperand(2).getReg();
8603 unsigned oldval = MI->getOperand(3).getReg();
8604 unsigned newval = MI->getOperand(4).getReg();
8605 DebugLoc dl = MI->getDebugLoc();
8607 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8608 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8609 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8610 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8611 F->insert(It, loop1MBB);
8612 F->insert(It, loop2MBB);
8613 F->insert(It, midMBB);
8614 F->insert(It, exitMBB);
8615 exitMBB->splice(exitMBB->begin(), BB,
8616 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8617 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8619 MachineRegisterInfo &RegInfo = F->getRegInfo();
8620 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8621 : &PPC::GPRCRegClass;
8622 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8623 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8624 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8625 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8626 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8627 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8628 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8629 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8630 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8631 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8632 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8633 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8634 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8636 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8637 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8640 // fallthrough --> loopMBB
8641 BB->addSuccessor(loop1MBB);
8643 // The 4-byte load must be aligned, while a char or short may be
8644 // anywhere in the word. Hence all this nasty bookkeeping code.
8645 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8646 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8647 // xori shift, shift1, 24 [16]
8648 // rlwinm ptr, ptr1, 0, 0, 29
8649 // slw newval2, newval, shift
8650 // slw oldval2, oldval,shift
8651 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8652 // slw mask, mask2, shift
8653 // and newval3, newval2, mask
8654 // and oldval3, oldval2, mask
8656 // lwarx tmpDest, ptr
8657 // and tmp, tmpDest, mask
8658 // cmpw tmp, oldval3
8661 // andc tmp2, tmpDest, mask
8662 // or tmp4, tmp2, newval3
8667 // stwcx. tmpDest, ptr
8669 // srw dest, tmpDest, shift
8670 if (ptrA != ZeroReg) {
8671 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8672 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8673 .addReg(ptrA).addReg(ptrB);
8677 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8678 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8679 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8680 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8682 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8683 .addReg(Ptr1Reg).addImm(0).addImm(61);
8685 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8686 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8687 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
8688 .addReg(newval).addReg(ShiftReg);
8689 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
8690 .addReg(oldval).addReg(ShiftReg);
8692 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8694 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8695 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
8696 .addReg(Mask3Reg).addImm(65535);
8698 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8699 .addReg(Mask2Reg).addReg(ShiftReg);
8700 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
8701 .addReg(NewVal2Reg).addReg(MaskReg);
8702 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
8703 .addReg(OldVal2Reg).addReg(MaskReg);
8706 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8707 .addReg(ZeroReg).addReg(PtrReg);
8708 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
8709 .addReg(TmpDestReg).addReg(MaskReg);
8710 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
8711 .addReg(TmpReg).addReg(OldVal3Reg);
8712 BuildMI(BB, dl, TII->get(PPC::BCC))
8713 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8714 BB->addSuccessor(loop2MBB);
8715 BB->addSuccessor(midMBB);
8718 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
8719 .addReg(TmpDestReg).addReg(MaskReg);
8720 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
8721 .addReg(Tmp2Reg).addReg(NewVal3Reg);
8722 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
8723 .addReg(ZeroReg).addReg(PtrReg);
8724 BuildMI(BB, dl, TII->get(PPC::BCC))
8725 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8726 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8727 BB->addSuccessor(loop1MBB);
8728 BB->addSuccessor(exitMBB);
8731 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
8732 .addReg(ZeroReg).addReg(PtrReg);
8733 BB->addSuccessor(exitMBB);
8738 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
8740 } else if (MI->getOpcode() == PPC::FADDrtz) {
8741 // This pseudo performs an FADD with rounding mode temporarily forced
8742 // to round-to-zero. We emit this via custom inserter since the FPSCR
8743 // is not modeled at the SelectionDAG level.
8744 unsigned Dest = MI->getOperand(0).getReg();
8745 unsigned Src1 = MI->getOperand(1).getReg();
8746 unsigned Src2 = MI->getOperand(2).getReg();
8747 DebugLoc dl = MI->getDebugLoc();
8749 MachineRegisterInfo &RegInfo = F->getRegInfo();
8750 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
8752 // Save FPSCR value.
8753 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
8755 // Set rounding mode to round-to-zero.
8756 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
8757 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
8759 // Perform addition.
8760 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
8762 // Restore FPSCR value.
8763 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
8764 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
8765 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
8766 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
8767 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
8768 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
8769 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
8770 PPC::ANDIo8 : PPC::ANDIo;
8771 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
8772 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
8774 MachineRegisterInfo &RegInfo = F->getRegInfo();
8775 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
8776 &PPC::GPRCRegClass :
8777 &PPC::G8RCRegClass);
8779 DebugLoc dl = MI->getDebugLoc();
8780 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
8781 .addReg(MI->getOperand(1).getReg()).addImm(1);
8782 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
8783 MI->getOperand(0).getReg())
8784 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
8785 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
8786 DebugLoc Dl = MI->getDebugLoc();
8787 MachineRegisterInfo &RegInfo = F->getRegInfo();
8788 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8789 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
8792 llvm_unreachable("Unexpected instr type to insert");
8795 MI->eraseFromParent(); // The pseudo instruction is gone now.
8799 //===----------------------------------------------------------------------===//
8800 // Target Optimization Hooks
8801 //===----------------------------------------------------------------------===//
8803 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
8804 DAGCombinerInfo &DCI,
8805 unsigned &RefinementSteps,
8806 bool &UseOneConstNR) const {
8807 EVT VT = Operand.getValueType();
8808 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
8809 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
8810 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
8811 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
8812 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
8813 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
8814 // Convergence is quadratic, so we essentially double the number of digits
8815 // correct after every iteration. For both FRE and FRSQRTE, the minimum
8816 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
8817 // 2^-14. IEEE float has 23 digits and double has 52 digits.
8818 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
8819 if (VT.getScalarType() == MVT::f64)
8821 UseOneConstNR = true;
8822 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
8827 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
8828 DAGCombinerInfo &DCI,
8829 unsigned &RefinementSteps) const {
8830 EVT VT = Operand.getValueType();
8831 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
8832 (VT == MVT::f64 && Subtarget.hasFRE()) ||
8833 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
8834 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
8835 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
8836 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
8837 // Convergence is quadratic, so we essentially double the number of digits
8838 // correct after every iteration. For both FRE and FRSQRTE, the minimum
8839 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
8840 // 2^-14. IEEE float has 23 digits and double has 52 digits.
8841 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
8842 if (VT.getScalarType() == MVT::f64)
8844 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
8849 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8850 // Note: This functionality is used only when unsafe-fp-math is enabled, and
8851 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
8852 // enabled for division), this functionality is redundant with the default
8853 // combiner logic (once the division -> reciprocal/multiply transformation
8854 // has taken place). As a result, this matters more for older cores than for
8857 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8858 // reciprocal if there are two or more FDIVs (for embedded cores with only
8859 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
8860 switch (Subtarget.getDarwinDirective()) {
8862 return NumUsers > 2;
8865 case PPC::DIR_E500mc:
8866 case PPC::DIR_E5500:
8867 return NumUsers > 1;
8871 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
8872 unsigned Bytes, int Dist,
8873 SelectionDAG &DAG) {
8874 if (VT.getSizeInBits() / 8 != Bytes)
8877 SDValue BaseLoc = Base->getBasePtr();
8878 if (Loc.getOpcode() == ISD::FrameIndex) {
8879 if (BaseLoc.getOpcode() != ISD::FrameIndex)
8881 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8882 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
8883 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
8884 int FS = MFI->getObjectSize(FI);
8885 int BFS = MFI->getObjectSize(BFI);
8886 if (FS != BFS || FS != (int)Bytes) return false;
8887 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
8891 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
8892 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
8895 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8896 const GlobalValue *GV1 = nullptr;
8897 const GlobalValue *GV2 = nullptr;
8898 int64_t Offset1 = 0;
8899 int64_t Offset2 = 0;
8900 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
8901 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
8902 if (isGA1 && isGA2 && GV1 == GV2)
8903 return Offset1 == (Offset2 + Dist*Bytes);
8907 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
8908 // not enforce equality of the chain operands.
8909 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
8910 unsigned Bytes, int Dist,
8911 SelectionDAG &DAG) {
8912 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
8913 EVT VT = LS->getMemoryVT();
8914 SDValue Loc = LS->getBasePtr();
8915 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
8918 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
8920 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8921 default: return false;
8922 case Intrinsic::ppc_qpx_qvlfd:
8923 case Intrinsic::ppc_qpx_qvlfda:
8926 case Intrinsic::ppc_qpx_qvlfs:
8927 case Intrinsic::ppc_qpx_qvlfsa:
8930 case Intrinsic::ppc_qpx_qvlfcd:
8931 case Intrinsic::ppc_qpx_qvlfcda:
8934 case Intrinsic::ppc_qpx_qvlfcs:
8935 case Intrinsic::ppc_qpx_qvlfcsa:
8938 case Intrinsic::ppc_qpx_qvlfiwa:
8939 case Intrinsic::ppc_qpx_qvlfiwz:
8940 case Intrinsic::ppc_altivec_lvx:
8941 case Intrinsic::ppc_altivec_lvxl:
8942 case Intrinsic::ppc_vsx_lxvw4x:
8945 case Intrinsic::ppc_vsx_lxvd2x:
8948 case Intrinsic::ppc_altivec_lvebx:
8951 case Intrinsic::ppc_altivec_lvehx:
8954 case Intrinsic::ppc_altivec_lvewx:
8959 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
8962 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
8964 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8965 default: return false;
8966 case Intrinsic::ppc_qpx_qvstfd:
8967 case Intrinsic::ppc_qpx_qvstfda:
8970 case Intrinsic::ppc_qpx_qvstfs:
8971 case Intrinsic::ppc_qpx_qvstfsa:
8974 case Intrinsic::ppc_qpx_qvstfcd:
8975 case Intrinsic::ppc_qpx_qvstfcda:
8978 case Intrinsic::ppc_qpx_qvstfcs:
8979 case Intrinsic::ppc_qpx_qvstfcsa:
8982 case Intrinsic::ppc_qpx_qvstfiw:
8983 case Intrinsic::ppc_qpx_qvstfiwa:
8984 case Intrinsic::ppc_altivec_stvx:
8985 case Intrinsic::ppc_altivec_stvxl:
8986 case Intrinsic::ppc_vsx_stxvw4x:
8989 case Intrinsic::ppc_vsx_stxvd2x:
8992 case Intrinsic::ppc_altivec_stvebx:
8995 case Intrinsic::ppc_altivec_stvehx:
8998 case Intrinsic::ppc_altivec_stvewx:
9003 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9009 // Return true is there is a nearyby consecutive load to the one provided
9010 // (regardless of alignment). We search up and down the chain, looking though
9011 // token factors and other loads (but nothing else). As a result, a true result
9012 // indicates that it is safe to create a new consecutive load adjacent to the
9014 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9015 SDValue Chain = LD->getChain();
9016 EVT VT = LD->getMemoryVT();
9018 SmallSet<SDNode *, 16> LoadRoots;
9019 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9020 SmallSet<SDNode *, 16> Visited;
9022 // First, search up the chain, branching to follow all token-factor operands.
9023 // If we find a consecutive load, then we're done, otherwise, record all
9024 // nodes just above the top-level loads and token factors.
9025 while (!Queue.empty()) {
9026 SDNode *ChainNext = Queue.pop_back_val();
9027 if (!Visited.insert(ChainNext).second)
9030 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9031 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9034 if (!Visited.count(ChainLD->getChain().getNode()))
9035 Queue.push_back(ChainLD->getChain().getNode());
9036 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9037 for (const SDUse &O : ChainNext->ops())
9038 if (!Visited.count(O.getNode()))
9039 Queue.push_back(O.getNode());
9041 LoadRoots.insert(ChainNext);
9044 // Second, search down the chain, starting from the top-level nodes recorded
9045 // in the first phase. These top-level nodes are the nodes just above all
9046 // loads and token factors. Starting with their uses, recursively look though
9047 // all loads (just the chain uses) and token factors to find a consecutive
9052 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9053 IE = LoadRoots.end(); I != IE; ++I) {
9054 Queue.push_back(*I);
9056 while (!Queue.empty()) {
9057 SDNode *LoadRoot = Queue.pop_back_val();
9058 if (!Visited.insert(LoadRoot).second)
9061 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9062 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9065 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9066 UE = LoadRoot->use_end(); UI != UE; ++UI)
9067 if (((isa<MemSDNode>(*UI) &&
9068 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9069 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9070 Queue.push_back(*UI);
9077 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9078 DAGCombinerInfo &DCI) const {
9079 SelectionDAG &DAG = DCI.DAG;
9082 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9083 // If we're tracking CR bits, we need to be careful that we don't have:
9084 // trunc(binary-ops(zext(x), zext(y)))
9086 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9087 // such that we're unnecessarily moving things into GPRs when it would be
9088 // better to keep them in CR bits.
9090 // Note that trunc here can be an actual i1 trunc, or can be the effective
9091 // truncation that comes from a setcc or select_cc.
9092 if (N->getOpcode() == ISD::TRUNCATE &&
9093 N->getValueType(0) != MVT::i1)
9096 if (N->getOperand(0).getValueType() != MVT::i32 &&
9097 N->getOperand(0).getValueType() != MVT::i64)
9100 if (N->getOpcode() == ISD::SETCC ||
9101 N->getOpcode() == ISD::SELECT_CC) {
9102 // If we're looking at a comparison, then we need to make sure that the
9103 // high bits (all except for the first) don't matter the result.
9105 cast<CondCodeSDNode>(N->getOperand(
9106 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9107 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9109 if (ISD::isSignedIntSetCC(CC)) {
9110 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9111 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9113 } else if (ISD::isUnsignedIntSetCC(CC)) {
9114 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9115 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9116 !DAG.MaskedValueIsZero(N->getOperand(1),
9117 APInt::getHighBitsSet(OpBits, OpBits-1)))
9120 // This is neither a signed nor an unsigned comparison, just make sure
9121 // that the high bits are equal.
9122 APInt Op1Zero, Op1One;
9123 APInt Op2Zero, Op2One;
9124 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9125 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9127 // We don't really care about what is known about the first bit (if
9128 // anything), so clear it in all masks prior to comparing them.
9129 Op1Zero.clearBit(0); Op1One.clearBit(0);
9130 Op2Zero.clearBit(0); Op2One.clearBit(0);
9132 if (Op1Zero != Op2Zero || Op1One != Op2One)
9137 // We now know that the higher-order bits are irrelevant, we just need to
9138 // make sure that all of the intermediate operations are bit operations, and
9139 // all inputs are extensions.
9140 if (N->getOperand(0).getOpcode() != ISD::AND &&
9141 N->getOperand(0).getOpcode() != ISD::OR &&
9142 N->getOperand(0).getOpcode() != ISD::XOR &&
9143 N->getOperand(0).getOpcode() != ISD::SELECT &&
9144 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9145 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9146 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9147 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9148 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9151 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9152 N->getOperand(1).getOpcode() != ISD::AND &&
9153 N->getOperand(1).getOpcode() != ISD::OR &&
9154 N->getOperand(1).getOpcode() != ISD::XOR &&
9155 N->getOperand(1).getOpcode() != ISD::SELECT &&
9156 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9157 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9158 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9159 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9160 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9163 SmallVector<SDValue, 4> Inputs;
9164 SmallVector<SDValue, 8> BinOps, PromOps;
9165 SmallPtrSet<SDNode *, 16> Visited;
9167 for (unsigned i = 0; i < 2; ++i) {
9168 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9169 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9170 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9171 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9172 isa<ConstantSDNode>(N->getOperand(i)))
9173 Inputs.push_back(N->getOperand(i));
9175 BinOps.push_back(N->getOperand(i));
9177 if (N->getOpcode() == ISD::TRUNCATE)
9181 // Visit all inputs, collect all binary operations (and, or, xor and
9182 // select) that are all fed by extensions.
9183 while (!BinOps.empty()) {
9184 SDValue BinOp = BinOps.back();
9187 if (!Visited.insert(BinOp.getNode()).second)
9190 PromOps.push_back(BinOp);
9192 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9193 // The condition of the select is not promoted.
9194 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9196 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9199 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9200 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9201 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9202 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9203 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9204 Inputs.push_back(BinOp.getOperand(i));
9205 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9206 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9207 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9208 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9209 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9210 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9211 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9212 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9213 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9214 BinOps.push_back(BinOp.getOperand(i));
9216 // We have an input that is not an extension or another binary
9217 // operation; we'll abort this transformation.
9223 // Make sure that this is a self-contained cluster of operations (which
9224 // is not quite the same thing as saying that everything has only one
9226 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9227 if (isa<ConstantSDNode>(Inputs[i]))
9230 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9231 UE = Inputs[i].getNode()->use_end();
9234 if (User != N && !Visited.count(User))
9237 // Make sure that we're not going to promote the non-output-value
9238 // operand(s) or SELECT or SELECT_CC.
9239 // FIXME: Although we could sometimes handle this, and it does occur in
9240 // practice that one of the condition inputs to the select is also one of
9241 // the outputs, we currently can't deal with this.
9242 if (User->getOpcode() == ISD::SELECT) {
9243 if (User->getOperand(0) == Inputs[i])
9245 } else if (User->getOpcode() == ISD::SELECT_CC) {
9246 if (User->getOperand(0) == Inputs[i] ||
9247 User->getOperand(1) == Inputs[i])
9253 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9254 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9255 UE = PromOps[i].getNode()->use_end();
9258 if (User != N && !Visited.count(User))
9261 // Make sure that we're not going to promote the non-output-value
9262 // operand(s) or SELECT or SELECT_CC.
9263 // FIXME: Although we could sometimes handle this, and it does occur in
9264 // practice that one of the condition inputs to the select is also one of
9265 // the outputs, we currently can't deal with this.
9266 if (User->getOpcode() == ISD::SELECT) {
9267 if (User->getOperand(0) == PromOps[i])
9269 } else if (User->getOpcode() == ISD::SELECT_CC) {
9270 if (User->getOperand(0) == PromOps[i] ||
9271 User->getOperand(1) == PromOps[i])
9277 // Replace all inputs with the extension operand.
9278 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9279 // Constants may have users outside the cluster of to-be-promoted nodes,
9280 // and so we need to replace those as we do the promotions.
9281 if (isa<ConstantSDNode>(Inputs[i]))
9284 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9287 // Replace all operations (these are all the same, but have a different
9288 // (i1) return type). DAG.getNode will validate that the types of
9289 // a binary operator match, so go through the list in reverse so that
9290 // we've likely promoted both operands first. Any intermediate truncations or
9291 // extensions disappear.
9292 while (!PromOps.empty()) {
9293 SDValue PromOp = PromOps.back();
9296 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9297 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9298 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9299 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9300 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9301 PromOp.getOperand(0).getValueType() != MVT::i1) {
9302 // The operand is not yet ready (see comment below).
9303 PromOps.insert(PromOps.begin(), PromOp);
9307 SDValue RepValue = PromOp.getOperand(0);
9308 if (isa<ConstantSDNode>(RepValue))
9309 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9311 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9316 switch (PromOp.getOpcode()) {
9317 default: C = 0; break;
9318 case ISD::SELECT: C = 1; break;
9319 case ISD::SELECT_CC: C = 2; break;
9322 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9323 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9324 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9325 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9326 // The to-be-promoted operands of this node have not yet been
9327 // promoted (this should be rare because we're going through the
9328 // list backward, but if one of the operands has several users in
9329 // this cluster of to-be-promoted nodes, it is possible).
9330 PromOps.insert(PromOps.begin(), PromOp);
9334 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9335 PromOp.getNode()->op_end());
9337 // If there are any constant inputs, make sure they're replaced now.
9338 for (unsigned i = 0; i < 2; ++i)
9339 if (isa<ConstantSDNode>(Ops[C+i]))
9340 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9342 DAG.ReplaceAllUsesOfValueWith(PromOp,
9343 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9346 // Now we're left with the initial truncation itself.
9347 if (N->getOpcode() == ISD::TRUNCATE)
9348 return N->getOperand(0);
9350 // Otherwise, this is a comparison. The operands to be compared have just
9351 // changed type (to i1), but everything else is the same.
9352 return SDValue(N, 0);
9355 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9356 DAGCombinerInfo &DCI) const {
9357 SelectionDAG &DAG = DCI.DAG;
9360 // If we're tracking CR bits, we need to be careful that we don't have:
9361 // zext(binary-ops(trunc(x), trunc(y)))
9363 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9364 // such that we're unnecessarily moving things into CR bits that can more
9365 // efficiently stay in GPRs. Note that if we're not certain that the high
9366 // bits are set as required by the final extension, we still may need to do
9367 // some masking to get the proper behavior.
9369 // This same functionality is important on PPC64 when dealing with
9370 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9371 // the return values of functions. Because it is so similar, it is handled
9374 if (N->getValueType(0) != MVT::i32 &&
9375 N->getValueType(0) != MVT::i64)
9378 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9379 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9382 if (N->getOperand(0).getOpcode() != ISD::AND &&
9383 N->getOperand(0).getOpcode() != ISD::OR &&
9384 N->getOperand(0).getOpcode() != ISD::XOR &&
9385 N->getOperand(0).getOpcode() != ISD::SELECT &&
9386 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9389 SmallVector<SDValue, 4> Inputs;
9390 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9391 SmallPtrSet<SDNode *, 16> Visited;
9393 // Visit all inputs, collect all binary operations (and, or, xor and
9394 // select) that are all fed by truncations.
9395 while (!BinOps.empty()) {
9396 SDValue BinOp = BinOps.back();
9399 if (!Visited.insert(BinOp.getNode()).second)
9402 PromOps.push_back(BinOp);
9404 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9405 // The condition of the select is not promoted.
9406 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9408 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9411 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9412 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9413 Inputs.push_back(BinOp.getOperand(i));
9414 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9415 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9416 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9417 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9418 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9419 BinOps.push_back(BinOp.getOperand(i));
9421 // We have an input that is not a truncation or another binary
9422 // operation; we'll abort this transformation.
9428 // The operands of a select that must be truncated when the select is
9429 // promoted because the operand is actually part of the to-be-promoted set.
9430 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9432 // Make sure that this is a self-contained cluster of operations (which
9433 // is not quite the same thing as saying that everything has only one
9435 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9436 if (isa<ConstantSDNode>(Inputs[i]))
9439 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9440 UE = Inputs[i].getNode()->use_end();
9443 if (User != N && !Visited.count(User))
9446 // If we're going to promote the non-output-value operand(s) or SELECT or
9447 // SELECT_CC, record them for truncation.
9448 if (User->getOpcode() == ISD::SELECT) {
9449 if (User->getOperand(0) == Inputs[i])
9450 SelectTruncOp[0].insert(std::make_pair(User,
9451 User->getOperand(0).getValueType()));
9452 } else if (User->getOpcode() == ISD::SELECT_CC) {
9453 if (User->getOperand(0) == Inputs[i])
9454 SelectTruncOp[0].insert(std::make_pair(User,
9455 User->getOperand(0).getValueType()));
9456 if (User->getOperand(1) == Inputs[i])
9457 SelectTruncOp[1].insert(std::make_pair(User,
9458 User->getOperand(1).getValueType()));
9463 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9464 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9465 UE = PromOps[i].getNode()->use_end();
9468 if (User != N && !Visited.count(User))
9471 // If we're going to promote the non-output-value operand(s) or SELECT or
9472 // SELECT_CC, record them for truncation.
9473 if (User->getOpcode() == ISD::SELECT) {
9474 if (User->getOperand(0) == PromOps[i])
9475 SelectTruncOp[0].insert(std::make_pair(User,
9476 User->getOperand(0).getValueType()));
9477 } else if (User->getOpcode() == ISD::SELECT_CC) {
9478 if (User->getOperand(0) == PromOps[i])
9479 SelectTruncOp[0].insert(std::make_pair(User,
9480 User->getOperand(0).getValueType()));
9481 if (User->getOperand(1) == PromOps[i])
9482 SelectTruncOp[1].insert(std::make_pair(User,
9483 User->getOperand(1).getValueType()));
9488 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9489 bool ReallyNeedsExt = false;
9490 if (N->getOpcode() != ISD::ANY_EXTEND) {
9491 // If all of the inputs are not already sign/zero extended, then
9492 // we'll still need to do that at the end.
9493 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9494 if (isa<ConstantSDNode>(Inputs[i]))
9498 Inputs[i].getOperand(0).getValueSizeInBits();
9499 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9501 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9502 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9503 APInt::getHighBitsSet(OpBits,
9504 OpBits-PromBits))) ||
9505 (N->getOpcode() == ISD::SIGN_EXTEND &&
9506 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9507 (OpBits-(PromBits-1)))) {
9508 ReallyNeedsExt = true;
9514 // Replace all inputs, either with the truncation operand, or a
9515 // truncation or extension to the final output type.
9516 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9517 // Constant inputs need to be replaced with the to-be-promoted nodes that
9518 // use them because they might have users outside of the cluster of
9520 if (isa<ConstantSDNode>(Inputs[i]))
9523 SDValue InSrc = Inputs[i].getOperand(0);
9524 if (Inputs[i].getValueType() == N->getValueType(0))
9525 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9526 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9527 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9528 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9529 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9530 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9531 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9533 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9534 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9537 // Replace all operations (these are all the same, but have a different
9538 // (promoted) return type). DAG.getNode will validate that the types of
9539 // a binary operator match, so go through the list in reverse so that
9540 // we've likely promoted both operands first.
9541 while (!PromOps.empty()) {
9542 SDValue PromOp = PromOps.back();
9546 switch (PromOp.getOpcode()) {
9547 default: C = 0; break;
9548 case ISD::SELECT: C = 1; break;
9549 case ISD::SELECT_CC: C = 2; break;
9552 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9553 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9554 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9555 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9556 // The to-be-promoted operands of this node have not yet been
9557 // promoted (this should be rare because we're going through the
9558 // list backward, but if one of the operands has several users in
9559 // this cluster of to-be-promoted nodes, it is possible).
9560 PromOps.insert(PromOps.begin(), PromOp);
9564 // For SELECT and SELECT_CC nodes, we do a similar check for any
9565 // to-be-promoted comparison inputs.
9566 if (PromOp.getOpcode() == ISD::SELECT ||
9567 PromOp.getOpcode() == ISD::SELECT_CC) {
9568 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9569 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9570 (SelectTruncOp[1].count(PromOp.getNode()) &&
9571 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9572 PromOps.insert(PromOps.begin(), PromOp);
9577 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9578 PromOp.getNode()->op_end());
9580 // If this node has constant inputs, then they'll need to be promoted here.
9581 for (unsigned i = 0; i < 2; ++i) {
9582 if (!isa<ConstantSDNode>(Ops[C+i]))
9584 if (Ops[C+i].getValueType() == N->getValueType(0))
9587 if (N->getOpcode() == ISD::SIGN_EXTEND)
9588 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9589 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9590 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9592 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9595 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9596 // truncate them again to the original value type.
9597 if (PromOp.getOpcode() == ISD::SELECT ||
9598 PromOp.getOpcode() == ISD::SELECT_CC) {
9599 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9600 if (SI0 != SelectTruncOp[0].end())
9601 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9602 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9603 if (SI1 != SelectTruncOp[1].end())
9604 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9607 DAG.ReplaceAllUsesOfValueWith(PromOp,
9608 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9611 // Now we're left with the initial extension itself.
9612 if (!ReallyNeedsExt)
9613 return N->getOperand(0);
9615 // To zero extend, just mask off everything except for the first bit (in the
9617 if (N->getOpcode() == ISD::ZERO_EXTEND)
9618 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9619 DAG.getConstant(APInt::getLowBitsSet(
9620 N->getValueSizeInBits(0), PromBits),
9621 N->getValueType(0)));
9623 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9624 "Invalid extension type");
9625 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
9627 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
9628 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
9629 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
9630 N->getOperand(0), ShiftCst), ShiftCst);
9633 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9634 DAGCombinerInfo &DCI) const {
9635 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9636 N->getOpcode() == ISD::UINT_TO_FP) &&
9637 "Need an int -> FP conversion node here");
9639 if (!Subtarget.has64BitSupport())
9642 SelectionDAG &DAG = DCI.DAG;
9646 // Don't handle ppc_fp128 here or i1 conversions.
9647 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9649 if (Op.getOperand(0).getValueType() == MVT::i1)
9652 // For i32 intermediate values, unfortunately, the conversion functions
9653 // leave the upper 32 bits of the value are undefined. Within the set of
9654 // scalar instructions, we have no method for zero- or sign-extending the
9655 // value. Thus, we cannot handle i32 intermediate values here.
9656 if (Op.getOperand(0).getValueType() == MVT::i32)
9659 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
9660 "UINT_TO_FP is supported only with FPCVT");
9662 // If we have FCFIDS, then use it when converting to single-precision.
9663 // Otherwise, convert to double-precision and then round.
9664 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9665 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
9667 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
9669 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9673 // If we're converting from a float, to an int, and back to a float again,
9674 // then we don't need the store/load pair at all.
9675 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
9676 Subtarget.hasFPCVT()) ||
9677 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
9678 SDValue Src = Op.getOperand(0).getOperand(0);
9679 if (Src.getValueType() == MVT::f32) {
9680 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
9681 DCI.AddToWorklist(Src.getNode());
9685 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
9688 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
9689 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
9691 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
9692 FP = DAG.getNode(ISD::FP_ROUND, dl,
9693 MVT::f32, FP, DAG.getIntPtrConstant(0));
9694 DCI.AddToWorklist(FP.getNode());
9703 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
9704 // builtins) into loads with swaps.
9705 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
9706 DAGCombinerInfo &DCI) const {
9707 SelectionDAG &DAG = DCI.DAG;
9711 MachineMemOperand *MMO;
9713 switch (N->getOpcode()) {
9715 llvm_unreachable("Unexpected opcode for little endian VSX load");
9717 LoadSDNode *LD = cast<LoadSDNode>(N);
9718 Chain = LD->getChain();
9719 Base = LD->getBasePtr();
9720 MMO = LD->getMemOperand();
9721 // If the MMO suggests this isn't a load of a full vector, leave
9722 // things alone. For a built-in, we have to make the change for
9723 // correctness, so if there is a size problem that will be a bug.
9724 if (MMO->getSize() < 16)
9728 case ISD::INTRINSIC_W_CHAIN: {
9729 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
9730 Chain = Intrin->getChain();
9731 Base = Intrin->getBasePtr();
9732 MMO = Intrin->getMemOperand();
9737 MVT VecTy = N->getValueType(0).getSimpleVT();
9738 SDValue LoadOps[] = { Chain, Base };
9739 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
9740 DAG.getVTList(VecTy, MVT::Other),
9741 LoadOps, VecTy, MMO);
9742 DCI.AddToWorklist(Load.getNode());
9743 Chain = Load.getValue(1);
9744 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
9745 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
9746 DCI.AddToWorklist(Swap.getNode());
9750 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
9751 // builtins) into stores with swaps.
9752 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
9753 DAGCombinerInfo &DCI) const {
9754 SelectionDAG &DAG = DCI.DAG;
9759 MachineMemOperand *MMO;
9761 switch (N->getOpcode()) {
9763 llvm_unreachable("Unexpected opcode for little endian VSX store");
9765 StoreSDNode *ST = cast<StoreSDNode>(N);
9766 Chain = ST->getChain();
9767 Base = ST->getBasePtr();
9768 MMO = ST->getMemOperand();
9770 // If the MMO suggests this isn't a store of a full vector, leave
9771 // things alone. For a built-in, we have to make the change for
9772 // correctness, so if there is a size problem that will be a bug.
9773 if (MMO->getSize() < 16)
9777 case ISD::INTRINSIC_VOID: {
9778 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
9779 Chain = Intrin->getChain();
9780 // Intrin->getBasePtr() oddly does not get what we want.
9781 Base = Intrin->getOperand(3);
9782 MMO = Intrin->getMemOperand();
9788 SDValue Src = N->getOperand(SrcOpnd);
9789 MVT VecTy = Src.getValueType().getSimpleVT();
9790 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
9791 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
9792 DCI.AddToWorklist(Swap.getNode());
9793 Chain = Swap.getValue(1);
9794 SDValue StoreOps[] = { Chain, Swap, Base };
9795 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
9796 DAG.getVTList(MVT::Other),
9797 StoreOps, VecTy, MMO);
9798 DCI.AddToWorklist(Store.getNode());
9802 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
9803 DAGCombinerInfo &DCI) const {
9804 SelectionDAG &DAG = DCI.DAG;
9806 switch (N->getOpcode()) {
9809 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9810 if (C->isNullValue()) // 0 << V -> 0.
9811 return N->getOperand(0);
9815 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9816 if (C->isNullValue()) // 0 >>u V -> 0.
9817 return N->getOperand(0);
9821 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9822 if (C->isNullValue() || // 0 >>s V -> 0.
9823 C->isAllOnesValue()) // -1 >>s V -> -1.
9824 return N->getOperand(0);
9827 case ISD::SIGN_EXTEND:
9828 case ISD::ZERO_EXTEND:
9829 case ISD::ANY_EXTEND:
9830 return DAGCombineExtBoolTrunc(N, DCI);
9833 case ISD::SELECT_CC:
9834 return DAGCombineTruncBoolExt(N, DCI);
9835 case ISD::SINT_TO_FP:
9836 case ISD::UINT_TO_FP:
9837 return combineFPToIntToFP(N, DCI);
9839 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
9840 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
9841 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
9842 N->getOperand(1).getValueType() == MVT::i32 &&
9843 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
9844 SDValue Val = N->getOperand(1).getOperand(0);
9845 if (Val.getValueType() == MVT::f32) {
9846 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
9847 DCI.AddToWorklist(Val.getNode());
9849 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
9850 DCI.AddToWorklist(Val.getNode());
9853 N->getOperand(0), Val, N->getOperand(2),
9854 DAG.getValueType(N->getOperand(1).getValueType())
9857 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
9858 DAG.getVTList(MVT::Other), Ops,
9859 cast<StoreSDNode>(N)->getMemoryVT(),
9860 cast<StoreSDNode>(N)->getMemOperand());
9861 DCI.AddToWorklist(Val.getNode());
9865 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
9866 if (cast<StoreSDNode>(N)->isUnindexed() &&
9867 N->getOperand(1).getOpcode() == ISD::BSWAP &&
9868 N->getOperand(1).getNode()->hasOneUse() &&
9869 (N->getOperand(1).getValueType() == MVT::i32 ||
9870 N->getOperand(1).getValueType() == MVT::i16 ||
9871 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
9872 N->getOperand(1).getValueType() == MVT::i64))) {
9873 SDValue BSwapOp = N->getOperand(1).getOperand(0);
9874 // Do an any-extend to 32-bits if this is a half-word input.
9875 if (BSwapOp.getValueType() == MVT::i16)
9876 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
9879 N->getOperand(0), BSwapOp, N->getOperand(2),
9880 DAG.getValueType(N->getOperand(1).getValueType())
9883 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
9884 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
9885 cast<StoreSDNode>(N)->getMemOperand());
9888 // For little endian, VSX stores require generating xxswapd/lxvd2x.
9889 EVT VT = N->getOperand(1).getValueType();
9890 if (VT.isSimple()) {
9891 MVT StoreVT = VT.getSimpleVT();
9892 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
9893 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
9894 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
9895 return expandVSXStoreForLE(N, DCI);
9900 LoadSDNode *LD = cast<LoadSDNode>(N);
9901 EVT VT = LD->getValueType(0);
9903 // For little endian, VSX loads require generating lxvd2x/xxswapd.
9904 if (VT.isSimple()) {
9905 MVT LoadVT = VT.getSimpleVT();
9906 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
9907 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
9908 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
9909 return expandVSXLoadForLE(N, DCI);
9912 EVT MemVT = LD->getMemoryVT();
9913 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
9914 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
9915 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
9916 unsigned ScalarABIAlignment = getDataLayout()->getABITypeAlignment(STy);
9917 if (LD->isUnindexed() && VT.isVector() &&
9918 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
9919 // P8 and later hardware should just use LOAD.
9920 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
9921 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
9922 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
9923 LD->getAlignment() >= ScalarABIAlignment)) &&
9924 LD->getAlignment() < ABIAlignment) {
9925 // This is a type-legal unaligned Altivec or QPX load.
9926 SDValue Chain = LD->getChain();
9927 SDValue Ptr = LD->getBasePtr();
9928 bool isLittleEndian = Subtarget.isLittleEndian();
9930 // This implements the loading of unaligned vectors as described in
9931 // the venerable Apple Velocity Engine overview. Specifically:
9932 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
9933 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
9935 // The general idea is to expand a sequence of one or more unaligned
9936 // loads into an alignment-based permutation-control instruction (lvsl
9937 // or lvsr), a series of regular vector loads (which always truncate
9938 // their input address to an aligned address), and a series of
9939 // permutations. The results of these permutations are the requested
9940 // loaded values. The trick is that the last "extra" load is not taken
9941 // from the address you might suspect (sizeof(vector) bytes after the
9942 // last requested load), but rather sizeof(vector) - 1 bytes after the
9943 // last requested vector. The point of this is to avoid a page fault if
9944 // the base address happened to be aligned. This works because if the
9945 // base address is aligned, then adding less than a full vector length
9946 // will cause the last vector in the sequence to be (re)loaded.
9947 // Otherwise, the next vector will be fetched as you might suspect was
9950 // We might be able to reuse the permutation generation from
9951 // a different base address offset from this one by an aligned amount.
9952 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
9953 // optimization later.
9954 Intrinsic::ID Intr, IntrLD, IntrPerm;
9955 MVT PermCntlTy, PermTy, LDTy;
9956 if (Subtarget.hasAltivec()) {
9957 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
9958 Intrinsic::ppc_altivec_lvsl;
9959 IntrLD = Intrinsic::ppc_altivec_lvx;
9960 IntrPerm = Intrinsic::ppc_altivec_vperm;
9961 PermCntlTy = MVT::v16i8;
9962 PermTy = MVT::v4i32;
9965 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
9966 Intrinsic::ppc_qpx_qvlpcls;
9967 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
9968 Intrinsic::ppc_qpx_qvlfs;
9969 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
9970 PermCntlTy = MVT::v4f64;
9971 PermTy = MVT::v4f64;
9972 LDTy = MemVT.getSimpleVT();
9975 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
9977 // Create the new MMO for the new base load. It is like the original MMO,
9978 // but represents an area in memory almost twice the vector size centered
9979 // on the original address. If the address is unaligned, we might start
9980 // reading up to (sizeof(vector)-1) bytes below the address of the
9981 // original unaligned load.
9982 MachineFunction &MF = DAG.getMachineFunction();
9983 MachineMemOperand *BaseMMO =
9984 MF.getMachineMemOperand(LD->getMemOperand(), -MemVT.getStoreSize()+1,
9985 2*MemVT.getStoreSize()-1);
9987 // Create the new base load.
9988 SDValue LDXIntID = DAG.getTargetConstant(IntrLD, getPointerTy());
9989 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
9991 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
9992 DAG.getVTList(PermTy, MVT::Other),
9993 BaseLoadOps, LDTy, BaseMMO);
9995 // Note that the value of IncOffset (which is provided to the next
9996 // load's pointer info offset value, and thus used to calculate the
9997 // alignment), and the value of IncValue (which is actually used to
9998 // increment the pointer value) are different! This is because we
9999 // require the next load to appear to be aligned, even though it
10000 // is actually offset from the base pointer by a lesser amount.
10001 int IncOffset = VT.getSizeInBits() / 8;
10002 int IncValue = IncOffset;
10004 // Walk (both up and down) the chain looking for another load at the real
10005 // (aligned) offset (the alignment of the other load does not matter in
10006 // this case). If found, then do not use the offset reduction trick, as
10007 // that will prevent the loads from being later combined (as they would
10008 // otherwise be duplicates).
10009 if (!findConsecutiveLoad(LD, DAG))
10012 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
10013 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10015 MachineMemOperand *ExtraMMO =
10016 MF.getMachineMemOperand(LD->getMemOperand(),
10017 1, 2*MemVT.getStoreSize()-1);
10018 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10019 SDValue ExtraLoad =
10020 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10021 DAG.getVTList(PermTy, MVT::Other),
10022 ExtraLoadOps, LDTy, ExtraMMO);
10024 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10025 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10027 // Because vperm has a big-endian bias, we must reverse the order
10028 // of the input vectors and complement the permute control vector
10029 // when generating little endian code. We have already handled the
10030 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10031 // and ExtraLoad here.
10033 if (isLittleEndian)
10034 Perm = BuildIntrinsicOp(IntrPerm,
10035 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10037 Perm = BuildIntrinsicOp(IntrPerm,
10038 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10041 Perm = Subtarget.hasAltivec() ?
10042 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10043 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10044 DAG.getTargetConstant(1, MVT::i64));
10045 // second argument is 1 because this rounding
10046 // is always exact.
10048 // The output of the permutation is our loaded result, the TokenFactor is
10050 DCI.CombineTo(N, Perm, TF);
10051 return SDValue(N, 0);
10055 case ISD::INTRINSIC_WO_CHAIN: {
10056 bool isLittleEndian = Subtarget.isLittleEndian();
10057 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10058 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10059 : Intrinsic::ppc_altivec_lvsl);
10060 if ((IID == Intr ||
10061 IID == Intrinsic::ppc_qpx_qvlpcld ||
10062 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10063 N->getOperand(1)->getOpcode() == ISD::ADD) {
10064 SDValue Add = N->getOperand(1);
10066 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10067 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10069 if (DAG.MaskedValueIsZero(
10070 Add->getOperand(1),
10071 APInt::getAllOnesValue(Bits /* alignment */)
10073 Add.getValueType().getScalarType().getSizeInBits()))) {
10074 SDNode *BasePtr = Add->getOperand(0).getNode();
10075 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10076 UE = BasePtr->use_end();
10078 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10079 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10080 // We've found another LVSL/LVSR, and this address is an aligned
10081 // multiple of that one. The results will be the same, so use the
10082 // one we've just found instead.
10084 return SDValue(*UI, 0);
10089 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10090 SDNode *BasePtr = Add->getOperand(0).getNode();
10091 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10092 UE = BasePtr->use_end(); UI != UE; ++UI) {
10093 if (UI->getOpcode() == ISD::ADD &&
10094 isa<ConstantSDNode>(UI->getOperand(1)) &&
10095 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10096 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10097 (1ULL << Bits) == 0) {
10098 SDNode *OtherAdd = *UI;
10099 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10100 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10101 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10102 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10103 return SDValue(*VI, 0);
10113 case ISD::INTRINSIC_W_CHAIN: {
10114 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10115 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10116 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10119 case Intrinsic::ppc_vsx_lxvw4x:
10120 case Intrinsic::ppc_vsx_lxvd2x:
10121 return expandVSXLoadForLE(N, DCI);
10126 case ISD::INTRINSIC_VOID: {
10127 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10128 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10129 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10132 case Intrinsic::ppc_vsx_stxvw4x:
10133 case Intrinsic::ppc_vsx_stxvd2x:
10134 return expandVSXStoreForLE(N, DCI);
10140 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10141 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10142 N->getOperand(0).hasOneUse() &&
10143 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10144 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10145 N->getValueType(0) == MVT::i64))) {
10146 SDValue Load = N->getOperand(0);
10147 LoadSDNode *LD = cast<LoadSDNode>(Load);
10148 // Create the byte-swapping load.
10150 LD->getChain(), // Chain
10151 LD->getBasePtr(), // Ptr
10152 DAG.getValueType(N->getValueType(0)) // VT
10155 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10156 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10157 MVT::i64 : MVT::i32, MVT::Other),
10158 Ops, LD->getMemoryVT(), LD->getMemOperand());
10160 // If this is an i16 load, insert the truncate.
10161 SDValue ResVal = BSLoad;
10162 if (N->getValueType(0) == MVT::i16)
10163 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10165 // First, combine the bswap away. This makes the value produced by the
10167 DCI.CombineTo(N, ResVal);
10169 // Next, combine the load away, we give it a bogus result value but a real
10170 // chain result. The result value is dead because the bswap is dead.
10171 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10173 // Return N so it doesn't get rechecked!
10174 return SDValue(N, 0);
10178 case PPCISD::VCMP: {
10179 // If a VCMPo node already exists with exactly the same operands as this
10180 // node, use its result instead of this node (VCMPo computes both a CR6 and
10181 // a normal output).
10183 if (!N->getOperand(0).hasOneUse() &&
10184 !N->getOperand(1).hasOneUse() &&
10185 !N->getOperand(2).hasOneUse()) {
10187 // Scan all of the users of the LHS, looking for VCMPo's that match.
10188 SDNode *VCMPoNode = nullptr;
10190 SDNode *LHSN = N->getOperand(0).getNode();
10191 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10193 if (UI->getOpcode() == PPCISD::VCMPo &&
10194 UI->getOperand(1) == N->getOperand(1) &&
10195 UI->getOperand(2) == N->getOperand(2) &&
10196 UI->getOperand(0) == N->getOperand(0)) {
10201 // If there is no VCMPo node, or if the flag value has a single use, don't
10203 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10206 // Look at the (necessarily single) use of the flag value. If it has a
10207 // chain, this transformation is more complex. Note that multiple things
10208 // could use the value result, which we should ignore.
10209 SDNode *FlagUser = nullptr;
10210 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10211 FlagUser == nullptr; ++UI) {
10212 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10213 SDNode *User = *UI;
10214 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10215 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10222 // If the user is a MFOCRF instruction, we know this is safe.
10223 // Otherwise we give up for right now.
10224 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10225 return SDValue(VCMPoNode, 0);
10229 case ISD::BRCOND: {
10230 SDValue Cond = N->getOperand(1);
10231 SDValue Target = N->getOperand(2);
10233 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10234 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10235 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10237 // We now need to make the intrinsic dead (it cannot be instruction
10239 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10240 assert(Cond.getNode()->hasOneUse() &&
10241 "Counter decrement has more than one use");
10243 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10244 N->getOperand(0), Target);
10249 // If this is a branch on an altivec predicate comparison, lower this so
10250 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10251 // lowering is done pre-legalize, because the legalizer lowers the predicate
10252 // compare down to code that is difficult to reassemble.
10253 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10254 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10256 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10257 // value. If so, pass-through the AND to get to the intrinsic.
10258 if (LHS.getOpcode() == ISD::AND &&
10259 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10260 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10261 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10262 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10263 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
10265 LHS = LHS.getOperand(0);
10267 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10268 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10269 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10270 isa<ConstantSDNode>(RHS)) {
10271 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10272 "Counter decrement comparison is not EQ or NE");
10274 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10275 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10276 (CC == ISD::SETNE && !Val);
10278 // We now need to make the intrinsic dead (it cannot be instruction
10280 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10281 assert(LHS.getNode()->hasOneUse() &&
10282 "Counter decrement has more than one use");
10284 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10285 N->getOperand(0), N->getOperand(4));
10291 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10292 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10293 getAltivecCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10294 assert(isDot && "Can't compare against a vector result!");
10296 // If this is a comparison against something other than 0/1, then we know
10297 // that the condition is never/always true.
10298 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10299 if (Val != 0 && Val != 1) {
10300 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10301 return N->getOperand(0);
10302 // Always !=, turn it into an unconditional branch.
10303 return DAG.getNode(ISD::BR, dl, MVT::Other,
10304 N->getOperand(0), N->getOperand(4));
10307 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10309 // Create the PPCISD altivec 'dot' comparison node.
10311 LHS.getOperand(2), // LHS of compare
10312 LHS.getOperand(3), // RHS of compare
10313 DAG.getConstant(CompareOpc, MVT::i32)
10315 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10316 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10318 // Unpack the result based on how the target uses it.
10319 PPC::Predicate CompOpc;
10320 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10321 default: // Can't happen, don't crash on invalid number though.
10322 case 0: // Branch on the value of the EQ bit of CR6.
10323 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10325 case 1: // Branch on the inverted value of the EQ bit of CR6.
10326 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10328 case 2: // Branch on the value of the LT bit of CR6.
10329 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10331 case 3: // Branch on the inverted value of the LT bit of CR6.
10332 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10336 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10337 DAG.getConstant(CompOpc, MVT::i32),
10338 DAG.getRegister(PPC::CR6, MVT::i32),
10339 N->getOperand(4), CompNode.getValue(1));
10349 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10351 std::vector<SDNode *> *Created) const {
10352 // fold (sdiv X, pow2)
10353 EVT VT = N->getValueType(0);
10354 if (VT == MVT::i64 && !Subtarget.isPPC64())
10356 if ((VT != MVT::i32 && VT != MVT::i64) ||
10357 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10361 SDValue N0 = N->getOperand(0);
10363 bool IsNegPow2 = (-Divisor).isPowerOf2();
10364 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10365 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
10367 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10369 Created->push_back(Op.getNode());
10372 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
10374 Created->push_back(Op.getNode());
10380 //===----------------------------------------------------------------------===//
10381 // Inline Assembly Support
10382 //===----------------------------------------------------------------------===//
10384 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10387 const SelectionDAG &DAG,
10388 unsigned Depth) const {
10389 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10390 switch (Op.getOpcode()) {
10392 case PPCISD::LBRX: {
10393 // lhbrx is known to have the top bits cleared out.
10394 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10395 KnownZero = 0xFFFF0000;
10398 case ISD::INTRINSIC_WO_CHAIN: {
10399 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10401 case Intrinsic::ppc_altivec_vcmpbfp_p:
10402 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10403 case Intrinsic::ppc_altivec_vcmpequb_p:
10404 case Intrinsic::ppc_altivec_vcmpequh_p:
10405 case Intrinsic::ppc_altivec_vcmpequw_p:
10406 case Intrinsic::ppc_altivec_vcmpequd_p:
10407 case Intrinsic::ppc_altivec_vcmpgefp_p:
10408 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10409 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10410 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10411 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10412 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10413 case Intrinsic::ppc_altivec_vcmpgtub_p:
10414 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10415 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10416 case Intrinsic::ppc_altivec_vcmpgtud_p:
10417 KnownZero = ~1U; // All bits but the low one are known to be zero.
10424 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10425 switch (Subtarget.getDarwinDirective()) {
10428 case PPC::DIR_PWR4:
10429 case PPC::DIR_PWR5:
10430 case PPC::DIR_PWR5X:
10431 case PPC::DIR_PWR6:
10432 case PPC::DIR_PWR6X:
10433 case PPC::DIR_PWR7:
10434 case PPC::DIR_PWR8: {
10438 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10440 // For small loops (between 5 and 8 instructions), align to a 32-byte
10441 // boundary so that the entire loop fits in one instruction-cache line.
10442 uint64_t LoopSize = 0;
10443 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10444 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10445 LoopSize += TII->GetInstSizeInBytes(J);
10447 if (LoopSize > 16 && LoopSize <= 32)
10454 return TargetLowering::getPrefLoopAlignment(ML);
10457 /// getConstraintType - Given a constraint, return the type of
10458 /// constraint it is for this target.
10459 PPCTargetLowering::ConstraintType
10460 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
10461 if (Constraint.size() == 1) {
10462 switch (Constraint[0]) {
10469 return C_RegisterClass;
10471 // FIXME: While Z does indicate a memory constraint, it specifically
10472 // indicates an r+r address (used in conjunction with the 'y' modifier
10473 // in the replacement string). Currently, we're forcing the base
10474 // register to be r0 in the asm printer (which is interpreted as zero)
10475 // and forming the complete address in the second register. This is
10479 } else if (Constraint == "wc") { // individual CR bits.
10480 return C_RegisterClass;
10481 } else if (Constraint == "wa" || Constraint == "wd" ||
10482 Constraint == "wf" || Constraint == "ws") {
10483 return C_RegisterClass; // VSX registers.
10485 return TargetLowering::getConstraintType(Constraint);
10488 /// Examine constraint type and operand type and determine a weight value.
10489 /// This object must already have been set up with the operand type
10490 /// and the current alternative constraint selected.
10491 TargetLowering::ConstraintWeight
10492 PPCTargetLowering::getSingleConstraintMatchWeight(
10493 AsmOperandInfo &info, const char *constraint) const {
10494 ConstraintWeight weight = CW_Invalid;
10495 Value *CallOperandVal = info.CallOperandVal;
10496 // If we don't have a value, we can't do a match,
10497 // but allow it at the lowest weight.
10498 if (!CallOperandVal)
10500 Type *type = CallOperandVal->getType();
10502 // Look at the constraint type.
10503 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10504 return CW_Register; // an individual CR bit.
10505 else if ((StringRef(constraint) == "wa" ||
10506 StringRef(constraint) == "wd" ||
10507 StringRef(constraint) == "wf") &&
10508 type->isVectorTy())
10509 return CW_Register;
10510 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10511 return CW_Register;
10513 switch (*constraint) {
10515 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10518 if (type->isIntegerTy())
10519 weight = CW_Register;
10522 if (type->isFloatTy())
10523 weight = CW_Register;
10526 if (type->isDoubleTy())
10527 weight = CW_Register;
10530 if (type->isVectorTy())
10531 weight = CW_Register;
10534 weight = CW_Register;
10537 weight = CW_Memory;
10543 std::pair<unsigned, const TargetRegisterClass *>
10544 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10545 const std::string &Constraint,
10547 if (Constraint.size() == 1) {
10548 // GCC RS6000 Constraint Letters
10549 switch (Constraint[0]) {
10550 case 'b': // R1-R31
10551 if (VT == MVT::i64 && Subtarget.isPPC64())
10552 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10553 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10554 case 'r': // R0-R31
10555 if (VT == MVT::i64 && Subtarget.isPPC64())
10556 return std::make_pair(0U, &PPC::G8RCRegClass);
10557 return std::make_pair(0U, &PPC::GPRCRegClass);
10559 if (VT == MVT::f32 || VT == MVT::i32)
10560 return std::make_pair(0U, &PPC::F4RCRegClass);
10561 if (VT == MVT::f64 || VT == MVT::i64)
10562 return std::make_pair(0U, &PPC::F8RCRegClass);
10563 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10564 return std::make_pair(0U, &PPC::QFRCRegClass);
10565 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10566 return std::make_pair(0U, &PPC::QSRCRegClass);
10569 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10570 return std::make_pair(0U, &PPC::QFRCRegClass);
10571 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10572 return std::make_pair(0U, &PPC::QSRCRegClass);
10573 return std::make_pair(0U, &PPC::VRRCRegClass);
10575 return std::make_pair(0U, &PPC::CRRCRegClass);
10577 } else if (Constraint == "wc") { // an individual CR bit.
10578 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10579 } else if (Constraint == "wa" || Constraint == "wd" ||
10580 Constraint == "wf") {
10581 return std::make_pair(0U, &PPC::VSRCRegClass);
10582 } else if (Constraint == "ws") {
10583 return std::make_pair(0U, &PPC::VSFRCRegClass);
10586 std::pair<unsigned, const TargetRegisterClass *> R =
10587 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10589 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10590 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10591 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10593 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10594 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10595 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10596 PPC::GPRCRegClass.contains(R.first))
10597 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10598 PPC::sub_32, &PPC::G8RCRegClass),
10599 &PPC::G8RCRegClass);
10601 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10602 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10603 R.first = PPC::CR0;
10604 R.second = &PPC::CRRCRegClass;
10611 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10612 /// vector. If it is invalid, don't add anything to Ops.
10613 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10614 std::string &Constraint,
10615 std::vector<SDValue>&Ops,
10616 SelectionDAG &DAG) const {
10619 // Only support length 1 constraints.
10620 if (Constraint.length() > 1) return;
10622 char Letter = Constraint[0];
10633 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10634 if (!CST) return; // Must be an immediate to match.
10635 int64_t Value = CST->getSExtValue();
10636 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10637 // numbers are printed as such.
10639 default: llvm_unreachable("Unknown constraint letter!");
10640 case 'I': // "I" is a signed 16-bit constant.
10641 if (isInt<16>(Value))
10642 Result = DAG.getTargetConstant(Value, TCVT);
10644 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
10645 if (isShiftedUInt<16, 16>(Value))
10646 Result = DAG.getTargetConstant(Value, TCVT);
10648 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
10649 if (isShiftedInt<16, 16>(Value))
10650 Result = DAG.getTargetConstant(Value, TCVT);
10652 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
10653 if (isUInt<16>(Value))
10654 Result = DAG.getTargetConstant(Value, TCVT);
10656 case 'M': // "M" is a constant that is greater than 31.
10658 Result = DAG.getTargetConstant(Value, TCVT);
10660 case 'N': // "N" is a positive constant that is an exact power of two.
10661 if (Value > 0 && isPowerOf2_64(Value))
10662 Result = DAG.getTargetConstant(Value, TCVT);
10664 case 'O': // "O" is the constant zero.
10666 Result = DAG.getTargetConstant(Value, TCVT);
10668 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
10669 if (isInt<16>(-Value))
10670 Result = DAG.getTargetConstant(Value, TCVT);
10677 if (Result.getNode()) {
10678 Ops.push_back(Result);
10682 // Handle standard constraint letters.
10683 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10686 // isLegalAddressingMode - Return true if the addressing mode represented
10687 // by AM is legal for this target, for a load/store of the specified type.
10688 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10690 // PPC does not allow r+i addressing modes for vectors!
10691 if (Ty->isVectorTy() && AM.BaseOffs != 0)
10694 // PPC allows a sign-extended 16-bit immediate field.
10695 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
10698 // No global is ever allowed as a base.
10702 // PPC only support r+r,
10703 switch (AM.Scale) {
10704 case 0: // "r+i" or just "i", depending on HasBaseReg.
10707 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
10709 // Otherwise we have r+r or r+i.
10712 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
10714 // Allow 2*r as r+r.
10717 // No other scales are supported.
10724 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
10725 SelectionDAG &DAG) const {
10726 MachineFunction &MF = DAG.getMachineFunction();
10727 MachineFrameInfo *MFI = MF.getFrameInfo();
10728 MFI->setReturnAddressIsTaken(true);
10730 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
10734 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10736 // Make sure the function does not optimize away the store of the RA to
10738 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
10739 FuncInfo->setLRStoreRequired();
10740 bool isPPC64 = Subtarget.isPPC64();
10743 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10745 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(),
10746 isPPC64 ? MVT::i64 : MVT::i32);
10747 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10748 DAG.getNode(ISD::ADD, dl, getPointerTy(),
10749 FrameAddr, Offset),
10750 MachinePointerInfo(), false, false, false, 0);
10753 // Just load the return address off the stack.
10754 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
10755 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10756 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10759 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
10760 SelectionDAG &DAG) const {
10762 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10764 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
10765 bool isPPC64 = PtrVT == MVT::i64;
10767 MachineFunction &MF = DAG.getMachineFunction();
10768 MachineFrameInfo *MFI = MF.getFrameInfo();
10769 MFI->setFrameAddressIsTaken(true);
10771 // Naked functions never have a frame pointer, and so we use r1. For all
10772 // other functions, this decision must be delayed until during PEI.
10774 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
10775 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
10777 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
10779 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
10782 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
10783 FrameAddr, MachinePointerInfo(), false, false,
10788 // FIXME? Maybe this could be a TableGen attribute on some registers and
10789 // this table could be generated automatically from RegInfo.
10790 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
10792 bool isPPC64 = Subtarget.isPPC64();
10793 bool isDarwinABI = Subtarget.isDarwinABI();
10795 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
10796 (!isPPC64 && VT != MVT::i32))
10797 report_fatal_error("Invalid register global variable type");
10799 bool is64Bit = isPPC64 && VT == MVT::i64;
10800 unsigned Reg = StringSwitch<unsigned>(RegName)
10801 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
10802 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
10803 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
10804 (is64Bit ? PPC::X13 : PPC::R13))
10809 report_fatal_error("Invalid register name global variable");
10813 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10814 // The PowerPC target isn't yet aware of offsets.
10818 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
10820 unsigned Intrinsic) const {
10822 switch (Intrinsic) {
10823 case Intrinsic::ppc_qpx_qvlfd:
10824 case Intrinsic::ppc_qpx_qvlfs:
10825 case Intrinsic::ppc_qpx_qvlfcd:
10826 case Intrinsic::ppc_qpx_qvlfcs:
10827 case Intrinsic::ppc_qpx_qvlfiwa:
10828 case Intrinsic::ppc_qpx_qvlfiwz:
10829 case Intrinsic::ppc_altivec_lvx:
10830 case Intrinsic::ppc_altivec_lvxl:
10831 case Intrinsic::ppc_altivec_lvebx:
10832 case Intrinsic::ppc_altivec_lvehx:
10833 case Intrinsic::ppc_altivec_lvewx:
10834 case Intrinsic::ppc_vsx_lxvd2x:
10835 case Intrinsic::ppc_vsx_lxvw4x: {
10837 switch (Intrinsic) {
10838 case Intrinsic::ppc_altivec_lvebx:
10841 case Intrinsic::ppc_altivec_lvehx:
10844 case Intrinsic::ppc_altivec_lvewx:
10847 case Intrinsic::ppc_vsx_lxvd2x:
10850 case Intrinsic::ppc_qpx_qvlfd:
10853 case Intrinsic::ppc_qpx_qvlfs:
10856 case Intrinsic::ppc_qpx_qvlfcd:
10859 case Intrinsic::ppc_qpx_qvlfcs:
10867 Info.opc = ISD::INTRINSIC_W_CHAIN;
10869 Info.ptrVal = I.getArgOperand(0);
10870 Info.offset = -VT.getStoreSize()+1;
10871 Info.size = 2*VT.getStoreSize()-1;
10874 Info.readMem = true;
10875 Info.writeMem = false;
10878 case Intrinsic::ppc_qpx_qvlfda:
10879 case Intrinsic::ppc_qpx_qvlfsa:
10880 case Intrinsic::ppc_qpx_qvlfcda:
10881 case Intrinsic::ppc_qpx_qvlfcsa:
10882 case Intrinsic::ppc_qpx_qvlfiwaa:
10883 case Intrinsic::ppc_qpx_qvlfiwza: {
10885 switch (Intrinsic) {
10886 case Intrinsic::ppc_qpx_qvlfda:
10889 case Intrinsic::ppc_qpx_qvlfsa:
10892 case Intrinsic::ppc_qpx_qvlfcda:
10895 case Intrinsic::ppc_qpx_qvlfcsa:
10903 Info.opc = ISD::INTRINSIC_W_CHAIN;
10905 Info.ptrVal = I.getArgOperand(0);
10907 Info.size = VT.getStoreSize();
10910 Info.readMem = true;
10911 Info.writeMem = false;
10914 case Intrinsic::ppc_qpx_qvstfd:
10915 case Intrinsic::ppc_qpx_qvstfs:
10916 case Intrinsic::ppc_qpx_qvstfcd:
10917 case Intrinsic::ppc_qpx_qvstfcs:
10918 case Intrinsic::ppc_qpx_qvstfiw:
10919 case Intrinsic::ppc_altivec_stvx:
10920 case Intrinsic::ppc_altivec_stvxl:
10921 case Intrinsic::ppc_altivec_stvebx:
10922 case Intrinsic::ppc_altivec_stvehx:
10923 case Intrinsic::ppc_altivec_stvewx:
10924 case Intrinsic::ppc_vsx_stxvd2x:
10925 case Intrinsic::ppc_vsx_stxvw4x: {
10927 switch (Intrinsic) {
10928 case Intrinsic::ppc_altivec_stvebx:
10931 case Intrinsic::ppc_altivec_stvehx:
10934 case Intrinsic::ppc_altivec_stvewx:
10937 case Intrinsic::ppc_vsx_stxvd2x:
10940 case Intrinsic::ppc_qpx_qvstfd:
10943 case Intrinsic::ppc_qpx_qvstfs:
10946 case Intrinsic::ppc_qpx_qvstfcd:
10949 case Intrinsic::ppc_qpx_qvstfcs:
10957 Info.opc = ISD::INTRINSIC_VOID;
10959 Info.ptrVal = I.getArgOperand(1);
10960 Info.offset = -VT.getStoreSize()+1;
10961 Info.size = 2*VT.getStoreSize()-1;
10964 Info.readMem = false;
10965 Info.writeMem = true;
10968 case Intrinsic::ppc_qpx_qvstfda:
10969 case Intrinsic::ppc_qpx_qvstfsa:
10970 case Intrinsic::ppc_qpx_qvstfcda:
10971 case Intrinsic::ppc_qpx_qvstfcsa:
10972 case Intrinsic::ppc_qpx_qvstfiwa: {
10974 switch (Intrinsic) {
10975 case Intrinsic::ppc_qpx_qvstfda:
10978 case Intrinsic::ppc_qpx_qvstfsa:
10981 case Intrinsic::ppc_qpx_qvstfcda:
10984 case Intrinsic::ppc_qpx_qvstfcsa:
10992 Info.opc = ISD::INTRINSIC_VOID;
10994 Info.ptrVal = I.getArgOperand(1);
10996 Info.size = VT.getStoreSize();
10999 Info.readMem = false;
11000 Info.writeMem = true;
11010 /// getOptimalMemOpType - Returns the target specific optimal type for load
11011 /// and store operations as a result of memset, memcpy, and memmove
11012 /// lowering. If DstAlign is zero that means it's safe to destination
11013 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11014 /// means there isn't a need to check it against alignment requirement,
11015 /// probably because the source does not need to be loaded. If 'IsMemset' is
11016 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11017 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11018 /// source is constant so it does not need to be loaded.
11019 /// It returns EVT::Other if the type should be determined using generic
11020 /// target-independent logic.
11021 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11022 unsigned DstAlign, unsigned SrcAlign,
11023 bool IsMemset, bool ZeroMemset,
11025 MachineFunction &MF) const {
11026 const Function *F = MF.getFunction();
11027 // When expanding a memset, require at least two QPX instructions to cover
11028 // the cost of loading the value to be stored from the constant pool.
11029 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11030 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11031 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11035 // We should use Altivec/VSX loads and stores when available. For unaligned
11036 // addresses, unaligned VSX loads are only fast starting with the P8.
11037 if (Subtarget.hasAltivec() && Size >= 16 &&
11038 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11039 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11042 if (Subtarget.isPPC64()) {
11049 /// \brief Returns true if it is beneficial to convert a load of a constant
11050 /// to just the constant itself.
11051 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11053 assert(Ty->isIntegerTy());
11055 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11056 if (BitSize == 0 || BitSize > 64)
11061 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11062 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11064 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11065 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11066 return NumBits1 == 64 && NumBits2 == 32;
11069 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11070 if (!VT1.isInteger() || !VT2.isInteger())
11072 unsigned NumBits1 = VT1.getSizeInBits();
11073 unsigned NumBits2 = VT2.getSizeInBits();
11074 return NumBits1 == 64 && NumBits2 == 32;
11077 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11078 // Generally speaking, zexts are not free, but they are free when they can be
11079 // folded with other operations.
11080 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11081 EVT MemVT = LD->getMemoryVT();
11082 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11083 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11084 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11085 LD->getExtensionType() == ISD::ZEXTLOAD))
11089 // FIXME: Add other cases...
11090 // - 32-bit shifts with a zext to i64
11091 // - zext after ctlz, bswap, etc.
11092 // - zext after and by a constant mask
11094 return TargetLowering::isZExtFree(Val, VT2);
11097 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11098 assert(VT.isFloatingPoint());
11102 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11103 return isInt<16>(Imm) || isUInt<16>(Imm);
11106 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11107 return isInt<16>(Imm) || isUInt<16>(Imm);
11110 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11113 bool *Fast) const {
11114 if (DisablePPCUnaligned)
11117 // PowerPC supports unaligned memory access for simple non-vector types.
11118 // Although accessing unaligned addresses is not as efficient as accessing
11119 // aligned addresses, it is generally more efficient than manual expansion,
11120 // and generally only traps for software emulation when crossing page
11123 if (!VT.isSimple())
11126 if (VT.getSimpleVT().isVector()) {
11127 if (Subtarget.hasVSX()) {
11128 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11129 VT != MVT::v4f32 && VT != MVT::v4i32)
11136 if (VT == MVT::ppcf128)
11145 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11146 VT = VT.getScalarType();
11148 if (!VT.isSimple())
11151 switch (VT.getSimpleVT().SimpleTy) {
11163 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11164 // LR is a callee-save register, but we must treat it as clobbered by any call
11165 // site. Hence we include LR in the scratch registers, which are in turn added
11166 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11167 // to CTR, which is used by any indirect call.
11168 static const MCPhysReg ScratchRegs[] = {
11169 PPC::X12, PPC::LR8, PPC::CTR8, 0
11172 return ScratchRegs;
11176 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11177 EVT VT , unsigned DefinedValues) const {
11178 if (VT == MVT::v2i64)
11181 if (Subtarget.hasQPX()) {
11182 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11186 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11189 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11190 if (DisableILPPref || Subtarget.enableMachineScheduler())
11191 return TargetLowering::getSchedulingPreference(N);
11196 // Create a fast isel object.
11198 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11199 const TargetLibraryInfo *LibInfo) const {
11200 return PPC::createFastISel(FuncInfo, LibInfo);