1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/DerivedTypes.h"
41 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
42 CCValAssign::LocInfo &LocInfo,
43 ISD::ArgFlagsTy &ArgFlags,
45 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
56 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
57 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
63 return new TargetLoweringObjectFileELF();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
78 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
79 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
81 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
85 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
87 // PowerPC has pre-inc load and store's.
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 // This is used in the ppcf128->int sequence. Note it has different semantics
100 // from FP_ROUND: that rounds to nearest, this rounds to zero.
101 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
103 // PowerPC has no SREM/UREM instructions
104 setOperationAction(ISD::SREM, MVT::i32, Expand);
105 setOperationAction(ISD::UREM, MVT::i32, Expand);
106 setOperationAction(ISD::SREM, MVT::i64, Expand);
107 setOperationAction(ISD::UREM, MVT::i64, Expand);
109 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
110 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
112 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
113 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
114 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
115 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
116 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
119 // We don't support sin/cos/sqrt/fmod/pow
120 setOperationAction(ISD::FSIN , MVT::f64, Expand);
121 setOperationAction(ISD::FCOS , MVT::f64, Expand);
122 setOperationAction(ISD::FREM , MVT::f64, Expand);
123 setOperationAction(ISD::FPOW , MVT::f64, Expand);
124 setOperationAction(ISD::FSIN , MVT::f32, Expand);
125 setOperationAction(ISD::FCOS , MVT::f32, Expand);
126 setOperationAction(ISD::FREM , MVT::f32, Expand);
127 setOperationAction(ISD::FPOW , MVT::f32, Expand);
129 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
131 // If we're enabling GP optimizations, use hardware square root
132 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
133 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
134 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
137 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
138 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
140 // PowerPC does not have BSWAP, CTPOP or CTTZ
141 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
142 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
143 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
144 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
145 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
146 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
148 // PowerPC does not have ROTR
149 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
150 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
152 // PowerPC does not have Select
153 setOperationAction(ISD::SELECT, MVT::i32, Expand);
154 setOperationAction(ISD::SELECT, MVT::i64, Expand);
155 setOperationAction(ISD::SELECT, MVT::f32, Expand);
156 setOperationAction(ISD::SELECT, MVT::f64, Expand);
158 // PowerPC wants to turn select_cc of FP into fsel when possible.
159 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
160 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
162 // PowerPC wants to optimize integer setcc a bit
163 setOperationAction(ISD::SETCC, MVT::i32, Custom);
165 // PowerPC does not have BRCOND which requires SetCC
166 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
168 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
170 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
171 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
173 // PowerPC does not have [U|S]INT_TO_FP
174 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
175 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
177 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
178 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
179 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
180 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
182 // We cannot sextinreg(i1). Expand to shifts.
183 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
185 // Support label based line numbers.
186 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
187 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
189 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
190 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
192 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
195 // We want to legalize GlobalAddress and ConstantPool nodes into the
196 // appropriate instructions to materialize the address.
197 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
199 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
200 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
201 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
202 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
203 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
204 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
206 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
209 setOperationAction(ISD::TRAP, MVT::Other, Legal);
211 // TRAMPOLINE is custom lowered.
212 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
214 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
215 setOperationAction(ISD::VASTART , MVT::Other, Custom);
217 // VAARG is custom lowered with the 32-bit SVR4 ABI.
218 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
219 && !TM.getSubtarget<PPCSubtarget>().isPPC64())
220 setOperationAction(ISD::VAARG, MVT::Other, Custom);
222 setOperationAction(ISD::VAARG, MVT::Other, Expand);
224 // Use the default implementation.
225 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
226 setOperationAction(ISD::VAEND , MVT::Other, Expand);
227 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
228 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
229 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
230 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
232 // We want to custom lower some of our intrinsics.
233 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
235 // Comparisons that require checking two conditions.
236 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
243 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
244 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
247 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
249 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
250 // They also have instructions for converting between i64 and fp.
251 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
252 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
253 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
254 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
255 // This is just the low 32 bits of a (signed) fp->i64 conversion.
256 // We cannot do this with Promote because i64 is not a legal type.
257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
259 // FIXME: disable this lowered code. This generates 64-bit register values,
260 // and we don't model the fact that the top part is clobbered by calls. We
261 // need to flag these together so that the value isn't live across a call.
262 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
264 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
265 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
268 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
269 // 64-bit PowerPC implementations can support i64 types directly
270 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
271 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
272 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
273 // 64-bit PowerPC wants to expand i128 shifts itself.
274 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
275 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
276 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
278 // 32-bit PowerPC wants to expand i64 shifts itself.
279 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
280 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
281 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
284 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
285 // First set operation action for all vector types to expand. Then we
286 // will selectively turn on ones that can be effectively codegen'd.
287 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
288 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
289 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
291 // add/sub are legal for all supported vector VT's.
292 setOperationAction(ISD::ADD , VT, Legal);
293 setOperationAction(ISD::SUB , VT, Legal);
295 // We promote all shuffles to v16i8.
296 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
297 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
299 // We promote all non-typed operations to v4i32.
300 setOperationAction(ISD::AND , VT, Promote);
301 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
302 setOperationAction(ISD::OR , VT, Promote);
303 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
304 setOperationAction(ISD::XOR , VT, Promote);
305 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
306 setOperationAction(ISD::LOAD , VT, Promote);
307 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
308 setOperationAction(ISD::SELECT, VT, Promote);
309 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
310 setOperationAction(ISD::STORE, VT, Promote);
311 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
313 // No other operations are legal.
314 setOperationAction(ISD::MUL , VT, Expand);
315 setOperationAction(ISD::SDIV, VT, Expand);
316 setOperationAction(ISD::SREM, VT, Expand);
317 setOperationAction(ISD::UDIV, VT, Expand);
318 setOperationAction(ISD::UREM, VT, Expand);
319 setOperationAction(ISD::FDIV, VT, Expand);
320 setOperationAction(ISD::FNEG, VT, Expand);
321 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
323 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
324 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
326 setOperationAction(ISD::UDIVREM, VT, Expand);
327 setOperationAction(ISD::SDIVREM, VT, Expand);
328 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
329 setOperationAction(ISD::FPOW, VT, Expand);
330 setOperationAction(ISD::CTPOP, VT, Expand);
331 setOperationAction(ISD::CTLZ, VT, Expand);
332 setOperationAction(ISD::CTTZ, VT, Expand);
335 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
336 // with merges, splats, etc.
337 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
339 setOperationAction(ISD::AND , MVT::v4i32, Legal);
340 setOperationAction(ISD::OR , MVT::v4i32, Legal);
341 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
342 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
343 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
344 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
346 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
347 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
348 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
349 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
351 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
352 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
353 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
354 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
356 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
357 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
359 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
360 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
361 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
362 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
365 setShiftAmountType(MVT::i32);
366 setBooleanContents(ZeroOrOneBooleanContent);
368 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
369 setStackPointerRegisterToSaveRestore(PPC::X1);
370 setExceptionPointerRegister(PPC::X3);
371 setExceptionSelectorRegister(PPC::X4);
373 setStackPointerRegisterToSaveRestore(PPC::R1);
374 setExceptionPointerRegister(PPC::R3);
375 setExceptionSelectorRegister(PPC::R4);
378 // We have target-specific dag combine patterns for the following nodes:
379 setTargetDAGCombine(ISD::SINT_TO_FP);
380 setTargetDAGCombine(ISD::STORE);
381 setTargetDAGCombine(ISD::BR_CC);
382 setTargetDAGCombine(ISD::BSWAP);
384 // Darwin long double math library functions have $LDBL128 appended.
385 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
386 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
387 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
388 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
389 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
390 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
391 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
392 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
393 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
394 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
395 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
398 computeRegisterProperties();
401 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
402 /// function arguments in the caller parameter area.
403 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
404 TargetMachine &TM = getTargetMachine();
405 // Darwin passes everything on 4 byte boundary.
406 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
412 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
415 case PPCISD::FSEL: return "PPCISD::FSEL";
416 case PPCISD::FCFID: return "PPCISD::FCFID";
417 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
418 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
419 case PPCISD::STFIWX: return "PPCISD::STFIWX";
420 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
421 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
422 case PPCISD::VPERM: return "PPCISD::VPERM";
423 case PPCISD::Hi: return "PPCISD::Hi";
424 case PPCISD::Lo: return "PPCISD::Lo";
425 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
426 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
427 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
428 case PPCISD::SRL: return "PPCISD::SRL";
429 case PPCISD::SRA: return "PPCISD::SRA";
430 case PPCISD::SHL: return "PPCISD::SHL";
431 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
432 case PPCISD::STD_32: return "PPCISD::STD_32";
433 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
434 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
435 case PPCISD::NOP: return "PPCISD::NOP";
436 case PPCISD::MTCTR: return "PPCISD::MTCTR";
437 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
438 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
439 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
440 case PPCISD::MFCR: return "PPCISD::MFCR";
441 case PPCISD::VCMP: return "PPCISD::VCMP";
442 case PPCISD::VCMPo: return "PPCISD::VCMPo";
443 case PPCISD::LBRX: return "PPCISD::LBRX";
444 case PPCISD::STBRX: return "PPCISD::STBRX";
445 case PPCISD::LARX: return "PPCISD::LARX";
446 case PPCISD::STCX: return "PPCISD::STCX";
447 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
448 case PPCISD::MFFS: return "PPCISD::MFFS";
449 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
450 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
451 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
452 case PPCISD::MTFSF: return "PPCISD::MTFSF";
453 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
457 MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
461 /// getFunctionAlignment - Return the Log2 alignment of this function.
462 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
463 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
464 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
469 //===----------------------------------------------------------------------===//
470 // Node matching predicates, for use by the tblgen matching code.
471 //===----------------------------------------------------------------------===//
473 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
474 static bool isFloatingPointZero(SDValue Op) {
475 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
476 return CFP->getValueAPF().isZero();
477 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
478 // Maybe this has already been legalized into the constant pool?
479 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
480 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
481 return CFP->getValueAPF().isZero();
486 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
487 /// true if Op is undef or if it matches the specified value.
488 static bool isConstantOrUndef(int Op, int Val) {
489 return Op < 0 || Op == Val;
492 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
493 /// VPKUHUM instruction.
494 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
496 for (unsigned i = 0; i != 16; ++i)
497 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
500 for (unsigned i = 0; i != 8; ++i)
501 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
502 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
508 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
509 /// VPKUWUM instruction.
510 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
512 for (unsigned i = 0; i != 16; i += 2)
513 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
514 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
517 for (unsigned i = 0; i != 8; i += 2)
518 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
519 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
520 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
521 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
527 /// isVMerge - Common function, used to match vmrg* shuffles.
529 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
530 unsigned LHSStart, unsigned RHSStart) {
531 assert(N->getValueType(0) == MVT::v16i8 &&
532 "PPC only supports shuffles by bytes!");
533 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
534 "Unsupported merge size!");
536 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
537 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
538 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
539 LHSStart+j+i*UnitSize) ||
540 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
541 RHSStart+j+i*UnitSize))
547 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
548 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
549 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
552 return isVMerge(N, UnitSize, 8, 24);
553 return isVMerge(N, UnitSize, 8, 8);
556 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
557 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
558 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
561 return isVMerge(N, UnitSize, 0, 16);
562 return isVMerge(N, UnitSize, 0, 0);
566 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
567 /// amount, otherwise return -1.
568 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
569 assert(N->getValueType(0) == MVT::v16i8 &&
570 "PPC only supports shuffles by bytes!");
572 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
574 // Find the first non-undef value in the shuffle mask.
576 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
579 if (i == 16) return -1; // all undef.
581 // Otherwise, check to see if the rest of the elements are consecutively
582 // numbered from this value.
583 unsigned ShiftAmt = SVOp->getMaskElt(i);
584 if (ShiftAmt < i) return -1;
588 // Check the rest of the elements to see if they are consecutive.
589 for (++i; i != 16; ++i)
590 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
593 // Check the rest of the elements to see if they are consecutive.
594 for (++i; i != 16; ++i)
595 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
601 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
602 /// specifies a splat of a single element that is suitable for input to
603 /// VSPLTB/VSPLTH/VSPLTW.
604 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
605 assert(N->getValueType(0) == MVT::v16i8 &&
606 (EltSize == 1 || EltSize == 2 || EltSize == 4));
608 // This is a splat operation if each element of the permute is the same, and
609 // if the value doesn't reference the second vector.
610 unsigned ElementBase = N->getMaskElt(0);
612 // FIXME: Handle UNDEF elements too!
613 if (ElementBase >= 16)
616 // Check that the indices are consecutive, in the case of a multi-byte element
617 // splatted with a v16i8 mask.
618 for (unsigned i = 1; i != EltSize; ++i)
619 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
622 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
623 if (N->getMaskElt(i) < 0) continue;
624 for (unsigned j = 0; j != EltSize; ++j)
625 if (N->getMaskElt(i+j) != N->getMaskElt(j))
631 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
633 bool PPC::isAllNegativeZeroVector(SDNode *N) {
634 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
636 APInt APVal, APUndef;
640 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32))
641 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
642 return CFP->getValueAPF().isNegZero();
647 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
648 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
649 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
650 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
651 assert(isSplatShuffleMask(SVOp, EltSize));
652 return SVOp->getMaskElt(0) / EltSize;
655 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
656 /// by using a vspltis[bhw] instruction of the specified element size, return
657 /// the constant being splatted. The ByteSize field indicates the number of
658 /// bytes of each element [124] -> [bhw].
659 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
662 // If ByteSize of the splat is bigger than the element size of the
663 // build_vector, then we have a case where we are checking for a splat where
664 // multiple elements of the buildvector are folded together into a single
665 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
666 unsigned EltSize = 16/N->getNumOperands();
667 if (EltSize < ByteSize) {
668 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
669 SDValue UniquedVals[4];
670 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
672 // See if all of the elements in the buildvector agree across.
673 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
674 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
675 // If the element isn't a constant, bail fully out.
676 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
679 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
680 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
681 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
682 return SDValue(); // no match.
685 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
686 // either constant or undef values that are identical for each chunk. See
687 // if these chunks can form into a larger vspltis*.
689 // Check to see if all of the leading entries are either 0 or -1. If
690 // neither, then this won't fit into the immediate field.
691 bool LeadingZero = true;
692 bool LeadingOnes = true;
693 for (unsigned i = 0; i != Multiple-1; ++i) {
694 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
696 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
697 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
699 // Finally, check the least significant entry.
701 if (UniquedVals[Multiple-1].getNode() == 0)
702 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
703 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
705 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
708 if (UniquedVals[Multiple-1].getNode() == 0)
709 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
710 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
711 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
712 return DAG.getTargetConstant(Val, MVT::i32);
718 // Check to see if this buildvec has a single non-undef value in its elements.
719 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
720 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
721 if (OpVal.getNode() == 0)
722 OpVal = N->getOperand(i);
723 else if (OpVal != N->getOperand(i))
727 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
729 unsigned ValSizeInBytes = EltSize;
731 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
732 Value = CN->getZExtValue();
733 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
734 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
735 Value = FloatToBits(CN->getValueAPF().convertToFloat());
738 // If the splat value is larger than the element value, then we can never do
739 // this splat. The only case that we could fit the replicated bits into our
740 // immediate field for would be zero, and we prefer to use vxor for it.
741 if (ValSizeInBytes < ByteSize) return SDValue();
743 // If the element value is larger than the splat value, cut it in half and
744 // check to see if the two halves are equal. Continue doing this until we
745 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
746 while (ValSizeInBytes > ByteSize) {
747 ValSizeInBytes >>= 1;
749 // If the top half equals the bottom half, we're still ok.
750 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
751 (Value & ((1 << (8*ValSizeInBytes))-1)))
755 // Properly sign extend the value.
756 int ShAmt = (4-ByteSize)*8;
757 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
759 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
760 if (MaskVal == 0) return SDValue();
762 // Finally, if this value fits in a 5 bit sext field, return it
763 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
764 return DAG.getTargetConstant(MaskVal, MVT::i32);
768 //===----------------------------------------------------------------------===//
769 // Addressing Mode Selection
770 //===----------------------------------------------------------------------===//
772 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
773 /// or 64-bit immediate, and if the value can be accurately represented as a
774 /// sign extension from a 16-bit value. If so, this returns true and the
776 static bool isIntS16Immediate(SDNode *N, short &Imm) {
777 if (N->getOpcode() != ISD::Constant)
780 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
781 if (N->getValueType(0) == MVT::i32)
782 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
784 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
786 static bool isIntS16Immediate(SDValue Op, short &Imm) {
787 return isIntS16Immediate(Op.getNode(), Imm);
791 /// SelectAddressRegReg - Given the specified addressed, check to see if it
792 /// can be represented as an indexed [r+r] operation. Returns false if it
793 /// can be more efficiently represented with [r+imm].
794 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
796 SelectionDAG &DAG) const {
798 if (N.getOpcode() == ISD::ADD) {
799 if (isIntS16Immediate(N.getOperand(1), imm))
801 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
804 Base = N.getOperand(0);
805 Index = N.getOperand(1);
807 } else if (N.getOpcode() == ISD::OR) {
808 if (isIntS16Immediate(N.getOperand(1), imm))
809 return false; // r+i can fold it if we can.
811 // If this is an or of disjoint bitfields, we can codegen this as an add
812 // (for better address arithmetic) if the LHS and RHS of the OR are provably
814 APInt LHSKnownZero, LHSKnownOne;
815 APInt RHSKnownZero, RHSKnownOne;
816 DAG.ComputeMaskedBits(N.getOperand(0),
817 APInt::getAllOnesValue(N.getOperand(0)
818 .getValueSizeInBits()),
819 LHSKnownZero, LHSKnownOne);
821 if (LHSKnownZero.getBoolValue()) {
822 DAG.ComputeMaskedBits(N.getOperand(1),
823 APInt::getAllOnesValue(N.getOperand(1)
824 .getValueSizeInBits()),
825 RHSKnownZero, RHSKnownOne);
826 // If all of the bits are known zero on the LHS or RHS, the add won't
828 if (~(LHSKnownZero | RHSKnownZero) == 0) {
829 Base = N.getOperand(0);
830 Index = N.getOperand(1);
839 /// Returns true if the address N can be represented by a base register plus
840 /// a signed 16-bit displacement [r+imm], and if it is not better
841 /// represented as reg+reg.
842 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
844 SelectionDAG &DAG) const {
845 // FIXME dl should come from parent load or store, not from address
846 DebugLoc dl = N.getDebugLoc();
847 // If this can be more profitably realized as r+r, fail.
848 if (SelectAddressRegReg(N, Disp, Base, DAG))
851 if (N.getOpcode() == ISD::ADD) {
853 if (isIntS16Immediate(N.getOperand(1), imm)) {
854 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
855 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
856 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
858 Base = N.getOperand(0);
860 return true; // [r+i]
861 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
862 // Match LOAD (ADD (X, Lo(G))).
863 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
864 && "Cannot handle constant offsets yet!");
865 Disp = N.getOperand(1).getOperand(0); // The global address.
866 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
867 Disp.getOpcode() == ISD::TargetConstantPool ||
868 Disp.getOpcode() == ISD::TargetJumpTable);
869 Base = N.getOperand(0);
870 return true; // [&g+r]
872 } else if (N.getOpcode() == ISD::OR) {
874 if (isIntS16Immediate(N.getOperand(1), imm)) {
875 // If this is an or of disjoint bitfields, we can codegen this as an add
876 // (for better address arithmetic) if the LHS and RHS of the OR are
877 // provably disjoint.
878 APInt LHSKnownZero, LHSKnownOne;
879 DAG.ComputeMaskedBits(N.getOperand(0),
880 APInt::getAllOnesValue(N.getOperand(0)
881 .getValueSizeInBits()),
882 LHSKnownZero, LHSKnownOne);
884 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
885 // If all of the bits are known zero on the LHS or RHS, the add won't
887 Base = N.getOperand(0);
888 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
892 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
893 // Loading from a constant address.
895 // If this address fits entirely in a 16-bit sext immediate field, codegen
898 if (isIntS16Immediate(CN, Imm)) {
899 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
900 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
904 // Handle 32-bit sext immediates with LIS + addr mode.
905 if (CN->getValueType(0) == MVT::i32 ||
906 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
907 int Addr = (int)CN->getZExtValue();
909 // Otherwise, break this down into an LIS + disp.
910 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
912 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
913 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
914 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
919 Disp = DAG.getTargetConstant(0, getPointerTy());
920 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
921 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
924 return true; // [r+0]
927 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
928 /// represented as an indexed [r+r] operation.
929 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
931 SelectionDAG &DAG) const {
932 // Check to see if we can easily represent this as an [r+r] address. This
933 // will fail if it thinks that the address is more profitably represented as
934 // reg+imm, e.g. where imm = 0.
935 if (SelectAddressRegReg(N, Base, Index, DAG))
938 // If the operand is an addition, always emit this as [r+r], since this is
939 // better (for code size, and execution, as the memop does the add for free)
940 // than emitting an explicit add.
941 if (N.getOpcode() == ISD::ADD) {
942 Base = N.getOperand(0);
943 Index = N.getOperand(1);
947 // Otherwise, do it the hard way, using R0 as the base register.
948 Base = DAG.getRegister(PPC::R0, N.getValueType());
953 /// SelectAddressRegImmShift - Returns true if the address N can be
954 /// represented by a base register plus a signed 14-bit displacement
955 /// [r+imm*4]. Suitable for use by STD and friends.
956 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
958 SelectionDAG &DAG) const {
959 // FIXME dl should come from the parent load or store, not the address
960 DebugLoc dl = N.getDebugLoc();
961 // If this can be more profitably realized as r+r, fail.
962 if (SelectAddressRegReg(N, Disp, Base, DAG))
965 if (N.getOpcode() == ISD::ADD) {
967 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
968 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
969 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
970 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
972 Base = N.getOperand(0);
974 return true; // [r+i]
975 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
976 // Match LOAD (ADD (X, Lo(G))).
977 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
978 && "Cannot handle constant offsets yet!");
979 Disp = N.getOperand(1).getOperand(0); // The global address.
980 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
981 Disp.getOpcode() == ISD::TargetConstantPool ||
982 Disp.getOpcode() == ISD::TargetJumpTable);
983 Base = N.getOperand(0);
984 return true; // [&g+r]
986 } else if (N.getOpcode() == ISD::OR) {
988 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
989 // If this is an or of disjoint bitfields, we can codegen this as an add
990 // (for better address arithmetic) if the LHS and RHS of the OR are
991 // provably disjoint.
992 APInt LHSKnownZero, LHSKnownOne;
993 DAG.ComputeMaskedBits(N.getOperand(0),
994 APInt::getAllOnesValue(N.getOperand(0)
995 .getValueSizeInBits()),
996 LHSKnownZero, LHSKnownOne);
997 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
998 // If all of the bits are known zero on the LHS or RHS, the add won't
1000 Base = N.getOperand(0);
1001 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1005 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1006 // Loading from a constant address. Verify low two bits are clear.
1007 if ((CN->getZExtValue() & 3) == 0) {
1008 // If this address fits entirely in a 14-bit sext immediate field, codegen
1011 if (isIntS16Immediate(CN, Imm)) {
1012 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1013 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1017 // Fold the low-part of 32-bit absolute addresses into addr mode.
1018 if (CN->getValueType(0) == MVT::i32 ||
1019 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1020 int Addr = (int)CN->getZExtValue();
1022 // Otherwise, break this down into an LIS + disp.
1023 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1024 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1025 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1026 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1032 Disp = DAG.getTargetConstant(0, getPointerTy());
1033 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1034 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1037 return true; // [r+0]
1041 /// getPreIndexedAddressParts - returns true by value, base pointer and
1042 /// offset pointer and addressing mode by reference if the node's address
1043 /// can be legally represented as pre-indexed load / store address.
1044 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1046 ISD::MemIndexedMode &AM,
1047 SelectionDAG &DAG) const {
1048 // Disabled by default for now.
1049 if (!EnablePPCPreinc) return false;
1053 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1054 Ptr = LD->getBasePtr();
1055 VT = LD->getMemoryVT();
1057 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1059 Ptr = ST->getBasePtr();
1060 VT = ST->getMemoryVT();
1064 // PowerPC doesn't have preinc load/store instructions for vectors.
1068 // TODO: Check reg+reg first.
1070 // LDU/STU use reg+imm*4, others use reg+imm.
1071 if (VT != MVT::i64) {
1073 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1077 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1081 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1082 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1083 // sext i32 to i64 when addr mode is r+i.
1084 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1085 LD->getExtensionType() == ISD::SEXTLOAD &&
1086 isa<ConstantSDNode>(Offset))
1094 //===----------------------------------------------------------------------===//
1095 // LowerOperation implementation
1096 //===----------------------------------------------------------------------===//
1098 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1099 SelectionDAG &DAG) {
1100 EVT PtrVT = Op.getValueType();
1101 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1102 Constant *C = CP->getConstVal();
1103 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1104 SDValue Zero = DAG.getConstant(0, PtrVT);
1105 // FIXME there isn't really any debug info here
1106 DebugLoc dl = Op.getDebugLoc();
1108 const TargetMachine &TM = DAG.getTarget();
1110 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
1111 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
1113 // If this is a non-darwin platform, we don't support non-static relo models
1115 if (TM.getRelocationModel() == Reloc::Static ||
1116 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1117 // Generate non-pic code that has direct accesses to the constant pool.
1118 // The address of the global is just (hi(&g)+lo(&g)).
1119 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1122 if (TM.getRelocationModel() == Reloc::PIC_) {
1123 // With PIC, the first instruction is actually "GR+hi(&G)".
1124 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1125 DAG.getNode(PPCISD::GlobalBaseReg,
1126 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1129 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1133 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1134 EVT PtrVT = Op.getValueType();
1135 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1136 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1137 SDValue Zero = DAG.getConstant(0, PtrVT);
1138 // FIXME there isn't really any debug loc here
1139 DebugLoc dl = Op.getDebugLoc();
1141 const TargetMachine &TM = DAG.getTarget();
1143 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
1144 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
1146 // If this is a non-darwin platform, we don't support non-static relo models
1148 if (TM.getRelocationModel() == Reloc::Static ||
1149 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1150 // Generate non-pic code that has direct accesses to the constant pool.
1151 // The address of the global is just (hi(&g)+lo(&g)).
1152 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1155 if (TM.getRelocationModel() == Reloc::PIC_) {
1156 // With PIC, the first instruction is actually "GR+hi(&G)".
1157 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1158 DAG.getNode(PPCISD::GlobalBaseReg,
1159 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1162 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1166 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1167 SelectionDAG &DAG) {
1168 llvm_unreachable("TLS not implemented for PPC.");
1169 return SDValue(); // Not reached
1172 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
1173 EVT PtrVT = Op.getValueType();
1174 DebugLoc DL = Op.getDebugLoc();
1176 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1177 SDValue TgtBA = DAG.getBlockAddress(BA, DL, /*isTarget=*/true);
1178 SDValue Zero = DAG.getConstant(0, PtrVT);
1179 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero);
1180 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero);
1182 // If this is a non-darwin platform, we don't support non-static relo models
1184 const TargetMachine &TM = DAG.getTarget();
1185 if (TM.getRelocationModel() == Reloc::Static ||
1186 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1187 // Generate non-pic code that has direct accesses to globals.
1188 // The address of the global is just (hi(&g)+lo(&g)).
1189 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1192 if (TM.getRelocationModel() == Reloc::PIC_) {
1193 // With PIC, the first instruction is actually "GR+hi(&G)".
1194 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1195 DAG.getNode(PPCISD::GlobalBaseReg,
1196 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1199 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1202 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1203 SelectionDAG &DAG) {
1204 EVT PtrVT = Op.getValueType();
1205 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1206 GlobalValue *GV = GSDN->getGlobal();
1207 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1208 SDValue Zero = DAG.getConstant(0, PtrVT);
1209 // FIXME there isn't really any debug info here
1210 DebugLoc dl = GSDN->getDebugLoc();
1212 const TargetMachine &TM = DAG.getTarget();
1214 // 64-bit SVR4 ABI code is always position-independent.
1215 // The actual address of the GlobalValue is stored in the TOC.
1216 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1217 return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA,
1218 DAG.getRegister(PPC::X2, MVT::i64));
1221 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1222 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1224 // If this is a non-darwin platform, we don't support non-static relo models
1226 if (TM.getRelocationModel() == Reloc::Static ||
1227 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1228 // Generate non-pic code that has direct accesses to globals.
1229 // The address of the global is just (hi(&g)+lo(&g)).
1230 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1233 if (TM.getRelocationModel() == Reloc::PIC_) {
1234 // With PIC, the first instruction is actually "GR+hi(&G)".
1235 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1236 DAG.getNode(PPCISD::GlobalBaseReg,
1237 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1240 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1242 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM))
1245 // If the global is weak or external, we have to go through the lazy
1247 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
1250 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1251 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1252 DebugLoc dl = Op.getDebugLoc();
1254 // If we're comparing for equality to zero, expose the fact that this is
1255 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1256 // fold the new nodes.
1257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1258 if (C->isNullValue() && CC == ISD::SETEQ) {
1259 EVT VT = Op.getOperand(0).getValueType();
1260 SDValue Zext = Op.getOperand(0);
1261 if (VT.bitsLT(MVT::i32)) {
1263 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1265 unsigned Log2b = Log2_32(VT.getSizeInBits());
1266 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1267 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1268 DAG.getConstant(Log2b, MVT::i32));
1269 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1271 // Leave comparisons against 0 and -1 alone for now, since they're usually
1272 // optimized. FIXME: revisit this when we can custom lower all setcc
1274 if (C->isAllOnesValue() || C->isNullValue())
1278 // If we have an integer seteq/setne, turn it into a compare against zero
1279 // by xor'ing the rhs with the lhs, which is faster than setting a
1280 // condition register, reading it back out, and masking the correct bit. The
1281 // normal approach here uses sub to do this instead of xor. Using xor exposes
1282 // the result to other bit-twiddling opportunities.
1283 EVT LHSVT = Op.getOperand(0).getValueType();
1284 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1285 EVT VT = Op.getValueType();
1286 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1288 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1293 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1294 int VarArgsFrameIndex,
1295 int VarArgsStackOffset,
1296 unsigned VarArgsNumGPR,
1297 unsigned VarArgsNumFPR,
1298 const PPCSubtarget &Subtarget) {
1300 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1301 return SDValue(); // Not reached
1304 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1305 SDValue Chain = Op.getOperand(0);
1306 SDValue Trmp = Op.getOperand(1); // trampoline
1307 SDValue FPtr = Op.getOperand(2); // nested function
1308 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1309 DebugLoc dl = Op.getDebugLoc();
1311 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1312 bool isPPC64 = (PtrVT == MVT::i64);
1313 const Type *IntPtrTy =
1314 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1317 TargetLowering::ArgListTy Args;
1318 TargetLowering::ArgListEntry Entry;
1320 Entry.Ty = IntPtrTy;
1321 Entry.Node = Trmp; Args.push_back(Entry);
1323 // TrampSize == (isPPC64 ? 48 : 40);
1324 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1325 isPPC64 ? MVT::i64 : MVT::i32);
1326 Args.push_back(Entry);
1328 Entry.Node = FPtr; Args.push_back(Entry);
1329 Entry.Node = Nest; Args.push_back(Entry);
1331 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1332 std::pair<SDValue, SDValue> CallResult =
1333 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
1334 false, false, false, false, 0, CallingConv::C, false,
1335 /*isReturnValueUsed=*/true,
1336 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1340 { CallResult.first, CallResult.second };
1342 return DAG.getMergeValues(Ops, 2, dl);
1345 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1346 int VarArgsFrameIndex,
1347 int VarArgsStackOffset,
1348 unsigned VarArgsNumGPR,
1349 unsigned VarArgsNumFPR,
1350 const PPCSubtarget &Subtarget) {
1351 DebugLoc dl = Op.getDebugLoc();
1353 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1354 // vastart just stores the address of the VarArgsFrameIndex slot into the
1355 // memory location argument.
1356 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1357 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1358 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1359 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1362 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1363 // We suppose the given va_list is already allocated.
1366 // char gpr; /* index into the array of 8 GPRs
1367 // * stored in the register save area
1368 // * gpr=0 corresponds to r3,
1369 // * gpr=1 to r4, etc.
1371 // char fpr; /* index into the array of 8 FPRs
1372 // * stored in the register save area
1373 // * fpr=0 corresponds to f1,
1374 // * fpr=1 to f2, etc.
1376 // char *overflow_arg_area;
1377 // /* location on stack that holds
1378 // * the next overflow argument
1380 // char *reg_save_area;
1381 // /* where r3:r10 and f1:f8 (if saved)
1387 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32);
1388 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32);
1391 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1393 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1394 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1396 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1397 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1399 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1400 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1402 uint64_t FPROffset = 1;
1403 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1405 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1407 // Store first byte : number of int regs
1408 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1409 Op.getOperand(1), SV, 0, MVT::i8);
1410 uint64_t nextOffset = FPROffset;
1411 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1414 // Store second byte : number of float regs
1415 SDValue secondStore =
1416 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8);
1417 nextOffset += StackOffset;
1418 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1420 // Store second word : arguments given on stack
1421 SDValue thirdStore =
1422 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
1423 nextOffset += FrameOffset;
1424 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1426 // Store third word : arguments given in registers
1427 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset);
1431 #include "PPCGenCallingConv.inc"
1433 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
1434 CCValAssign::LocInfo &LocInfo,
1435 ISD::ArgFlagsTy &ArgFlags,
1440 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
1442 CCValAssign::LocInfo &LocInfo,
1443 ISD::ArgFlagsTy &ArgFlags,
1445 static const unsigned ArgRegs[] = {
1446 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1447 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1449 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1451 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1453 // Skip one register if the first unallocated register has an even register
1454 // number and there are still argument registers available which have not been
1455 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1456 // need to skip a register if RegNum is odd.
1457 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1458 State.AllocateReg(ArgRegs[RegNum]);
1461 // Always return false here, as this function only makes sure that the first
1462 // unallocated register has an odd register number and does not actually
1463 // allocate a register for the current argument.
1467 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
1469 CCValAssign::LocInfo &LocInfo,
1470 ISD::ArgFlagsTy &ArgFlags,
1472 static const unsigned ArgRegs[] = {
1473 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1477 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1479 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1481 // If there is only one Floating-point register left we need to put both f64
1482 // values of a split ppc_fp128 value on the stack.
1483 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1484 State.AllocateReg(ArgRegs[RegNum]);
1487 // Always return false here, as this function only makes sure that the two f64
1488 // values a ppc_fp128 value is split into are both passed in registers or both
1489 // passed on the stack and does not actually allocate a register for the
1490 // current argument.
1494 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1496 static const unsigned *GetFPR() {
1497 static const unsigned FPR[] = {
1498 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1499 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1505 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1507 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1508 unsigned PtrByteSize) {
1509 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1510 if (Flags.isByVal())
1511 ArgSize = Flags.getByValSize();
1512 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1518 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1519 CallingConv::ID CallConv, bool isVarArg,
1520 const SmallVectorImpl<ISD::InputArg>
1522 DebugLoc dl, SelectionDAG &DAG,
1523 SmallVectorImpl<SDValue> &InVals) {
1524 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1525 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1528 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1534 PPCTargetLowering::LowerFormalArguments_SVR4(
1536 CallingConv::ID CallConv, bool isVarArg,
1537 const SmallVectorImpl<ISD::InputArg>
1539 DebugLoc dl, SelectionDAG &DAG,
1540 SmallVectorImpl<SDValue> &InVals) {
1542 // 32-bit SVR4 ABI Stack Frame Layout:
1543 // +-----------------------------------+
1544 // +--> | Back chain |
1545 // | +-----------------------------------+
1546 // | | Floating-point register save area |
1547 // | +-----------------------------------+
1548 // | | General register save area |
1549 // | +-----------------------------------+
1550 // | | CR save word |
1551 // | +-----------------------------------+
1552 // | | VRSAVE save word |
1553 // | +-----------------------------------+
1554 // | | Alignment padding |
1555 // | +-----------------------------------+
1556 // | | Vector register save area |
1557 // | +-----------------------------------+
1558 // | | Local variable space |
1559 // | +-----------------------------------+
1560 // | | Parameter list area |
1561 // | +-----------------------------------+
1562 // | | LR save word |
1563 // | +-----------------------------------+
1564 // SP--> +--- | Back chain |
1565 // +-----------------------------------+
1568 // System V Application Binary Interface PowerPC Processor Supplement
1569 // AltiVec Technology Programming Interface Manual
1571 MachineFunction &MF = DAG.getMachineFunction();
1572 MachineFrameInfo *MFI = MF.getFrameInfo();
1574 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1575 // Potential tail calls could cause overwriting of argument stack slots.
1576 bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast));
1577 unsigned PtrByteSize = 4;
1579 // Assign locations to all of the incoming arguments.
1580 SmallVector<CCValAssign, 16> ArgLocs;
1581 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1584 // Reserve space for the linkage area on the stack.
1585 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
1587 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1589 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1590 CCValAssign &VA = ArgLocs[i];
1592 // Arguments stored in registers.
1593 if (VA.isRegLoc()) {
1594 TargetRegisterClass *RC;
1595 EVT ValVT = VA.getValVT();
1597 switch (ValVT.getSimpleVT().SimpleTy) {
1599 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1601 RC = PPC::GPRCRegisterClass;
1604 RC = PPC::F4RCRegisterClass;
1607 RC = PPC::F8RCRegisterClass;
1613 RC = PPC::VRRCRegisterClass;
1617 // Transform the arguments stored in physical registers into virtual ones.
1618 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1619 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1621 InVals.push_back(ArgValue);
1623 // Argument stored in memory.
1624 assert(VA.isMemLoc());
1626 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1627 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1630 // Create load nodes to retrieve arguments from the stack.
1631 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1632 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1636 // Assign locations to all of the incoming aggregate by value arguments.
1637 // Aggregates passed by value are stored in the local variable space of the
1638 // caller's stack frame, right above the parameter list area.
1639 SmallVector<CCValAssign, 16> ByValArgLocs;
1640 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1641 ByValArgLocs, *DAG.getContext());
1643 // Reserve stack space for the allocations in CCInfo.
1644 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1646 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1648 // Area that is at least reserved in the caller of this function.
1649 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1651 // Set the size that is at least reserved in caller of this function. Tail
1652 // call optimized function's reserved stack space needs to be aligned so that
1653 // taking the difference between two stack areas will result in an aligned
1655 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1658 std::max(MinReservedArea,
1659 PPCFrameInfo::getMinCallFrameSize(false, false));
1661 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1662 getStackAlignment();
1663 unsigned AlignMask = TargetAlign-1;
1664 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1666 FI->setMinReservedArea(MinReservedArea);
1668 SmallVector<SDValue, 8> MemOps;
1670 // If the function takes variable number of arguments, make a frame index for
1671 // the start of the first vararg value... for expansion of llvm.va_start.
1673 static const unsigned GPArgRegs[] = {
1674 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1675 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1677 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1679 static const unsigned FPArgRegs[] = {
1680 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1683 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1685 VarArgsNumGPR = CCInfo.getFirstUnallocated(GPArgRegs, NumGPArgRegs);
1686 VarArgsNumFPR = CCInfo.getFirstUnallocated(FPArgRegs, NumFPArgRegs);
1688 // Make room for NumGPArgRegs and NumFPArgRegs.
1689 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1690 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1692 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1693 CCInfo.getNextStackOffset());
1695 VarArgsFrameIndex = MFI->CreateStackObject(Depth, 8);
1696 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1698 // The fixed integer arguments of a variadic function are
1699 // stored to the VarArgsFrameIndex on the stack.
1700 unsigned GPRIndex = 0;
1701 for (; GPRIndex != VarArgsNumGPR; ++GPRIndex) {
1702 SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT);
1703 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0);
1704 MemOps.push_back(Store);
1705 // Increment the address by four for the next argument to store
1706 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1707 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1710 // If this function is vararg, store any remaining integer argument regs
1711 // to their spots on the stack so that they may be loaded by deferencing the
1712 // result of va_next.
1713 for (; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1714 unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1716 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1717 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1718 MemOps.push_back(Store);
1719 // Increment the address by four for the next argument to store
1720 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1721 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1724 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1727 // The double arguments are stored to the VarArgsFrameIndex
1729 unsigned FPRIndex = 0;
1730 for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) {
1731 SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
1732 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0);
1733 MemOps.push_back(Store);
1734 // Increment the address by eight for the next argument to store
1735 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1737 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1740 for (; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1741 unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1743 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1744 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1745 MemOps.push_back(Store);
1746 // Increment the address by eight for the next argument to store
1747 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1749 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1753 if (!MemOps.empty())
1754 Chain = DAG.getNode(ISD::TokenFactor, dl,
1755 MVT::Other, &MemOps[0], MemOps.size());
1761 PPCTargetLowering::LowerFormalArguments_Darwin(
1763 CallingConv::ID CallConv, bool isVarArg,
1764 const SmallVectorImpl<ISD::InputArg>
1766 DebugLoc dl, SelectionDAG &DAG,
1767 SmallVectorImpl<SDValue> &InVals) {
1768 // TODO: add description of PPC stack frame format, or at least some docs.
1770 MachineFunction &MF = DAG.getMachineFunction();
1771 MachineFrameInfo *MFI = MF.getFrameInfo();
1773 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1774 bool isPPC64 = PtrVT == MVT::i64;
1775 // Potential tail calls could cause overwriting of argument stack slots.
1776 bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast));
1777 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1779 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
1780 // Area that is at least reserved in caller of this function.
1781 unsigned MinReservedArea = ArgOffset;
1783 static const unsigned GPR_32[] = { // 32-bit registers.
1784 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1785 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1787 static const unsigned GPR_64[] = { // 64-bit registers.
1788 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1789 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1792 static const unsigned *FPR = GetFPR();
1794 static const unsigned VR[] = {
1795 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1796 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1799 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1800 const unsigned Num_FPR_Regs = 13;
1801 const unsigned Num_VR_Regs = array_lengthof( VR);
1803 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1805 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1807 // In 32-bit non-varargs functions, the stack space for vectors is after the
1808 // stack space for non-vectors. We do not use this space unless we have
1809 // too many vectors to fit in registers, something that only occurs in
1810 // constructed examples:), but we have to walk the arglist to figure
1811 // that out...for the pathological case, compute VecArgOffset as the
1812 // start of the vector parameter area. Computing VecArgOffset is the
1813 // entire point of the following loop.
1814 unsigned VecArgOffset = ArgOffset;
1815 if (!isVarArg && !isPPC64) {
1816 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1818 EVT ObjectVT = Ins[ArgNo].VT;
1819 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1820 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1822 if (Flags.isByVal()) {
1823 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1824 ObjSize = Flags.getByValSize();
1826 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1827 VecArgOffset += ArgSize;
1831 switch(ObjectVT.getSimpleVT().SimpleTy) {
1832 default: llvm_unreachable("Unhandled argument type!");
1835 VecArgOffset += isPPC64 ? 8 : 4;
1837 case MVT::i64: // PPC64
1845 // Nothing to do, we're only looking at Nonvector args here.
1850 // We've found where the vector parameter area in memory is. Skip the
1851 // first 12 parameters; these don't use that memory.
1852 VecArgOffset = ((VecArgOffset+15)/16)*16;
1853 VecArgOffset += 12*16;
1855 // Add DAG nodes to load the arguments or copy them out of registers. On
1856 // entry to a function on PPC, the arguments start after the linkage area,
1857 // although the first ones are often in registers.
1859 SmallVector<SDValue, 8> MemOps;
1860 unsigned nAltivecParamsAtEnd = 0;
1861 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1863 bool needsLoad = false;
1864 EVT ObjectVT = Ins[ArgNo].VT;
1865 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1866 unsigned ArgSize = ObjSize;
1867 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1869 unsigned CurArgOffset = ArgOffset;
1871 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1872 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1873 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1874 if (isVarArg || isPPC64) {
1875 MinReservedArea = ((MinReservedArea+15)/16)*16;
1876 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1879 } else nAltivecParamsAtEnd++;
1881 // Calculate min reserved area.
1882 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1886 // FIXME the codegen can be much improved in some cases.
1887 // We do not have to keep everything in memory.
1888 if (Flags.isByVal()) {
1889 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1890 ObjSize = Flags.getByValSize();
1891 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1892 // Objects of size 1 and 2 are right justified, everything else is
1893 // left justified. This means the memory address is adjusted forwards.
1894 if (ObjSize==1 || ObjSize==2) {
1895 CurArgOffset = CurArgOffset + (4 - ObjSize);
1897 // The value of the object is its address.
1898 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1899 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1900 InVals.push_back(FIN);
1901 if (ObjSize==1 || ObjSize==2) {
1902 if (GPR_idx != Num_GPR_Regs) {
1903 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1904 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1905 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1906 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1907 MemOps.push_back(Store);
1911 ArgOffset += PtrByteSize;
1915 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1916 // Store whatever pieces of the object are in registers
1917 // to memory. ArgVal will be address of the beginning of
1919 if (GPR_idx != Num_GPR_Regs) {
1920 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1921 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1922 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1923 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1924 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1925 MemOps.push_back(Store);
1927 ArgOffset += PtrByteSize;
1929 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1936 switch (ObjectVT.getSimpleVT().SimpleTy) {
1937 default: llvm_unreachable("Unhandled argument type!");
1940 if (GPR_idx != Num_GPR_Regs) {
1941 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1942 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1946 ArgSize = PtrByteSize;
1948 // All int arguments reserve stack space in the Darwin ABI.
1949 ArgOffset += PtrByteSize;
1953 case MVT::i64: // PPC64
1954 if (GPR_idx != Num_GPR_Regs) {
1955 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1956 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1958 if (ObjectVT == MVT::i32) {
1959 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1960 // value to MVT::i64 and then truncate to the correct register size.
1962 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1963 DAG.getValueType(ObjectVT));
1964 else if (Flags.isZExt())
1965 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1966 DAG.getValueType(ObjectVT));
1968 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1974 ArgSize = PtrByteSize;
1976 // All int arguments reserve stack space in the Darwin ABI.
1982 // Every 4 bytes of argument space consumes one of the GPRs available for
1983 // argument passing.
1984 if (GPR_idx != Num_GPR_Regs) {
1986 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1989 if (FPR_idx != Num_FPR_Regs) {
1992 if (ObjectVT == MVT::f32)
1993 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1995 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1997 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2003 // All FP arguments reserve stack space in the Darwin ABI.
2004 ArgOffset += isPPC64 ? 8 : ObjSize;
2010 // Note that vector arguments in registers don't reserve stack space,
2011 // except in varargs functions.
2012 if (VR_idx != Num_VR_Regs) {
2013 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2014 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2016 while ((ArgOffset % 16) != 0) {
2017 ArgOffset += PtrByteSize;
2018 if (GPR_idx != Num_GPR_Regs)
2022 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2026 if (!isVarArg && !isPPC64) {
2027 // Vectors go after all the nonvectors.
2028 CurArgOffset = VecArgOffset;
2031 // Vectors are aligned.
2032 ArgOffset = ((ArgOffset+15)/16)*16;
2033 CurArgOffset = ArgOffset;
2041 // We need to load the argument to a virtual register if we determined above
2042 // that we ran out of physical registers of the appropriate type.
2044 int FI = MFI->CreateFixedObject(ObjSize,
2045 CurArgOffset + (ArgSize - ObjSize),
2047 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2048 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0);
2051 InVals.push_back(ArgVal);
2054 // Set the size that is at least reserved in caller of this function. Tail
2055 // call optimized function's reserved stack space needs to be aligned so that
2056 // taking the difference between two stack areas will result in an aligned
2058 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2059 // Add the Altivec parameters at the end, if needed.
2060 if (nAltivecParamsAtEnd) {
2061 MinReservedArea = ((MinReservedArea+15)/16)*16;
2062 MinReservedArea += 16*nAltivecParamsAtEnd;
2065 std::max(MinReservedArea,
2066 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2067 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2068 getStackAlignment();
2069 unsigned AlignMask = TargetAlign-1;
2070 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2071 FI->setMinReservedArea(MinReservedArea);
2073 // If the function takes variable number of arguments, make a frame index for
2074 // the start of the first vararg value... for expansion of llvm.va_start.
2076 int Depth = ArgOffset;
2078 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2080 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
2082 // If this function is vararg, store any remaining integer argument regs
2083 // to their spots on the stack so that they may be loaded by deferencing the
2084 // result of va_next.
2085 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2089 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2091 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2093 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2094 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
2095 MemOps.push_back(Store);
2096 // Increment the address by four for the next argument to store
2097 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2098 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2102 if (!MemOps.empty())
2103 Chain = DAG.getNode(ISD::TokenFactor, dl,
2104 MVT::Other, &MemOps[0], MemOps.size());
2109 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2110 /// linkage area for the Darwin ABI.
2112 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2116 const SmallVectorImpl<ISD::OutputArg>
2118 unsigned &nAltivecParamsAtEnd) {
2119 // Count how many bytes are to be pushed on the stack, including the linkage
2120 // area, and parameter passing area. We start with 24/48 bytes, which is
2121 // prereserved space for [SP][CR][LR][3 x unused].
2122 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true);
2123 unsigned NumOps = Outs.size();
2124 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2126 // Add up all the space actually used.
2127 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2128 // they all go in registers, but we must reserve stack space for them for
2129 // possible use by the caller. In varargs or 64-bit calls, parameters are
2130 // assigned stack space in order, with padding so Altivec parameters are
2132 nAltivecParamsAtEnd = 0;
2133 for (unsigned i = 0; i != NumOps; ++i) {
2134 SDValue Arg = Outs[i].Val;
2135 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2136 EVT ArgVT = Arg.getValueType();
2137 // Varargs Altivec parameters are padded to a 16 byte boundary.
2138 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2139 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2140 if (!isVarArg && !isPPC64) {
2141 // Non-varargs Altivec parameters go after all the non-Altivec
2142 // parameters; handle those later so we know how much padding we need.
2143 nAltivecParamsAtEnd++;
2146 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2147 NumBytes = ((NumBytes+15)/16)*16;
2149 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2152 // Allow for Altivec parameters at the end, if needed.
2153 if (nAltivecParamsAtEnd) {
2154 NumBytes = ((NumBytes+15)/16)*16;
2155 NumBytes += 16*nAltivecParamsAtEnd;
2158 // The prolog code of the callee may store up to 8 GPR argument registers to
2159 // the stack, allowing va_start to index over them in memory if its varargs.
2160 // Because we cannot tell if this is needed on the caller side, we have to
2161 // conservatively assume that it is needed. As such, make sure we have at
2162 // least enough stack space for the caller to store the 8 GPRs.
2163 NumBytes = std::max(NumBytes,
2164 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2166 // Tail call needs the stack to be aligned.
2167 if (CC==CallingConv::Fast && PerformTailCallOpt) {
2168 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2169 getStackAlignment();
2170 unsigned AlignMask = TargetAlign-1;
2171 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2177 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2178 /// adjusted to accomodate the arguments for the tailcall.
2179 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
2180 unsigned ParamSize) {
2182 if (!IsTailCall) return 0;
2184 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2185 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2186 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2187 // Remember only if the new adjustement is bigger.
2188 if (SPDiff < FI->getTailCallSPDelta())
2189 FI->setTailCallSPDelta(SPDiff);
2194 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2195 /// for tail call optimization. Targets which want to do tail call
2196 /// optimization should implement this function.
2198 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2199 CallingConv::ID CalleeCC,
2201 const SmallVectorImpl<ISD::InputArg> &Ins,
2202 SelectionDAG& DAG) const {
2203 // Variable argument functions are not supported.
2207 MachineFunction &MF = DAG.getMachineFunction();
2208 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2209 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2210 // Functions containing by val parameters are not supported.
2211 for (unsigned i = 0; i != Ins.size(); i++) {
2212 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2213 if (Flags.isByVal()) return false;
2216 // Non PIC/GOT tail calls are supported.
2217 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2220 // At the moment we can only do local tail calls (in same module, hidden
2221 // or protected) if we are generating PIC.
2222 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2223 return G->getGlobal()->hasHiddenVisibility()
2224 || G->getGlobal()->hasProtectedVisibility();
2230 /// isCallCompatibleAddress - Return the immediate to use if the specified
2231 /// 32-bit value is representable in the immediate field of a BxA instruction.
2232 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2233 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2236 int Addr = C->getZExtValue();
2237 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2238 (Addr << 6 >> 6) != Addr)
2239 return 0; // Top 6 bits have to be sext of immediate.
2241 return DAG.getConstant((int)C->getZExtValue() >> 2,
2242 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2247 struct TailCallArgumentInfo {
2252 TailCallArgumentInfo() : FrameIdx(0) {}
2257 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2259 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2261 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2262 SmallVector<SDValue, 8> &MemOpChains,
2264 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2265 SDValue Arg = TailCallArgs[i].Arg;
2266 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2267 int FI = TailCallArgs[i].FrameIdx;
2268 // Store relative to framepointer.
2269 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2270 PseudoSourceValue::getFixedStack(FI),
2275 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2276 /// the appropriate stack slot for the tail call optimized function call.
2277 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2278 MachineFunction &MF,
2287 // Calculate the new stack slot for the return address.
2288 int SlotSize = isPPC64 ? 8 : 4;
2289 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2291 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2293 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2294 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2295 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2296 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
2298 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2299 // slot as the FP is never overwritten.
2302 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2303 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
2304 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2305 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2306 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
2312 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2313 /// the position of the argument.
2315 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2316 SDValue Arg, int SPDiff, unsigned ArgOffset,
2317 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2318 int Offset = ArgOffset + SPDiff;
2319 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2320 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
2321 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2322 SDValue FIN = DAG.getFrameIndex(FI, VT);
2323 TailCallArgumentInfo Info;
2325 Info.FrameIdxOp = FIN;
2327 TailCallArguments.push_back(Info);
2330 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2331 /// stack slot. Returns the chain as result and the loaded frame pointers in
2332 /// LROpOut/FPOpout. Used when tail calling.
2333 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2341 // Load the LR and FP stack slot for later adjusting.
2342 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2343 LROpOut = getReturnAddrFrameIndex(DAG);
2344 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
2345 Chain = SDValue(LROpOut.getNode(), 1);
2347 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2348 // slot as the FP is never overwritten.
2350 FPOpOut = getFramePointerFrameIndex(DAG);
2351 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
2352 Chain = SDValue(FPOpOut.getNode(), 1);
2358 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2359 /// by "Src" to address "Dst" of size "Size". Alignment information is
2360 /// specified by the specific parameter attribute. The copy will be passed as
2361 /// a byval function parameter.
2362 /// Sometimes what we are copying is the end of a larger object, the part that
2363 /// does not fit in registers.
2365 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2366 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2368 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2369 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2370 false, NULL, 0, NULL, 0);
2373 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2376 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2377 SDValue Arg, SDValue PtrOff, int SPDiff,
2378 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2379 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2380 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2382 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2387 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2389 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2390 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2391 DAG.getConstant(ArgOffset, PtrVT));
2393 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
2394 // Calculate and remember argument location.
2395 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2400 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2401 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2402 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2403 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2404 MachineFunction &MF = DAG.getMachineFunction();
2406 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2407 // might overwrite each other in case of tail call optimization.
2408 SmallVector<SDValue, 8> MemOpChains2;
2409 // Do not flag preceeding copytoreg stuff together with the following stuff.
2411 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2413 if (!MemOpChains2.empty())
2414 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2415 &MemOpChains2[0], MemOpChains2.size());
2417 // Store the return address to the appropriate stack slot.
2418 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2419 isPPC64, isDarwinABI, dl);
2421 // Emit callseq_end just before tailcall node.
2422 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2423 DAG.getIntPtrConstant(0, true), InFlag);
2424 InFlag = Chain.getValue(1);
2428 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2429 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2430 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2431 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2433 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2434 NodeTys.push_back(MVT::Other); // Returns a chain
2435 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2437 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2439 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2440 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2441 // node so that legalize doesn't hack it.
2442 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2443 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2444 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2445 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2446 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2447 // If this is an absolute destination address, use the munged value.
2448 Callee = SDValue(Dest, 0);
2450 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2451 // to do the call, we can't use PPCISD::CALL.
2452 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2453 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2454 2 + (InFlag.getNode() != 0));
2455 InFlag = Chain.getValue(1);
2458 NodeTys.push_back(MVT::Other);
2459 NodeTys.push_back(MVT::Flag);
2460 Ops.push_back(Chain);
2461 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2463 // Add CTR register as callee so a bctr can be emitted later.
2465 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2468 // If this is a direct call, pass the chain and the callee.
2469 if (Callee.getNode()) {
2470 Ops.push_back(Chain);
2471 Ops.push_back(Callee);
2473 // If this is a tail call add stack pointer delta.
2475 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2477 // Add argument registers to the end of the list so that they are known live
2479 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2480 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2481 RegsToPass[i].second.getValueType()));
2487 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2488 CallingConv::ID CallConv, bool isVarArg,
2489 const SmallVectorImpl<ISD::InputArg> &Ins,
2490 DebugLoc dl, SelectionDAG &DAG,
2491 SmallVectorImpl<SDValue> &InVals) {
2493 SmallVector<CCValAssign, 16> RVLocs;
2494 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2495 RVLocs, *DAG.getContext());
2496 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2498 // Copy all of the result registers out of their specified physreg.
2499 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2500 CCValAssign &VA = RVLocs[i];
2501 EVT VT = VA.getValVT();
2502 assert(VA.isRegLoc() && "Can only return in registers!");
2503 Chain = DAG.getCopyFromReg(Chain, dl,
2504 VA.getLocReg(), VT, InFlag).getValue(1);
2505 InVals.push_back(Chain.getValue(0));
2506 InFlag = Chain.getValue(2);
2513 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2514 bool isTailCall, bool isVarArg,
2516 SmallVector<std::pair<unsigned, SDValue>, 8>
2518 SDValue InFlag, SDValue Chain,
2520 int SPDiff, unsigned NumBytes,
2521 const SmallVectorImpl<ISD::InputArg> &Ins,
2522 SmallVectorImpl<SDValue> &InVals) {
2523 std::vector<EVT> NodeTys;
2524 SmallVector<SDValue, 8> Ops;
2525 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2526 isTailCall, RegsToPass, Ops, NodeTys,
2527 PPCSubTarget.isSVR4ABI());
2529 // When performing tail call optimization the callee pops its arguments off
2530 // the stack. Account for this here so these bytes can be pushed back on in
2531 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2532 int BytesCalleePops =
2533 (CallConv==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2535 if (InFlag.getNode())
2536 Ops.push_back(InFlag);
2540 // If this is the first return lowered for this function, add the regs
2541 // to the liveout set for the function.
2542 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2543 SmallVector<CCValAssign, 16> RVLocs;
2544 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2546 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2547 for (unsigned i = 0; i != RVLocs.size(); ++i)
2548 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2551 assert(((Callee.getOpcode() == ISD::Register &&
2552 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2553 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2554 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2555 isa<ConstantSDNode>(Callee)) &&
2556 "Expecting an global address, external symbol, absolute value or register");
2558 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2561 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2562 InFlag = Chain.getValue(1);
2564 // Add a NOP immediately after the branch instruction when using the 64-bit
2565 // SVR4 ABI. At link time, if caller and callee are in a different module and
2566 // thus have a different TOC, the call will be replaced with a call to a stub
2567 // function which saves the current TOC, loads the TOC of the callee and
2568 // branches to the callee. The NOP will be replaced with a load instruction
2569 // which restores the TOC of the caller from the TOC save slot of the current
2570 // stack frame. If caller and callee belong to the same module (and have the
2571 // same TOC), the NOP will remain unchanged.
2572 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2574 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag);
2577 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2578 DAG.getIntPtrConstant(BytesCalleePops, true),
2581 InFlag = Chain.getValue(1);
2583 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2584 Ins, dl, DAG, InVals);
2588 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2589 CallingConv::ID CallConv, bool isVarArg,
2591 const SmallVectorImpl<ISD::OutputArg> &Outs,
2592 const SmallVectorImpl<ISD::InputArg> &Ins,
2593 DebugLoc dl, SelectionDAG &DAG,
2594 SmallVectorImpl<SDValue> &InVals) {
2595 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
2596 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2597 isTailCall, Outs, Ins,
2600 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2601 isTailCall, Outs, Ins,
2607 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2608 CallingConv::ID CallConv, bool isVarArg,
2610 const SmallVectorImpl<ISD::OutputArg> &Outs,
2611 const SmallVectorImpl<ISD::InputArg> &Ins,
2612 DebugLoc dl, SelectionDAG &DAG,
2613 SmallVectorImpl<SDValue> &InVals) {
2614 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2615 // of the 32-bit SVR4 ABI stack frame layout.
2617 assert((!isTailCall ||
2618 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
2619 "IsEligibleForTailCallOptimization missed a case!");
2621 assert((CallConv == CallingConv::C ||
2622 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2624 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2625 unsigned PtrByteSize = 4;
2627 MachineFunction &MF = DAG.getMachineFunction();
2629 // Mark this function as potentially containing a function that contains a
2630 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2631 // and restoring the callers stack pointer in this functions epilog. This is
2632 // done because by tail calling the called function might overwrite the value
2633 // in this function's (MF) stack pointer stack slot 0(SP).
2634 if (PerformTailCallOpt && CallConv==CallingConv::Fast)
2635 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2637 // Count how many bytes are to be pushed on the stack, including the linkage
2638 // area, parameter list area and the part of the local variable space which
2639 // contains copies of aggregates which are passed by value.
2641 // Assign locations to all of the outgoing arguments.
2642 SmallVector<CCValAssign, 16> ArgLocs;
2643 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2644 ArgLocs, *DAG.getContext());
2646 // Reserve space for the linkage area on the stack.
2647 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
2650 // Handle fixed and variable vector arguments differently.
2651 // Fixed vector arguments go into registers as long as registers are
2652 // available. Variable vector arguments always go into memory.
2653 unsigned NumArgs = Outs.size();
2655 for (unsigned i = 0; i != NumArgs; ++i) {
2656 EVT ArgVT = Outs[i].Val.getValueType();
2657 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2660 if (Outs[i].IsFixed) {
2661 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2664 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2670 errs() << "Call operand #" << i << " has unhandled type "
2671 << ArgVT.getEVTString() << "\n";
2673 llvm_unreachable(0);
2677 // All arguments are treated the same.
2678 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2681 // Assign locations to all of the outgoing aggregate by value arguments.
2682 SmallVector<CCValAssign, 16> ByValArgLocs;
2683 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2686 // Reserve stack space for the allocations in CCInfo.
2687 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2689 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2691 // Size of the linkage area, parameter list area and the part of the local
2692 // space variable where copies of aggregates which are passed by value are
2694 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2696 // Calculate by how many bytes the stack has to be adjusted in case of tail
2697 // call optimization.
2698 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2700 // Adjust the stack pointer for the new arguments...
2701 // These operations are automatically eliminated by the prolog/epilog pass
2702 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2703 SDValue CallSeqStart = Chain;
2705 // Load the return address and frame pointer so it can be moved somewhere else
2708 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2711 // Set up a copy of the stack pointer for use loading and storing any
2712 // arguments that may not fit in the registers available for argument
2714 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2716 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2717 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2718 SmallVector<SDValue, 8> MemOpChains;
2720 // Walk the register/memloc assignments, inserting copies/loads.
2721 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2724 CCValAssign &VA = ArgLocs[i];
2725 SDValue Arg = Outs[i].Val;
2726 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2728 if (Flags.isByVal()) {
2729 // Argument is an aggregate which is passed by value, thus we need to
2730 // create a copy of it in the local variable space of the current stack
2731 // frame (which is the stack frame of the caller) and pass the address of
2732 // this copy to the callee.
2733 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2734 CCValAssign &ByValVA = ByValArgLocs[j++];
2735 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2737 // Memory reserved in the local variable space of the callers stack frame.
2738 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2740 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2741 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2743 // Create a copy of the argument in the local area of the current
2745 SDValue MemcpyCall =
2746 CreateCopyOfByValArgument(Arg, PtrOff,
2747 CallSeqStart.getNode()->getOperand(0),
2750 // This must go outside the CALLSEQ_START..END.
2751 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2752 CallSeqStart.getNode()->getOperand(1));
2753 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2754 NewCallSeqStart.getNode());
2755 Chain = CallSeqStart = NewCallSeqStart;
2757 // Pass the address of the aggregate copy on the stack either in a
2758 // physical register or in the parameter list area of the current stack
2759 // frame to the callee.
2763 if (VA.isRegLoc()) {
2764 // Put argument in a physical register.
2765 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2767 // Put argument in the parameter list area of the current stack frame.
2768 assert(VA.isMemLoc());
2769 unsigned LocMemOffset = VA.getLocMemOffset();
2772 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2773 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2775 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2776 PseudoSourceValue::getStack(), LocMemOffset));
2778 // Calculate and remember argument location.
2779 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2785 if (!MemOpChains.empty())
2786 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2787 &MemOpChains[0], MemOpChains.size());
2789 // Build a sequence of copy-to-reg nodes chained together with token chain
2790 // and flag operands which copy the outgoing args into the appropriate regs.
2792 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2793 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2794 RegsToPass[i].second, InFlag);
2795 InFlag = Chain.getValue(1);
2798 // Set CR6 to true if this is a vararg call.
2800 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0);
2801 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2802 InFlag = Chain.getValue(1);
2806 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2807 false, TailCallArguments);
2810 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
2811 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
2816 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
2817 CallingConv::ID CallConv, bool isVarArg,
2819 const SmallVectorImpl<ISD::OutputArg> &Outs,
2820 const SmallVectorImpl<ISD::InputArg> &Ins,
2821 DebugLoc dl, SelectionDAG &DAG,
2822 SmallVectorImpl<SDValue> &InVals) {
2824 unsigned NumOps = Outs.size();
2826 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2827 bool isPPC64 = PtrVT == MVT::i64;
2828 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2830 MachineFunction &MF = DAG.getMachineFunction();
2832 // Mark this function as potentially containing a function that contains a
2833 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2834 // and restoring the callers stack pointer in this functions epilog. This is
2835 // done because by tail calling the called function might overwrite the value
2836 // in this function's (MF) stack pointer stack slot 0(SP).
2837 if (PerformTailCallOpt && CallConv==CallingConv::Fast)
2838 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2840 unsigned nAltivecParamsAtEnd = 0;
2842 // Count how many bytes are to be pushed on the stack, including the linkage
2843 // area, and parameter passing area. We start with 24/48 bytes, which is
2844 // prereserved space for [SP][CR][LR][3 x unused].
2846 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2848 nAltivecParamsAtEnd);
2850 // Calculate by how many bytes the stack has to be adjusted in case of tail
2851 // call optimization.
2852 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2854 // To protect arguments on the stack from being clobbered in a tail call,
2855 // force all the loads to happen before doing any other lowering.
2857 Chain = DAG.getStackArgumentTokenFactor(Chain);
2859 // Adjust the stack pointer for the new arguments...
2860 // These operations are automatically eliminated by the prolog/epilog pass
2861 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2862 SDValue CallSeqStart = Chain;
2864 // Load the return address and frame pointer so it can be move somewhere else
2867 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2870 // Set up a copy of the stack pointer for use loading and storing any
2871 // arguments that may not fit in the registers available for argument
2875 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2877 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2879 // Figure out which arguments are going to go in registers, and which in
2880 // memory. Also, if this is a vararg function, floating point operations
2881 // must be stored to our stack, and loaded into integer regs as well, if
2882 // any integer regs are available for argument passing.
2883 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
2884 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2886 static const unsigned GPR_32[] = { // 32-bit registers.
2887 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2888 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2890 static const unsigned GPR_64[] = { // 64-bit registers.
2891 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2892 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2894 static const unsigned *FPR = GetFPR();
2896 static const unsigned VR[] = {
2897 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2898 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2900 const unsigned NumGPRs = array_lengthof(GPR_32);
2901 const unsigned NumFPRs = 13;
2902 const unsigned NumVRs = array_lengthof(VR);
2904 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2906 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2907 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2909 SmallVector<SDValue, 8> MemOpChains;
2910 for (unsigned i = 0; i != NumOps; ++i) {
2911 SDValue Arg = Outs[i].Val;
2912 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2914 // PtrOff will be used to store the current argument to the stack if a
2915 // register cannot be found for it.
2918 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2920 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
2922 // On PPC64, promote integers to 64-bit values.
2923 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2924 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2925 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2926 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
2929 // FIXME memcpy is used way more than necessary. Correctness first.
2930 if (Flags.isByVal()) {
2931 unsigned Size = Flags.getByValSize();
2932 if (Size==1 || Size==2) {
2933 // Very small objects are passed right-justified.
2934 // Everything else is passed left-justified.
2935 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2936 if (GPR_idx != NumGPRs) {
2937 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
2939 MemOpChains.push_back(Load.getValue(1));
2940 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2942 ArgOffset += PtrByteSize;
2944 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2945 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
2946 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2947 CallSeqStart.getNode()->getOperand(0),
2949 // This must go outside the CALLSEQ_START..END.
2950 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2951 CallSeqStart.getNode()->getOperand(1));
2952 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2953 NewCallSeqStart.getNode());
2954 Chain = CallSeqStart = NewCallSeqStart;
2955 ArgOffset += PtrByteSize;
2959 // Copy entire object into memory. There are cases where gcc-generated
2960 // code assumes it is there, even if it could be put entirely into
2961 // registers. (This is not what the doc says.)
2962 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2963 CallSeqStart.getNode()->getOperand(0),
2965 // This must go outside the CALLSEQ_START..END.
2966 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2967 CallSeqStart.getNode()->getOperand(1));
2968 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2969 Chain = CallSeqStart = NewCallSeqStart;
2970 // And copy the pieces of it that fit into registers.
2971 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2972 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
2973 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2974 if (GPR_idx != NumGPRs) {
2975 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
2976 MemOpChains.push_back(Load.getValue(1));
2977 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2978 ArgOffset += PtrByteSize;
2980 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2987 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
2988 default: llvm_unreachable("Unexpected ValueType for argument!");
2991 if (GPR_idx != NumGPRs) {
2992 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2994 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2995 isPPC64, isTailCall, false, MemOpChains,
2996 TailCallArguments, dl);
2998 ArgOffset += PtrByteSize;
3002 if (FPR_idx != NumFPRs) {
3003 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3006 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
3007 MemOpChains.push_back(Store);
3009 // Float varargs are always shadowed in available integer registers
3010 if (GPR_idx != NumGPRs) {
3011 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
3012 MemOpChains.push_back(Load.getValue(1));
3013 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3015 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3016 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3017 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3018 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
3019 MemOpChains.push_back(Load.getValue(1));
3020 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3023 // If we have any FPRs remaining, we may also have GPRs remaining.
3024 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3026 if (GPR_idx != NumGPRs)
3028 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3029 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3033 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3034 isPPC64, isTailCall, false, MemOpChains,
3035 TailCallArguments, dl);
3040 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3047 // These go aligned on the stack, or in the corresponding R registers
3048 // when within range. The Darwin PPC ABI doc claims they also go in
3049 // V registers; in fact gcc does this only for arguments that are
3050 // prototyped, not for those that match the ... We do it for all
3051 // arguments, seems to work.
3052 while (ArgOffset % 16 !=0) {
3053 ArgOffset += PtrByteSize;
3054 if (GPR_idx != NumGPRs)
3057 // We could elide this store in the case where the object fits
3058 // entirely in R registers. Maybe later.
3059 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3060 DAG.getConstant(ArgOffset, PtrVT));
3061 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
3062 MemOpChains.push_back(Store);
3063 if (VR_idx != NumVRs) {
3064 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
3065 MemOpChains.push_back(Load.getValue(1));
3066 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3069 for (unsigned i=0; i<16; i+=PtrByteSize) {
3070 if (GPR_idx == NumGPRs)
3072 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3073 DAG.getConstant(i, PtrVT));
3074 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
3075 MemOpChains.push_back(Load.getValue(1));
3076 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3081 // Non-varargs Altivec params generally go in registers, but have
3082 // stack space allocated at the end.
3083 if (VR_idx != NumVRs) {
3084 // Doesn't have GPR space allocated.
3085 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3086 } else if (nAltivecParamsAtEnd==0) {
3087 // We are emitting Altivec params in order.
3088 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3089 isPPC64, isTailCall, true, MemOpChains,
3090 TailCallArguments, dl);
3096 // If all Altivec parameters fit in registers, as they usually do,
3097 // they get stack space following the non-Altivec parameters. We
3098 // don't track this here because nobody below needs it.
3099 // If there are more Altivec parameters than fit in registers emit
3101 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3103 // Offset is aligned; skip 1st 12 params which go in V registers.
3104 ArgOffset = ((ArgOffset+15)/16)*16;
3106 for (unsigned i = 0; i != NumOps; ++i) {
3107 SDValue Arg = Outs[i].Val;
3108 EVT ArgType = Arg.getValueType();
3109 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3110 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3113 // We are emitting Altivec params in order.
3114 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3115 isPPC64, isTailCall, true, MemOpChains,
3116 TailCallArguments, dl);
3123 if (!MemOpChains.empty())
3124 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3125 &MemOpChains[0], MemOpChains.size());
3127 // Build a sequence of copy-to-reg nodes chained together with token chain
3128 // and flag operands which copy the outgoing args into the appropriate regs.
3130 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3131 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3132 RegsToPass[i].second, InFlag);
3133 InFlag = Chain.getValue(1);
3137 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3138 FPOp, true, TailCallArguments);
3141 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3142 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3147 PPCTargetLowering::LowerReturn(SDValue Chain,
3148 CallingConv::ID CallConv, bool isVarArg,
3149 const SmallVectorImpl<ISD::OutputArg> &Outs,
3150 DebugLoc dl, SelectionDAG &DAG) {
3152 SmallVector<CCValAssign, 16> RVLocs;
3153 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3154 RVLocs, *DAG.getContext());
3155 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3157 // If this is the first return lowered for this function, add the regs to the
3158 // liveout set for the function.
3159 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3160 for (unsigned i = 0; i != RVLocs.size(); ++i)
3161 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3166 // Copy the result values into the output registers.
3167 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3168 CCValAssign &VA = RVLocs[i];
3169 assert(VA.isRegLoc() && "Can only return in registers!");
3170 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3172 Flag = Chain.getValue(1);
3176 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3178 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3181 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3182 const PPCSubtarget &Subtarget) {
3183 // When we pop the dynamic allocation we need to restore the SP link.
3184 DebugLoc dl = Op.getDebugLoc();
3186 // Get the corect type for pointers.
3187 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3189 // Construct the stack pointer operand.
3190 bool IsPPC64 = Subtarget.isPPC64();
3191 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
3192 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3194 // Get the operands for the STACKRESTORE.
3195 SDValue Chain = Op.getOperand(0);
3196 SDValue SaveSP = Op.getOperand(1);
3198 // Load the old link SP.
3199 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
3201 // Restore the stack pointer.
3202 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3204 // Store the old link SP.
3205 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
3211 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3212 MachineFunction &MF = DAG.getMachineFunction();
3213 bool IsPPC64 = PPCSubTarget.isPPC64();
3214 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3215 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3217 // Get current frame pointer save index. The users of this index will be
3218 // primarily DYNALLOC instructions.
3219 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3220 int RASI = FI->getReturnAddrSaveIndex();
3222 // If the frame pointer save index hasn't been defined yet.
3224 // Find out what the fix offset of the frame pointer save area.
3225 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
3226 // Allocate the frame index for frame pointer save area.
3227 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
3229 FI->setReturnAddrSaveIndex(RASI);
3231 return DAG.getFrameIndex(RASI, PtrVT);
3235 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3236 MachineFunction &MF = DAG.getMachineFunction();
3237 bool IsPPC64 = PPCSubTarget.isPPC64();
3238 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3239 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3241 // Get current frame pointer save index. The users of this index will be
3242 // primarily DYNALLOC instructions.
3243 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3244 int FPSI = FI->getFramePointerSaveIndex();
3246 // If the frame pointer save index hasn't been defined yet.
3248 // Find out what the fix offset of the frame pointer save area.
3249 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
3252 // Allocate the frame index for frame pointer save area.
3253 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
3255 FI->setFramePointerSaveIndex(FPSI);
3257 return DAG.getFrameIndex(FPSI, PtrVT);
3260 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3262 const PPCSubtarget &Subtarget) {
3264 SDValue Chain = Op.getOperand(0);
3265 SDValue Size = Op.getOperand(1);
3266 DebugLoc dl = Op.getDebugLoc();
3268 // Get the corect type for pointers.
3269 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3271 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3272 DAG.getConstant(0, PtrVT), Size);
3273 // Construct a node for the frame pointer save index.
3274 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3275 // Build a DYNALLOC node.
3276 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3277 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3278 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3281 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3283 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
3284 // Not FP? Not a fsel.
3285 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3286 !Op.getOperand(2).getValueType().isFloatingPoint())
3289 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3291 // Cannot handle SETEQ/SETNE.
3292 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3294 EVT ResVT = Op.getValueType();
3295 EVT CmpVT = Op.getOperand(0).getValueType();
3296 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3297 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3298 DebugLoc dl = Op.getDebugLoc();
3300 // If the RHS of the comparison is a 0.0, we don't need to do the
3301 // subtraction at all.
3302 if (isFloatingPointZero(RHS))
3304 default: break; // SETUO etc aren't handled by fsel.
3307 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3310 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3311 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3312 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3315 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3318 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3319 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3320 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3321 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3326 default: break; // SETUO etc aren't handled by fsel.
3329 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3330 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3331 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3332 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3335 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3336 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3337 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3338 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3341 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3342 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3343 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3344 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3347 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3348 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3349 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3350 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3355 // FIXME: Split this code up when LegalizeDAGTypes lands.
3356 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3358 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3359 SDValue Src = Op.getOperand(0);
3360 if (Src.getValueType() == MVT::f32)
3361 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3364 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3365 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3367 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3372 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3376 // Convert the FP value to an int value through memory.
3377 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3379 // Emit a store to the stack slot.
3380 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
3382 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3384 if (Op.getValueType() == MVT::i32)
3385 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3386 DAG.getConstant(4, FIPtr.getValueType()));
3387 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
3390 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3391 DebugLoc dl = Op.getDebugLoc();
3392 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3393 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3396 if (Op.getOperand(0).getValueType() == MVT::i64) {
3397 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
3398 MVT::f64, Op.getOperand(0));
3399 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3400 if (Op.getValueType() == MVT::f32)
3401 FP = DAG.getNode(ISD::FP_ROUND, dl,
3402 MVT::f32, FP, DAG.getIntPtrConstant(0));
3406 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3407 "Unhandled SINT_TO_FP type in custom expander!");
3408 // Since we only generate this in 64-bit mode, we can take advantage of
3409 // 64-bit registers. In particular, sign extend the input value into the
3410 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3411 // then lfd it and fcfid it.
3412 MachineFunction &MF = DAG.getMachineFunction();
3413 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3414 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
3415 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3416 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3418 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3421 // STD the extended value into the stack slot.
3422 MachineMemOperand *MMO =
3423 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
3424 MachineMemOperand::MOStore, 0, 8, 8);
3425 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3427 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3428 Ops, 4, MVT::i64, MMO);
3429 // Load the value as a double.
3430 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
3432 // FCFID it and return it.
3433 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3434 if (Op.getValueType() == MVT::f32)
3435 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3439 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
3440 DebugLoc dl = Op.getDebugLoc();
3442 The rounding mode is in bits 30:31 of FPSR, and has the following
3449 FLT_ROUNDS, on the other hand, expects the following:
3456 To perform the conversion, we do:
3457 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3460 MachineFunction &MF = DAG.getMachineFunction();
3461 EVT VT = Op.getValueType();
3462 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3463 std::vector<EVT> NodeTys;
3464 SDValue MFFSreg, InFlag;
3466 // Save FP Control Word to register
3467 NodeTys.push_back(MVT::f64); // return register
3468 NodeTys.push_back(MVT::Flag); // unused in this context
3469 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3471 // Save FP register to stack slot
3472 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3473 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3474 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3475 StackSlot, NULL, 0);
3477 // Load FP Control Word from low 32 bits of stack slot.
3478 SDValue Four = DAG.getConstant(4, PtrVT);
3479 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3480 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
3482 // Transform as necessary
3484 DAG.getNode(ISD::AND, dl, MVT::i32,
3485 CWD, DAG.getConstant(3, MVT::i32));
3487 DAG.getNode(ISD::SRL, dl, MVT::i32,
3488 DAG.getNode(ISD::AND, dl, MVT::i32,
3489 DAG.getNode(ISD::XOR, dl, MVT::i32,
3490 CWD, DAG.getConstant(3, MVT::i32)),
3491 DAG.getConstant(3, MVT::i32)),
3492 DAG.getConstant(1, MVT::i32));
3495 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3497 return DAG.getNode((VT.getSizeInBits() < 16 ?
3498 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3501 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
3502 EVT VT = Op.getValueType();
3503 unsigned BitWidth = VT.getSizeInBits();
3504 DebugLoc dl = Op.getDebugLoc();
3505 assert(Op.getNumOperands() == 3 &&
3506 VT == Op.getOperand(1).getValueType() &&
3509 // Expand into a bunch of logical ops. Note that these ops
3510 // depend on the PPC behavior for oversized shift amounts.
3511 SDValue Lo = Op.getOperand(0);
3512 SDValue Hi = Op.getOperand(1);
3513 SDValue Amt = Op.getOperand(2);
3514 EVT AmtVT = Amt.getValueType();
3516 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3517 DAG.getConstant(BitWidth, AmtVT), Amt);
3518 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3519 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3520 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3521 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3522 DAG.getConstant(-BitWidth, AmtVT));
3523 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3524 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3525 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3526 SDValue OutOps[] = { OutLo, OutHi };
3527 return DAG.getMergeValues(OutOps, 2, dl);
3530 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3531 EVT VT = Op.getValueType();
3532 DebugLoc dl = Op.getDebugLoc();
3533 unsigned BitWidth = VT.getSizeInBits();
3534 assert(Op.getNumOperands() == 3 &&
3535 VT == Op.getOperand(1).getValueType() &&
3538 // Expand into a bunch of logical ops. Note that these ops
3539 // depend on the PPC behavior for oversized shift amounts.
3540 SDValue Lo = Op.getOperand(0);
3541 SDValue Hi = Op.getOperand(1);
3542 SDValue Amt = Op.getOperand(2);
3543 EVT AmtVT = Amt.getValueType();
3545 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3546 DAG.getConstant(BitWidth, AmtVT), Amt);
3547 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3548 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3549 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3550 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3551 DAG.getConstant(-BitWidth, AmtVT));
3552 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3553 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3554 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3555 SDValue OutOps[] = { OutLo, OutHi };
3556 return DAG.getMergeValues(OutOps, 2, dl);
3559 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3560 DebugLoc dl = Op.getDebugLoc();
3561 EVT VT = Op.getValueType();
3562 unsigned BitWidth = VT.getSizeInBits();
3563 assert(Op.getNumOperands() == 3 &&
3564 VT == Op.getOperand(1).getValueType() &&
3567 // Expand into a bunch of logical ops, followed by a select_cc.
3568 SDValue Lo = Op.getOperand(0);
3569 SDValue Hi = Op.getOperand(1);
3570 SDValue Amt = Op.getOperand(2);
3571 EVT AmtVT = Amt.getValueType();
3573 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3574 DAG.getConstant(BitWidth, AmtVT), Amt);
3575 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3576 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3577 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3578 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3579 DAG.getConstant(-BitWidth, AmtVT));
3580 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3581 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3582 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3583 Tmp4, Tmp6, ISD::SETLE);
3584 SDValue OutOps[] = { OutLo, OutHi };
3585 return DAG.getMergeValues(OutOps, 2, dl);
3588 //===----------------------------------------------------------------------===//
3589 // Vector related lowering.
3592 /// BuildSplatI - Build a canonical splati of Val with an element size of
3593 /// SplatSize. Cast the result to VT.
3594 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3595 SelectionDAG &DAG, DebugLoc dl) {
3596 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3598 static const EVT VTys[] = { // canonical VT to use for each size.
3599 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3602 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3604 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3608 EVT CanonicalVT = VTys[SplatSize-1];
3610 // Build a canonical splat for this value.
3611 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3612 SmallVector<SDValue, 8> Ops;
3613 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3614 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3615 &Ops[0], Ops.size());
3616 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3619 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3620 /// specified intrinsic ID.
3621 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3622 SelectionDAG &DAG, DebugLoc dl,
3623 EVT DestVT = MVT::Other) {
3624 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3625 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3626 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3629 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3630 /// specified intrinsic ID.
3631 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3632 SDValue Op2, SelectionDAG &DAG,
3633 DebugLoc dl, EVT DestVT = MVT::Other) {
3634 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3635 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3636 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3640 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3641 /// amount. The result has the specified value type.
3642 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3643 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3644 // Force LHS/RHS to be the right type.
3645 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3646 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3649 for (unsigned i = 0; i != 16; ++i)
3651 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3652 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3655 // If this is a case we can't handle, return null and let the default
3656 // expansion code take care of it. If we CAN select this case, and if it
3657 // selects to a single instruction, return Op. Otherwise, if we can codegen
3658 // this case more efficiently than a constant pool load, lower it to the
3659 // sequence of ops that should be used.
3660 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3661 DebugLoc dl = Op.getDebugLoc();
3662 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3663 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3665 // Check if this is a splat of a constant value.
3666 APInt APSplatBits, APSplatUndef;
3667 unsigned SplatBitSize;
3669 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3670 HasAnyUndefs) || SplatBitSize > 32)
3673 unsigned SplatBits = APSplatBits.getZExtValue();
3674 unsigned SplatUndef = APSplatUndef.getZExtValue();
3675 unsigned SplatSize = SplatBitSize / 8;
3677 // First, handle single instruction cases.
3680 if (SplatBits == 0) {
3681 // Canonicalize all zero vectors to be v4i32.
3682 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3683 SDValue Z = DAG.getConstant(0, MVT::i32);
3684 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3685 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3690 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3691 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3693 if (SextVal >= -16 && SextVal <= 15)
3694 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3697 // Two instruction sequences.
3699 // If this value is in the range [-32,30] and is even, use:
3700 // tmp = VSPLTI[bhw], result = add tmp, tmp
3701 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3702 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3703 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3704 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3707 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3708 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3710 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3711 // Make -1 and vspltisw -1:
3712 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3714 // Make the VSLW intrinsic, computing 0x8000_0000.
3715 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3718 // xor by OnesV to invert it.
3719 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3720 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3723 // Check to see if this is a wide variety of vsplti*, binop self cases.
3724 static const signed char SplatCsts[] = {
3725 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3726 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3729 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3730 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3731 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3732 int i = SplatCsts[idx];
3734 // Figure out what shift amount will be used by altivec if shifted by i in
3736 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3738 // vsplti + shl self.
3739 if (SextVal == (i << (int)TypeShiftAmt)) {
3740 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3741 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3742 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3743 Intrinsic::ppc_altivec_vslw
3745 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3746 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3749 // vsplti + srl self.
3750 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3751 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3752 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3753 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3754 Intrinsic::ppc_altivec_vsrw
3756 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3757 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3760 // vsplti + sra self.
3761 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3762 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3763 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3764 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3765 Intrinsic::ppc_altivec_vsraw
3767 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3768 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3771 // vsplti + rol self.
3772 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3773 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3774 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3775 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3776 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3777 Intrinsic::ppc_altivec_vrlw
3779 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3780 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3783 // t = vsplti c, result = vsldoi t, t, 1
3784 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3785 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3786 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3788 // t = vsplti c, result = vsldoi t, t, 2
3789 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3790 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3791 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3793 // t = vsplti c, result = vsldoi t, t, 3
3794 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3795 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3796 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3800 // Three instruction sequences.
3802 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3803 if (SextVal >= 0 && SextVal <= 31) {
3804 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3805 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3806 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3807 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3809 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3810 if (SextVal >= -31 && SextVal <= 0) {
3811 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3812 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3813 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3814 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3820 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3821 /// the specified operations to build the shuffle.
3822 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3823 SDValue RHS, SelectionDAG &DAG,
3825 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3826 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3827 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3830 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3842 if (OpNum == OP_COPY) {
3843 if (LHSID == (1*9+2)*9+3) return LHS;
3844 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3848 SDValue OpLHS, OpRHS;
3849 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3850 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3854 default: llvm_unreachable("Unknown i32 permute!");
3856 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3857 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3858 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3859 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3862 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3863 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3864 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3865 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3868 for (unsigned i = 0; i != 16; ++i)
3869 ShufIdxs[i] = (i&3)+0;
3872 for (unsigned i = 0; i != 16; ++i)
3873 ShufIdxs[i] = (i&3)+4;
3876 for (unsigned i = 0; i != 16; ++i)
3877 ShufIdxs[i] = (i&3)+8;
3880 for (unsigned i = 0; i != 16; ++i)
3881 ShufIdxs[i] = (i&3)+12;
3884 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
3886 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
3888 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
3890 EVT VT = OpLHS.getValueType();
3891 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
3892 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
3893 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
3894 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3897 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3898 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3899 /// return the code it can be lowered into. Worst case, it can always be
3900 /// lowered into a vperm.
3901 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
3902 SelectionDAG &DAG) {
3903 DebugLoc dl = Op.getDebugLoc();
3904 SDValue V1 = Op.getOperand(0);
3905 SDValue V2 = Op.getOperand(1);
3906 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
3907 EVT VT = Op.getValueType();
3909 // Cases that are handled by instructions that take permute immediates
3910 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3911 // selected by the instruction selector.
3912 if (V2.getOpcode() == ISD::UNDEF) {
3913 if (PPC::isSplatShuffleMask(SVOp, 1) ||
3914 PPC::isSplatShuffleMask(SVOp, 2) ||
3915 PPC::isSplatShuffleMask(SVOp, 4) ||
3916 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
3917 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
3918 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
3919 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
3920 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
3921 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
3922 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
3923 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
3924 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
3929 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3930 // and produce a fixed permutation. If any of these match, do not lower to
3932 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
3933 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
3934 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
3935 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
3936 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
3937 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
3938 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
3939 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
3940 PPC::isVMRGHShuffleMask(SVOp, 4, false))
3943 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3944 // perfect shuffle table to emit an optimal matching sequence.
3945 SmallVector<int, 16> PermMask;
3946 SVOp->getMask(PermMask);
3948 unsigned PFIndexes[4];
3949 bool isFourElementShuffle = true;
3950 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3951 unsigned EltNo = 8; // Start out undef.
3952 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3953 if (PermMask[i*4+j] < 0)
3954 continue; // Undef, ignore it.
3956 unsigned ByteSource = PermMask[i*4+j];
3957 if ((ByteSource & 3) != j) {
3958 isFourElementShuffle = false;
3963 EltNo = ByteSource/4;
3964 } else if (EltNo != ByteSource/4) {
3965 isFourElementShuffle = false;
3969 PFIndexes[i] = EltNo;
3972 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3973 // perfect shuffle vector to determine if it is cost effective to do this as
3974 // discrete instructions, or whether we should use a vperm.
3975 if (isFourElementShuffle) {
3976 // Compute the index in the perfect shuffle table.
3977 unsigned PFTableIndex =
3978 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3980 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3981 unsigned Cost = (PFEntry >> 30);
3983 // Determining when to avoid vperm is tricky. Many things affect the cost
3984 // of vperm, particularly how many times the perm mask needs to be computed.
3985 // For example, if the perm mask can be hoisted out of a loop or is already
3986 // used (perhaps because there are multiple permutes with the same shuffle
3987 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3988 // the loop requires an extra register.
3990 // As a compromise, we only emit discrete instructions if the shuffle can be
3991 // generated in 3 or fewer operations. When we have loop information
3992 // available, if this block is within a loop, we should avoid using vperm
3993 // for 3-operation perms and use a constant pool load instead.
3995 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3998 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3999 // vector that will get spilled to the constant pool.
4000 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4002 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4003 // that it is in input element units, not in bytes. Convert now.
4004 EVT EltVT = V1.getValueType().getVectorElementType();
4005 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4007 SmallVector<SDValue, 16> ResultMask;
4008 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4009 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4011 for (unsigned j = 0; j != BytesPerElement; ++j)
4012 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4016 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4017 &ResultMask[0], ResultMask.size());
4018 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4021 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4022 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4023 /// information about the intrinsic.
4024 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4026 unsigned IntrinsicID =
4027 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4030 switch (IntrinsicID) {
4031 default: return false;
4032 // Comparison predicates.
4033 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4034 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4035 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4036 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4037 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4038 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4039 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4040 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4041 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4042 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4043 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4044 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4045 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4047 // Normal Comparisons.
4048 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4049 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4050 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4051 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4052 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4053 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4054 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4055 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4056 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4057 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4058 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4059 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4060 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4065 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4066 /// lower, do it, otherwise return null.
4067 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4068 SelectionDAG &DAG) {
4069 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4070 // opcode number of the comparison.
4071 DebugLoc dl = Op.getDebugLoc();
4074 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4075 return SDValue(); // Don't custom lower most intrinsics.
4077 // If this is a non-dot comparison, make the VCMP node and we are done.
4079 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4080 Op.getOperand(1), Op.getOperand(2),
4081 DAG.getConstant(CompareOpc, MVT::i32));
4082 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
4085 // Create the PPCISD altivec 'dot' comparison node.
4087 Op.getOperand(2), // LHS
4088 Op.getOperand(3), // RHS
4089 DAG.getConstant(CompareOpc, MVT::i32)
4091 std::vector<EVT> VTs;
4092 VTs.push_back(Op.getOperand(2).getValueType());
4093 VTs.push_back(MVT::Flag);
4094 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4096 // Now that we have the comparison, emit a copy from the CR to a GPR.
4097 // This is flagged to the above dot comparison.
4098 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4099 DAG.getRegister(PPC::CR6, MVT::i32),
4100 CompNode.getValue(1));
4102 // Unpack the result based on how the target uses it.
4103 unsigned BitNo; // Bit # of CR6.
4104 bool InvertBit; // Invert result?
4105 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4106 default: // Can't happen, don't crash on invalid number though.
4107 case 0: // Return the value of the EQ bit of CR6.
4108 BitNo = 0; InvertBit = false;
4110 case 1: // Return the inverted value of the EQ bit of CR6.
4111 BitNo = 0; InvertBit = true;
4113 case 2: // Return the value of the LT bit of CR6.
4114 BitNo = 2; InvertBit = false;
4116 case 3: // Return the inverted value of the LT bit of CR6.
4117 BitNo = 2; InvertBit = true;
4121 // Shift the bit into the low position.
4122 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4123 DAG.getConstant(8-(3-BitNo), MVT::i32));
4125 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4126 DAG.getConstant(1, MVT::i32));
4128 // If we are supposed to, toggle the bit.
4130 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4131 DAG.getConstant(1, MVT::i32));
4135 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4136 SelectionDAG &DAG) {
4137 DebugLoc dl = Op.getDebugLoc();
4138 // Create a stack slot that is 16-byte aligned.
4139 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4140 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
4141 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4142 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4144 // Store the input value into Value#0 of the stack slot.
4145 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4146 Op.getOperand(0), FIdx, NULL, 0);
4148 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0);
4151 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
4152 DebugLoc dl = Op.getDebugLoc();
4153 if (Op.getValueType() == MVT::v4i32) {
4154 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4156 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4157 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4159 SDValue RHSSwap = // = vrlw RHS, 16
4160 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4162 // Shrinkify inputs to v8i16.
4163 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
4164 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
4165 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
4167 // Low parts multiplied together, generating 32-bit results (we ignore the
4169 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4170 LHS, RHS, DAG, dl, MVT::v4i32);
4172 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4173 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4174 // Shift the high parts up 16 bits.
4175 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4177 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4178 } else if (Op.getValueType() == MVT::v8i16) {
4179 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4181 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4183 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4184 LHS, RHS, Zero, DAG, dl);
4185 } else if (Op.getValueType() == MVT::v16i8) {
4186 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4188 // Multiply the even 8-bit parts, producing 16-bit sums.
4189 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4190 LHS, RHS, DAG, dl, MVT::v8i16);
4191 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
4193 // Multiply the odd 8-bit parts, producing 16-bit sums.
4194 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4195 LHS, RHS, DAG, dl, MVT::v8i16);
4196 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
4198 // Merge the results together.
4200 for (unsigned i = 0; i != 8; ++i) {
4202 Ops[i*2+1] = 2*i+1+16;
4204 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4206 llvm_unreachable("Unknown mul to lower!");
4210 /// LowerOperation - Provide custom lowering hooks for some operations.
4212 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4213 switch (Op.getOpcode()) {
4214 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4215 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4216 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4217 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4218 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4219 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4220 case ISD::SETCC: return LowerSETCC(Op, DAG);
4221 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4223 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4224 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4227 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4228 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4230 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4231 case ISD::DYNAMIC_STACKALLOC:
4232 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4234 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4235 case ISD::FP_TO_UINT:
4236 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4238 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4239 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4241 // Lower 64-bit shifts.
4242 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4243 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4244 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4246 // Vector-related lowering.
4247 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4248 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4249 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4250 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4251 case ISD::MUL: return LowerMUL(Op, DAG);
4253 // Frame & Return address.
4254 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4255 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4260 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4261 SmallVectorImpl<SDValue>&Results,
4262 SelectionDAG &DAG) {
4263 DebugLoc dl = N->getDebugLoc();
4264 switch (N->getOpcode()) {
4266 assert(false && "Do not know how to custom type legalize this operation!");
4268 case ISD::FP_ROUND_INREG: {
4269 assert(N->getValueType(0) == MVT::ppcf128);
4270 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4271 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4272 MVT::f64, N->getOperand(0),
4273 DAG.getIntPtrConstant(0));
4274 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4275 MVT::f64, N->getOperand(0),
4276 DAG.getIntPtrConstant(1));
4278 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4279 // of the long double, and puts FPSCR back the way it was. We do not
4280 // actually model FPSCR.
4281 std::vector<EVT> NodeTys;
4282 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4284 NodeTys.push_back(MVT::f64); // Return register
4285 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
4286 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4287 MFFSreg = Result.getValue(0);
4288 InFlag = Result.getValue(1);
4291 NodeTys.push_back(MVT::Flag); // Returns a flag
4292 Ops[0] = DAG.getConstant(31, MVT::i32);
4294 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4295 InFlag = Result.getValue(0);
4298 NodeTys.push_back(MVT::Flag); // Returns a flag
4299 Ops[0] = DAG.getConstant(30, MVT::i32);
4301 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4302 InFlag = Result.getValue(0);
4305 NodeTys.push_back(MVT::f64); // result of add
4306 NodeTys.push_back(MVT::Flag); // Returns a flag
4310 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4311 FPreg = Result.getValue(0);
4312 InFlag = Result.getValue(1);
4315 NodeTys.push_back(MVT::f64);
4316 Ops[0] = DAG.getConstant(1, MVT::i32);
4320 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4321 FPreg = Result.getValue(0);
4323 // We know the low half is about to be thrown away, so just use something
4325 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4329 case ISD::FP_TO_SINT:
4330 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4336 //===----------------------------------------------------------------------===//
4337 // Other Lowering Code
4338 //===----------------------------------------------------------------------===//
4341 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4342 bool is64bit, unsigned BinOpcode) const {
4343 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4344 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4346 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4347 MachineFunction *F = BB->getParent();
4348 MachineFunction::iterator It = BB;
4351 unsigned dest = MI->getOperand(0).getReg();
4352 unsigned ptrA = MI->getOperand(1).getReg();
4353 unsigned ptrB = MI->getOperand(2).getReg();
4354 unsigned incr = MI->getOperand(3).getReg();
4355 DebugLoc dl = MI->getDebugLoc();
4357 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4358 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4359 F->insert(It, loopMBB);
4360 F->insert(It, exitMBB);
4361 exitMBB->transferSuccessors(BB);
4363 MachineRegisterInfo &RegInfo = F->getRegInfo();
4364 unsigned TmpReg = (!BinOpcode) ? incr :
4365 RegInfo.createVirtualRegister(
4366 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4367 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4371 // fallthrough --> loopMBB
4372 BB->addSuccessor(loopMBB);
4375 // l[wd]arx dest, ptr
4376 // add r0, dest, incr
4377 // st[wd]cx. r0, ptr
4379 // fallthrough --> exitMBB
4381 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4382 .addReg(ptrA).addReg(ptrB);
4384 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4385 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4386 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4387 BuildMI(BB, dl, TII->get(PPC::BCC))
4388 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4389 BB->addSuccessor(loopMBB);
4390 BB->addSuccessor(exitMBB);
4399 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4400 MachineBasicBlock *BB,
4401 bool is8bit, // operation
4402 unsigned BinOpcode) const {
4403 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4404 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4405 // In 64 bit mode we have to use 64 bits for addresses, even though the
4406 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4407 // registers without caring whether they're 32 or 64, but here we're
4408 // doing actual arithmetic on the addresses.
4409 bool is64bit = PPCSubTarget.isPPC64();
4411 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4412 MachineFunction *F = BB->getParent();
4413 MachineFunction::iterator It = BB;
4416 unsigned dest = MI->getOperand(0).getReg();
4417 unsigned ptrA = MI->getOperand(1).getReg();
4418 unsigned ptrB = MI->getOperand(2).getReg();
4419 unsigned incr = MI->getOperand(3).getReg();
4420 DebugLoc dl = MI->getDebugLoc();
4422 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4423 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4424 F->insert(It, loopMBB);
4425 F->insert(It, exitMBB);
4426 exitMBB->transferSuccessors(BB);
4428 MachineRegisterInfo &RegInfo = F->getRegInfo();
4429 const TargetRegisterClass *RC =
4430 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4431 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4432 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4433 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4434 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4435 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4436 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4437 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4438 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4439 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4440 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4441 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4442 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4444 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4448 // fallthrough --> loopMBB
4449 BB->addSuccessor(loopMBB);
4451 // The 4-byte load must be aligned, while a char or short may be
4452 // anywhere in the word. Hence all this nasty bookkeeping code.
4453 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4454 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4455 // xori shift, shift1, 24 [16]
4456 // rlwinm ptr, ptr1, 0, 0, 29
4457 // slw incr2, incr, shift
4458 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4459 // slw mask, mask2, shift
4461 // lwarx tmpDest, ptr
4462 // add tmp, tmpDest, incr2
4463 // andc tmp2, tmpDest, mask
4464 // and tmp3, tmp, mask
4465 // or tmp4, tmp3, tmp2
4468 // fallthrough --> exitMBB
4469 // srw dest, tmpDest, shift
4471 if (ptrA!=PPC::R0) {
4472 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4473 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4474 .addReg(ptrA).addReg(ptrB);
4478 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4479 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4480 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4481 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4483 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4484 .addReg(Ptr1Reg).addImm(0).addImm(61);
4486 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4487 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4488 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4489 .addReg(incr).addReg(ShiftReg);
4491 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4493 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4494 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4496 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4497 .addReg(Mask2Reg).addReg(ShiftReg);
4500 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4501 .addReg(PPC::R0).addReg(PtrReg);
4503 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4504 .addReg(Incr2Reg).addReg(TmpDestReg);
4505 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4506 .addReg(TmpDestReg).addReg(MaskReg);
4507 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4508 .addReg(TmpReg).addReg(MaskReg);
4509 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4510 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4511 BuildMI(BB, dl, TII->get(PPC::STWCX))
4512 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4513 BuildMI(BB, dl, TII->get(PPC::BCC))
4514 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4515 BB->addSuccessor(loopMBB);
4516 BB->addSuccessor(exitMBB);
4521 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4526 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4527 MachineBasicBlock *BB,
4528 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
4529 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4531 // To "insert" these instructions we actually have to insert their
4532 // control-flow patterns.
4533 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4534 MachineFunction::iterator It = BB;
4537 MachineFunction *F = BB->getParent();
4539 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4540 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4541 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4542 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4543 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4545 // The incoming instruction knows the destination vreg to set, the
4546 // condition code register to branch on, the true/false values to
4547 // select between, and a branch opcode to use.
4552 // cmpTY ccX, r1, r2
4554 // fallthrough --> copy0MBB
4555 MachineBasicBlock *thisMBB = BB;
4556 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4557 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4558 unsigned SelectPred = MI->getOperand(4).getImm();
4559 DebugLoc dl = MI->getDebugLoc();
4560 BuildMI(BB, dl, TII->get(PPC::BCC))
4561 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4562 F->insert(It, copy0MBB);
4563 F->insert(It, sinkMBB);
4564 // Update machine-CFG edges by first adding all successors of the current
4565 // block to the new block which will contain the Phi node for the select.
4566 // Also inform sdisel of the edge changes.
4567 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
4568 E = BB->succ_end(); I != E; ++I) {
4569 EM->insert(std::make_pair(*I, sinkMBB));
4570 sinkMBB->addSuccessor(*I);
4572 // Next, remove all successors of the current block, and add the true
4573 // and fallthrough blocks as its successors.
4574 while (!BB->succ_empty())
4575 BB->removeSuccessor(BB->succ_begin());
4576 // Next, add the true and fallthrough blocks as its successors.
4577 BB->addSuccessor(copy0MBB);
4578 BB->addSuccessor(sinkMBB);
4581 // %FalseValue = ...
4582 // # fallthrough to sinkMBB
4585 // Update machine-CFG edges
4586 BB->addSuccessor(sinkMBB);
4589 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4592 BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4593 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4594 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4596 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4597 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4598 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4599 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4600 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4601 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4602 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4603 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4605 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4606 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4607 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4608 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4609 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4610 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4611 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4612 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4614 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4615 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4616 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4617 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4618 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4619 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4620 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4621 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4623 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4624 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4625 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4626 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4627 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4628 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4629 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4630 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4632 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4633 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4634 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4635 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4636 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4637 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4638 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4639 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4641 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4642 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4643 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4644 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4645 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4646 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4647 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4648 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4650 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4651 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4652 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4653 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4654 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4655 BB = EmitAtomicBinary(MI, BB, false, 0);
4656 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4657 BB = EmitAtomicBinary(MI, BB, true, 0);
4659 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4660 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4661 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4663 unsigned dest = MI->getOperand(0).getReg();
4664 unsigned ptrA = MI->getOperand(1).getReg();
4665 unsigned ptrB = MI->getOperand(2).getReg();
4666 unsigned oldval = MI->getOperand(3).getReg();
4667 unsigned newval = MI->getOperand(4).getReg();
4668 DebugLoc dl = MI->getDebugLoc();
4670 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4671 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4672 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4673 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4674 F->insert(It, loop1MBB);
4675 F->insert(It, loop2MBB);
4676 F->insert(It, midMBB);
4677 F->insert(It, exitMBB);
4678 exitMBB->transferSuccessors(BB);
4682 // fallthrough --> loopMBB
4683 BB->addSuccessor(loop1MBB);
4686 // l[wd]arx dest, ptr
4687 // cmp[wd] dest, oldval
4690 // st[wd]cx. newval, ptr
4694 // st[wd]cx. dest, ptr
4697 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4698 .addReg(ptrA).addReg(ptrB);
4699 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4700 .addReg(oldval).addReg(dest);
4701 BuildMI(BB, dl, TII->get(PPC::BCC))
4702 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4703 BB->addSuccessor(loop2MBB);
4704 BB->addSuccessor(midMBB);
4707 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4708 .addReg(newval).addReg(ptrA).addReg(ptrB);
4709 BuildMI(BB, dl, TII->get(PPC::BCC))
4710 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4711 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4712 BB->addSuccessor(loop1MBB);
4713 BB->addSuccessor(exitMBB);
4716 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4717 .addReg(dest).addReg(ptrA).addReg(ptrB);
4718 BB->addSuccessor(exitMBB);
4723 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4724 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4725 // We must use 64-bit registers for addresses when targeting 64-bit,
4726 // since we're actually doing arithmetic on them. Other registers
4728 bool is64bit = PPCSubTarget.isPPC64();
4729 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4731 unsigned dest = MI->getOperand(0).getReg();
4732 unsigned ptrA = MI->getOperand(1).getReg();
4733 unsigned ptrB = MI->getOperand(2).getReg();
4734 unsigned oldval = MI->getOperand(3).getReg();
4735 unsigned newval = MI->getOperand(4).getReg();
4736 DebugLoc dl = MI->getDebugLoc();
4738 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4739 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4740 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4741 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4742 F->insert(It, loop1MBB);
4743 F->insert(It, loop2MBB);
4744 F->insert(It, midMBB);
4745 F->insert(It, exitMBB);
4746 exitMBB->transferSuccessors(BB);
4748 MachineRegisterInfo &RegInfo = F->getRegInfo();
4749 const TargetRegisterClass *RC =
4750 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4751 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4752 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4753 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4754 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4755 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4756 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4757 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4758 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4759 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4760 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4761 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4762 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4763 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4764 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4766 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4769 // fallthrough --> loopMBB
4770 BB->addSuccessor(loop1MBB);
4772 // The 4-byte load must be aligned, while a char or short may be
4773 // anywhere in the word. Hence all this nasty bookkeeping code.
4774 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4775 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4776 // xori shift, shift1, 24 [16]
4777 // rlwinm ptr, ptr1, 0, 0, 29
4778 // slw newval2, newval, shift
4779 // slw oldval2, oldval,shift
4780 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4781 // slw mask, mask2, shift
4782 // and newval3, newval2, mask
4783 // and oldval3, oldval2, mask
4785 // lwarx tmpDest, ptr
4786 // and tmp, tmpDest, mask
4787 // cmpw tmp, oldval3
4790 // andc tmp2, tmpDest, mask
4791 // or tmp4, tmp2, newval3
4796 // stwcx. tmpDest, ptr
4798 // srw dest, tmpDest, shift
4799 if (ptrA!=PPC::R0) {
4800 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4801 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4802 .addReg(ptrA).addReg(ptrB);
4806 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4807 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4808 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4809 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4811 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4812 .addReg(Ptr1Reg).addImm(0).addImm(61);
4814 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4815 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4816 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4817 .addReg(newval).addReg(ShiftReg);
4818 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4819 .addReg(oldval).addReg(ShiftReg);
4821 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4823 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4824 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4825 .addReg(Mask3Reg).addImm(65535);
4827 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4828 .addReg(Mask2Reg).addReg(ShiftReg);
4829 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
4830 .addReg(NewVal2Reg).addReg(MaskReg);
4831 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
4832 .addReg(OldVal2Reg).addReg(MaskReg);
4835 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4836 .addReg(PPC::R0).addReg(PtrReg);
4837 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
4838 .addReg(TmpDestReg).addReg(MaskReg);
4839 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
4840 .addReg(TmpReg).addReg(OldVal3Reg);
4841 BuildMI(BB, dl, TII->get(PPC::BCC))
4842 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4843 BB->addSuccessor(loop2MBB);
4844 BB->addSuccessor(midMBB);
4847 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
4848 .addReg(TmpDestReg).addReg(MaskReg);
4849 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
4850 .addReg(Tmp2Reg).addReg(NewVal3Reg);
4851 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4852 .addReg(PPC::R0).addReg(PtrReg);
4853 BuildMI(BB, dl, TII->get(PPC::BCC))
4854 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4855 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4856 BB->addSuccessor(loop1MBB);
4857 BB->addSuccessor(exitMBB);
4860 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4861 .addReg(PPC::R0).addReg(PtrReg);
4862 BB->addSuccessor(exitMBB);
4867 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4869 llvm_unreachable("Unexpected instr type to insert");
4872 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4876 //===----------------------------------------------------------------------===//
4877 // Target Optimization Hooks
4878 //===----------------------------------------------------------------------===//
4880 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4881 DAGCombinerInfo &DCI) const {
4882 TargetMachine &TM = getTargetMachine();
4883 SelectionDAG &DAG = DCI.DAG;
4884 DebugLoc dl = N->getDebugLoc();
4885 switch (N->getOpcode()) {
4888 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4889 if (C->getZExtValue() == 0) // 0 << V -> 0.
4890 return N->getOperand(0);
4894 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4895 if (C->getZExtValue() == 0) // 0 >>u V -> 0.
4896 return N->getOperand(0);
4900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4901 if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
4902 C->isAllOnesValue()) // -1 >>s V -> -1.
4903 return N->getOperand(0);
4907 case ISD::SINT_TO_FP:
4908 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4909 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4910 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4911 // We allow the src/dst to be either f32/f64, but the intermediate
4912 // type must be i64.
4913 if (N->getOperand(0).getValueType() == MVT::i64 &&
4914 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4915 SDValue Val = N->getOperand(0).getOperand(0);
4916 if (Val.getValueType() == MVT::f32) {
4917 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4918 DCI.AddToWorklist(Val.getNode());
4921 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
4922 DCI.AddToWorklist(Val.getNode());
4923 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
4924 DCI.AddToWorklist(Val.getNode());
4925 if (N->getValueType(0) == MVT::f32) {
4926 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
4927 DAG.getIntPtrConstant(0));
4928 DCI.AddToWorklist(Val.getNode());
4931 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4932 // If the intermediate type is i32, we can avoid the load/store here
4939 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4940 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4941 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4942 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4943 N->getOperand(1).getValueType() == MVT::i32 &&
4944 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4945 SDValue Val = N->getOperand(1).getOperand(0);
4946 if (Val.getValueType() == MVT::f32) {
4947 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4948 DCI.AddToWorklist(Val.getNode());
4950 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
4951 DCI.AddToWorklist(Val.getNode());
4953 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
4954 N->getOperand(2), N->getOperand(3));
4955 DCI.AddToWorklist(Val.getNode());
4959 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4960 if (cast<StoreSDNode>(N)->isUnindexed() &&
4961 N->getOperand(1).getOpcode() == ISD::BSWAP &&
4962 N->getOperand(1).getNode()->hasOneUse() &&
4963 (N->getOperand(1).getValueType() == MVT::i32 ||
4964 N->getOperand(1).getValueType() == MVT::i16)) {
4965 SDValue BSwapOp = N->getOperand(1).getOperand(0);
4966 // Do an any-extend to 32-bits if this is a half-word input.
4967 if (BSwapOp.getValueType() == MVT::i16)
4968 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
4971 N->getOperand(0), BSwapOp, N->getOperand(2),
4972 DAG.getValueType(N->getOperand(1).getValueType())
4975 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
4976 Ops, array_lengthof(Ops),
4977 cast<StoreSDNode>(N)->getMemoryVT(),
4978 cast<StoreSDNode>(N)->getMemOperand());
4982 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4983 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
4984 N->getOperand(0).hasOneUse() &&
4985 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4986 SDValue Load = N->getOperand(0);
4987 LoadSDNode *LD = cast<LoadSDNode>(Load);
4988 // Create the byte-swapping load.
4990 LD->getChain(), // Chain
4991 LD->getBasePtr(), // Ptr
4992 DAG.getValueType(N->getValueType(0)) // VT
4995 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
4996 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
4997 LD->getMemoryVT(), LD->getMemOperand());
4999 // If this is an i16 load, insert the truncate.
5000 SDValue ResVal = BSLoad;
5001 if (N->getValueType(0) == MVT::i16)
5002 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5004 // First, combine the bswap away. This makes the value produced by the
5006 DCI.CombineTo(N, ResVal);
5008 // Next, combine the load away, we give it a bogus result value but a real
5009 // chain result. The result value is dead because the bswap is dead.
5010 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5012 // Return N so it doesn't get rechecked!
5013 return SDValue(N, 0);
5017 case PPCISD::VCMP: {
5018 // If a VCMPo node already exists with exactly the same operands as this
5019 // node, use its result instead of this node (VCMPo computes both a CR6 and
5020 // a normal output).
5022 if (!N->getOperand(0).hasOneUse() &&
5023 !N->getOperand(1).hasOneUse() &&
5024 !N->getOperand(2).hasOneUse()) {
5026 // Scan all of the users of the LHS, looking for VCMPo's that match.
5027 SDNode *VCMPoNode = 0;
5029 SDNode *LHSN = N->getOperand(0).getNode();
5030 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5032 if (UI->getOpcode() == PPCISD::VCMPo &&
5033 UI->getOperand(1) == N->getOperand(1) &&
5034 UI->getOperand(2) == N->getOperand(2) &&
5035 UI->getOperand(0) == N->getOperand(0)) {
5040 // If there is no VCMPo node, or if the flag value has a single use, don't
5042 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5045 // Look at the (necessarily single) use of the flag value. If it has a
5046 // chain, this transformation is more complex. Note that multiple things
5047 // could use the value result, which we should ignore.
5048 SDNode *FlagUser = 0;
5049 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5050 FlagUser == 0; ++UI) {
5051 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5053 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5054 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5061 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5062 // give up for right now.
5063 if (FlagUser->getOpcode() == PPCISD::MFCR)
5064 return SDValue(VCMPoNode, 0);
5069 // If this is a branch on an altivec predicate comparison, lower this so
5070 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5071 // lowering is done pre-legalize, because the legalizer lowers the predicate
5072 // compare down to code that is difficult to reassemble.
5073 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5074 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5078 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5079 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5080 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5081 assert(isDot && "Can't compare against a vector result!");
5083 // If this is a comparison against something other than 0/1, then we know
5084 // that the condition is never/always true.
5085 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5086 if (Val != 0 && Val != 1) {
5087 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5088 return N->getOperand(0);
5089 // Always !=, turn it into an unconditional branch.
5090 return DAG.getNode(ISD::BR, dl, MVT::Other,
5091 N->getOperand(0), N->getOperand(4));
5094 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5096 // Create the PPCISD altivec 'dot' comparison node.
5097 std::vector<EVT> VTs;
5099 LHS.getOperand(2), // LHS of compare
5100 LHS.getOperand(3), // RHS of compare
5101 DAG.getConstant(CompareOpc, MVT::i32)
5103 VTs.push_back(LHS.getOperand(2).getValueType());
5104 VTs.push_back(MVT::Flag);
5105 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5107 // Unpack the result based on how the target uses it.
5108 PPC::Predicate CompOpc;
5109 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5110 default: // Can't happen, don't crash on invalid number though.
5111 case 0: // Branch on the value of the EQ bit of CR6.
5112 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5114 case 1: // Branch on the inverted value of the EQ bit of CR6.
5115 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5117 case 2: // Branch on the value of the LT bit of CR6.
5118 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5120 case 3: // Branch on the inverted value of the LT bit of CR6.
5121 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5125 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5126 DAG.getConstant(CompOpc, MVT::i32),
5127 DAG.getRegister(PPC::CR6, MVT::i32),
5128 N->getOperand(4), CompNode.getValue(1));
5137 //===----------------------------------------------------------------------===//
5138 // Inline Assembly Support
5139 //===----------------------------------------------------------------------===//
5141 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5145 const SelectionDAG &DAG,
5146 unsigned Depth) const {
5147 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5148 switch (Op.getOpcode()) {
5150 case PPCISD::LBRX: {
5151 // lhbrx is known to have the top bits cleared out.
5152 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5153 KnownZero = 0xFFFF0000;
5156 case ISD::INTRINSIC_WO_CHAIN: {
5157 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5159 case Intrinsic::ppc_altivec_vcmpbfp_p:
5160 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5161 case Intrinsic::ppc_altivec_vcmpequb_p:
5162 case Intrinsic::ppc_altivec_vcmpequh_p:
5163 case Intrinsic::ppc_altivec_vcmpequw_p:
5164 case Intrinsic::ppc_altivec_vcmpgefp_p:
5165 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5166 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5167 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5168 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5169 case Intrinsic::ppc_altivec_vcmpgtub_p:
5170 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5171 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5172 KnownZero = ~1U; // All bits but the low one are known to be zero.
5180 /// getConstraintType - Given a constraint, return the type of
5181 /// constraint it is for this target.
5182 PPCTargetLowering::ConstraintType
5183 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5184 if (Constraint.size() == 1) {
5185 switch (Constraint[0]) {
5192 return C_RegisterClass;
5195 return TargetLowering::getConstraintType(Constraint);
5198 std::pair<unsigned, const TargetRegisterClass*>
5199 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5201 if (Constraint.size() == 1) {
5202 // GCC RS6000 Constraint Letters
5203 switch (Constraint[0]) {
5206 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5207 return std::make_pair(0U, PPC::G8RCRegisterClass);
5208 return std::make_pair(0U, PPC::GPRCRegisterClass);
5211 return std::make_pair(0U, PPC::F4RCRegisterClass);
5212 else if (VT == MVT::f64)
5213 return std::make_pair(0U, PPC::F8RCRegisterClass);
5216 return std::make_pair(0U, PPC::VRRCRegisterClass);
5218 return std::make_pair(0U, PPC::CRRCRegisterClass);
5222 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5226 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5227 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
5228 /// it means one of the asm constraint of the inline asm instruction being
5229 /// processed is 'm'.
5230 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5232 std::vector<SDValue>&Ops,
5233 SelectionDAG &DAG) const {
5234 SDValue Result(0,0);
5245 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5246 if (!CST) return; // Must be an immediate to match.
5247 unsigned Value = CST->getZExtValue();
5249 default: llvm_unreachable("Unknown constraint letter!");
5250 case 'I': // "I" is a signed 16-bit constant.
5251 if ((short)Value == (int)Value)
5252 Result = DAG.getTargetConstant(Value, Op.getValueType());
5254 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5255 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5256 if ((short)Value == 0)
5257 Result = DAG.getTargetConstant(Value, Op.getValueType());
5259 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5260 if ((Value >> 16) == 0)
5261 Result = DAG.getTargetConstant(Value, Op.getValueType());
5263 case 'M': // "M" is a constant that is greater than 31.
5265 Result = DAG.getTargetConstant(Value, Op.getValueType());
5267 case 'N': // "N" is a positive constant that is an exact power of two.
5268 if ((int)Value > 0 && isPowerOf2_32(Value))
5269 Result = DAG.getTargetConstant(Value, Op.getValueType());
5271 case 'O': // "O" is the constant zero.
5273 Result = DAG.getTargetConstant(Value, Op.getValueType());
5275 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5276 if ((short)-Value == (int)-Value)
5277 Result = DAG.getTargetConstant(Value, Op.getValueType());
5284 if (Result.getNode()) {
5285 Ops.push_back(Result);
5289 // Handle standard constraint letters.
5290 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
5293 // isLegalAddressingMode - Return true if the addressing mode represented
5294 // by AM is legal for this target, for a load/store of the specified type.
5295 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5296 const Type *Ty) const {
5297 // FIXME: PPC does not allow r+i addressing modes for vectors!
5299 // PPC allows a sign-extended 16-bit immediate field.
5300 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5303 // No global is ever allowed as a base.
5307 // PPC only support r+r,
5309 case 0: // "r+i" or just "i", depending on HasBaseReg.
5312 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5314 // Otherwise we have r+r or r+i.
5317 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5319 // Allow 2*r as r+r.
5322 // No other scales are supported.
5329 /// isLegalAddressImmediate - Return true if the integer value can be used
5330 /// as the offset of the target addressing mode for load / store of the
5332 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5333 // PPC allows a sign-extended 16-bit immediate field.
5334 return (V > -(1 << 16) && V < (1 << 16)-1);
5337 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5341 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5342 DebugLoc dl = Op.getDebugLoc();
5343 // Depths > 0 not supported yet!
5344 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5347 MachineFunction &MF = DAG.getMachineFunction();
5348 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5350 // Just load the return address off the stack.
5351 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5353 // Make sure the function really does not optimize away the store of the RA
5355 FuncInfo->setLRStoreRequired();
5356 return DAG.getLoad(getPointerTy(), dl,
5357 DAG.getEntryNode(), RetAddrFI, NULL, 0);
5360 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5361 DebugLoc dl = Op.getDebugLoc();
5362 // Depths > 0 not supported yet!
5363 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5366 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5367 bool isPPC64 = PtrVT == MVT::i64;
5369 MachineFunction &MF = DAG.getMachineFunction();
5370 MachineFrameInfo *MFI = MF.getFrameInfo();
5371 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
5372 && MFI->getStackSize();
5375 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
5378 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
5383 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5384 // The PowerPC target isn't yet aware of offsets.
5388 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
5389 bool isSrcConst, bool isSrcStr,
5390 SelectionDAG &DAG) const {
5391 if (this->PPCSubTarget.isPPC64()) {