1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPerfectShuffle.h"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/CallingConv.h"
30 #include "llvm/Constants.h"
31 #include "llvm/Function.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/DerivedTypes.h"
41 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
42 CCValAssign::LocInfo &LocInfo,
43 ISD::ArgFlagsTy &ArgFlags,
45 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
56 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
57 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
64 return new TargetLoweringObjectFileELF();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
77 // arguments are at least 4/8 bytes aligned.
78 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4);
80 // Set up the register classes.
81 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
82 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
83 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
85 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
86 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
89 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
91 // PowerPC has pre-inc load and store's.
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
103 // This is used in the ppcf128->int sequence. Note it has different semantics
104 // from FP_ROUND: that rounds to nearest, this rounds to zero.
105 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
107 // PowerPC has no SREM/UREM instructions
108 setOperationAction(ISD::SREM, MVT::i32, Expand);
109 setOperationAction(ISD::UREM, MVT::i32, Expand);
110 setOperationAction(ISD::SREM, MVT::i64, Expand);
111 setOperationAction(ISD::UREM, MVT::i64, Expand);
113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
114 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
118 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
119 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
123 // We don't support sin/cos/sqrt/fmod/pow
124 setOperationAction(ISD::FSIN , MVT::f64, Expand);
125 setOperationAction(ISD::FCOS , MVT::f64, Expand);
126 setOperationAction(ISD::FREM , MVT::f64, Expand);
127 setOperationAction(ISD::FPOW , MVT::f64, Expand);
128 setOperationAction(ISD::FSIN , MVT::f32, Expand);
129 setOperationAction(ISD::FCOS , MVT::f32, Expand);
130 setOperationAction(ISD::FREM , MVT::f32, Expand);
131 setOperationAction(ISD::FPOW , MVT::f32, Expand);
133 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
135 // If we're enabling GP optimizations, use hardware square root
136 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
137 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
138 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
141 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
142 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
144 // PowerPC does not have BSWAP, CTPOP or CTTZ
145 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
146 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
147 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
148 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
149 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
150 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
152 // PowerPC does not have ROTR
153 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
154 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
156 // PowerPC does not have Select
157 setOperationAction(ISD::SELECT, MVT::i32, Expand);
158 setOperationAction(ISD::SELECT, MVT::i64, Expand);
159 setOperationAction(ISD::SELECT, MVT::f32, Expand);
160 setOperationAction(ISD::SELECT, MVT::f64, Expand);
162 // PowerPC wants to turn select_cc of FP into fsel when possible.
163 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
164 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
166 // PowerPC wants to optimize integer setcc a bit
167 setOperationAction(ISD::SETCC, MVT::i32, Custom);
169 // PowerPC does not have BRCOND which requires SetCC
170 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
172 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
174 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
175 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
177 // PowerPC does not have [U|S]INT_TO_FP
178 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
179 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
181 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
182 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
183 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
184 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
186 // We cannot sextinreg(i1). Expand to shifts.
187 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
189 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
190 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
192 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
195 // We want to legalize GlobalAddress and ConstantPool nodes into the
196 // appropriate instructions to materialize the address.
197 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
199 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
200 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
201 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
202 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
203 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
204 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
206 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
209 setOperationAction(ISD::TRAP, MVT::Other, Legal);
211 // TRAMPOLINE is custom lowered.
212 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
214 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
215 setOperationAction(ISD::VASTART , MVT::Other, Custom);
217 // VAARG is custom lowered with the 32-bit SVR4 ABI.
218 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
219 && !TM.getSubtarget<PPCSubtarget>().isPPC64())
220 setOperationAction(ISD::VAARG, MVT::Other, Custom);
222 setOperationAction(ISD::VAARG, MVT::Other, Expand);
224 // Use the default implementation.
225 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
226 setOperationAction(ISD::VAEND , MVT::Other, Expand);
227 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
228 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
229 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
230 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
232 // We want to custom lower some of our intrinsics.
233 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
235 // Comparisons that require checking two conditions.
236 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
243 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
244 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
247 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
249 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
250 // They also have instructions for converting between i64 and fp.
251 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
252 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
253 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
254 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
255 // This is just the low 32 bits of a (signed) fp->i64 conversion.
256 // We cannot do this with Promote because i64 is not a legal type.
257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
259 // FIXME: disable this lowered code. This generates 64-bit register values,
260 // and we don't model the fact that the top part is clobbered by calls. We
261 // need to flag these together so that the value isn't live across a call.
262 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
264 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
265 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
268 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
269 // 64-bit PowerPC implementations can support i64 types directly
270 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
271 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
272 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
273 // 64-bit PowerPC wants to expand i128 shifts itself.
274 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
275 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
276 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
278 // 32-bit PowerPC wants to expand i64 shifts itself.
279 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
280 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
281 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
284 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
285 // First set operation action for all vector types to expand. Then we
286 // will selectively turn on ones that can be effectively codegen'd.
287 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
288 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
289 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
291 // add/sub are legal for all supported vector VT's.
292 setOperationAction(ISD::ADD , VT, Legal);
293 setOperationAction(ISD::SUB , VT, Legal);
295 // We promote all shuffles to v16i8.
296 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
297 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
299 // We promote all non-typed operations to v4i32.
300 setOperationAction(ISD::AND , VT, Promote);
301 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
302 setOperationAction(ISD::OR , VT, Promote);
303 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
304 setOperationAction(ISD::XOR , VT, Promote);
305 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
306 setOperationAction(ISD::LOAD , VT, Promote);
307 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
308 setOperationAction(ISD::SELECT, VT, Promote);
309 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
310 setOperationAction(ISD::STORE, VT, Promote);
311 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
313 // No other operations are legal.
314 setOperationAction(ISD::MUL , VT, Expand);
315 setOperationAction(ISD::SDIV, VT, Expand);
316 setOperationAction(ISD::SREM, VT, Expand);
317 setOperationAction(ISD::UDIV, VT, Expand);
318 setOperationAction(ISD::UREM, VT, Expand);
319 setOperationAction(ISD::FDIV, VT, Expand);
320 setOperationAction(ISD::FNEG, VT, Expand);
321 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
323 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
324 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
326 setOperationAction(ISD::UDIVREM, VT, Expand);
327 setOperationAction(ISD::SDIVREM, VT, Expand);
328 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
329 setOperationAction(ISD::FPOW, VT, Expand);
330 setOperationAction(ISD::CTPOP, VT, Expand);
331 setOperationAction(ISD::CTLZ, VT, Expand);
332 setOperationAction(ISD::CTTZ, VT, Expand);
335 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
336 // with merges, splats, etc.
337 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
339 setOperationAction(ISD::AND , MVT::v4i32, Legal);
340 setOperationAction(ISD::OR , MVT::v4i32, Legal);
341 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
342 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
343 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
344 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
346 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
347 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
348 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
349 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
351 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
352 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
353 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
354 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
356 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
357 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
359 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
360 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
361 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
362 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
365 setBooleanContents(ZeroOrOneBooleanContent);
367 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
368 setStackPointerRegisterToSaveRestore(PPC::X1);
369 setExceptionPointerRegister(PPC::X3);
370 setExceptionSelectorRegister(PPC::X4);
372 setStackPointerRegisterToSaveRestore(PPC::R1);
373 setExceptionPointerRegister(PPC::R3);
374 setExceptionSelectorRegister(PPC::R4);
377 // We have target-specific dag combine patterns for the following nodes:
378 setTargetDAGCombine(ISD::SINT_TO_FP);
379 setTargetDAGCombine(ISD::STORE);
380 setTargetDAGCombine(ISD::BR_CC);
381 setTargetDAGCombine(ISD::BSWAP);
383 // Darwin long double math library functions have $LDBL128 appended.
384 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
385 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
386 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
387 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
388 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
389 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
390 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
391 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
392 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
393 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
394 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
397 computeRegisterProperties();
400 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
401 /// function arguments in the caller parameter area.
402 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
403 const TargetMachine &TM = getTargetMachine();
404 // Darwin passes everything on 4 byte boundary.
405 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
411 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
414 case PPCISD::FSEL: return "PPCISD::FSEL";
415 case PPCISD::FCFID: return "PPCISD::FCFID";
416 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
417 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
418 case PPCISD::STFIWX: return "PPCISD::STFIWX";
419 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
420 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
421 case PPCISD::VPERM: return "PPCISD::VPERM";
422 case PPCISD::Hi: return "PPCISD::Hi";
423 case PPCISD::Lo: return "PPCISD::Lo";
424 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
425 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
426 case PPCISD::LOAD: return "PPCISD::LOAD";
427 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
428 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
429 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
430 case PPCISD::SRL: return "PPCISD::SRL";
431 case PPCISD::SRA: return "PPCISD::SRA";
432 case PPCISD::SHL: return "PPCISD::SHL";
433 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
434 case PPCISD::STD_32: return "PPCISD::STD_32";
435 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
436 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
437 case PPCISD::NOP: return "PPCISD::NOP";
438 case PPCISD::MTCTR: return "PPCISD::MTCTR";
439 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
440 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
441 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
442 case PPCISD::MFCR: return "PPCISD::MFCR";
443 case PPCISD::VCMP: return "PPCISD::VCMP";
444 case PPCISD::VCMPo: return "PPCISD::VCMPo";
445 case PPCISD::LBRX: return "PPCISD::LBRX";
446 case PPCISD::STBRX: return "PPCISD::STBRX";
447 case PPCISD::LARX: return "PPCISD::LARX";
448 case PPCISD::STCX: return "PPCISD::STCX";
449 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
450 case PPCISD::MFFS: return "PPCISD::MFFS";
451 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
452 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
453 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
454 case PPCISD::MTFSF: return "PPCISD::MTFSF";
455 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
459 MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
463 /// getFunctionAlignment - Return the Log2 alignment of this function.
464 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
465 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
466 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
471 //===----------------------------------------------------------------------===//
472 // Node matching predicates, for use by the tblgen matching code.
473 //===----------------------------------------------------------------------===//
475 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
476 static bool isFloatingPointZero(SDValue Op) {
477 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
478 return CFP->getValueAPF().isZero();
479 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
480 // Maybe this has already been legalized into the constant pool?
481 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
482 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
483 return CFP->getValueAPF().isZero();
488 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
489 /// true if Op is undef or if it matches the specified value.
490 static bool isConstantOrUndef(int Op, int Val) {
491 return Op < 0 || Op == Val;
494 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
495 /// VPKUHUM instruction.
496 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
498 for (unsigned i = 0; i != 16; ++i)
499 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
502 for (unsigned i = 0; i != 8; ++i)
503 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
504 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
510 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
511 /// VPKUWUM instruction.
512 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
514 for (unsigned i = 0; i != 16; i += 2)
515 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
516 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
519 for (unsigned i = 0; i != 8; i += 2)
520 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
521 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
522 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
523 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
529 /// isVMerge - Common function, used to match vmrg* shuffles.
531 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
532 unsigned LHSStart, unsigned RHSStart) {
533 assert(N->getValueType(0) == MVT::v16i8 &&
534 "PPC only supports shuffles by bytes!");
535 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
536 "Unsupported merge size!");
538 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
539 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
540 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
541 LHSStart+j+i*UnitSize) ||
542 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
543 RHSStart+j+i*UnitSize))
549 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
550 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
551 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
554 return isVMerge(N, UnitSize, 8, 24);
555 return isVMerge(N, UnitSize, 8, 8);
558 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
559 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
560 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
563 return isVMerge(N, UnitSize, 0, 16);
564 return isVMerge(N, UnitSize, 0, 0);
568 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
569 /// amount, otherwise return -1.
570 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
571 assert(N->getValueType(0) == MVT::v16i8 &&
572 "PPC only supports shuffles by bytes!");
574 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
576 // Find the first non-undef value in the shuffle mask.
578 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
581 if (i == 16) return -1; // all undef.
583 // Otherwise, check to see if the rest of the elements are consecutively
584 // numbered from this value.
585 unsigned ShiftAmt = SVOp->getMaskElt(i);
586 if (ShiftAmt < i) return -1;
590 // Check the rest of the elements to see if they are consecutive.
591 for (++i; i != 16; ++i)
592 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
595 // Check the rest of the elements to see if they are consecutive.
596 for (++i; i != 16; ++i)
597 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
603 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
604 /// specifies a splat of a single element that is suitable for input to
605 /// VSPLTB/VSPLTH/VSPLTW.
606 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
607 assert(N->getValueType(0) == MVT::v16i8 &&
608 (EltSize == 1 || EltSize == 2 || EltSize == 4));
610 // This is a splat operation if each element of the permute is the same, and
611 // if the value doesn't reference the second vector.
612 unsigned ElementBase = N->getMaskElt(0);
614 // FIXME: Handle UNDEF elements too!
615 if (ElementBase >= 16)
618 // Check that the indices are consecutive, in the case of a multi-byte element
619 // splatted with a v16i8 mask.
620 for (unsigned i = 1; i != EltSize; ++i)
621 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
624 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
625 if (N->getMaskElt(i) < 0) continue;
626 for (unsigned j = 0; j != EltSize; ++j)
627 if (N->getMaskElt(i+j) != N->getMaskElt(j))
633 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
635 bool PPC::isAllNegativeZeroVector(SDNode *N) {
636 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
638 APInt APVal, APUndef;
642 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
643 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
644 return CFP->getValueAPF().isNegZero();
649 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
650 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
651 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
652 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
653 assert(isSplatShuffleMask(SVOp, EltSize));
654 return SVOp->getMaskElt(0) / EltSize;
657 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
658 /// by using a vspltis[bhw] instruction of the specified element size, return
659 /// the constant being splatted. The ByteSize field indicates the number of
660 /// bytes of each element [124] -> [bhw].
661 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
664 // If ByteSize of the splat is bigger than the element size of the
665 // build_vector, then we have a case where we are checking for a splat where
666 // multiple elements of the buildvector are folded together into a single
667 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
668 unsigned EltSize = 16/N->getNumOperands();
669 if (EltSize < ByteSize) {
670 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
671 SDValue UniquedVals[4];
672 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
674 // See if all of the elements in the buildvector agree across.
675 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
676 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
677 // If the element isn't a constant, bail fully out.
678 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
681 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
682 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
683 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
684 return SDValue(); // no match.
687 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
688 // either constant or undef values that are identical for each chunk. See
689 // if these chunks can form into a larger vspltis*.
691 // Check to see if all of the leading entries are either 0 or -1. If
692 // neither, then this won't fit into the immediate field.
693 bool LeadingZero = true;
694 bool LeadingOnes = true;
695 for (unsigned i = 0; i != Multiple-1; ++i) {
696 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
698 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
699 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
701 // Finally, check the least significant entry.
703 if (UniquedVals[Multiple-1].getNode() == 0)
704 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
705 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
707 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
710 if (UniquedVals[Multiple-1].getNode() == 0)
711 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
712 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
713 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
714 return DAG.getTargetConstant(Val, MVT::i32);
720 // Check to see if this buildvec has a single non-undef value in its elements.
721 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
722 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
723 if (OpVal.getNode() == 0)
724 OpVal = N->getOperand(i);
725 else if (OpVal != N->getOperand(i))
729 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
731 unsigned ValSizeInBytes = EltSize;
733 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
734 Value = CN->getZExtValue();
735 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
736 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
737 Value = FloatToBits(CN->getValueAPF().convertToFloat());
740 // If the splat value is larger than the element value, then we can never do
741 // this splat. The only case that we could fit the replicated bits into our
742 // immediate field for would be zero, and we prefer to use vxor for it.
743 if (ValSizeInBytes < ByteSize) return SDValue();
745 // If the element value is larger than the splat value, cut it in half and
746 // check to see if the two halves are equal. Continue doing this until we
747 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
748 while (ValSizeInBytes > ByteSize) {
749 ValSizeInBytes >>= 1;
751 // If the top half equals the bottom half, we're still ok.
752 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
753 (Value & ((1 << (8*ValSizeInBytes))-1)))
757 // Properly sign extend the value.
758 int ShAmt = (4-ByteSize)*8;
759 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
761 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
762 if (MaskVal == 0) return SDValue();
764 // Finally, if this value fits in a 5 bit sext field, return it
765 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
766 return DAG.getTargetConstant(MaskVal, MVT::i32);
770 //===----------------------------------------------------------------------===//
771 // Addressing Mode Selection
772 //===----------------------------------------------------------------------===//
774 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
775 /// or 64-bit immediate, and if the value can be accurately represented as a
776 /// sign extension from a 16-bit value. If so, this returns true and the
778 static bool isIntS16Immediate(SDNode *N, short &Imm) {
779 if (N->getOpcode() != ISD::Constant)
782 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
783 if (N->getValueType(0) == MVT::i32)
784 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
786 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
788 static bool isIntS16Immediate(SDValue Op, short &Imm) {
789 return isIntS16Immediate(Op.getNode(), Imm);
793 /// SelectAddressRegReg - Given the specified addressed, check to see if it
794 /// can be represented as an indexed [r+r] operation. Returns false if it
795 /// can be more efficiently represented with [r+imm].
796 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
798 SelectionDAG &DAG) const {
800 if (N.getOpcode() == ISD::ADD) {
801 if (isIntS16Immediate(N.getOperand(1), imm))
803 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
806 Base = N.getOperand(0);
807 Index = N.getOperand(1);
809 } else if (N.getOpcode() == ISD::OR) {
810 if (isIntS16Immediate(N.getOperand(1), imm))
811 return false; // r+i can fold it if we can.
813 // If this is an or of disjoint bitfields, we can codegen this as an add
814 // (for better address arithmetic) if the LHS and RHS of the OR are provably
816 APInt LHSKnownZero, LHSKnownOne;
817 APInt RHSKnownZero, RHSKnownOne;
818 DAG.ComputeMaskedBits(N.getOperand(0),
819 APInt::getAllOnesValue(N.getOperand(0)
820 .getValueSizeInBits()),
821 LHSKnownZero, LHSKnownOne);
823 if (LHSKnownZero.getBoolValue()) {
824 DAG.ComputeMaskedBits(N.getOperand(1),
825 APInt::getAllOnesValue(N.getOperand(1)
826 .getValueSizeInBits()),
827 RHSKnownZero, RHSKnownOne);
828 // If all of the bits are known zero on the LHS or RHS, the add won't
830 if (~(LHSKnownZero | RHSKnownZero) == 0) {
831 Base = N.getOperand(0);
832 Index = N.getOperand(1);
841 /// Returns true if the address N can be represented by a base register plus
842 /// a signed 16-bit displacement [r+imm], and if it is not better
843 /// represented as reg+reg.
844 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
846 SelectionDAG &DAG) const {
847 // FIXME dl should come from parent load or store, not from address
848 DebugLoc dl = N.getDebugLoc();
849 // If this can be more profitably realized as r+r, fail.
850 if (SelectAddressRegReg(N, Disp, Base, DAG))
853 if (N.getOpcode() == ISD::ADD) {
855 if (isIntS16Immediate(N.getOperand(1), imm)) {
856 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
857 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
858 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
860 Base = N.getOperand(0);
862 return true; // [r+i]
863 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
864 // Match LOAD (ADD (X, Lo(G))).
865 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
866 && "Cannot handle constant offsets yet!");
867 Disp = N.getOperand(1).getOperand(0); // The global address.
868 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
869 Disp.getOpcode() == ISD::TargetConstantPool ||
870 Disp.getOpcode() == ISD::TargetJumpTable);
871 Base = N.getOperand(0);
872 return true; // [&g+r]
874 } else if (N.getOpcode() == ISD::OR) {
876 if (isIntS16Immediate(N.getOperand(1), imm)) {
877 // If this is an or of disjoint bitfields, we can codegen this as an add
878 // (for better address arithmetic) if the LHS and RHS of the OR are
879 // provably disjoint.
880 APInt LHSKnownZero, LHSKnownOne;
881 DAG.ComputeMaskedBits(N.getOperand(0),
882 APInt::getAllOnesValue(N.getOperand(0)
883 .getValueSizeInBits()),
884 LHSKnownZero, LHSKnownOne);
886 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
887 // If all of the bits are known zero on the LHS or RHS, the add won't
889 Base = N.getOperand(0);
890 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
894 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
895 // Loading from a constant address.
897 // If this address fits entirely in a 16-bit sext immediate field, codegen
900 if (isIntS16Immediate(CN, Imm)) {
901 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
902 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
903 CN->getValueType(0));
907 // Handle 32-bit sext immediates with LIS + addr mode.
908 if (CN->getValueType(0) == MVT::i32 ||
909 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
910 int Addr = (int)CN->getZExtValue();
912 // Otherwise, break this down into an LIS + disp.
913 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
915 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
916 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
917 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
922 Disp = DAG.getTargetConstant(0, getPointerTy());
923 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
924 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
927 return true; // [r+0]
930 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
931 /// represented as an indexed [r+r] operation.
932 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
934 SelectionDAG &DAG) const {
935 // Check to see if we can easily represent this as an [r+r] address. This
936 // will fail if it thinks that the address is more profitably represented as
937 // reg+imm, e.g. where imm = 0.
938 if (SelectAddressRegReg(N, Base, Index, DAG))
941 // If the operand is an addition, always emit this as [r+r], since this is
942 // better (for code size, and execution, as the memop does the add for free)
943 // than emitting an explicit add.
944 if (N.getOpcode() == ISD::ADD) {
945 Base = N.getOperand(0);
946 Index = N.getOperand(1);
950 // Otherwise, do it the hard way, using R0 as the base register.
951 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
957 /// SelectAddressRegImmShift - Returns true if the address N can be
958 /// represented by a base register plus a signed 14-bit displacement
959 /// [r+imm*4]. Suitable for use by STD and friends.
960 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
962 SelectionDAG &DAG) const {
963 // FIXME dl should come from the parent load or store, not the address
964 DebugLoc dl = N.getDebugLoc();
965 // If this can be more profitably realized as r+r, fail.
966 if (SelectAddressRegReg(N, Disp, Base, DAG))
969 if (N.getOpcode() == ISD::ADD) {
971 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
972 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
973 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
974 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
976 Base = N.getOperand(0);
978 return true; // [r+i]
979 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
980 // Match LOAD (ADD (X, Lo(G))).
981 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
982 && "Cannot handle constant offsets yet!");
983 Disp = N.getOperand(1).getOperand(0); // The global address.
984 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
985 Disp.getOpcode() == ISD::TargetConstantPool ||
986 Disp.getOpcode() == ISD::TargetJumpTable);
987 Base = N.getOperand(0);
988 return true; // [&g+r]
990 } else if (N.getOpcode() == ISD::OR) {
992 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
993 // If this is an or of disjoint bitfields, we can codegen this as an add
994 // (for better address arithmetic) if the LHS and RHS of the OR are
995 // provably disjoint.
996 APInt LHSKnownZero, LHSKnownOne;
997 DAG.ComputeMaskedBits(N.getOperand(0),
998 APInt::getAllOnesValue(N.getOperand(0)
999 .getValueSizeInBits()),
1000 LHSKnownZero, LHSKnownOne);
1001 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1002 // If all of the bits are known zero on the LHS or RHS, the add won't
1004 Base = N.getOperand(0);
1005 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1009 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1010 // Loading from a constant address. Verify low two bits are clear.
1011 if ((CN->getZExtValue() & 3) == 0) {
1012 // If this address fits entirely in a 14-bit sext immediate field, codegen
1015 if (isIntS16Immediate(CN, Imm)) {
1016 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1017 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1021 // Fold the low-part of 32-bit absolute addresses into addr mode.
1022 if (CN->getValueType(0) == MVT::i32 ||
1023 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1024 int Addr = (int)CN->getZExtValue();
1026 // Otherwise, break this down into an LIS + disp.
1027 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1028 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1029 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1030 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1036 Disp = DAG.getTargetConstant(0, getPointerTy());
1037 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1038 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1041 return true; // [r+0]
1045 /// getPreIndexedAddressParts - returns true by value, base pointer and
1046 /// offset pointer and addressing mode by reference if the node's address
1047 /// can be legally represented as pre-indexed load / store address.
1048 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1050 ISD::MemIndexedMode &AM,
1051 SelectionDAG &DAG) const {
1052 // Disabled by default for now.
1053 if (!EnablePPCPreinc) return false;
1057 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1058 Ptr = LD->getBasePtr();
1059 VT = LD->getMemoryVT();
1061 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1062 Ptr = ST->getBasePtr();
1063 VT = ST->getMemoryVT();
1067 // PowerPC doesn't have preinc load/store instructions for vectors.
1071 // TODO: Check reg+reg first.
1073 // LDU/STU use reg+imm*4, others use reg+imm.
1074 if (VT != MVT::i64) {
1076 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1080 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1084 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1085 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1086 // sext i32 to i64 when addr mode is r+i.
1087 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1088 LD->getExtensionType() == ISD::SEXTLOAD &&
1089 isa<ConstantSDNode>(Offset))
1097 //===----------------------------------------------------------------------===//
1098 // LowerOperation implementation
1099 //===----------------------------------------------------------------------===//
1101 /// GetLabelAccessInfo - Return true if we should reference labels using a
1102 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1103 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1104 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1105 HiOpFlags = PPCII::MO_HA16;
1106 LoOpFlags = PPCII::MO_LO16;
1108 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1109 // non-darwin platform. We don't support PIC on other platforms yet.
1110 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1111 TM.getSubtarget<PPCSubtarget>().isDarwin();
1113 HiOpFlags |= PPCII::MO_PIC_FLAG;
1114 LoOpFlags |= PPCII::MO_PIC_FLAG;
1117 // If this is a reference to a global value that requires a non-lazy-ptr, make
1118 // sure that instruction lowering adds it.
1119 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1120 HiOpFlags |= PPCII::MO_NLP_FLAG;
1121 LoOpFlags |= PPCII::MO_NLP_FLAG;
1123 if (GV->hasHiddenVisibility()) {
1124 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1125 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1132 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1133 SelectionDAG &DAG) {
1134 EVT PtrVT = HiPart.getValueType();
1135 SDValue Zero = DAG.getConstant(0, PtrVT);
1136 DebugLoc DL = HiPart.getDebugLoc();
1138 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1139 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1141 // With PIC, the first instruction is actually "GR+hi(&G)".
1143 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1144 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1146 // Generate non-pic code that has direct accesses to the constant pool.
1147 // The address of the global is just (hi(&g)+lo(&g)).
1148 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1151 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1152 SelectionDAG &DAG) const {
1153 EVT PtrVT = Op.getValueType();
1154 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1155 const Constant *C = CP->getConstVal();
1157 unsigned MOHiFlag, MOLoFlag;
1158 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1160 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1162 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1163 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1166 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1167 EVT PtrVT = Op.getValueType();
1168 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1170 unsigned MOHiFlag, MOLoFlag;
1171 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1172 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1173 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1174 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1177 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1178 SelectionDAG &DAG) const {
1179 EVT PtrVT = Op.getValueType();
1181 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1183 unsigned MOHiFlag, MOLoFlag;
1184 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1185 SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag);
1186 SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag);
1187 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1190 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1191 SelectionDAG &DAG) const {
1192 EVT PtrVT = Op.getValueType();
1193 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1194 DebugLoc DL = GSDN->getDebugLoc();
1195 const GlobalValue *GV = GSDN->getGlobal();
1197 // 64-bit SVR4 ABI code is always position-independent.
1198 // The actual address of the GlobalValue is stored in the TOC.
1199 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1200 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1201 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1202 DAG.getRegister(PPC::X2, MVT::i64));
1205 unsigned MOHiFlag, MOLoFlag;
1206 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1209 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1211 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1213 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1215 // If the global reference is actually to a non-lazy-pointer, we have to do an
1216 // extra load to get the address of the global.
1217 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1218 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1223 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1224 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1225 DebugLoc dl = Op.getDebugLoc();
1227 // If we're comparing for equality to zero, expose the fact that this is
1228 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1229 // fold the new nodes.
1230 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1231 if (C->isNullValue() && CC == ISD::SETEQ) {
1232 EVT VT = Op.getOperand(0).getValueType();
1233 SDValue Zext = Op.getOperand(0);
1234 if (VT.bitsLT(MVT::i32)) {
1236 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1238 unsigned Log2b = Log2_32(VT.getSizeInBits());
1239 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1240 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1241 DAG.getConstant(Log2b, MVT::i32));
1242 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1244 // Leave comparisons against 0 and -1 alone for now, since they're usually
1245 // optimized. FIXME: revisit this when we can custom lower all setcc
1247 if (C->isAllOnesValue() || C->isNullValue())
1251 // If we have an integer seteq/setne, turn it into a compare against zero
1252 // by xor'ing the rhs with the lhs, which is faster than setting a
1253 // condition register, reading it back out, and masking the correct bit. The
1254 // normal approach here uses sub to do this instead of xor. Using xor exposes
1255 // the result to other bit-twiddling opportunities.
1256 EVT LHSVT = Op.getOperand(0).getValueType();
1257 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1258 EVT VT = Op.getValueType();
1259 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1261 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1266 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1267 const PPCSubtarget &Subtarget) const {
1269 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1270 return SDValue(); // Not reached
1273 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op,
1274 SelectionDAG &DAG) const {
1275 SDValue Chain = Op.getOperand(0);
1276 SDValue Trmp = Op.getOperand(1); // trampoline
1277 SDValue FPtr = Op.getOperand(2); // nested function
1278 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1279 DebugLoc dl = Op.getDebugLoc();
1281 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1282 bool isPPC64 = (PtrVT == MVT::i64);
1283 const Type *IntPtrTy =
1284 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1287 TargetLowering::ArgListTy Args;
1288 TargetLowering::ArgListEntry Entry;
1290 Entry.Ty = IntPtrTy;
1291 Entry.Node = Trmp; Args.push_back(Entry);
1293 // TrampSize == (isPPC64 ? 48 : 40);
1294 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1295 isPPC64 ? MVT::i64 : MVT::i32);
1296 Args.push_back(Entry);
1298 Entry.Node = FPtr; Args.push_back(Entry);
1299 Entry.Node = Nest; Args.push_back(Entry);
1301 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1302 std::pair<SDValue, SDValue> CallResult =
1303 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
1304 false, false, false, false, 0, CallingConv::C, false,
1305 /*isReturnValueUsed=*/true,
1306 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1310 { CallResult.first, CallResult.second };
1312 return DAG.getMergeValues(Ops, 2, dl);
1315 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1316 const PPCSubtarget &Subtarget) const {
1317 MachineFunction &MF = DAG.getMachineFunction();
1318 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1320 DebugLoc dl = Op.getDebugLoc();
1322 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1323 // vastart just stores the address of the VarArgsFrameIndex slot into the
1324 // memory location argument.
1325 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1326 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1327 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1328 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1329 MachinePointerInfo(SV),
1333 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1334 // We suppose the given va_list is already allocated.
1337 // char gpr; /* index into the array of 8 GPRs
1338 // * stored in the register save area
1339 // * gpr=0 corresponds to r3,
1340 // * gpr=1 to r4, etc.
1342 // char fpr; /* index into the array of 8 FPRs
1343 // * stored in the register save area
1344 // * fpr=0 corresponds to f1,
1345 // * fpr=1 to f2, etc.
1347 // char *overflow_arg_area;
1348 // /* location on stack that holds
1349 // * the next overflow argument
1351 // char *reg_save_area;
1352 // /* where r3:r10 and f1:f8 (if saved)
1358 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1359 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1362 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1364 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1366 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1369 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1370 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1372 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1373 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1375 uint64_t FPROffset = 1;
1376 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1378 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1380 // Store first byte : number of int regs
1381 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1383 MachinePointerInfo(SV),
1384 MVT::i8, false, false, 0);
1385 uint64_t nextOffset = FPROffset;
1386 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1389 // Store second byte : number of float regs
1390 SDValue secondStore =
1391 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1392 MachinePointerInfo(SV, nextOffset), MVT::i8,
1394 nextOffset += StackOffset;
1395 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1397 // Store second word : arguments given on stack
1398 SDValue thirdStore =
1399 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1400 MachinePointerInfo(SV, nextOffset),
1402 nextOffset += FrameOffset;
1403 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1405 // Store third word : arguments given in registers
1406 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1407 MachinePointerInfo(SV, nextOffset),
1412 #include "PPCGenCallingConv.inc"
1414 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1415 CCValAssign::LocInfo &LocInfo,
1416 ISD::ArgFlagsTy &ArgFlags,
1421 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1423 CCValAssign::LocInfo &LocInfo,
1424 ISD::ArgFlagsTy &ArgFlags,
1426 static const unsigned ArgRegs[] = {
1427 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1428 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1430 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1432 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1434 // Skip one register if the first unallocated register has an even register
1435 // number and there are still argument registers available which have not been
1436 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1437 // need to skip a register if RegNum is odd.
1438 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1439 State.AllocateReg(ArgRegs[RegNum]);
1442 // Always return false here, as this function only makes sure that the first
1443 // unallocated register has an odd register number and does not actually
1444 // allocate a register for the current argument.
1448 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1450 CCValAssign::LocInfo &LocInfo,
1451 ISD::ArgFlagsTy &ArgFlags,
1453 static const unsigned ArgRegs[] = {
1454 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1458 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1460 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1462 // If there is only one Floating-point register left we need to put both f64
1463 // values of a split ppc_fp128 value on the stack.
1464 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1465 State.AllocateReg(ArgRegs[RegNum]);
1468 // Always return false here, as this function only makes sure that the two f64
1469 // values a ppc_fp128 value is split into are both passed in registers or both
1470 // passed on the stack and does not actually allocate a register for the
1471 // current argument.
1475 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1477 static const unsigned *GetFPR() {
1478 static const unsigned FPR[] = {
1479 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1480 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1486 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1488 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1489 unsigned PtrByteSize) {
1490 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1491 if (Flags.isByVal())
1492 ArgSize = Flags.getByValSize();
1493 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1499 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1500 CallingConv::ID CallConv, bool isVarArg,
1501 const SmallVectorImpl<ISD::InputArg>
1503 DebugLoc dl, SelectionDAG &DAG,
1504 SmallVectorImpl<SDValue> &InVals)
1506 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1507 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1510 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1516 PPCTargetLowering::LowerFormalArguments_SVR4(
1518 CallingConv::ID CallConv, bool isVarArg,
1519 const SmallVectorImpl<ISD::InputArg>
1521 DebugLoc dl, SelectionDAG &DAG,
1522 SmallVectorImpl<SDValue> &InVals) const {
1524 // 32-bit SVR4 ABI Stack Frame Layout:
1525 // +-----------------------------------+
1526 // +--> | Back chain |
1527 // | +-----------------------------------+
1528 // | | Floating-point register save area |
1529 // | +-----------------------------------+
1530 // | | General register save area |
1531 // | +-----------------------------------+
1532 // | | CR save word |
1533 // | +-----------------------------------+
1534 // | | VRSAVE save word |
1535 // | +-----------------------------------+
1536 // | | Alignment padding |
1537 // | +-----------------------------------+
1538 // | | Vector register save area |
1539 // | +-----------------------------------+
1540 // | | Local variable space |
1541 // | +-----------------------------------+
1542 // | | Parameter list area |
1543 // | +-----------------------------------+
1544 // | | LR save word |
1545 // | +-----------------------------------+
1546 // SP--> +--- | Back chain |
1547 // +-----------------------------------+
1550 // System V Application Binary Interface PowerPC Processor Supplement
1551 // AltiVec Technology Programming Interface Manual
1553 MachineFunction &MF = DAG.getMachineFunction();
1554 MachineFrameInfo *MFI = MF.getFrameInfo();
1555 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1557 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1558 // Potential tail calls could cause overwriting of argument stack slots.
1559 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1560 unsigned PtrByteSize = 4;
1562 // Assign locations to all of the incoming arguments.
1563 SmallVector<CCValAssign, 16> ArgLocs;
1564 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1567 // Reserve space for the linkage area on the stack.
1568 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1570 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1572 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1573 CCValAssign &VA = ArgLocs[i];
1575 // Arguments stored in registers.
1576 if (VA.isRegLoc()) {
1577 TargetRegisterClass *RC;
1578 EVT ValVT = VA.getValVT();
1580 switch (ValVT.getSimpleVT().SimpleTy) {
1582 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1584 RC = PPC::GPRCRegisterClass;
1587 RC = PPC::F4RCRegisterClass;
1590 RC = PPC::F8RCRegisterClass;
1596 RC = PPC::VRRCRegisterClass;
1600 // Transform the arguments stored in physical registers into virtual ones.
1601 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1602 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1604 InVals.push_back(ArgValue);
1606 // Argument stored in memory.
1607 assert(VA.isMemLoc());
1609 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1610 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1613 // Create load nodes to retrieve arguments from the stack.
1614 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1615 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1616 MachinePointerInfo(),
1621 // Assign locations to all of the incoming aggregate by value arguments.
1622 // Aggregates passed by value are stored in the local variable space of the
1623 // caller's stack frame, right above the parameter list area.
1624 SmallVector<CCValAssign, 16> ByValArgLocs;
1625 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1626 ByValArgLocs, *DAG.getContext());
1628 // Reserve stack space for the allocations in CCInfo.
1629 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1631 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1633 // Area that is at least reserved in the caller of this function.
1634 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1636 // Set the size that is at least reserved in caller of this function. Tail
1637 // call optimized function's reserved stack space needs to be aligned so that
1638 // taking the difference between two stack areas will result in an aligned
1640 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1643 std::max(MinReservedArea,
1644 PPCFrameLowering::getMinCallFrameSize(false, false));
1646 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
1647 getStackAlignment();
1648 unsigned AlignMask = TargetAlign-1;
1649 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1651 FI->setMinReservedArea(MinReservedArea);
1653 SmallVector<SDValue, 8> MemOps;
1655 // If the function takes variable number of arguments, make a frame index for
1656 // the start of the first vararg value... for expansion of llvm.va_start.
1658 static const unsigned GPArgRegs[] = {
1659 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1660 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1662 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1664 static const unsigned FPArgRegs[] = {
1665 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1668 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1670 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
1672 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
1675 // Make room for NumGPArgRegs and NumFPArgRegs.
1676 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1677 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1679 FuncInfo->setVarArgsStackOffset(
1680 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1681 CCInfo.getNextStackOffset(), true));
1683 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
1684 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1686 // The fixed integer arguments of a variadic function are stored to the
1687 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
1688 // the result of va_next.
1689 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1690 // Get an existing live-in vreg, or add a new one.
1691 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
1693 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1695 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1696 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1697 MachinePointerInfo(), false, false, 0);
1698 MemOps.push_back(Store);
1699 // Increment the address by four for the next argument to store
1700 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1701 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1704 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1706 // The double arguments are stored to the VarArgsFrameIndex
1708 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1709 // Get an existing live-in vreg, or add a new one.
1710 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
1712 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1714 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1715 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1716 MachinePointerInfo(), false, false, 0);
1717 MemOps.push_back(Store);
1718 // Increment the address by eight for the next argument to store
1719 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1721 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1725 if (!MemOps.empty())
1726 Chain = DAG.getNode(ISD::TokenFactor, dl,
1727 MVT::Other, &MemOps[0], MemOps.size());
1733 PPCTargetLowering::LowerFormalArguments_Darwin(
1735 CallingConv::ID CallConv, bool isVarArg,
1736 const SmallVectorImpl<ISD::InputArg>
1738 DebugLoc dl, SelectionDAG &DAG,
1739 SmallVectorImpl<SDValue> &InVals) const {
1740 // TODO: add description of PPC stack frame format, or at least some docs.
1742 MachineFunction &MF = DAG.getMachineFunction();
1743 MachineFrameInfo *MFI = MF.getFrameInfo();
1744 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1746 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1747 bool isPPC64 = PtrVT == MVT::i64;
1748 // Potential tail calls could cause overwriting of argument stack slots.
1749 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1750 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1752 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
1753 // Area that is at least reserved in caller of this function.
1754 unsigned MinReservedArea = ArgOffset;
1756 static const unsigned GPR_32[] = { // 32-bit registers.
1757 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1758 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1760 static const unsigned GPR_64[] = { // 64-bit registers.
1761 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1762 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1765 static const unsigned *FPR = GetFPR();
1767 static const unsigned VR[] = {
1768 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1769 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1772 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1773 const unsigned Num_FPR_Regs = 13;
1774 const unsigned Num_VR_Regs = array_lengthof( VR);
1776 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1778 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1780 // In 32-bit non-varargs functions, the stack space for vectors is after the
1781 // stack space for non-vectors. We do not use this space unless we have
1782 // too many vectors to fit in registers, something that only occurs in
1783 // constructed examples:), but we have to walk the arglist to figure
1784 // that out...for the pathological case, compute VecArgOffset as the
1785 // start of the vector parameter area. Computing VecArgOffset is the
1786 // entire point of the following loop.
1787 unsigned VecArgOffset = ArgOffset;
1788 if (!isVarArg && !isPPC64) {
1789 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1791 EVT ObjectVT = Ins[ArgNo].VT;
1792 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1793 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1795 if (Flags.isByVal()) {
1796 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1797 ObjSize = Flags.getByValSize();
1799 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1800 VecArgOffset += ArgSize;
1804 switch(ObjectVT.getSimpleVT().SimpleTy) {
1805 default: llvm_unreachable("Unhandled argument type!");
1808 VecArgOffset += isPPC64 ? 8 : 4;
1810 case MVT::i64: // PPC64
1818 // Nothing to do, we're only looking at Nonvector args here.
1823 // We've found where the vector parameter area in memory is. Skip the
1824 // first 12 parameters; these don't use that memory.
1825 VecArgOffset = ((VecArgOffset+15)/16)*16;
1826 VecArgOffset += 12*16;
1828 // Add DAG nodes to load the arguments or copy them out of registers. On
1829 // entry to a function on PPC, the arguments start after the linkage area,
1830 // although the first ones are often in registers.
1832 SmallVector<SDValue, 8> MemOps;
1833 unsigned nAltivecParamsAtEnd = 0;
1834 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1836 bool needsLoad = false;
1837 EVT ObjectVT = Ins[ArgNo].VT;
1838 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1839 unsigned ArgSize = ObjSize;
1840 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1842 unsigned CurArgOffset = ArgOffset;
1844 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1845 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1846 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1847 if (isVarArg || isPPC64) {
1848 MinReservedArea = ((MinReservedArea+15)/16)*16;
1849 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1852 } else nAltivecParamsAtEnd++;
1854 // Calculate min reserved area.
1855 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1859 // FIXME the codegen can be much improved in some cases.
1860 // We do not have to keep everything in memory.
1861 if (Flags.isByVal()) {
1862 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1863 ObjSize = Flags.getByValSize();
1864 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1865 // Objects of size 1 and 2 are right justified, everything else is
1866 // left justified. This means the memory address is adjusted forwards.
1867 if (ObjSize==1 || ObjSize==2) {
1868 CurArgOffset = CurArgOffset + (4 - ObjSize);
1870 // The value of the object is its address.
1871 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
1872 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1873 InVals.push_back(FIN);
1874 if (ObjSize==1 || ObjSize==2) {
1875 if (GPR_idx != Num_GPR_Regs) {
1876 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1877 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1878 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1879 MachinePointerInfo(),
1880 ObjSize==1 ? MVT::i8 : MVT::i16,
1882 MemOps.push_back(Store);
1886 ArgOffset += PtrByteSize;
1890 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1891 // Store whatever pieces of the object are in registers
1892 // to memory. ArgVal will be address of the beginning of
1894 if (GPR_idx != Num_GPR_Regs) {
1895 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1896 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
1897 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1898 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1899 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1900 MachinePointerInfo(),
1902 MemOps.push_back(Store);
1904 ArgOffset += PtrByteSize;
1906 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1913 switch (ObjectVT.getSimpleVT().SimpleTy) {
1914 default: llvm_unreachable("Unhandled argument type!");
1917 if (GPR_idx != Num_GPR_Regs) {
1918 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1919 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1923 ArgSize = PtrByteSize;
1925 // All int arguments reserve stack space in the Darwin ABI.
1926 ArgOffset += PtrByteSize;
1930 case MVT::i64: // PPC64
1931 if (GPR_idx != Num_GPR_Regs) {
1932 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1933 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1935 if (ObjectVT == MVT::i32) {
1936 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1937 // value to MVT::i64 and then truncate to the correct register size.
1939 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1940 DAG.getValueType(ObjectVT));
1941 else if (Flags.isZExt())
1942 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1943 DAG.getValueType(ObjectVT));
1945 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1951 ArgSize = PtrByteSize;
1953 // All int arguments reserve stack space in the Darwin ABI.
1959 // Every 4 bytes of argument space consumes one of the GPRs available for
1960 // argument passing.
1961 if (GPR_idx != Num_GPR_Regs) {
1963 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1966 if (FPR_idx != Num_FPR_Regs) {
1969 if (ObjectVT == MVT::f32)
1970 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1972 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1974 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1980 // All FP arguments reserve stack space in the Darwin ABI.
1981 ArgOffset += isPPC64 ? 8 : ObjSize;
1987 // Note that vector arguments in registers don't reserve stack space,
1988 // except in varargs functions.
1989 if (VR_idx != Num_VR_Regs) {
1990 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
1991 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1993 while ((ArgOffset % 16) != 0) {
1994 ArgOffset += PtrByteSize;
1995 if (GPR_idx != Num_GPR_Regs)
1999 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2003 if (!isVarArg && !isPPC64) {
2004 // Vectors go after all the nonvectors.
2005 CurArgOffset = VecArgOffset;
2008 // Vectors are aligned.
2009 ArgOffset = ((ArgOffset+15)/16)*16;
2010 CurArgOffset = ArgOffset;
2018 // We need to load the argument to a virtual register if we determined above
2019 // that we ran out of physical registers of the appropriate type.
2021 int FI = MFI->CreateFixedObject(ObjSize,
2022 CurArgOffset + (ArgSize - ObjSize),
2024 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2025 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2029 InVals.push_back(ArgVal);
2032 // Set the size that is at least reserved in caller of this function. Tail
2033 // call optimized function's reserved stack space needs to be aligned so that
2034 // taking the difference between two stack areas will result in an aligned
2036 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2037 // Add the Altivec parameters at the end, if needed.
2038 if (nAltivecParamsAtEnd) {
2039 MinReservedArea = ((MinReservedArea+15)/16)*16;
2040 MinReservedArea += 16*nAltivecParamsAtEnd;
2043 std::max(MinReservedArea,
2044 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2045 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2046 getStackAlignment();
2047 unsigned AlignMask = TargetAlign-1;
2048 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2049 FI->setMinReservedArea(MinReservedArea);
2051 // If the function takes variable number of arguments, make a frame index for
2052 // the start of the first vararg value... for expansion of llvm.va_start.
2054 int Depth = ArgOffset;
2056 FuncInfo->setVarArgsFrameIndex(
2057 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2059 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2061 // If this function is vararg, store any remaining integer argument regs
2062 // to their spots on the stack so that they may be loaded by deferencing the
2063 // result of va_next.
2064 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2068 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2070 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2072 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2073 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2074 MachinePointerInfo(), false, false, 0);
2075 MemOps.push_back(Store);
2076 // Increment the address by four for the next argument to store
2077 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2078 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2082 if (!MemOps.empty())
2083 Chain = DAG.getNode(ISD::TokenFactor, dl,
2084 MVT::Other, &MemOps[0], MemOps.size());
2089 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2090 /// linkage area for the Darwin ABI.
2092 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2096 const SmallVectorImpl<ISD::OutputArg>
2098 const SmallVectorImpl<SDValue> &OutVals,
2099 unsigned &nAltivecParamsAtEnd) {
2100 // Count how many bytes are to be pushed on the stack, including the linkage
2101 // area, and parameter passing area. We start with 24/48 bytes, which is
2102 // prereserved space for [SP][CR][LR][3 x unused].
2103 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2104 unsigned NumOps = Outs.size();
2105 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2107 // Add up all the space actually used.
2108 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2109 // they all go in registers, but we must reserve stack space for them for
2110 // possible use by the caller. In varargs or 64-bit calls, parameters are
2111 // assigned stack space in order, with padding so Altivec parameters are
2113 nAltivecParamsAtEnd = 0;
2114 for (unsigned i = 0; i != NumOps; ++i) {
2115 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2116 EVT ArgVT = Outs[i].VT;
2117 // Varargs Altivec parameters are padded to a 16 byte boundary.
2118 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2119 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2120 if (!isVarArg && !isPPC64) {
2121 // Non-varargs Altivec parameters go after all the non-Altivec
2122 // parameters; handle those later so we know how much padding we need.
2123 nAltivecParamsAtEnd++;
2126 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2127 NumBytes = ((NumBytes+15)/16)*16;
2129 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2132 // Allow for Altivec parameters at the end, if needed.
2133 if (nAltivecParamsAtEnd) {
2134 NumBytes = ((NumBytes+15)/16)*16;
2135 NumBytes += 16*nAltivecParamsAtEnd;
2138 // The prolog code of the callee may store up to 8 GPR argument registers to
2139 // the stack, allowing va_start to index over them in memory if its varargs.
2140 // Because we cannot tell if this is needed on the caller side, we have to
2141 // conservatively assume that it is needed. As such, make sure we have at
2142 // least enough stack space for the caller to store the 8 GPRs.
2143 NumBytes = std::max(NumBytes,
2144 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2146 // Tail call needs the stack to be aligned.
2147 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) {
2148 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2149 getStackAlignment();
2150 unsigned AlignMask = TargetAlign-1;
2151 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2157 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2158 /// adjusted to accommodate the arguments for the tailcall.
2159 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2160 unsigned ParamSize) {
2162 if (!isTailCall) return 0;
2164 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2165 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2166 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2167 // Remember only if the new adjustement is bigger.
2168 if (SPDiff < FI->getTailCallSPDelta())
2169 FI->setTailCallSPDelta(SPDiff);
2174 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2175 /// for tail call optimization. Targets which want to do tail call
2176 /// optimization should implement this function.
2178 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2179 CallingConv::ID CalleeCC,
2181 const SmallVectorImpl<ISD::InputArg> &Ins,
2182 SelectionDAG& DAG) const {
2183 if (!GuaranteedTailCallOpt)
2186 // Variable argument functions are not supported.
2190 MachineFunction &MF = DAG.getMachineFunction();
2191 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2192 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2193 // Functions containing by val parameters are not supported.
2194 for (unsigned i = 0; i != Ins.size(); i++) {
2195 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2196 if (Flags.isByVal()) return false;
2199 // Non PIC/GOT tail calls are supported.
2200 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2203 // At the moment we can only do local tail calls (in same module, hidden
2204 // or protected) if we are generating PIC.
2205 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2206 return G->getGlobal()->hasHiddenVisibility()
2207 || G->getGlobal()->hasProtectedVisibility();
2213 /// isCallCompatibleAddress - Return the immediate to use if the specified
2214 /// 32-bit value is representable in the immediate field of a BxA instruction.
2215 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2216 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2219 int Addr = C->getZExtValue();
2220 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2221 (Addr << 6 >> 6) != Addr)
2222 return 0; // Top 6 bits have to be sext of immediate.
2224 return DAG.getConstant((int)C->getZExtValue() >> 2,
2225 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2230 struct TailCallArgumentInfo {
2235 TailCallArgumentInfo() : FrameIdx(0) {}
2240 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2242 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2244 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2245 SmallVector<SDValue, 8> &MemOpChains,
2247 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2248 SDValue Arg = TailCallArgs[i].Arg;
2249 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2250 int FI = TailCallArgs[i].FrameIdx;
2251 // Store relative to framepointer.
2252 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2253 MachinePointerInfo::getFixedStack(FI),
2258 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2259 /// the appropriate stack slot for the tail call optimized function call.
2260 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2261 MachineFunction &MF,
2270 // Calculate the new stack slot for the return address.
2271 int SlotSize = isPPC64 ? 8 : 4;
2272 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2274 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2275 NewRetAddrLoc, true);
2276 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2277 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2278 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2279 MachinePointerInfo::getFixedStack(NewRetAddr),
2282 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2283 // slot as the FP is never overwritten.
2286 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2287 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2289 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2290 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2291 MachinePointerInfo::getFixedStack(NewFPIdx),
2298 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2299 /// the position of the argument.
2301 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2302 SDValue Arg, int SPDiff, unsigned ArgOffset,
2303 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2304 int Offset = ArgOffset + SPDiff;
2305 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2306 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2307 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2308 SDValue FIN = DAG.getFrameIndex(FI, VT);
2309 TailCallArgumentInfo Info;
2311 Info.FrameIdxOp = FIN;
2313 TailCallArguments.push_back(Info);
2316 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2317 /// stack slot. Returns the chain as result and the loaded frame pointers in
2318 /// LROpOut/FPOpout. Used when tail calling.
2319 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2325 DebugLoc dl) const {
2327 // Load the LR and FP stack slot for later adjusting.
2328 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2329 LROpOut = getReturnAddrFrameIndex(DAG);
2330 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2332 Chain = SDValue(LROpOut.getNode(), 1);
2334 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2335 // slot as the FP is never overwritten.
2337 FPOpOut = getFramePointerFrameIndex(DAG);
2338 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
2340 Chain = SDValue(FPOpOut.getNode(), 1);
2346 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2347 /// by "Src" to address "Dst" of size "Size". Alignment information is
2348 /// specified by the specific parameter attribute. The copy will be passed as
2349 /// a byval function parameter.
2350 /// Sometimes what we are copying is the end of a larger object, the part that
2351 /// does not fit in registers.
2353 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2354 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2356 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2357 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2358 false, false, MachinePointerInfo(0),
2359 MachinePointerInfo(0));
2362 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2365 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2366 SDValue Arg, SDValue PtrOff, int SPDiff,
2367 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2368 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2369 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
2371 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2376 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2378 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2379 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2380 DAG.getConstant(ArgOffset, PtrVT));
2382 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2383 MachinePointerInfo(), false, false, 0));
2384 // Calculate and remember argument location.
2385 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2390 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2391 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2392 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2393 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2394 MachineFunction &MF = DAG.getMachineFunction();
2396 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2397 // might overwrite each other in case of tail call optimization.
2398 SmallVector<SDValue, 8> MemOpChains2;
2399 // Do not flag preceding copytoreg stuff together with the following stuff.
2401 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2403 if (!MemOpChains2.empty())
2404 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2405 &MemOpChains2[0], MemOpChains2.size());
2407 // Store the return address to the appropriate stack slot.
2408 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2409 isPPC64, isDarwinABI, dl);
2411 // Emit callseq_end just before tailcall node.
2412 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2413 DAG.getIntPtrConstant(0, true), InFlag);
2414 InFlag = Chain.getValue(1);
2418 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2419 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2420 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2421 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2422 const PPCSubtarget &PPCSubTarget) {
2424 bool isPPC64 = PPCSubTarget.isPPC64();
2425 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
2427 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2428 NodeTys.push_back(MVT::Other); // Returns a chain
2429 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
2431 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2433 bool needIndirectCall = true;
2434 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
2435 // If this is an absolute destination address, use the munged value.
2436 Callee = SDValue(Dest, 0);
2437 needIndirectCall = false;
2440 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2441 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
2442 // Use indirect calls for ALL functions calls in JIT mode, since the
2443 // far-call stubs may be outside relocation limits for a BL instruction.
2444 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
2445 unsigned OpFlags = 0;
2446 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2447 PPCSubTarget.getDarwinVers() < 9 &&
2448 (G->getGlobal()->isDeclaration() ||
2449 G->getGlobal()->isWeakForLinker())) {
2450 // PC-relative references to external symbols should go through $stub,
2451 // unless we're building with the leopard linker or later, which
2452 // automatically synthesizes these stubs.
2453 OpFlags = PPCII::MO_DARWIN_STUB;
2456 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
2457 // every direct call is) turn it into a TargetGlobalAddress /
2458 // TargetExternalSymbol node so that legalize doesn't hack it.
2459 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2460 Callee.getValueType(),
2462 needIndirectCall = false;
2466 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2467 unsigned char OpFlags = 0;
2469 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2470 PPCSubTarget.getDarwinVers() < 9) {
2471 // PC-relative references to external symbols should go through $stub,
2472 // unless we're building with the leopard linker or later, which
2473 // automatically synthesizes these stubs.
2474 OpFlags = PPCII::MO_DARWIN_STUB;
2477 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
2479 needIndirectCall = false;
2482 if (needIndirectCall) {
2483 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2484 // to do the call, we can't use PPCISD::CALL.
2485 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2487 if (isSVR4ABI && isPPC64) {
2488 // Function pointers in the 64-bit SVR4 ABI do not point to the function
2489 // entry point, but to the function descriptor (the function entry point
2490 // address is part of the function descriptor though).
2491 // The function descriptor is a three doubleword structure with the
2492 // following fields: function entry point, TOC base address and
2493 // environment pointer.
2494 // Thus for a call through a function pointer, the following actions need
2496 // 1. Save the TOC of the caller in the TOC save area of its stack
2497 // frame (this is done in LowerCall_Darwin()).
2498 // 2. Load the address of the function entry point from the function
2500 // 3. Load the TOC of the callee from the function descriptor into r2.
2501 // 4. Load the environment pointer from the function descriptor into
2503 // 5. Branch to the function entry point address.
2504 // 6. On return of the callee, the TOC of the caller needs to be
2505 // restored (this is done in FinishCall()).
2507 // All those operations are flagged together to ensure that no other
2508 // operations can be scheduled in between. E.g. without flagging the
2509 // operations together, a TOC access in the caller could be scheduled
2510 // between the load of the callee TOC and the branch to the callee, which
2511 // results in the TOC access going through the TOC of the callee instead
2512 // of going through the TOC of the caller, which leads to incorrect code.
2514 // Load the address of the function entry point from the function
2516 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
2517 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2518 InFlag.getNode() ? 3 : 2);
2519 Chain = LoadFuncPtr.getValue(1);
2520 InFlag = LoadFuncPtr.getValue(2);
2522 // Load environment pointer into r11.
2523 // Offset of the environment pointer within the function descriptor.
2524 SDValue PtrOff = DAG.getIntPtrConstant(16);
2526 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2527 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2529 Chain = LoadEnvPtr.getValue(1);
2530 InFlag = LoadEnvPtr.getValue(2);
2532 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2534 Chain = EnvVal.getValue(0);
2535 InFlag = EnvVal.getValue(1);
2537 // Load TOC of the callee into r2. We are using a target-specific load
2538 // with r2 hard coded, because the result of a target-independent load
2539 // would never go directly into r2, since r2 is a reserved register (which
2540 // prevents the register allocator from allocating it), resulting in an
2541 // additional register being allocated and an unnecessary move instruction
2543 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2544 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2546 Chain = LoadTOCPtr.getValue(0);
2547 InFlag = LoadTOCPtr.getValue(1);
2549 MTCTROps[0] = Chain;
2550 MTCTROps[1] = LoadFuncPtr;
2551 MTCTROps[2] = InFlag;
2554 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2555 2 + (InFlag.getNode() != 0));
2556 InFlag = Chain.getValue(1);
2559 NodeTys.push_back(MVT::Other);
2560 NodeTys.push_back(MVT::Glue);
2561 Ops.push_back(Chain);
2562 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2564 // Add CTR register as callee so a bctr can be emitted later.
2566 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2569 // If this is a direct call, pass the chain and the callee.
2570 if (Callee.getNode()) {
2571 Ops.push_back(Chain);
2572 Ops.push_back(Callee);
2574 // If this is a tail call add stack pointer delta.
2576 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2578 // Add argument registers to the end of the list so that they are known live
2580 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2581 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2582 RegsToPass[i].second.getValueType()));
2588 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2589 CallingConv::ID CallConv, bool isVarArg,
2590 const SmallVectorImpl<ISD::InputArg> &Ins,
2591 DebugLoc dl, SelectionDAG &DAG,
2592 SmallVectorImpl<SDValue> &InVals) const {
2594 SmallVector<CCValAssign, 16> RVLocs;
2595 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2596 RVLocs, *DAG.getContext());
2597 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2599 // Copy all of the result registers out of their specified physreg.
2600 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2601 CCValAssign &VA = RVLocs[i];
2602 EVT VT = VA.getValVT();
2603 assert(VA.isRegLoc() && "Can only return in registers!");
2604 Chain = DAG.getCopyFromReg(Chain, dl,
2605 VA.getLocReg(), VT, InFlag).getValue(1);
2606 InVals.push_back(Chain.getValue(0));
2607 InFlag = Chain.getValue(2);
2614 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2615 bool isTailCall, bool isVarArg,
2617 SmallVector<std::pair<unsigned, SDValue>, 8>
2619 SDValue InFlag, SDValue Chain,
2621 int SPDiff, unsigned NumBytes,
2622 const SmallVectorImpl<ISD::InputArg> &Ins,
2623 SmallVectorImpl<SDValue> &InVals) const {
2624 std::vector<EVT> NodeTys;
2625 SmallVector<SDValue, 8> Ops;
2626 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2627 isTailCall, RegsToPass, Ops, NodeTys,
2630 // When performing tail call optimization the callee pops its arguments off
2631 // the stack. Account for this here so these bytes can be pushed back on in
2632 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2633 int BytesCalleePops =
2634 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0;
2636 if (InFlag.getNode())
2637 Ops.push_back(InFlag);
2641 // If this is the first return lowered for this function, add the regs
2642 // to the liveout set for the function.
2643 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2644 SmallVector<CCValAssign, 16> RVLocs;
2645 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2647 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2648 for (unsigned i = 0; i != RVLocs.size(); ++i)
2649 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2652 assert(((Callee.getOpcode() == ISD::Register &&
2653 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2654 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2655 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2656 isa<ConstantSDNode>(Callee)) &&
2657 "Expecting an global address, external symbol, absolute value or register");
2659 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2662 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2663 InFlag = Chain.getValue(1);
2665 // Add a NOP immediately after the branch instruction when using the 64-bit
2666 // SVR4 ABI. At link time, if caller and callee are in a different module and
2667 // thus have a different TOC, the call will be replaced with a call to a stub
2668 // function which saves the current TOC, loads the TOC of the callee and
2669 // branches to the callee. The NOP will be replaced with a load instruction
2670 // which restores the TOC of the caller from the TOC save slot of the current
2671 // stack frame. If caller and callee belong to the same module (and have the
2672 // same TOC), the NOP will remain unchanged.
2673 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2674 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2675 if (CallOpc == PPCISD::BCTRL_SVR4) {
2676 // This is a call through a function pointer.
2677 // Restore the caller TOC from the save area into R2.
2678 // See PrepareCall() for more information about calls through function
2679 // pointers in the 64-bit SVR4 ABI.
2680 // We are using a target-specific load with r2 hard coded, because the
2681 // result of a target-independent load would never go directly into r2,
2682 // since r2 is a reserved register (which prevents the register allocator
2683 // from allocating it), resulting in an additional register being
2684 // allocated and an unnecessary move instruction being generated.
2685 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2686 InFlag = Chain.getValue(1);
2688 // Otherwise insert NOP.
2689 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Glue, InFlag);
2693 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2694 DAG.getIntPtrConstant(BytesCalleePops, true),
2697 InFlag = Chain.getValue(1);
2699 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2700 Ins, dl, DAG, InVals);
2704 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2705 CallingConv::ID CallConv, bool isVarArg,
2707 const SmallVectorImpl<ISD::OutputArg> &Outs,
2708 const SmallVectorImpl<SDValue> &OutVals,
2709 const SmallVectorImpl<ISD::InputArg> &Ins,
2710 DebugLoc dl, SelectionDAG &DAG,
2711 SmallVectorImpl<SDValue> &InVals) const {
2713 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2716 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
2717 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2718 isTailCall, Outs, OutVals, Ins,
2721 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2722 isTailCall, Outs, OutVals, Ins,
2727 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2728 CallingConv::ID CallConv, bool isVarArg,
2730 const SmallVectorImpl<ISD::OutputArg> &Outs,
2731 const SmallVectorImpl<SDValue> &OutVals,
2732 const SmallVectorImpl<ISD::InputArg> &Ins,
2733 DebugLoc dl, SelectionDAG &DAG,
2734 SmallVectorImpl<SDValue> &InVals) const {
2735 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2736 // of the 32-bit SVR4 ABI stack frame layout.
2738 assert((CallConv == CallingConv::C ||
2739 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2741 unsigned PtrByteSize = 4;
2743 MachineFunction &MF = DAG.getMachineFunction();
2745 // Mark this function as potentially containing a function that contains a
2746 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2747 // and restoring the callers stack pointer in this functions epilog. This is
2748 // done because by tail calling the called function might overwrite the value
2749 // in this function's (MF) stack pointer stack slot 0(SP).
2750 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2751 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2753 // Count how many bytes are to be pushed on the stack, including the linkage
2754 // area, parameter list area and the part of the local variable space which
2755 // contains copies of aggregates which are passed by value.
2757 // Assign locations to all of the outgoing arguments.
2758 SmallVector<CCValAssign, 16> ArgLocs;
2759 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2760 ArgLocs, *DAG.getContext());
2762 // Reserve space for the linkage area on the stack.
2763 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2766 // Handle fixed and variable vector arguments differently.
2767 // Fixed vector arguments go into registers as long as registers are
2768 // available. Variable vector arguments always go into memory.
2769 unsigned NumArgs = Outs.size();
2771 for (unsigned i = 0; i != NumArgs; ++i) {
2772 MVT ArgVT = Outs[i].VT;
2773 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2776 if (Outs[i].IsFixed) {
2777 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2780 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2786 errs() << "Call operand #" << i << " has unhandled type "
2787 << EVT(ArgVT).getEVTString() << "\n";
2789 llvm_unreachable(0);
2793 // All arguments are treated the same.
2794 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2797 // Assign locations to all of the outgoing aggregate by value arguments.
2798 SmallVector<CCValAssign, 16> ByValArgLocs;
2799 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2802 // Reserve stack space for the allocations in CCInfo.
2803 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2805 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2807 // Size of the linkage area, parameter list area and the part of the local
2808 // space variable where copies of aggregates which are passed by value are
2810 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2812 // Calculate by how many bytes the stack has to be adjusted in case of tail
2813 // call optimization.
2814 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2816 // Adjust the stack pointer for the new arguments...
2817 // These operations are automatically eliminated by the prolog/epilog pass
2818 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2819 SDValue CallSeqStart = Chain;
2821 // Load the return address and frame pointer so it can be moved somewhere else
2824 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2827 // Set up a copy of the stack pointer for use loading and storing any
2828 // arguments that may not fit in the registers available for argument
2830 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2832 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2833 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2834 SmallVector<SDValue, 8> MemOpChains;
2836 // Walk the register/memloc assignments, inserting copies/loads.
2837 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2840 CCValAssign &VA = ArgLocs[i];
2841 SDValue Arg = OutVals[i];
2842 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2844 if (Flags.isByVal()) {
2845 // Argument is an aggregate which is passed by value, thus we need to
2846 // create a copy of it in the local variable space of the current stack
2847 // frame (which is the stack frame of the caller) and pass the address of
2848 // this copy to the callee.
2849 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2850 CCValAssign &ByValVA = ByValArgLocs[j++];
2851 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2853 // Memory reserved in the local variable space of the callers stack frame.
2854 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2856 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2857 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2859 // Create a copy of the argument in the local area of the current
2861 SDValue MemcpyCall =
2862 CreateCopyOfByValArgument(Arg, PtrOff,
2863 CallSeqStart.getNode()->getOperand(0),
2866 // This must go outside the CALLSEQ_START..END.
2867 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2868 CallSeqStart.getNode()->getOperand(1));
2869 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2870 NewCallSeqStart.getNode());
2871 Chain = CallSeqStart = NewCallSeqStart;
2873 // Pass the address of the aggregate copy on the stack either in a
2874 // physical register or in the parameter list area of the current stack
2875 // frame to the callee.
2879 if (VA.isRegLoc()) {
2880 // Put argument in a physical register.
2881 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2883 // Put argument in the parameter list area of the current stack frame.
2884 assert(VA.isMemLoc());
2885 unsigned LocMemOffset = VA.getLocMemOffset();
2888 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2889 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2891 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2892 MachinePointerInfo(),
2895 // Calculate and remember argument location.
2896 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2902 if (!MemOpChains.empty())
2903 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2904 &MemOpChains[0], MemOpChains.size());
2906 // Build a sequence of copy-to-reg nodes chained together with token chain
2907 // and flag operands which copy the outgoing args into the appropriate regs.
2909 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2910 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2911 RegsToPass[i].second, InFlag);
2912 InFlag = Chain.getValue(1);
2915 // Set CR6 to true if this is a vararg call.
2917 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0);
2918 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2919 InFlag = Chain.getValue(1);
2923 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2924 false, TailCallArguments);
2926 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
2927 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
2932 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
2933 CallingConv::ID CallConv, bool isVarArg,
2935 const SmallVectorImpl<ISD::OutputArg> &Outs,
2936 const SmallVectorImpl<SDValue> &OutVals,
2937 const SmallVectorImpl<ISD::InputArg> &Ins,
2938 DebugLoc dl, SelectionDAG &DAG,
2939 SmallVectorImpl<SDValue> &InVals) const {
2941 unsigned NumOps = Outs.size();
2943 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2944 bool isPPC64 = PtrVT == MVT::i64;
2945 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2947 MachineFunction &MF = DAG.getMachineFunction();
2949 // Mark this function as potentially containing a function that contains a
2950 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2951 // and restoring the callers stack pointer in this functions epilog. This is
2952 // done because by tail calling the called function might overwrite the value
2953 // in this function's (MF) stack pointer stack slot 0(SP).
2954 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2955 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2957 unsigned nAltivecParamsAtEnd = 0;
2959 // Count how many bytes are to be pushed on the stack, including the linkage
2960 // area, and parameter passing area. We start with 24/48 bytes, which is
2961 // prereserved space for [SP][CR][LR][3 x unused].
2963 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2965 nAltivecParamsAtEnd);
2967 // Calculate by how many bytes the stack has to be adjusted in case of tail
2968 // call optimization.
2969 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2971 // To protect arguments on the stack from being clobbered in a tail call,
2972 // force all the loads to happen before doing any other lowering.
2974 Chain = DAG.getStackArgumentTokenFactor(Chain);
2976 // Adjust the stack pointer for the new arguments...
2977 // These operations are automatically eliminated by the prolog/epilog pass
2978 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2979 SDValue CallSeqStart = Chain;
2981 // Load the return address and frame pointer so it can be move somewhere else
2984 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2987 // Set up a copy of the stack pointer for use loading and storing any
2988 // arguments that may not fit in the registers available for argument
2992 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2994 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2996 // Figure out which arguments are going to go in registers, and which in
2997 // memory. Also, if this is a vararg function, floating point operations
2998 // must be stored to our stack, and loaded into integer regs as well, if
2999 // any integer regs are available for argument passing.
3000 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
3001 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3003 static const unsigned GPR_32[] = { // 32-bit registers.
3004 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3005 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3007 static const unsigned GPR_64[] = { // 64-bit registers.
3008 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3009 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3011 static const unsigned *FPR = GetFPR();
3013 static const unsigned VR[] = {
3014 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3015 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3017 const unsigned NumGPRs = array_lengthof(GPR_32);
3018 const unsigned NumFPRs = 13;
3019 const unsigned NumVRs = array_lengthof(VR);
3021 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
3023 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3024 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3026 SmallVector<SDValue, 8> MemOpChains;
3027 for (unsigned i = 0; i != NumOps; ++i) {
3028 SDValue Arg = OutVals[i];
3029 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3031 // PtrOff will be used to store the current argument to the stack if a
3032 // register cannot be found for it.
3035 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3037 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3039 // On PPC64, promote integers to 64-bit values.
3040 if (isPPC64 && Arg.getValueType() == MVT::i32) {
3041 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3042 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3043 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3046 // FIXME memcpy is used way more than necessary. Correctness first.
3047 if (Flags.isByVal()) {
3048 unsigned Size = Flags.getByValSize();
3049 if (Size==1 || Size==2) {
3050 // Very small objects are passed right-justified.
3051 // Everything else is passed left-justified.
3052 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3053 if (GPR_idx != NumGPRs) {
3054 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3055 MachinePointerInfo(), VT,
3057 MemOpChains.push_back(Load.getValue(1));
3058 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3060 ArgOffset += PtrByteSize;
3062 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3063 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3064 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3065 CallSeqStart.getNode()->getOperand(0),
3067 // This must go outside the CALLSEQ_START..END.
3068 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3069 CallSeqStart.getNode()->getOperand(1));
3070 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3071 NewCallSeqStart.getNode());
3072 Chain = CallSeqStart = NewCallSeqStart;
3073 ArgOffset += PtrByteSize;
3077 // Copy entire object into memory. There are cases where gcc-generated
3078 // code assumes it is there, even if it could be put entirely into
3079 // registers. (This is not what the doc says.)
3080 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3081 CallSeqStart.getNode()->getOperand(0),
3083 // This must go outside the CALLSEQ_START..END.
3084 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3085 CallSeqStart.getNode()->getOperand(1));
3086 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3087 Chain = CallSeqStart = NewCallSeqStart;
3088 // And copy the pieces of it that fit into registers.
3089 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3090 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3091 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3092 if (GPR_idx != NumGPRs) {
3093 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3094 MachinePointerInfo(),
3096 MemOpChains.push_back(Load.getValue(1));
3097 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3098 ArgOffset += PtrByteSize;
3100 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3107 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3108 default: llvm_unreachable("Unexpected ValueType for argument!");
3111 if (GPR_idx != NumGPRs) {
3112 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3114 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3115 isPPC64, isTailCall, false, MemOpChains,
3116 TailCallArguments, dl);
3118 ArgOffset += PtrByteSize;
3122 if (FPR_idx != NumFPRs) {
3123 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3126 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3127 MachinePointerInfo(), false, false, 0);
3128 MemOpChains.push_back(Store);
3130 // Float varargs are always shadowed in available integer registers
3131 if (GPR_idx != NumGPRs) {
3132 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3133 MachinePointerInfo(), false, false, 0);
3134 MemOpChains.push_back(Load.getValue(1));
3135 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3137 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3138 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3139 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3140 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3141 MachinePointerInfo(),
3143 MemOpChains.push_back(Load.getValue(1));
3144 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3147 // If we have any FPRs remaining, we may also have GPRs remaining.
3148 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3150 if (GPR_idx != NumGPRs)
3152 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3153 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3157 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3158 isPPC64, isTailCall, false, MemOpChains,
3159 TailCallArguments, dl);
3164 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3171 // These go aligned on the stack, or in the corresponding R registers
3172 // when within range. The Darwin PPC ABI doc claims they also go in
3173 // V registers; in fact gcc does this only for arguments that are
3174 // prototyped, not for those that match the ... We do it for all
3175 // arguments, seems to work.
3176 while (ArgOffset % 16 !=0) {
3177 ArgOffset += PtrByteSize;
3178 if (GPR_idx != NumGPRs)
3181 // We could elide this store in the case where the object fits
3182 // entirely in R registers. Maybe later.
3183 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3184 DAG.getConstant(ArgOffset, PtrVT));
3185 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3186 MachinePointerInfo(), false, false, 0);
3187 MemOpChains.push_back(Store);
3188 if (VR_idx != NumVRs) {
3189 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3190 MachinePointerInfo(),
3192 MemOpChains.push_back(Load.getValue(1));
3193 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3196 for (unsigned i=0; i<16; i+=PtrByteSize) {
3197 if (GPR_idx == NumGPRs)
3199 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3200 DAG.getConstant(i, PtrVT));
3201 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3203 MemOpChains.push_back(Load.getValue(1));
3204 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3209 // Non-varargs Altivec params generally go in registers, but have
3210 // stack space allocated at the end.
3211 if (VR_idx != NumVRs) {
3212 // Doesn't have GPR space allocated.
3213 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3214 } else if (nAltivecParamsAtEnd==0) {
3215 // We are emitting Altivec params in order.
3216 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3217 isPPC64, isTailCall, true, MemOpChains,
3218 TailCallArguments, dl);
3224 // If all Altivec parameters fit in registers, as they usually do,
3225 // they get stack space following the non-Altivec parameters. We
3226 // don't track this here because nobody below needs it.
3227 // If there are more Altivec parameters than fit in registers emit
3229 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3231 // Offset is aligned; skip 1st 12 params which go in V registers.
3232 ArgOffset = ((ArgOffset+15)/16)*16;
3234 for (unsigned i = 0; i != NumOps; ++i) {
3235 SDValue Arg = OutVals[i];
3236 EVT ArgType = Outs[i].VT;
3237 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3238 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3241 // We are emitting Altivec params in order.
3242 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3243 isPPC64, isTailCall, true, MemOpChains,
3244 TailCallArguments, dl);
3251 if (!MemOpChains.empty())
3252 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3253 &MemOpChains[0], MemOpChains.size());
3255 // Check if this is an indirect call (MTCTR/BCTRL).
3256 // See PrepareCall() for more information about calls through function
3257 // pointers in the 64-bit SVR4 ABI.
3258 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3259 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3260 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3261 !isBLACompatibleAddress(Callee, DAG)) {
3262 // Load r2 into a virtual register and store it to the TOC save area.
3263 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3264 // TOC save area offset.
3265 SDValue PtrOff = DAG.getIntPtrConstant(40);
3266 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3267 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
3271 // On Darwin, R12 must contain the address of an indirect callee. This does
3272 // not mean the MTCTR instruction must use R12; it's easier to model this as
3273 // an extra parameter, so do that.
3275 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3276 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3277 !isBLACompatibleAddress(Callee, DAG))
3278 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
3279 PPC::R12), Callee));
3281 // Build a sequence of copy-to-reg nodes chained together with token chain
3282 // and flag operands which copy the outgoing args into the appropriate regs.
3284 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3285 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3286 RegsToPass[i].second, InFlag);
3287 InFlag = Chain.getValue(1);
3291 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3292 FPOp, true, TailCallArguments);
3294 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3295 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3300 PPCTargetLowering::LowerReturn(SDValue Chain,
3301 CallingConv::ID CallConv, bool isVarArg,
3302 const SmallVectorImpl<ISD::OutputArg> &Outs,
3303 const SmallVectorImpl<SDValue> &OutVals,
3304 DebugLoc dl, SelectionDAG &DAG) const {
3306 SmallVector<CCValAssign, 16> RVLocs;
3307 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3308 RVLocs, *DAG.getContext());
3309 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3311 // If this is the first return lowered for this function, add the regs to the
3312 // liveout set for the function.
3313 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3314 for (unsigned i = 0; i != RVLocs.size(); ++i)
3315 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3320 // Copy the result values into the output registers.
3321 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3322 CCValAssign &VA = RVLocs[i];
3323 assert(VA.isRegLoc() && "Can only return in registers!");
3324 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3326 Flag = Chain.getValue(1);
3330 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3332 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3335 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3336 const PPCSubtarget &Subtarget) const {
3337 // When we pop the dynamic allocation we need to restore the SP link.
3338 DebugLoc dl = Op.getDebugLoc();
3340 // Get the corect type for pointers.
3341 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3343 // Construct the stack pointer operand.
3344 bool isPPC64 = Subtarget.isPPC64();
3345 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3346 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3348 // Get the operands for the STACKRESTORE.
3349 SDValue Chain = Op.getOperand(0);
3350 SDValue SaveSP = Op.getOperand(1);
3352 // Load the old link SP.
3353 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
3354 MachinePointerInfo(),
3357 // Restore the stack pointer.
3358 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3360 // Store the old link SP.
3361 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
3368 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3369 MachineFunction &MF = DAG.getMachineFunction();
3370 bool isPPC64 = PPCSubTarget.isPPC64();
3371 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3372 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3374 // Get current frame pointer save index. The users of this index will be
3375 // primarily DYNALLOC instructions.
3376 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3377 int RASI = FI->getReturnAddrSaveIndex();
3379 // If the frame pointer save index hasn't been defined yet.
3381 // Find out what the fix offset of the frame pointer save area.
3382 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
3383 // Allocate the frame index for frame pointer save area.
3384 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
3386 FI->setReturnAddrSaveIndex(RASI);
3388 return DAG.getFrameIndex(RASI, PtrVT);
3392 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3393 MachineFunction &MF = DAG.getMachineFunction();
3394 bool isPPC64 = PPCSubTarget.isPPC64();
3395 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3396 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3398 // Get current frame pointer save index. The users of this index will be
3399 // primarily DYNALLOC instructions.
3400 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3401 int FPSI = FI->getFramePointerSaveIndex();
3403 // If the frame pointer save index hasn't been defined yet.
3405 // Find out what the fix offset of the frame pointer save area.
3406 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
3409 // Allocate the frame index for frame pointer save area.
3410 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
3412 FI->setFramePointerSaveIndex(FPSI);
3414 return DAG.getFrameIndex(FPSI, PtrVT);
3417 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3419 const PPCSubtarget &Subtarget) const {
3421 SDValue Chain = Op.getOperand(0);
3422 SDValue Size = Op.getOperand(1);
3423 DebugLoc dl = Op.getDebugLoc();
3425 // Get the corect type for pointers.
3426 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3428 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3429 DAG.getConstant(0, PtrVT), Size);
3430 // Construct a node for the frame pointer save index.
3431 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3432 // Build a DYNALLOC node.
3433 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3434 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3435 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3438 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3440 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3441 // Not FP? Not a fsel.
3442 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3443 !Op.getOperand(2).getValueType().isFloatingPoint())
3446 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3448 // Cannot handle SETEQ/SETNE.
3449 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3451 EVT ResVT = Op.getValueType();
3452 EVT CmpVT = Op.getOperand(0).getValueType();
3453 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3454 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3455 DebugLoc dl = Op.getDebugLoc();
3457 // If the RHS of the comparison is a 0.0, we don't need to do the
3458 // subtraction at all.
3459 if (isFloatingPointZero(RHS))
3461 default: break; // SETUO etc aren't handled by fsel.
3464 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3467 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3468 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3469 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3472 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3475 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3476 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3477 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3478 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3483 default: break; // SETUO etc aren't handled by fsel.
3486 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3487 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3488 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3489 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3492 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3493 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3494 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3495 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3498 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3499 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3500 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3501 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3504 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3505 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3506 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3507 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3512 // FIXME: Split this code up when LegalizeDAGTypes lands.
3513 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3514 DebugLoc dl) const {
3515 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3516 SDValue Src = Op.getOperand(0);
3517 if (Src.getValueType() == MVT::f32)
3518 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3521 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3522 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3524 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3529 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3533 // Convert the FP value to an int value through memory.
3534 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3536 // Emit a store to the stack slot.
3537 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
3538 MachinePointerInfo(), false, false, 0);
3540 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3542 if (Op.getValueType() == MVT::i32)
3543 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3544 DAG.getConstant(4, FIPtr.getValueType()));
3545 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
3549 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
3550 SelectionDAG &DAG) const {
3551 DebugLoc dl = Op.getDebugLoc();
3552 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3553 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3556 if (Op.getOperand(0).getValueType() == MVT::i64) {
3557 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
3558 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3559 if (Op.getValueType() == MVT::f32)
3560 FP = DAG.getNode(ISD::FP_ROUND, dl,
3561 MVT::f32, FP, DAG.getIntPtrConstant(0));
3565 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3566 "Unhandled SINT_TO_FP type in custom expander!");
3567 // Since we only generate this in 64-bit mode, we can take advantage of
3568 // 64-bit registers. In particular, sign extend the input value into the
3569 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3570 // then lfd it and fcfid it.
3571 MachineFunction &MF = DAG.getMachineFunction();
3572 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3573 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3574 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3575 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3577 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3580 // STD the extended value into the stack slot.
3581 MachineMemOperand *MMO =
3582 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
3583 MachineMemOperand::MOStore, 8, 8);
3584 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3586 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3587 Ops, 4, MVT::i64, MMO);
3588 // Load the value as a double.
3589 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
3592 // FCFID it and return it.
3593 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3594 if (Op.getValueType() == MVT::f32)
3595 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3599 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3600 SelectionDAG &DAG) const {
3601 DebugLoc dl = Op.getDebugLoc();
3603 The rounding mode is in bits 30:31 of FPSR, and has the following
3610 FLT_ROUNDS, on the other hand, expects the following:
3617 To perform the conversion, we do:
3618 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3621 MachineFunction &MF = DAG.getMachineFunction();
3622 EVT VT = Op.getValueType();
3623 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3624 std::vector<EVT> NodeTys;
3625 SDValue MFFSreg, InFlag;
3627 // Save FP Control Word to register
3628 NodeTys.push_back(MVT::f64); // return register
3629 NodeTys.push_back(MVT::Glue); // unused in this context
3630 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3632 // Save FP register to stack slot
3633 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3634 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3635 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3636 StackSlot, MachinePointerInfo(), false, false,0);
3638 // Load FP Control Word from low 32 bits of stack slot.
3639 SDValue Four = DAG.getConstant(4, PtrVT);
3640 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3641 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
3644 // Transform as necessary
3646 DAG.getNode(ISD::AND, dl, MVT::i32,
3647 CWD, DAG.getConstant(3, MVT::i32));
3649 DAG.getNode(ISD::SRL, dl, MVT::i32,
3650 DAG.getNode(ISD::AND, dl, MVT::i32,
3651 DAG.getNode(ISD::XOR, dl, MVT::i32,
3652 CWD, DAG.getConstant(3, MVT::i32)),
3653 DAG.getConstant(3, MVT::i32)),
3654 DAG.getConstant(1, MVT::i32));
3657 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3659 return DAG.getNode((VT.getSizeInBits() < 16 ?
3660 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3663 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3664 EVT VT = Op.getValueType();
3665 unsigned BitWidth = VT.getSizeInBits();
3666 DebugLoc dl = Op.getDebugLoc();
3667 assert(Op.getNumOperands() == 3 &&
3668 VT == Op.getOperand(1).getValueType() &&
3671 // Expand into a bunch of logical ops. Note that these ops
3672 // depend on the PPC behavior for oversized shift amounts.
3673 SDValue Lo = Op.getOperand(0);
3674 SDValue Hi = Op.getOperand(1);
3675 SDValue Amt = Op.getOperand(2);
3676 EVT AmtVT = Amt.getValueType();
3678 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3679 DAG.getConstant(BitWidth, AmtVT), Amt);
3680 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3681 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3682 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3683 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3684 DAG.getConstant(-BitWidth, AmtVT));
3685 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3686 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3687 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3688 SDValue OutOps[] = { OutLo, OutHi };
3689 return DAG.getMergeValues(OutOps, 2, dl);
3692 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3693 EVT VT = Op.getValueType();
3694 DebugLoc dl = Op.getDebugLoc();
3695 unsigned BitWidth = VT.getSizeInBits();
3696 assert(Op.getNumOperands() == 3 &&
3697 VT == Op.getOperand(1).getValueType() &&
3700 // Expand into a bunch of logical ops. Note that these ops
3701 // depend on the PPC behavior for oversized shift amounts.
3702 SDValue Lo = Op.getOperand(0);
3703 SDValue Hi = Op.getOperand(1);
3704 SDValue Amt = Op.getOperand(2);
3705 EVT AmtVT = Amt.getValueType();
3707 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3708 DAG.getConstant(BitWidth, AmtVT), Amt);
3709 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3710 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3711 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3712 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3713 DAG.getConstant(-BitWidth, AmtVT));
3714 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3715 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3716 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3717 SDValue OutOps[] = { OutLo, OutHi };
3718 return DAG.getMergeValues(OutOps, 2, dl);
3721 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
3722 DebugLoc dl = Op.getDebugLoc();
3723 EVT VT = Op.getValueType();
3724 unsigned BitWidth = VT.getSizeInBits();
3725 assert(Op.getNumOperands() == 3 &&
3726 VT == Op.getOperand(1).getValueType() &&
3729 // Expand into a bunch of logical ops, followed by a select_cc.
3730 SDValue Lo = Op.getOperand(0);
3731 SDValue Hi = Op.getOperand(1);
3732 SDValue Amt = Op.getOperand(2);
3733 EVT AmtVT = Amt.getValueType();
3735 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3736 DAG.getConstant(BitWidth, AmtVT), Amt);
3737 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3738 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3739 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3740 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3741 DAG.getConstant(-BitWidth, AmtVT));
3742 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3743 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3744 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3745 Tmp4, Tmp6, ISD::SETLE);
3746 SDValue OutOps[] = { OutLo, OutHi };
3747 return DAG.getMergeValues(OutOps, 2, dl);
3750 //===----------------------------------------------------------------------===//
3751 // Vector related lowering.
3754 /// BuildSplatI - Build a canonical splati of Val with an element size of
3755 /// SplatSize. Cast the result to VT.
3756 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3757 SelectionDAG &DAG, DebugLoc dl) {
3758 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3760 static const EVT VTys[] = { // canonical VT to use for each size.
3761 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3764 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3766 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3770 EVT CanonicalVT = VTys[SplatSize-1];
3772 // Build a canonical splat for this value.
3773 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3774 SmallVector<SDValue, 8> Ops;
3775 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3776 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3777 &Ops[0], Ops.size());
3778 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
3781 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3782 /// specified intrinsic ID.
3783 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3784 SelectionDAG &DAG, DebugLoc dl,
3785 EVT DestVT = MVT::Other) {
3786 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3787 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3788 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3791 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3792 /// specified intrinsic ID.
3793 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3794 SDValue Op2, SelectionDAG &DAG,
3795 DebugLoc dl, EVT DestVT = MVT::Other) {
3796 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3797 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3798 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3802 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3803 /// amount. The result has the specified value type.
3804 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3805 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3806 // Force LHS/RHS to be the right type.
3807 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
3808 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
3811 for (unsigned i = 0; i != 16; ++i)
3813 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3814 return DAG.getNode(ISD::BITCAST, dl, VT, T);
3817 // If this is a case we can't handle, return null and let the default
3818 // expansion code take care of it. If we CAN select this case, and if it
3819 // selects to a single instruction, return Op. Otherwise, if we can codegen
3820 // this case more efficiently than a constant pool load, lower it to the
3821 // sequence of ops that should be used.
3822 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3823 SelectionDAG &DAG) const {
3824 DebugLoc dl = Op.getDebugLoc();
3825 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3826 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3828 // Check if this is a splat of a constant value.
3829 APInt APSplatBits, APSplatUndef;
3830 unsigned SplatBitSize;
3832 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3833 HasAnyUndefs, 0, true) || SplatBitSize > 32)
3836 unsigned SplatBits = APSplatBits.getZExtValue();
3837 unsigned SplatUndef = APSplatUndef.getZExtValue();
3838 unsigned SplatSize = SplatBitSize / 8;
3840 // First, handle single instruction cases.
3843 if (SplatBits == 0) {
3844 // Canonicalize all zero vectors to be v4i32.
3845 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3846 SDValue Z = DAG.getConstant(0, MVT::i32);
3847 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3848 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
3853 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3854 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3856 if (SextVal >= -16 && SextVal <= 15)
3857 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3860 // Two instruction sequences.
3862 // If this value is in the range [-32,30] and is even, use:
3863 // tmp = VSPLTI[bhw], result = add tmp, tmp
3864 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3865 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3866 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3867 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3870 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3871 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3873 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3874 // Make -1 and vspltisw -1:
3875 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3877 // Make the VSLW intrinsic, computing 0x8000_0000.
3878 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3881 // xor by OnesV to invert it.
3882 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3883 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3886 // Check to see if this is a wide variety of vsplti*, binop self cases.
3887 static const signed char SplatCsts[] = {
3888 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3889 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3892 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3893 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3894 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3895 int i = SplatCsts[idx];
3897 // Figure out what shift amount will be used by altivec if shifted by i in
3899 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3901 // vsplti + shl self.
3902 if (SextVal == (i << (int)TypeShiftAmt)) {
3903 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3904 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3905 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3906 Intrinsic::ppc_altivec_vslw
3908 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3909 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3912 // vsplti + srl self.
3913 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3914 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3915 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3916 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3917 Intrinsic::ppc_altivec_vsrw
3919 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3920 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3923 // vsplti + sra self.
3924 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3925 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3926 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3927 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3928 Intrinsic::ppc_altivec_vsraw
3930 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3931 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3934 // vsplti + rol self.
3935 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3936 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3937 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3938 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3939 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3940 Intrinsic::ppc_altivec_vrlw
3942 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3943 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3946 // t = vsplti c, result = vsldoi t, t, 1
3947 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) {
3948 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3949 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3951 // t = vsplti c, result = vsldoi t, t, 2
3952 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) {
3953 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3954 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3956 // t = vsplti c, result = vsldoi t, t, 3
3957 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
3958 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3959 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3963 // Three instruction sequences.
3965 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3966 if (SextVal >= 0 && SextVal <= 31) {
3967 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3968 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3969 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3970 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
3972 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3973 if (SextVal >= -31 && SextVal <= 0) {
3974 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3975 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3976 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3977 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
3983 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3984 /// the specified operations to build the shuffle.
3985 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3986 SDValue RHS, SelectionDAG &DAG,
3988 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3989 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3990 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3993 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4005 if (OpNum == OP_COPY) {
4006 if (LHSID == (1*9+2)*9+3) return LHS;
4007 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4011 SDValue OpLHS, OpRHS;
4012 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4013 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4017 default: llvm_unreachable("Unknown i32 permute!");
4019 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
4020 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
4021 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
4022 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
4025 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
4026 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
4027 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
4028 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
4031 for (unsigned i = 0; i != 16; ++i)
4032 ShufIdxs[i] = (i&3)+0;
4035 for (unsigned i = 0; i != 16; ++i)
4036 ShufIdxs[i] = (i&3)+4;
4039 for (unsigned i = 0; i != 16; ++i)
4040 ShufIdxs[i] = (i&3)+8;
4043 for (unsigned i = 0; i != 16; ++i)
4044 ShufIdxs[i] = (i&3)+12;
4047 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4049 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4051 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4053 EVT VT = OpLHS.getValueType();
4054 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
4055 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
4056 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
4057 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4060 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
4061 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
4062 /// return the code it can be lowered into. Worst case, it can always be
4063 /// lowered into a vperm.
4064 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4065 SelectionDAG &DAG) const {
4066 DebugLoc dl = Op.getDebugLoc();
4067 SDValue V1 = Op.getOperand(0);
4068 SDValue V2 = Op.getOperand(1);
4069 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4070 EVT VT = Op.getValueType();
4072 // Cases that are handled by instructions that take permute immediates
4073 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4074 // selected by the instruction selector.
4075 if (V2.getOpcode() == ISD::UNDEF) {
4076 if (PPC::isSplatShuffleMask(SVOp, 1) ||
4077 PPC::isSplatShuffleMask(SVOp, 2) ||
4078 PPC::isSplatShuffleMask(SVOp, 4) ||
4079 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4080 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4081 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4082 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4083 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4084 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4085 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4086 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4087 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4092 // Altivec has a variety of "shuffle immediates" that take two vector inputs
4093 // and produce a fixed permutation. If any of these match, do not lower to
4095 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4096 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4097 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4098 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4099 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4100 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4101 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4102 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4103 PPC::isVMRGHShuffleMask(SVOp, 4, false))
4106 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
4107 // perfect shuffle table to emit an optimal matching sequence.
4108 SmallVector<int, 16> PermMask;
4109 SVOp->getMask(PermMask);
4111 unsigned PFIndexes[4];
4112 bool isFourElementShuffle = true;
4113 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4114 unsigned EltNo = 8; // Start out undef.
4115 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
4116 if (PermMask[i*4+j] < 0)
4117 continue; // Undef, ignore it.
4119 unsigned ByteSource = PermMask[i*4+j];
4120 if ((ByteSource & 3) != j) {
4121 isFourElementShuffle = false;
4126 EltNo = ByteSource/4;
4127 } else if (EltNo != ByteSource/4) {
4128 isFourElementShuffle = false;
4132 PFIndexes[i] = EltNo;
4135 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4136 // perfect shuffle vector to determine if it is cost effective to do this as
4137 // discrete instructions, or whether we should use a vperm.
4138 if (isFourElementShuffle) {
4139 // Compute the index in the perfect shuffle table.
4140 unsigned PFTableIndex =
4141 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4143 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4144 unsigned Cost = (PFEntry >> 30);
4146 // Determining when to avoid vperm is tricky. Many things affect the cost
4147 // of vperm, particularly how many times the perm mask needs to be computed.
4148 // For example, if the perm mask can be hoisted out of a loop or is already
4149 // used (perhaps because there are multiple permutes with the same shuffle
4150 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
4151 // the loop requires an extra register.
4153 // As a compromise, we only emit discrete instructions if the shuffle can be
4154 // generated in 3 or fewer operations. When we have loop information
4155 // available, if this block is within a loop, we should avoid using vperm
4156 // for 3-operation perms and use a constant pool load instead.
4158 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4161 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4162 // vector that will get spilled to the constant pool.
4163 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4165 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4166 // that it is in input element units, not in bytes. Convert now.
4167 EVT EltVT = V1.getValueType().getVectorElementType();
4168 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4170 SmallVector<SDValue, 16> ResultMask;
4171 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4172 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4174 for (unsigned j = 0; j != BytesPerElement; ++j)
4175 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4179 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4180 &ResultMask[0], ResultMask.size());
4181 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4184 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4185 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4186 /// information about the intrinsic.
4187 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4189 unsigned IntrinsicID =
4190 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4193 switch (IntrinsicID) {
4194 default: return false;
4195 // Comparison predicates.
4196 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4197 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4198 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4199 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4200 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4201 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4202 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4203 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4204 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4205 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4206 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4207 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4208 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4210 // Normal Comparisons.
4211 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4212 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4213 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4214 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4215 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4216 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4217 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4218 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4219 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4220 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4221 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4222 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4223 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4228 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4229 /// lower, do it, otherwise return null.
4230 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4231 SelectionDAG &DAG) const {
4232 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4233 // opcode number of the comparison.
4234 DebugLoc dl = Op.getDebugLoc();
4237 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4238 return SDValue(); // Don't custom lower most intrinsics.
4240 // If this is a non-dot comparison, make the VCMP node and we are done.
4242 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4243 Op.getOperand(1), Op.getOperand(2),
4244 DAG.getConstant(CompareOpc, MVT::i32));
4245 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
4248 // Create the PPCISD altivec 'dot' comparison node.
4250 Op.getOperand(2), // LHS
4251 Op.getOperand(3), // RHS
4252 DAG.getConstant(CompareOpc, MVT::i32)
4254 std::vector<EVT> VTs;
4255 VTs.push_back(Op.getOperand(2).getValueType());
4256 VTs.push_back(MVT::Glue);
4257 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4259 // Now that we have the comparison, emit a copy from the CR to a GPR.
4260 // This is flagged to the above dot comparison.
4261 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4262 DAG.getRegister(PPC::CR6, MVT::i32),
4263 CompNode.getValue(1));
4265 // Unpack the result based on how the target uses it.
4266 unsigned BitNo; // Bit # of CR6.
4267 bool InvertBit; // Invert result?
4268 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4269 default: // Can't happen, don't crash on invalid number though.
4270 case 0: // Return the value of the EQ bit of CR6.
4271 BitNo = 0; InvertBit = false;
4273 case 1: // Return the inverted value of the EQ bit of CR6.
4274 BitNo = 0; InvertBit = true;
4276 case 2: // Return the value of the LT bit of CR6.
4277 BitNo = 2; InvertBit = false;
4279 case 3: // Return the inverted value of the LT bit of CR6.
4280 BitNo = 2; InvertBit = true;
4284 // Shift the bit into the low position.
4285 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4286 DAG.getConstant(8-(3-BitNo), MVT::i32));
4288 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4289 DAG.getConstant(1, MVT::i32));
4291 // If we are supposed to, toggle the bit.
4293 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4294 DAG.getConstant(1, MVT::i32));
4298 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4299 SelectionDAG &DAG) const {
4300 DebugLoc dl = Op.getDebugLoc();
4301 // Create a stack slot that is 16-byte aligned.
4302 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4303 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4304 EVT PtrVT = getPointerTy();
4305 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4307 // Store the input value into Value#0 of the stack slot.
4308 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4309 Op.getOperand(0), FIdx, MachinePointerInfo(),
4312 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
4316 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
4317 DebugLoc dl = Op.getDebugLoc();
4318 if (Op.getValueType() == MVT::v4i32) {
4319 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4321 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4322 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4324 SDValue RHSSwap = // = vrlw RHS, 16
4325 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4327 // Shrinkify inputs to v8i16.
4328 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
4329 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
4330 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
4332 // Low parts multiplied together, generating 32-bit results (we ignore the
4334 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4335 LHS, RHS, DAG, dl, MVT::v4i32);
4337 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4338 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4339 // Shift the high parts up 16 bits.
4340 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4342 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4343 } else if (Op.getValueType() == MVT::v8i16) {
4344 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4346 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4348 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4349 LHS, RHS, Zero, DAG, dl);
4350 } else if (Op.getValueType() == MVT::v16i8) {
4351 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4353 // Multiply the even 8-bit parts, producing 16-bit sums.
4354 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4355 LHS, RHS, DAG, dl, MVT::v8i16);
4356 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
4358 // Multiply the odd 8-bit parts, producing 16-bit sums.
4359 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4360 LHS, RHS, DAG, dl, MVT::v8i16);
4361 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
4363 // Merge the results together.
4365 for (unsigned i = 0; i != 8; ++i) {
4367 Ops[i*2+1] = 2*i+1+16;
4369 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4371 llvm_unreachable("Unknown mul to lower!");
4375 /// LowerOperation - Provide custom lowering hooks for some operations.
4377 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4378 switch (Op.getOpcode()) {
4379 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4380 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4381 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4382 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4383 case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for PPC");
4384 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4385 case ISD::SETCC: return LowerSETCC(Op, DAG);
4386 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4388 return LowerVASTART(Op, DAG, PPCSubTarget);
4391 return LowerVAARG(Op, DAG, PPCSubTarget);
4393 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4394 case ISD::DYNAMIC_STACKALLOC:
4395 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4397 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4398 case ISD::FP_TO_UINT:
4399 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4401 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4402 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4404 // Lower 64-bit shifts.
4405 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4406 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4407 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4409 // Vector-related lowering.
4410 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4411 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4412 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4413 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4414 case ISD::MUL: return LowerMUL(Op, DAG);
4416 // Frame & Return address.
4417 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4418 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4423 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4424 SmallVectorImpl<SDValue>&Results,
4425 SelectionDAG &DAG) const {
4426 DebugLoc dl = N->getDebugLoc();
4427 switch (N->getOpcode()) {
4429 assert(false && "Do not know how to custom type legalize this operation!");
4431 case ISD::FP_ROUND_INREG: {
4432 assert(N->getValueType(0) == MVT::ppcf128);
4433 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4434 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4435 MVT::f64, N->getOperand(0),
4436 DAG.getIntPtrConstant(0));
4437 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4438 MVT::f64, N->getOperand(0),
4439 DAG.getIntPtrConstant(1));
4441 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4442 // of the long double, and puts FPSCR back the way it was. We do not
4443 // actually model FPSCR.
4444 std::vector<EVT> NodeTys;
4445 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4447 NodeTys.push_back(MVT::f64); // Return register
4448 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns
4449 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4450 MFFSreg = Result.getValue(0);
4451 InFlag = Result.getValue(1);
4454 NodeTys.push_back(MVT::Glue); // Returns a flag
4455 Ops[0] = DAG.getConstant(31, MVT::i32);
4457 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4458 InFlag = Result.getValue(0);
4461 NodeTys.push_back(MVT::Glue); // Returns a flag
4462 Ops[0] = DAG.getConstant(30, MVT::i32);
4464 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4465 InFlag = Result.getValue(0);
4468 NodeTys.push_back(MVT::f64); // result of add
4469 NodeTys.push_back(MVT::Glue); // Returns a flag
4473 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4474 FPreg = Result.getValue(0);
4475 InFlag = Result.getValue(1);
4478 NodeTys.push_back(MVT::f64);
4479 Ops[0] = DAG.getConstant(1, MVT::i32);
4483 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4484 FPreg = Result.getValue(0);
4486 // We know the low half is about to be thrown away, so just use something
4488 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4492 case ISD::FP_TO_SINT:
4493 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4499 //===----------------------------------------------------------------------===//
4500 // Other Lowering Code
4501 //===----------------------------------------------------------------------===//
4504 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4505 bool is64bit, unsigned BinOpcode) const {
4506 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4507 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4509 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4510 MachineFunction *F = BB->getParent();
4511 MachineFunction::iterator It = BB;
4514 unsigned dest = MI->getOperand(0).getReg();
4515 unsigned ptrA = MI->getOperand(1).getReg();
4516 unsigned ptrB = MI->getOperand(2).getReg();
4517 unsigned incr = MI->getOperand(3).getReg();
4518 DebugLoc dl = MI->getDebugLoc();
4520 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4521 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4522 F->insert(It, loopMBB);
4523 F->insert(It, exitMBB);
4524 exitMBB->splice(exitMBB->begin(), BB,
4525 llvm::next(MachineBasicBlock::iterator(MI)),
4527 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4529 MachineRegisterInfo &RegInfo = F->getRegInfo();
4530 unsigned TmpReg = (!BinOpcode) ? incr :
4531 RegInfo.createVirtualRegister(
4532 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4533 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4537 // fallthrough --> loopMBB
4538 BB->addSuccessor(loopMBB);
4541 // l[wd]arx dest, ptr
4542 // add r0, dest, incr
4543 // st[wd]cx. r0, ptr
4545 // fallthrough --> exitMBB
4547 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4548 .addReg(ptrA).addReg(ptrB);
4550 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4551 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4552 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4553 BuildMI(BB, dl, TII->get(PPC::BCC))
4554 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4555 BB->addSuccessor(loopMBB);
4556 BB->addSuccessor(exitMBB);
4565 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4566 MachineBasicBlock *BB,
4567 bool is8bit, // operation
4568 unsigned BinOpcode) const {
4569 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4570 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4571 // In 64 bit mode we have to use 64 bits for addresses, even though the
4572 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4573 // registers without caring whether they're 32 or 64, but here we're
4574 // doing actual arithmetic on the addresses.
4575 bool is64bit = PPCSubTarget.isPPC64();
4576 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
4578 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4579 MachineFunction *F = BB->getParent();
4580 MachineFunction::iterator It = BB;
4583 unsigned dest = MI->getOperand(0).getReg();
4584 unsigned ptrA = MI->getOperand(1).getReg();
4585 unsigned ptrB = MI->getOperand(2).getReg();
4586 unsigned incr = MI->getOperand(3).getReg();
4587 DebugLoc dl = MI->getDebugLoc();
4589 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4590 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4591 F->insert(It, loopMBB);
4592 F->insert(It, exitMBB);
4593 exitMBB->splice(exitMBB->begin(), BB,
4594 llvm::next(MachineBasicBlock::iterator(MI)),
4596 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4598 MachineRegisterInfo &RegInfo = F->getRegInfo();
4599 const TargetRegisterClass *RC =
4600 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4601 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4602 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4603 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4604 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4605 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4606 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4607 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4608 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4609 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4610 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4611 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4612 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4614 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4618 // fallthrough --> loopMBB
4619 BB->addSuccessor(loopMBB);
4621 // The 4-byte load must be aligned, while a char or short may be
4622 // anywhere in the word. Hence all this nasty bookkeeping code.
4623 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4624 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4625 // xori shift, shift1, 24 [16]
4626 // rlwinm ptr, ptr1, 0, 0, 29
4627 // slw incr2, incr, shift
4628 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4629 // slw mask, mask2, shift
4631 // lwarx tmpDest, ptr
4632 // add tmp, tmpDest, incr2
4633 // andc tmp2, tmpDest, mask
4634 // and tmp3, tmp, mask
4635 // or tmp4, tmp3, tmp2
4638 // fallthrough --> exitMBB
4639 // srw dest, tmpDest, shift
4640 if (ptrA != ZeroReg) {
4641 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4642 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4643 .addReg(ptrA).addReg(ptrB);
4647 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4648 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4649 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4650 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4652 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4653 .addReg(Ptr1Reg).addImm(0).addImm(61);
4655 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4656 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4657 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4658 .addReg(incr).addReg(ShiftReg);
4660 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4662 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4663 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4665 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4666 .addReg(Mask2Reg).addReg(ShiftReg);
4669 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4670 .addReg(ZeroReg).addReg(PtrReg);
4672 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4673 .addReg(Incr2Reg).addReg(TmpDestReg);
4674 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4675 .addReg(TmpDestReg).addReg(MaskReg);
4676 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4677 .addReg(TmpReg).addReg(MaskReg);
4678 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4679 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4680 BuildMI(BB, dl, TII->get(PPC::STWCX))
4681 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
4682 BuildMI(BB, dl, TII->get(PPC::BCC))
4683 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4684 BB->addSuccessor(loopMBB);
4685 BB->addSuccessor(exitMBB);
4690 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
4696 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4697 MachineBasicBlock *BB) const {
4698 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4700 // To "insert" these instructions we actually have to insert their
4701 // control-flow patterns.
4702 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4703 MachineFunction::iterator It = BB;
4706 MachineFunction *F = BB->getParent();
4708 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4709 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4710 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4711 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4712 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4714 // The incoming instruction knows the destination vreg to set, the
4715 // condition code register to branch on, the true/false values to
4716 // select between, and a branch opcode to use.
4721 // cmpTY ccX, r1, r2
4723 // fallthrough --> copy0MBB
4724 MachineBasicBlock *thisMBB = BB;
4725 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4726 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4727 unsigned SelectPred = MI->getOperand(4).getImm();
4728 DebugLoc dl = MI->getDebugLoc();
4729 F->insert(It, copy0MBB);
4730 F->insert(It, sinkMBB);
4732 // Transfer the remainder of BB and its successor edges to sinkMBB.
4733 sinkMBB->splice(sinkMBB->begin(), BB,
4734 llvm::next(MachineBasicBlock::iterator(MI)),
4736 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4738 // Next, add the true and fallthrough blocks as its successors.
4739 BB->addSuccessor(copy0MBB);
4740 BB->addSuccessor(sinkMBB);
4742 BuildMI(BB, dl, TII->get(PPC::BCC))
4743 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4746 // %FalseValue = ...
4747 // # fallthrough to sinkMBB
4750 // Update machine-CFG edges
4751 BB->addSuccessor(sinkMBB);
4754 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4757 BuildMI(*BB, BB->begin(), dl,
4758 TII->get(PPC::PHI), MI->getOperand(0).getReg())
4759 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4760 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4762 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4763 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4764 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4765 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4766 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4767 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4768 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4769 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4772 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4774 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4775 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4776 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4777 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4778 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4781 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4783 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4784 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4785 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4786 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4787 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4789 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4790 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4791 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4792 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4793 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4794 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4795 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4796 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4798 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4799 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4800 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4801 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4802 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4803 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4804 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4805 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4807 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4808 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4809 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4810 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4811 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4812 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4813 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4814 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4816 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4817 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4818 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4819 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4820 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4821 BB = EmitAtomicBinary(MI, BB, false, 0);
4822 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4823 BB = EmitAtomicBinary(MI, BB, true, 0);
4825 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4826 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4827 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4829 unsigned dest = MI->getOperand(0).getReg();
4830 unsigned ptrA = MI->getOperand(1).getReg();
4831 unsigned ptrB = MI->getOperand(2).getReg();
4832 unsigned oldval = MI->getOperand(3).getReg();
4833 unsigned newval = MI->getOperand(4).getReg();
4834 DebugLoc dl = MI->getDebugLoc();
4836 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4837 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4838 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4839 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4840 F->insert(It, loop1MBB);
4841 F->insert(It, loop2MBB);
4842 F->insert(It, midMBB);
4843 F->insert(It, exitMBB);
4844 exitMBB->splice(exitMBB->begin(), BB,
4845 llvm::next(MachineBasicBlock::iterator(MI)),
4847 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4851 // fallthrough --> loopMBB
4852 BB->addSuccessor(loop1MBB);
4855 // l[wd]arx dest, ptr
4856 // cmp[wd] dest, oldval
4859 // st[wd]cx. newval, ptr
4863 // st[wd]cx. dest, ptr
4866 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4867 .addReg(ptrA).addReg(ptrB);
4868 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4869 .addReg(oldval).addReg(dest);
4870 BuildMI(BB, dl, TII->get(PPC::BCC))
4871 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4872 BB->addSuccessor(loop2MBB);
4873 BB->addSuccessor(midMBB);
4876 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4877 .addReg(newval).addReg(ptrA).addReg(ptrB);
4878 BuildMI(BB, dl, TII->get(PPC::BCC))
4879 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4880 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4881 BB->addSuccessor(loop1MBB);
4882 BB->addSuccessor(exitMBB);
4885 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4886 .addReg(dest).addReg(ptrA).addReg(ptrB);
4887 BB->addSuccessor(exitMBB);
4892 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4893 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4894 // We must use 64-bit registers for addresses when targeting 64-bit,
4895 // since we're actually doing arithmetic on them. Other registers
4897 bool is64bit = PPCSubTarget.isPPC64();
4898 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4900 unsigned dest = MI->getOperand(0).getReg();
4901 unsigned ptrA = MI->getOperand(1).getReg();
4902 unsigned ptrB = MI->getOperand(2).getReg();
4903 unsigned oldval = MI->getOperand(3).getReg();
4904 unsigned newval = MI->getOperand(4).getReg();
4905 DebugLoc dl = MI->getDebugLoc();
4907 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4908 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4909 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4910 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4911 F->insert(It, loop1MBB);
4912 F->insert(It, loop2MBB);
4913 F->insert(It, midMBB);
4914 F->insert(It, exitMBB);
4915 exitMBB->splice(exitMBB->begin(), BB,
4916 llvm::next(MachineBasicBlock::iterator(MI)),
4918 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4920 MachineRegisterInfo &RegInfo = F->getRegInfo();
4921 const TargetRegisterClass *RC =
4922 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4923 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4924 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4925 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4926 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4927 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4928 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4929 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4930 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4931 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4932 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4933 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4934 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4935 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4936 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4938 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4939 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
4942 // fallthrough --> loopMBB
4943 BB->addSuccessor(loop1MBB);
4945 // The 4-byte load must be aligned, while a char or short may be
4946 // anywhere in the word. Hence all this nasty bookkeeping code.
4947 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4948 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4949 // xori shift, shift1, 24 [16]
4950 // rlwinm ptr, ptr1, 0, 0, 29
4951 // slw newval2, newval, shift
4952 // slw oldval2, oldval,shift
4953 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4954 // slw mask, mask2, shift
4955 // and newval3, newval2, mask
4956 // and oldval3, oldval2, mask
4958 // lwarx tmpDest, ptr
4959 // and tmp, tmpDest, mask
4960 // cmpw tmp, oldval3
4963 // andc tmp2, tmpDest, mask
4964 // or tmp4, tmp2, newval3
4969 // stwcx. tmpDest, ptr
4971 // srw dest, tmpDest, shift
4972 if (ptrA != ZeroReg) {
4973 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4974 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4975 .addReg(ptrA).addReg(ptrB);
4979 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4980 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4981 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4982 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4984 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4985 .addReg(Ptr1Reg).addImm(0).addImm(61);
4987 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4988 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4989 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4990 .addReg(newval).addReg(ShiftReg);
4991 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4992 .addReg(oldval).addReg(ShiftReg);
4994 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4996 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4997 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4998 .addReg(Mask3Reg).addImm(65535);
5000 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5001 .addReg(Mask2Reg).addReg(ShiftReg);
5002 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
5003 .addReg(NewVal2Reg).addReg(MaskReg);
5004 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
5005 .addReg(OldVal2Reg).addReg(MaskReg);
5008 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5009 .addReg(ZeroReg).addReg(PtrReg);
5010 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
5011 .addReg(TmpDestReg).addReg(MaskReg);
5012 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
5013 .addReg(TmpReg).addReg(OldVal3Reg);
5014 BuildMI(BB, dl, TII->get(PPC::BCC))
5015 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5016 BB->addSuccessor(loop2MBB);
5017 BB->addSuccessor(midMBB);
5020 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
5021 .addReg(TmpDestReg).addReg(MaskReg);
5022 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
5023 .addReg(Tmp2Reg).addReg(NewVal3Reg);
5024 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
5025 .addReg(ZeroReg).addReg(PtrReg);
5026 BuildMI(BB, dl, TII->get(PPC::BCC))
5027 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5028 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5029 BB->addSuccessor(loop1MBB);
5030 BB->addSuccessor(exitMBB);
5033 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
5034 .addReg(ZeroReg).addReg(PtrReg);
5035 BB->addSuccessor(exitMBB);
5040 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
5043 llvm_unreachable("Unexpected instr type to insert");
5046 MI->eraseFromParent(); // The pseudo instruction is gone now.
5050 //===----------------------------------------------------------------------===//
5051 // Target Optimization Hooks
5052 //===----------------------------------------------------------------------===//
5054 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
5055 DAGCombinerInfo &DCI) const {
5056 const TargetMachine &TM = getTargetMachine();
5057 SelectionDAG &DAG = DCI.DAG;
5058 DebugLoc dl = N->getDebugLoc();
5059 switch (N->getOpcode()) {
5062 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5063 if (C->isNullValue()) // 0 << V -> 0.
5064 return N->getOperand(0);
5068 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5069 if (C->isNullValue()) // 0 >>u V -> 0.
5070 return N->getOperand(0);
5074 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5075 if (C->isNullValue() || // 0 >>s V -> 0.
5076 C->isAllOnesValue()) // -1 >>s V -> -1.
5077 return N->getOperand(0);
5081 case ISD::SINT_TO_FP:
5082 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5083 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5084 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5085 // We allow the src/dst to be either f32/f64, but the intermediate
5086 // type must be i64.
5087 if (N->getOperand(0).getValueType() == MVT::i64 &&
5088 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5089 SDValue Val = N->getOperand(0).getOperand(0);
5090 if (Val.getValueType() == MVT::f32) {
5091 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5092 DCI.AddToWorklist(Val.getNode());
5095 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5096 DCI.AddToWorklist(Val.getNode());
5097 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5098 DCI.AddToWorklist(Val.getNode());
5099 if (N->getValueType(0) == MVT::f32) {
5100 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5101 DAG.getIntPtrConstant(0));
5102 DCI.AddToWorklist(Val.getNode());
5105 } else if (N->getOperand(0).getValueType() == MVT::i32) {
5106 // If the intermediate type is i32, we can avoid the load/store here
5113 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5114 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5115 !cast<StoreSDNode>(N)->isTruncatingStore() &&
5116 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5117 N->getOperand(1).getValueType() == MVT::i32 &&
5118 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5119 SDValue Val = N->getOperand(1).getOperand(0);
5120 if (Val.getValueType() == MVT::f32) {
5121 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5122 DCI.AddToWorklist(Val.getNode());
5124 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5125 DCI.AddToWorklist(Val.getNode());
5127 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5128 N->getOperand(2), N->getOperand(3));
5129 DCI.AddToWorklist(Val.getNode());
5133 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
5134 if (cast<StoreSDNode>(N)->isUnindexed() &&
5135 N->getOperand(1).getOpcode() == ISD::BSWAP &&
5136 N->getOperand(1).getNode()->hasOneUse() &&
5137 (N->getOperand(1).getValueType() == MVT::i32 ||
5138 N->getOperand(1).getValueType() == MVT::i16)) {
5139 SDValue BSwapOp = N->getOperand(1).getOperand(0);
5140 // Do an any-extend to 32-bits if this is a half-word input.
5141 if (BSwapOp.getValueType() == MVT::i16)
5142 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5145 N->getOperand(0), BSwapOp, N->getOperand(2),
5146 DAG.getValueType(N->getOperand(1).getValueType())
5149 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5150 Ops, array_lengthof(Ops),
5151 cast<StoreSDNode>(N)->getMemoryVT(),
5152 cast<StoreSDNode>(N)->getMemOperand());
5156 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5157 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5158 N->getOperand(0).hasOneUse() &&
5159 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5160 SDValue Load = N->getOperand(0);
5161 LoadSDNode *LD = cast<LoadSDNode>(Load);
5162 // Create the byte-swapping load.
5164 LD->getChain(), // Chain
5165 LD->getBasePtr(), // Ptr
5166 DAG.getValueType(N->getValueType(0)) // VT
5169 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5170 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5171 LD->getMemoryVT(), LD->getMemOperand());
5173 // If this is an i16 load, insert the truncate.
5174 SDValue ResVal = BSLoad;
5175 if (N->getValueType(0) == MVT::i16)
5176 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5178 // First, combine the bswap away. This makes the value produced by the
5180 DCI.CombineTo(N, ResVal);
5182 // Next, combine the load away, we give it a bogus result value but a real
5183 // chain result. The result value is dead because the bswap is dead.
5184 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5186 // Return N so it doesn't get rechecked!
5187 return SDValue(N, 0);
5191 case PPCISD::VCMP: {
5192 // If a VCMPo node already exists with exactly the same operands as this
5193 // node, use its result instead of this node (VCMPo computes both a CR6 and
5194 // a normal output).
5196 if (!N->getOperand(0).hasOneUse() &&
5197 !N->getOperand(1).hasOneUse() &&
5198 !N->getOperand(2).hasOneUse()) {
5200 // Scan all of the users of the LHS, looking for VCMPo's that match.
5201 SDNode *VCMPoNode = 0;
5203 SDNode *LHSN = N->getOperand(0).getNode();
5204 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5206 if (UI->getOpcode() == PPCISD::VCMPo &&
5207 UI->getOperand(1) == N->getOperand(1) &&
5208 UI->getOperand(2) == N->getOperand(2) &&
5209 UI->getOperand(0) == N->getOperand(0)) {
5214 // If there is no VCMPo node, or if the flag value has a single use, don't
5216 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5219 // Look at the (necessarily single) use of the flag value. If it has a
5220 // chain, this transformation is more complex. Note that multiple things
5221 // could use the value result, which we should ignore.
5222 SDNode *FlagUser = 0;
5223 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5224 FlagUser == 0; ++UI) {
5225 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5227 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5228 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5235 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5236 // give up for right now.
5237 if (FlagUser->getOpcode() == PPCISD::MFCR)
5238 return SDValue(VCMPoNode, 0);
5243 // If this is a branch on an altivec predicate comparison, lower this so
5244 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5245 // lowering is done pre-legalize, because the legalizer lowers the predicate
5246 // compare down to code that is difficult to reassemble.
5247 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5248 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5252 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5253 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5254 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5255 assert(isDot && "Can't compare against a vector result!");
5257 // If this is a comparison against something other than 0/1, then we know
5258 // that the condition is never/always true.
5259 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5260 if (Val != 0 && Val != 1) {
5261 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5262 return N->getOperand(0);
5263 // Always !=, turn it into an unconditional branch.
5264 return DAG.getNode(ISD::BR, dl, MVT::Other,
5265 N->getOperand(0), N->getOperand(4));
5268 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5270 // Create the PPCISD altivec 'dot' comparison node.
5271 std::vector<EVT> VTs;
5273 LHS.getOperand(2), // LHS of compare
5274 LHS.getOperand(3), // RHS of compare
5275 DAG.getConstant(CompareOpc, MVT::i32)
5277 VTs.push_back(LHS.getOperand(2).getValueType());
5278 VTs.push_back(MVT::Glue);
5279 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5281 // Unpack the result based on how the target uses it.
5282 PPC::Predicate CompOpc;
5283 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5284 default: // Can't happen, don't crash on invalid number though.
5285 case 0: // Branch on the value of the EQ bit of CR6.
5286 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5288 case 1: // Branch on the inverted value of the EQ bit of CR6.
5289 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5291 case 2: // Branch on the value of the LT bit of CR6.
5292 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5294 case 3: // Branch on the inverted value of the LT bit of CR6.
5295 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5299 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5300 DAG.getConstant(CompOpc, MVT::i32),
5301 DAG.getRegister(PPC::CR6, MVT::i32),
5302 N->getOperand(4), CompNode.getValue(1));
5311 //===----------------------------------------------------------------------===//
5312 // Inline Assembly Support
5313 //===----------------------------------------------------------------------===//
5315 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5319 const SelectionDAG &DAG,
5320 unsigned Depth) const {
5321 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5322 switch (Op.getOpcode()) {
5324 case PPCISD::LBRX: {
5325 // lhbrx is known to have the top bits cleared out.
5326 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5327 KnownZero = 0xFFFF0000;
5330 case ISD::INTRINSIC_WO_CHAIN: {
5331 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5333 case Intrinsic::ppc_altivec_vcmpbfp_p:
5334 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5335 case Intrinsic::ppc_altivec_vcmpequb_p:
5336 case Intrinsic::ppc_altivec_vcmpequh_p:
5337 case Intrinsic::ppc_altivec_vcmpequw_p:
5338 case Intrinsic::ppc_altivec_vcmpgefp_p:
5339 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5340 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5341 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5342 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5343 case Intrinsic::ppc_altivec_vcmpgtub_p:
5344 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5345 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5346 KnownZero = ~1U; // All bits but the low one are known to be zero.
5354 /// getConstraintType - Given a constraint, return the type of
5355 /// constraint it is for this target.
5356 PPCTargetLowering::ConstraintType
5357 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5358 if (Constraint.size() == 1) {
5359 switch (Constraint[0]) {
5366 return C_RegisterClass;
5369 return TargetLowering::getConstraintType(Constraint);
5372 /// Examine constraint type and operand type and determine a weight value.
5373 /// This object must already have been set up with the operand type
5374 /// and the current alternative constraint selected.
5375 TargetLowering::ConstraintWeight
5376 PPCTargetLowering::getSingleConstraintMatchWeight(
5377 AsmOperandInfo &info, const char *constraint) const {
5378 ConstraintWeight weight = CW_Invalid;
5379 Value *CallOperandVal = info.CallOperandVal;
5380 // If we don't have a value, we can't do a match,
5381 // but allow it at the lowest weight.
5382 if (CallOperandVal == NULL)
5384 const Type *type = CallOperandVal->getType();
5385 // Look at the constraint type.
5386 switch (*constraint) {
5388 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5391 if (type->isIntegerTy())
5392 weight = CW_Register;
5395 if (type->isFloatTy())
5396 weight = CW_Register;
5399 if (type->isDoubleTy())
5400 weight = CW_Register;
5403 if (type->isVectorTy())
5404 weight = CW_Register;
5407 weight = CW_Register;
5413 std::pair<unsigned, const TargetRegisterClass*>
5414 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5416 if (Constraint.size() == 1) {
5417 // GCC RS6000 Constraint Letters
5418 switch (Constraint[0]) {
5421 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5422 return std::make_pair(0U, PPC::G8RCRegisterClass);
5423 return std::make_pair(0U, PPC::GPRCRegisterClass);
5426 return std::make_pair(0U, PPC::F4RCRegisterClass);
5427 else if (VT == MVT::f64)
5428 return std::make_pair(0U, PPC::F8RCRegisterClass);
5431 return std::make_pair(0U, PPC::VRRCRegisterClass);
5433 return std::make_pair(0U, PPC::CRRCRegisterClass);
5437 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5441 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5442 /// vector. If it is invalid, don't add anything to Ops.
5443 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5444 std::vector<SDValue>&Ops,
5445 SelectionDAG &DAG) const {
5446 SDValue Result(0,0);
5457 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5458 if (!CST) return; // Must be an immediate to match.
5459 unsigned Value = CST->getZExtValue();
5461 default: llvm_unreachable("Unknown constraint letter!");
5462 case 'I': // "I" is a signed 16-bit constant.
5463 if ((short)Value == (int)Value)
5464 Result = DAG.getTargetConstant(Value, Op.getValueType());
5466 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5467 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5468 if ((short)Value == 0)
5469 Result = DAG.getTargetConstant(Value, Op.getValueType());
5471 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5472 if ((Value >> 16) == 0)
5473 Result = DAG.getTargetConstant(Value, Op.getValueType());
5475 case 'M': // "M" is a constant that is greater than 31.
5477 Result = DAG.getTargetConstant(Value, Op.getValueType());
5479 case 'N': // "N" is a positive constant that is an exact power of two.
5480 if ((int)Value > 0 && isPowerOf2_32(Value))
5481 Result = DAG.getTargetConstant(Value, Op.getValueType());
5483 case 'O': // "O" is the constant zero.
5485 Result = DAG.getTargetConstant(Value, Op.getValueType());
5487 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5488 if ((short)-Value == (int)-Value)
5489 Result = DAG.getTargetConstant(Value, Op.getValueType());
5496 if (Result.getNode()) {
5497 Ops.push_back(Result);
5501 // Handle standard constraint letters.
5502 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
5505 // isLegalAddressingMode - Return true if the addressing mode represented
5506 // by AM is legal for this target, for a load/store of the specified type.
5507 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5508 const Type *Ty) const {
5509 // FIXME: PPC does not allow r+i addressing modes for vectors!
5511 // PPC allows a sign-extended 16-bit immediate field.
5512 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5515 // No global is ever allowed as a base.
5519 // PPC only support r+r,
5521 case 0: // "r+i" or just "i", depending on HasBaseReg.
5524 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5526 // Otherwise we have r+r or r+i.
5529 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5531 // Allow 2*r as r+r.
5534 // No other scales are supported.
5541 /// isLegalAddressImmediate - Return true if the integer value can be used
5542 /// as the offset of the target addressing mode for load / store of the
5544 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5545 // PPC allows a sign-extended 16-bit immediate field.
5546 return (V > -(1 << 16) && V < (1 << 16)-1);
5549 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5553 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
5554 SelectionDAG &DAG) const {
5555 MachineFunction &MF = DAG.getMachineFunction();
5556 MachineFrameInfo *MFI = MF.getFrameInfo();
5557 MFI->setReturnAddressIsTaken(true);
5559 DebugLoc dl = Op.getDebugLoc();
5560 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5562 // Make sure the function does not optimize away the store of the RA to
5564 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5565 FuncInfo->setLRStoreRequired();
5566 bool isPPC64 = PPCSubTarget.isPPC64();
5567 bool isDarwinABI = PPCSubTarget.isDarwinABI();
5570 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5573 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
5574 isPPC64? MVT::i64 : MVT::i32);
5575 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5576 DAG.getNode(ISD::ADD, dl, getPointerTy(),
5578 MachinePointerInfo(), false, false, 0);
5581 // Just load the return address off the stack.
5582 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5583 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5584 RetAddrFI, MachinePointerInfo(), false, false, 0);
5587 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
5588 SelectionDAG &DAG) const {
5589 DebugLoc dl = Op.getDebugLoc();
5590 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5592 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5593 bool isPPC64 = PtrVT == MVT::i64;
5595 MachineFunction &MF = DAG.getMachineFunction();
5596 MachineFrameInfo *MFI = MF.getFrameInfo();
5597 MFI->setFrameAddressIsTaken(true);
5598 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) &&
5599 MFI->getStackSize() &&
5600 !MF.getFunction()->hasFnAttr(Attribute::Naked);
5601 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
5602 (is31 ? PPC::R31 : PPC::R1);
5603 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
5606 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
5607 FrameAddr, MachinePointerInfo(), false, false, 0);
5612 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5613 // The PowerPC target isn't yet aware of offsets.
5617 /// getOptimalMemOpType - Returns the target specific optimal type for load
5618 /// and store operations as a result of memset, memcpy, and memmove
5619 /// lowering. If DstAlign is zero that means it's safe to destination
5620 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
5621 /// means there isn't a need to check it against alignment requirement,
5622 /// probably because the source does not need to be loaded. If
5623 /// 'NonScalarIntSafe' is true, that means it's safe to return a
5624 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
5625 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
5626 /// constant so it does not need to be loaded.
5627 /// It returns EVT::Other if the type should be determined using generic
5628 /// target-independent logic.
5629 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
5630 unsigned DstAlign, unsigned SrcAlign,
5631 bool NonScalarIntSafe,
5633 MachineFunction &MF) const {
5634 if (this->PPCSubTarget.isPPC64()) {