1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 // These libcalls are not available in 32-bit.
631 setLibcallName(RTLIB::SHL_I128, nullptr);
632 setLibcallName(RTLIB::SRL_I128, nullptr);
633 setLibcallName(RTLIB::SRA_I128, nullptr);
637 setStackPointerRegisterToSaveRestore(PPC::X1);
638 setExceptionPointerRegister(PPC::X3);
639 setExceptionSelectorRegister(PPC::X4);
641 setStackPointerRegisterToSaveRestore(PPC::R1);
642 setExceptionPointerRegister(PPC::R3);
643 setExceptionSelectorRegister(PPC::R4);
646 // We have target-specific dag combine patterns for the following nodes:
647 setTargetDAGCombine(ISD::SINT_TO_FP);
648 setTargetDAGCombine(ISD::LOAD);
649 setTargetDAGCombine(ISD::STORE);
650 setTargetDAGCombine(ISD::BR_CC);
651 if (Subtarget.useCRBits())
652 setTargetDAGCombine(ISD::BRCOND);
653 setTargetDAGCombine(ISD::BSWAP);
654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
656 setTargetDAGCombine(ISD::SIGN_EXTEND);
657 setTargetDAGCombine(ISD::ZERO_EXTEND);
658 setTargetDAGCombine(ISD::ANY_EXTEND);
660 if (Subtarget.useCRBits()) {
661 setTargetDAGCombine(ISD::TRUNCATE);
662 setTargetDAGCombine(ISD::SETCC);
663 setTargetDAGCombine(ISD::SELECT_CC);
666 // Use reciprocal estimates.
667 if (TM.Options.UnsafeFPMath) {
668 setTargetDAGCombine(ISD::FDIV);
669 setTargetDAGCombine(ISD::FSQRT);
672 // Darwin long double math library functions have $LDBL128 appended.
673 if (Subtarget.isDarwin()) {
674 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
675 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
676 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
677 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
678 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
679 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
680 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
681 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
682 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
683 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
686 // With 32 condition bits, we don't need to sink (and duplicate) compares
687 // aggressively in CodeGenPrep.
688 if (Subtarget.useCRBits())
689 setHasMultipleConditionRegisters();
691 setMinFunctionAlignment(2);
692 if (Subtarget.isDarwin())
693 setPrefFunctionAlignment(4);
695 if (isPPC64 && Subtarget.isJITCodeModel())
696 // Temporary workaround for the inability of PPC64 JIT to handle jump
698 setSupportJumpTables(false);
700 setInsertFencesForAtomic(true);
702 if (Subtarget.enableMachineScheduler())
703 setSchedulingPreference(Sched::Source);
705 setSchedulingPreference(Sched::Hybrid);
707 computeRegisterProperties();
709 // The Freescale cores does better with aggressive inlining of memcpy and
710 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
711 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
712 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
713 MaxStoresPerMemset = 32;
714 MaxStoresPerMemsetOptSize = 16;
715 MaxStoresPerMemcpy = 32;
716 MaxStoresPerMemcpyOptSize = 8;
717 MaxStoresPerMemmove = 32;
718 MaxStoresPerMemmoveOptSize = 8;
720 setPrefFunctionAlignment(4);
724 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
725 /// the desired ByVal argument alignment.
726 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
727 unsigned MaxMaxAlign) {
728 if (MaxAlign == MaxMaxAlign)
730 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
731 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
733 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
735 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
736 unsigned EltAlign = 0;
737 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
738 if (EltAlign > MaxAlign)
740 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
741 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
742 unsigned EltAlign = 0;
743 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
744 if (EltAlign > MaxAlign)
746 if (MaxAlign == MaxMaxAlign)
752 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
753 /// function arguments in the caller parameter area.
754 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
755 // Darwin passes everything on 4 byte boundary.
756 if (Subtarget.isDarwin())
759 // 16byte and wider vectors are passed on 16byte boundary.
760 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
761 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
762 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
763 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
767 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
769 default: return nullptr;
770 case PPCISD::FSEL: return "PPCISD::FSEL";
771 case PPCISD::FCFID: return "PPCISD::FCFID";
772 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
773 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
774 case PPCISD::FRE: return "PPCISD::FRE";
775 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
776 case PPCISD::STFIWX: return "PPCISD::STFIWX";
777 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
778 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
779 case PPCISD::VPERM: return "PPCISD::VPERM";
780 case PPCISD::Hi: return "PPCISD::Hi";
781 case PPCISD::Lo: return "PPCISD::Lo";
782 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
783 case PPCISD::LOAD: return "PPCISD::LOAD";
784 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
785 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
786 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
787 case PPCISD::SRL: return "PPCISD::SRL";
788 case PPCISD::SRA: return "PPCISD::SRA";
789 case PPCISD::SHL: return "PPCISD::SHL";
790 case PPCISD::CALL: return "PPCISD::CALL";
791 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
792 case PPCISD::MTCTR: return "PPCISD::MTCTR";
793 case PPCISD::BCTRL: return "PPCISD::BCTRL";
794 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
795 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
796 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
797 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
798 case PPCISD::VCMP: return "PPCISD::VCMP";
799 case PPCISD::VCMPo: return "PPCISD::VCMPo";
800 case PPCISD::LBRX: return "PPCISD::LBRX";
801 case PPCISD::STBRX: return "PPCISD::STBRX";
802 case PPCISD::LARX: return "PPCISD::LARX";
803 case PPCISD::STCX: return "PPCISD::STCX";
804 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
805 case PPCISD::BDNZ: return "PPCISD::BDNZ";
806 case PPCISD::BDZ: return "PPCISD::BDZ";
807 case PPCISD::MFFS: return "PPCISD::MFFS";
808 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
809 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
810 case PPCISD::CR6SET: return "PPCISD::CR6SET";
811 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
812 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
813 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
814 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
815 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
816 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
817 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
818 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
819 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
820 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
821 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
822 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
823 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
824 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
825 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
826 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
827 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
828 case PPCISD::SC: return "PPCISD::SC";
832 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
834 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
835 return VT.changeVectorElementTypeToInteger();
838 //===----------------------------------------------------------------------===//
839 // Node matching predicates, for use by the tblgen matching code.
840 //===----------------------------------------------------------------------===//
842 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
843 static bool isFloatingPointZero(SDValue Op) {
844 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
845 return CFP->getValueAPF().isZero();
846 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
847 // Maybe this has already been legalized into the constant pool?
848 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
849 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
850 return CFP->getValueAPF().isZero();
855 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
856 /// true if Op is undef or if it matches the specified value.
857 static bool isConstantOrUndef(int Op, int Val) {
858 return Op < 0 || Op == Val;
861 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
862 /// VPKUHUM instruction.
863 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
865 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
867 for (unsigned i = 0; i != 16; ++i)
868 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
871 for (unsigned i = 0; i != 8; ++i)
872 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
873 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
879 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
880 /// VPKUWUM instruction.
881 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
884 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
892 for (unsigned i = 0; i != 16; i += 2)
893 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
897 for (unsigned i = 0; i != 8; i += 2)
898 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
899 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
900 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
901 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
907 /// isVMerge - Common function, used to match vmrg* shuffles.
909 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
910 unsigned LHSStart, unsigned RHSStart) {
911 if (N->getValueType(0) != MVT::v16i8)
913 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
914 "Unsupported merge size!");
916 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
917 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
918 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
919 LHSStart+j+i*UnitSize) ||
920 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
921 RHSStart+j+i*UnitSize))
927 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
928 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
929 /// The ShuffleKind distinguishes between big-endian merges with two
930 /// different inputs (0), either-endian merges with two identical inputs (1),
931 /// and little-endian merges with two different inputs (2). For the latter,
932 /// the input operands are swapped (see PPCInstrAltivec.td).
933 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
934 unsigned ShuffleKind, SelectionDAG &DAG) {
935 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
936 if (ShuffleKind == 1) // unary
937 return isVMerge(N, UnitSize, 0, 0);
938 else if (ShuffleKind == 2) // swapped
939 return isVMerge(N, UnitSize, 0, 16);
943 if (ShuffleKind == 1) // unary
944 return isVMerge(N, UnitSize, 8, 8);
945 else if (ShuffleKind == 0) // normal
946 return isVMerge(N, UnitSize, 8, 24);
952 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
953 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
954 /// The ShuffleKind distinguishes between big-endian merges with two
955 /// different inputs (0), either-endian merges with two identical inputs (1),
956 /// and little-endian merges with two different inputs (2). For the latter,
957 /// the input operands are swapped (see PPCInstrAltivec.td).
958 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
959 unsigned ShuffleKind, SelectionDAG &DAG) {
960 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
961 if (ShuffleKind == 1) // unary
962 return isVMerge(N, UnitSize, 8, 8);
963 else if (ShuffleKind == 2) // swapped
964 return isVMerge(N, UnitSize, 8, 24);
968 if (ShuffleKind == 1) // unary
969 return isVMerge(N, UnitSize, 0, 0);
970 else if (ShuffleKind == 0) // normal
971 return isVMerge(N, UnitSize, 0, 16);
978 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
979 /// amount, otherwise return -1.
980 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
981 if (N->getValueType(0) != MVT::v16i8)
984 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
986 // Find the first non-undef value in the shuffle mask.
988 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
991 if (i == 16) return -1; // all undef.
993 // Otherwise, check to see if the rest of the elements are consecutively
994 // numbered from this value.
995 unsigned ShiftAmt = SVOp->getMaskElt(i);
996 if (ShiftAmt < i) return -1;
998 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1003 // Check the rest of the elements to see if they are consecutive.
1004 for (++i; i != 16; ++i)
1005 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
1008 // Check the rest of the elements to see if they are consecutive.
1009 for (++i; i != 16; ++i)
1010 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
1014 } else { // Big Endian
1019 // Check the rest of the elements to see if they are consecutive.
1020 for (++i; i != 16; ++i)
1021 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1024 // Check the rest of the elements to see if they are consecutive.
1025 for (++i; i != 16; ++i)
1026 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1033 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1034 /// specifies a splat of a single element that is suitable for input to
1035 /// VSPLTB/VSPLTH/VSPLTW.
1036 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1037 assert(N->getValueType(0) == MVT::v16i8 &&
1038 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1040 // This is a splat operation if each element of the permute is the same, and
1041 // if the value doesn't reference the second vector.
1042 unsigned ElementBase = N->getMaskElt(0);
1044 // FIXME: Handle UNDEF elements too!
1045 if (ElementBase >= 16)
1048 // Check that the indices are consecutive, in the case of a multi-byte element
1049 // splatted with a v16i8 mask.
1050 for (unsigned i = 1; i != EltSize; ++i)
1051 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1054 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1055 if (N->getMaskElt(i) < 0) continue;
1056 for (unsigned j = 0; j != EltSize; ++j)
1057 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1063 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1065 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1066 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1068 APInt APVal, APUndef;
1072 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1073 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1074 return CFP->getValueAPF().isNegZero();
1079 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1080 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1081 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1082 SelectionDAG &DAG) {
1083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1084 assert(isSplatShuffleMask(SVOp, EltSize));
1085 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1086 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1088 return SVOp->getMaskElt(0) / EltSize;
1091 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1092 /// by using a vspltis[bhw] instruction of the specified element size, return
1093 /// the constant being splatted. The ByteSize field indicates the number of
1094 /// bytes of each element [124] -> [bhw].
1095 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1096 SDValue OpVal(nullptr, 0);
1098 // If ByteSize of the splat is bigger than the element size of the
1099 // build_vector, then we have a case where we are checking for a splat where
1100 // multiple elements of the buildvector are folded together into a single
1101 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1102 unsigned EltSize = 16/N->getNumOperands();
1103 if (EltSize < ByteSize) {
1104 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1105 SDValue UniquedVals[4];
1106 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1108 // See if all of the elements in the buildvector agree across.
1109 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1110 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1111 // If the element isn't a constant, bail fully out.
1112 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1115 if (!UniquedVals[i&(Multiple-1)].getNode())
1116 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1117 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1118 return SDValue(); // no match.
1121 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1122 // either constant or undef values that are identical for each chunk. See
1123 // if these chunks can form into a larger vspltis*.
1125 // Check to see if all of the leading entries are either 0 or -1. If
1126 // neither, then this won't fit into the immediate field.
1127 bool LeadingZero = true;
1128 bool LeadingOnes = true;
1129 for (unsigned i = 0; i != Multiple-1; ++i) {
1130 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1132 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1133 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1135 // Finally, check the least significant entry.
1137 if (!UniquedVals[Multiple-1].getNode())
1138 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1139 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1141 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1144 if (!UniquedVals[Multiple-1].getNode())
1145 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1146 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1147 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1148 return DAG.getTargetConstant(Val, MVT::i32);
1154 // Check to see if this buildvec has a single non-undef value in its elements.
1155 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1156 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1157 if (!OpVal.getNode())
1158 OpVal = N->getOperand(i);
1159 else if (OpVal != N->getOperand(i))
1163 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1165 unsigned ValSizeInBytes = EltSize;
1167 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1168 Value = CN->getZExtValue();
1169 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1170 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1171 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1174 // If the splat value is larger than the element value, then we can never do
1175 // this splat. The only case that we could fit the replicated bits into our
1176 // immediate field for would be zero, and we prefer to use vxor for it.
1177 if (ValSizeInBytes < ByteSize) return SDValue();
1179 // If the element value is larger than the splat value, cut it in half and
1180 // check to see if the two halves are equal. Continue doing this until we
1181 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1182 while (ValSizeInBytes > ByteSize) {
1183 ValSizeInBytes >>= 1;
1185 // If the top half equals the bottom half, we're still ok.
1186 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1187 (Value & ((1 << (8*ValSizeInBytes))-1)))
1191 // Properly sign extend the value.
1192 int MaskVal = SignExtend32(Value, ByteSize * 8);
1194 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1195 if (MaskVal == 0) return SDValue();
1197 // Finally, if this value fits in a 5 bit sext field, return it
1198 if (SignExtend32<5>(MaskVal) == MaskVal)
1199 return DAG.getTargetConstant(MaskVal, MVT::i32);
1203 //===----------------------------------------------------------------------===//
1204 // Addressing Mode Selection
1205 //===----------------------------------------------------------------------===//
1207 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1208 /// or 64-bit immediate, and if the value can be accurately represented as a
1209 /// sign extension from a 16-bit value. If so, this returns true and the
1211 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1212 if (!isa<ConstantSDNode>(N))
1215 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1216 if (N->getValueType(0) == MVT::i32)
1217 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1219 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1221 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1222 return isIntS16Immediate(Op.getNode(), Imm);
1226 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1227 /// can be represented as an indexed [r+r] operation. Returns false if it
1228 /// can be more efficiently represented with [r+imm].
1229 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1231 SelectionDAG &DAG) const {
1233 if (N.getOpcode() == ISD::ADD) {
1234 if (isIntS16Immediate(N.getOperand(1), imm))
1235 return false; // r+i
1236 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1237 return false; // r+i
1239 Base = N.getOperand(0);
1240 Index = N.getOperand(1);
1242 } else if (N.getOpcode() == ISD::OR) {
1243 if (isIntS16Immediate(N.getOperand(1), imm))
1244 return false; // r+i can fold it if we can.
1246 // If this is an or of disjoint bitfields, we can codegen this as an add
1247 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1249 APInt LHSKnownZero, LHSKnownOne;
1250 APInt RHSKnownZero, RHSKnownOne;
1251 DAG.computeKnownBits(N.getOperand(0),
1252 LHSKnownZero, LHSKnownOne);
1254 if (LHSKnownZero.getBoolValue()) {
1255 DAG.computeKnownBits(N.getOperand(1),
1256 RHSKnownZero, RHSKnownOne);
1257 // If all of the bits are known zero on the LHS or RHS, the add won't
1259 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1260 Base = N.getOperand(0);
1261 Index = N.getOperand(1);
1270 // If we happen to be doing an i64 load or store into a stack slot that has
1271 // less than a 4-byte alignment, then the frame-index elimination may need to
1272 // use an indexed load or store instruction (because the offset may not be a
1273 // multiple of 4). The extra register needed to hold the offset comes from the
1274 // register scavenger, and it is possible that the scavenger will need to use
1275 // an emergency spill slot. As a result, we need to make sure that a spill slot
1276 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1278 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1279 // FIXME: This does not handle the LWA case.
1283 // NOTE: We'll exclude negative FIs here, which come from argument
1284 // lowering, because there are no known test cases triggering this problem
1285 // using packed structures (or similar). We can remove this exclusion if
1286 // we find such a test case. The reason why this is so test-case driven is
1287 // because this entire 'fixup' is only to prevent crashes (from the
1288 // register scavenger) on not-really-valid inputs. For example, if we have:
1290 // %b = bitcast i1* %a to i64*
1291 // store i64* a, i64 b
1292 // then the store should really be marked as 'align 1', but is not. If it
1293 // were marked as 'align 1' then the indexed form would have been
1294 // instruction-selected initially, and the problem this 'fixup' is preventing
1295 // won't happen regardless.
1299 MachineFunction &MF = DAG.getMachineFunction();
1300 MachineFrameInfo *MFI = MF.getFrameInfo();
1302 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1306 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1307 FuncInfo->setHasNonRISpills();
1310 /// Returns true if the address N can be represented by a base register plus
1311 /// a signed 16-bit displacement [r+imm], and if it is not better
1312 /// represented as reg+reg. If Aligned is true, only accept displacements
1313 /// suitable for STD and friends, i.e. multiples of 4.
1314 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1317 bool Aligned) const {
1318 // FIXME dl should come from parent load or store, not from address
1320 // If this can be more profitably realized as r+r, fail.
1321 if (SelectAddressRegReg(N, Disp, Base, DAG))
1324 if (N.getOpcode() == ISD::ADD) {
1326 if (isIntS16Immediate(N.getOperand(1), imm) &&
1327 (!Aligned || (imm & 3) == 0)) {
1328 Disp = DAG.getTargetConstant(imm, N.getValueType());
1329 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1330 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1331 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1333 Base = N.getOperand(0);
1335 return true; // [r+i]
1336 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1337 // Match LOAD (ADD (X, Lo(G))).
1338 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1339 && "Cannot handle constant offsets yet!");
1340 Disp = N.getOperand(1).getOperand(0); // The global address.
1341 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1342 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1343 Disp.getOpcode() == ISD::TargetConstantPool ||
1344 Disp.getOpcode() == ISD::TargetJumpTable);
1345 Base = N.getOperand(0);
1346 return true; // [&g+r]
1348 } else if (N.getOpcode() == ISD::OR) {
1350 if (isIntS16Immediate(N.getOperand(1), imm) &&
1351 (!Aligned || (imm & 3) == 0)) {
1352 // If this is an or of disjoint bitfields, we can codegen this as an add
1353 // (for better address arithmetic) if the LHS and RHS of the OR are
1354 // provably disjoint.
1355 APInt LHSKnownZero, LHSKnownOne;
1356 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1358 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1359 // If all of the bits are known zero on the LHS or RHS, the add won't
1361 if (FrameIndexSDNode *FI =
1362 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1363 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1364 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1366 Base = N.getOperand(0);
1368 Disp = DAG.getTargetConstant(imm, N.getValueType());
1372 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1373 // Loading from a constant address.
1375 // If this address fits entirely in a 16-bit sext immediate field, codegen
1378 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1379 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1380 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1381 CN->getValueType(0));
1385 // Handle 32-bit sext immediates with LIS + addr mode.
1386 if ((CN->getValueType(0) == MVT::i32 ||
1387 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1388 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1389 int Addr = (int)CN->getZExtValue();
1391 // Otherwise, break this down into an LIS + disp.
1392 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1394 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1395 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1396 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1401 Disp = DAG.getTargetConstant(0, getPointerTy());
1402 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1403 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1404 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1407 return true; // [r+0]
1410 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1411 /// represented as an indexed [r+r] operation.
1412 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1414 SelectionDAG &DAG) const {
1415 // Check to see if we can easily represent this as an [r+r] address. This
1416 // will fail if it thinks that the address is more profitably represented as
1417 // reg+imm, e.g. where imm = 0.
1418 if (SelectAddressRegReg(N, Base, Index, DAG))
1421 // If the operand is an addition, always emit this as [r+r], since this is
1422 // better (for code size, and execution, as the memop does the add for free)
1423 // than emitting an explicit add.
1424 if (N.getOpcode() == ISD::ADD) {
1425 Base = N.getOperand(0);
1426 Index = N.getOperand(1);
1430 // Otherwise, do it the hard way, using R0 as the base register.
1431 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1437 /// getPreIndexedAddressParts - returns true by value, base pointer and
1438 /// offset pointer and addressing mode by reference if the node's address
1439 /// can be legally represented as pre-indexed load / store address.
1440 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1442 ISD::MemIndexedMode &AM,
1443 SelectionDAG &DAG) const {
1444 if (DisablePPCPreinc) return false;
1450 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1451 Ptr = LD->getBasePtr();
1452 VT = LD->getMemoryVT();
1453 Alignment = LD->getAlignment();
1454 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1455 Ptr = ST->getBasePtr();
1456 VT = ST->getMemoryVT();
1457 Alignment = ST->getAlignment();
1462 // PowerPC doesn't have preinc load/store instructions for vectors.
1466 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1468 // Common code will reject creating a pre-inc form if the base pointer
1469 // is a frame index, or if N is a store and the base pointer is either
1470 // the same as or a predecessor of the value being stored. Check for
1471 // those situations here, and try with swapped Base/Offset instead.
1474 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1477 SDValue Val = cast<StoreSDNode>(N)->getValue();
1478 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1483 std::swap(Base, Offset);
1489 // LDU/STU can only handle immediates that are a multiple of 4.
1490 if (VT != MVT::i64) {
1491 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1494 // LDU/STU need an address with at least 4-byte alignment.
1498 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1502 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1503 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1504 // sext i32 to i64 when addr mode is r+i.
1505 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1506 LD->getExtensionType() == ISD::SEXTLOAD &&
1507 isa<ConstantSDNode>(Offset))
1515 //===----------------------------------------------------------------------===//
1516 // LowerOperation implementation
1517 //===----------------------------------------------------------------------===//
1519 /// GetLabelAccessInfo - Return true if we should reference labels using a
1520 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1521 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1522 unsigned &LoOpFlags,
1523 const GlobalValue *GV = nullptr) {
1524 HiOpFlags = PPCII::MO_HA;
1525 LoOpFlags = PPCII::MO_LO;
1527 // Don't use the pic base if not in PIC relocation model.
1528 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1531 HiOpFlags |= PPCII::MO_PIC_FLAG;
1532 LoOpFlags |= PPCII::MO_PIC_FLAG;
1535 // If this is a reference to a global value that requires a non-lazy-ptr, make
1536 // sure that instruction lowering adds it.
1537 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1538 HiOpFlags |= PPCII::MO_NLP_FLAG;
1539 LoOpFlags |= PPCII::MO_NLP_FLAG;
1541 if (GV->hasHiddenVisibility()) {
1542 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1543 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1550 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1551 SelectionDAG &DAG) {
1552 EVT PtrVT = HiPart.getValueType();
1553 SDValue Zero = DAG.getConstant(0, PtrVT);
1556 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1557 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1559 // With PIC, the first instruction is actually "GR+hi(&G)".
1561 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1562 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1564 // Generate non-pic code that has direct accesses to the constant pool.
1565 // The address of the global is just (hi(&g)+lo(&g)).
1566 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1569 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1570 SelectionDAG &DAG) const {
1571 EVT PtrVT = Op.getValueType();
1572 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1573 const Constant *C = CP->getConstVal();
1575 // 64-bit SVR4 ABI code is always position-independent.
1576 // The actual address of the GlobalValue is stored in the TOC.
1577 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1578 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1579 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1580 DAG.getRegister(PPC::X2, MVT::i64));
1583 unsigned MOHiFlag, MOLoFlag;
1584 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1586 if (isPIC && Subtarget.isSVR4ABI()) {
1587 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1588 PPCII::MO_PIC_FLAG);
1590 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1591 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1595 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1597 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1598 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1601 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1602 EVT PtrVT = Op.getValueType();
1603 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1605 // 64-bit SVR4 ABI code is always position-independent.
1606 // The actual address of the GlobalValue is stored in the TOC.
1607 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1608 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1609 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1610 DAG.getRegister(PPC::X2, MVT::i64));
1613 unsigned MOHiFlag, MOLoFlag;
1614 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1616 if (isPIC && Subtarget.isSVR4ABI()) {
1617 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1618 PPCII::MO_PIC_FLAG);
1620 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1621 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1624 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1625 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1626 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1629 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1630 SelectionDAG &DAG) const {
1631 EVT PtrVT = Op.getValueType();
1633 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1635 unsigned MOHiFlag, MOLoFlag;
1636 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1637 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1638 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1639 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1642 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1643 SelectionDAG &DAG) const {
1645 // FIXME: TLS addresses currently use medium model code sequences,
1646 // which is the most useful form. Eventually support for small and
1647 // large models could be added if users need it, at the cost of
1648 // additional complexity.
1649 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1651 const GlobalValue *GV = GA->getGlobal();
1652 EVT PtrVT = getPointerTy();
1653 bool is64bit = Subtarget.isPPC64();
1655 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1657 if (Model == TLSModel::LocalExec) {
1658 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1659 PPCII::MO_TPREL_HA);
1660 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1661 PPCII::MO_TPREL_LO);
1662 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1663 is64bit ? MVT::i64 : MVT::i32);
1664 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1665 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1668 if (Model == TLSModel::InitialExec) {
1669 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1670 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1674 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1675 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1676 PtrVT, GOTReg, TGA);
1678 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1679 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1680 PtrVT, TGA, GOTPtr);
1681 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1684 if (Model == TLSModel::GeneralDynamic) {
1685 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1688 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1689 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1692 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1694 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1697 // We need a chain node, and don't have one handy. The underlying
1698 // call has no side effects, so using the function entry node
1700 SDValue Chain = DAG.getEntryNode();
1701 Chain = DAG.getCopyToReg(Chain, dl,
1702 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1703 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1704 is64bit ? MVT::i64 : MVT::i32);
1705 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1706 PtrVT, ParmReg, TGA);
1707 // The return value from GET_TLS_ADDR really is in X3 already, but
1708 // some hacks are needed here to tie everything together. The extra
1709 // copies dissolve during subsequent transforms.
1710 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1711 return DAG.getCopyFromReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, PtrVT);
1714 if (Model == TLSModel::LocalDynamic) {
1715 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1718 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1719 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1722 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1724 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1727 // We need a chain node, and don't have one handy. The underlying
1728 // call has no side effects, so using the function entry node
1730 SDValue Chain = DAG.getEntryNode();
1731 Chain = DAG.getCopyToReg(Chain, dl,
1732 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1733 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1734 is64bit ? MVT::i64 : MVT::i32);
1735 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1736 PtrVT, ParmReg, TGA);
1737 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1738 // some hacks are needed here to tie everything together. The extra
1739 // copies dissolve during subsequent transforms.
1740 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1741 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1742 Chain, ParmReg, TGA);
1743 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1746 llvm_unreachable("Unknown TLS model!");
1749 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1750 SelectionDAG &DAG) const {
1751 EVT PtrVT = Op.getValueType();
1752 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1754 const GlobalValue *GV = GSDN->getGlobal();
1756 // 64-bit SVR4 ABI code is always position-independent.
1757 // The actual address of the GlobalValue is stored in the TOC.
1758 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1759 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1760 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1761 DAG.getRegister(PPC::X2, MVT::i64));
1764 unsigned MOHiFlag, MOLoFlag;
1765 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1767 if (isPIC && Subtarget.isSVR4ABI()) {
1768 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1770 PPCII::MO_PIC_FLAG);
1771 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1772 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1776 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1778 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1780 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1782 // If the global reference is actually to a non-lazy-pointer, we have to do an
1783 // extra load to get the address of the global.
1784 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1785 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1786 false, false, false, 0);
1790 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1791 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1794 if (Op.getValueType() == MVT::v2i64) {
1795 // When the operands themselves are v2i64 values, we need to do something
1796 // special because VSX has no underlying comparison operations for these.
1797 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1798 // Equality can be handled by casting to the legal type for Altivec
1799 // comparisons, everything else needs to be expanded.
1800 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1801 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1802 DAG.getSetCC(dl, MVT::v4i32,
1803 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1804 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1811 // We handle most of these in the usual way.
1815 // If we're comparing for equality to zero, expose the fact that this is
1816 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1817 // fold the new nodes.
1818 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1819 if (C->isNullValue() && CC == ISD::SETEQ) {
1820 EVT VT = Op.getOperand(0).getValueType();
1821 SDValue Zext = Op.getOperand(0);
1822 if (VT.bitsLT(MVT::i32)) {
1824 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1826 unsigned Log2b = Log2_32(VT.getSizeInBits());
1827 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1828 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1829 DAG.getConstant(Log2b, MVT::i32));
1830 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1832 // Leave comparisons against 0 and -1 alone for now, since they're usually
1833 // optimized. FIXME: revisit this when we can custom lower all setcc
1835 if (C->isAllOnesValue() || C->isNullValue())
1839 // If we have an integer seteq/setne, turn it into a compare against zero
1840 // by xor'ing the rhs with the lhs, which is faster than setting a
1841 // condition register, reading it back out, and masking the correct bit. The
1842 // normal approach here uses sub to do this instead of xor. Using xor exposes
1843 // the result to other bit-twiddling opportunities.
1844 EVT LHSVT = Op.getOperand(0).getValueType();
1845 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1846 EVT VT = Op.getValueType();
1847 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1849 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1854 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1855 const PPCSubtarget &Subtarget) const {
1856 SDNode *Node = Op.getNode();
1857 EVT VT = Node->getValueType(0);
1858 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1859 SDValue InChain = Node->getOperand(0);
1860 SDValue VAListPtr = Node->getOperand(1);
1861 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1864 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1867 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1868 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1870 InChain = GprIndex.getValue(1);
1872 if (VT == MVT::i64) {
1873 // Check if GprIndex is even
1874 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1875 DAG.getConstant(1, MVT::i32));
1876 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1877 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1878 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1879 DAG.getConstant(1, MVT::i32));
1880 // Align GprIndex to be even if it isn't
1881 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1885 // fpr index is 1 byte after gpr
1886 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1887 DAG.getConstant(1, MVT::i32));
1890 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1891 FprPtr, MachinePointerInfo(SV), MVT::i8,
1893 InChain = FprIndex.getValue(1);
1895 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1896 DAG.getConstant(8, MVT::i32));
1898 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1899 DAG.getConstant(4, MVT::i32));
1902 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1903 MachinePointerInfo(), false, false,
1905 InChain = OverflowArea.getValue(1);
1907 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1908 MachinePointerInfo(), false, false,
1910 InChain = RegSaveArea.getValue(1);
1912 // select overflow_area if index > 8
1913 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1914 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1916 // adjustment constant gpr_index * 4/8
1917 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1918 VT.isInteger() ? GprIndex : FprIndex,
1919 DAG.getConstant(VT.isInteger() ? 4 : 8,
1922 // OurReg = RegSaveArea + RegConstant
1923 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1926 // Floating types are 32 bytes into RegSaveArea
1927 if (VT.isFloatingPoint())
1928 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1929 DAG.getConstant(32, MVT::i32));
1931 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1932 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1933 VT.isInteger() ? GprIndex : FprIndex,
1934 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1937 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1938 VT.isInteger() ? VAListPtr : FprPtr,
1939 MachinePointerInfo(SV),
1940 MVT::i8, false, false, 0);
1942 // determine if we should load from reg_save_area or overflow_area
1943 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1945 // increase overflow_area by 4/8 if gpr/fpr > 8
1946 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1947 DAG.getConstant(VT.isInteger() ? 4 : 8,
1950 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1953 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1955 MachinePointerInfo(),
1956 MVT::i32, false, false, 0);
1958 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1959 false, false, false, 0);
1962 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1963 const PPCSubtarget &Subtarget) const {
1964 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1966 // We have to copy the entire va_list struct:
1967 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1968 return DAG.getMemcpy(Op.getOperand(0), Op,
1969 Op.getOperand(1), Op.getOperand(2),
1970 DAG.getConstant(12, MVT::i32), 8, false, true,
1971 MachinePointerInfo(), MachinePointerInfo());
1974 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1975 SelectionDAG &DAG) const {
1976 return Op.getOperand(0);
1979 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1980 SelectionDAG &DAG) const {
1981 SDValue Chain = Op.getOperand(0);
1982 SDValue Trmp = Op.getOperand(1); // trampoline
1983 SDValue FPtr = Op.getOperand(2); // nested function
1984 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1987 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1988 bool isPPC64 = (PtrVT == MVT::i64);
1990 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1993 TargetLowering::ArgListTy Args;
1994 TargetLowering::ArgListEntry Entry;
1996 Entry.Ty = IntPtrTy;
1997 Entry.Node = Trmp; Args.push_back(Entry);
1999 // TrampSize == (isPPC64 ? 48 : 40);
2000 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2001 isPPC64 ? MVT::i64 : MVT::i32);
2002 Args.push_back(Entry);
2004 Entry.Node = FPtr; Args.push_back(Entry);
2005 Entry.Node = Nest; Args.push_back(Entry);
2007 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2008 TargetLowering::CallLoweringInfo CLI(DAG);
2009 CLI.setDebugLoc(dl).setChain(Chain)
2010 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2011 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2012 std::move(Args), 0);
2014 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2015 return CallResult.second;
2018 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2019 const PPCSubtarget &Subtarget) const {
2020 MachineFunction &MF = DAG.getMachineFunction();
2021 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2025 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2026 // vastart just stores the address of the VarArgsFrameIndex slot into the
2027 // memory location argument.
2028 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2029 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2030 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2031 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2032 MachinePointerInfo(SV),
2036 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2037 // We suppose the given va_list is already allocated.
2040 // char gpr; /* index into the array of 8 GPRs
2041 // * stored in the register save area
2042 // * gpr=0 corresponds to r3,
2043 // * gpr=1 to r4, etc.
2045 // char fpr; /* index into the array of 8 FPRs
2046 // * stored in the register save area
2047 // * fpr=0 corresponds to f1,
2048 // * fpr=1 to f2, etc.
2050 // char *overflow_arg_area;
2051 // /* location on stack that holds
2052 // * the next overflow argument
2054 // char *reg_save_area;
2055 // /* where r3:r10 and f1:f8 (if saved)
2061 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2062 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2065 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2067 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2069 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2072 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2073 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2075 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2076 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2078 uint64_t FPROffset = 1;
2079 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2081 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2083 // Store first byte : number of int regs
2084 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2086 MachinePointerInfo(SV),
2087 MVT::i8, false, false, 0);
2088 uint64_t nextOffset = FPROffset;
2089 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2092 // Store second byte : number of float regs
2093 SDValue secondStore =
2094 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2095 MachinePointerInfo(SV, nextOffset), MVT::i8,
2097 nextOffset += StackOffset;
2098 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2100 // Store second word : arguments given on stack
2101 SDValue thirdStore =
2102 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2103 MachinePointerInfo(SV, nextOffset),
2105 nextOffset += FrameOffset;
2106 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2108 // Store third word : arguments given in registers
2109 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2110 MachinePointerInfo(SV, nextOffset),
2115 #include "PPCGenCallingConv.inc"
2117 // Function whose sole purpose is to kill compiler warnings
2118 // stemming from unused functions included from PPCGenCallingConv.inc.
2119 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2120 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2123 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2124 CCValAssign::LocInfo &LocInfo,
2125 ISD::ArgFlagsTy &ArgFlags,
2130 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2132 CCValAssign::LocInfo &LocInfo,
2133 ISD::ArgFlagsTy &ArgFlags,
2135 static const MCPhysReg ArgRegs[] = {
2136 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2137 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2139 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2141 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2143 // Skip one register if the first unallocated register has an even register
2144 // number and there are still argument registers available which have not been
2145 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2146 // need to skip a register if RegNum is odd.
2147 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2148 State.AllocateReg(ArgRegs[RegNum]);
2151 // Always return false here, as this function only makes sure that the first
2152 // unallocated register has an odd register number and does not actually
2153 // allocate a register for the current argument.
2157 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2159 CCValAssign::LocInfo &LocInfo,
2160 ISD::ArgFlagsTy &ArgFlags,
2162 static const MCPhysReg ArgRegs[] = {
2163 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2167 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2169 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2171 // If there is only one Floating-point register left we need to put both f64
2172 // values of a split ppc_fp128 value on the stack.
2173 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2174 State.AllocateReg(ArgRegs[RegNum]);
2177 // Always return false here, as this function only makes sure that the two f64
2178 // values a ppc_fp128 value is split into are both passed in registers or both
2179 // passed on the stack and does not actually allocate a register for the
2180 // current argument.
2184 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2186 static const MCPhysReg *GetFPR() {
2187 static const MCPhysReg FPR[] = {
2188 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2189 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2195 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2197 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2198 unsigned PtrByteSize) {
2199 unsigned ArgSize = ArgVT.getStoreSize();
2200 if (Flags.isByVal())
2201 ArgSize = Flags.getByValSize();
2203 // Round up to multiples of the pointer size, except for array members,
2204 // which are always packed.
2205 if (!Flags.isInConsecutiveRegs())
2206 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2211 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2213 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2214 ISD::ArgFlagsTy Flags,
2215 unsigned PtrByteSize) {
2216 unsigned Align = PtrByteSize;
2218 // Altivec parameters are padded to a 16 byte boundary.
2219 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2220 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2221 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2224 // ByVal parameters are aligned as requested.
2225 if (Flags.isByVal()) {
2226 unsigned BVAlign = Flags.getByValAlign();
2227 if (BVAlign > PtrByteSize) {
2228 if (BVAlign % PtrByteSize != 0)
2230 "ByVal alignment is not a multiple of the pointer size");
2236 // Array members are always packed to their original alignment.
2237 if (Flags.isInConsecutiveRegs()) {
2238 // If the array member was split into multiple registers, the first
2239 // needs to be aligned to the size of the full type. (Except for
2240 // ppcf128, which is only aligned as its f64 components.)
2241 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2242 Align = OrigVT.getStoreSize();
2244 Align = ArgVT.getStoreSize();
2250 /// CalculateStackSlotUsed - Return whether this argument will use its
2251 /// stack slot (instead of being passed in registers). ArgOffset,
2252 /// AvailableFPRs, and AvailableVRs must hold the current argument
2253 /// position, and will be updated to account for this argument.
2254 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2255 ISD::ArgFlagsTy Flags,
2256 unsigned PtrByteSize,
2257 unsigned LinkageSize,
2258 unsigned ParamAreaSize,
2259 unsigned &ArgOffset,
2260 unsigned &AvailableFPRs,
2261 unsigned &AvailableVRs) {
2262 bool UseMemory = false;
2264 // Respect alignment of argument on the stack.
2266 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2267 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2268 // If there's no space left in the argument save area, we must
2269 // use memory (this check also catches zero-sized arguments).
2270 if (ArgOffset >= LinkageSize + ParamAreaSize)
2273 // Allocate argument on the stack.
2274 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2275 if (Flags.isInConsecutiveRegsLast())
2276 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2277 // If we overran the argument save area, we must use memory
2278 // (this check catches arguments passed partially in memory)
2279 if (ArgOffset > LinkageSize + ParamAreaSize)
2282 // However, if the argument is actually passed in an FPR or a VR,
2283 // we don't use memory after all.
2284 if (!Flags.isByVal()) {
2285 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2286 if (AvailableFPRs > 0) {
2290 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2291 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2292 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2293 if (AvailableVRs > 0) {
2302 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2303 /// ensure minimum alignment required for target.
2304 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2305 unsigned NumBytes) {
2306 unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment();
2307 unsigned AlignMask = TargetAlign - 1;
2308 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2313 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2314 CallingConv::ID CallConv, bool isVarArg,
2315 const SmallVectorImpl<ISD::InputArg>
2317 SDLoc dl, SelectionDAG &DAG,
2318 SmallVectorImpl<SDValue> &InVals)
2320 if (Subtarget.isSVR4ABI()) {
2321 if (Subtarget.isPPC64())
2322 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2325 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2328 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2334 PPCTargetLowering::LowerFormalArguments_32SVR4(
2336 CallingConv::ID CallConv, bool isVarArg,
2337 const SmallVectorImpl<ISD::InputArg>
2339 SDLoc dl, SelectionDAG &DAG,
2340 SmallVectorImpl<SDValue> &InVals) const {
2342 // 32-bit SVR4 ABI Stack Frame Layout:
2343 // +-----------------------------------+
2344 // +--> | Back chain |
2345 // | +-----------------------------------+
2346 // | | Floating-point register save area |
2347 // | +-----------------------------------+
2348 // | | General register save area |
2349 // | +-----------------------------------+
2350 // | | CR save word |
2351 // | +-----------------------------------+
2352 // | | VRSAVE save word |
2353 // | +-----------------------------------+
2354 // | | Alignment padding |
2355 // | +-----------------------------------+
2356 // | | Vector register save area |
2357 // | +-----------------------------------+
2358 // | | Local variable space |
2359 // | +-----------------------------------+
2360 // | | Parameter list area |
2361 // | +-----------------------------------+
2362 // | | LR save word |
2363 // | +-----------------------------------+
2364 // SP--> +--- | Back chain |
2365 // +-----------------------------------+
2368 // System V Application Binary Interface PowerPC Processor Supplement
2369 // AltiVec Technology Programming Interface Manual
2371 MachineFunction &MF = DAG.getMachineFunction();
2372 MachineFrameInfo *MFI = MF.getFrameInfo();
2373 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2375 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2376 // Potential tail calls could cause overwriting of argument stack slots.
2377 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2378 (CallConv == CallingConv::Fast));
2379 unsigned PtrByteSize = 4;
2381 // Assign locations to all of the incoming arguments.
2382 SmallVector<CCValAssign, 16> ArgLocs;
2383 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2384 getTargetMachine(), ArgLocs, *DAG.getContext());
2386 // Reserve space for the linkage area on the stack.
2387 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2388 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2390 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2393 CCValAssign &VA = ArgLocs[i];
2395 // Arguments stored in registers.
2396 if (VA.isRegLoc()) {
2397 const TargetRegisterClass *RC;
2398 EVT ValVT = VA.getValVT();
2400 switch (ValVT.getSimpleVT().SimpleTy) {
2402 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2405 RC = &PPC::GPRCRegClass;
2408 RC = &PPC::F4RCRegClass;
2411 if (Subtarget.hasVSX())
2412 RC = &PPC::VSFRCRegClass;
2414 RC = &PPC::F8RCRegClass;
2420 RC = &PPC::VRRCRegClass;
2424 RC = &PPC::VSHRCRegClass;
2428 // Transform the arguments stored in physical registers into virtual ones.
2429 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2430 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2431 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2433 if (ValVT == MVT::i1)
2434 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2436 InVals.push_back(ArgValue);
2438 // Argument stored in memory.
2439 assert(VA.isMemLoc());
2441 unsigned ArgSize = VA.getLocVT().getStoreSize();
2442 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2445 // Create load nodes to retrieve arguments from the stack.
2446 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2447 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2448 MachinePointerInfo(),
2449 false, false, false, 0));
2453 // Assign locations to all of the incoming aggregate by value arguments.
2454 // Aggregates passed by value are stored in the local variable space of the
2455 // caller's stack frame, right above the parameter list area.
2456 SmallVector<CCValAssign, 16> ByValArgLocs;
2457 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2458 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2460 // Reserve stack space for the allocations in CCInfo.
2461 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2463 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2465 // Area that is at least reserved in the caller of this function.
2466 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2467 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2469 // Set the size that is at least reserved in caller of this function. Tail
2470 // call optimized function's reserved stack space needs to be aligned so that
2471 // taking the difference between two stack areas will result in an aligned
2473 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2474 FuncInfo->setMinReservedArea(MinReservedArea);
2476 SmallVector<SDValue, 8> MemOps;
2478 // If the function takes variable number of arguments, make a frame index for
2479 // the start of the first vararg value... for expansion of llvm.va_start.
2481 static const MCPhysReg GPArgRegs[] = {
2482 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2483 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2485 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2487 static const MCPhysReg FPArgRegs[] = {
2488 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2491 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2493 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2495 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2498 // Make room for NumGPArgRegs and NumFPArgRegs.
2499 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2500 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2502 FuncInfo->setVarArgsStackOffset(
2503 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2504 CCInfo.getNextStackOffset(), true));
2506 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2507 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2509 // The fixed integer arguments of a variadic function are stored to the
2510 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2511 // the result of va_next.
2512 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2513 // Get an existing live-in vreg, or add a new one.
2514 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2516 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2518 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2519 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2520 MachinePointerInfo(), false, false, 0);
2521 MemOps.push_back(Store);
2522 // Increment the address by four for the next argument to store
2523 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2524 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2527 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2529 // The double arguments are stored to the VarArgsFrameIndex
2531 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2532 // Get an existing live-in vreg, or add a new one.
2533 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2535 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2537 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2538 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2539 MachinePointerInfo(), false, false, 0);
2540 MemOps.push_back(Store);
2541 // Increment the address by eight for the next argument to store
2542 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2544 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2548 if (!MemOps.empty())
2549 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2554 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2555 // value to MVT::i64 and then truncate to the correct register size.
2557 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2558 SelectionDAG &DAG, SDValue ArgVal,
2561 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2562 DAG.getValueType(ObjectVT));
2563 else if (Flags.isZExt())
2564 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2565 DAG.getValueType(ObjectVT));
2567 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2571 PPCTargetLowering::LowerFormalArguments_64SVR4(
2573 CallingConv::ID CallConv, bool isVarArg,
2574 const SmallVectorImpl<ISD::InputArg>
2576 SDLoc dl, SelectionDAG &DAG,
2577 SmallVectorImpl<SDValue> &InVals) const {
2578 // TODO: add description of PPC stack frame format, or at least some docs.
2580 bool isELFv2ABI = Subtarget.isELFv2ABI();
2581 bool isLittleEndian = Subtarget.isLittleEndian();
2582 MachineFunction &MF = DAG.getMachineFunction();
2583 MachineFrameInfo *MFI = MF.getFrameInfo();
2584 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2586 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2587 // Potential tail calls could cause overwriting of argument stack slots.
2588 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2589 (CallConv == CallingConv::Fast));
2590 unsigned PtrByteSize = 8;
2592 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2595 static const MCPhysReg GPR[] = {
2596 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2597 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2600 static const MCPhysReg *FPR = GetFPR();
2602 static const MCPhysReg VR[] = {
2603 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2604 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2606 static const MCPhysReg VSRH[] = {
2607 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2608 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2611 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2612 const unsigned Num_FPR_Regs = 13;
2613 const unsigned Num_VR_Regs = array_lengthof(VR);
2615 // Do a first pass over the arguments to determine whether the ABI
2616 // guarantees that our caller has allocated the parameter save area
2617 // on its stack frame. In the ELFv1 ABI, this is always the case;
2618 // in the ELFv2 ABI, it is true if this is a vararg function or if
2619 // any parameter is located in a stack slot.
2621 bool HasParameterArea = !isELFv2ABI || isVarArg;
2622 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2623 unsigned NumBytes = LinkageSize;
2624 unsigned AvailableFPRs = Num_FPR_Regs;
2625 unsigned AvailableVRs = Num_VR_Regs;
2626 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2627 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2628 PtrByteSize, LinkageSize, ParamAreaSize,
2629 NumBytes, AvailableFPRs, AvailableVRs))
2630 HasParameterArea = true;
2632 // Add DAG nodes to load the arguments or copy them out of registers. On
2633 // entry to a function on PPC, the arguments start after the linkage area,
2634 // although the first ones are often in registers.
2636 unsigned ArgOffset = LinkageSize;
2637 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2638 SmallVector<SDValue, 8> MemOps;
2639 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2640 unsigned CurArgIdx = 0;
2641 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2643 bool needsLoad = false;
2644 EVT ObjectVT = Ins[ArgNo].VT;
2645 EVT OrigVT = Ins[ArgNo].ArgVT;
2646 unsigned ObjSize = ObjectVT.getStoreSize();
2647 unsigned ArgSize = ObjSize;
2648 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2649 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2650 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2652 /* Respect alignment of argument on the stack. */
2654 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2655 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2656 unsigned CurArgOffset = ArgOffset;
2658 /* Compute GPR index associated with argument offset. */
2659 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2660 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2662 // FIXME the codegen can be much improved in some cases.
2663 // We do not have to keep everything in memory.
2664 if (Flags.isByVal()) {
2665 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2666 ObjSize = Flags.getByValSize();
2667 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2668 // Empty aggregate parameters do not take up registers. Examples:
2672 // etc. However, we have to provide a place-holder in InVals, so
2673 // pretend we have an 8-byte item at the current address for that
2676 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2677 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2678 InVals.push_back(FIN);
2682 // Create a stack object covering all stack doublewords occupied
2683 // by the argument. If the argument is (fully or partially) on
2684 // the stack, or if the argument is fully in registers but the
2685 // caller has allocated the parameter save anyway, we can refer
2686 // directly to the caller's stack frame. Otherwise, create a
2687 // local copy in our own frame.
2689 if (HasParameterArea ||
2690 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2691 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, true);
2693 FI = MFI->CreateStackObject(ArgSize, Align, false);
2694 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2696 // Handle aggregates smaller than 8 bytes.
2697 if (ObjSize < PtrByteSize) {
2698 // The value of the object is its address, which differs from the
2699 // address of the enclosing doubleword on big-endian systems.
2701 if (!isLittleEndian) {
2702 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2703 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2705 InVals.push_back(Arg);
2707 if (GPR_idx != Num_GPR_Regs) {
2708 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2709 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2712 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2713 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2714 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2715 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2716 MachinePointerInfo(FuncArg),
2717 ObjType, false, false, 0);
2719 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2720 // store the whole register as-is to the parameter save area
2722 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2723 MachinePointerInfo(FuncArg),
2727 MemOps.push_back(Store);
2729 // Whether we copied from a register or not, advance the offset
2730 // into the parameter save area by a full doubleword.
2731 ArgOffset += PtrByteSize;
2735 // The value of the object is its address, which is the address of
2736 // its first stack doubleword.
2737 InVals.push_back(FIN);
2739 // Store whatever pieces of the object are in registers to memory.
2740 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2741 if (GPR_idx == Num_GPR_Regs)
2744 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2745 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2748 SDValue Off = DAG.getConstant(j, PtrVT);
2749 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2751 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2752 MachinePointerInfo(FuncArg, j),
2754 MemOps.push_back(Store);
2757 ArgOffset += ArgSize;
2761 switch (ObjectVT.getSimpleVT().SimpleTy) {
2762 default: llvm_unreachable("Unhandled argument type!");
2766 // These can be scalar arguments or elements of an integer array type
2767 // passed directly. Clang may use those instead of "byval" aggregate
2768 // types to avoid forcing arguments to memory unnecessarily.
2769 if (GPR_idx != Num_GPR_Regs) {
2770 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2771 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2773 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2774 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2775 // value to MVT::i64 and then truncate to the correct register size.
2776 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2779 ArgSize = PtrByteSize;
2786 // These can be scalar arguments or elements of a float array type
2787 // passed directly. The latter are used to implement ELFv2 homogenous
2788 // float aggregates.
2789 if (FPR_idx != Num_FPR_Regs) {
2792 if (ObjectVT == MVT::f32)
2793 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2795 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2796 &PPC::VSFRCRegClass :
2797 &PPC::F8RCRegClass);
2799 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2801 } else if (GPR_idx != Num_GPR_Regs) {
2802 // This can only ever happen in the presence of f32 array types,
2803 // since otherwise we never run out of FPRs before running out
2805 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2806 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2808 if (ObjectVT == MVT::f32) {
2809 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2810 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2811 DAG.getConstant(32, MVT::i32));
2812 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2815 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2820 // When passing an array of floats, the array occupies consecutive
2821 // space in the argument area; only round up to the next doubleword
2822 // at the end of the array. Otherwise, each float takes 8 bytes.
2823 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2824 ArgOffset += ArgSize;
2825 if (Flags.isInConsecutiveRegsLast())
2826 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2834 // These can be scalar arguments or elements of a vector array type
2835 // passed directly. The latter are used to implement ELFv2 homogenous
2836 // vector aggregates.
2837 if (VR_idx != Num_VR_Regs) {
2838 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2839 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2840 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2841 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2850 // We need to load the argument to a virtual register if we determined
2851 // above that we ran out of physical registers of the appropriate type.
2853 if (ObjSize < ArgSize && !isLittleEndian)
2854 CurArgOffset += ArgSize - ObjSize;
2855 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2856 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2857 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2858 false, false, false, 0);
2861 InVals.push_back(ArgVal);
2864 // Area that is at least reserved in the caller of this function.
2865 unsigned MinReservedArea;
2866 if (HasParameterArea)
2867 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2869 MinReservedArea = LinkageSize;
2871 // Set the size that is at least reserved in caller of this function. Tail
2872 // call optimized functions' reserved stack space needs to be aligned so that
2873 // taking the difference between two stack areas will result in an aligned
2875 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2876 FuncInfo->setMinReservedArea(MinReservedArea);
2878 // If the function takes variable number of arguments, make a frame index for
2879 // the start of the first vararg value... for expansion of llvm.va_start.
2881 int Depth = ArgOffset;
2883 FuncInfo->setVarArgsFrameIndex(
2884 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2885 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2887 // If this function is vararg, store any remaining integer argument regs
2888 // to their spots on the stack so that they may be loaded by deferencing the
2889 // result of va_next.
2890 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2891 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2892 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2893 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2894 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2895 MachinePointerInfo(), false, false, 0);
2896 MemOps.push_back(Store);
2897 // Increment the address by four for the next argument to store
2898 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2899 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2903 if (!MemOps.empty())
2904 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2910 PPCTargetLowering::LowerFormalArguments_Darwin(
2912 CallingConv::ID CallConv, bool isVarArg,
2913 const SmallVectorImpl<ISD::InputArg>
2915 SDLoc dl, SelectionDAG &DAG,
2916 SmallVectorImpl<SDValue> &InVals) const {
2917 // TODO: add description of PPC stack frame format, or at least some docs.
2919 MachineFunction &MF = DAG.getMachineFunction();
2920 MachineFrameInfo *MFI = MF.getFrameInfo();
2921 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2923 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2924 bool isPPC64 = PtrVT == MVT::i64;
2925 // Potential tail calls could cause overwriting of argument stack slots.
2926 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2927 (CallConv == CallingConv::Fast));
2928 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2930 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2932 unsigned ArgOffset = LinkageSize;
2933 // Area that is at least reserved in caller of this function.
2934 unsigned MinReservedArea = ArgOffset;
2936 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2937 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2938 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2940 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2941 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2942 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2945 static const MCPhysReg *FPR = GetFPR();
2947 static const MCPhysReg VR[] = {
2948 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2949 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2952 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2953 const unsigned Num_FPR_Regs = 13;
2954 const unsigned Num_VR_Regs = array_lengthof( VR);
2956 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2958 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2960 // In 32-bit non-varargs functions, the stack space for vectors is after the
2961 // stack space for non-vectors. We do not use this space unless we have
2962 // too many vectors to fit in registers, something that only occurs in
2963 // constructed examples:), but we have to walk the arglist to figure
2964 // that out...for the pathological case, compute VecArgOffset as the
2965 // start of the vector parameter area. Computing VecArgOffset is the
2966 // entire point of the following loop.
2967 unsigned VecArgOffset = ArgOffset;
2968 if (!isVarArg && !isPPC64) {
2969 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2971 EVT ObjectVT = Ins[ArgNo].VT;
2972 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2974 if (Flags.isByVal()) {
2975 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2976 unsigned ObjSize = Flags.getByValSize();
2978 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2979 VecArgOffset += ArgSize;
2983 switch(ObjectVT.getSimpleVT().SimpleTy) {
2984 default: llvm_unreachable("Unhandled argument type!");
2990 case MVT::i64: // PPC64
2992 // FIXME: We are guaranteed to be !isPPC64 at this point.
2993 // Does MVT::i64 apply?
3000 // Nothing to do, we're only looking at Nonvector args here.
3005 // We've found where the vector parameter area in memory is. Skip the
3006 // first 12 parameters; these don't use that memory.
3007 VecArgOffset = ((VecArgOffset+15)/16)*16;
3008 VecArgOffset += 12*16;
3010 // Add DAG nodes to load the arguments or copy them out of registers. On
3011 // entry to a function on PPC, the arguments start after the linkage area,
3012 // although the first ones are often in registers.
3014 SmallVector<SDValue, 8> MemOps;
3015 unsigned nAltivecParamsAtEnd = 0;
3016 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3017 unsigned CurArgIdx = 0;
3018 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3020 bool needsLoad = false;
3021 EVT ObjectVT = Ins[ArgNo].VT;
3022 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3023 unsigned ArgSize = ObjSize;
3024 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3025 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3026 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3028 unsigned CurArgOffset = ArgOffset;
3030 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3031 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3032 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3033 if (isVarArg || isPPC64) {
3034 MinReservedArea = ((MinReservedArea+15)/16)*16;
3035 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3038 } else nAltivecParamsAtEnd++;
3040 // Calculate min reserved area.
3041 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3045 // FIXME the codegen can be much improved in some cases.
3046 // We do not have to keep everything in memory.
3047 if (Flags.isByVal()) {
3048 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3049 ObjSize = Flags.getByValSize();
3050 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3051 // Objects of size 1 and 2 are right justified, everything else is
3052 // left justified. This means the memory address is adjusted forwards.
3053 if (ObjSize==1 || ObjSize==2) {
3054 CurArgOffset = CurArgOffset + (4 - ObjSize);
3056 // The value of the object is its address.
3057 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
3058 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3059 InVals.push_back(FIN);
3060 if (ObjSize==1 || ObjSize==2) {
3061 if (GPR_idx != Num_GPR_Regs) {
3064 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3066 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3067 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3068 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3069 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3070 MachinePointerInfo(FuncArg),
3071 ObjType, false, false, 0);
3072 MemOps.push_back(Store);
3076 ArgOffset += PtrByteSize;
3080 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3081 // Store whatever pieces of the object are in registers
3082 // to memory. ArgOffset will be the address of the beginning
3084 if (GPR_idx != Num_GPR_Regs) {
3087 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3089 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3090 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3091 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3092 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3093 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3094 MachinePointerInfo(FuncArg, j),
3096 MemOps.push_back(Store);
3098 ArgOffset += PtrByteSize;
3100 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3107 switch (ObjectVT.getSimpleVT().SimpleTy) {
3108 default: llvm_unreachable("Unhandled argument type!");
3112 if (GPR_idx != Num_GPR_Regs) {
3113 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3114 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3116 if (ObjectVT == MVT::i1)
3117 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3122 ArgSize = PtrByteSize;
3124 // All int arguments reserve stack space in the Darwin ABI.
3125 ArgOffset += PtrByteSize;
3129 case MVT::i64: // PPC64
3130 if (GPR_idx != Num_GPR_Regs) {
3131 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3132 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3134 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3135 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3136 // value to MVT::i64 and then truncate to the correct register size.
3137 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3142 ArgSize = PtrByteSize;
3144 // All int arguments reserve stack space in the Darwin ABI.
3150 // Every 4 bytes of argument space consumes one of the GPRs available for
3151 // argument passing.
3152 if (GPR_idx != Num_GPR_Regs) {
3154 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3157 if (FPR_idx != Num_FPR_Regs) {
3160 if (ObjectVT == MVT::f32)
3161 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3163 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3165 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3171 // All FP arguments reserve stack space in the Darwin ABI.
3172 ArgOffset += isPPC64 ? 8 : ObjSize;
3178 // Note that vector arguments in registers don't reserve stack space,
3179 // except in varargs functions.
3180 if (VR_idx != Num_VR_Regs) {
3181 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3182 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3184 while ((ArgOffset % 16) != 0) {
3185 ArgOffset += PtrByteSize;
3186 if (GPR_idx != Num_GPR_Regs)
3190 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3194 if (!isVarArg && !isPPC64) {
3195 // Vectors go after all the nonvectors.
3196 CurArgOffset = VecArgOffset;
3199 // Vectors are aligned.
3200 ArgOffset = ((ArgOffset+15)/16)*16;
3201 CurArgOffset = ArgOffset;
3209 // We need to load the argument to a virtual register if we determined above
3210 // that we ran out of physical registers of the appropriate type.
3212 int FI = MFI->CreateFixedObject(ObjSize,
3213 CurArgOffset + (ArgSize - ObjSize),
3215 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3216 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3217 false, false, false, 0);
3220 InVals.push_back(ArgVal);
3223 // Allow for Altivec parameters at the end, if needed.
3224 if (nAltivecParamsAtEnd) {
3225 MinReservedArea = ((MinReservedArea+15)/16)*16;
3226 MinReservedArea += 16*nAltivecParamsAtEnd;
3229 // Area that is at least reserved in the caller of this function.
3230 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3232 // Set the size that is at least reserved in caller of this function. Tail
3233 // call optimized functions' reserved stack space needs to be aligned so that
3234 // taking the difference between two stack areas will result in an aligned
3236 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3237 FuncInfo->setMinReservedArea(MinReservedArea);
3239 // If the function takes variable number of arguments, make a frame index for
3240 // the start of the first vararg value... for expansion of llvm.va_start.
3242 int Depth = ArgOffset;
3244 FuncInfo->setVarArgsFrameIndex(
3245 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3247 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3249 // If this function is vararg, store any remaining integer argument regs
3250 // to their spots on the stack so that they may be loaded by deferencing the
3251 // result of va_next.
3252 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3256 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3258 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3260 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3261 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3262 MachinePointerInfo(), false, false, 0);
3263 MemOps.push_back(Store);
3264 // Increment the address by four for the next argument to store
3265 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3266 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3270 if (!MemOps.empty())
3271 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3276 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3277 /// adjusted to accommodate the arguments for the tailcall.
3278 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3279 unsigned ParamSize) {
3281 if (!isTailCall) return 0;
3283 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3284 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3285 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3286 // Remember only if the new adjustement is bigger.
3287 if (SPDiff < FI->getTailCallSPDelta())
3288 FI->setTailCallSPDelta(SPDiff);
3293 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3294 /// for tail call optimization. Targets which want to do tail call
3295 /// optimization should implement this function.
3297 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3298 CallingConv::ID CalleeCC,
3300 const SmallVectorImpl<ISD::InputArg> &Ins,
3301 SelectionDAG& DAG) const {
3302 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3305 // Variable argument functions are not supported.
3309 MachineFunction &MF = DAG.getMachineFunction();
3310 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3311 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3312 // Functions containing by val parameters are not supported.
3313 for (unsigned i = 0; i != Ins.size(); i++) {
3314 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3315 if (Flags.isByVal()) return false;
3318 // Non-PIC/GOT tail calls are supported.
3319 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3322 // At the moment we can only do local tail calls (in same module, hidden
3323 // or protected) if we are generating PIC.
3324 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3325 return G->getGlobal()->hasHiddenVisibility()
3326 || G->getGlobal()->hasProtectedVisibility();
3332 /// isCallCompatibleAddress - Return the immediate to use if the specified
3333 /// 32-bit value is representable in the immediate field of a BxA instruction.
3334 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3335 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3336 if (!C) return nullptr;
3338 int Addr = C->getZExtValue();
3339 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3340 SignExtend32<26>(Addr) != Addr)
3341 return nullptr; // Top 6 bits have to be sext of immediate.
3343 return DAG.getConstant((int)C->getZExtValue() >> 2,
3344 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3349 struct TailCallArgumentInfo {
3354 TailCallArgumentInfo() : FrameIdx(0) {}
3359 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3361 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3363 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3364 SmallVectorImpl<SDValue> &MemOpChains,
3366 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3367 SDValue Arg = TailCallArgs[i].Arg;
3368 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3369 int FI = TailCallArgs[i].FrameIdx;
3370 // Store relative to framepointer.
3371 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3372 MachinePointerInfo::getFixedStack(FI),
3377 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3378 /// the appropriate stack slot for the tail call optimized function call.
3379 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3380 MachineFunction &MF,
3389 // Calculate the new stack slot for the return address.
3390 int SlotSize = isPPC64 ? 8 : 4;
3391 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3393 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3394 NewRetAddrLoc, true);
3395 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3396 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3397 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3398 MachinePointerInfo::getFixedStack(NewRetAddr),
3401 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3402 // slot as the FP is never overwritten.
3405 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3406 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3408 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3409 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3410 MachinePointerInfo::getFixedStack(NewFPIdx),
3417 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3418 /// the position of the argument.
3420 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3421 SDValue Arg, int SPDiff, unsigned ArgOffset,
3422 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3423 int Offset = ArgOffset + SPDiff;
3424 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3425 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3426 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3427 SDValue FIN = DAG.getFrameIndex(FI, VT);
3428 TailCallArgumentInfo Info;
3430 Info.FrameIdxOp = FIN;
3432 TailCallArguments.push_back(Info);
3435 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3436 /// stack slot. Returns the chain as result and the loaded frame pointers in
3437 /// LROpOut/FPOpout. Used when tail calling.
3438 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3446 // Load the LR and FP stack slot for later adjusting.
3447 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3448 LROpOut = getReturnAddrFrameIndex(DAG);
3449 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3450 false, false, false, 0);
3451 Chain = SDValue(LROpOut.getNode(), 1);
3453 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3454 // slot as the FP is never overwritten.
3456 FPOpOut = getFramePointerFrameIndex(DAG);
3457 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3458 false, false, false, 0);
3459 Chain = SDValue(FPOpOut.getNode(), 1);
3465 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3466 /// by "Src" to address "Dst" of size "Size". Alignment information is
3467 /// specified by the specific parameter attribute. The copy will be passed as
3468 /// a byval function parameter.
3469 /// Sometimes what we are copying is the end of a larger object, the part that
3470 /// does not fit in registers.
3472 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3473 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3475 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3476 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3477 false, false, MachinePointerInfo(),
3478 MachinePointerInfo());
3481 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3484 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3485 SDValue Arg, SDValue PtrOff, int SPDiff,
3486 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3487 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3488 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3490 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3495 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3497 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3498 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3499 DAG.getConstant(ArgOffset, PtrVT));
3501 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3502 MachinePointerInfo(), false, false, 0));
3503 // Calculate and remember argument location.
3504 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3509 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3510 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3511 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3512 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3513 MachineFunction &MF = DAG.getMachineFunction();
3515 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3516 // might overwrite each other in case of tail call optimization.
3517 SmallVector<SDValue, 8> MemOpChains2;
3518 // Do not flag preceding copytoreg stuff together with the following stuff.
3520 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3522 if (!MemOpChains2.empty())
3523 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3525 // Store the return address to the appropriate stack slot.
3526 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3527 isPPC64, isDarwinABI, dl);
3529 // Emit callseq_end just before tailcall node.
3530 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3531 DAG.getIntPtrConstant(0, true), InFlag, dl);
3532 InFlag = Chain.getValue(1);
3536 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3537 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3538 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3539 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3540 const PPCSubtarget &Subtarget) {
3542 bool isPPC64 = Subtarget.isPPC64();
3543 bool isSVR4ABI = Subtarget.isSVR4ABI();
3544 bool isELFv2ABI = Subtarget.isELFv2ABI();
3546 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3547 NodeTys.push_back(MVT::Other); // Returns a chain
3548 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3550 unsigned CallOpc = PPCISD::CALL;
3552 bool needIndirectCall = true;
3553 if (!isSVR4ABI || !isPPC64)
3554 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3555 // If this is an absolute destination address, use the munged value.
3556 Callee = SDValue(Dest, 0);
3557 needIndirectCall = false;
3560 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3561 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3562 // Use indirect calls for ALL functions calls in JIT mode, since the
3563 // far-call stubs may be outside relocation limits for a BL instruction.
3564 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3565 unsigned OpFlags = 0;
3566 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3567 (Subtarget.getTargetTriple().isMacOSX() &&
3568 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3569 (G->getGlobal()->isDeclaration() ||
3570 G->getGlobal()->isWeakForLinker())) ||
3571 (Subtarget.isTargetELF() && !isPPC64 &&
3572 !G->getGlobal()->hasLocalLinkage() &&
3573 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3574 // PC-relative references to external symbols should go through $stub,
3575 // unless we're building with the leopard linker or later, which
3576 // automatically synthesizes these stubs.
3577 OpFlags = PPCII::MO_PLT_OR_STUB;
3580 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3581 // every direct call is) turn it into a TargetGlobalAddress /
3582 // TargetExternalSymbol node so that legalize doesn't hack it.
3583 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3584 Callee.getValueType(),
3586 needIndirectCall = false;
3590 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3591 unsigned char OpFlags = 0;
3593 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3594 (Subtarget.getTargetTriple().isMacOSX() &&
3595 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3596 (Subtarget.isTargetELF() && !isPPC64 &&
3597 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3598 // PC-relative references to external symbols should go through $stub,
3599 // unless we're building with the leopard linker or later, which
3600 // automatically synthesizes these stubs.
3601 OpFlags = PPCII::MO_PLT_OR_STUB;
3604 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3606 needIndirectCall = false;
3609 if (needIndirectCall) {
3610 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3611 // to do the call, we can't use PPCISD::CALL.
3612 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3614 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3615 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3616 // entry point, but to the function descriptor (the function entry point
3617 // address is part of the function descriptor though).
3618 // The function descriptor is a three doubleword structure with the
3619 // following fields: function entry point, TOC base address and
3620 // environment pointer.
3621 // Thus for a call through a function pointer, the following actions need
3623 // 1. Save the TOC of the caller in the TOC save area of its stack
3624 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3625 // 2. Load the address of the function entry point from the function
3627 // 3. Load the TOC of the callee from the function descriptor into r2.
3628 // 4. Load the environment pointer from the function descriptor into
3630 // 5. Branch to the function entry point address.
3631 // 6. On return of the callee, the TOC of the caller needs to be
3632 // restored (this is done in FinishCall()).
3634 // All those operations are flagged together to ensure that no other
3635 // operations can be scheduled in between. E.g. without flagging the
3636 // operations together, a TOC access in the caller could be scheduled
3637 // between the load of the callee TOC and the branch to the callee, which
3638 // results in the TOC access going through the TOC of the callee instead
3639 // of going through the TOC of the caller, which leads to incorrect code.
3641 // Load the address of the function entry point from the function
3643 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3644 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3645 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3646 Chain = LoadFuncPtr.getValue(1);
3647 InFlag = LoadFuncPtr.getValue(2);
3649 // Load environment pointer into r11.
3650 // Offset of the environment pointer within the function descriptor.
3651 SDValue PtrOff = DAG.getIntPtrConstant(16);
3653 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3654 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3656 Chain = LoadEnvPtr.getValue(1);
3657 InFlag = LoadEnvPtr.getValue(2);
3659 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3661 Chain = EnvVal.getValue(0);
3662 InFlag = EnvVal.getValue(1);
3664 // Load TOC of the callee into r2. We are using a target-specific load
3665 // with r2 hard coded, because the result of a target-independent load
3666 // would never go directly into r2, since r2 is a reserved register (which
3667 // prevents the register allocator from allocating it), resulting in an
3668 // additional register being allocated and an unnecessary move instruction
3670 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3671 SDValue TOCOff = DAG.getIntPtrConstant(8);
3672 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3673 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3675 Chain = LoadTOCPtr.getValue(0);
3676 InFlag = LoadTOCPtr.getValue(1);
3678 MTCTROps[0] = Chain;
3679 MTCTROps[1] = LoadFuncPtr;
3680 MTCTROps[2] = InFlag;
3683 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3684 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3685 InFlag = Chain.getValue(1);
3688 NodeTys.push_back(MVT::Other);
3689 NodeTys.push_back(MVT::Glue);
3690 Ops.push_back(Chain);
3691 CallOpc = PPCISD::BCTRL;
3692 Callee.setNode(nullptr);
3693 // Add use of X11 (holding environment pointer)
3694 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3695 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3696 // Add CTR register as callee so a bctr can be emitted later.
3698 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3701 // If this is a direct call, pass the chain and the callee.
3702 if (Callee.getNode()) {
3703 Ops.push_back(Chain);
3704 Ops.push_back(Callee);
3706 // If this is a tail call add stack pointer delta.
3708 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3710 // Add argument registers to the end of the list so that they are known live
3712 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3713 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3714 RegsToPass[i].second.getValueType()));
3716 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3717 if (Callee.getNode() && isELFv2ABI)
3718 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3724 bool isLocalCall(const SDValue &Callee)
3726 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3727 return !G->getGlobal()->isDeclaration() &&
3728 !G->getGlobal()->isWeakForLinker();
3733 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3734 CallingConv::ID CallConv, bool isVarArg,
3735 const SmallVectorImpl<ISD::InputArg> &Ins,
3736 SDLoc dl, SelectionDAG &DAG,
3737 SmallVectorImpl<SDValue> &InVals) const {
3739 SmallVector<CCValAssign, 16> RVLocs;
3740 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3741 getTargetMachine(), RVLocs, *DAG.getContext());
3742 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3744 // Copy all of the result registers out of their specified physreg.
3745 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3746 CCValAssign &VA = RVLocs[i];
3747 assert(VA.isRegLoc() && "Can only return in registers!");
3749 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3750 VA.getLocReg(), VA.getLocVT(), InFlag);
3751 Chain = Val.getValue(1);
3752 InFlag = Val.getValue(2);
3754 switch (VA.getLocInfo()) {
3755 default: llvm_unreachable("Unknown loc info!");
3756 case CCValAssign::Full: break;
3757 case CCValAssign::AExt:
3758 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3760 case CCValAssign::ZExt:
3761 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3762 DAG.getValueType(VA.getValVT()));
3763 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3765 case CCValAssign::SExt:
3766 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3767 DAG.getValueType(VA.getValVT()));
3768 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3772 InVals.push_back(Val);
3779 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3780 bool isTailCall, bool isVarArg,
3782 SmallVector<std::pair<unsigned, SDValue>, 8>
3784 SDValue InFlag, SDValue Chain,
3786 int SPDiff, unsigned NumBytes,
3787 const SmallVectorImpl<ISD::InputArg> &Ins,
3788 SmallVectorImpl<SDValue> &InVals) const {
3790 bool isELFv2ABI = Subtarget.isELFv2ABI();
3791 std::vector<EVT> NodeTys;
3792 SmallVector<SDValue, 8> Ops;
3793 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3794 isTailCall, RegsToPass, Ops, NodeTys,
3797 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3798 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3799 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3801 // When performing tail call optimization the callee pops its arguments off
3802 // the stack. Account for this here so these bytes can be pushed back on in
3803 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3804 int BytesCalleePops =
3805 (CallConv == CallingConv::Fast &&
3806 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3808 // Add a register mask operand representing the call-preserved registers.
3809 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3810 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3811 assert(Mask && "Missing call preserved mask for calling convention");
3812 Ops.push_back(DAG.getRegisterMask(Mask));
3814 if (InFlag.getNode())
3815 Ops.push_back(InFlag);
3819 assert(((Callee.getOpcode() == ISD::Register &&
3820 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3821 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3822 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3823 isa<ConstantSDNode>(Callee)) &&
3824 "Expecting an global address, external symbol, absolute value or register");
3826 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3829 // Add a NOP immediately after the branch instruction when using the 64-bit
3830 // SVR4 ABI. At link time, if caller and callee are in a different module and
3831 // thus have a different TOC, the call will be replaced with a call to a stub
3832 // function which saves the current TOC, loads the TOC of the callee and
3833 // branches to the callee. The NOP will be replaced with a load instruction
3834 // which restores the TOC of the caller from the TOC save slot of the current
3835 // stack frame. If caller and callee belong to the same module (and have the
3836 // same TOC), the NOP will remain unchanged.
3838 bool needsTOCRestore = false;
3839 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3840 if (CallOpc == PPCISD::BCTRL) {
3841 // This is a call through a function pointer.
3842 // Restore the caller TOC from the save area into R2.
3843 // See PrepareCall() for more information about calls through function
3844 // pointers in the 64-bit SVR4 ABI.
3845 // We are using a target-specific load with r2 hard coded, because the
3846 // result of a target-independent load would never go directly into r2,
3847 // since r2 is a reserved register (which prevents the register allocator
3848 // from allocating it), resulting in an additional register being
3849 // allocated and an unnecessary move instruction being generated.
3850 needsTOCRestore = true;
3851 } else if ((CallOpc == PPCISD::CALL) &&
3852 (!isLocalCall(Callee) ||
3853 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3854 // Otherwise insert NOP for non-local calls.
3855 CallOpc = PPCISD::CALL_NOP;
3859 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3860 InFlag = Chain.getValue(1);
3862 if (needsTOCRestore) {
3863 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3864 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3865 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3866 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3867 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3868 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3869 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3870 InFlag = Chain.getValue(1);
3873 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3874 DAG.getIntPtrConstant(BytesCalleePops, true),
3877 InFlag = Chain.getValue(1);
3879 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3880 Ins, dl, DAG, InVals);
3884 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3885 SmallVectorImpl<SDValue> &InVals) const {
3886 SelectionDAG &DAG = CLI.DAG;
3888 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3889 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3890 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3891 SDValue Chain = CLI.Chain;
3892 SDValue Callee = CLI.Callee;
3893 bool &isTailCall = CLI.IsTailCall;
3894 CallingConv::ID CallConv = CLI.CallConv;
3895 bool isVarArg = CLI.IsVarArg;
3898 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3901 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3902 report_fatal_error("failed to perform tail call elimination on a call "
3903 "site marked musttail");
3905 if (Subtarget.isSVR4ABI()) {
3906 if (Subtarget.isPPC64())
3907 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3908 isTailCall, Outs, OutVals, Ins,
3911 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3912 isTailCall, Outs, OutVals, Ins,
3916 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3917 isTailCall, Outs, OutVals, Ins,
3922 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3923 CallingConv::ID CallConv, bool isVarArg,
3925 const SmallVectorImpl<ISD::OutputArg> &Outs,
3926 const SmallVectorImpl<SDValue> &OutVals,
3927 const SmallVectorImpl<ISD::InputArg> &Ins,
3928 SDLoc dl, SelectionDAG &DAG,
3929 SmallVectorImpl<SDValue> &InVals) const {
3930 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3931 // of the 32-bit SVR4 ABI stack frame layout.
3933 assert((CallConv == CallingConv::C ||
3934 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3936 unsigned PtrByteSize = 4;
3938 MachineFunction &MF = DAG.getMachineFunction();
3940 // Mark this function as potentially containing a function that contains a
3941 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3942 // and restoring the callers stack pointer in this functions epilog. This is
3943 // done because by tail calling the called function might overwrite the value
3944 // in this function's (MF) stack pointer stack slot 0(SP).
3945 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3946 CallConv == CallingConv::Fast)
3947 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3949 // Count how many bytes are to be pushed on the stack, including the linkage
3950 // area, parameter list area and the part of the local variable space which
3951 // contains copies of aggregates which are passed by value.
3953 // Assign locations to all of the outgoing arguments.
3954 SmallVector<CCValAssign, 16> ArgLocs;
3955 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3956 getTargetMachine(), ArgLocs, *DAG.getContext());
3958 // Reserve space for the linkage area on the stack.
3959 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3963 // Handle fixed and variable vector arguments differently.
3964 // Fixed vector arguments go into registers as long as registers are
3965 // available. Variable vector arguments always go into memory.
3966 unsigned NumArgs = Outs.size();
3968 for (unsigned i = 0; i != NumArgs; ++i) {
3969 MVT ArgVT = Outs[i].VT;
3970 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3973 if (Outs[i].IsFixed) {
3974 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3977 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3983 errs() << "Call operand #" << i << " has unhandled type "
3984 << EVT(ArgVT).getEVTString() << "\n";
3986 llvm_unreachable(nullptr);
3990 // All arguments are treated the same.
3991 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3994 // Assign locations to all of the outgoing aggregate by value arguments.
3995 SmallVector<CCValAssign, 16> ByValArgLocs;
3996 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3997 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3999 // Reserve stack space for the allocations in CCInfo.
4000 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4002 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4004 // Size of the linkage area, parameter list area and the part of the local
4005 // space variable where copies of aggregates which are passed by value are
4007 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4009 // Calculate by how many bytes the stack has to be adjusted in case of tail
4010 // call optimization.
4011 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4013 // Adjust the stack pointer for the new arguments...
4014 // These operations are automatically eliminated by the prolog/epilog pass
4015 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4017 SDValue CallSeqStart = Chain;
4019 // Load the return address and frame pointer so it can be moved somewhere else
4022 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4025 // Set up a copy of the stack pointer for use loading and storing any
4026 // arguments that may not fit in the registers available for argument
4028 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4030 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4031 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4032 SmallVector<SDValue, 8> MemOpChains;
4034 bool seenFloatArg = false;
4035 // Walk the register/memloc assignments, inserting copies/loads.
4036 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4039 CCValAssign &VA = ArgLocs[i];
4040 SDValue Arg = OutVals[i];
4041 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4043 if (Flags.isByVal()) {
4044 // Argument is an aggregate which is passed by value, thus we need to
4045 // create a copy of it in the local variable space of the current stack
4046 // frame (which is the stack frame of the caller) and pass the address of
4047 // this copy to the callee.
4048 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4049 CCValAssign &ByValVA = ByValArgLocs[j++];
4050 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4052 // Memory reserved in the local variable space of the callers stack frame.
4053 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4055 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4056 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4058 // Create a copy of the argument in the local area of the current
4060 SDValue MemcpyCall =
4061 CreateCopyOfByValArgument(Arg, PtrOff,
4062 CallSeqStart.getNode()->getOperand(0),
4065 // This must go outside the CALLSEQ_START..END.
4066 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4067 CallSeqStart.getNode()->getOperand(1),
4069 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4070 NewCallSeqStart.getNode());
4071 Chain = CallSeqStart = NewCallSeqStart;
4073 // Pass the address of the aggregate copy on the stack either in a
4074 // physical register or in the parameter list area of the current stack
4075 // frame to the callee.
4079 if (VA.isRegLoc()) {
4080 if (Arg.getValueType() == MVT::i1)
4081 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4083 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4084 // Put argument in a physical register.
4085 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4087 // Put argument in the parameter list area of the current stack frame.
4088 assert(VA.isMemLoc());
4089 unsigned LocMemOffset = VA.getLocMemOffset();
4092 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4093 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4095 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4096 MachinePointerInfo(),
4099 // Calculate and remember argument location.
4100 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4106 if (!MemOpChains.empty())
4107 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4109 // Build a sequence of copy-to-reg nodes chained together with token chain
4110 // and flag operands which copy the outgoing args into the appropriate regs.
4112 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4113 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4114 RegsToPass[i].second, InFlag);
4115 InFlag = Chain.getValue(1);
4118 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4121 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4122 SDValue Ops[] = { Chain, InFlag };
4124 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4125 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4127 InFlag = Chain.getValue(1);
4131 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4132 false, TailCallArguments);
4134 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4135 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4139 // Copy an argument into memory, being careful to do this outside the
4140 // call sequence for the call to which the argument belongs.
4142 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4143 SDValue CallSeqStart,
4144 ISD::ArgFlagsTy Flags,
4147 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4148 CallSeqStart.getNode()->getOperand(0),
4150 // The MEMCPY must go outside the CALLSEQ_START..END.
4151 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4152 CallSeqStart.getNode()->getOperand(1),
4154 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4155 NewCallSeqStart.getNode());
4156 return NewCallSeqStart;
4160 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4161 CallingConv::ID CallConv, bool isVarArg,
4163 const SmallVectorImpl<ISD::OutputArg> &Outs,
4164 const SmallVectorImpl<SDValue> &OutVals,
4165 const SmallVectorImpl<ISD::InputArg> &Ins,
4166 SDLoc dl, SelectionDAG &DAG,
4167 SmallVectorImpl<SDValue> &InVals) const {
4169 bool isELFv2ABI = Subtarget.isELFv2ABI();
4170 bool isLittleEndian = Subtarget.isLittleEndian();
4171 unsigned NumOps = Outs.size();
4173 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4174 unsigned PtrByteSize = 8;
4176 MachineFunction &MF = DAG.getMachineFunction();
4178 // Mark this function as potentially containing a function that contains a
4179 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4180 // and restoring the callers stack pointer in this functions epilog. This is
4181 // done because by tail calling the called function might overwrite the value
4182 // in this function's (MF) stack pointer stack slot 0(SP).
4183 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4184 CallConv == CallingConv::Fast)
4185 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4187 // Count how many bytes are to be pushed on the stack, including the linkage
4188 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4189 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4190 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4191 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4193 unsigned NumBytes = LinkageSize;
4195 // Add up all the space actually used.
4196 for (unsigned i = 0; i != NumOps; ++i) {
4197 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4198 EVT ArgVT = Outs[i].VT;
4199 EVT OrigVT = Outs[i].ArgVT;
4201 /* Respect alignment of argument on the stack. */
4203 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4204 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4206 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4207 if (Flags.isInConsecutiveRegsLast())
4208 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4211 unsigned NumBytesActuallyUsed = NumBytes;
4213 // The prolog code of the callee may store up to 8 GPR argument registers to
4214 // the stack, allowing va_start to index over them in memory if its varargs.
4215 // Because we cannot tell if this is needed on the caller side, we have to
4216 // conservatively assume that it is needed. As such, make sure we have at
4217 // least enough stack space for the caller to store the 8 GPRs.
4218 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4219 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4221 // Tail call needs the stack to be aligned.
4222 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4223 CallConv == CallingConv::Fast)
4224 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4226 // Calculate by how many bytes the stack has to be adjusted in case of tail
4227 // call optimization.
4228 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4230 // To protect arguments on the stack from being clobbered in a tail call,
4231 // force all the loads to happen before doing any other lowering.
4233 Chain = DAG.getStackArgumentTokenFactor(Chain);
4235 // Adjust the stack pointer for the new arguments...
4236 // These operations are automatically eliminated by the prolog/epilog pass
4237 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4239 SDValue CallSeqStart = Chain;
4241 // Load the return address and frame pointer so it can be move somewhere else
4244 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4247 // Set up a copy of the stack pointer for use loading and storing any
4248 // arguments that may not fit in the registers available for argument
4250 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4252 // Figure out which arguments are going to go in registers, and which in
4253 // memory. Also, if this is a vararg function, floating point operations
4254 // must be stored to our stack, and loaded into integer regs as well, if
4255 // any integer regs are available for argument passing.
4256 unsigned ArgOffset = LinkageSize;
4257 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4259 static const MCPhysReg GPR[] = {
4260 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4261 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4263 static const MCPhysReg *FPR = GetFPR();
4265 static const MCPhysReg VR[] = {
4266 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4267 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4269 static const MCPhysReg VSRH[] = {
4270 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4271 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4274 const unsigned NumGPRs = array_lengthof(GPR);
4275 const unsigned NumFPRs = 13;
4276 const unsigned NumVRs = array_lengthof(VR);
4278 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4279 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4281 SmallVector<SDValue, 8> MemOpChains;
4282 for (unsigned i = 0; i != NumOps; ++i) {
4283 SDValue Arg = OutVals[i];
4284 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4285 EVT ArgVT = Outs[i].VT;
4286 EVT OrigVT = Outs[i].ArgVT;
4288 /* Respect alignment of argument on the stack. */
4290 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4291 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4293 /* Compute GPR index associated with argument offset. */
4294 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4295 GPR_idx = std::min(GPR_idx, NumGPRs);
4297 // PtrOff will be used to store the current argument to the stack if a
4298 // register cannot be found for it.
4301 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4303 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4305 // Promote integers to 64-bit values.
4306 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4307 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4308 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4309 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4312 // FIXME memcpy is used way more than necessary. Correctness first.
4313 // Note: "by value" is code for passing a structure by value, not
4315 if (Flags.isByVal()) {
4316 // Note: Size includes alignment padding, so
4317 // struct x { short a; char b; }
4318 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4319 // These are the proper values we need for right-justifying the
4320 // aggregate in a parameter register.
4321 unsigned Size = Flags.getByValSize();
4323 // An empty aggregate parameter takes up no storage and no
4328 // All aggregates smaller than 8 bytes must be passed right-justified.
4329 if (Size==1 || Size==2 || Size==4) {
4330 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4331 if (GPR_idx != NumGPRs) {
4332 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4333 MachinePointerInfo(), VT,
4335 MemOpChains.push_back(Load.getValue(1));
4336 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4338 ArgOffset += PtrByteSize;
4343 if (GPR_idx == NumGPRs && Size < 8) {
4344 SDValue AddPtr = PtrOff;
4345 if (!isLittleEndian) {
4346 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4347 PtrOff.getValueType());
4348 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4350 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4353 ArgOffset += PtrByteSize;
4356 // Copy entire object into memory. There are cases where gcc-generated
4357 // code assumes it is there, even if it could be put entirely into
4358 // registers. (This is not what the doc says.)
4360 // FIXME: The above statement is likely due to a misunderstanding of the
4361 // documents. All arguments must be copied into the parameter area BY
4362 // THE CALLEE in the event that the callee takes the address of any
4363 // formal argument. That has not yet been implemented. However, it is
4364 // reasonable to use the stack area as a staging area for the register
4367 // Skip this for small aggregates, as we will use the same slot for a
4368 // right-justified copy, below.
4370 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4374 // When a register is available, pass a small aggregate right-justified.
4375 if (Size < 8 && GPR_idx != NumGPRs) {
4376 // The easiest way to get this right-justified in a register
4377 // is to copy the structure into the rightmost portion of a
4378 // local variable slot, then load the whole slot into the
4380 // FIXME: The memcpy seems to produce pretty awful code for
4381 // small aggregates, particularly for packed ones.
4382 // FIXME: It would be preferable to use the slot in the
4383 // parameter save area instead of a new local variable.
4384 SDValue AddPtr = PtrOff;
4385 if (!isLittleEndian) {
4386 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4387 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4389 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4393 // Load the slot into the register.
4394 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4395 MachinePointerInfo(),
4396 false, false, false, 0);
4397 MemOpChains.push_back(Load.getValue(1));
4398 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4400 // Done with this argument.
4401 ArgOffset += PtrByteSize;
4405 // For aggregates larger than PtrByteSize, copy the pieces of the
4406 // object that fit into registers from the parameter save area.
4407 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4408 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4409 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4410 if (GPR_idx != NumGPRs) {
4411 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4412 MachinePointerInfo(),
4413 false, false, false, 0);
4414 MemOpChains.push_back(Load.getValue(1));
4415 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4416 ArgOffset += PtrByteSize;
4418 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4425 switch (Arg.getSimpleValueType().SimpleTy) {
4426 default: llvm_unreachable("Unexpected ValueType for argument!");
4430 // These can be scalar arguments or elements of an integer array type
4431 // passed directly. Clang may use those instead of "byval" aggregate
4432 // types to avoid forcing arguments to memory unnecessarily.
4433 if (GPR_idx != NumGPRs) {
4434 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4436 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4437 true, isTailCall, false, MemOpChains,
4438 TailCallArguments, dl);
4440 ArgOffset += PtrByteSize;
4444 // These can be scalar arguments or elements of a float array type
4445 // passed directly. The latter are used to implement ELFv2 homogenous
4446 // float aggregates.
4448 // Named arguments go into FPRs first, and once they overflow, the
4449 // remaining arguments go into GPRs and then the parameter save area.
4450 // Unnamed arguments for vararg functions always go to GPRs and
4451 // then the parameter save area. For now, put all arguments to vararg
4452 // routines always in both locations (FPR *and* GPR or stack slot).
4453 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4455 // First load the argument into the next available FPR.
4456 if (FPR_idx != NumFPRs)
4457 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4459 // Next, load the argument into GPR or stack slot if needed.
4460 if (!NeedGPROrStack)
4462 else if (GPR_idx != NumGPRs) {
4463 // In the non-vararg case, this can only ever happen in the
4464 // presence of f32 array types, since otherwise we never run
4465 // out of FPRs before running out of GPRs.
4468 // Double values are always passed in a single GPR.
4469 if (Arg.getValueType() != MVT::f32) {
4470 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4472 // Non-array float values are extended and passed in a GPR.
4473 } else if (!Flags.isInConsecutiveRegs()) {
4474 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4475 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4477 // If we have an array of floats, we collect every odd element
4478 // together with its predecessor into one GPR.
4479 } else if (ArgOffset % PtrByteSize != 0) {
4481 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4482 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4483 if (!isLittleEndian)
4485 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4487 // The final element, if even, goes into the first half of a GPR.
4488 } else if (Flags.isInConsecutiveRegsLast()) {
4489 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4490 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4491 if (!isLittleEndian)
4492 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4493 DAG.getConstant(32, MVT::i32));
4495 // Non-final even elements are skipped; they will be handled
4496 // together the with subsequent argument on the next go-around.
4500 if (ArgVal.getNode())
4501 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4503 // Single-precision floating-point values are mapped to the
4504 // second (rightmost) word of the stack doubleword.
4505 if (Arg.getValueType() == MVT::f32 &&
4506 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4507 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4508 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4511 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4512 true, isTailCall, false, MemOpChains,
4513 TailCallArguments, dl);
4515 // When passing an array of floats, the array occupies consecutive
4516 // space in the argument area; only round up to the next doubleword
4517 // at the end of the array. Otherwise, each float takes 8 bytes.
4518 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4519 Flags.isInConsecutiveRegs()) ? 4 : 8;
4520 if (Flags.isInConsecutiveRegsLast())
4521 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4530 // These can be scalar arguments or elements of a vector array type
4531 // passed directly. The latter are used to implement ELFv2 homogenous
4532 // vector aggregates.
4534 // For a varargs call, named arguments go into VRs or on the stack as
4535 // usual; unnamed arguments always go to the stack or the corresponding
4536 // GPRs when within range. For now, we always put the value in both
4537 // locations (or even all three).
4539 // We could elide this store in the case where the object fits
4540 // entirely in R registers. Maybe later.
4541 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4542 MachinePointerInfo(), false, false, 0);
4543 MemOpChains.push_back(Store);
4544 if (VR_idx != NumVRs) {
4545 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4546 MachinePointerInfo(),
4547 false, false, false, 0);
4548 MemOpChains.push_back(Load.getValue(1));
4550 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4551 Arg.getSimpleValueType() == MVT::v2i64) ?
4552 VSRH[VR_idx] : VR[VR_idx];
4555 RegsToPass.push_back(std::make_pair(VReg, Load));
4558 for (unsigned i=0; i<16; i+=PtrByteSize) {
4559 if (GPR_idx == NumGPRs)
4561 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4562 DAG.getConstant(i, PtrVT));
4563 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4564 false, false, false, 0);
4565 MemOpChains.push_back(Load.getValue(1));
4566 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4571 // Non-varargs Altivec params go into VRs or on the stack.
4572 if (VR_idx != NumVRs) {
4573 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4574 Arg.getSimpleValueType() == MVT::v2i64) ?
4575 VSRH[VR_idx] : VR[VR_idx];
4578 RegsToPass.push_back(std::make_pair(VReg, Arg));
4580 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4581 true, isTailCall, true, MemOpChains,
4582 TailCallArguments, dl);
4589 assert(NumBytesActuallyUsed == ArgOffset);
4590 (void)NumBytesActuallyUsed;
4592 if (!MemOpChains.empty())
4593 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4595 // Check if this is an indirect call (MTCTR/BCTRL).
4596 // See PrepareCall() for more information about calls through function
4597 // pointers in the 64-bit SVR4 ABI.
4599 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4600 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4601 // Load r2 into a virtual register and store it to the TOC save area.
4602 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4603 // TOC save area offset.
4604 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4605 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4606 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4607 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4609 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4610 // This does not mean the MTCTR instruction must use R12; it's easier
4611 // to model this as an extra parameter, so do that.
4613 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4616 // Build a sequence of copy-to-reg nodes chained together with token chain
4617 // and flag operands which copy the outgoing args into the appropriate regs.
4619 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4620 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4621 RegsToPass[i].second, InFlag);
4622 InFlag = Chain.getValue(1);
4626 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4627 FPOp, true, TailCallArguments);
4629 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4630 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4635 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4636 CallingConv::ID CallConv, bool isVarArg,
4638 const SmallVectorImpl<ISD::OutputArg> &Outs,
4639 const SmallVectorImpl<SDValue> &OutVals,
4640 const SmallVectorImpl<ISD::InputArg> &Ins,
4641 SDLoc dl, SelectionDAG &DAG,
4642 SmallVectorImpl<SDValue> &InVals) const {
4644 unsigned NumOps = Outs.size();
4646 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4647 bool isPPC64 = PtrVT == MVT::i64;
4648 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4650 MachineFunction &MF = DAG.getMachineFunction();
4652 // Mark this function as potentially containing a function that contains a
4653 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4654 // and restoring the callers stack pointer in this functions epilog. This is
4655 // done because by tail calling the called function might overwrite the value
4656 // in this function's (MF) stack pointer stack slot 0(SP).
4657 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4658 CallConv == CallingConv::Fast)
4659 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4661 // Count how many bytes are to be pushed on the stack, including the linkage
4662 // area, and parameter passing area. We start with 24/48 bytes, which is
4663 // prereserved space for [SP][CR][LR][3 x unused].
4664 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4666 unsigned NumBytes = LinkageSize;
4668 // Add up all the space actually used.
4669 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4670 // they all go in registers, but we must reserve stack space for them for
4671 // possible use by the caller. In varargs or 64-bit calls, parameters are
4672 // assigned stack space in order, with padding so Altivec parameters are
4674 unsigned nAltivecParamsAtEnd = 0;
4675 for (unsigned i = 0; i != NumOps; ++i) {
4676 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4677 EVT ArgVT = Outs[i].VT;
4678 // Varargs Altivec parameters are padded to a 16 byte boundary.
4679 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4680 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4681 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4682 if (!isVarArg && !isPPC64) {
4683 // Non-varargs Altivec parameters go after all the non-Altivec
4684 // parameters; handle those later so we know how much padding we need.
4685 nAltivecParamsAtEnd++;
4688 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4689 NumBytes = ((NumBytes+15)/16)*16;
4691 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4694 // Allow for Altivec parameters at the end, if needed.
4695 if (nAltivecParamsAtEnd) {
4696 NumBytes = ((NumBytes+15)/16)*16;
4697 NumBytes += 16*nAltivecParamsAtEnd;
4700 // The prolog code of the callee may store up to 8 GPR argument registers to
4701 // the stack, allowing va_start to index over them in memory if its varargs.
4702 // Because we cannot tell if this is needed on the caller side, we have to
4703 // conservatively assume that it is needed. As such, make sure we have at
4704 // least enough stack space for the caller to store the 8 GPRs.
4705 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4707 // Tail call needs the stack to be aligned.
4708 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4709 CallConv == CallingConv::Fast)
4710 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4712 // Calculate by how many bytes the stack has to be adjusted in case of tail
4713 // call optimization.
4714 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4716 // To protect arguments on the stack from being clobbered in a tail call,
4717 // force all the loads to happen before doing any other lowering.
4719 Chain = DAG.getStackArgumentTokenFactor(Chain);
4721 // Adjust the stack pointer for the new arguments...
4722 // These operations are automatically eliminated by the prolog/epilog pass
4723 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4725 SDValue CallSeqStart = Chain;
4727 // Load the return address and frame pointer so it can be move somewhere else
4730 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4733 // Set up a copy of the stack pointer for use loading and storing any
4734 // arguments that may not fit in the registers available for argument
4738 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4740 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4742 // Figure out which arguments are going to go in registers, and which in
4743 // memory. Also, if this is a vararg function, floating point operations
4744 // must be stored to our stack, and loaded into integer regs as well, if
4745 // any integer regs are available for argument passing.
4746 unsigned ArgOffset = LinkageSize;
4747 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4749 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4750 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4751 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4753 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4754 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4755 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4757 static const MCPhysReg *FPR = GetFPR();
4759 static const MCPhysReg VR[] = {
4760 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4761 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4763 const unsigned NumGPRs = array_lengthof(GPR_32);
4764 const unsigned NumFPRs = 13;
4765 const unsigned NumVRs = array_lengthof(VR);
4767 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4769 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4770 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4772 SmallVector<SDValue, 8> MemOpChains;
4773 for (unsigned i = 0; i != NumOps; ++i) {
4774 SDValue Arg = OutVals[i];
4775 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4777 // PtrOff will be used to store the current argument to the stack if a
4778 // register cannot be found for it.
4781 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4783 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4785 // On PPC64, promote integers to 64-bit values.
4786 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4787 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4788 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4789 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4792 // FIXME memcpy is used way more than necessary. Correctness first.
4793 // Note: "by value" is code for passing a structure by value, not
4795 if (Flags.isByVal()) {
4796 unsigned Size = Flags.getByValSize();
4797 // Very small objects are passed right-justified. Everything else is
4798 // passed left-justified.
4799 if (Size==1 || Size==2) {
4800 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4801 if (GPR_idx != NumGPRs) {
4802 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4803 MachinePointerInfo(), VT,
4805 MemOpChains.push_back(Load.getValue(1));
4806 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4808 ArgOffset += PtrByteSize;
4810 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4811 PtrOff.getValueType());
4812 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4813 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4816 ArgOffset += PtrByteSize;
4820 // Copy entire object into memory. There are cases where gcc-generated
4821 // code assumes it is there, even if it could be put entirely into
4822 // registers. (This is not what the doc says.)
4823 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4827 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4828 // copy the pieces of the object that fit into registers from the
4829 // parameter save area.
4830 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4831 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4832 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4833 if (GPR_idx != NumGPRs) {
4834 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4835 MachinePointerInfo(),
4836 false, false, false, 0);
4837 MemOpChains.push_back(Load.getValue(1));
4838 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4839 ArgOffset += PtrByteSize;
4841 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4848 switch (Arg.getSimpleValueType().SimpleTy) {
4849 default: llvm_unreachable("Unexpected ValueType for argument!");
4853 if (GPR_idx != NumGPRs) {
4854 if (Arg.getValueType() == MVT::i1)
4855 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4857 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4859 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4860 isPPC64, isTailCall, false, MemOpChains,
4861 TailCallArguments, dl);
4863 ArgOffset += PtrByteSize;
4867 if (FPR_idx != NumFPRs) {
4868 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4871 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4872 MachinePointerInfo(), false, false, 0);
4873 MemOpChains.push_back(Store);
4875 // Float varargs are always shadowed in available integer registers
4876 if (GPR_idx != NumGPRs) {
4877 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4878 MachinePointerInfo(), false, false,
4880 MemOpChains.push_back(Load.getValue(1));
4881 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4883 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4884 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4885 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4886 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4887 MachinePointerInfo(),
4888 false, false, false, 0);
4889 MemOpChains.push_back(Load.getValue(1));
4890 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4893 // If we have any FPRs remaining, we may also have GPRs remaining.
4894 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4896 if (GPR_idx != NumGPRs)
4898 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4899 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4903 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4904 isPPC64, isTailCall, false, MemOpChains,
4905 TailCallArguments, dl);
4909 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4916 // These go aligned on the stack, or in the corresponding R registers
4917 // when within range. The Darwin PPC ABI doc claims they also go in
4918 // V registers; in fact gcc does this only for arguments that are
4919 // prototyped, not for those that match the ... We do it for all
4920 // arguments, seems to work.
4921 while (ArgOffset % 16 !=0) {
4922 ArgOffset += PtrByteSize;
4923 if (GPR_idx != NumGPRs)
4926 // We could elide this store in the case where the object fits
4927 // entirely in R registers. Maybe later.
4928 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4929 DAG.getConstant(ArgOffset, PtrVT));
4930 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4931 MachinePointerInfo(), false, false, 0);
4932 MemOpChains.push_back(Store);
4933 if (VR_idx != NumVRs) {
4934 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4935 MachinePointerInfo(),
4936 false, false, false, 0);
4937 MemOpChains.push_back(Load.getValue(1));
4938 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4941 for (unsigned i=0; i<16; i+=PtrByteSize) {
4942 if (GPR_idx == NumGPRs)
4944 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4945 DAG.getConstant(i, PtrVT));
4946 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4947 false, false, false, 0);
4948 MemOpChains.push_back(Load.getValue(1));
4949 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4954 // Non-varargs Altivec params generally go in registers, but have
4955 // stack space allocated at the end.
4956 if (VR_idx != NumVRs) {
4957 // Doesn't have GPR space allocated.
4958 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4959 } else if (nAltivecParamsAtEnd==0) {
4960 // We are emitting Altivec params in order.
4961 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4962 isPPC64, isTailCall, true, MemOpChains,
4963 TailCallArguments, dl);
4969 // If all Altivec parameters fit in registers, as they usually do,
4970 // they get stack space following the non-Altivec parameters. We
4971 // don't track this here because nobody below needs it.
4972 // If there are more Altivec parameters than fit in registers emit
4974 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4976 // Offset is aligned; skip 1st 12 params which go in V registers.
4977 ArgOffset = ((ArgOffset+15)/16)*16;
4979 for (unsigned i = 0; i != NumOps; ++i) {
4980 SDValue Arg = OutVals[i];
4981 EVT ArgType = Outs[i].VT;
4982 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4983 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4986 // We are emitting Altivec params in order.
4987 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4988 isPPC64, isTailCall, true, MemOpChains,
4989 TailCallArguments, dl);
4996 if (!MemOpChains.empty())
4997 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4999 // On Darwin, R12 must contain the address of an indirect callee. This does
5000 // not mean the MTCTR instruction must use R12; it's easier to model this as
5001 // an extra parameter, so do that.
5003 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5004 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5005 !isBLACompatibleAddress(Callee, DAG))
5006 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5007 PPC::R12), Callee));
5009 // Build a sequence of copy-to-reg nodes chained together with token chain
5010 // and flag operands which copy the outgoing args into the appropriate regs.
5012 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5013 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5014 RegsToPass[i].second, InFlag);
5015 InFlag = Chain.getValue(1);
5019 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5020 FPOp, true, TailCallArguments);
5022 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5023 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5028 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5029 MachineFunction &MF, bool isVarArg,
5030 const SmallVectorImpl<ISD::OutputArg> &Outs,
5031 LLVMContext &Context) const {
5032 SmallVector<CCValAssign, 16> RVLocs;
5033 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
5035 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5039 PPCTargetLowering::LowerReturn(SDValue Chain,
5040 CallingConv::ID CallConv, bool isVarArg,
5041 const SmallVectorImpl<ISD::OutputArg> &Outs,
5042 const SmallVectorImpl<SDValue> &OutVals,
5043 SDLoc dl, SelectionDAG &DAG) const {
5045 SmallVector<CCValAssign, 16> RVLocs;
5046 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
5047 getTargetMachine(), RVLocs, *DAG.getContext());
5048 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5051 SmallVector<SDValue, 4> RetOps(1, Chain);
5053 // Copy the result values into the output registers.
5054 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5055 CCValAssign &VA = RVLocs[i];
5056 assert(VA.isRegLoc() && "Can only return in registers!");
5058 SDValue Arg = OutVals[i];
5060 switch (VA.getLocInfo()) {
5061 default: llvm_unreachable("Unknown loc info!");
5062 case CCValAssign::Full: break;
5063 case CCValAssign::AExt:
5064 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5066 case CCValAssign::ZExt:
5067 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5069 case CCValAssign::SExt:
5070 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5074 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5075 Flag = Chain.getValue(1);
5076 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5079 RetOps[0] = Chain; // Update chain.
5081 // Add the flag if we have it.
5083 RetOps.push_back(Flag);
5085 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5088 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5089 const PPCSubtarget &Subtarget) const {
5090 // When we pop the dynamic allocation we need to restore the SP link.
5093 // Get the corect type for pointers.
5094 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5096 // Construct the stack pointer operand.
5097 bool isPPC64 = Subtarget.isPPC64();
5098 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5099 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5101 // Get the operands for the STACKRESTORE.
5102 SDValue Chain = Op.getOperand(0);
5103 SDValue SaveSP = Op.getOperand(1);
5105 // Load the old link SP.
5106 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5107 MachinePointerInfo(),
5108 false, false, false, 0);
5110 // Restore the stack pointer.
5111 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5113 // Store the old link SP.
5114 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5121 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5122 MachineFunction &MF = DAG.getMachineFunction();
5123 bool isPPC64 = Subtarget.isPPC64();
5124 bool isDarwinABI = Subtarget.isDarwinABI();
5125 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5127 // Get current frame pointer save index. The users of this index will be
5128 // primarily DYNALLOC instructions.
5129 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5130 int RASI = FI->getReturnAddrSaveIndex();
5132 // If the frame pointer save index hasn't been defined yet.
5134 // Find out what the fix offset of the frame pointer save area.
5135 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5136 // Allocate the frame index for frame pointer save area.
5137 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5139 FI->setReturnAddrSaveIndex(RASI);
5141 return DAG.getFrameIndex(RASI, PtrVT);
5145 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5146 MachineFunction &MF = DAG.getMachineFunction();
5147 bool isPPC64 = Subtarget.isPPC64();
5148 bool isDarwinABI = Subtarget.isDarwinABI();
5149 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5151 // Get current frame pointer save index. The users of this index will be
5152 // primarily DYNALLOC instructions.
5153 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5154 int FPSI = FI->getFramePointerSaveIndex();
5156 // If the frame pointer save index hasn't been defined yet.
5158 // Find out what the fix offset of the frame pointer save area.
5159 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5162 // Allocate the frame index for frame pointer save area.
5163 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5165 FI->setFramePointerSaveIndex(FPSI);
5167 return DAG.getFrameIndex(FPSI, PtrVT);
5170 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5172 const PPCSubtarget &Subtarget) const {
5174 SDValue Chain = Op.getOperand(0);
5175 SDValue Size = Op.getOperand(1);
5178 // Get the corect type for pointers.
5179 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5181 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5182 DAG.getConstant(0, PtrVT), Size);
5183 // Construct a node for the frame pointer save index.
5184 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5185 // Build a DYNALLOC node.
5186 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5187 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5188 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5191 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5192 SelectionDAG &DAG) const {
5194 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5195 DAG.getVTList(MVT::i32, MVT::Other),
5196 Op.getOperand(0), Op.getOperand(1));
5199 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5200 SelectionDAG &DAG) const {
5202 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5203 Op.getOperand(0), Op.getOperand(1));
5206 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5207 assert(Op.getValueType() == MVT::i1 &&
5208 "Custom lowering only for i1 loads");
5210 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5213 LoadSDNode *LD = cast<LoadSDNode>(Op);
5215 SDValue Chain = LD->getChain();
5216 SDValue BasePtr = LD->getBasePtr();
5217 MachineMemOperand *MMO = LD->getMemOperand();
5219 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5220 BasePtr, MVT::i8, MMO);
5221 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5223 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5224 return DAG.getMergeValues(Ops, dl);
5227 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5228 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5229 "Custom lowering only for i1 stores");
5231 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5234 StoreSDNode *ST = cast<StoreSDNode>(Op);
5236 SDValue Chain = ST->getChain();
5237 SDValue BasePtr = ST->getBasePtr();
5238 SDValue Value = ST->getValue();
5239 MachineMemOperand *MMO = ST->getMemOperand();
5241 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5242 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5245 // FIXME: Remove this once the ANDI glue bug is fixed:
5246 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5247 assert(Op.getValueType() == MVT::i1 &&
5248 "Custom lowering only for i1 results");
5251 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5255 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5257 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5258 // Not FP? Not a fsel.
5259 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5260 !Op.getOperand(2).getValueType().isFloatingPoint())
5263 // We might be able to do better than this under some circumstances, but in
5264 // general, fsel-based lowering of select is a finite-math-only optimization.
5265 // For more information, see section F.3 of the 2.06 ISA specification.
5266 if (!DAG.getTarget().Options.NoInfsFPMath ||
5267 !DAG.getTarget().Options.NoNaNsFPMath)
5270 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5272 EVT ResVT = Op.getValueType();
5273 EVT CmpVT = Op.getOperand(0).getValueType();
5274 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5275 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5278 // If the RHS of the comparison is a 0.0, we don't need to do the
5279 // subtraction at all.
5281 if (isFloatingPointZero(RHS))
5283 default: break; // SETUO etc aren't handled by fsel.
5287 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5288 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5289 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5290 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5291 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5292 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5293 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5296 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5299 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5300 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5301 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5304 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5307 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5308 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5309 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5310 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5315 default: break; // SETUO etc aren't handled by fsel.
5319 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5320 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5321 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5322 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5323 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5324 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5325 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5326 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5329 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5330 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5331 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5332 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5335 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5336 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5337 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5338 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5341 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5342 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5343 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5344 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5347 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5348 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5349 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5350 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5355 // FIXME: Split this code up when LegalizeDAGTypes lands.
5356 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5358 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5359 SDValue Src = Op.getOperand(0);
5360 if (Src.getValueType() == MVT::f32)
5361 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5364 switch (Op.getSimpleValueType().SimpleTy) {
5365 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5367 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5368 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5373 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5374 "i64 FP_TO_UINT is supported only with FPCVT");
5375 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5381 // Convert the FP value to an int value through memory.
5382 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5383 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5384 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5385 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5386 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5388 // Emit a store to the stack slot.
5391 MachineFunction &MF = DAG.getMachineFunction();
5392 MachineMemOperand *MMO =
5393 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5394 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5395 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5396 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5398 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5399 MPI, false, false, 0);
5401 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5403 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5404 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5405 DAG.getConstant(4, FIPtr.getValueType()));
5406 MPI = MachinePointerInfo();
5409 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5410 false, false, false, 0);
5413 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5414 SelectionDAG &DAG) const {
5416 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5417 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5420 if (Op.getOperand(0).getValueType() == MVT::i1)
5421 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5422 DAG.getConstantFP(1.0, Op.getValueType()),
5423 DAG.getConstantFP(0.0, Op.getValueType()));
5425 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5426 "UINT_TO_FP is supported only with FPCVT");
5428 // If we have FCFIDS, then use it when converting to single-precision.
5429 // Otherwise, convert to double-precision and then round.
5430 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5431 (Op.getOpcode() == ISD::UINT_TO_FP ?
5432 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5433 (Op.getOpcode() == ISD::UINT_TO_FP ?
5434 PPCISD::FCFIDU : PPCISD::FCFID);
5435 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5436 MVT::f32 : MVT::f64;
5438 if (Op.getOperand(0).getValueType() == MVT::i64) {
5439 SDValue SINT = Op.getOperand(0);
5440 // When converting to single-precision, we actually need to convert
5441 // to double-precision first and then round to single-precision.
5442 // To avoid double-rounding effects during that operation, we have
5443 // to prepare the input operand. Bits that might be truncated when
5444 // converting to double-precision are replaced by a bit that won't
5445 // be lost at this stage, but is below the single-precision rounding
5448 // However, if -enable-unsafe-fp-math is in effect, accept double
5449 // rounding to avoid the extra overhead.
5450 if (Op.getValueType() == MVT::f32 &&
5451 !Subtarget.hasFPCVT() &&
5452 !DAG.getTarget().Options.UnsafeFPMath) {
5454 // Twiddle input to make sure the low 11 bits are zero. (If this
5455 // is the case, we are guaranteed the value will fit into the 53 bit
5456 // mantissa of an IEEE double-precision value without rounding.)
5457 // If any of those low 11 bits were not zero originally, make sure
5458 // bit 12 (value 2048) is set instead, so that the final rounding
5459 // to single-precision gets the correct result.
5460 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5461 SINT, DAG.getConstant(2047, MVT::i64));
5462 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5463 Round, DAG.getConstant(2047, MVT::i64));
5464 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5465 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5466 Round, DAG.getConstant(-2048, MVT::i64));
5468 // However, we cannot use that value unconditionally: if the magnitude
5469 // of the input value is small, the bit-twiddling we did above might
5470 // end up visibly changing the output. Fortunately, in that case, we
5471 // don't need to twiddle bits since the original input will convert
5472 // exactly to double-precision floating-point already. Therefore,
5473 // construct a conditional to use the original value if the top 11
5474 // bits are all sign-bit copies, and use the rounded value computed
5476 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5477 SINT, DAG.getConstant(53, MVT::i32));
5478 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5479 Cond, DAG.getConstant(1, MVT::i64));
5480 Cond = DAG.getSetCC(dl, MVT::i32,
5481 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5483 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5486 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5487 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5489 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5490 FP = DAG.getNode(ISD::FP_ROUND, dl,
5491 MVT::f32, FP, DAG.getIntPtrConstant(0));
5495 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5496 "Unhandled INT_TO_FP type in custom expander!");
5497 // Since we only generate this in 64-bit mode, we can take advantage of
5498 // 64-bit registers. In particular, sign extend the input value into the
5499 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5500 // then lfd it and fcfid it.
5501 MachineFunction &MF = DAG.getMachineFunction();
5502 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5503 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5506 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5507 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5508 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5510 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5511 MachinePointerInfo::getFixedStack(FrameIdx),
5514 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5515 "Expected an i32 store");
5516 MachineMemOperand *MMO =
5517 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5518 MachineMemOperand::MOLoad, 4, 4);
5519 SDValue Ops[] = { Store, FIdx };
5520 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5521 PPCISD::LFIWZX : PPCISD::LFIWAX,
5522 dl, DAG.getVTList(MVT::f64, MVT::Other),
5523 Ops, MVT::i32, MMO);
5525 assert(Subtarget.isPPC64() &&
5526 "i32->FP without LFIWAX supported only on PPC64");
5528 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5529 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5531 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5534 // STD the extended value into the stack slot.
5535 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5536 MachinePointerInfo::getFixedStack(FrameIdx),
5539 // Load the value as a double.
5540 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5541 MachinePointerInfo::getFixedStack(FrameIdx),
5542 false, false, false, 0);
5545 // FCFID it and return it.
5546 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5547 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5548 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5552 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5553 SelectionDAG &DAG) const {
5556 The rounding mode is in bits 30:31 of FPSR, and has the following
5563 FLT_ROUNDS, on the other hand, expects the following:
5570 To perform the conversion, we do:
5571 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5574 MachineFunction &MF = DAG.getMachineFunction();
5575 EVT VT = Op.getValueType();
5576 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5578 // Save FP Control Word to register
5580 MVT::f64, // return register
5581 MVT::Glue // unused in this context
5583 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5585 // Save FP register to stack slot
5586 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5587 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5588 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5589 StackSlot, MachinePointerInfo(), false, false,0);
5591 // Load FP Control Word from low 32 bits of stack slot.
5592 SDValue Four = DAG.getConstant(4, PtrVT);
5593 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5594 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5595 false, false, false, 0);
5597 // Transform as necessary
5599 DAG.getNode(ISD::AND, dl, MVT::i32,
5600 CWD, DAG.getConstant(3, MVT::i32));
5602 DAG.getNode(ISD::SRL, dl, MVT::i32,
5603 DAG.getNode(ISD::AND, dl, MVT::i32,
5604 DAG.getNode(ISD::XOR, dl, MVT::i32,
5605 CWD, DAG.getConstant(3, MVT::i32)),
5606 DAG.getConstant(3, MVT::i32)),
5607 DAG.getConstant(1, MVT::i32));
5610 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5612 return DAG.getNode((VT.getSizeInBits() < 16 ?
5613 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5616 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5617 EVT VT = Op.getValueType();
5618 unsigned BitWidth = VT.getSizeInBits();
5620 assert(Op.getNumOperands() == 3 &&
5621 VT == Op.getOperand(1).getValueType() &&
5624 // Expand into a bunch of logical ops. Note that these ops
5625 // depend on the PPC behavior for oversized shift amounts.
5626 SDValue Lo = Op.getOperand(0);
5627 SDValue Hi = Op.getOperand(1);
5628 SDValue Amt = Op.getOperand(2);
5629 EVT AmtVT = Amt.getValueType();
5631 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5632 DAG.getConstant(BitWidth, AmtVT), Amt);
5633 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5634 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5635 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5636 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5637 DAG.getConstant(-BitWidth, AmtVT));
5638 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5639 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5640 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5641 SDValue OutOps[] = { OutLo, OutHi };
5642 return DAG.getMergeValues(OutOps, dl);
5645 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5646 EVT VT = Op.getValueType();
5648 unsigned BitWidth = VT.getSizeInBits();
5649 assert(Op.getNumOperands() == 3 &&
5650 VT == Op.getOperand(1).getValueType() &&
5653 // Expand into a bunch of logical ops. Note that these ops
5654 // depend on the PPC behavior for oversized shift amounts.
5655 SDValue Lo = Op.getOperand(0);
5656 SDValue Hi = Op.getOperand(1);
5657 SDValue Amt = Op.getOperand(2);
5658 EVT AmtVT = Amt.getValueType();
5660 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5661 DAG.getConstant(BitWidth, AmtVT), Amt);
5662 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5663 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5664 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5665 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5666 DAG.getConstant(-BitWidth, AmtVT));
5667 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5668 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5669 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5670 SDValue OutOps[] = { OutLo, OutHi };
5671 return DAG.getMergeValues(OutOps, dl);
5674 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5676 EVT VT = Op.getValueType();
5677 unsigned BitWidth = VT.getSizeInBits();
5678 assert(Op.getNumOperands() == 3 &&
5679 VT == Op.getOperand(1).getValueType() &&
5682 // Expand into a bunch of logical ops, followed by a select_cc.
5683 SDValue Lo = Op.getOperand(0);
5684 SDValue Hi = Op.getOperand(1);
5685 SDValue Amt = Op.getOperand(2);
5686 EVT AmtVT = Amt.getValueType();
5688 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5689 DAG.getConstant(BitWidth, AmtVT), Amt);
5690 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5691 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5692 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5693 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5694 DAG.getConstant(-BitWidth, AmtVT));
5695 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5696 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5697 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5698 Tmp4, Tmp6, ISD::SETLE);
5699 SDValue OutOps[] = { OutLo, OutHi };
5700 return DAG.getMergeValues(OutOps, dl);
5703 //===----------------------------------------------------------------------===//
5704 // Vector related lowering.
5707 /// BuildSplatI - Build a canonical splati of Val with an element size of
5708 /// SplatSize. Cast the result to VT.
5709 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5710 SelectionDAG &DAG, SDLoc dl) {
5711 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5713 static const EVT VTys[] = { // canonical VT to use for each size.
5714 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5717 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5719 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5723 EVT CanonicalVT = VTys[SplatSize-1];
5725 // Build a canonical splat for this value.
5726 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5727 SmallVector<SDValue, 8> Ops;
5728 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5729 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5730 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5733 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5734 /// specified intrinsic ID.
5735 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5736 SelectionDAG &DAG, SDLoc dl,
5737 EVT DestVT = MVT::Other) {
5738 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5739 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5740 DAG.getConstant(IID, MVT::i32), Op);
5743 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5744 /// specified intrinsic ID.
5745 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5746 SelectionDAG &DAG, SDLoc dl,
5747 EVT DestVT = MVT::Other) {
5748 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5749 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5750 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5753 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5754 /// specified intrinsic ID.
5755 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5756 SDValue Op2, SelectionDAG &DAG,
5757 SDLoc dl, EVT DestVT = MVT::Other) {
5758 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5759 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5760 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5764 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5765 /// amount. The result has the specified value type.
5766 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5767 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5768 // Force LHS/RHS to be the right type.
5769 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5770 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5773 for (unsigned i = 0; i != 16; ++i)
5775 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5776 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5779 // If this is a case we can't handle, return null and let the default
5780 // expansion code take care of it. If we CAN select this case, and if it
5781 // selects to a single instruction, return Op. Otherwise, if we can codegen
5782 // this case more efficiently than a constant pool load, lower it to the
5783 // sequence of ops that should be used.
5784 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5785 SelectionDAG &DAG) const {
5787 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5788 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5790 // Check if this is a splat of a constant value.
5791 APInt APSplatBits, APSplatUndef;
5792 unsigned SplatBitSize;
5794 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5795 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5798 unsigned SplatBits = APSplatBits.getZExtValue();
5799 unsigned SplatUndef = APSplatUndef.getZExtValue();
5800 unsigned SplatSize = SplatBitSize / 8;
5802 // First, handle single instruction cases.
5805 if (SplatBits == 0) {
5806 // Canonicalize all zero vectors to be v4i32.
5807 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5808 SDValue Z = DAG.getConstant(0, MVT::i32);
5809 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5810 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5815 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5816 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5818 if (SextVal >= -16 && SextVal <= 15)
5819 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5822 // Two instruction sequences.
5824 // If this value is in the range [-32,30] and is even, use:
5825 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5826 // If this value is in the range [17,31] and is odd, use:
5827 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5828 // If this value is in the range [-31,-17] and is odd, use:
5829 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5830 // Note the last two are three-instruction sequences.
5831 if (SextVal >= -32 && SextVal <= 31) {
5832 // To avoid having these optimizations undone by constant folding,
5833 // we convert to a pseudo that will be expanded later into one of
5835 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5836 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5837 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5838 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5839 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5840 if (VT == Op.getValueType())
5843 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5846 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5847 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5849 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5850 // Make -1 and vspltisw -1:
5851 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5853 // Make the VSLW intrinsic, computing 0x8000_0000.
5854 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5857 // xor by OnesV to invert it.
5858 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5859 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5862 // The remaining cases assume either big endian element order or
5863 // a splat-size that equates to the element size of the vector
5864 // to be built. An example that doesn't work for little endian is
5865 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5866 // and a vector element size of 16 bits. The code below will
5867 // produce the vector in big endian element order, which for little
5868 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5870 // For now, just avoid these optimizations in that case.
5871 // FIXME: Develop correct optimizations for LE with mismatched
5872 // splat and element sizes.
5874 if (Subtarget.isLittleEndian() &&
5875 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5878 // Check to see if this is a wide variety of vsplti*, binop self cases.
5879 static const signed char SplatCsts[] = {
5880 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5881 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5884 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5885 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5886 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5887 int i = SplatCsts[idx];
5889 // Figure out what shift amount will be used by altivec if shifted by i in
5891 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5893 // vsplti + shl self.
5894 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5895 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5896 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5897 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5898 Intrinsic::ppc_altivec_vslw
5900 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5901 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5904 // vsplti + srl self.
5905 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5906 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5907 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5908 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5909 Intrinsic::ppc_altivec_vsrw
5911 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5912 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5915 // vsplti + sra self.
5916 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5917 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5918 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5919 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5920 Intrinsic::ppc_altivec_vsraw
5922 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5923 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5926 // vsplti + rol self.
5927 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5928 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5929 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5930 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5931 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5932 Intrinsic::ppc_altivec_vrlw
5934 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5935 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5938 // t = vsplti c, result = vsldoi t, t, 1
5939 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5940 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5941 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5943 // t = vsplti c, result = vsldoi t, t, 2
5944 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5945 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5946 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5948 // t = vsplti c, result = vsldoi t, t, 3
5949 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5950 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5951 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5958 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5959 /// the specified operations to build the shuffle.
5960 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5961 SDValue RHS, SelectionDAG &DAG,
5963 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5964 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5965 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5968 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5980 if (OpNum == OP_COPY) {
5981 if (LHSID == (1*9+2)*9+3) return LHS;
5982 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5986 SDValue OpLHS, OpRHS;
5987 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5988 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5992 default: llvm_unreachable("Unknown i32 permute!");
5994 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5995 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5996 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5997 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6000 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6001 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6002 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6003 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6006 for (unsigned i = 0; i != 16; ++i)
6007 ShufIdxs[i] = (i&3)+0;
6010 for (unsigned i = 0; i != 16; ++i)
6011 ShufIdxs[i] = (i&3)+4;
6014 for (unsigned i = 0; i != 16; ++i)
6015 ShufIdxs[i] = (i&3)+8;
6018 for (unsigned i = 0; i != 16; ++i)
6019 ShufIdxs[i] = (i&3)+12;
6022 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6024 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6026 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6028 EVT VT = OpLHS.getValueType();
6029 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6030 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6031 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6032 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6035 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6036 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6037 /// return the code it can be lowered into. Worst case, it can always be
6038 /// lowered into a vperm.
6039 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6040 SelectionDAG &DAG) const {
6042 SDValue V1 = Op.getOperand(0);
6043 SDValue V2 = Op.getOperand(1);
6044 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6045 EVT VT = Op.getValueType();
6046 bool isLittleEndian = Subtarget.isLittleEndian();
6048 // Cases that are handled by instructions that take permute immediates
6049 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6050 // selected by the instruction selector.
6051 if (V2.getOpcode() == ISD::UNDEF) {
6052 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6053 PPC::isSplatShuffleMask(SVOp, 2) ||
6054 PPC::isSplatShuffleMask(SVOp, 4) ||
6055 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
6056 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
6057 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
6058 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6059 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6060 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6061 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6062 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6063 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6068 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6069 // and produce a fixed permutation. If any of these match, do not lower to
6071 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6072 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
6073 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
6074 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
6075 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6076 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6077 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6078 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6079 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6080 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6083 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6084 // perfect shuffle table to emit an optimal matching sequence.
6085 ArrayRef<int> PermMask = SVOp->getMask();
6087 unsigned PFIndexes[4];
6088 bool isFourElementShuffle = true;
6089 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6090 unsigned EltNo = 8; // Start out undef.
6091 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6092 if (PermMask[i*4+j] < 0)
6093 continue; // Undef, ignore it.
6095 unsigned ByteSource = PermMask[i*4+j];
6096 if ((ByteSource & 3) != j) {
6097 isFourElementShuffle = false;
6102 EltNo = ByteSource/4;
6103 } else if (EltNo != ByteSource/4) {
6104 isFourElementShuffle = false;
6108 PFIndexes[i] = EltNo;
6111 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6112 // perfect shuffle vector to determine if it is cost effective to do this as
6113 // discrete instructions, or whether we should use a vperm.
6114 // For now, we skip this for little endian until such time as we have a
6115 // little-endian perfect shuffle table.
6116 if (isFourElementShuffle && !isLittleEndian) {
6117 // Compute the index in the perfect shuffle table.
6118 unsigned PFTableIndex =
6119 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6121 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6122 unsigned Cost = (PFEntry >> 30);
6124 // Determining when to avoid vperm is tricky. Many things affect the cost
6125 // of vperm, particularly how many times the perm mask needs to be computed.
6126 // For example, if the perm mask can be hoisted out of a loop or is already
6127 // used (perhaps because there are multiple permutes with the same shuffle
6128 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6129 // the loop requires an extra register.
6131 // As a compromise, we only emit discrete instructions if the shuffle can be
6132 // generated in 3 or fewer operations. When we have loop information
6133 // available, if this block is within a loop, we should avoid using vperm
6134 // for 3-operation perms and use a constant pool load instead.
6136 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6139 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6140 // vector that will get spilled to the constant pool.
6141 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6143 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6144 // that it is in input element units, not in bytes. Convert now.
6146 // For little endian, the order of the input vectors is reversed, and
6147 // the permutation mask is complemented with respect to 31. This is
6148 // necessary to produce proper semantics with the big-endian-biased vperm
6150 EVT EltVT = V1.getValueType().getVectorElementType();
6151 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6153 SmallVector<SDValue, 16> ResultMask;
6154 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6155 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6157 for (unsigned j = 0; j != BytesPerElement; ++j)
6159 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6162 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6166 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6169 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6172 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6176 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6177 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6178 /// information about the intrinsic.
6179 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6181 unsigned IntrinsicID =
6182 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6185 switch (IntrinsicID) {
6186 default: return false;
6187 // Comparison predicates.
6188 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6189 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6190 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6191 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6192 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6193 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6194 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6195 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6196 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6197 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6198 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6199 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6200 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6202 // Normal Comparisons.
6203 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6204 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6205 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6206 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6207 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6208 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6209 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6210 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6211 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6212 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6213 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6214 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6215 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6220 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6221 /// lower, do it, otherwise return null.
6222 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6223 SelectionDAG &DAG) const {
6224 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6225 // opcode number of the comparison.
6229 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6230 return SDValue(); // Don't custom lower most intrinsics.
6232 // If this is a non-dot comparison, make the VCMP node and we are done.
6234 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6235 Op.getOperand(1), Op.getOperand(2),
6236 DAG.getConstant(CompareOpc, MVT::i32));
6237 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6240 // Create the PPCISD altivec 'dot' comparison node.
6242 Op.getOperand(2), // LHS
6243 Op.getOperand(3), // RHS
6244 DAG.getConstant(CompareOpc, MVT::i32)
6246 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6247 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6249 // Now that we have the comparison, emit a copy from the CR to a GPR.
6250 // This is flagged to the above dot comparison.
6251 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6252 DAG.getRegister(PPC::CR6, MVT::i32),
6253 CompNode.getValue(1));
6255 // Unpack the result based on how the target uses it.
6256 unsigned BitNo; // Bit # of CR6.
6257 bool InvertBit; // Invert result?
6258 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6259 default: // Can't happen, don't crash on invalid number though.
6260 case 0: // Return the value of the EQ bit of CR6.
6261 BitNo = 0; InvertBit = false;
6263 case 1: // Return the inverted value of the EQ bit of CR6.
6264 BitNo = 0; InvertBit = true;
6266 case 2: // Return the value of the LT bit of CR6.
6267 BitNo = 2; InvertBit = false;
6269 case 3: // Return the inverted value of the LT bit of CR6.
6270 BitNo = 2; InvertBit = true;
6274 // Shift the bit into the low position.
6275 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6276 DAG.getConstant(8-(3-BitNo), MVT::i32));
6278 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6279 DAG.getConstant(1, MVT::i32));
6281 // If we are supposed to, toggle the bit.
6283 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6284 DAG.getConstant(1, MVT::i32));
6288 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6289 SelectionDAG &DAG) const {
6291 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6292 // instructions), but for smaller types, we need to first extend up to v2i32
6293 // before doing going farther.
6294 if (Op.getValueType() == MVT::v2i64) {
6295 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6296 if (ExtVT != MVT::v2i32) {
6297 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6298 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6299 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6300 ExtVT.getVectorElementType(), 4)));
6301 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6302 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6303 DAG.getValueType(MVT::v2i32));
6312 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6313 SelectionDAG &DAG) const {
6315 // Create a stack slot that is 16-byte aligned.
6316 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6317 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6318 EVT PtrVT = getPointerTy();
6319 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6321 // Store the input value into Value#0 of the stack slot.
6322 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6323 Op.getOperand(0), FIdx, MachinePointerInfo(),
6326 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6327 false, false, false, 0);
6330 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6332 if (Op.getValueType() == MVT::v4i32) {
6333 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6335 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6336 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6338 SDValue RHSSwap = // = vrlw RHS, 16
6339 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6341 // Shrinkify inputs to v8i16.
6342 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6343 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6344 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6346 // Low parts multiplied together, generating 32-bit results (we ignore the
6348 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6349 LHS, RHS, DAG, dl, MVT::v4i32);
6351 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6352 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6353 // Shift the high parts up 16 bits.
6354 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6356 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6357 } else if (Op.getValueType() == MVT::v8i16) {
6358 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6360 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6362 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6363 LHS, RHS, Zero, DAG, dl);
6364 } else if (Op.getValueType() == MVT::v16i8) {
6365 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6366 bool isLittleEndian = Subtarget.isLittleEndian();
6368 // Multiply the even 8-bit parts, producing 16-bit sums.
6369 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6370 LHS, RHS, DAG, dl, MVT::v8i16);
6371 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6373 // Multiply the odd 8-bit parts, producing 16-bit sums.
6374 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6375 LHS, RHS, DAG, dl, MVT::v8i16);
6376 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6378 // Merge the results together. Because vmuleub and vmuloub are
6379 // instructions with a big-endian bias, we must reverse the
6380 // element numbering and reverse the meaning of "odd" and "even"
6381 // when generating little endian code.
6383 for (unsigned i = 0; i != 8; ++i) {
6384 if (isLittleEndian) {
6386 Ops[i*2+1] = 2*i+16;
6389 Ops[i*2+1] = 2*i+1+16;
6393 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6395 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6397 llvm_unreachable("Unknown mul to lower!");
6401 /// LowerOperation - Provide custom lowering hooks for some operations.
6403 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6404 switch (Op.getOpcode()) {
6405 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6406 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6407 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6408 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6409 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6410 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6411 case ISD::SETCC: return LowerSETCC(Op, DAG);
6412 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6413 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6415 return LowerVASTART(Op, DAG, Subtarget);
6418 return LowerVAARG(Op, DAG, Subtarget);
6421 return LowerVACOPY(Op, DAG, Subtarget);
6423 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6424 case ISD::DYNAMIC_STACKALLOC:
6425 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6427 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6428 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6430 case ISD::LOAD: return LowerLOAD(Op, DAG);
6431 case ISD::STORE: return LowerSTORE(Op, DAG);
6432 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6433 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6434 case ISD::FP_TO_UINT:
6435 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6437 case ISD::UINT_TO_FP:
6438 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6439 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6441 // Lower 64-bit shifts.
6442 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6443 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6444 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6446 // Vector-related lowering.
6447 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6448 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6449 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6450 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6451 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6452 case ISD::MUL: return LowerMUL(Op, DAG);
6454 // For counter-based loop handling.
6455 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6457 // Frame & Return address.
6458 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6459 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6463 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6464 SmallVectorImpl<SDValue>&Results,
6465 SelectionDAG &DAG) const {
6466 const TargetMachine &TM = getTargetMachine();
6468 switch (N->getOpcode()) {
6470 llvm_unreachable("Do not know how to custom type legalize this operation!");
6471 case ISD::INTRINSIC_W_CHAIN: {
6472 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6473 Intrinsic::ppc_is_decremented_ctr_nonzero)
6476 assert(N->getValueType(0) == MVT::i1 &&
6477 "Unexpected result type for CTR decrement intrinsic");
6478 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6479 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6480 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6483 Results.push_back(NewInt);
6484 Results.push_back(NewInt.getValue(1));
6488 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6489 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6492 EVT VT = N->getValueType(0);
6494 if (VT == MVT::i64) {
6495 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6497 Results.push_back(NewNode);
6498 Results.push_back(NewNode.getValue(1));
6502 case ISD::FP_ROUND_INREG: {
6503 assert(N->getValueType(0) == MVT::ppcf128);
6504 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6505 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6506 MVT::f64, N->getOperand(0),
6507 DAG.getIntPtrConstant(0));
6508 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6509 MVT::f64, N->getOperand(0),
6510 DAG.getIntPtrConstant(1));
6512 // Add the two halves of the long double in round-to-zero mode.
6513 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6515 // We know the low half is about to be thrown away, so just use something
6517 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6521 case ISD::FP_TO_SINT:
6522 // LowerFP_TO_INT() can only handle f32 and f64.
6523 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6525 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6531 //===----------------------------------------------------------------------===//
6532 // Other Lowering Code
6533 //===----------------------------------------------------------------------===//
6536 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6537 bool is64bit, unsigned BinOpcode) const {
6538 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6539 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6541 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6542 MachineFunction *F = BB->getParent();
6543 MachineFunction::iterator It = BB;
6546 unsigned dest = MI->getOperand(0).getReg();
6547 unsigned ptrA = MI->getOperand(1).getReg();
6548 unsigned ptrB = MI->getOperand(2).getReg();
6549 unsigned incr = MI->getOperand(3).getReg();
6550 DebugLoc dl = MI->getDebugLoc();
6552 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6553 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6554 F->insert(It, loopMBB);
6555 F->insert(It, exitMBB);
6556 exitMBB->splice(exitMBB->begin(), BB,
6557 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6558 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6560 MachineRegisterInfo &RegInfo = F->getRegInfo();
6561 unsigned TmpReg = (!BinOpcode) ? incr :
6562 RegInfo.createVirtualRegister(
6563 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6564 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6568 // fallthrough --> loopMBB
6569 BB->addSuccessor(loopMBB);
6572 // l[wd]arx dest, ptr
6573 // add r0, dest, incr
6574 // st[wd]cx. r0, ptr
6576 // fallthrough --> exitMBB
6578 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6579 .addReg(ptrA).addReg(ptrB);
6581 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6582 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6583 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6584 BuildMI(BB, dl, TII->get(PPC::BCC))
6585 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6586 BB->addSuccessor(loopMBB);
6587 BB->addSuccessor(exitMBB);
6596 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6597 MachineBasicBlock *BB,
6598 bool is8bit, // operation
6599 unsigned BinOpcode) const {
6600 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6601 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6602 // In 64 bit mode we have to use 64 bits for addresses, even though the
6603 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6604 // registers without caring whether they're 32 or 64, but here we're
6605 // doing actual arithmetic on the addresses.
6606 bool is64bit = Subtarget.isPPC64();
6607 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6609 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6610 MachineFunction *F = BB->getParent();
6611 MachineFunction::iterator It = BB;
6614 unsigned dest = MI->getOperand(0).getReg();
6615 unsigned ptrA = MI->getOperand(1).getReg();
6616 unsigned ptrB = MI->getOperand(2).getReg();
6617 unsigned incr = MI->getOperand(3).getReg();
6618 DebugLoc dl = MI->getDebugLoc();
6620 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6621 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6622 F->insert(It, loopMBB);
6623 F->insert(It, exitMBB);
6624 exitMBB->splice(exitMBB->begin(), BB,
6625 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6626 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6628 MachineRegisterInfo &RegInfo = F->getRegInfo();
6629 const TargetRegisterClass *RC =
6630 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6631 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6632 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6633 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6634 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6635 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6636 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6637 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6638 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6639 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6640 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6641 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6642 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6644 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6648 // fallthrough --> loopMBB
6649 BB->addSuccessor(loopMBB);
6651 // The 4-byte load must be aligned, while a char or short may be
6652 // anywhere in the word. Hence all this nasty bookkeeping code.
6653 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6654 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6655 // xori shift, shift1, 24 [16]
6656 // rlwinm ptr, ptr1, 0, 0, 29
6657 // slw incr2, incr, shift
6658 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6659 // slw mask, mask2, shift
6661 // lwarx tmpDest, ptr
6662 // add tmp, tmpDest, incr2
6663 // andc tmp2, tmpDest, mask
6664 // and tmp3, tmp, mask
6665 // or tmp4, tmp3, tmp2
6668 // fallthrough --> exitMBB
6669 // srw dest, tmpDest, shift
6670 if (ptrA != ZeroReg) {
6671 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6672 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6673 .addReg(ptrA).addReg(ptrB);
6677 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6678 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6679 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6680 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6682 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6683 .addReg(Ptr1Reg).addImm(0).addImm(61);
6685 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6686 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6687 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6688 .addReg(incr).addReg(ShiftReg);
6690 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6692 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6693 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6695 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6696 .addReg(Mask2Reg).addReg(ShiftReg);
6699 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6700 .addReg(ZeroReg).addReg(PtrReg);
6702 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6703 .addReg(Incr2Reg).addReg(TmpDestReg);
6704 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6705 .addReg(TmpDestReg).addReg(MaskReg);
6706 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6707 .addReg(TmpReg).addReg(MaskReg);
6708 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6709 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6710 BuildMI(BB, dl, TII->get(PPC::STWCX))
6711 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6712 BuildMI(BB, dl, TII->get(PPC::BCC))
6713 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6714 BB->addSuccessor(loopMBB);
6715 BB->addSuccessor(exitMBB);
6720 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6725 llvm::MachineBasicBlock*
6726 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6727 MachineBasicBlock *MBB) const {
6728 DebugLoc DL = MI->getDebugLoc();
6729 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6731 MachineFunction *MF = MBB->getParent();
6732 MachineRegisterInfo &MRI = MF->getRegInfo();
6734 const BasicBlock *BB = MBB->getBasicBlock();
6735 MachineFunction::iterator I = MBB;
6739 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6740 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6742 unsigned DstReg = MI->getOperand(0).getReg();
6743 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6744 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6745 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6746 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6748 MVT PVT = getPointerTy();
6749 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6750 "Invalid Pointer Size!");
6751 // For v = setjmp(buf), we generate
6754 // SjLjSetup mainMBB
6760 // buf[LabelOffset] = LR
6764 // v = phi(main, restore)
6767 MachineBasicBlock *thisMBB = MBB;
6768 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6769 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6770 MF->insert(I, mainMBB);
6771 MF->insert(I, sinkMBB);
6773 MachineInstrBuilder MIB;
6775 // Transfer the remainder of BB and its successor edges to sinkMBB.
6776 sinkMBB->splice(sinkMBB->begin(), MBB,
6777 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6778 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6780 // Note that the structure of the jmp_buf used here is not compatible
6781 // with that used by libc, and is not designed to be. Specifically, it
6782 // stores only those 'reserved' registers that LLVM does not otherwise
6783 // understand how to spill. Also, by convention, by the time this
6784 // intrinsic is called, Clang has already stored the frame address in the
6785 // first slot of the buffer and stack address in the third. Following the
6786 // X86 target code, we'll store the jump address in the second slot. We also
6787 // need to save the TOC pointer (R2) to handle jumps between shared
6788 // libraries, and that will be stored in the fourth slot. The thread
6789 // identifier (R13) is not affected.
6792 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6793 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6794 const int64_t BPOffset = 4 * PVT.getStoreSize();
6796 // Prepare IP either in reg.
6797 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6798 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6799 unsigned BufReg = MI->getOperand(1).getReg();
6801 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6802 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6806 MIB.setMemRefs(MMOBegin, MMOEnd);
6809 // Naked functions never have a base pointer, and so we use r1. For all
6810 // other functions, this decision must be delayed until during PEI.
6812 if (MF->getFunction()->getAttributes().hasAttribute(
6813 AttributeSet::FunctionIndex, Attribute::Naked))
6814 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6816 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6818 MIB = BuildMI(*thisMBB, MI, DL,
6819 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6823 MIB.setMemRefs(MMOBegin, MMOEnd);
6826 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6827 const PPCRegisterInfo *TRI =
6828 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6829 MIB.addRegMask(TRI->getNoPreservedMask());
6831 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6833 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6835 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6837 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6838 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6842 MIB = BuildMI(mainMBB, DL,
6843 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6846 if (Subtarget.isPPC64()) {
6847 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6849 .addImm(LabelOffset)
6852 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6854 .addImm(LabelOffset)
6858 MIB.setMemRefs(MMOBegin, MMOEnd);
6860 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6861 mainMBB->addSuccessor(sinkMBB);
6864 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6865 TII->get(PPC::PHI), DstReg)
6866 .addReg(mainDstReg).addMBB(mainMBB)
6867 .addReg(restoreDstReg).addMBB(thisMBB);
6869 MI->eraseFromParent();
6874 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6875 MachineBasicBlock *MBB) const {
6876 DebugLoc DL = MI->getDebugLoc();
6877 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6879 MachineFunction *MF = MBB->getParent();
6880 MachineRegisterInfo &MRI = MF->getRegInfo();
6883 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6884 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6886 MVT PVT = getPointerTy();
6887 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6888 "Invalid Pointer Size!");
6890 const TargetRegisterClass *RC =
6891 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6892 unsigned Tmp = MRI.createVirtualRegister(RC);
6893 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6894 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6895 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6896 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6897 (Subtarget.isSVR4ABI() &&
6898 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6899 PPC::R29 : PPC::R30);
6901 MachineInstrBuilder MIB;
6903 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6904 const int64_t SPOffset = 2 * PVT.getStoreSize();
6905 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6906 const int64_t BPOffset = 4 * PVT.getStoreSize();
6908 unsigned BufReg = MI->getOperand(0).getReg();
6910 // Reload FP (the jumped-to function may not have had a
6911 // frame pointer, and if so, then its r31 will be restored
6913 if (PVT == MVT::i64) {
6914 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6918 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6922 MIB.setMemRefs(MMOBegin, MMOEnd);
6925 if (PVT == MVT::i64) {
6926 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6927 .addImm(LabelOffset)
6930 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6931 .addImm(LabelOffset)
6934 MIB.setMemRefs(MMOBegin, MMOEnd);
6937 if (PVT == MVT::i64) {
6938 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6942 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6946 MIB.setMemRefs(MMOBegin, MMOEnd);
6949 if (PVT == MVT::i64) {
6950 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6954 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6958 MIB.setMemRefs(MMOBegin, MMOEnd);
6961 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6962 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6966 MIB.setMemRefs(MMOBegin, MMOEnd);
6970 BuildMI(*MBB, MI, DL,
6971 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6972 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6974 MI->eraseFromParent();
6979 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6980 MachineBasicBlock *BB) const {
6981 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6982 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6983 return emitEHSjLjSetJmp(MI, BB);
6984 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6985 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6986 return emitEHSjLjLongJmp(MI, BB);
6989 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6991 // To "insert" these instructions we actually have to insert their
6992 // control-flow patterns.
6993 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6994 MachineFunction::iterator It = BB;
6997 MachineFunction *F = BB->getParent();
6999 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7000 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7001 MI->getOpcode() == PPC::SELECT_I4 ||
7002 MI->getOpcode() == PPC::SELECT_I8)) {
7003 SmallVector<MachineOperand, 2> Cond;
7004 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7005 MI->getOpcode() == PPC::SELECT_CC_I8)
7006 Cond.push_back(MI->getOperand(4));
7008 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7009 Cond.push_back(MI->getOperand(1));
7011 DebugLoc dl = MI->getDebugLoc();
7012 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7013 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7014 Cond, MI->getOperand(2).getReg(),
7015 MI->getOperand(3).getReg());
7016 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7017 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7018 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7019 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7020 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7021 MI->getOpcode() == PPC::SELECT_I4 ||
7022 MI->getOpcode() == PPC::SELECT_I8 ||
7023 MI->getOpcode() == PPC::SELECT_F4 ||
7024 MI->getOpcode() == PPC::SELECT_F8 ||
7025 MI->getOpcode() == PPC::SELECT_VRRC) {
7026 // The incoming instruction knows the destination vreg to set, the
7027 // condition code register to branch on, the true/false values to
7028 // select between, and a branch opcode to use.
7033 // cmpTY ccX, r1, r2
7035 // fallthrough --> copy0MBB
7036 MachineBasicBlock *thisMBB = BB;
7037 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7038 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7039 DebugLoc dl = MI->getDebugLoc();
7040 F->insert(It, copy0MBB);
7041 F->insert(It, sinkMBB);
7043 // Transfer the remainder of BB and its successor edges to sinkMBB.
7044 sinkMBB->splice(sinkMBB->begin(), BB,
7045 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7046 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7048 // Next, add the true and fallthrough blocks as its successors.
7049 BB->addSuccessor(copy0MBB);
7050 BB->addSuccessor(sinkMBB);
7052 if (MI->getOpcode() == PPC::SELECT_I4 ||
7053 MI->getOpcode() == PPC::SELECT_I8 ||
7054 MI->getOpcode() == PPC::SELECT_F4 ||
7055 MI->getOpcode() == PPC::SELECT_F8 ||
7056 MI->getOpcode() == PPC::SELECT_VRRC) {
7057 BuildMI(BB, dl, TII->get(PPC::BC))
7058 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7060 unsigned SelectPred = MI->getOperand(4).getImm();
7061 BuildMI(BB, dl, TII->get(PPC::BCC))
7062 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7066 // %FalseValue = ...
7067 // # fallthrough to sinkMBB
7070 // Update machine-CFG edges
7071 BB->addSuccessor(sinkMBB);
7074 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7077 BuildMI(*BB, BB->begin(), dl,
7078 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7079 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7080 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7082 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7083 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7084 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7085 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7086 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7087 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7088 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7089 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7091 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7092 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7093 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7094 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7095 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7096 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7097 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7098 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7100 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7101 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7102 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7103 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7104 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7105 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7106 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7107 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7109 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7110 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7111 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7112 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7113 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7114 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7115 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7116 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7118 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7119 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7120 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7121 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7122 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7123 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7124 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7125 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7127 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7128 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7129 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7130 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7131 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7132 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7133 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7134 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7136 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7137 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7138 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7139 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7140 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7141 BB = EmitAtomicBinary(MI, BB, false, 0);
7142 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7143 BB = EmitAtomicBinary(MI, BB, true, 0);
7145 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7146 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7147 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7149 unsigned dest = MI->getOperand(0).getReg();
7150 unsigned ptrA = MI->getOperand(1).getReg();
7151 unsigned ptrB = MI->getOperand(2).getReg();
7152 unsigned oldval = MI->getOperand(3).getReg();
7153 unsigned newval = MI->getOperand(4).getReg();
7154 DebugLoc dl = MI->getDebugLoc();
7156 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7157 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7158 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7159 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7160 F->insert(It, loop1MBB);
7161 F->insert(It, loop2MBB);
7162 F->insert(It, midMBB);
7163 F->insert(It, exitMBB);
7164 exitMBB->splice(exitMBB->begin(), BB,
7165 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7166 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7170 // fallthrough --> loopMBB
7171 BB->addSuccessor(loop1MBB);
7174 // l[wd]arx dest, ptr
7175 // cmp[wd] dest, oldval
7178 // st[wd]cx. newval, ptr
7182 // st[wd]cx. dest, ptr
7185 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7186 .addReg(ptrA).addReg(ptrB);
7187 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7188 .addReg(oldval).addReg(dest);
7189 BuildMI(BB, dl, TII->get(PPC::BCC))
7190 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7191 BB->addSuccessor(loop2MBB);
7192 BB->addSuccessor(midMBB);
7195 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7196 .addReg(newval).addReg(ptrA).addReg(ptrB);
7197 BuildMI(BB, dl, TII->get(PPC::BCC))
7198 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7199 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7200 BB->addSuccessor(loop1MBB);
7201 BB->addSuccessor(exitMBB);
7204 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7205 .addReg(dest).addReg(ptrA).addReg(ptrB);
7206 BB->addSuccessor(exitMBB);
7211 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7212 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7213 // We must use 64-bit registers for addresses when targeting 64-bit,
7214 // since we're actually doing arithmetic on them. Other registers
7216 bool is64bit = Subtarget.isPPC64();
7217 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7219 unsigned dest = MI->getOperand(0).getReg();
7220 unsigned ptrA = MI->getOperand(1).getReg();
7221 unsigned ptrB = MI->getOperand(2).getReg();
7222 unsigned oldval = MI->getOperand(3).getReg();
7223 unsigned newval = MI->getOperand(4).getReg();
7224 DebugLoc dl = MI->getDebugLoc();
7226 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7227 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7228 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7229 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7230 F->insert(It, loop1MBB);
7231 F->insert(It, loop2MBB);
7232 F->insert(It, midMBB);
7233 F->insert(It, exitMBB);
7234 exitMBB->splice(exitMBB->begin(), BB,
7235 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7236 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7238 MachineRegisterInfo &RegInfo = F->getRegInfo();
7239 const TargetRegisterClass *RC =
7240 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7241 (const TargetRegisterClass *) &PPC::GPRCRegClass;
7242 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7243 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7244 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7245 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7246 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7247 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7248 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7249 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7250 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7251 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7252 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7253 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7254 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7256 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7257 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7260 // fallthrough --> loopMBB
7261 BB->addSuccessor(loop1MBB);
7263 // The 4-byte load must be aligned, while a char or short may be
7264 // anywhere in the word. Hence all this nasty bookkeeping code.
7265 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7266 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7267 // xori shift, shift1, 24 [16]
7268 // rlwinm ptr, ptr1, 0, 0, 29
7269 // slw newval2, newval, shift
7270 // slw oldval2, oldval,shift
7271 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7272 // slw mask, mask2, shift
7273 // and newval3, newval2, mask
7274 // and oldval3, oldval2, mask
7276 // lwarx tmpDest, ptr
7277 // and tmp, tmpDest, mask
7278 // cmpw tmp, oldval3
7281 // andc tmp2, tmpDest, mask
7282 // or tmp4, tmp2, newval3
7287 // stwcx. tmpDest, ptr
7289 // srw dest, tmpDest, shift
7290 if (ptrA != ZeroReg) {
7291 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7292 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7293 .addReg(ptrA).addReg(ptrB);
7297 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7298 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7299 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7300 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7302 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7303 .addReg(Ptr1Reg).addImm(0).addImm(61);
7305 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7306 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7307 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7308 .addReg(newval).addReg(ShiftReg);
7309 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7310 .addReg(oldval).addReg(ShiftReg);
7312 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7314 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7315 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7316 .addReg(Mask3Reg).addImm(65535);
7318 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7319 .addReg(Mask2Reg).addReg(ShiftReg);
7320 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7321 .addReg(NewVal2Reg).addReg(MaskReg);
7322 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7323 .addReg(OldVal2Reg).addReg(MaskReg);
7326 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7327 .addReg(ZeroReg).addReg(PtrReg);
7328 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7329 .addReg(TmpDestReg).addReg(MaskReg);
7330 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7331 .addReg(TmpReg).addReg(OldVal3Reg);
7332 BuildMI(BB, dl, TII->get(PPC::BCC))
7333 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7334 BB->addSuccessor(loop2MBB);
7335 BB->addSuccessor(midMBB);
7338 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7339 .addReg(TmpDestReg).addReg(MaskReg);
7340 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7341 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7342 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7343 .addReg(ZeroReg).addReg(PtrReg);
7344 BuildMI(BB, dl, TII->get(PPC::BCC))
7345 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7346 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7347 BB->addSuccessor(loop1MBB);
7348 BB->addSuccessor(exitMBB);
7351 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7352 .addReg(ZeroReg).addReg(PtrReg);
7353 BB->addSuccessor(exitMBB);
7358 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7360 } else if (MI->getOpcode() == PPC::FADDrtz) {
7361 // This pseudo performs an FADD with rounding mode temporarily forced
7362 // to round-to-zero. We emit this via custom inserter since the FPSCR
7363 // is not modeled at the SelectionDAG level.
7364 unsigned Dest = MI->getOperand(0).getReg();
7365 unsigned Src1 = MI->getOperand(1).getReg();
7366 unsigned Src2 = MI->getOperand(2).getReg();
7367 DebugLoc dl = MI->getDebugLoc();
7369 MachineRegisterInfo &RegInfo = F->getRegInfo();
7370 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7372 // Save FPSCR value.
7373 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7375 // Set rounding mode to round-to-zero.
7376 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7377 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7379 // Perform addition.
7380 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7382 // Restore FPSCR value.
7383 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7384 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7385 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7386 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7387 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7388 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7389 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7390 PPC::ANDIo8 : PPC::ANDIo;
7391 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7392 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7394 MachineRegisterInfo &RegInfo = F->getRegInfo();
7395 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7396 &PPC::GPRCRegClass :
7397 &PPC::G8RCRegClass);
7399 DebugLoc dl = MI->getDebugLoc();
7400 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7401 .addReg(MI->getOperand(1).getReg()).addImm(1);
7402 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7403 MI->getOperand(0).getReg())
7404 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7406 llvm_unreachable("Unexpected instr type to insert");
7409 MI->eraseFromParent(); // The pseudo instruction is gone now.
7413 //===----------------------------------------------------------------------===//
7414 // Target Optimization Hooks
7415 //===----------------------------------------------------------------------===//
7417 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7418 DAGCombinerInfo &DCI) const {
7419 if (DCI.isAfterLegalizeVectorOps())
7422 EVT VT = Op.getValueType();
7424 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7425 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7426 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7427 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7429 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7430 // For the reciprocal, we need to find the zero of the function:
7431 // F(X) = A X - 1 [which has a zero at X = 1/A]
7433 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7434 // does not require additional intermediate precision]
7436 // Convergence is quadratic, so we essentially double the number of digits
7437 // correct after every iteration. The minimum architected relative
7438 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7439 // 23 digits and double has 52 digits.
7440 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7441 if (VT.getScalarType() == MVT::f64)
7444 SelectionDAG &DAG = DCI.DAG;
7448 DAG.getConstantFP(1.0, VT.getScalarType());
7449 if (VT.isVector()) {
7450 assert(VT.getVectorNumElements() == 4 &&
7451 "Unknown vector type");
7452 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7453 FPOne, FPOne, FPOne, FPOne);
7456 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7457 DCI.AddToWorklist(Est.getNode());
7459 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7460 for (int i = 0; i < Iterations; ++i) {
7461 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7462 DCI.AddToWorklist(NewEst.getNode());
7464 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7465 DCI.AddToWorklist(NewEst.getNode());
7467 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7468 DCI.AddToWorklist(NewEst.getNode());
7470 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7471 DCI.AddToWorklist(Est.getNode());
7480 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7481 DAGCombinerInfo &DCI) const {
7482 if (DCI.isAfterLegalizeVectorOps())
7485 EVT VT = Op.getValueType();
7487 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7488 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7489 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7490 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7492 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7493 // For the reciprocal sqrt, we need to find the zero of the function:
7494 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7496 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7497 // As a result, we precompute A/2 prior to the iteration loop.
7499 // Convergence is quadratic, so we essentially double the number of digits
7500 // correct after every iteration. The minimum architected relative
7501 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7502 // 23 digits and double has 52 digits.
7503 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7504 if (VT.getScalarType() == MVT::f64)
7507 SelectionDAG &DAG = DCI.DAG;
7510 SDValue FPThreeHalves =
7511 DAG.getConstantFP(1.5, VT.getScalarType());
7512 if (VT.isVector()) {
7513 assert(VT.getVectorNumElements() == 4 &&
7514 "Unknown vector type");
7515 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7516 FPThreeHalves, FPThreeHalves,
7517 FPThreeHalves, FPThreeHalves);
7520 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7521 DCI.AddToWorklist(Est.getNode());
7523 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7524 // this entire sequence requires only one FP constant.
7525 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7526 DCI.AddToWorklist(HalfArg.getNode());
7528 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7529 DCI.AddToWorklist(HalfArg.getNode());
7531 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7532 for (int i = 0; i < Iterations; ++i) {
7533 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7534 DCI.AddToWorklist(NewEst.getNode());
7536 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7537 DCI.AddToWorklist(NewEst.getNode());
7539 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7540 DCI.AddToWorklist(NewEst.getNode());
7542 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7543 DCI.AddToWorklist(Est.getNode());
7552 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7553 // not enforce equality of the chain operands.
7554 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7555 unsigned Bytes, int Dist,
7556 SelectionDAG &DAG) {
7557 EVT VT = LS->getMemoryVT();
7558 if (VT.getSizeInBits() / 8 != Bytes)
7561 SDValue Loc = LS->getBasePtr();
7562 SDValue BaseLoc = Base->getBasePtr();
7563 if (Loc.getOpcode() == ISD::FrameIndex) {
7564 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7566 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7567 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7568 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7569 int FS = MFI->getObjectSize(FI);
7570 int BFS = MFI->getObjectSize(BFI);
7571 if (FS != BFS || FS != (int)Bytes) return false;
7572 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7576 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7577 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7580 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7581 const GlobalValue *GV1 = nullptr;
7582 const GlobalValue *GV2 = nullptr;
7583 int64_t Offset1 = 0;
7584 int64_t Offset2 = 0;
7585 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7586 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7587 if (isGA1 && isGA2 && GV1 == GV2)
7588 return Offset1 == (Offset2 + Dist*Bytes);
7592 // Return true is there is a nearyby consecutive load to the one provided
7593 // (regardless of alignment). We search up and down the chain, looking though
7594 // token factors and other loads (but nothing else). As a result, a true
7595 // results indicates that it is safe to create a new consecutive load adjacent
7596 // to the load provided.
7597 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7598 SDValue Chain = LD->getChain();
7599 EVT VT = LD->getMemoryVT();
7601 SmallSet<SDNode *, 16> LoadRoots;
7602 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7603 SmallSet<SDNode *, 16> Visited;
7605 // First, search up the chain, branching to follow all token-factor operands.
7606 // If we find a consecutive load, then we're done, otherwise, record all
7607 // nodes just above the top-level loads and token factors.
7608 while (!Queue.empty()) {
7609 SDNode *ChainNext = Queue.pop_back_val();
7610 if (!Visited.insert(ChainNext))
7613 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7614 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7617 if (!Visited.count(ChainLD->getChain().getNode()))
7618 Queue.push_back(ChainLD->getChain().getNode());
7619 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7620 for (const SDUse &O : ChainNext->ops())
7621 if (!Visited.count(O.getNode()))
7622 Queue.push_back(O.getNode());
7624 LoadRoots.insert(ChainNext);
7627 // Second, search down the chain, starting from the top-level nodes recorded
7628 // in the first phase. These top-level nodes are the nodes just above all
7629 // loads and token factors. Starting with their uses, recursively look though
7630 // all loads (just the chain uses) and token factors to find a consecutive
7635 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7636 IE = LoadRoots.end(); I != IE; ++I) {
7637 Queue.push_back(*I);
7639 while (!Queue.empty()) {
7640 SDNode *LoadRoot = Queue.pop_back_val();
7641 if (!Visited.insert(LoadRoot))
7644 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7645 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7648 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7649 UE = LoadRoot->use_end(); UI != UE; ++UI)
7650 if (((isa<LoadSDNode>(*UI) &&
7651 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7652 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7653 Queue.push_back(*UI);
7660 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7661 DAGCombinerInfo &DCI) const {
7662 SelectionDAG &DAG = DCI.DAG;
7665 assert(Subtarget.useCRBits() &&
7666 "Expecting to be tracking CR bits");
7667 // If we're tracking CR bits, we need to be careful that we don't have:
7668 // trunc(binary-ops(zext(x), zext(y)))
7670 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7671 // such that we're unnecessarily moving things into GPRs when it would be
7672 // better to keep them in CR bits.
7674 // Note that trunc here can be an actual i1 trunc, or can be the effective
7675 // truncation that comes from a setcc or select_cc.
7676 if (N->getOpcode() == ISD::TRUNCATE &&
7677 N->getValueType(0) != MVT::i1)
7680 if (N->getOperand(0).getValueType() != MVT::i32 &&
7681 N->getOperand(0).getValueType() != MVT::i64)
7684 if (N->getOpcode() == ISD::SETCC ||
7685 N->getOpcode() == ISD::SELECT_CC) {
7686 // If we're looking at a comparison, then we need to make sure that the
7687 // high bits (all except for the first) don't matter the result.
7689 cast<CondCodeSDNode>(N->getOperand(
7690 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7691 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7693 if (ISD::isSignedIntSetCC(CC)) {
7694 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7695 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7697 } else if (ISD::isUnsignedIntSetCC(CC)) {
7698 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7699 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7700 !DAG.MaskedValueIsZero(N->getOperand(1),
7701 APInt::getHighBitsSet(OpBits, OpBits-1)))
7704 // This is neither a signed nor an unsigned comparison, just make sure
7705 // that the high bits are equal.
7706 APInt Op1Zero, Op1One;
7707 APInt Op2Zero, Op2One;
7708 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7709 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7711 // We don't really care about what is known about the first bit (if
7712 // anything), so clear it in all masks prior to comparing them.
7713 Op1Zero.clearBit(0); Op1One.clearBit(0);
7714 Op2Zero.clearBit(0); Op2One.clearBit(0);
7716 if (Op1Zero != Op2Zero || Op1One != Op2One)
7721 // We now know that the higher-order bits are irrelevant, we just need to
7722 // make sure that all of the intermediate operations are bit operations, and
7723 // all inputs are extensions.
7724 if (N->getOperand(0).getOpcode() != ISD::AND &&
7725 N->getOperand(0).getOpcode() != ISD::OR &&
7726 N->getOperand(0).getOpcode() != ISD::XOR &&
7727 N->getOperand(0).getOpcode() != ISD::SELECT &&
7728 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7729 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7730 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7731 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7732 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7735 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7736 N->getOperand(1).getOpcode() != ISD::AND &&
7737 N->getOperand(1).getOpcode() != ISD::OR &&
7738 N->getOperand(1).getOpcode() != ISD::XOR &&
7739 N->getOperand(1).getOpcode() != ISD::SELECT &&
7740 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7741 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7742 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7743 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7744 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7747 SmallVector<SDValue, 4> Inputs;
7748 SmallVector<SDValue, 8> BinOps, PromOps;
7749 SmallPtrSet<SDNode *, 16> Visited;
7751 for (unsigned i = 0; i < 2; ++i) {
7752 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7753 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7754 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7755 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7756 isa<ConstantSDNode>(N->getOperand(i)))
7757 Inputs.push_back(N->getOperand(i));
7759 BinOps.push_back(N->getOperand(i));
7761 if (N->getOpcode() == ISD::TRUNCATE)
7765 // Visit all inputs, collect all binary operations (and, or, xor and
7766 // select) that are all fed by extensions.
7767 while (!BinOps.empty()) {
7768 SDValue BinOp = BinOps.back();
7771 if (!Visited.insert(BinOp.getNode()))
7774 PromOps.push_back(BinOp);
7776 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7777 // The condition of the select is not promoted.
7778 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7780 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7783 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7784 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7785 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7786 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7787 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7788 Inputs.push_back(BinOp.getOperand(i));
7789 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7790 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7791 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7792 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7793 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7794 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7795 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7796 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7797 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7798 BinOps.push_back(BinOp.getOperand(i));
7800 // We have an input that is not an extension or another binary
7801 // operation; we'll abort this transformation.
7807 // Make sure that this is a self-contained cluster of operations (which
7808 // is not quite the same thing as saying that everything has only one
7810 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7811 if (isa<ConstantSDNode>(Inputs[i]))
7814 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7815 UE = Inputs[i].getNode()->use_end();
7818 if (User != N && !Visited.count(User))
7821 // Make sure that we're not going to promote the non-output-value
7822 // operand(s) or SELECT or SELECT_CC.
7823 // FIXME: Although we could sometimes handle this, and it does occur in
7824 // practice that one of the condition inputs to the select is also one of
7825 // the outputs, we currently can't deal with this.
7826 if (User->getOpcode() == ISD::SELECT) {
7827 if (User->getOperand(0) == Inputs[i])
7829 } else if (User->getOpcode() == ISD::SELECT_CC) {
7830 if (User->getOperand(0) == Inputs[i] ||
7831 User->getOperand(1) == Inputs[i])
7837 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7838 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7839 UE = PromOps[i].getNode()->use_end();
7842 if (User != N && !Visited.count(User))
7845 // Make sure that we're not going to promote the non-output-value
7846 // operand(s) or SELECT or SELECT_CC.
7847 // FIXME: Although we could sometimes handle this, and it does occur in
7848 // practice that one of the condition inputs to the select is also one of
7849 // the outputs, we currently can't deal with this.
7850 if (User->getOpcode() == ISD::SELECT) {
7851 if (User->getOperand(0) == PromOps[i])
7853 } else if (User->getOpcode() == ISD::SELECT_CC) {
7854 if (User->getOperand(0) == PromOps[i] ||
7855 User->getOperand(1) == PromOps[i])
7861 // Replace all inputs with the extension operand.
7862 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7863 // Constants may have users outside the cluster of to-be-promoted nodes,
7864 // and so we need to replace those as we do the promotions.
7865 if (isa<ConstantSDNode>(Inputs[i]))
7868 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7871 // Replace all operations (these are all the same, but have a different
7872 // (i1) return type). DAG.getNode will validate that the types of
7873 // a binary operator match, so go through the list in reverse so that
7874 // we've likely promoted both operands first. Any intermediate truncations or
7875 // extensions disappear.
7876 while (!PromOps.empty()) {
7877 SDValue PromOp = PromOps.back();
7880 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7881 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7882 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7883 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7884 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7885 PromOp.getOperand(0).getValueType() != MVT::i1) {
7886 // The operand is not yet ready (see comment below).
7887 PromOps.insert(PromOps.begin(), PromOp);
7891 SDValue RepValue = PromOp.getOperand(0);
7892 if (isa<ConstantSDNode>(RepValue))
7893 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7895 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7900 switch (PromOp.getOpcode()) {
7901 default: C = 0; break;
7902 case ISD::SELECT: C = 1; break;
7903 case ISD::SELECT_CC: C = 2; break;
7906 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7907 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7908 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7909 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7910 // The to-be-promoted operands of this node have not yet been
7911 // promoted (this should be rare because we're going through the
7912 // list backward, but if one of the operands has several users in
7913 // this cluster of to-be-promoted nodes, it is possible).
7914 PromOps.insert(PromOps.begin(), PromOp);
7918 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7919 PromOp.getNode()->op_end());
7921 // If there are any constant inputs, make sure they're replaced now.
7922 for (unsigned i = 0; i < 2; ++i)
7923 if (isa<ConstantSDNode>(Ops[C+i]))
7924 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7926 DAG.ReplaceAllUsesOfValueWith(PromOp,
7927 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7930 // Now we're left with the initial truncation itself.
7931 if (N->getOpcode() == ISD::TRUNCATE)
7932 return N->getOperand(0);
7934 // Otherwise, this is a comparison. The operands to be compared have just
7935 // changed type (to i1), but everything else is the same.
7936 return SDValue(N, 0);
7939 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7940 DAGCombinerInfo &DCI) const {
7941 SelectionDAG &DAG = DCI.DAG;
7944 // If we're tracking CR bits, we need to be careful that we don't have:
7945 // zext(binary-ops(trunc(x), trunc(y)))
7947 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7948 // such that we're unnecessarily moving things into CR bits that can more
7949 // efficiently stay in GPRs. Note that if we're not certain that the high
7950 // bits are set as required by the final extension, we still may need to do
7951 // some masking to get the proper behavior.
7953 // This same functionality is important on PPC64 when dealing with
7954 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7955 // the return values of functions. Because it is so similar, it is handled
7958 if (N->getValueType(0) != MVT::i32 &&
7959 N->getValueType(0) != MVT::i64)
7962 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7963 Subtarget.useCRBits()) ||
7964 (N->getOperand(0).getValueType() == MVT::i32 &&
7965 Subtarget.isPPC64())))
7968 if (N->getOperand(0).getOpcode() != ISD::AND &&
7969 N->getOperand(0).getOpcode() != ISD::OR &&
7970 N->getOperand(0).getOpcode() != ISD::XOR &&
7971 N->getOperand(0).getOpcode() != ISD::SELECT &&
7972 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7975 SmallVector<SDValue, 4> Inputs;
7976 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7977 SmallPtrSet<SDNode *, 16> Visited;
7979 // Visit all inputs, collect all binary operations (and, or, xor and
7980 // select) that are all fed by truncations.
7981 while (!BinOps.empty()) {
7982 SDValue BinOp = BinOps.back();
7985 if (!Visited.insert(BinOp.getNode()))
7988 PromOps.push_back(BinOp);
7990 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7991 // The condition of the select is not promoted.
7992 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7994 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7997 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7998 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7999 Inputs.push_back(BinOp.getOperand(i));
8000 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8001 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8002 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8003 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8004 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8005 BinOps.push_back(BinOp.getOperand(i));
8007 // We have an input that is not a truncation or another binary
8008 // operation; we'll abort this transformation.
8014 // Make sure that this is a self-contained cluster of operations (which
8015 // is not quite the same thing as saying that everything has only one
8017 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8018 if (isa<ConstantSDNode>(Inputs[i]))
8021 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8022 UE = Inputs[i].getNode()->use_end();
8025 if (User != N && !Visited.count(User))
8028 // Make sure that we're not going to promote the non-output-value
8029 // operand(s) or SELECT or SELECT_CC.
8030 // FIXME: Although we could sometimes handle this, and it does occur in
8031 // practice that one of the condition inputs to the select is also one of
8032 // the outputs, we currently can't deal with this.
8033 if (User->getOpcode() == ISD::SELECT) {
8034 if (User->getOperand(0) == Inputs[i])
8036 } else if (User->getOpcode() == ISD::SELECT_CC) {
8037 if (User->getOperand(0) == Inputs[i] ||
8038 User->getOperand(1) == Inputs[i])
8044 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8045 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8046 UE = PromOps[i].getNode()->use_end();
8049 if (User != N && !Visited.count(User))
8052 // Make sure that we're not going to promote the non-output-value
8053 // operand(s) or SELECT or SELECT_CC.
8054 // FIXME: Although we could sometimes handle this, and it does occur in
8055 // practice that one of the condition inputs to the select is also one of
8056 // the outputs, we currently can't deal with this.
8057 if (User->getOpcode() == ISD::SELECT) {
8058 if (User->getOperand(0) == PromOps[i])
8060 } else if (User->getOpcode() == ISD::SELECT_CC) {
8061 if (User->getOperand(0) == PromOps[i] ||
8062 User->getOperand(1) == PromOps[i])
8068 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8069 bool ReallyNeedsExt = false;
8070 if (N->getOpcode() != ISD::ANY_EXTEND) {
8071 // If all of the inputs are not already sign/zero extended, then
8072 // we'll still need to do that at the end.
8073 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8074 if (isa<ConstantSDNode>(Inputs[i]))
8078 Inputs[i].getOperand(0).getValueSizeInBits();
8079 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8081 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8082 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8083 APInt::getHighBitsSet(OpBits,
8084 OpBits-PromBits))) ||
8085 (N->getOpcode() == ISD::SIGN_EXTEND &&
8086 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8087 (OpBits-(PromBits-1)))) {
8088 ReallyNeedsExt = true;
8094 // Replace all inputs, either with the truncation operand, or a
8095 // truncation or extension to the final output type.
8096 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8097 // Constant inputs need to be replaced with the to-be-promoted nodes that
8098 // use them because they might have users outside of the cluster of
8100 if (isa<ConstantSDNode>(Inputs[i]))
8103 SDValue InSrc = Inputs[i].getOperand(0);
8104 if (Inputs[i].getValueType() == N->getValueType(0))
8105 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8106 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8107 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8108 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8109 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8110 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8111 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8113 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8114 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8117 // Replace all operations (these are all the same, but have a different
8118 // (promoted) return type). DAG.getNode will validate that the types of
8119 // a binary operator match, so go through the list in reverse so that
8120 // we've likely promoted both operands first.
8121 while (!PromOps.empty()) {
8122 SDValue PromOp = PromOps.back();
8126 switch (PromOp.getOpcode()) {
8127 default: C = 0; break;
8128 case ISD::SELECT: C = 1; break;
8129 case ISD::SELECT_CC: C = 2; break;
8132 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8133 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8134 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8135 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8136 // The to-be-promoted operands of this node have not yet been
8137 // promoted (this should be rare because we're going through the
8138 // list backward, but if one of the operands has several users in
8139 // this cluster of to-be-promoted nodes, it is possible).
8140 PromOps.insert(PromOps.begin(), PromOp);
8144 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8145 PromOp.getNode()->op_end());
8147 // If this node has constant inputs, then they'll need to be promoted here.
8148 for (unsigned i = 0; i < 2; ++i) {
8149 if (!isa<ConstantSDNode>(Ops[C+i]))
8151 if (Ops[C+i].getValueType() == N->getValueType(0))
8154 if (N->getOpcode() == ISD::SIGN_EXTEND)
8155 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8156 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8157 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8159 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8162 DAG.ReplaceAllUsesOfValueWith(PromOp,
8163 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8166 // Now we're left with the initial extension itself.
8167 if (!ReallyNeedsExt)
8168 return N->getOperand(0);
8170 // To zero extend, just mask off everything except for the first bit (in the
8172 if (N->getOpcode() == ISD::ZERO_EXTEND)
8173 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8174 DAG.getConstant(APInt::getLowBitsSet(
8175 N->getValueSizeInBits(0), PromBits),
8176 N->getValueType(0)));
8178 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8179 "Invalid extension type");
8180 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8182 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8183 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8184 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8185 N->getOperand(0), ShiftCst), ShiftCst);
8188 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8189 DAGCombinerInfo &DCI) const {
8190 const TargetMachine &TM = getTargetMachine();
8191 SelectionDAG &DAG = DCI.DAG;
8193 switch (N->getOpcode()) {
8196 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8197 if (C->isNullValue()) // 0 << V -> 0.
8198 return N->getOperand(0);
8202 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8203 if (C->isNullValue()) // 0 >>u V -> 0.
8204 return N->getOperand(0);
8208 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8209 if (C->isNullValue() || // 0 >>s V -> 0.
8210 C->isAllOnesValue()) // -1 >>s V -> -1.
8211 return N->getOperand(0);
8214 case ISD::SIGN_EXTEND:
8215 case ISD::ZERO_EXTEND:
8216 case ISD::ANY_EXTEND:
8217 return DAGCombineExtBoolTrunc(N, DCI);
8220 case ISD::SELECT_CC:
8221 return DAGCombineTruncBoolExt(N, DCI);
8223 assert(TM.Options.UnsafeFPMath &&
8224 "Reciprocal estimates require UnsafeFPMath");
8226 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
8228 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
8230 DCI.AddToWorklist(RV.getNode());
8231 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8232 N->getOperand(0), RV);
8234 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
8235 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8237 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8240 DCI.AddToWorklist(RV.getNode());
8241 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
8242 N->getValueType(0), RV);
8243 DCI.AddToWorklist(RV.getNode());
8244 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8245 N->getOperand(0), RV);
8247 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
8248 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8250 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8253 DCI.AddToWorklist(RV.getNode());
8254 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
8255 N->getValueType(0), RV,
8256 N->getOperand(1).getOperand(1));
8257 DCI.AddToWorklist(RV.getNode());
8258 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8259 N->getOperand(0), RV);
8263 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8265 DCI.AddToWorklist(RV.getNode());
8266 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8267 N->getOperand(0), RV);
8273 assert(TM.Options.UnsafeFPMath &&
8274 "Reciprocal estimates require UnsafeFPMath");
8276 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8278 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8280 DCI.AddToWorklist(RV.getNode());
8281 RV = DAGCombineFastRecip(RV, DCI);
8283 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8284 // this case and force the answer to 0.
8286 EVT VT = RV.getValueType();
8288 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8289 if (VT.isVector()) {
8290 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8291 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8295 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8296 N->getOperand(0), Zero, ISD::SETEQ);
8297 DCI.AddToWorklist(ZeroCmp.getNode());
8298 DCI.AddToWorklist(RV.getNode());
8300 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8308 case ISD::SINT_TO_FP:
8309 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8310 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8311 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8312 // We allow the src/dst to be either f32/f64, but the intermediate
8313 // type must be i64.
8314 if (N->getOperand(0).getValueType() == MVT::i64 &&
8315 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8316 SDValue Val = N->getOperand(0).getOperand(0);
8317 if (Val.getValueType() == MVT::f32) {
8318 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8319 DCI.AddToWorklist(Val.getNode());
8322 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8323 DCI.AddToWorklist(Val.getNode());
8324 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8325 DCI.AddToWorklist(Val.getNode());
8326 if (N->getValueType(0) == MVT::f32) {
8327 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8328 DAG.getIntPtrConstant(0));
8329 DCI.AddToWorklist(Val.getNode());
8332 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8333 // If the intermediate type is i32, we can avoid the load/store here
8340 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8341 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8342 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8343 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8344 N->getOperand(1).getValueType() == MVT::i32 &&
8345 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8346 SDValue Val = N->getOperand(1).getOperand(0);
8347 if (Val.getValueType() == MVT::f32) {
8348 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8349 DCI.AddToWorklist(Val.getNode());
8351 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8352 DCI.AddToWorklist(Val.getNode());
8355 N->getOperand(0), Val, N->getOperand(2),
8356 DAG.getValueType(N->getOperand(1).getValueType())
8359 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8360 DAG.getVTList(MVT::Other), Ops,
8361 cast<StoreSDNode>(N)->getMemoryVT(),
8362 cast<StoreSDNode>(N)->getMemOperand());
8363 DCI.AddToWorklist(Val.getNode());
8367 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8368 if (cast<StoreSDNode>(N)->isUnindexed() &&
8369 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8370 N->getOperand(1).getNode()->hasOneUse() &&
8371 (N->getOperand(1).getValueType() == MVT::i32 ||
8372 N->getOperand(1).getValueType() == MVT::i16 ||
8373 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8374 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8375 N->getOperand(1).getValueType() == MVT::i64))) {
8376 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8377 // Do an any-extend to 32-bits if this is a half-word input.
8378 if (BSwapOp.getValueType() == MVT::i16)
8379 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8382 N->getOperand(0), BSwapOp, N->getOperand(2),
8383 DAG.getValueType(N->getOperand(1).getValueType())
8386 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8387 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8388 cast<StoreSDNode>(N)->getMemOperand());
8392 LoadSDNode *LD = cast<LoadSDNode>(N);
8393 EVT VT = LD->getValueType(0);
8394 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8395 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8396 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8397 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8398 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8399 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8400 LD->getAlignment() < ABIAlignment) {
8401 // This is a type-legal unaligned Altivec load.
8402 SDValue Chain = LD->getChain();
8403 SDValue Ptr = LD->getBasePtr();
8404 bool isLittleEndian = Subtarget.isLittleEndian();
8406 // This implements the loading of unaligned vectors as described in
8407 // the venerable Apple Velocity Engine overview. Specifically:
8408 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8409 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8411 // The general idea is to expand a sequence of one or more unaligned
8412 // loads into an alignment-based permutation-control instruction (lvsl
8413 // or lvsr), a series of regular vector loads (which always truncate
8414 // their input address to an aligned address), and a series of
8415 // permutations. The results of these permutations are the requested
8416 // loaded values. The trick is that the last "extra" load is not taken
8417 // from the address you might suspect (sizeof(vector) bytes after the
8418 // last requested load), but rather sizeof(vector) - 1 bytes after the
8419 // last requested vector. The point of this is to avoid a page fault if
8420 // the base address happened to be aligned. This works because if the
8421 // base address is aligned, then adding less than a full vector length
8422 // will cause the last vector in the sequence to be (re)loaded.
8423 // Otherwise, the next vector will be fetched as you might suspect was
8426 // We might be able to reuse the permutation generation from
8427 // a different base address offset from this one by an aligned amount.
8428 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8429 // optimization later.
8430 Intrinsic::ID Intr = (isLittleEndian ?
8431 Intrinsic::ppc_altivec_lvsr :
8432 Intrinsic::ppc_altivec_lvsl);
8433 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8435 // Refine the alignment of the original load (a "new" load created here
8436 // which was identical to the first except for the alignment would be
8437 // merged with the existing node regardless).
8438 MachineFunction &MF = DAG.getMachineFunction();
8439 MachineMemOperand *MMO =
8440 MF.getMachineMemOperand(LD->getPointerInfo(),
8441 LD->getMemOperand()->getFlags(),
8442 LD->getMemoryVT().getStoreSize(),
8444 LD->refineAlignment(MMO);
8445 SDValue BaseLoad = SDValue(LD, 0);
8447 // Note that the value of IncOffset (which is provided to the next
8448 // load's pointer info offset value, and thus used to calculate the
8449 // alignment), and the value of IncValue (which is actually used to
8450 // increment the pointer value) are different! This is because we
8451 // require the next load to appear to be aligned, even though it
8452 // is actually offset from the base pointer by a lesser amount.
8453 int IncOffset = VT.getSizeInBits() / 8;
8454 int IncValue = IncOffset;
8456 // Walk (both up and down) the chain looking for another load at the real
8457 // (aligned) offset (the alignment of the other load does not matter in
8458 // this case). If found, then do not use the offset reduction trick, as
8459 // that will prevent the loads from being later combined (as they would
8460 // otherwise be duplicates).
8461 if (!findConsecutiveLoad(LD, DAG))
8464 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8465 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8468 DAG.getLoad(VT, dl, Chain, Ptr,
8469 LD->getPointerInfo().getWithOffset(IncOffset),
8470 LD->isVolatile(), LD->isNonTemporal(),
8471 LD->isInvariant(), ABIAlignment);
8473 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8474 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8476 if (BaseLoad.getValueType() != MVT::v4i32)
8477 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8479 if (ExtraLoad.getValueType() != MVT::v4i32)
8480 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8482 // Because vperm has a big-endian bias, we must reverse the order
8483 // of the input vectors and complement the permute control vector
8484 // when generating little endian code. We have already handled the
8485 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8486 // and ExtraLoad here.
8489 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8490 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8492 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8493 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8495 if (VT != MVT::v4i32)
8496 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8498 // Now we need to be really careful about how we update the users of the
8499 // original load. We cannot just call DCI.CombineTo (or
8500 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8501 // uses created here (the permutation for example) that need to stay.
8502 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8504 SDUse &Use = UI.getUse();
8506 // Note: BaseLoad is checked here because it might not be N, but a
8508 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8509 User == TF.getNode() || Use.getResNo() > 1) {
8514 SDValue To = Use.getResNo() ? TF : Perm;
8517 SmallVector<SDValue, 8> Ops;
8518 for (const SDUse &O : User->ops()) {
8525 DAG.UpdateNodeOperands(User, Ops);
8528 return SDValue(N, 0);
8532 case ISD::INTRINSIC_WO_CHAIN: {
8533 bool isLittleEndian = Subtarget.isLittleEndian();
8534 Intrinsic::ID Intr = (isLittleEndian ?
8535 Intrinsic::ppc_altivec_lvsr :
8536 Intrinsic::ppc_altivec_lvsl);
8537 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8538 N->getOperand(1)->getOpcode() == ISD::ADD) {
8539 SDValue Add = N->getOperand(1);
8541 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8542 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8543 Add.getValueType().getScalarType().getSizeInBits()))) {
8544 SDNode *BasePtr = Add->getOperand(0).getNode();
8545 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8546 UE = BasePtr->use_end(); UI != UE; ++UI) {
8547 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8548 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8550 // We've found another LVSL/LVSR, and this address is an aligned
8551 // multiple of that one. The results will be the same, so use the
8552 // one we've just found instead.
8554 return SDValue(*UI, 0);
8563 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8564 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8565 N->getOperand(0).hasOneUse() &&
8566 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8567 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8568 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8569 N->getValueType(0) == MVT::i64))) {
8570 SDValue Load = N->getOperand(0);
8571 LoadSDNode *LD = cast<LoadSDNode>(Load);
8572 // Create the byte-swapping load.
8574 LD->getChain(), // Chain
8575 LD->getBasePtr(), // Ptr
8576 DAG.getValueType(N->getValueType(0)) // VT
8579 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8580 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8581 MVT::i64 : MVT::i32, MVT::Other),
8582 Ops, LD->getMemoryVT(), LD->getMemOperand());
8584 // If this is an i16 load, insert the truncate.
8585 SDValue ResVal = BSLoad;
8586 if (N->getValueType(0) == MVT::i16)
8587 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8589 // First, combine the bswap away. This makes the value produced by the
8591 DCI.CombineTo(N, ResVal);
8593 // Next, combine the load away, we give it a bogus result value but a real
8594 // chain result. The result value is dead because the bswap is dead.
8595 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8597 // Return N so it doesn't get rechecked!
8598 return SDValue(N, 0);
8602 case PPCISD::VCMP: {
8603 // If a VCMPo node already exists with exactly the same operands as this
8604 // node, use its result instead of this node (VCMPo computes both a CR6 and
8605 // a normal output).
8607 if (!N->getOperand(0).hasOneUse() &&
8608 !N->getOperand(1).hasOneUse() &&
8609 !N->getOperand(2).hasOneUse()) {
8611 // Scan all of the users of the LHS, looking for VCMPo's that match.
8612 SDNode *VCMPoNode = nullptr;
8614 SDNode *LHSN = N->getOperand(0).getNode();
8615 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8617 if (UI->getOpcode() == PPCISD::VCMPo &&
8618 UI->getOperand(1) == N->getOperand(1) &&
8619 UI->getOperand(2) == N->getOperand(2) &&
8620 UI->getOperand(0) == N->getOperand(0)) {
8625 // If there is no VCMPo node, or if the flag value has a single use, don't
8627 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8630 // Look at the (necessarily single) use of the flag value. If it has a
8631 // chain, this transformation is more complex. Note that multiple things
8632 // could use the value result, which we should ignore.
8633 SDNode *FlagUser = nullptr;
8634 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8635 FlagUser == nullptr; ++UI) {
8636 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8638 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8639 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8646 // If the user is a MFOCRF instruction, we know this is safe.
8647 // Otherwise we give up for right now.
8648 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8649 return SDValue(VCMPoNode, 0);
8654 SDValue Cond = N->getOperand(1);
8655 SDValue Target = N->getOperand(2);
8657 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8658 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8659 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8661 // We now need to make the intrinsic dead (it cannot be instruction
8663 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8664 assert(Cond.getNode()->hasOneUse() &&
8665 "Counter decrement has more than one use");
8667 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8668 N->getOperand(0), Target);
8673 // If this is a branch on an altivec predicate comparison, lower this so
8674 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8675 // lowering is done pre-legalize, because the legalizer lowers the predicate
8676 // compare down to code that is difficult to reassemble.
8677 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8678 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8680 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8681 // value. If so, pass-through the AND to get to the intrinsic.
8682 if (LHS.getOpcode() == ISD::AND &&
8683 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8684 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8685 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8686 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8687 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8689 LHS = LHS.getOperand(0);
8691 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8692 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8693 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8694 isa<ConstantSDNode>(RHS)) {
8695 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8696 "Counter decrement comparison is not EQ or NE");
8698 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8699 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8700 (CC == ISD::SETNE && !Val);
8702 // We now need to make the intrinsic dead (it cannot be instruction
8704 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8705 assert(LHS.getNode()->hasOneUse() &&
8706 "Counter decrement has more than one use");
8708 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8709 N->getOperand(0), N->getOperand(4));
8715 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8716 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8717 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8718 assert(isDot && "Can't compare against a vector result!");
8720 // If this is a comparison against something other than 0/1, then we know
8721 // that the condition is never/always true.
8722 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8723 if (Val != 0 && Val != 1) {
8724 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8725 return N->getOperand(0);
8726 // Always !=, turn it into an unconditional branch.
8727 return DAG.getNode(ISD::BR, dl, MVT::Other,
8728 N->getOperand(0), N->getOperand(4));
8731 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8733 // Create the PPCISD altivec 'dot' comparison node.
8735 LHS.getOperand(2), // LHS of compare
8736 LHS.getOperand(3), // RHS of compare
8737 DAG.getConstant(CompareOpc, MVT::i32)
8739 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8740 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8742 // Unpack the result based on how the target uses it.
8743 PPC::Predicate CompOpc;
8744 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8745 default: // Can't happen, don't crash on invalid number though.
8746 case 0: // Branch on the value of the EQ bit of CR6.
8747 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8749 case 1: // Branch on the inverted value of the EQ bit of CR6.
8750 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8752 case 2: // Branch on the value of the LT bit of CR6.
8753 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8755 case 3: // Branch on the inverted value of the LT bit of CR6.
8756 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8760 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8761 DAG.getConstant(CompOpc, MVT::i32),
8762 DAG.getRegister(PPC::CR6, MVT::i32),
8763 N->getOperand(4), CompNode.getValue(1));
8772 //===----------------------------------------------------------------------===//
8773 // Inline Assembly Support
8774 //===----------------------------------------------------------------------===//
8776 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8779 const SelectionDAG &DAG,
8780 unsigned Depth) const {
8781 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8782 switch (Op.getOpcode()) {
8784 case PPCISD::LBRX: {
8785 // lhbrx is known to have the top bits cleared out.
8786 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8787 KnownZero = 0xFFFF0000;
8790 case ISD::INTRINSIC_WO_CHAIN: {
8791 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8793 case Intrinsic::ppc_altivec_vcmpbfp_p:
8794 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8795 case Intrinsic::ppc_altivec_vcmpequb_p:
8796 case Intrinsic::ppc_altivec_vcmpequh_p:
8797 case Intrinsic::ppc_altivec_vcmpequw_p:
8798 case Intrinsic::ppc_altivec_vcmpgefp_p:
8799 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8800 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8801 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8802 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8803 case Intrinsic::ppc_altivec_vcmpgtub_p:
8804 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8805 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8806 KnownZero = ~1U; // All bits but the low one are known to be zero.
8814 /// getConstraintType - Given a constraint, return the type of
8815 /// constraint it is for this target.
8816 PPCTargetLowering::ConstraintType
8817 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8818 if (Constraint.size() == 1) {
8819 switch (Constraint[0]) {
8826 return C_RegisterClass;
8828 // FIXME: While Z does indicate a memory constraint, it specifically
8829 // indicates an r+r address (used in conjunction with the 'y' modifier
8830 // in the replacement string). Currently, we're forcing the base
8831 // register to be r0 in the asm printer (which is interpreted as zero)
8832 // and forming the complete address in the second register. This is
8836 } else if (Constraint == "wc") { // individual CR bits.
8837 return C_RegisterClass;
8838 } else if (Constraint == "wa" || Constraint == "wd" ||
8839 Constraint == "wf" || Constraint == "ws") {
8840 return C_RegisterClass; // VSX registers.
8842 return TargetLowering::getConstraintType(Constraint);
8845 /// Examine constraint type and operand type and determine a weight value.
8846 /// This object must already have been set up with the operand type
8847 /// and the current alternative constraint selected.
8848 TargetLowering::ConstraintWeight
8849 PPCTargetLowering::getSingleConstraintMatchWeight(
8850 AsmOperandInfo &info, const char *constraint) const {
8851 ConstraintWeight weight = CW_Invalid;
8852 Value *CallOperandVal = info.CallOperandVal;
8853 // If we don't have a value, we can't do a match,
8854 // but allow it at the lowest weight.
8855 if (!CallOperandVal)
8857 Type *type = CallOperandVal->getType();
8859 // Look at the constraint type.
8860 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8861 return CW_Register; // an individual CR bit.
8862 else if ((StringRef(constraint) == "wa" ||
8863 StringRef(constraint) == "wd" ||
8864 StringRef(constraint) == "wf") &&
8867 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8870 switch (*constraint) {
8872 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8875 if (type->isIntegerTy())
8876 weight = CW_Register;
8879 if (type->isFloatTy())
8880 weight = CW_Register;
8883 if (type->isDoubleTy())
8884 weight = CW_Register;
8887 if (type->isVectorTy())
8888 weight = CW_Register;
8891 weight = CW_Register;
8900 std::pair<unsigned, const TargetRegisterClass*>
8901 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8903 if (Constraint.size() == 1) {
8904 // GCC RS6000 Constraint Letters
8905 switch (Constraint[0]) {
8907 if (VT == MVT::i64 && Subtarget.isPPC64())
8908 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8909 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8911 if (VT == MVT::i64 && Subtarget.isPPC64())
8912 return std::make_pair(0U, &PPC::G8RCRegClass);
8913 return std::make_pair(0U, &PPC::GPRCRegClass);
8915 if (VT == MVT::f32 || VT == MVT::i32)
8916 return std::make_pair(0U, &PPC::F4RCRegClass);
8917 if (VT == MVT::f64 || VT == MVT::i64)
8918 return std::make_pair(0U, &PPC::F8RCRegClass);
8921 return std::make_pair(0U, &PPC::VRRCRegClass);
8923 return std::make_pair(0U, &PPC::CRRCRegClass);
8925 } else if (Constraint == "wc") { // an individual CR bit.
8926 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8927 } else if (Constraint == "wa" || Constraint == "wd" ||
8928 Constraint == "wf") {
8929 return std::make_pair(0U, &PPC::VSRCRegClass);
8930 } else if (Constraint == "ws") {
8931 return std::make_pair(0U, &PPC::VSFRCRegClass);
8934 std::pair<unsigned, const TargetRegisterClass*> R =
8935 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8937 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8938 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8939 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8941 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8942 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8943 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8944 PPC::GPRCRegClass.contains(R.first)) {
8945 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8946 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8947 PPC::sub_32, &PPC::G8RCRegClass),
8948 &PPC::G8RCRegClass);
8955 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8956 /// vector. If it is invalid, don't add anything to Ops.
8957 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8958 std::string &Constraint,
8959 std::vector<SDValue>&Ops,
8960 SelectionDAG &DAG) const {
8963 // Only support length 1 constraints.
8964 if (Constraint.length() > 1) return;
8966 char Letter = Constraint[0];
8977 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8978 if (!CST) return; // Must be an immediate to match.
8979 unsigned Value = CST->getZExtValue();
8981 default: llvm_unreachable("Unknown constraint letter!");
8982 case 'I': // "I" is a signed 16-bit constant.
8983 if ((short)Value == (int)Value)
8984 Result = DAG.getTargetConstant(Value, Op.getValueType());
8986 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8987 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8988 if ((short)Value == 0)
8989 Result = DAG.getTargetConstant(Value, Op.getValueType());
8991 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8992 if ((Value >> 16) == 0)
8993 Result = DAG.getTargetConstant(Value, Op.getValueType());
8995 case 'M': // "M" is a constant that is greater than 31.
8997 Result = DAG.getTargetConstant(Value, Op.getValueType());
8999 case 'N': // "N" is a positive constant that is an exact power of two.
9000 if ((int)Value > 0 && isPowerOf2_32(Value))
9001 Result = DAG.getTargetConstant(Value, Op.getValueType());
9003 case 'O': // "O" is the constant zero.
9005 Result = DAG.getTargetConstant(Value, Op.getValueType());
9007 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9008 if ((short)-Value == (int)-Value)
9009 Result = DAG.getTargetConstant(Value, Op.getValueType());
9016 if (Result.getNode()) {
9017 Ops.push_back(Result);
9021 // Handle standard constraint letters.
9022 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9025 // isLegalAddressingMode - Return true if the addressing mode represented
9026 // by AM is legal for this target, for a load/store of the specified type.
9027 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9029 // FIXME: PPC does not allow r+i addressing modes for vectors!
9031 // PPC allows a sign-extended 16-bit immediate field.
9032 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9035 // No global is ever allowed as a base.
9039 // PPC only support r+r,
9041 case 0: // "r+i" or just "i", depending on HasBaseReg.
9044 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9046 // Otherwise we have r+r or r+i.
9049 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9051 // Allow 2*r as r+r.
9054 // No other scales are supported.
9061 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9062 SelectionDAG &DAG) const {
9063 MachineFunction &MF = DAG.getMachineFunction();
9064 MachineFrameInfo *MFI = MF.getFrameInfo();
9065 MFI->setReturnAddressIsTaken(true);
9067 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9071 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9073 // Make sure the function does not optimize away the store of the RA to
9075 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9076 FuncInfo->setLRStoreRequired();
9077 bool isPPC64 = Subtarget.isPPC64();
9078 bool isDarwinABI = Subtarget.isDarwinABI();
9081 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9084 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9085 isPPC64? MVT::i64 : MVT::i32);
9086 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9087 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9089 MachinePointerInfo(), false, false, false, 0);
9092 // Just load the return address off the stack.
9093 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9094 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9095 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9098 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9099 SelectionDAG &DAG) const {
9101 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9103 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9104 bool isPPC64 = PtrVT == MVT::i64;
9106 MachineFunction &MF = DAG.getMachineFunction();
9107 MachineFrameInfo *MFI = MF.getFrameInfo();
9108 MFI->setFrameAddressIsTaken(true);
9110 // Naked functions never have a frame pointer, and so we use r1. For all
9111 // other functions, this decision must be delayed until during PEI.
9113 if (MF.getFunction()->getAttributes().hasAttribute(
9114 AttributeSet::FunctionIndex, Attribute::Naked))
9115 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9117 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9119 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9122 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9123 FrameAddr, MachinePointerInfo(), false, false,
9128 // FIXME? Maybe this could be a TableGen attribute on some registers and
9129 // this table could be generated automatically from RegInfo.
9130 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9132 bool isPPC64 = Subtarget.isPPC64();
9133 bool isDarwinABI = Subtarget.isDarwinABI();
9135 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9136 (!isPPC64 && VT != MVT::i32))
9137 report_fatal_error("Invalid register global variable type");
9139 bool is64Bit = isPPC64 && VT == MVT::i64;
9140 unsigned Reg = StringSwitch<unsigned>(RegName)
9141 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9142 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9143 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9144 (is64Bit ? PPC::X13 : PPC::R13))
9149 report_fatal_error("Invalid register name global variable");
9153 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9154 // The PowerPC target isn't yet aware of offsets.
9158 /// getOptimalMemOpType - Returns the target specific optimal type for load
9159 /// and store operations as a result of memset, memcpy, and memmove
9160 /// lowering. If DstAlign is zero that means it's safe to destination
9161 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9162 /// means there isn't a need to check it against alignment requirement,
9163 /// probably because the source does not need to be loaded. If 'IsMemset' is
9164 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9165 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9166 /// source is constant so it does not need to be loaded.
9167 /// It returns EVT::Other if the type should be determined using generic
9168 /// target-independent logic.
9169 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9170 unsigned DstAlign, unsigned SrcAlign,
9171 bool IsMemset, bool ZeroMemset,
9173 MachineFunction &MF) const {
9174 if (Subtarget.isPPC64()) {
9181 /// \brief Returns true if it is beneficial to convert a load of a constant
9182 /// to just the constant itself.
9183 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9185 assert(Ty->isIntegerTy());
9187 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9188 if (BitSize == 0 || BitSize > 64)
9193 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9194 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9196 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9197 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9198 return NumBits1 == 64 && NumBits2 == 32;
9201 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9202 if (!VT1.isInteger() || !VT2.isInteger())
9204 unsigned NumBits1 = VT1.getSizeInBits();
9205 unsigned NumBits2 = VT2.getSizeInBits();
9206 return NumBits1 == 64 && NumBits2 == 32;
9209 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9210 return isInt<16>(Imm) || isUInt<16>(Imm);
9213 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9214 return isInt<16>(Imm) || isUInt<16>(Imm);
9217 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9221 if (DisablePPCUnaligned)
9224 // PowerPC supports unaligned memory access for simple non-vector types.
9225 // Although accessing unaligned addresses is not as efficient as accessing
9226 // aligned addresses, it is generally more efficient than manual expansion,
9227 // and generally only traps for software emulation when crossing page
9233 if (VT.getSimpleVT().isVector()) {
9234 if (Subtarget.hasVSX()) {
9235 if (VT != MVT::v2f64 && VT != MVT::v2i64)
9242 if (VT == MVT::ppcf128)
9251 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9252 VT = VT.getScalarType();
9257 switch (VT.getSimpleVT().SimpleTy) {
9269 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9270 EVT VT , unsigned DefinedValues) const {
9271 if (VT == MVT::v2i64)
9274 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9277 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9278 if (DisableILPPref || Subtarget.enableMachineScheduler())
9279 return TargetLowering::getSchedulingPreference(N);
9284 // Create a fast isel object.
9286 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9287 const TargetLibraryInfo *LibInfo) const {
9288 return PPC::createFastISel(FuncInfo, LibInfo);