1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
32 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc");
34 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
35 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
37 // Fold away setcc operations if possible.
38 setSetCCIsExpensive();
41 // Use _setjmp/_longjmp instead of setjmp/longjmp.
42 setUseUnderscoreSetJmpLongJmp(true);
44 // Set up the register classes.
45 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
46 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
47 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
49 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
50 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
51 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
53 // PowerPC does not have truncstore for i1.
54 setStoreXAction(MVT::i1, Promote);
56 // PowerPC has i32 and i64 pre-inc load and store's.
57 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
58 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
59 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
60 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
62 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
63 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
65 // PowerPC has no intrinsics for these particular operations
66 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
67 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
68 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
70 // PowerPC has no SREM/UREM instructions
71 setOperationAction(ISD::SREM, MVT::i32, Expand);
72 setOperationAction(ISD::UREM, MVT::i32, Expand);
73 setOperationAction(ISD::SREM, MVT::i64, Expand);
74 setOperationAction(ISD::UREM, MVT::i64, Expand);
76 // We don't support sin/cos/sqrt/fmod
77 setOperationAction(ISD::FSIN , MVT::f64, Expand);
78 setOperationAction(ISD::FCOS , MVT::f64, Expand);
79 setOperationAction(ISD::FREM , MVT::f64, Expand);
80 setOperationAction(ISD::FSIN , MVT::f32, Expand);
81 setOperationAction(ISD::FCOS , MVT::f32, Expand);
82 setOperationAction(ISD::FREM , MVT::f32, Expand);
84 // If we're enabling GP optimizations, use hardware square root
85 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
86 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
87 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
90 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
91 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
93 // PowerPC does not have BSWAP, CTPOP or CTTZ
94 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
95 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
96 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
97 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
98 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
99 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
101 // PowerPC does not have ROTR
102 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
104 // PowerPC does not have Select
105 setOperationAction(ISD::SELECT, MVT::i32, Expand);
106 setOperationAction(ISD::SELECT, MVT::i64, Expand);
107 setOperationAction(ISD::SELECT, MVT::f32, Expand);
108 setOperationAction(ISD::SELECT, MVT::f64, Expand);
110 // PowerPC wants to turn select_cc of FP into fsel when possible.
111 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
112 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
114 // PowerPC wants to optimize integer setcc a bit
115 setOperationAction(ISD::SETCC, MVT::i32, Custom);
117 // PowerPC does not have BRCOND which requires SetCC
118 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
120 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
122 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
123 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
125 // PowerPC does not have [U|S]INT_TO_FP
126 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
127 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
129 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
130 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
131 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
132 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
134 // We cannot sextinreg(i1). Expand to shifts.
135 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
138 // Support label based line numbers.
139 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
140 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
141 // FIXME - use subtarget debug flags
142 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
143 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
145 // We want to legalize GlobalAddress and ConstantPool nodes into the
146 // appropriate instructions to materialize the address.
147 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
148 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
149 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
150 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
151 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
152 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
154 // RET must be custom lowered, to meet ABI requirements
155 setOperationAction(ISD::RET , MVT::Other, Custom);
157 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
158 setOperationAction(ISD::VASTART , MVT::Other, Custom);
160 // Use the default implementation.
161 setOperationAction(ISD::VAARG , MVT::Other, Expand);
162 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
163 setOperationAction(ISD::VAEND , MVT::Other, Expand);
164 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
165 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
166 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
167 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
169 // We want to custom lower some of our intrinsics.
170 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
172 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
173 // They also have instructions for converting between i64 and fp.
174 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
175 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
177 // FIXME: disable this lowered code. This generates 64-bit register values,
178 // and we don't model the fact that the top part is clobbered by calls. We
179 // need to flag these together so that the value isn't live across a call.
180 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
182 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
183 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
185 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
186 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
189 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
190 // 64 bit PowerPC implementations can support i64 types directly
191 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
192 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
193 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
195 // 32 bit PowerPC wants to expand i64 shifts itself.
196 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
197 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
198 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
201 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
202 // First set operation action for all vector types to expand. Then we
203 // will selectively turn on ones that can be effectively codegen'd.
204 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
205 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
206 // add/sub are legal for all supported vector VT's.
207 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
208 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
210 // We promote all shuffles to v16i8.
211 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
212 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
214 // We promote all non-typed operations to v4i32.
215 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
216 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
217 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
218 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
219 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
220 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
221 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
222 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
223 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
224 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
225 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
226 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
228 // No other operations are legal.
229 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
230 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
231 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
232 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
233 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
234 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
235 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
236 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
237 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
239 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
242 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
243 // with merges, splats, etc.
244 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
246 setOperationAction(ISD::AND , MVT::v4i32, Legal);
247 setOperationAction(ISD::OR , MVT::v4i32, Legal);
248 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
249 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
250 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
251 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
253 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
254 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
255 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
256 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
258 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
259 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
260 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
261 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
263 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
264 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
266 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
267 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
268 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
269 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
272 setSetCCResultType(MVT::i32);
273 setShiftAmountType(MVT::i32);
274 setSetCCResultContents(ZeroOrOneSetCCResult);
276 if (TM.getSubtarget<PPCSubtarget>().isPPC64())
277 setStackPointerRegisterToSaveRestore(PPC::X1);
279 setStackPointerRegisterToSaveRestore(PPC::R1);
281 // We have target-specific dag combine patterns for the following nodes:
282 setTargetDAGCombine(ISD::SINT_TO_FP);
283 setTargetDAGCombine(ISD::STORE);
284 setTargetDAGCombine(ISD::BR_CC);
285 setTargetDAGCombine(ISD::BSWAP);
287 computeRegisterProperties();
290 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
293 case PPCISD::FSEL: return "PPCISD::FSEL";
294 case PPCISD::FCFID: return "PPCISD::FCFID";
295 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
296 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
297 case PPCISD::STFIWX: return "PPCISD::STFIWX";
298 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
299 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
300 case PPCISD::VPERM: return "PPCISD::VPERM";
301 case PPCISD::Hi: return "PPCISD::Hi";
302 case PPCISD::Lo: return "PPCISD::Lo";
303 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
304 case PPCISD::SRL: return "PPCISD::SRL";
305 case PPCISD::SRA: return "PPCISD::SRA";
306 case PPCISD::SHL: return "PPCISD::SHL";
307 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
308 case PPCISD::STD_32: return "PPCISD::STD_32";
309 case PPCISD::CALL: return "PPCISD::CALL";
310 case PPCISD::MTCTR: return "PPCISD::MTCTR";
311 case PPCISD::BCTRL: return "PPCISD::BCTRL";
312 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
313 case PPCISD::MFCR: return "PPCISD::MFCR";
314 case PPCISD::VCMP: return "PPCISD::VCMP";
315 case PPCISD::VCMPo: return "PPCISD::VCMPo";
316 case PPCISD::LBRX: return "PPCISD::LBRX";
317 case PPCISD::STBRX: return "PPCISD::STBRX";
318 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
322 //===----------------------------------------------------------------------===//
323 // Node matching predicates, for use by the tblgen matching code.
324 //===----------------------------------------------------------------------===//
326 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
327 static bool isFloatingPointZero(SDOperand Op) {
328 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
329 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
330 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
331 // Maybe this has already been legalized into the constant pool?
332 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
333 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
334 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
339 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
340 /// true if Op is undef or if it matches the specified value.
341 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
342 return Op.getOpcode() == ISD::UNDEF ||
343 cast<ConstantSDNode>(Op)->getValue() == Val;
346 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
347 /// VPKUHUM instruction.
348 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
350 for (unsigned i = 0; i != 16; ++i)
351 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
354 for (unsigned i = 0; i != 8; ++i)
355 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
356 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
362 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
363 /// VPKUWUM instruction.
364 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
366 for (unsigned i = 0; i != 16; i += 2)
367 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
368 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
371 for (unsigned i = 0; i != 8; i += 2)
372 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
373 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
374 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
375 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
381 /// isVMerge - Common function, used to match vmrg* shuffles.
383 static bool isVMerge(SDNode *N, unsigned UnitSize,
384 unsigned LHSStart, unsigned RHSStart) {
385 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
386 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
387 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
388 "Unsupported merge size!");
390 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
391 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
392 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
393 LHSStart+j+i*UnitSize) ||
394 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
395 RHSStart+j+i*UnitSize))
401 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
402 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
403 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
405 return isVMerge(N, UnitSize, 8, 24);
406 return isVMerge(N, UnitSize, 8, 8);
409 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
410 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
411 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
413 return isVMerge(N, UnitSize, 0, 16);
414 return isVMerge(N, UnitSize, 0, 0);
418 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
419 /// amount, otherwise return -1.
420 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
421 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
422 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
423 // Find the first non-undef value in the shuffle mask.
425 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
428 if (i == 16) return -1; // all undef.
430 // Otherwise, check to see if the rest of the elements are consequtively
431 // numbered from this value.
432 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
433 if (ShiftAmt < i) return -1;
437 // Check the rest of the elements to see if they are consequtive.
438 for (++i; i != 16; ++i)
439 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
442 // Check the rest of the elements to see if they are consequtive.
443 for (++i; i != 16; ++i)
444 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
451 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
452 /// specifies a splat of a single element that is suitable for input to
453 /// VSPLTB/VSPLTH/VSPLTW.
454 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
455 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
456 N->getNumOperands() == 16 &&
457 (EltSize == 1 || EltSize == 2 || EltSize == 4));
459 // This is a splat operation if each element of the permute is the same, and
460 // if the value doesn't reference the second vector.
461 unsigned ElementBase = 0;
462 SDOperand Elt = N->getOperand(0);
463 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
464 ElementBase = EltV->getValue();
466 return false; // FIXME: Handle UNDEF elements too!
468 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
471 // Check that they are consequtive.
472 for (unsigned i = 1; i != EltSize; ++i) {
473 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
474 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
478 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
479 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
480 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
481 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
482 "Invalid VECTOR_SHUFFLE mask!");
483 for (unsigned j = 0; j != EltSize; ++j)
484 if (N->getOperand(i+j) != N->getOperand(j))
491 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
492 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
493 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
494 assert(isSplatShuffleMask(N, EltSize));
495 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
498 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
499 /// by using a vspltis[bhw] instruction of the specified element size, return
500 /// the constant being splatted. The ByteSize field indicates the number of
501 /// bytes of each element [124] -> [bhw].
502 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
503 SDOperand OpVal(0, 0);
505 // If ByteSize of the splat is bigger than the element size of the
506 // build_vector, then we have a case where we are checking for a splat where
507 // multiple elements of the buildvector are folded together into a single
508 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
509 unsigned EltSize = 16/N->getNumOperands();
510 if (EltSize < ByteSize) {
511 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
512 SDOperand UniquedVals[4];
513 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
515 // See if all of the elements in the buildvector agree across.
516 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
517 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
518 // If the element isn't a constant, bail fully out.
519 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
522 if (UniquedVals[i&(Multiple-1)].Val == 0)
523 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
524 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
525 return SDOperand(); // no match.
528 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
529 // either constant or undef values that are identical for each chunk. See
530 // if these chunks can form into a larger vspltis*.
532 // Check to see if all of the leading entries are either 0 or -1. If
533 // neither, then this won't fit into the immediate field.
534 bool LeadingZero = true;
535 bool LeadingOnes = true;
536 for (unsigned i = 0; i != Multiple-1; ++i) {
537 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
539 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
540 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
542 // Finally, check the least significant entry.
544 if (UniquedVals[Multiple-1].Val == 0)
545 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
546 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
548 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
551 if (UniquedVals[Multiple-1].Val == 0)
552 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
553 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
554 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
555 return DAG.getTargetConstant(Val, MVT::i32);
561 // Check to see if this buildvec has a single non-undef value in its elements.
562 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
563 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
565 OpVal = N->getOperand(i);
566 else if (OpVal != N->getOperand(i))
570 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
572 unsigned ValSizeInBytes = 0;
574 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
575 Value = CN->getValue();
576 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
577 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
578 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
579 Value = FloatToBits(CN->getValue());
583 // If the splat value is larger than the element value, then we can never do
584 // this splat. The only case that we could fit the replicated bits into our
585 // immediate field for would be zero, and we prefer to use vxor for it.
586 if (ValSizeInBytes < ByteSize) return SDOperand();
588 // If the element value is larger than the splat value, cut it in half and
589 // check to see if the two halves are equal. Continue doing this until we
590 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
591 while (ValSizeInBytes > ByteSize) {
592 ValSizeInBytes >>= 1;
594 // If the top half equals the bottom half, we're still ok.
595 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
596 (Value & ((1 << (8*ValSizeInBytes))-1)))
600 // Properly sign extend the value.
601 int ShAmt = (4-ByteSize)*8;
602 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
604 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
605 if (MaskVal == 0) return SDOperand();
607 // Finally, if this value fits in a 5 bit sext field, return it
608 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
609 return DAG.getTargetConstant(MaskVal, MVT::i32);
613 //===----------------------------------------------------------------------===//
614 // Addressing Mode Selection
615 //===----------------------------------------------------------------------===//
617 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
618 /// or 64-bit immediate, and if the value can be accurately represented as a
619 /// sign extension from a 16-bit value. If so, this returns true and the
621 static bool isIntS16Immediate(SDNode *N, short &Imm) {
622 if (N->getOpcode() != ISD::Constant)
625 Imm = (short)cast<ConstantSDNode>(N)->getValue();
626 if (N->getValueType(0) == MVT::i32)
627 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
629 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
631 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
632 return isIntS16Immediate(Op.Val, Imm);
636 /// SelectAddressRegReg - Given the specified addressed, check to see if it
637 /// can be represented as an indexed [r+r] operation. Returns false if it
638 /// can be more efficiently represented with [r+imm].
639 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
643 if (N.getOpcode() == ISD::ADD) {
644 if (isIntS16Immediate(N.getOperand(1), imm))
646 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
649 Base = N.getOperand(0);
650 Index = N.getOperand(1);
652 } else if (N.getOpcode() == ISD::OR) {
653 if (isIntS16Immediate(N.getOperand(1), imm))
654 return false; // r+i can fold it if we can.
656 // If this is an or of disjoint bitfields, we can codegen this as an add
657 // (for better address arithmetic) if the LHS and RHS of the OR are provably
659 uint64_t LHSKnownZero, LHSKnownOne;
660 uint64_t RHSKnownZero, RHSKnownOne;
661 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
664 ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
665 // If all of the bits are known zero on the LHS or RHS, the add won't
667 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
668 Base = N.getOperand(0);
669 Index = N.getOperand(1);
678 /// Returns true if the address N can be represented by a base register plus
679 /// a signed 16-bit displacement [r+imm], and if it is not better
680 /// represented as reg+reg.
681 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
682 SDOperand &Base, SelectionDAG &DAG){
683 // If this can be more profitably realized as r+r, fail.
684 if (SelectAddressRegReg(N, Disp, Base, DAG))
687 if (N.getOpcode() == ISD::ADD) {
689 if (isIntS16Immediate(N.getOperand(1), imm)) {
690 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
691 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
692 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
694 Base = N.getOperand(0);
696 return true; // [r+i]
697 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
698 // Match LOAD (ADD (X, Lo(G))).
699 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
700 && "Cannot handle constant offsets yet!");
701 Disp = N.getOperand(1).getOperand(0); // The global address.
702 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
703 Disp.getOpcode() == ISD::TargetConstantPool ||
704 Disp.getOpcode() == ISD::TargetJumpTable);
705 Base = N.getOperand(0);
706 return true; // [&g+r]
708 } else if (N.getOpcode() == ISD::OR) {
710 if (isIntS16Immediate(N.getOperand(1), imm)) {
711 // If this is an or of disjoint bitfields, we can codegen this as an add
712 // (for better address arithmetic) if the LHS and RHS of the OR are
713 // provably disjoint.
714 uint64_t LHSKnownZero, LHSKnownOne;
715 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
716 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
717 // If all of the bits are known zero on the LHS or RHS, the add won't
719 Base = N.getOperand(0);
720 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
724 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
725 // Loading from a constant address.
727 // If this address fits entirely in a 16-bit sext immediate field, codegen
730 if (isIntS16Immediate(CN, Imm)) {
731 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
732 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
736 // FIXME: Handle small sext constant offsets in PPC64 mode also!
737 if (CN->getValueType(0) == MVT::i32) {
738 int Addr = (int)CN->getValue();
740 // Otherwise, break this down into an LIS + disp.
741 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
742 Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
747 Disp = DAG.getTargetConstant(0, getPointerTy());
748 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
749 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
752 return true; // [r+0]
755 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
756 /// represented as an indexed [r+r] operation.
757 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
760 // Check to see if we can easily represent this as an [r+r] address. This
761 // will fail if it thinks that the address is more profitably represented as
762 // reg+imm, e.g. where imm = 0.
763 if (SelectAddressRegReg(N, Base, Index, DAG))
766 // If the operand is an addition, always emit this as [r+r], since this is
767 // better (for code size, and execution, as the memop does the add for free)
768 // than emitting an explicit add.
769 if (N.getOpcode() == ISD::ADD) {
770 Base = N.getOperand(0);
771 Index = N.getOperand(1);
775 // Otherwise, do it the hard way, using R0 as the base register.
776 Base = DAG.getRegister(PPC::R0, N.getValueType());
781 /// SelectAddressRegImmShift - Returns true if the address N can be
782 /// represented by a base register plus a signed 14-bit displacement
783 /// [r+imm*4]. Suitable for use by STD and friends.
784 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
787 // If this can be more profitably realized as r+r, fail.
788 if (SelectAddressRegReg(N, Disp, Base, DAG))
791 if (N.getOpcode() == ISD::ADD) {
793 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
794 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
795 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
796 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
798 Base = N.getOperand(0);
800 return true; // [r+i]
801 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
802 // Match LOAD (ADD (X, Lo(G))).
803 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
804 && "Cannot handle constant offsets yet!");
805 Disp = N.getOperand(1).getOperand(0); // The global address.
806 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
807 Disp.getOpcode() == ISD::TargetConstantPool ||
808 Disp.getOpcode() == ISD::TargetJumpTable);
809 Base = N.getOperand(0);
810 return true; // [&g+r]
812 } else if (N.getOpcode() == ISD::OR) {
814 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
815 // If this is an or of disjoint bitfields, we can codegen this as an add
816 // (for better address arithmetic) if the LHS and RHS of the OR are
817 // provably disjoint.
818 uint64_t LHSKnownZero, LHSKnownOne;
819 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
820 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
821 // If all of the bits are known zero on the LHS or RHS, the add won't
823 Base = N.getOperand(0);
824 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
828 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
829 // Loading from a constant address.
831 // If this address fits entirely in a 14-bit sext immediate field, codegen
834 if (isIntS16Immediate(CN, Imm)) {
835 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
836 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
840 // FIXME: Handle small sext constant offsets in PPC64 mode also!
841 if (CN->getValueType(0) == MVT::i32) {
842 int Addr = (int)CN->getValue();
844 // Otherwise, break this down into an LIS + disp.
845 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
846 Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
851 Disp = DAG.getTargetConstant(0, getPointerTy());
852 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
853 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
856 return true; // [r+0]
860 /// getPreIndexedAddressParts - returns true by value, base pointer and
861 /// offset pointer and addressing mode by reference if the node's address
862 /// can be legally represented as pre-indexed load / store address.
863 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
865 ISD::MemIndexedMode &AM,
867 // Disabled by default for now.
868 if (!EnablePPCPreinc) return false;
871 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
872 Ptr = LD->getBasePtr();
873 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
875 //Ptr = ST->getBasePtr();
876 //VT = ST->getStoredVT();
877 // TODO: handle stores.
882 // TODO: Handle reg+reg.
883 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
890 //===----------------------------------------------------------------------===//
891 // LowerOperation implementation
892 //===----------------------------------------------------------------------===//
894 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
895 MVT::ValueType PtrVT = Op.getValueType();
896 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
897 Constant *C = CP->getConstVal();
898 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
899 SDOperand Zero = DAG.getConstant(0, PtrVT);
901 const TargetMachine &TM = DAG.getTarget();
903 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
904 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
906 // If this is a non-darwin platform, we don't support non-static relo models
908 if (TM.getRelocationModel() == Reloc::Static ||
909 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
910 // Generate non-pic code that has direct accesses to the constant pool.
911 // The address of the global is just (hi(&g)+lo(&g)).
912 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
915 if (TM.getRelocationModel() == Reloc::PIC_) {
916 // With PIC, the first instruction is actually "GR+hi(&G)".
917 Hi = DAG.getNode(ISD::ADD, PtrVT,
918 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
921 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
925 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
926 MVT::ValueType PtrVT = Op.getValueType();
927 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
928 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
929 SDOperand Zero = DAG.getConstant(0, PtrVT);
931 const TargetMachine &TM = DAG.getTarget();
933 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
934 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
936 // If this is a non-darwin platform, we don't support non-static relo models
938 if (TM.getRelocationModel() == Reloc::Static ||
939 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
940 // Generate non-pic code that has direct accesses to the constant pool.
941 // The address of the global is just (hi(&g)+lo(&g)).
942 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
945 if (TM.getRelocationModel() == Reloc::PIC_) {
946 // With PIC, the first instruction is actually "GR+hi(&G)".
947 Hi = DAG.getNode(ISD::ADD, PtrVT,
948 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
951 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
955 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
956 MVT::ValueType PtrVT = Op.getValueType();
957 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
958 GlobalValue *GV = GSDN->getGlobal();
959 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
960 SDOperand Zero = DAG.getConstant(0, PtrVT);
962 const TargetMachine &TM = DAG.getTarget();
964 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
965 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
967 // If this is a non-darwin platform, we don't support non-static relo models
969 if (TM.getRelocationModel() == Reloc::Static ||
970 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
971 // Generate non-pic code that has direct accesses to globals.
972 // The address of the global is just (hi(&g)+lo(&g)).
973 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
976 if (TM.getRelocationModel() == Reloc::PIC_) {
977 // With PIC, the first instruction is actually "GR+hi(&G)".
978 Hi = DAG.getNode(ISD::ADD, PtrVT,
979 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
982 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
984 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
985 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
988 // If the global is weak or external, we have to go through the lazy
990 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
993 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
994 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
996 // If we're comparing for equality to zero, expose the fact that this is
997 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
998 // fold the new nodes.
999 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1000 if (C->isNullValue() && CC == ISD::SETEQ) {
1001 MVT::ValueType VT = Op.getOperand(0).getValueType();
1002 SDOperand Zext = Op.getOperand(0);
1003 if (VT < MVT::i32) {
1005 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1007 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1008 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1009 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1010 DAG.getConstant(Log2b, MVT::i32));
1011 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1013 // Leave comparisons against 0 and -1 alone for now, since they're usually
1014 // optimized. FIXME: revisit this when we can custom lower all setcc
1016 if (C->isAllOnesValue() || C->isNullValue())
1020 // If we have an integer seteq/setne, turn it into a compare against zero
1021 // by subtracting the rhs from the lhs, which is faster than setting a
1022 // condition register, reading it back out, and masking the correct bit.
1023 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1024 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1025 MVT::ValueType VT = Op.getValueType();
1026 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
1028 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1033 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1034 unsigned VarArgsFrameIndex) {
1035 // vastart just stores the address of the VarArgsFrameIndex slot into the
1036 // memory location argument.
1037 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1038 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1039 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1040 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
1044 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1045 int &VarArgsFrameIndex) {
1046 // TODO: add description of PPC stack frame format, or at least some docs.
1048 MachineFunction &MF = DAG.getMachineFunction();
1049 MachineFrameInfo *MFI = MF.getFrameInfo();
1050 SSARegMap *RegMap = MF.getSSARegMap();
1051 SmallVector<SDOperand, 8> ArgValues;
1052 SDOperand Root = Op.getOperand(0);
1054 unsigned ArgOffset = 24;
1055 const unsigned Num_GPR_Regs = 8;
1056 const unsigned Num_FPR_Regs = 13;
1057 const unsigned Num_VR_Regs = 12;
1058 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1060 static const unsigned GPR_32[] = { // 32-bit registers.
1061 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1062 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1064 static const unsigned GPR_64[] = { // 64-bit registers.
1065 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1066 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1068 static const unsigned FPR[] = {
1069 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1070 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1072 static const unsigned VR[] = {
1073 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1074 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1077 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1078 bool isPPC64 = PtrVT == MVT::i64;
1079 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1081 // Add DAG nodes to load the arguments or copy them out of registers. On
1082 // entry to a function on PPC, the arguments start at offset 24, although the
1083 // first ones are often in registers.
1084 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1086 bool needsLoad = false;
1087 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1088 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1090 unsigned CurArgOffset = ArgOffset;
1092 default: assert(0 && "Unhandled argument type!");
1094 // All int arguments reserve stack space.
1095 ArgOffset += isPPC64 ? 8 : 4;
1097 if (GPR_idx != Num_GPR_Regs) {
1098 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1099 MF.addLiveIn(GPR[GPR_idx], VReg);
1100 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1106 case MVT::i64: // PPC64
1107 // All int arguments reserve stack space.
1110 if (GPR_idx != Num_GPR_Regs) {
1111 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1112 MF.addLiveIn(GPR[GPR_idx], VReg);
1113 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1121 // All FP arguments reserve stack space.
1122 ArgOffset += ObjSize;
1124 // Every 4 bytes of argument space consumes one of the GPRs available for
1125 // argument passing.
1126 if (GPR_idx != Num_GPR_Regs) {
1128 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs)
1131 if (FPR_idx != Num_FPR_Regs) {
1133 if (ObjectVT == MVT::f32)
1134 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1136 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1137 MF.addLiveIn(FPR[FPR_idx], VReg);
1138 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1148 // Note that vector arguments in registers don't reserve stack space.
1149 if (VR_idx != Num_VR_Regs) {
1150 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
1151 MF.addLiveIn(VR[VR_idx], VReg);
1152 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1155 // This should be simple, but requires getting 16-byte aligned stack
1157 assert(0 && "Loading VR argument not implemented yet!");
1163 // We need to load the argument to a virtual register if we determined above
1164 // that we ran out of physical registers of the appropriate type
1166 // If the argument is actually used, emit a load from the right stack
1168 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1169 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1170 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1171 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1173 // Don't emit a dead load.
1174 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1178 ArgValues.push_back(ArgVal);
1181 // If the function takes variable number of arguments, make a frame index for
1182 // the start of the first vararg value... for expansion of llvm.va_start.
1183 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1185 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1187 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1188 // If this function is vararg, store any remaining integer argument regs
1189 // to their spots on the stack so that they may be loaded by deferencing the
1190 // result of va_next.
1191 SmallVector<SDOperand, 8> MemOps;
1192 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1193 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1194 MF.addLiveIn(GPR[GPR_idx], VReg);
1195 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1196 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1197 MemOps.push_back(Store);
1198 // Increment the address by four for the next argument to store
1199 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1200 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1202 if (!MemOps.empty())
1203 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1206 ArgValues.push_back(Root);
1208 // Return the new list of results.
1209 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1210 Op.Val->value_end());
1211 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1214 /// isCallCompatibleAddress - Return the immediate to use if the specified
1215 /// 32-bit value is representable in the immediate field of a BxA instruction.
1216 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1217 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1220 int Addr = C->getValue();
1221 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1222 (Addr << 6 >> 6) != Addr)
1223 return 0; // Top 6 bits have to be sext of immediate.
1225 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
1229 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1230 SDOperand Chain = Op.getOperand(0);
1231 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1232 SDOperand Callee = Op.getOperand(4);
1233 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1235 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1236 bool isPPC64 = PtrVT == MVT::i64;
1237 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1240 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1241 // SelectExpr to use to put the arguments in the appropriate registers.
1242 std::vector<SDOperand> args_to_use;
1244 // Count how many bytes are to be pushed on the stack, including the linkage
1245 // area, and parameter passing area. We start with 24/48 bytes, which is
1246 // prereserved space for [SP][CR][LR][3 x unused].
1247 unsigned NumBytes = 6*PtrByteSize;
1249 // Add up all the space actually used.
1250 for (unsigned i = 0; i != NumOps; ++i)
1251 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1253 // The prolog code of the callee may store up to 8 GPR argument registers to
1254 // the stack, allowing va_start to index over them in memory if its varargs.
1255 // Because we cannot tell if this is needed on the caller side, we have to
1256 // conservatively assume that it is needed. As such, make sure we have at
1257 // least enough stack space for the caller to store the 8 GPRs.
1258 if (NumBytes < 6*PtrByteSize+8*PtrByteSize)
1259 NumBytes = 6*PtrByteSize+8*PtrByteSize;
1261 // Adjust the stack pointer for the new arguments...
1262 // These operations are automatically eliminated by the prolog/epilog pass
1263 Chain = DAG.getCALLSEQ_START(Chain,
1264 DAG.getConstant(NumBytes, PtrVT));
1266 // Set up a copy of the stack pointer for use loading and storing any
1267 // arguments that may not fit in the registers available for argument
1271 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1273 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1275 // Figure out which arguments are going to go in registers, and which in
1276 // memory. Also, if this is a vararg function, floating point operations
1277 // must be stored to our stack, and loaded into integer regs as well, if
1278 // any integer regs are available for argument passing.
1279 unsigned ArgOffset = 6*PtrByteSize;
1280 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1281 static const unsigned GPR_32[] = { // 32-bit registers.
1282 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1283 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1285 static const unsigned GPR_64[] = { // 64-bit registers.
1286 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1287 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1289 static const unsigned FPR[] = {
1290 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1291 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1293 static const unsigned VR[] = {
1294 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1295 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1297 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1298 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]);
1299 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
1301 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1303 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1304 SmallVector<SDOperand, 8> MemOpChains;
1305 for (unsigned i = 0; i != NumOps; ++i) {
1306 SDOperand Arg = Op.getOperand(5+2*i);
1308 // PtrOff will be used to store the current argument to the stack if a
1309 // register cannot be found for it.
1310 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1311 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1313 // On PPC64, promote integers to 64-bit values.
1314 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1315 unsigned ExtOp = ISD::ZERO_EXTEND;
1316 if (cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue())
1317 ExtOp = ISD::SIGN_EXTEND;
1318 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1321 switch (Arg.getValueType()) {
1322 default: assert(0 && "Unexpected ValueType for argument!");
1325 if (GPR_idx != NumGPRs) {
1326 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1328 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1330 ArgOffset += PtrByteSize;
1334 if (FPR_idx != NumFPRs) {
1335 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1338 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1339 MemOpChains.push_back(Store);
1341 // Float varargs are always shadowed in available integer registers
1342 if (GPR_idx != NumGPRs) {
1343 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1344 MemOpChains.push_back(Load.getValue(1));
1345 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1347 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
1348 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1349 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1350 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1351 MemOpChains.push_back(Load.getValue(1));
1352 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1355 // If we have any FPRs remaining, we may also have GPRs remaining.
1356 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1358 if (GPR_idx != NumGPRs)
1360 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64)
1364 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1369 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1375 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1376 assert(VR_idx != NumVRs &&
1377 "Don't support passing more than 12 vector args yet!");
1378 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1382 if (!MemOpChains.empty())
1383 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1384 &MemOpChains[0], MemOpChains.size());
1386 // Build a sequence of copy-to-reg nodes chained together with token chain
1387 // and flag operands which copy the outgoing args into the appropriate regs.
1389 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1390 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1392 InFlag = Chain.getValue(1);
1395 std::vector<MVT::ValueType> NodeTys;
1396 NodeTys.push_back(MVT::Other); // Returns a chain
1397 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1399 SmallVector<SDOperand, 8> Ops;
1400 unsigned CallOpc = PPCISD::CALL;
1402 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1403 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1404 // node so that legalize doesn't hack it.
1405 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1406 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1407 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1408 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1409 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1410 // If this is an absolute destination address, use the munged value.
1411 Callee = SDOperand(Dest, 0);
1413 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1414 // to do the call, we can't use PPCISD::CALL.
1415 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1416 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1417 InFlag = Chain.getValue(1);
1419 // Copy the callee address into R12 on darwin.
1420 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1421 InFlag = Chain.getValue(1);
1424 NodeTys.push_back(MVT::Other);
1425 NodeTys.push_back(MVT::Flag);
1426 Ops.push_back(Chain);
1427 CallOpc = PPCISD::BCTRL;
1431 // If this is a direct call, pass the chain and the callee.
1433 Ops.push_back(Chain);
1434 Ops.push_back(Callee);
1437 // Add argument registers to the end of the list so that they are known live
1439 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1440 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1441 RegsToPass[i].second.getValueType()));
1444 Ops.push_back(InFlag);
1445 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1446 InFlag = Chain.getValue(1);
1448 SDOperand ResultVals[3];
1449 unsigned NumResults = 0;
1452 // If the call has results, copy the values out of the ret val registers.
1453 switch (Op.Val->getValueType(0)) {
1454 default: assert(0 && "Unexpected ret value!");
1455 case MVT::Other: break;
1457 if (Op.Val->getValueType(1) == MVT::i32) {
1458 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1459 ResultVals[0] = Chain.getValue(0);
1460 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1461 Chain.getValue(2)).getValue(1);
1462 ResultVals[1] = Chain.getValue(0);
1464 NodeTys.push_back(MVT::i32);
1466 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1467 ResultVals[0] = Chain.getValue(0);
1470 NodeTys.push_back(MVT::i32);
1473 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1474 ResultVals[0] = Chain.getValue(0);
1476 NodeTys.push_back(MVT::i64);
1480 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1481 InFlag).getValue(1);
1482 ResultVals[0] = Chain.getValue(0);
1484 NodeTys.push_back(Op.Val->getValueType(0));
1490 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1491 InFlag).getValue(1);
1492 ResultVals[0] = Chain.getValue(0);
1494 NodeTys.push_back(Op.Val->getValueType(0));
1498 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1499 DAG.getConstant(NumBytes, PtrVT));
1500 NodeTys.push_back(MVT::Other);
1502 // If the function returns void, just return the chain.
1503 if (NumResults == 0)
1506 // Otherwise, merge everything together with a MERGE_VALUES node.
1507 ResultVals[NumResults++] = Chain;
1508 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1509 ResultVals, NumResults);
1510 return Res.getValue(Op.ResNo);
1513 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
1515 switch(Op.getNumOperands()) {
1517 assert(0 && "Do not know how to return this many arguments!");
1520 return SDOperand(); // ret void is legal
1522 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1524 if (ArgVT == MVT::i32) {
1526 } else if (ArgVT == MVT::i64) {
1528 } else if (MVT::isVector(ArgVT)) {
1531 assert(MVT::isFloatingPoint(ArgVT));
1535 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
1538 // If we haven't noted the R3/F1 are live out, do so now.
1539 if (DAG.getMachineFunction().liveout_empty())
1540 DAG.getMachineFunction().addLiveOut(ArgReg);
1544 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
1546 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
1547 // If we haven't noted the R3+R4 are live out, do so now.
1548 if (DAG.getMachineFunction().liveout_empty()) {
1549 DAG.getMachineFunction().addLiveOut(PPC::R3);
1550 DAG.getMachineFunction().addLiveOut(PPC::R4);
1554 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
1557 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1559 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1560 // Not FP? Not a fsel.
1561 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1562 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1565 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1567 // Cannot handle SETEQ/SETNE.
1568 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1570 MVT::ValueType ResVT = Op.getValueType();
1571 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1572 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1573 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1575 // If the RHS of the comparison is a 0.0, we don't need to do the
1576 // subtraction at all.
1577 if (isFloatingPointZero(RHS))
1579 default: break; // SETUO etc aren't handled by fsel.
1583 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1587 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1588 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1589 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1593 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1597 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1598 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1599 return DAG.getNode(PPCISD::FSEL, ResVT,
1600 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1605 default: break; // SETUO etc aren't handled by fsel.
1609 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1610 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1611 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1612 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1616 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1617 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1618 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1619 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1623 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1624 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1625 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1626 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1630 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1631 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1632 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1633 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1638 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1639 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1640 SDOperand Src = Op.getOperand(0);
1641 if (Src.getValueType() == MVT::f32)
1642 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1645 switch (Op.getValueType()) {
1646 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1648 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1651 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1655 // Convert the FP value to an int value through memory.
1656 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1657 if (Op.getValueType() == MVT::i32)
1658 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1662 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1663 if (Op.getOperand(0).getValueType() == MVT::i64) {
1664 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1665 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1666 if (Op.getValueType() == MVT::f32)
1667 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1671 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1672 "Unhandled SINT_TO_FP type in custom expander!");
1673 // Since we only generate this in 64-bit mode, we can take advantage of
1674 // 64-bit registers. In particular, sign extend the input value into the
1675 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1676 // then lfd it and fcfid it.
1677 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1678 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1679 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1680 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
1682 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1685 // STD the extended value into the stack slot.
1686 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1687 DAG.getEntryNode(), Ext64, FIdx,
1688 DAG.getSrcValue(NULL));
1689 // Load the value as a double.
1690 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
1692 // FCFID it and return it.
1693 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1694 if (Op.getValueType() == MVT::f32)
1695 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1699 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
1700 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1701 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1703 // Expand into a bunch of logical ops. Note that these ops
1704 // depend on the PPC behavior for oversized shift amounts.
1705 SDOperand Lo = Op.getOperand(0);
1706 SDOperand Hi = Op.getOperand(1);
1707 SDOperand Amt = Op.getOperand(2);
1709 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1710 DAG.getConstant(32, MVT::i32), Amt);
1711 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1712 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1713 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1714 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1715 DAG.getConstant(-32U, MVT::i32));
1716 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1717 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1718 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1719 SDOperand OutOps[] = { OutLo, OutHi };
1720 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1724 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
1725 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1726 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
1728 // Otherwise, expand into a bunch of logical ops. Note that these ops
1729 // depend on the PPC behavior for oversized shift amounts.
1730 SDOperand Lo = Op.getOperand(0);
1731 SDOperand Hi = Op.getOperand(1);
1732 SDOperand Amt = Op.getOperand(2);
1734 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1735 DAG.getConstant(32, MVT::i32), Amt);
1736 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1737 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1738 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1739 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1740 DAG.getConstant(-32U, MVT::i32));
1741 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1742 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1743 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1744 SDOperand OutOps[] = { OutLo, OutHi };
1745 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1749 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
1750 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1751 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1753 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1754 SDOperand Lo = Op.getOperand(0);
1755 SDOperand Hi = Op.getOperand(1);
1756 SDOperand Amt = Op.getOperand(2);
1758 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1759 DAG.getConstant(32, MVT::i32), Amt);
1760 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1761 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1762 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1763 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1764 DAG.getConstant(-32U, MVT::i32));
1765 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1766 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1767 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1768 Tmp4, Tmp6, ISD::SETLE);
1769 SDOperand OutOps[] = { OutLo, OutHi };
1770 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1774 //===----------------------------------------------------------------------===//
1775 // Vector related lowering.
1778 // If this is a vector of constants or undefs, get the bits. A bit in
1779 // UndefBits is set if the corresponding element of the vector is an
1780 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1781 // zero. Return true if this is not an array of constants, false if it is.
1783 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1784 uint64_t UndefBits[2]) {
1785 // Start with zero'd results.
1786 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1788 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1789 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1790 SDOperand OpVal = BV->getOperand(i);
1792 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1793 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1795 uint64_t EltBits = 0;
1796 if (OpVal.getOpcode() == ISD::UNDEF) {
1797 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1798 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1800 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1801 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1802 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1803 assert(CN->getValueType(0) == MVT::f32 &&
1804 "Only one legal FP vector type!");
1805 EltBits = FloatToBits(CN->getValue());
1807 // Nonconstant element.
1811 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1814 //printf("%llx %llx %llx %llx\n",
1815 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1819 // If this is a splat (repetition) of a value across the whole vector, return
1820 // the smallest size that splats it. For example, "0x01010101010101..." is a
1821 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1822 // SplatSize = 1 byte.
1823 static bool isConstantSplat(const uint64_t Bits128[2],
1824 const uint64_t Undef128[2],
1825 unsigned &SplatBits, unsigned &SplatUndef,
1826 unsigned &SplatSize) {
1828 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1829 // the same as the lower 64-bits, ignoring undefs.
1830 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1831 return false; // Can't be a splat if two pieces don't match.
1833 uint64_t Bits64 = Bits128[0] | Bits128[1];
1834 uint64_t Undef64 = Undef128[0] & Undef128[1];
1836 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1838 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1839 return false; // Can't be a splat if two pieces don't match.
1841 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1842 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1844 // If the top 16-bits are different than the lower 16-bits, ignoring
1845 // undefs, we have an i32 splat.
1846 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1848 SplatUndef = Undef32;
1853 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1854 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1856 // If the top 8-bits are different than the lower 8-bits, ignoring
1857 // undefs, we have an i16 splat.
1858 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1860 SplatUndef = Undef16;
1865 // Otherwise, we have an 8-bit splat.
1866 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1867 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1872 /// BuildSplatI - Build a canonical splati of Val with an element size of
1873 /// SplatSize. Cast the result to VT.
1874 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1875 SelectionDAG &DAG) {
1876 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1878 // Force vspltis[hw] -1 to vspltisb -1.
1879 if (Val == -1) SplatSize = 1;
1881 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1882 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1884 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1886 // Build a canonical splat for this value.
1887 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1888 SmallVector<SDOperand, 8> Ops;
1889 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
1890 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
1891 &Ops[0], Ops.size());
1892 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1895 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1896 /// specified intrinsic ID.
1897 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1899 MVT::ValueType DestVT = MVT::Other) {
1900 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1901 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1902 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1905 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1906 /// specified intrinsic ID.
1907 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1908 SDOperand Op2, SelectionDAG &DAG,
1909 MVT::ValueType DestVT = MVT::Other) {
1910 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1911 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1912 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1916 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1917 /// amount. The result has the specified value type.
1918 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1919 MVT::ValueType VT, SelectionDAG &DAG) {
1920 // Force LHS/RHS to be the right type.
1921 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
1922 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
1925 for (unsigned i = 0; i != 16; ++i)
1926 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
1927 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
1928 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
1929 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
1932 // If this is a case we can't handle, return null and let the default
1933 // expansion code take care of it. If we CAN select this case, and if it
1934 // selects to a single instruction, return Op. Otherwise, if we can codegen
1935 // this case more efficiently than a constant pool load, lower it to the
1936 // sequence of ops that should be used.
1937 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1938 // If this is a vector of constants or undefs, get the bits. A bit in
1939 // UndefBits is set if the corresponding element of the vector is an
1940 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1942 uint64_t VectorBits[2];
1943 uint64_t UndefBits[2];
1944 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1945 return SDOperand(); // Not a constant vector.
1947 // If this is a splat (repetition) of a value across the whole vector, return
1948 // the smallest size that splats it. For example, "0x01010101010101..." is a
1949 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1950 // SplatSize = 1 byte.
1951 unsigned SplatBits, SplatUndef, SplatSize;
1952 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1953 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1955 // First, handle single instruction cases.
1958 if (SplatBits == 0) {
1959 // Canonicalize all zero vectors to be v4i32.
1960 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1961 SDOperand Z = DAG.getConstant(0, MVT::i32);
1962 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1963 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1968 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1969 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1970 if (SextVal >= -16 && SextVal <= 15)
1971 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
1974 // Two instruction sequences.
1976 // If this value is in the range [-32,30] and is even, use:
1977 // tmp = VSPLTI[bhw], result = add tmp, tmp
1978 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
1979 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
1980 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
1983 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1984 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
1986 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
1987 // Make -1 and vspltisw -1:
1988 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
1990 // Make the VSLW intrinsic, computing 0x8000_0000.
1991 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
1994 // xor by OnesV to invert it.
1995 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1996 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1999 // Check to see if this is a wide variety of vsplti*, binop self cases.
2000 unsigned SplatBitSize = SplatSize*8;
2001 static const char SplatCsts[] = {
2002 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2003 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2005 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
2006 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2007 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2008 int i = SplatCsts[idx];
2010 // Figure out what shift amount will be used by altivec if shifted by i in
2012 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2014 // vsplti + shl self.
2015 if (SextVal == (i << (int)TypeShiftAmt)) {
2016 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2017 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2018 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2019 Intrinsic::ppc_altivec_vslw
2021 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2024 // vsplti + srl self.
2025 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2026 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2027 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2028 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2029 Intrinsic::ppc_altivec_vsrw
2031 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2034 // vsplti + sra self.
2035 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2036 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2037 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2038 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2039 Intrinsic::ppc_altivec_vsraw
2041 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2044 // vsplti + rol self.
2045 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2046 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2047 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2048 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2049 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2050 Intrinsic::ppc_altivec_vrlw
2052 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2055 // t = vsplti c, result = vsldoi t, t, 1
2056 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2057 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2058 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2060 // t = vsplti c, result = vsldoi t, t, 2
2061 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2062 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2063 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2065 // t = vsplti c, result = vsldoi t, t, 3
2066 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2067 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2068 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2072 // Three instruction sequences.
2074 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2075 if (SextVal >= 0 && SextVal <= 31) {
2076 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
2077 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
2078 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
2080 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2081 if (SextVal >= -31 && SextVal <= 0) {
2082 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
2083 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
2084 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
2091 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2092 /// the specified operations to build the shuffle.
2093 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2094 SDOperand RHS, SelectionDAG &DAG) {
2095 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2096 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2097 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2100 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2112 if (OpNum == OP_COPY) {
2113 if (LHSID == (1*9+2)*9+3) return LHS;
2114 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2118 SDOperand OpLHS, OpRHS;
2119 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2120 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2122 unsigned ShufIdxs[16];
2124 default: assert(0 && "Unknown i32 permute!");
2126 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2127 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2128 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2129 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2132 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2133 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2134 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2135 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2138 for (unsigned i = 0; i != 16; ++i)
2139 ShufIdxs[i] = (i&3)+0;
2142 for (unsigned i = 0; i != 16; ++i)
2143 ShufIdxs[i] = (i&3)+4;
2146 for (unsigned i = 0; i != 16; ++i)
2147 ShufIdxs[i] = (i&3)+8;
2150 for (unsigned i = 0; i != 16; ++i)
2151 ShufIdxs[i] = (i&3)+12;
2154 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2156 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2158 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2161 for (unsigned i = 0; i != 16; ++i)
2162 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2164 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2165 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2168 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2169 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2170 /// return the code it can be lowered into. Worst case, it can always be
2171 /// lowered into a vperm.
2172 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2173 SDOperand V1 = Op.getOperand(0);
2174 SDOperand V2 = Op.getOperand(1);
2175 SDOperand PermMask = Op.getOperand(2);
2177 // Cases that are handled by instructions that take permute immediates
2178 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2179 // selected by the instruction selector.
2180 if (V2.getOpcode() == ISD::UNDEF) {
2181 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2182 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2183 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2184 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2185 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2186 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2187 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2188 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2189 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2190 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2191 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2192 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2197 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2198 // and produce a fixed permutation. If any of these match, do not lower to
2200 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2201 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2202 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2203 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2204 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2205 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2206 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2207 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2208 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2211 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2212 // perfect shuffle table to emit an optimal matching sequence.
2213 unsigned PFIndexes[4];
2214 bool isFourElementShuffle = true;
2215 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2216 unsigned EltNo = 8; // Start out undef.
2217 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2218 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2219 continue; // Undef, ignore it.
2221 unsigned ByteSource =
2222 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2223 if ((ByteSource & 3) != j) {
2224 isFourElementShuffle = false;
2229 EltNo = ByteSource/4;
2230 } else if (EltNo != ByteSource/4) {
2231 isFourElementShuffle = false;
2235 PFIndexes[i] = EltNo;
2238 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2239 // perfect shuffle vector to determine if it is cost effective to do this as
2240 // discrete instructions, or whether we should use a vperm.
2241 if (isFourElementShuffle) {
2242 // Compute the index in the perfect shuffle table.
2243 unsigned PFTableIndex =
2244 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2246 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2247 unsigned Cost = (PFEntry >> 30);
2249 // Determining when to avoid vperm is tricky. Many things affect the cost
2250 // of vperm, particularly how many times the perm mask needs to be computed.
2251 // For example, if the perm mask can be hoisted out of a loop or is already
2252 // used (perhaps because there are multiple permutes with the same shuffle
2253 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2254 // the loop requires an extra register.
2256 // As a compromise, we only emit discrete instructions if the shuffle can be
2257 // generated in 3 or fewer operations. When we have loop information
2258 // available, if this block is within a loop, we should avoid using vperm
2259 // for 3-operation perms and use a constant pool load instead.
2261 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2264 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2265 // vector that will get spilled to the constant pool.
2266 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2268 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2269 // that it is in input element units, not in bytes. Convert now.
2270 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
2271 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2273 SmallVector<SDOperand, 16> ResultMask;
2274 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2276 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2279 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2281 for (unsigned j = 0; j != BytesPerElement; ++j)
2282 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2286 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2287 &ResultMask[0], ResultMask.size());
2288 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2291 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2292 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2293 /// information about the intrinsic.
2294 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2296 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2299 switch (IntrinsicID) {
2300 default: return false;
2301 // Comparison predicates.
2302 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2303 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2304 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2305 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2306 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2307 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2308 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2309 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2310 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2311 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2312 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2313 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2314 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2316 // Normal Comparisons.
2317 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2318 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2319 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2320 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2321 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2322 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2323 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2324 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2325 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2326 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2327 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2328 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2329 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2334 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2335 /// lower, do it, otherwise return null.
2336 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2337 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2338 // opcode number of the comparison.
2341 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2342 return SDOperand(); // Don't custom lower most intrinsics.
2344 // If this is a non-dot comparison, make the VCMP node and we are done.
2346 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2347 Op.getOperand(1), Op.getOperand(2),
2348 DAG.getConstant(CompareOpc, MVT::i32));
2349 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2352 // Create the PPCISD altivec 'dot' comparison node.
2354 Op.getOperand(2), // LHS
2355 Op.getOperand(3), // RHS
2356 DAG.getConstant(CompareOpc, MVT::i32)
2358 std::vector<MVT::ValueType> VTs;
2359 VTs.push_back(Op.getOperand(2).getValueType());
2360 VTs.push_back(MVT::Flag);
2361 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2363 // Now that we have the comparison, emit a copy from the CR to a GPR.
2364 // This is flagged to the above dot comparison.
2365 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2366 DAG.getRegister(PPC::CR6, MVT::i32),
2367 CompNode.getValue(1));
2369 // Unpack the result based on how the target uses it.
2370 unsigned BitNo; // Bit # of CR6.
2371 bool InvertBit; // Invert result?
2372 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2373 default: // Can't happen, don't crash on invalid number though.
2374 case 0: // Return the value of the EQ bit of CR6.
2375 BitNo = 0; InvertBit = false;
2377 case 1: // Return the inverted value of the EQ bit of CR6.
2378 BitNo = 0; InvertBit = true;
2380 case 2: // Return the value of the LT bit of CR6.
2381 BitNo = 2; InvertBit = false;
2383 case 3: // Return the inverted value of the LT bit of CR6.
2384 BitNo = 2; InvertBit = true;
2388 // Shift the bit into the low position.
2389 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2390 DAG.getConstant(8-(3-BitNo), MVT::i32));
2392 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2393 DAG.getConstant(1, MVT::i32));
2395 // If we are supposed to, toggle the bit.
2397 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2398 DAG.getConstant(1, MVT::i32));
2402 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2403 // Create a stack slot that is 16-byte aligned.
2404 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2405 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2406 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2407 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2409 // Store the input value into Value#0 of the stack slot.
2410 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2411 Op.getOperand(0), FIdx, NULL, 0);
2413 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
2416 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2417 if (Op.getValueType() == MVT::v4i32) {
2418 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2420 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2421 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2423 SDOperand RHSSwap = // = vrlw RHS, 16
2424 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2426 // Shrinkify inputs to v8i16.
2427 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2428 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2429 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2431 // Low parts multiplied together, generating 32-bit results (we ignore the
2433 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2434 LHS, RHS, DAG, MVT::v4i32);
2436 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2437 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2438 // Shift the high parts up 16 bits.
2439 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2440 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2441 } else if (Op.getValueType() == MVT::v8i16) {
2442 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2444 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2446 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2447 LHS, RHS, Zero, DAG);
2448 } else if (Op.getValueType() == MVT::v16i8) {
2449 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2451 // Multiply the even 8-bit parts, producing 16-bit sums.
2452 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2453 LHS, RHS, DAG, MVT::v8i16);
2454 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2456 // Multiply the odd 8-bit parts, producing 16-bit sums.
2457 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2458 LHS, RHS, DAG, MVT::v8i16);
2459 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2461 // Merge the results together.
2463 for (unsigned i = 0; i != 8; ++i) {
2464 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2465 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2467 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2468 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2470 assert(0 && "Unknown mul to lower!");
2475 /// LowerOperation - Provide custom lowering hooks for some operations.
2477 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2478 switch (Op.getOpcode()) {
2479 default: assert(0 && "Wasn't expecting to be able to lower this!");
2480 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2481 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2482 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2483 case ISD::SETCC: return LowerSETCC(Op, DAG);
2484 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2485 case ISD::FORMAL_ARGUMENTS:
2486 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
2487 case ISD::CALL: return LowerCALL(Op, DAG);
2488 case ISD::RET: return LowerRET(Op, DAG);
2490 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2491 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2492 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2494 // Lower 64-bit shifts.
2495 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
2496 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
2497 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
2499 // Vector-related lowering.
2500 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2501 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2502 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2503 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2504 case ISD::MUL: return LowerMUL(Op, DAG);
2509 //===----------------------------------------------------------------------===//
2510 // Other Lowering Code
2511 //===----------------------------------------------------------------------===//
2514 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2515 MachineBasicBlock *BB) {
2516 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2517 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2518 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2519 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2520 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2521 "Unexpected instr type to insert");
2523 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2524 // control-flow pattern. The incoming instruction knows the destination vreg
2525 // to set, the condition code register to branch on, the true/false values to
2526 // select between, and a branch opcode to use.
2527 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2528 ilist<MachineBasicBlock>::iterator It = BB;
2534 // cmpTY ccX, r1, r2
2536 // fallthrough --> copy0MBB
2537 MachineBasicBlock *thisMBB = BB;
2538 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2539 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2540 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
2541 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2542 MachineFunction *F = BB->getParent();
2543 F->getBasicBlockList().insert(It, copy0MBB);
2544 F->getBasicBlockList().insert(It, sinkMBB);
2545 // Update machine-CFG edges by first adding all successors of the current
2546 // block to the new block which will contain the Phi node for the select.
2547 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2548 e = BB->succ_end(); i != e; ++i)
2549 sinkMBB->addSuccessor(*i);
2550 // Next, remove all successors of the current block, and add the true
2551 // and fallthrough blocks as its successors.
2552 while(!BB->succ_empty())
2553 BB->removeSuccessor(BB->succ_begin());
2554 BB->addSuccessor(copy0MBB);
2555 BB->addSuccessor(sinkMBB);
2558 // %FalseValue = ...
2559 // # fallthrough to sinkMBB
2562 // Update machine-CFG edges
2563 BB->addSuccessor(sinkMBB);
2566 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2569 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2570 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2571 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2573 delete MI; // The pseudo instruction is gone now.
2577 //===----------------------------------------------------------------------===//
2578 // Target Optimization Hooks
2579 //===----------------------------------------------------------------------===//
2581 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2582 DAGCombinerInfo &DCI) const {
2583 TargetMachine &TM = getTargetMachine();
2584 SelectionDAG &DAG = DCI.DAG;
2585 switch (N->getOpcode()) {
2588 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2589 if (C->getValue() == 0) // 0 << V -> 0.
2590 return N->getOperand(0);
2594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2595 if (C->getValue() == 0) // 0 >>u V -> 0.
2596 return N->getOperand(0);
2600 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2601 if (C->getValue() == 0 || // 0 >>s V -> 0.
2602 C->isAllOnesValue()) // -1 >>s V -> -1.
2603 return N->getOperand(0);
2607 case ISD::SINT_TO_FP:
2608 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
2609 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2610 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2611 // We allow the src/dst to be either f32/f64, but the intermediate
2612 // type must be i64.
2613 if (N->getOperand(0).getValueType() == MVT::i64) {
2614 SDOperand Val = N->getOperand(0).getOperand(0);
2615 if (Val.getValueType() == MVT::f32) {
2616 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2617 DCI.AddToWorklist(Val.Val);
2620 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2621 DCI.AddToWorklist(Val.Val);
2622 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2623 DCI.AddToWorklist(Val.Val);
2624 if (N->getValueType(0) == MVT::f32) {
2625 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2626 DCI.AddToWorklist(Val.Val);
2629 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2630 // If the intermediate type is i32, we can avoid the load/store here
2637 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2638 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2639 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2640 N->getOperand(1).getValueType() == MVT::i32) {
2641 SDOperand Val = N->getOperand(1).getOperand(0);
2642 if (Val.getValueType() == MVT::f32) {
2643 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2644 DCI.AddToWorklist(Val.Val);
2646 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2647 DCI.AddToWorklist(Val.Val);
2649 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2650 N->getOperand(2), N->getOperand(3));
2651 DCI.AddToWorklist(Val.Val);
2655 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
2656 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
2657 N->getOperand(1).Val->hasOneUse() &&
2658 (N->getOperand(1).getValueType() == MVT::i32 ||
2659 N->getOperand(1).getValueType() == MVT::i16)) {
2660 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
2661 // Do an any-extend to 32-bits if this is a half-word input.
2662 if (BSwapOp.getValueType() == MVT::i16)
2663 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
2665 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
2666 N->getOperand(2), N->getOperand(3),
2667 DAG.getValueType(N->getOperand(1).getValueType()));
2671 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
2672 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
2673 N->getOperand(0).hasOneUse() &&
2674 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
2675 SDOperand Load = N->getOperand(0);
2676 LoadSDNode *LD = cast<LoadSDNode>(Load);
2677 // Create the byte-swapping load.
2678 std::vector<MVT::ValueType> VTs;
2679 VTs.push_back(MVT::i32);
2680 VTs.push_back(MVT::Other);
2681 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
2683 LD->getChain(), // Chain
2684 LD->getBasePtr(), // Ptr
2686 DAG.getValueType(N->getValueType(0)) // VT
2688 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
2690 // If this is an i16 load, insert the truncate.
2691 SDOperand ResVal = BSLoad;
2692 if (N->getValueType(0) == MVT::i16)
2693 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
2695 // First, combine the bswap away. This makes the value produced by the
2697 DCI.CombineTo(N, ResVal);
2699 // Next, combine the load away, we give it a bogus result value but a real
2700 // chain result. The result value is dead because the bswap is dead.
2701 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
2703 // Return N so it doesn't get rechecked!
2704 return SDOperand(N, 0);
2708 case PPCISD::VCMP: {
2709 // If a VCMPo node already exists with exactly the same operands as this
2710 // node, use its result instead of this node (VCMPo computes both a CR6 and
2711 // a normal output).
2713 if (!N->getOperand(0).hasOneUse() &&
2714 !N->getOperand(1).hasOneUse() &&
2715 !N->getOperand(2).hasOneUse()) {
2717 // Scan all of the users of the LHS, looking for VCMPo's that match.
2718 SDNode *VCMPoNode = 0;
2720 SDNode *LHSN = N->getOperand(0).Val;
2721 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2723 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2724 (*UI)->getOperand(1) == N->getOperand(1) &&
2725 (*UI)->getOperand(2) == N->getOperand(2) &&
2726 (*UI)->getOperand(0) == N->getOperand(0)) {
2731 // If there is no VCMPo node, or if the flag value has a single use, don't
2733 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2736 // Look at the (necessarily single) use of the flag value. If it has a
2737 // chain, this transformation is more complex. Note that multiple things
2738 // could use the value result, which we should ignore.
2739 SDNode *FlagUser = 0;
2740 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2741 FlagUser == 0; ++UI) {
2742 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2744 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2745 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2752 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2753 // give up for right now.
2754 if (FlagUser->getOpcode() == PPCISD::MFCR)
2755 return SDOperand(VCMPoNode, 0);
2760 // If this is a branch on an altivec predicate comparison, lower this so
2761 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2762 // lowering is done pre-legalize, because the legalizer lowers the predicate
2763 // compare down to code that is difficult to reassemble.
2764 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2765 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2769 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2770 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2771 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2772 assert(isDot && "Can't compare against a vector result!");
2774 // If this is a comparison against something other than 0/1, then we know
2775 // that the condition is never/always true.
2776 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2777 if (Val != 0 && Val != 1) {
2778 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2779 return N->getOperand(0);
2780 // Always !=, turn it into an unconditional branch.
2781 return DAG.getNode(ISD::BR, MVT::Other,
2782 N->getOperand(0), N->getOperand(4));
2785 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2787 // Create the PPCISD altivec 'dot' comparison node.
2788 std::vector<MVT::ValueType> VTs;
2790 LHS.getOperand(2), // LHS of compare
2791 LHS.getOperand(3), // RHS of compare
2792 DAG.getConstant(CompareOpc, MVT::i32)
2794 VTs.push_back(LHS.getOperand(2).getValueType());
2795 VTs.push_back(MVT::Flag);
2796 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2798 // Unpack the result based on how the target uses it.
2800 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2801 default: // Can't happen, don't crash on invalid number though.
2802 case 0: // Branch on the value of the EQ bit of CR6.
2803 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
2805 case 1: // Branch on the inverted value of the EQ bit of CR6.
2806 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
2808 case 2: // Branch on the value of the LT bit of CR6.
2809 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
2811 case 3: // Branch on the inverted value of the LT bit of CR6.
2812 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
2816 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2817 DAG.getRegister(PPC::CR6, MVT::i32),
2818 DAG.getConstant(CompOpc, MVT::i32),
2819 N->getOperand(4), CompNode.getValue(1));
2828 //===----------------------------------------------------------------------===//
2829 // Inline Assembly Support
2830 //===----------------------------------------------------------------------===//
2832 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2834 uint64_t &KnownZero,
2836 unsigned Depth) const {
2839 switch (Op.getOpcode()) {
2841 case PPCISD::LBRX: {
2842 // lhbrx is known to have the top bits cleared out.
2843 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
2844 KnownZero = 0xFFFF0000;
2847 case ISD::INTRINSIC_WO_CHAIN: {
2848 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2850 case Intrinsic::ppc_altivec_vcmpbfp_p:
2851 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2852 case Intrinsic::ppc_altivec_vcmpequb_p:
2853 case Intrinsic::ppc_altivec_vcmpequh_p:
2854 case Intrinsic::ppc_altivec_vcmpequw_p:
2855 case Intrinsic::ppc_altivec_vcmpgefp_p:
2856 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2857 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2858 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2859 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2860 case Intrinsic::ppc_altivec_vcmpgtub_p:
2861 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2862 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2863 KnownZero = ~1U; // All bits but the low one are known to be zero.
2871 /// getConstraintType - Given a constraint letter, return the type of
2872 /// constraint it is for this target.
2873 PPCTargetLowering::ConstraintType
2874 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2875 switch (ConstraintLetter) {
2882 return C_RegisterClass;
2884 return TargetLowering::getConstraintType(ConstraintLetter);
2887 std::pair<unsigned, const TargetRegisterClass*>
2888 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2889 MVT::ValueType VT) const {
2890 if (Constraint.size() == 1) {
2891 // GCC RS6000 Constraint Letters
2892 switch (Constraint[0]) {
2895 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
2896 return std::make_pair(0U, PPC::G8RCRegisterClass);
2897 return std::make_pair(0U, PPC::GPRCRegisterClass);
2900 return std::make_pair(0U, PPC::F4RCRegisterClass);
2901 else if (VT == MVT::f64)
2902 return std::make_pair(0U, PPC::F8RCRegisterClass);
2905 return std::make_pair(0U, PPC::VRRCRegisterClass);
2907 return std::make_pair(0U, PPC::CRRCRegisterClass);
2911 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2915 // isOperandValidForConstraint
2916 SDOperand PPCTargetLowering::
2917 isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
2928 if (!isa<ConstantSDNode>(Op)) return SDOperand(0,0);// Must be an immediate.
2929 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2931 default: assert(0 && "Unknown constraint letter!");
2932 case 'I': // "I" is a signed 16-bit constant.
2933 if ((short)Value == (int)Value) return Op;
2935 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2936 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2937 if ((short)Value == 0) return Op;
2939 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2940 if ((Value >> 16) == 0) return Op;
2942 case 'M': // "M" is a constant that is greater than 31.
2943 if (Value > 31) return Op;
2945 case 'N': // "N" is a positive constant that is an exact power of two.
2946 if ((int)Value > 0 && isPowerOf2_32(Value)) return Op;
2948 case 'O': // "O" is the constant zero.
2949 if (Value == 0) return Op;
2951 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2952 if ((short)-Value == (int)-Value) return Op;
2959 // Handle standard constraint letters.
2960 return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
2963 /// isLegalAddressImmediate - Return true if the integer value can be used
2964 /// as the offset of the target addressing mode.
2965 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2966 // PPC allows a sign-extended 16-bit immediate field.
2967 return (V > -(1 << 16) && V < (1 << 16)-1);
2970 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
2971 return TargetLowering::isLegalAddressImmediate(GV);