1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
49 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
50 if (TM.getSubtargetImpl()->isDarwin())
51 return new TargetLoweringObjectFileMachO();
53 if (TM.getSubtargetImpl()->isSVR4ABI())
54 return new PPC64LinuxTargetObjectFile();
56 return new TargetLoweringObjectFileELF();
59 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
60 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
61 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
65 // Use _setjmp/_longjmp instead of setjmp/longjmp.
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
69 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
70 // arguments are at least 4/8 bytes aligned.
71 bool isPPC64 = Subtarget->isPPC64();
72 setMinStackArgumentAlignment(isPPC64 ? 8:4);
74 // Set up the register classes.
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
79 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 // This is used in the ppcf128->int sequence. Note it has different semantics
98 // from FP_ROUND: that rounds to nearest, this rounds to zero.
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
101 // We do not currently implement these libm ops for PowerPC.
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
109 // PowerPC has no SREM/UREM instructions
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
115 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
125 // We don't support sin/cos/sqrt/fmod/pow
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
141 // If we're enabling GP optimizations, use hardware square root
142 if (!Subtarget->hasFSQRT() &&
143 !(TM.Options.UnsafeFPMath &&
144 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
147 if (!Subtarget->hasFSQRT() &&
148 !(TM.Options.UnsafeFPMath &&
149 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
153 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
155 if (Subtarget->hasFPRND()) {
156 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
157 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
158 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
159 setOperationAction(ISD::FROUND, MVT::f64, Legal);
161 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
162 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
163 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
164 setOperationAction(ISD::FROUND, MVT::f32, Legal);
167 // PowerPC does not have BSWAP, CTPOP or CTTZ
168 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
169 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
170 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
171 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
172 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
173 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
174 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
175 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
177 if (Subtarget->hasPOPCNTD()) {
178 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
179 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
181 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
182 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
185 // PowerPC does not have ROTR
186 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
187 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
189 // PowerPC does not have Select
190 setOperationAction(ISD::SELECT, MVT::i32, Expand);
191 setOperationAction(ISD::SELECT, MVT::i64, Expand);
192 setOperationAction(ISD::SELECT, MVT::f32, Expand);
193 setOperationAction(ISD::SELECT, MVT::f64, Expand);
195 // PowerPC wants to turn select_cc of FP into fsel when possible.
196 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
197 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
199 // PowerPC wants to optimize integer setcc a bit
200 setOperationAction(ISD::SETCC, MVT::i32, Custom);
202 // PowerPC does not have BRCOND which requires SetCC
203 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
205 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
207 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
208 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
210 // PowerPC does not have [U|S]INT_TO_FP
211 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
212 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
214 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
215 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
216 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
217 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
219 // We cannot sextinreg(i1). Expand to shifts.
220 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
222 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
223 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
224 // support continuation, user-level threading, and etc.. As a result, no
225 // other SjLj exception interfaces are implemented and please don't build
226 // your own exception handling based on them.
227 // LLVM/Clang supports zero-cost DWARF exception handling.
228 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
229 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
231 // We want to legalize GlobalAddress and ConstantPool nodes into the
232 // appropriate instructions to materialize the address.
233 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
234 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
235 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
236 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
237 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
238 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
239 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
240 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
241 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
242 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
245 setOperationAction(ISD::TRAP, MVT::Other, Legal);
247 // TRAMPOLINE is custom lowered.
248 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
249 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
251 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
252 setOperationAction(ISD::VASTART , MVT::Other, Custom);
254 if (Subtarget->isSVR4ABI()) {
256 // VAARG always uses double-word chunks, so promote anything smaller.
257 setOperationAction(ISD::VAARG, MVT::i1, Promote);
258 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
259 setOperationAction(ISD::VAARG, MVT::i8, Promote);
260 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
261 setOperationAction(ISD::VAARG, MVT::i16, Promote);
262 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
263 setOperationAction(ISD::VAARG, MVT::i32, Promote);
264 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
265 setOperationAction(ISD::VAARG, MVT::Other, Expand);
267 // VAARG is custom lowered with the 32-bit SVR4 ABI.
268 setOperationAction(ISD::VAARG, MVT::Other, Custom);
269 setOperationAction(ISD::VAARG, MVT::i64, Custom);
272 setOperationAction(ISD::VAARG, MVT::Other, Expand);
274 if (Subtarget->isSVR4ABI() && !isPPC64)
275 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
276 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
278 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
280 // Use the default implementation.
281 setOperationAction(ISD::VAEND , MVT::Other, Expand);
282 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
283 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
284 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
285 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
287 // We want to custom lower some of our intrinsics.
288 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
290 // To handle counter-based loop conditions.
291 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
293 // Comparisons that require checking two conditions.
294 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
295 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
296 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
297 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
298 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
299 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
300 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
301 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
302 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
303 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
304 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
307 if (Subtarget->has64BitSupport()) {
308 // They also have instructions for converting between i64 and fp.
309 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
310 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
311 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
312 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
313 // This is just the low 32 bits of a (signed) fp->i64 conversion.
314 // We cannot do this with Promote because i64 is not a legal type.
315 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
317 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
318 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
320 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
321 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
324 // With the instructions enabled under FPCVT, we can do everything.
325 if (PPCSubTarget.hasFPCVT()) {
326 if (Subtarget->has64BitSupport()) {
327 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
328 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
329 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
330 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
333 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
334 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
335 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
336 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
339 if (Subtarget->use64BitRegs()) {
340 // 64-bit PowerPC implementations can support i64 types directly
341 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
342 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
343 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
344 // 64-bit PowerPC wants to expand i128 shifts itself.
345 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
346 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
347 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
349 // 32-bit PowerPC wants to expand i64 shifts itself.
350 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
351 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
352 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
355 if (Subtarget->hasAltivec()) {
356 // First set operation action for all vector types to expand. Then we
357 // will selectively turn on ones that can be effectively codegen'd.
358 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
359 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
360 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
362 // add/sub are legal for all supported vector VT's.
363 setOperationAction(ISD::ADD , VT, Legal);
364 setOperationAction(ISD::SUB , VT, Legal);
366 // We promote all shuffles to v16i8.
367 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
368 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
370 // We promote all non-typed operations to v4i32.
371 setOperationAction(ISD::AND , VT, Promote);
372 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
373 setOperationAction(ISD::OR , VT, Promote);
374 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
375 setOperationAction(ISD::XOR , VT, Promote);
376 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
377 setOperationAction(ISD::LOAD , VT, Promote);
378 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
379 setOperationAction(ISD::SELECT, VT, Promote);
380 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
381 setOperationAction(ISD::STORE, VT, Promote);
382 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
384 // No other operations are legal.
385 setOperationAction(ISD::MUL , VT, Expand);
386 setOperationAction(ISD::SDIV, VT, Expand);
387 setOperationAction(ISD::SREM, VT, Expand);
388 setOperationAction(ISD::UDIV, VT, Expand);
389 setOperationAction(ISD::UREM, VT, Expand);
390 setOperationAction(ISD::FDIV, VT, Expand);
391 setOperationAction(ISD::FREM, VT, Expand);
392 setOperationAction(ISD::FNEG, VT, Expand);
393 setOperationAction(ISD::FSQRT, VT, Expand);
394 setOperationAction(ISD::FLOG, VT, Expand);
395 setOperationAction(ISD::FLOG10, VT, Expand);
396 setOperationAction(ISD::FLOG2, VT, Expand);
397 setOperationAction(ISD::FEXP, VT, Expand);
398 setOperationAction(ISD::FEXP2, VT, Expand);
399 setOperationAction(ISD::FSIN, VT, Expand);
400 setOperationAction(ISD::FCOS, VT, Expand);
401 setOperationAction(ISD::FABS, VT, Expand);
402 setOperationAction(ISD::FPOWI, VT, Expand);
403 setOperationAction(ISD::FFLOOR, VT, Expand);
404 setOperationAction(ISD::FCEIL, VT, Expand);
405 setOperationAction(ISD::FTRUNC, VT, Expand);
406 setOperationAction(ISD::FRINT, VT, Expand);
407 setOperationAction(ISD::FNEARBYINT, VT, Expand);
408 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
409 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
410 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
411 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
412 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
413 setOperationAction(ISD::UDIVREM, VT, Expand);
414 setOperationAction(ISD::SDIVREM, VT, Expand);
415 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
416 setOperationAction(ISD::FPOW, VT, Expand);
417 setOperationAction(ISD::CTPOP, VT, Expand);
418 setOperationAction(ISD::CTLZ, VT, Expand);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
420 setOperationAction(ISD::CTTZ, VT, Expand);
421 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
422 setOperationAction(ISD::VSELECT, VT, Expand);
423 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
425 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
426 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
427 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
428 setTruncStoreAction(VT, InnerVT, Expand);
430 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
431 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
432 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
435 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
436 // with merges, splats, etc.
437 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
439 setOperationAction(ISD::AND , MVT::v4i32, Legal);
440 setOperationAction(ISD::OR , MVT::v4i32, Legal);
441 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
442 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
443 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
444 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
445 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
446 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
447 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
448 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
449 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
450 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
451 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
452 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
454 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
455 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
456 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
457 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
459 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
460 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
462 if (TM.Options.UnsafeFPMath) {
463 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
464 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
467 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
468 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
469 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
471 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
472 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
474 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
475 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
476 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
477 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
479 // Altivec does not contain unordered floating-point compare instructions
480 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
481 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
482 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
483 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
484 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
485 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
487 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
488 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
491 if (Subtarget->has64BitSupport()) {
492 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
493 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
496 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
497 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
498 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
499 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
501 setBooleanContents(ZeroOrOneBooleanContent);
502 // Altivec instructions set fields to all zeros or all ones.
503 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
506 setStackPointerRegisterToSaveRestore(PPC::X1);
507 setExceptionPointerRegister(PPC::X3);
508 setExceptionSelectorRegister(PPC::X4);
510 setStackPointerRegisterToSaveRestore(PPC::R1);
511 setExceptionPointerRegister(PPC::R3);
512 setExceptionSelectorRegister(PPC::R4);
515 // We have target-specific dag combine patterns for the following nodes:
516 setTargetDAGCombine(ISD::SINT_TO_FP);
517 setTargetDAGCombine(ISD::LOAD);
518 setTargetDAGCombine(ISD::STORE);
519 setTargetDAGCombine(ISD::BR_CC);
520 setTargetDAGCombine(ISD::BSWAP);
521 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
523 // Use reciprocal estimates.
524 if (TM.Options.UnsafeFPMath) {
525 setTargetDAGCombine(ISD::FDIV);
526 setTargetDAGCombine(ISD::FSQRT);
529 // Darwin long double math library functions have $LDBL128 appended.
530 if (Subtarget->isDarwin()) {
531 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
532 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
533 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
534 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
535 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
536 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
537 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
538 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
539 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
540 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
543 setMinFunctionAlignment(2);
544 if (PPCSubTarget.isDarwin())
545 setPrefFunctionAlignment(4);
547 if (isPPC64 && Subtarget->isJITCodeModel())
548 // Temporary workaround for the inability of PPC64 JIT to handle jump
550 setSupportJumpTables(false);
552 setInsertFencesForAtomic(true);
554 setSchedulingPreference(Sched::Hybrid);
556 computeRegisterProperties();
558 // The Freescale cores does better with aggressive inlining of memcpy and
559 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
560 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
561 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
562 MaxStoresPerMemset = 32;
563 MaxStoresPerMemsetOptSize = 16;
564 MaxStoresPerMemcpy = 32;
565 MaxStoresPerMemcpyOptSize = 8;
566 MaxStoresPerMemmove = 32;
567 MaxStoresPerMemmoveOptSize = 8;
569 setPrefFunctionAlignment(4);
573 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
574 /// function arguments in the caller parameter area.
575 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
576 const TargetMachine &TM = getTargetMachine();
577 // Darwin passes everything on 4 byte boundary.
578 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
581 // 16byte and wider vectors are passed on 16byte boundary.
582 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
583 if (VTy->getBitWidth() >= 128)
586 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
587 if (PPCSubTarget.isPPC64())
593 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
596 case PPCISD::FSEL: return "PPCISD::FSEL";
597 case PPCISD::FCFID: return "PPCISD::FCFID";
598 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
599 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
600 case PPCISD::FRE: return "PPCISD::FRE";
601 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
602 case PPCISD::STFIWX: return "PPCISD::STFIWX";
603 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
604 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
605 case PPCISD::VPERM: return "PPCISD::VPERM";
606 case PPCISD::Hi: return "PPCISD::Hi";
607 case PPCISD::Lo: return "PPCISD::Lo";
608 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
609 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
610 case PPCISD::LOAD: return "PPCISD::LOAD";
611 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
612 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
613 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
614 case PPCISD::SRL: return "PPCISD::SRL";
615 case PPCISD::SRA: return "PPCISD::SRA";
616 case PPCISD::SHL: return "PPCISD::SHL";
617 case PPCISD::CALL: return "PPCISD::CALL";
618 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
619 case PPCISD::MTCTR: return "PPCISD::MTCTR";
620 case PPCISD::BCTRL: return "PPCISD::BCTRL";
621 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
622 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
623 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
624 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
625 case PPCISD::VCMP: return "PPCISD::VCMP";
626 case PPCISD::VCMPo: return "PPCISD::VCMPo";
627 case PPCISD::LBRX: return "PPCISD::LBRX";
628 case PPCISD::STBRX: return "PPCISD::STBRX";
629 case PPCISD::LARX: return "PPCISD::LARX";
630 case PPCISD::STCX: return "PPCISD::STCX";
631 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
632 case PPCISD::BDNZ: return "PPCISD::BDNZ";
633 case PPCISD::BDZ: return "PPCISD::BDZ";
634 case PPCISD::MFFS: return "PPCISD::MFFS";
635 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
636 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
637 case PPCISD::CR6SET: return "PPCISD::CR6SET";
638 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
639 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
640 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
641 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
642 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
643 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
644 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
645 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
646 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
647 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
648 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
649 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
650 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
651 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
652 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
653 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
654 case PPCISD::SC: return "PPCISD::SC";
658 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
661 return VT.changeVectorElementTypeToInteger();
664 //===----------------------------------------------------------------------===//
665 // Node matching predicates, for use by the tblgen matching code.
666 //===----------------------------------------------------------------------===//
668 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
669 static bool isFloatingPointZero(SDValue Op) {
670 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
671 return CFP->getValueAPF().isZero();
672 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
673 // Maybe this has already been legalized into the constant pool?
674 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
675 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
676 return CFP->getValueAPF().isZero();
681 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
682 /// true if Op is undef or if it matches the specified value.
683 static bool isConstantOrUndef(int Op, int Val) {
684 return Op < 0 || Op == Val;
687 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
688 /// VPKUHUM instruction.
689 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
691 for (unsigned i = 0; i != 16; ++i)
692 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
695 for (unsigned i = 0; i != 8; ++i)
696 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
697 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
703 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
704 /// VPKUWUM instruction.
705 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
707 for (unsigned i = 0; i != 16; i += 2)
708 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
709 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
712 for (unsigned i = 0; i != 8; i += 2)
713 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
714 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
715 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
716 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
722 /// isVMerge - Common function, used to match vmrg* shuffles.
724 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
725 unsigned LHSStart, unsigned RHSStart) {
726 assert(N->getValueType(0) == MVT::v16i8 &&
727 "PPC only supports shuffles by bytes!");
728 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
729 "Unsupported merge size!");
731 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
732 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
733 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
734 LHSStart+j+i*UnitSize) ||
735 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
736 RHSStart+j+i*UnitSize))
742 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
743 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
744 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
747 return isVMerge(N, UnitSize, 8, 24);
748 return isVMerge(N, UnitSize, 8, 8);
751 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
752 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
753 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
756 return isVMerge(N, UnitSize, 0, 16);
757 return isVMerge(N, UnitSize, 0, 0);
761 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
762 /// amount, otherwise return -1.
763 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
764 assert(N->getValueType(0) == MVT::v16i8 &&
765 "PPC only supports shuffles by bytes!");
767 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
769 // Find the first non-undef value in the shuffle mask.
771 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
774 if (i == 16) return -1; // all undef.
776 // Otherwise, check to see if the rest of the elements are consecutively
777 // numbered from this value.
778 unsigned ShiftAmt = SVOp->getMaskElt(i);
779 if (ShiftAmt < i) return -1;
783 // Check the rest of the elements to see if they are consecutive.
784 for (++i; i != 16; ++i)
785 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
788 // Check the rest of the elements to see if they are consecutive.
789 for (++i; i != 16; ++i)
790 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
796 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
797 /// specifies a splat of a single element that is suitable for input to
798 /// VSPLTB/VSPLTH/VSPLTW.
799 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
800 assert(N->getValueType(0) == MVT::v16i8 &&
801 (EltSize == 1 || EltSize == 2 || EltSize == 4));
803 // This is a splat operation if each element of the permute is the same, and
804 // if the value doesn't reference the second vector.
805 unsigned ElementBase = N->getMaskElt(0);
807 // FIXME: Handle UNDEF elements too!
808 if (ElementBase >= 16)
811 // Check that the indices are consecutive, in the case of a multi-byte element
812 // splatted with a v16i8 mask.
813 for (unsigned i = 1; i != EltSize; ++i)
814 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
817 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
818 if (N->getMaskElt(i) < 0) continue;
819 for (unsigned j = 0; j != EltSize; ++j)
820 if (N->getMaskElt(i+j) != N->getMaskElt(j))
826 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
828 bool PPC::isAllNegativeZeroVector(SDNode *N) {
829 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
831 APInt APVal, APUndef;
835 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
836 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
837 return CFP->getValueAPF().isNegZero();
842 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
843 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
844 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
845 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
846 assert(isSplatShuffleMask(SVOp, EltSize));
847 return SVOp->getMaskElt(0) / EltSize;
850 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
851 /// by using a vspltis[bhw] instruction of the specified element size, return
852 /// the constant being splatted. The ByteSize field indicates the number of
853 /// bytes of each element [124] -> [bhw].
854 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
857 // If ByteSize of the splat is bigger than the element size of the
858 // build_vector, then we have a case where we are checking for a splat where
859 // multiple elements of the buildvector are folded together into a single
860 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
861 unsigned EltSize = 16/N->getNumOperands();
862 if (EltSize < ByteSize) {
863 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
864 SDValue UniquedVals[4];
865 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
867 // See if all of the elements in the buildvector agree across.
868 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
869 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
870 // If the element isn't a constant, bail fully out.
871 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
874 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
875 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
876 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
877 return SDValue(); // no match.
880 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
881 // either constant or undef values that are identical for each chunk. See
882 // if these chunks can form into a larger vspltis*.
884 // Check to see if all of the leading entries are either 0 or -1. If
885 // neither, then this won't fit into the immediate field.
886 bool LeadingZero = true;
887 bool LeadingOnes = true;
888 for (unsigned i = 0; i != Multiple-1; ++i) {
889 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
891 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
892 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
894 // Finally, check the least significant entry.
896 if (UniquedVals[Multiple-1].getNode() == 0)
897 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
898 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
900 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
903 if (UniquedVals[Multiple-1].getNode() == 0)
904 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
905 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
906 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
907 return DAG.getTargetConstant(Val, MVT::i32);
913 // Check to see if this buildvec has a single non-undef value in its elements.
914 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
915 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
916 if (OpVal.getNode() == 0)
917 OpVal = N->getOperand(i);
918 else if (OpVal != N->getOperand(i))
922 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
924 unsigned ValSizeInBytes = EltSize;
926 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
927 Value = CN->getZExtValue();
928 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
929 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
930 Value = FloatToBits(CN->getValueAPF().convertToFloat());
933 // If the splat value is larger than the element value, then we can never do
934 // this splat. The only case that we could fit the replicated bits into our
935 // immediate field for would be zero, and we prefer to use vxor for it.
936 if (ValSizeInBytes < ByteSize) return SDValue();
938 // If the element value is larger than the splat value, cut it in half and
939 // check to see if the two halves are equal. Continue doing this until we
940 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
941 while (ValSizeInBytes > ByteSize) {
942 ValSizeInBytes >>= 1;
944 // If the top half equals the bottom half, we're still ok.
945 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
946 (Value & ((1 << (8*ValSizeInBytes))-1)))
950 // Properly sign extend the value.
951 int MaskVal = SignExtend32(Value, ByteSize * 8);
953 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
954 if (MaskVal == 0) return SDValue();
956 // Finally, if this value fits in a 5 bit sext field, return it
957 if (SignExtend32<5>(MaskVal) == MaskVal)
958 return DAG.getTargetConstant(MaskVal, MVT::i32);
962 //===----------------------------------------------------------------------===//
963 // Addressing Mode Selection
964 //===----------------------------------------------------------------------===//
966 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
967 /// or 64-bit immediate, and if the value can be accurately represented as a
968 /// sign extension from a 16-bit value. If so, this returns true and the
970 static bool isIntS16Immediate(SDNode *N, short &Imm) {
971 if (N->getOpcode() != ISD::Constant)
974 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
975 if (N->getValueType(0) == MVT::i32)
976 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
978 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
980 static bool isIntS16Immediate(SDValue Op, short &Imm) {
981 return isIntS16Immediate(Op.getNode(), Imm);
985 /// SelectAddressRegReg - Given the specified addressed, check to see if it
986 /// can be represented as an indexed [r+r] operation. Returns false if it
987 /// can be more efficiently represented with [r+imm].
988 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
990 SelectionDAG &DAG) const {
992 if (N.getOpcode() == ISD::ADD) {
993 if (isIntS16Immediate(N.getOperand(1), imm))
995 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
998 Base = N.getOperand(0);
999 Index = N.getOperand(1);
1001 } else if (N.getOpcode() == ISD::OR) {
1002 if (isIntS16Immediate(N.getOperand(1), imm))
1003 return false; // r+i can fold it if we can.
1005 // If this is an or of disjoint bitfields, we can codegen this as an add
1006 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1008 APInt LHSKnownZero, LHSKnownOne;
1009 APInt RHSKnownZero, RHSKnownOne;
1010 DAG.ComputeMaskedBits(N.getOperand(0),
1011 LHSKnownZero, LHSKnownOne);
1013 if (LHSKnownZero.getBoolValue()) {
1014 DAG.ComputeMaskedBits(N.getOperand(1),
1015 RHSKnownZero, RHSKnownOne);
1016 // If all of the bits are known zero on the LHS or RHS, the add won't
1018 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1019 Base = N.getOperand(0);
1020 Index = N.getOperand(1);
1029 // If we happen to be doing an i64 load or store into a stack slot that has
1030 // less than a 4-byte alignment, then the frame-index elimination may need to
1031 // use an indexed load or store instruction (because the offset may not be a
1032 // multiple of 4). The extra register needed to hold the offset comes from the
1033 // register scavenger, and it is possible that the scavenger will need to use
1034 // an emergency spill slot. As a result, we need to make sure that a spill slot
1035 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1037 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1038 // FIXME: This does not handle the LWA case.
1042 // NOTE: We'll exclude negative FIs here, which come from argument
1043 // lowering, because there are no known test cases triggering this problem
1044 // using packed structures (or similar). We can remove this exclusion if
1045 // we find such a test case. The reason why this is so test-case driven is
1046 // because this entire 'fixup' is only to prevent crashes (from the
1047 // register scavenger) on not-really-valid inputs. For example, if we have:
1049 // %b = bitcast i1* %a to i64*
1050 // store i64* a, i64 b
1051 // then the store should really be marked as 'align 1', but is not. If it
1052 // were marked as 'align 1' then the indexed form would have been
1053 // instruction-selected initially, and the problem this 'fixup' is preventing
1054 // won't happen regardless.
1058 MachineFunction &MF = DAG.getMachineFunction();
1059 MachineFrameInfo *MFI = MF.getFrameInfo();
1061 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1065 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1066 FuncInfo->setHasNonRISpills();
1069 /// Returns true if the address N can be represented by a base register plus
1070 /// a signed 16-bit displacement [r+imm], and if it is not better
1071 /// represented as reg+reg. If Aligned is true, only accept displacements
1072 /// suitable for STD and friends, i.e. multiples of 4.
1073 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1076 bool Aligned) const {
1077 // FIXME dl should come from parent load or store, not from address
1079 // If this can be more profitably realized as r+r, fail.
1080 if (SelectAddressRegReg(N, Disp, Base, DAG))
1083 if (N.getOpcode() == ISD::ADD) {
1085 if (isIntS16Immediate(N.getOperand(1), imm) &&
1086 (!Aligned || (imm & 3) == 0)) {
1087 Disp = DAG.getTargetConstant(imm, N.getValueType());
1088 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1089 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1090 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1092 Base = N.getOperand(0);
1094 return true; // [r+i]
1095 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1096 // Match LOAD (ADD (X, Lo(G))).
1097 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1098 && "Cannot handle constant offsets yet!");
1099 Disp = N.getOperand(1).getOperand(0); // The global address.
1100 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1101 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1102 Disp.getOpcode() == ISD::TargetConstantPool ||
1103 Disp.getOpcode() == ISD::TargetJumpTable);
1104 Base = N.getOperand(0);
1105 return true; // [&g+r]
1107 } else if (N.getOpcode() == ISD::OR) {
1109 if (isIntS16Immediate(N.getOperand(1), imm) &&
1110 (!Aligned || (imm & 3) == 0)) {
1111 // If this is an or of disjoint bitfields, we can codegen this as an add
1112 // (for better address arithmetic) if the LHS and RHS of the OR are
1113 // provably disjoint.
1114 APInt LHSKnownZero, LHSKnownOne;
1115 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1117 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1118 // If all of the bits are known zero on the LHS or RHS, the add won't
1120 Base = N.getOperand(0);
1121 Disp = DAG.getTargetConstant(imm, N.getValueType());
1125 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1126 // Loading from a constant address.
1128 // If this address fits entirely in a 16-bit sext immediate field, codegen
1131 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1132 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1133 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1134 CN->getValueType(0));
1138 // Handle 32-bit sext immediates with LIS + addr mode.
1139 if ((CN->getValueType(0) == MVT::i32 ||
1140 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1141 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1142 int Addr = (int)CN->getZExtValue();
1144 // Otherwise, break this down into an LIS + disp.
1145 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1147 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1148 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1149 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1154 Disp = DAG.getTargetConstant(0, getPointerTy());
1155 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1156 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1157 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1160 return true; // [r+0]
1163 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1164 /// represented as an indexed [r+r] operation.
1165 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1167 SelectionDAG &DAG) const {
1168 // Check to see if we can easily represent this as an [r+r] address. This
1169 // will fail if it thinks that the address is more profitably represented as
1170 // reg+imm, e.g. where imm = 0.
1171 if (SelectAddressRegReg(N, Base, Index, DAG))
1174 // If the operand is an addition, always emit this as [r+r], since this is
1175 // better (for code size, and execution, as the memop does the add for free)
1176 // than emitting an explicit add.
1177 if (N.getOpcode() == ISD::ADD) {
1178 Base = N.getOperand(0);
1179 Index = N.getOperand(1);
1183 // Otherwise, do it the hard way, using R0 as the base register.
1184 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1190 /// getPreIndexedAddressParts - returns true by value, base pointer and
1191 /// offset pointer and addressing mode by reference if the node's address
1192 /// can be legally represented as pre-indexed load / store address.
1193 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1195 ISD::MemIndexedMode &AM,
1196 SelectionDAG &DAG) const {
1197 if (DisablePPCPreinc) return false;
1203 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1204 Ptr = LD->getBasePtr();
1205 VT = LD->getMemoryVT();
1206 Alignment = LD->getAlignment();
1207 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1208 Ptr = ST->getBasePtr();
1209 VT = ST->getMemoryVT();
1210 Alignment = ST->getAlignment();
1215 // PowerPC doesn't have preinc load/store instructions for vectors.
1219 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1221 // Common code will reject creating a pre-inc form if the base pointer
1222 // is a frame index, or if N is a store and the base pointer is either
1223 // the same as or a predecessor of the value being stored. Check for
1224 // those situations here, and try with swapped Base/Offset instead.
1227 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1230 SDValue Val = cast<StoreSDNode>(N)->getValue();
1231 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1236 std::swap(Base, Offset);
1242 // LDU/STU can only handle immediates that are a multiple of 4.
1243 if (VT != MVT::i64) {
1244 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1247 // LDU/STU need an address with at least 4-byte alignment.
1251 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1255 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1256 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1257 // sext i32 to i64 when addr mode is r+i.
1258 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1259 LD->getExtensionType() == ISD::SEXTLOAD &&
1260 isa<ConstantSDNode>(Offset))
1268 //===----------------------------------------------------------------------===//
1269 // LowerOperation implementation
1270 //===----------------------------------------------------------------------===//
1272 /// GetLabelAccessInfo - Return true if we should reference labels using a
1273 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1274 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1275 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1276 HiOpFlags = PPCII::MO_HA;
1277 LoOpFlags = PPCII::MO_LO;
1279 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1280 // non-darwin platform. We don't support PIC on other platforms yet.
1281 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1282 TM.getSubtarget<PPCSubtarget>().isDarwin();
1284 HiOpFlags |= PPCII::MO_PIC_FLAG;
1285 LoOpFlags |= PPCII::MO_PIC_FLAG;
1288 // If this is a reference to a global value that requires a non-lazy-ptr, make
1289 // sure that instruction lowering adds it.
1290 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1291 HiOpFlags |= PPCII::MO_NLP_FLAG;
1292 LoOpFlags |= PPCII::MO_NLP_FLAG;
1294 if (GV->hasHiddenVisibility()) {
1295 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1296 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1303 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1304 SelectionDAG &DAG) {
1305 EVT PtrVT = HiPart.getValueType();
1306 SDValue Zero = DAG.getConstant(0, PtrVT);
1309 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1310 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1312 // With PIC, the first instruction is actually "GR+hi(&G)".
1314 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1315 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1317 // Generate non-pic code that has direct accesses to the constant pool.
1318 // The address of the global is just (hi(&g)+lo(&g)).
1319 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1322 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1323 SelectionDAG &DAG) const {
1324 EVT PtrVT = Op.getValueType();
1325 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1326 const Constant *C = CP->getConstVal();
1328 // 64-bit SVR4 ABI code is always position-independent.
1329 // The actual address of the GlobalValue is stored in the TOC.
1330 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1331 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1332 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1333 DAG.getRegister(PPC::X2, MVT::i64));
1336 unsigned MOHiFlag, MOLoFlag;
1337 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1339 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1341 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1342 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1345 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1346 EVT PtrVT = Op.getValueType();
1347 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1349 // 64-bit SVR4 ABI code is always position-independent.
1350 // The actual address of the GlobalValue is stored in the TOC.
1351 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1352 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1353 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1354 DAG.getRegister(PPC::X2, MVT::i64));
1357 unsigned MOHiFlag, MOLoFlag;
1358 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1359 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1360 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1361 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1364 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1365 SelectionDAG &DAG) const {
1366 EVT PtrVT = Op.getValueType();
1368 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1370 unsigned MOHiFlag, MOLoFlag;
1371 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1372 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1373 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1374 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1377 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1378 SelectionDAG &DAG) const {
1380 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1382 const GlobalValue *GV = GA->getGlobal();
1383 EVT PtrVT = getPointerTy();
1384 bool is64bit = PPCSubTarget.isPPC64();
1386 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1388 if (Model == TLSModel::LocalExec) {
1389 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1390 PPCII::MO_TPREL_HA);
1391 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1392 PPCII::MO_TPREL_LO);
1393 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1394 is64bit ? MVT::i64 : MVT::i32);
1395 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1396 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1400 llvm_unreachable("only local-exec is currently supported for ppc32");
1402 if (Model == TLSModel::InitialExec) {
1403 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1404 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1406 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1407 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1408 PtrVT, GOTReg, TGA);
1409 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1410 PtrVT, TGA, TPOffsetHi);
1411 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1414 if (Model == TLSModel::GeneralDynamic) {
1415 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1416 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1417 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1419 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1422 // We need a chain node, and don't have one handy. The underlying
1423 // call has no side effects, so using the function entry node
1425 SDValue Chain = DAG.getEntryNode();
1426 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1427 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1428 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1429 PtrVT, ParmReg, TGA);
1430 // The return value from GET_TLS_ADDR really is in X3 already, but
1431 // some hacks are needed here to tie everything together. The extra
1432 // copies dissolve during subsequent transforms.
1433 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1434 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1437 if (Model == TLSModel::LocalDynamic) {
1438 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1439 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1440 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1442 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1445 // We need a chain node, and don't have one handy. The underlying
1446 // call has no side effects, so using the function entry node
1448 SDValue Chain = DAG.getEntryNode();
1449 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1450 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1451 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1452 PtrVT, ParmReg, TGA);
1453 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1454 // some hacks are needed here to tie everything together. The extra
1455 // copies dissolve during subsequent transforms.
1456 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1457 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1458 Chain, ParmReg, TGA);
1459 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1462 llvm_unreachable("Unknown TLS model!");
1465 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1466 SelectionDAG &DAG) const {
1467 EVT PtrVT = Op.getValueType();
1468 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1470 const GlobalValue *GV = GSDN->getGlobal();
1472 // 64-bit SVR4 ABI code is always position-independent.
1473 // The actual address of the GlobalValue is stored in the TOC.
1474 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1475 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1476 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1477 DAG.getRegister(PPC::X2, MVT::i64));
1480 unsigned MOHiFlag, MOLoFlag;
1481 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1484 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1486 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1488 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1490 // If the global reference is actually to a non-lazy-pointer, we have to do an
1491 // extra load to get the address of the global.
1492 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1493 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1494 false, false, false, 0);
1498 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1499 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1502 // If we're comparing for equality to zero, expose the fact that this is
1503 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1504 // fold the new nodes.
1505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1506 if (C->isNullValue() && CC == ISD::SETEQ) {
1507 EVT VT = Op.getOperand(0).getValueType();
1508 SDValue Zext = Op.getOperand(0);
1509 if (VT.bitsLT(MVT::i32)) {
1511 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1513 unsigned Log2b = Log2_32(VT.getSizeInBits());
1514 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1515 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1516 DAG.getConstant(Log2b, MVT::i32));
1517 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1519 // Leave comparisons against 0 and -1 alone for now, since they're usually
1520 // optimized. FIXME: revisit this when we can custom lower all setcc
1522 if (C->isAllOnesValue() || C->isNullValue())
1526 // If we have an integer seteq/setne, turn it into a compare against zero
1527 // by xor'ing the rhs with the lhs, which is faster than setting a
1528 // condition register, reading it back out, and masking the correct bit. The
1529 // normal approach here uses sub to do this instead of xor. Using xor exposes
1530 // the result to other bit-twiddling opportunities.
1531 EVT LHSVT = Op.getOperand(0).getValueType();
1532 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1533 EVT VT = Op.getValueType();
1534 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1536 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1541 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1542 const PPCSubtarget &Subtarget) const {
1543 SDNode *Node = Op.getNode();
1544 EVT VT = Node->getValueType(0);
1545 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1546 SDValue InChain = Node->getOperand(0);
1547 SDValue VAListPtr = Node->getOperand(1);
1548 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1551 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1554 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1555 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1557 InChain = GprIndex.getValue(1);
1559 if (VT == MVT::i64) {
1560 // Check if GprIndex is even
1561 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1562 DAG.getConstant(1, MVT::i32));
1563 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1564 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1565 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1566 DAG.getConstant(1, MVT::i32));
1567 // Align GprIndex to be even if it isn't
1568 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1572 // fpr index is 1 byte after gpr
1573 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1574 DAG.getConstant(1, MVT::i32));
1577 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1578 FprPtr, MachinePointerInfo(SV), MVT::i8,
1580 InChain = FprIndex.getValue(1);
1582 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1583 DAG.getConstant(8, MVT::i32));
1585 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1586 DAG.getConstant(4, MVT::i32));
1589 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1590 MachinePointerInfo(), false, false,
1592 InChain = OverflowArea.getValue(1);
1594 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1595 MachinePointerInfo(), false, false,
1597 InChain = RegSaveArea.getValue(1);
1599 // select overflow_area if index > 8
1600 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1601 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1603 // adjustment constant gpr_index * 4/8
1604 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1605 VT.isInteger() ? GprIndex : FprIndex,
1606 DAG.getConstant(VT.isInteger() ? 4 : 8,
1609 // OurReg = RegSaveArea + RegConstant
1610 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1613 // Floating types are 32 bytes into RegSaveArea
1614 if (VT.isFloatingPoint())
1615 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1616 DAG.getConstant(32, MVT::i32));
1618 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1619 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1620 VT.isInteger() ? GprIndex : FprIndex,
1621 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1624 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1625 VT.isInteger() ? VAListPtr : FprPtr,
1626 MachinePointerInfo(SV),
1627 MVT::i8, false, false, 0);
1629 // determine if we should load from reg_save_area or overflow_area
1630 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1632 // increase overflow_area by 4/8 if gpr/fpr > 8
1633 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1634 DAG.getConstant(VT.isInteger() ? 4 : 8,
1637 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1640 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1642 MachinePointerInfo(),
1643 MVT::i32, false, false, 0);
1645 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1646 false, false, false, 0);
1649 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1650 const PPCSubtarget &Subtarget) const {
1651 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1653 // We have to copy the entire va_list struct:
1654 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1655 return DAG.getMemcpy(Op.getOperand(0), Op,
1656 Op.getOperand(1), Op.getOperand(2),
1657 DAG.getConstant(12, MVT::i32), 8, false, true,
1658 MachinePointerInfo(), MachinePointerInfo());
1661 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1662 SelectionDAG &DAG) const {
1663 return Op.getOperand(0);
1666 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1667 SelectionDAG &DAG) const {
1668 SDValue Chain = Op.getOperand(0);
1669 SDValue Trmp = Op.getOperand(1); // trampoline
1670 SDValue FPtr = Op.getOperand(2); // nested function
1671 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1674 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1675 bool isPPC64 = (PtrVT == MVT::i64);
1677 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1680 TargetLowering::ArgListTy Args;
1681 TargetLowering::ArgListEntry Entry;
1683 Entry.Ty = IntPtrTy;
1684 Entry.Node = Trmp; Args.push_back(Entry);
1686 // TrampSize == (isPPC64 ? 48 : 40);
1687 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1688 isPPC64 ? MVT::i64 : MVT::i32);
1689 Args.push_back(Entry);
1691 Entry.Node = FPtr; Args.push_back(Entry);
1692 Entry.Node = Nest; Args.push_back(Entry);
1694 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1695 TargetLowering::CallLoweringInfo CLI(Chain,
1696 Type::getVoidTy(*DAG.getContext()),
1697 false, false, false, false, 0,
1699 /*isTailCall=*/false,
1700 /*doesNotRet=*/false,
1701 /*isReturnValueUsed=*/true,
1702 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1704 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1706 return CallResult.second;
1709 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1710 const PPCSubtarget &Subtarget) const {
1711 MachineFunction &MF = DAG.getMachineFunction();
1712 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1716 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1717 // vastart just stores the address of the VarArgsFrameIndex slot into the
1718 // memory location argument.
1719 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1720 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1721 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1722 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1723 MachinePointerInfo(SV),
1727 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1728 // We suppose the given va_list is already allocated.
1731 // char gpr; /* index into the array of 8 GPRs
1732 // * stored in the register save area
1733 // * gpr=0 corresponds to r3,
1734 // * gpr=1 to r4, etc.
1736 // char fpr; /* index into the array of 8 FPRs
1737 // * stored in the register save area
1738 // * fpr=0 corresponds to f1,
1739 // * fpr=1 to f2, etc.
1741 // char *overflow_arg_area;
1742 // /* location on stack that holds
1743 // * the next overflow argument
1745 // char *reg_save_area;
1746 // /* where r3:r10 and f1:f8 (if saved)
1752 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1753 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1756 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1758 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1760 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1763 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1764 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1766 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1767 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1769 uint64_t FPROffset = 1;
1770 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1772 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1774 // Store first byte : number of int regs
1775 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1777 MachinePointerInfo(SV),
1778 MVT::i8, false, false, 0);
1779 uint64_t nextOffset = FPROffset;
1780 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1783 // Store second byte : number of float regs
1784 SDValue secondStore =
1785 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1786 MachinePointerInfo(SV, nextOffset), MVT::i8,
1788 nextOffset += StackOffset;
1789 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1791 // Store second word : arguments given on stack
1792 SDValue thirdStore =
1793 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1794 MachinePointerInfo(SV, nextOffset),
1796 nextOffset += FrameOffset;
1797 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1799 // Store third word : arguments given in registers
1800 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1801 MachinePointerInfo(SV, nextOffset),
1806 #include "PPCGenCallingConv.inc"
1808 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1809 CCValAssign::LocInfo &LocInfo,
1810 ISD::ArgFlagsTy &ArgFlags,
1815 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1817 CCValAssign::LocInfo &LocInfo,
1818 ISD::ArgFlagsTy &ArgFlags,
1820 static const uint16_t ArgRegs[] = {
1821 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1822 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1824 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1826 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1828 // Skip one register if the first unallocated register has an even register
1829 // number and there are still argument registers available which have not been
1830 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1831 // need to skip a register if RegNum is odd.
1832 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1833 State.AllocateReg(ArgRegs[RegNum]);
1836 // Always return false here, as this function only makes sure that the first
1837 // unallocated register has an odd register number and does not actually
1838 // allocate a register for the current argument.
1842 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1844 CCValAssign::LocInfo &LocInfo,
1845 ISD::ArgFlagsTy &ArgFlags,
1847 static const uint16_t ArgRegs[] = {
1848 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1852 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1854 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1856 // If there is only one Floating-point register left we need to put both f64
1857 // values of a split ppc_fp128 value on the stack.
1858 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1859 State.AllocateReg(ArgRegs[RegNum]);
1862 // Always return false here, as this function only makes sure that the two f64
1863 // values a ppc_fp128 value is split into are both passed in registers or both
1864 // passed on the stack and does not actually allocate a register for the
1865 // current argument.
1869 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1871 static const uint16_t *GetFPR() {
1872 static const uint16_t FPR[] = {
1873 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1874 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1880 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1882 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1883 unsigned PtrByteSize) {
1884 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1885 if (Flags.isByVal())
1886 ArgSize = Flags.getByValSize();
1887 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1893 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1894 CallingConv::ID CallConv, bool isVarArg,
1895 const SmallVectorImpl<ISD::InputArg>
1897 SDLoc dl, SelectionDAG &DAG,
1898 SmallVectorImpl<SDValue> &InVals)
1900 if (PPCSubTarget.isSVR4ABI()) {
1901 if (PPCSubTarget.isPPC64())
1902 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1905 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1908 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1914 PPCTargetLowering::LowerFormalArguments_32SVR4(
1916 CallingConv::ID CallConv, bool isVarArg,
1917 const SmallVectorImpl<ISD::InputArg>
1919 SDLoc dl, SelectionDAG &DAG,
1920 SmallVectorImpl<SDValue> &InVals) const {
1922 // 32-bit SVR4 ABI Stack Frame Layout:
1923 // +-----------------------------------+
1924 // +--> | Back chain |
1925 // | +-----------------------------------+
1926 // | | Floating-point register save area |
1927 // | +-----------------------------------+
1928 // | | General register save area |
1929 // | +-----------------------------------+
1930 // | | CR save word |
1931 // | +-----------------------------------+
1932 // | | VRSAVE save word |
1933 // | +-----------------------------------+
1934 // | | Alignment padding |
1935 // | +-----------------------------------+
1936 // | | Vector register save area |
1937 // | +-----------------------------------+
1938 // | | Local variable space |
1939 // | +-----------------------------------+
1940 // | | Parameter list area |
1941 // | +-----------------------------------+
1942 // | | LR save word |
1943 // | +-----------------------------------+
1944 // SP--> +--- | Back chain |
1945 // +-----------------------------------+
1948 // System V Application Binary Interface PowerPC Processor Supplement
1949 // AltiVec Technology Programming Interface Manual
1951 MachineFunction &MF = DAG.getMachineFunction();
1952 MachineFrameInfo *MFI = MF.getFrameInfo();
1953 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1955 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1956 // Potential tail calls could cause overwriting of argument stack slots.
1957 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1958 (CallConv == CallingConv::Fast));
1959 unsigned PtrByteSize = 4;
1961 // Assign locations to all of the incoming arguments.
1962 SmallVector<CCValAssign, 16> ArgLocs;
1963 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1964 getTargetMachine(), ArgLocs, *DAG.getContext());
1966 // Reserve space for the linkage area on the stack.
1967 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1969 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1971 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1972 CCValAssign &VA = ArgLocs[i];
1974 // Arguments stored in registers.
1975 if (VA.isRegLoc()) {
1976 const TargetRegisterClass *RC;
1977 EVT ValVT = VA.getValVT();
1979 switch (ValVT.getSimpleVT().SimpleTy) {
1981 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1983 RC = &PPC::GPRCRegClass;
1986 RC = &PPC::F4RCRegClass;
1989 RC = &PPC::F8RCRegClass;
1995 RC = &PPC::VRRCRegClass;
1999 // Transform the arguments stored in physical registers into virtual ones.
2000 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2001 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2003 InVals.push_back(ArgValue);
2005 // Argument stored in memory.
2006 assert(VA.isMemLoc());
2008 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2009 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2012 // Create load nodes to retrieve arguments from the stack.
2013 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2014 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2015 MachinePointerInfo(),
2016 false, false, false, 0));
2020 // Assign locations to all of the incoming aggregate by value arguments.
2021 // Aggregates passed by value are stored in the local variable space of the
2022 // caller's stack frame, right above the parameter list area.
2023 SmallVector<CCValAssign, 16> ByValArgLocs;
2024 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2025 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2027 // Reserve stack space for the allocations in CCInfo.
2028 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2030 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2032 // Area that is at least reserved in the caller of this function.
2033 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2035 // Set the size that is at least reserved in caller of this function. Tail
2036 // call optimized function's reserved stack space needs to be aligned so that
2037 // taking the difference between two stack areas will result in an aligned
2039 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2042 std::max(MinReservedArea,
2043 PPCFrameLowering::getMinCallFrameSize(false, false));
2045 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2046 getStackAlignment();
2047 unsigned AlignMask = TargetAlign-1;
2048 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2050 FI->setMinReservedArea(MinReservedArea);
2052 SmallVector<SDValue, 8> MemOps;
2054 // If the function takes variable number of arguments, make a frame index for
2055 // the start of the first vararg value... for expansion of llvm.va_start.
2057 static const uint16_t GPArgRegs[] = {
2058 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2059 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2061 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2063 static const uint16_t FPArgRegs[] = {
2064 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2067 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2069 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2071 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2074 // Make room for NumGPArgRegs and NumFPArgRegs.
2075 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2076 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2078 FuncInfo->setVarArgsStackOffset(
2079 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2080 CCInfo.getNextStackOffset(), true));
2082 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2083 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2085 // The fixed integer arguments of a variadic function are stored to the
2086 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2087 // the result of va_next.
2088 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2089 // Get an existing live-in vreg, or add a new one.
2090 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2092 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2094 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2095 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2096 MachinePointerInfo(), false, false, 0);
2097 MemOps.push_back(Store);
2098 // Increment the address by four for the next argument to store
2099 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2100 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2103 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2105 // The double arguments are stored to the VarArgsFrameIndex
2107 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2108 // Get an existing live-in vreg, or add a new one.
2109 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2111 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2113 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2114 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2115 MachinePointerInfo(), false, false, 0);
2116 MemOps.push_back(Store);
2117 // Increment the address by eight for the next argument to store
2118 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2120 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2124 if (!MemOps.empty())
2125 Chain = DAG.getNode(ISD::TokenFactor, dl,
2126 MVT::Other, &MemOps[0], MemOps.size());
2131 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2132 // value to MVT::i64 and then truncate to the correct register size.
2134 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2135 SelectionDAG &DAG, SDValue ArgVal,
2138 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2139 DAG.getValueType(ObjectVT));
2140 else if (Flags.isZExt())
2141 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2142 DAG.getValueType(ObjectVT));
2144 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2147 // Set the size that is at least reserved in caller of this function. Tail
2148 // call optimized functions' reserved stack space needs to be aligned so that
2149 // taking the difference between two stack areas will result in an aligned
2152 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2153 unsigned nAltivecParamsAtEnd,
2154 unsigned MinReservedArea,
2155 bool isPPC64) const {
2156 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2157 // Add the Altivec parameters at the end, if needed.
2158 if (nAltivecParamsAtEnd) {
2159 MinReservedArea = ((MinReservedArea+15)/16)*16;
2160 MinReservedArea += 16*nAltivecParamsAtEnd;
2163 std::max(MinReservedArea,
2164 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2165 unsigned TargetAlign
2166 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2167 getStackAlignment();
2168 unsigned AlignMask = TargetAlign-1;
2169 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2170 FI->setMinReservedArea(MinReservedArea);
2174 PPCTargetLowering::LowerFormalArguments_64SVR4(
2176 CallingConv::ID CallConv, bool isVarArg,
2177 const SmallVectorImpl<ISD::InputArg>
2179 SDLoc dl, SelectionDAG &DAG,
2180 SmallVectorImpl<SDValue> &InVals) const {
2181 // TODO: add description of PPC stack frame format, or at least some docs.
2183 MachineFunction &MF = DAG.getMachineFunction();
2184 MachineFrameInfo *MFI = MF.getFrameInfo();
2185 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2187 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2188 // Potential tail calls could cause overwriting of argument stack slots.
2189 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2190 (CallConv == CallingConv::Fast));
2191 unsigned PtrByteSize = 8;
2193 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2194 // Area that is at least reserved in caller of this function.
2195 unsigned MinReservedArea = ArgOffset;
2197 static const uint16_t GPR[] = {
2198 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2199 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2202 static const uint16_t *FPR = GetFPR();
2204 static const uint16_t VR[] = {
2205 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2206 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2209 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2210 const unsigned Num_FPR_Regs = 13;
2211 const unsigned Num_VR_Regs = array_lengthof(VR);
2213 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2215 // Add DAG nodes to load the arguments or copy them out of registers. On
2216 // entry to a function on PPC, the arguments start after the linkage area,
2217 // although the first ones are often in registers.
2219 SmallVector<SDValue, 8> MemOps;
2220 unsigned nAltivecParamsAtEnd = 0;
2221 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2222 unsigned CurArgIdx = 0;
2223 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2225 bool needsLoad = false;
2226 EVT ObjectVT = Ins[ArgNo].VT;
2227 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2228 unsigned ArgSize = ObjSize;
2229 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2230 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2231 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2233 unsigned CurArgOffset = ArgOffset;
2235 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2236 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2237 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2239 MinReservedArea = ((MinReservedArea+15)/16)*16;
2240 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2244 nAltivecParamsAtEnd++;
2246 // Calculate min reserved area.
2247 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2251 // FIXME the codegen can be much improved in some cases.
2252 // We do not have to keep everything in memory.
2253 if (Flags.isByVal()) {
2254 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2255 ObjSize = Flags.getByValSize();
2256 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2257 // Empty aggregate parameters do not take up registers. Examples:
2261 // etc. However, we have to provide a place-holder in InVals, so
2262 // pretend we have an 8-byte item at the current address for that
2265 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2266 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2267 InVals.push_back(FIN);
2270 // All aggregates smaller than 8 bytes must be passed right-justified.
2271 if (ObjSize < PtrByteSize)
2272 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2273 // The value of the object is its address.
2274 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2275 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2276 InVals.push_back(FIN);
2279 if (GPR_idx != Num_GPR_Regs) {
2280 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2281 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2284 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2285 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2286 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2287 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2288 MachinePointerInfo(FuncArg, CurArgOffset),
2289 ObjType, false, false, 0);
2291 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2292 // store the whole register as-is to the parameter save area
2293 // slot. The address of the parameter was already calculated
2294 // above (InVals.push_back(FIN)) to be the right-justified
2295 // offset within the slot. For this store, we need a new
2296 // frame index that points at the beginning of the slot.
2297 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2298 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2299 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2300 MachinePointerInfo(FuncArg, ArgOffset),
2304 MemOps.push_back(Store);
2307 // Whether we copied from a register or not, advance the offset
2308 // into the parameter save area by a full doubleword.
2309 ArgOffset += PtrByteSize;
2313 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2314 // Store whatever pieces of the object are in registers
2315 // to memory. ArgOffset will be the address of the beginning
2317 if (GPR_idx != Num_GPR_Regs) {
2319 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2320 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2321 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2322 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2323 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2324 MachinePointerInfo(FuncArg, ArgOffset),
2326 MemOps.push_back(Store);
2328 ArgOffset += PtrByteSize;
2330 ArgOffset += ArgSize - j;
2337 switch (ObjectVT.getSimpleVT().SimpleTy) {
2338 default: llvm_unreachable("Unhandled argument type!");
2341 if (GPR_idx != Num_GPR_Regs) {
2342 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2343 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2345 if (ObjectVT == MVT::i32)
2346 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2347 // value to MVT::i64 and then truncate to the correct register size.
2348 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2353 ArgSize = PtrByteSize;
2360 // Every 8 bytes of argument space consumes one of the GPRs available for
2361 // argument passing.
2362 if (GPR_idx != Num_GPR_Regs) {
2365 if (FPR_idx != Num_FPR_Regs) {
2368 if (ObjectVT == MVT::f32)
2369 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2371 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2373 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2377 ArgSize = PtrByteSize;
2386 // Note that vector arguments in registers don't reserve stack space,
2387 // except in varargs functions.
2388 if (VR_idx != Num_VR_Regs) {
2389 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2390 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2392 while ((ArgOffset % 16) != 0) {
2393 ArgOffset += PtrByteSize;
2394 if (GPR_idx != Num_GPR_Regs)
2398 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2402 // Vectors are aligned.
2403 ArgOffset = ((ArgOffset+15)/16)*16;
2404 CurArgOffset = ArgOffset;
2411 // We need to load the argument to a virtual register if we determined
2412 // above that we ran out of physical registers of the appropriate type.
2414 int FI = MFI->CreateFixedObject(ObjSize,
2415 CurArgOffset + (ArgSize - ObjSize),
2417 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2418 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2419 false, false, false, 0);
2422 InVals.push_back(ArgVal);
2425 // Set the size that is at least reserved in caller of this function. Tail
2426 // call optimized functions' reserved stack space needs to be aligned so that
2427 // taking the difference between two stack areas will result in an aligned
2429 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2431 // If the function takes variable number of arguments, make a frame index for
2432 // the start of the first vararg value... for expansion of llvm.va_start.
2434 int Depth = ArgOffset;
2436 FuncInfo->setVarArgsFrameIndex(
2437 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2438 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2440 // If this function is vararg, store any remaining integer argument regs
2441 // to their spots on the stack so that they may be loaded by deferencing the
2442 // result of va_next.
2443 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2444 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2445 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2446 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2447 MachinePointerInfo(), false, false, 0);
2448 MemOps.push_back(Store);
2449 // Increment the address by four for the next argument to store
2450 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2451 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2455 if (!MemOps.empty())
2456 Chain = DAG.getNode(ISD::TokenFactor, dl,
2457 MVT::Other, &MemOps[0], MemOps.size());
2463 PPCTargetLowering::LowerFormalArguments_Darwin(
2465 CallingConv::ID CallConv, bool isVarArg,
2466 const SmallVectorImpl<ISD::InputArg>
2468 SDLoc dl, SelectionDAG &DAG,
2469 SmallVectorImpl<SDValue> &InVals) const {
2470 // TODO: add description of PPC stack frame format, or at least some docs.
2472 MachineFunction &MF = DAG.getMachineFunction();
2473 MachineFrameInfo *MFI = MF.getFrameInfo();
2474 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2476 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2477 bool isPPC64 = PtrVT == MVT::i64;
2478 // Potential tail calls could cause overwriting of argument stack slots.
2479 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2480 (CallConv == CallingConv::Fast));
2481 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2483 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2484 // Area that is at least reserved in caller of this function.
2485 unsigned MinReservedArea = ArgOffset;
2487 static const uint16_t GPR_32[] = { // 32-bit registers.
2488 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2489 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2491 static const uint16_t GPR_64[] = { // 64-bit registers.
2492 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2493 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2496 static const uint16_t *FPR = GetFPR();
2498 static const uint16_t VR[] = {
2499 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2500 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2503 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2504 const unsigned Num_FPR_Regs = 13;
2505 const unsigned Num_VR_Regs = array_lengthof( VR);
2507 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2509 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2511 // In 32-bit non-varargs functions, the stack space for vectors is after the
2512 // stack space for non-vectors. We do not use this space unless we have
2513 // too many vectors to fit in registers, something that only occurs in
2514 // constructed examples:), but we have to walk the arglist to figure
2515 // that out...for the pathological case, compute VecArgOffset as the
2516 // start of the vector parameter area. Computing VecArgOffset is the
2517 // entire point of the following loop.
2518 unsigned VecArgOffset = ArgOffset;
2519 if (!isVarArg && !isPPC64) {
2520 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2522 EVT ObjectVT = Ins[ArgNo].VT;
2523 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2525 if (Flags.isByVal()) {
2526 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2527 unsigned ObjSize = Flags.getByValSize();
2529 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2530 VecArgOffset += ArgSize;
2534 switch(ObjectVT.getSimpleVT().SimpleTy) {
2535 default: llvm_unreachable("Unhandled argument type!");
2540 case MVT::i64: // PPC64
2542 // FIXME: We are guaranteed to be !isPPC64 at this point.
2543 // Does MVT::i64 apply?
2550 // Nothing to do, we're only looking at Nonvector args here.
2555 // We've found where the vector parameter area in memory is. Skip the
2556 // first 12 parameters; these don't use that memory.
2557 VecArgOffset = ((VecArgOffset+15)/16)*16;
2558 VecArgOffset += 12*16;
2560 // Add DAG nodes to load the arguments or copy them out of registers. On
2561 // entry to a function on PPC, the arguments start after the linkage area,
2562 // although the first ones are often in registers.
2564 SmallVector<SDValue, 8> MemOps;
2565 unsigned nAltivecParamsAtEnd = 0;
2566 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2567 unsigned CurArgIdx = 0;
2568 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2570 bool needsLoad = false;
2571 EVT ObjectVT = Ins[ArgNo].VT;
2572 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2573 unsigned ArgSize = ObjSize;
2574 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2575 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2576 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2578 unsigned CurArgOffset = ArgOffset;
2580 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2581 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2582 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2583 if (isVarArg || isPPC64) {
2584 MinReservedArea = ((MinReservedArea+15)/16)*16;
2585 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2588 } else nAltivecParamsAtEnd++;
2590 // Calculate min reserved area.
2591 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2595 // FIXME the codegen can be much improved in some cases.
2596 // We do not have to keep everything in memory.
2597 if (Flags.isByVal()) {
2598 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2599 ObjSize = Flags.getByValSize();
2600 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2601 // Objects of size 1 and 2 are right justified, everything else is
2602 // left justified. This means the memory address is adjusted forwards.
2603 if (ObjSize==1 || ObjSize==2) {
2604 CurArgOffset = CurArgOffset + (4 - ObjSize);
2606 // The value of the object is its address.
2607 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2608 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2609 InVals.push_back(FIN);
2610 if (ObjSize==1 || ObjSize==2) {
2611 if (GPR_idx != Num_GPR_Regs) {
2614 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2616 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2617 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2618 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2619 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2620 MachinePointerInfo(FuncArg,
2622 ObjType, false, false, 0);
2623 MemOps.push_back(Store);
2627 ArgOffset += PtrByteSize;
2631 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2632 // Store whatever pieces of the object are in registers
2633 // to memory. ArgOffset will be the address of the beginning
2635 if (GPR_idx != Num_GPR_Regs) {
2638 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2640 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2641 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2642 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2643 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2644 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2645 MachinePointerInfo(FuncArg, ArgOffset),
2647 MemOps.push_back(Store);
2649 ArgOffset += PtrByteSize;
2651 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2658 switch (ObjectVT.getSimpleVT().SimpleTy) {
2659 default: llvm_unreachable("Unhandled argument type!");
2662 if (GPR_idx != Num_GPR_Regs) {
2663 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2664 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2668 ArgSize = PtrByteSize;
2670 // All int arguments reserve stack space in the Darwin ABI.
2671 ArgOffset += PtrByteSize;
2675 case MVT::i64: // PPC64
2676 if (GPR_idx != Num_GPR_Regs) {
2677 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2678 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2680 if (ObjectVT == MVT::i32)
2681 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2682 // value to MVT::i64 and then truncate to the correct register size.
2683 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2688 ArgSize = PtrByteSize;
2690 // All int arguments reserve stack space in the Darwin ABI.
2696 // Every 4 bytes of argument space consumes one of the GPRs available for
2697 // argument passing.
2698 if (GPR_idx != Num_GPR_Regs) {
2700 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2703 if (FPR_idx != Num_FPR_Regs) {
2706 if (ObjectVT == MVT::f32)
2707 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2709 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2711 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2717 // All FP arguments reserve stack space in the Darwin ABI.
2718 ArgOffset += isPPC64 ? 8 : ObjSize;
2724 // Note that vector arguments in registers don't reserve stack space,
2725 // except in varargs functions.
2726 if (VR_idx != Num_VR_Regs) {
2727 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2728 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2730 while ((ArgOffset % 16) != 0) {
2731 ArgOffset += PtrByteSize;
2732 if (GPR_idx != Num_GPR_Regs)
2736 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2740 if (!isVarArg && !isPPC64) {
2741 // Vectors go after all the nonvectors.
2742 CurArgOffset = VecArgOffset;
2745 // Vectors are aligned.
2746 ArgOffset = ((ArgOffset+15)/16)*16;
2747 CurArgOffset = ArgOffset;
2755 // We need to load the argument to a virtual register if we determined above
2756 // that we ran out of physical registers of the appropriate type.
2758 int FI = MFI->CreateFixedObject(ObjSize,
2759 CurArgOffset + (ArgSize - ObjSize),
2761 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2762 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2763 false, false, false, 0);
2766 InVals.push_back(ArgVal);
2769 // Set the size that is at least reserved in caller of this function. Tail
2770 // call optimized functions' reserved stack space needs to be aligned so that
2771 // taking the difference between two stack areas will result in an aligned
2773 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2775 // If the function takes variable number of arguments, make a frame index for
2776 // the start of the first vararg value... for expansion of llvm.va_start.
2778 int Depth = ArgOffset;
2780 FuncInfo->setVarArgsFrameIndex(
2781 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2783 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2785 // If this function is vararg, store any remaining integer argument regs
2786 // to their spots on the stack so that they may be loaded by deferencing the
2787 // result of va_next.
2788 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2792 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2794 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2796 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2797 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2798 MachinePointerInfo(), false, false, 0);
2799 MemOps.push_back(Store);
2800 // Increment the address by four for the next argument to store
2801 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2802 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2806 if (!MemOps.empty())
2807 Chain = DAG.getNode(ISD::TokenFactor, dl,
2808 MVT::Other, &MemOps[0], MemOps.size());
2813 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2814 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2816 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2820 const SmallVectorImpl<ISD::OutputArg>
2822 const SmallVectorImpl<SDValue> &OutVals,
2823 unsigned &nAltivecParamsAtEnd) {
2824 // Count how many bytes are to be pushed on the stack, including the linkage
2825 // area, and parameter passing area. We start with 24/48 bytes, which is
2826 // prereserved space for [SP][CR][LR][3 x unused].
2827 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2828 unsigned NumOps = Outs.size();
2829 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2831 // Add up all the space actually used.
2832 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2833 // they all go in registers, but we must reserve stack space for them for
2834 // possible use by the caller. In varargs or 64-bit calls, parameters are
2835 // assigned stack space in order, with padding so Altivec parameters are
2837 nAltivecParamsAtEnd = 0;
2838 for (unsigned i = 0; i != NumOps; ++i) {
2839 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2840 EVT ArgVT = Outs[i].VT;
2841 // Varargs Altivec parameters are padded to a 16 byte boundary.
2842 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2843 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2844 if (!isVarArg && !isPPC64) {
2845 // Non-varargs Altivec parameters go after all the non-Altivec
2846 // parameters; handle those later so we know how much padding we need.
2847 nAltivecParamsAtEnd++;
2850 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2851 NumBytes = ((NumBytes+15)/16)*16;
2853 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2856 // Allow for Altivec parameters at the end, if needed.
2857 if (nAltivecParamsAtEnd) {
2858 NumBytes = ((NumBytes+15)/16)*16;
2859 NumBytes += 16*nAltivecParamsAtEnd;
2862 // The prolog code of the callee may store up to 8 GPR argument registers to
2863 // the stack, allowing va_start to index over them in memory if its varargs.
2864 // Because we cannot tell if this is needed on the caller side, we have to
2865 // conservatively assume that it is needed. As such, make sure we have at
2866 // least enough stack space for the caller to store the 8 GPRs.
2867 NumBytes = std::max(NumBytes,
2868 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2870 // Tail call needs the stack to be aligned.
2871 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2872 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2873 getFrameLowering()->getStackAlignment();
2874 unsigned AlignMask = TargetAlign-1;
2875 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2881 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2882 /// adjusted to accommodate the arguments for the tailcall.
2883 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2884 unsigned ParamSize) {
2886 if (!isTailCall) return 0;
2888 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2889 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2890 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2891 // Remember only if the new adjustement is bigger.
2892 if (SPDiff < FI->getTailCallSPDelta())
2893 FI->setTailCallSPDelta(SPDiff);
2898 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2899 /// for tail call optimization. Targets which want to do tail call
2900 /// optimization should implement this function.
2902 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2903 CallingConv::ID CalleeCC,
2905 const SmallVectorImpl<ISD::InputArg> &Ins,
2906 SelectionDAG& DAG) const {
2907 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2910 // Variable argument functions are not supported.
2914 MachineFunction &MF = DAG.getMachineFunction();
2915 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2916 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2917 // Functions containing by val parameters are not supported.
2918 for (unsigned i = 0; i != Ins.size(); i++) {
2919 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2920 if (Flags.isByVal()) return false;
2923 // Non PIC/GOT tail calls are supported.
2924 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2927 // At the moment we can only do local tail calls (in same module, hidden
2928 // or protected) if we are generating PIC.
2929 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2930 return G->getGlobal()->hasHiddenVisibility()
2931 || G->getGlobal()->hasProtectedVisibility();
2937 /// isCallCompatibleAddress - Return the immediate to use if the specified
2938 /// 32-bit value is representable in the immediate field of a BxA instruction.
2939 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2940 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2943 int Addr = C->getZExtValue();
2944 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2945 SignExtend32<26>(Addr) != Addr)
2946 return 0; // Top 6 bits have to be sext of immediate.
2948 return DAG.getConstant((int)C->getZExtValue() >> 2,
2949 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2954 struct TailCallArgumentInfo {
2959 TailCallArgumentInfo() : FrameIdx(0) {}
2964 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2966 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2968 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
2969 SmallVectorImpl<SDValue> &MemOpChains,
2971 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2972 SDValue Arg = TailCallArgs[i].Arg;
2973 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2974 int FI = TailCallArgs[i].FrameIdx;
2975 // Store relative to framepointer.
2976 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2977 MachinePointerInfo::getFixedStack(FI),
2982 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2983 /// the appropriate stack slot for the tail call optimized function call.
2984 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2985 MachineFunction &MF,
2994 // Calculate the new stack slot for the return address.
2995 int SlotSize = isPPC64 ? 8 : 4;
2996 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2998 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2999 NewRetAddrLoc, true);
3000 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3001 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3002 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3003 MachinePointerInfo::getFixedStack(NewRetAddr),
3006 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3007 // slot as the FP is never overwritten.
3010 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3011 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3013 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3014 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3015 MachinePointerInfo::getFixedStack(NewFPIdx),
3022 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3023 /// the position of the argument.
3025 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3026 SDValue Arg, int SPDiff, unsigned ArgOffset,
3027 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3028 int Offset = ArgOffset + SPDiff;
3029 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3030 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3031 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3032 SDValue FIN = DAG.getFrameIndex(FI, VT);
3033 TailCallArgumentInfo Info;
3035 Info.FrameIdxOp = FIN;
3037 TailCallArguments.push_back(Info);
3040 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3041 /// stack slot. Returns the chain as result and the loaded frame pointers in
3042 /// LROpOut/FPOpout. Used when tail calling.
3043 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3051 // Load the LR and FP stack slot for later adjusting.
3052 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3053 LROpOut = getReturnAddrFrameIndex(DAG);
3054 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3055 false, false, false, 0);
3056 Chain = SDValue(LROpOut.getNode(), 1);
3058 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3059 // slot as the FP is never overwritten.
3061 FPOpOut = getFramePointerFrameIndex(DAG);
3062 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3063 false, false, false, 0);
3064 Chain = SDValue(FPOpOut.getNode(), 1);
3070 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3071 /// by "Src" to address "Dst" of size "Size". Alignment information is
3072 /// specified by the specific parameter attribute. The copy will be passed as
3073 /// a byval function parameter.
3074 /// Sometimes what we are copying is the end of a larger object, the part that
3075 /// does not fit in registers.
3077 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3078 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3080 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3081 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3082 false, false, MachinePointerInfo(0),
3083 MachinePointerInfo(0));
3086 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3089 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3090 SDValue Arg, SDValue PtrOff, int SPDiff,
3091 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3092 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3093 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3095 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3100 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3102 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3103 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3104 DAG.getConstant(ArgOffset, PtrVT));
3106 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3107 MachinePointerInfo(), false, false, 0));
3108 // Calculate and remember argument location.
3109 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3114 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3115 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3116 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3117 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3118 MachineFunction &MF = DAG.getMachineFunction();
3120 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3121 // might overwrite each other in case of tail call optimization.
3122 SmallVector<SDValue, 8> MemOpChains2;
3123 // Do not flag preceding copytoreg stuff together with the following stuff.
3125 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3127 if (!MemOpChains2.empty())
3128 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3129 &MemOpChains2[0], MemOpChains2.size());
3131 // Store the return address to the appropriate stack slot.
3132 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3133 isPPC64, isDarwinABI, dl);
3135 // Emit callseq_end just before tailcall node.
3136 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3137 DAG.getIntPtrConstant(0, true), InFlag, dl);
3138 InFlag = Chain.getValue(1);
3142 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3143 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3144 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3145 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3146 const PPCSubtarget &PPCSubTarget) {
3148 bool isPPC64 = PPCSubTarget.isPPC64();
3149 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3151 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3152 NodeTys.push_back(MVT::Other); // Returns a chain
3153 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3155 unsigned CallOpc = PPCISD::CALL;
3157 bool needIndirectCall = true;
3158 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3159 // If this is an absolute destination address, use the munged value.
3160 Callee = SDValue(Dest, 0);
3161 needIndirectCall = false;
3164 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3165 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3166 // Use indirect calls for ALL functions calls in JIT mode, since the
3167 // far-call stubs may be outside relocation limits for a BL instruction.
3168 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3169 unsigned OpFlags = 0;
3170 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3171 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3172 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3173 (G->getGlobal()->isDeclaration() ||
3174 G->getGlobal()->isWeakForLinker())) {
3175 // PC-relative references to external symbols should go through $stub,
3176 // unless we're building with the leopard linker or later, which
3177 // automatically synthesizes these stubs.
3178 OpFlags = PPCII::MO_DARWIN_STUB;
3181 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3182 // every direct call is) turn it into a TargetGlobalAddress /
3183 // TargetExternalSymbol node so that legalize doesn't hack it.
3184 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3185 Callee.getValueType(),
3187 needIndirectCall = false;
3191 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3192 unsigned char OpFlags = 0;
3194 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3195 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3196 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3197 // PC-relative references to external symbols should go through $stub,
3198 // unless we're building with the leopard linker or later, which
3199 // automatically synthesizes these stubs.
3200 OpFlags = PPCII::MO_DARWIN_STUB;
3203 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3205 needIndirectCall = false;
3208 if (needIndirectCall) {
3209 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3210 // to do the call, we can't use PPCISD::CALL.
3211 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3213 if (isSVR4ABI && isPPC64) {
3214 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3215 // entry point, but to the function descriptor (the function entry point
3216 // address is part of the function descriptor though).
3217 // The function descriptor is a three doubleword structure with the
3218 // following fields: function entry point, TOC base address and
3219 // environment pointer.
3220 // Thus for a call through a function pointer, the following actions need
3222 // 1. Save the TOC of the caller in the TOC save area of its stack
3223 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3224 // 2. Load the address of the function entry point from the function
3226 // 3. Load the TOC of the callee from the function descriptor into r2.
3227 // 4. Load the environment pointer from the function descriptor into
3229 // 5. Branch to the function entry point address.
3230 // 6. On return of the callee, the TOC of the caller needs to be
3231 // restored (this is done in FinishCall()).
3233 // All those operations are flagged together to ensure that no other
3234 // operations can be scheduled in between. E.g. without flagging the
3235 // operations together, a TOC access in the caller could be scheduled
3236 // between the load of the callee TOC and the branch to the callee, which
3237 // results in the TOC access going through the TOC of the callee instead
3238 // of going through the TOC of the caller, which leads to incorrect code.
3240 // Load the address of the function entry point from the function
3242 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3243 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3244 InFlag.getNode() ? 3 : 2);
3245 Chain = LoadFuncPtr.getValue(1);
3246 InFlag = LoadFuncPtr.getValue(2);
3248 // Load environment pointer into r11.
3249 // Offset of the environment pointer within the function descriptor.
3250 SDValue PtrOff = DAG.getIntPtrConstant(16);
3252 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3253 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3255 Chain = LoadEnvPtr.getValue(1);
3256 InFlag = LoadEnvPtr.getValue(2);
3258 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3260 Chain = EnvVal.getValue(0);
3261 InFlag = EnvVal.getValue(1);
3263 // Load TOC of the callee into r2. We are using a target-specific load
3264 // with r2 hard coded, because the result of a target-independent load
3265 // would never go directly into r2, since r2 is a reserved register (which
3266 // prevents the register allocator from allocating it), resulting in an
3267 // additional register being allocated and an unnecessary move instruction
3269 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3270 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3272 Chain = LoadTOCPtr.getValue(0);
3273 InFlag = LoadTOCPtr.getValue(1);
3275 MTCTROps[0] = Chain;
3276 MTCTROps[1] = LoadFuncPtr;
3277 MTCTROps[2] = InFlag;
3280 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3281 2 + (InFlag.getNode() != 0));
3282 InFlag = Chain.getValue(1);
3285 NodeTys.push_back(MVT::Other);
3286 NodeTys.push_back(MVT::Glue);
3287 Ops.push_back(Chain);
3288 CallOpc = PPCISD::BCTRL;
3290 // Add use of X11 (holding environment pointer)
3291 if (isSVR4ABI && isPPC64)
3292 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3293 // Add CTR register as callee so a bctr can be emitted later.
3295 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3298 // If this is a direct call, pass the chain and the callee.
3299 if (Callee.getNode()) {
3300 Ops.push_back(Chain);
3301 Ops.push_back(Callee);
3303 // If this is a tail call add stack pointer delta.
3305 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3307 // Add argument registers to the end of the list so that they are known live
3309 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3310 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3311 RegsToPass[i].second.getValueType()));
3317 bool isLocalCall(const SDValue &Callee)
3319 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3320 return !G->getGlobal()->isDeclaration() &&
3321 !G->getGlobal()->isWeakForLinker();
3326 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3327 CallingConv::ID CallConv, bool isVarArg,
3328 const SmallVectorImpl<ISD::InputArg> &Ins,
3329 SDLoc dl, SelectionDAG &DAG,
3330 SmallVectorImpl<SDValue> &InVals) const {
3332 SmallVector<CCValAssign, 16> RVLocs;
3333 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3334 getTargetMachine(), RVLocs, *DAG.getContext());
3335 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3337 // Copy all of the result registers out of their specified physreg.
3338 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3339 CCValAssign &VA = RVLocs[i];
3340 assert(VA.isRegLoc() && "Can only return in registers!");
3342 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3343 VA.getLocReg(), VA.getLocVT(), InFlag);
3344 Chain = Val.getValue(1);
3345 InFlag = Val.getValue(2);
3347 switch (VA.getLocInfo()) {
3348 default: llvm_unreachable("Unknown loc info!");
3349 case CCValAssign::Full: break;
3350 case CCValAssign::AExt:
3351 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3353 case CCValAssign::ZExt:
3354 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3355 DAG.getValueType(VA.getValVT()));
3356 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3358 case CCValAssign::SExt:
3359 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3360 DAG.getValueType(VA.getValVT()));
3361 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3365 InVals.push_back(Val);
3372 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3373 bool isTailCall, bool isVarArg,
3375 SmallVector<std::pair<unsigned, SDValue>, 8>
3377 SDValue InFlag, SDValue Chain,
3379 int SPDiff, unsigned NumBytes,
3380 const SmallVectorImpl<ISD::InputArg> &Ins,
3381 SmallVectorImpl<SDValue> &InVals) const {
3382 std::vector<EVT> NodeTys;
3383 SmallVector<SDValue, 8> Ops;
3384 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3385 isTailCall, RegsToPass, Ops, NodeTys,
3388 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3389 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3390 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3392 // When performing tail call optimization the callee pops its arguments off
3393 // the stack. Account for this here so these bytes can be pushed back on in
3394 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3395 int BytesCalleePops =
3396 (CallConv == CallingConv::Fast &&
3397 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3399 // Add a register mask operand representing the call-preserved registers.
3400 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3401 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3402 assert(Mask && "Missing call preserved mask for calling convention");
3403 Ops.push_back(DAG.getRegisterMask(Mask));
3405 if (InFlag.getNode())
3406 Ops.push_back(InFlag);
3410 assert(((Callee.getOpcode() == ISD::Register &&
3411 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3412 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3413 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3414 isa<ConstantSDNode>(Callee)) &&
3415 "Expecting an global address, external symbol, absolute value or register");
3417 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3420 // Add a NOP immediately after the branch instruction when using the 64-bit
3421 // SVR4 ABI. At link time, if caller and callee are in a different module and
3422 // thus have a different TOC, the call will be replaced with a call to a stub
3423 // function which saves the current TOC, loads the TOC of the callee and
3424 // branches to the callee. The NOP will be replaced with a load instruction
3425 // which restores the TOC of the caller from the TOC save slot of the current
3426 // stack frame. If caller and callee belong to the same module (and have the
3427 // same TOC), the NOP will remain unchanged.
3429 bool needsTOCRestore = false;
3430 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3431 if (CallOpc == PPCISD::BCTRL) {
3432 // This is a call through a function pointer.
3433 // Restore the caller TOC from the save area into R2.
3434 // See PrepareCall() for more information about calls through function
3435 // pointers in the 64-bit SVR4 ABI.
3436 // We are using a target-specific load with r2 hard coded, because the
3437 // result of a target-independent load would never go directly into r2,
3438 // since r2 is a reserved register (which prevents the register allocator
3439 // from allocating it), resulting in an additional register being
3440 // allocated and an unnecessary move instruction being generated.
3441 needsTOCRestore = true;
3442 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3443 // Otherwise insert NOP for non-local calls.
3444 CallOpc = PPCISD::CALL_NOP;
3448 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3449 InFlag = Chain.getValue(1);
3451 if (needsTOCRestore) {
3452 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3453 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3454 InFlag = Chain.getValue(1);
3457 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3458 DAG.getIntPtrConstant(BytesCalleePops, true),
3461 InFlag = Chain.getValue(1);
3463 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3464 Ins, dl, DAG, InVals);
3468 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3469 SmallVectorImpl<SDValue> &InVals) const {
3470 SelectionDAG &DAG = CLI.DAG;
3472 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3473 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3474 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3475 SDValue Chain = CLI.Chain;
3476 SDValue Callee = CLI.Callee;
3477 bool &isTailCall = CLI.IsTailCall;
3478 CallingConv::ID CallConv = CLI.CallConv;
3479 bool isVarArg = CLI.IsVarArg;
3482 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3485 if (PPCSubTarget.isSVR4ABI()) {
3486 if (PPCSubTarget.isPPC64())
3487 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3488 isTailCall, Outs, OutVals, Ins,
3491 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3492 isTailCall, Outs, OutVals, Ins,
3496 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3497 isTailCall, Outs, OutVals, Ins,
3502 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3503 CallingConv::ID CallConv, bool isVarArg,
3505 const SmallVectorImpl<ISD::OutputArg> &Outs,
3506 const SmallVectorImpl<SDValue> &OutVals,
3507 const SmallVectorImpl<ISD::InputArg> &Ins,
3508 SDLoc dl, SelectionDAG &DAG,
3509 SmallVectorImpl<SDValue> &InVals) const {
3510 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3511 // of the 32-bit SVR4 ABI stack frame layout.
3513 assert((CallConv == CallingConv::C ||
3514 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3516 unsigned PtrByteSize = 4;
3518 MachineFunction &MF = DAG.getMachineFunction();
3520 // Mark this function as potentially containing a function that contains a
3521 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3522 // and restoring the callers stack pointer in this functions epilog. This is
3523 // done because by tail calling the called function might overwrite the value
3524 // in this function's (MF) stack pointer stack slot 0(SP).
3525 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3526 CallConv == CallingConv::Fast)
3527 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3529 // Count how many bytes are to be pushed on the stack, including the linkage
3530 // area, parameter list area and the part of the local variable space which
3531 // contains copies of aggregates which are passed by value.
3533 // Assign locations to all of the outgoing arguments.
3534 SmallVector<CCValAssign, 16> ArgLocs;
3535 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3536 getTargetMachine(), ArgLocs, *DAG.getContext());
3538 // Reserve space for the linkage area on the stack.
3539 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3542 // Handle fixed and variable vector arguments differently.
3543 // Fixed vector arguments go into registers as long as registers are
3544 // available. Variable vector arguments always go into memory.
3545 unsigned NumArgs = Outs.size();
3547 for (unsigned i = 0; i != NumArgs; ++i) {
3548 MVT ArgVT = Outs[i].VT;
3549 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3552 if (Outs[i].IsFixed) {
3553 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3556 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3562 errs() << "Call operand #" << i << " has unhandled type "
3563 << EVT(ArgVT).getEVTString() << "\n";
3565 llvm_unreachable(0);
3569 // All arguments are treated the same.
3570 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3573 // Assign locations to all of the outgoing aggregate by value arguments.
3574 SmallVector<CCValAssign, 16> ByValArgLocs;
3575 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3576 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3578 // Reserve stack space for the allocations in CCInfo.
3579 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3581 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3583 // Size of the linkage area, parameter list area and the part of the local
3584 // space variable where copies of aggregates which are passed by value are
3586 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3588 // Calculate by how many bytes the stack has to be adjusted in case of tail
3589 // call optimization.
3590 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3592 // Adjust the stack pointer for the new arguments...
3593 // These operations are automatically eliminated by the prolog/epilog pass
3594 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3596 SDValue CallSeqStart = Chain;
3598 // Load the return address and frame pointer so it can be moved somewhere else
3601 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3604 // Set up a copy of the stack pointer for use loading and storing any
3605 // arguments that may not fit in the registers available for argument
3607 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3609 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3610 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3611 SmallVector<SDValue, 8> MemOpChains;
3613 bool seenFloatArg = false;
3614 // Walk the register/memloc assignments, inserting copies/loads.
3615 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3618 CCValAssign &VA = ArgLocs[i];
3619 SDValue Arg = OutVals[i];
3620 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3622 if (Flags.isByVal()) {
3623 // Argument is an aggregate which is passed by value, thus we need to
3624 // create a copy of it in the local variable space of the current stack
3625 // frame (which is the stack frame of the caller) and pass the address of
3626 // this copy to the callee.
3627 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3628 CCValAssign &ByValVA = ByValArgLocs[j++];
3629 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3631 // Memory reserved in the local variable space of the callers stack frame.
3632 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3634 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3635 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3637 // Create a copy of the argument in the local area of the current
3639 SDValue MemcpyCall =
3640 CreateCopyOfByValArgument(Arg, PtrOff,
3641 CallSeqStart.getNode()->getOperand(0),
3644 // This must go outside the CALLSEQ_START..END.
3645 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3646 CallSeqStart.getNode()->getOperand(1),
3648 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3649 NewCallSeqStart.getNode());
3650 Chain = CallSeqStart = NewCallSeqStart;
3652 // Pass the address of the aggregate copy on the stack either in a
3653 // physical register or in the parameter list area of the current stack
3654 // frame to the callee.
3658 if (VA.isRegLoc()) {
3659 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3660 // Put argument in a physical register.
3661 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3663 // Put argument in the parameter list area of the current stack frame.
3664 assert(VA.isMemLoc());
3665 unsigned LocMemOffset = VA.getLocMemOffset();
3668 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3669 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3671 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3672 MachinePointerInfo(),
3675 // Calculate and remember argument location.
3676 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3682 if (!MemOpChains.empty())
3683 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3684 &MemOpChains[0], MemOpChains.size());
3686 // Build a sequence of copy-to-reg nodes chained together with token chain
3687 // and flag operands which copy the outgoing args into the appropriate regs.
3689 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3690 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3691 RegsToPass[i].second, InFlag);
3692 InFlag = Chain.getValue(1);
3695 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3698 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3699 SDValue Ops[] = { Chain, InFlag };
3701 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3702 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3704 InFlag = Chain.getValue(1);
3708 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3709 false, TailCallArguments);
3711 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3712 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3716 // Copy an argument into memory, being careful to do this outside the
3717 // call sequence for the call to which the argument belongs.
3719 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3720 SDValue CallSeqStart,
3721 ISD::ArgFlagsTy Flags,
3724 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3725 CallSeqStart.getNode()->getOperand(0),
3727 // The MEMCPY must go outside the CALLSEQ_START..END.
3728 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3729 CallSeqStart.getNode()->getOperand(1),
3731 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3732 NewCallSeqStart.getNode());
3733 return NewCallSeqStart;
3737 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3738 CallingConv::ID CallConv, bool isVarArg,
3740 const SmallVectorImpl<ISD::OutputArg> &Outs,
3741 const SmallVectorImpl<SDValue> &OutVals,
3742 const SmallVectorImpl<ISD::InputArg> &Ins,
3743 SDLoc dl, SelectionDAG &DAG,
3744 SmallVectorImpl<SDValue> &InVals) const {
3746 unsigned NumOps = Outs.size();
3748 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3749 unsigned PtrByteSize = 8;
3751 MachineFunction &MF = DAG.getMachineFunction();
3753 // Mark this function as potentially containing a function that contains a
3754 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3755 // and restoring the callers stack pointer in this functions epilog. This is
3756 // done because by tail calling the called function might overwrite the value
3757 // in this function's (MF) stack pointer stack slot 0(SP).
3758 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3759 CallConv == CallingConv::Fast)
3760 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3762 unsigned nAltivecParamsAtEnd = 0;
3764 // Count how many bytes are to be pushed on the stack, including the linkage
3765 // area, and parameter passing area. We start with at least 48 bytes, which
3766 // is reserved space for [SP][CR][LR][3 x unused].
3767 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3770 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3771 Outs, OutVals, nAltivecParamsAtEnd);
3773 // Calculate by how many bytes the stack has to be adjusted in case of tail
3774 // call optimization.
3775 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3777 // To protect arguments on the stack from being clobbered in a tail call,
3778 // force all the loads to happen before doing any other lowering.
3780 Chain = DAG.getStackArgumentTokenFactor(Chain);
3782 // Adjust the stack pointer for the new arguments...
3783 // These operations are automatically eliminated by the prolog/epilog pass
3784 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3786 SDValue CallSeqStart = Chain;
3788 // Load the return address and frame pointer so it can be move somewhere else
3791 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3794 // Set up a copy of the stack pointer for use loading and storing any
3795 // arguments that may not fit in the registers available for argument
3797 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3799 // Figure out which arguments are going to go in registers, and which in
3800 // memory. Also, if this is a vararg function, floating point operations
3801 // must be stored to our stack, and loaded into integer regs as well, if
3802 // any integer regs are available for argument passing.
3803 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3804 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3806 static const uint16_t GPR[] = {
3807 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3808 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3810 static const uint16_t *FPR = GetFPR();
3812 static const uint16_t VR[] = {
3813 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3814 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3816 const unsigned NumGPRs = array_lengthof(GPR);
3817 const unsigned NumFPRs = 13;
3818 const unsigned NumVRs = array_lengthof(VR);
3820 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3821 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3823 SmallVector<SDValue, 8> MemOpChains;
3824 for (unsigned i = 0; i != NumOps; ++i) {
3825 SDValue Arg = OutVals[i];
3826 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3828 // PtrOff will be used to store the current argument to the stack if a
3829 // register cannot be found for it.
3832 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3834 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3836 // Promote integers to 64-bit values.
3837 if (Arg.getValueType() == MVT::i32) {
3838 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3839 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3840 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3843 // FIXME memcpy is used way more than necessary. Correctness first.
3844 // Note: "by value" is code for passing a structure by value, not
3846 if (Flags.isByVal()) {
3847 // Note: Size includes alignment padding, so
3848 // struct x { short a; char b; }
3849 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3850 // These are the proper values we need for right-justifying the
3851 // aggregate in a parameter register.
3852 unsigned Size = Flags.getByValSize();
3854 // An empty aggregate parameter takes up no storage and no
3859 // All aggregates smaller than 8 bytes must be passed right-justified.
3860 if (Size==1 || Size==2 || Size==4) {
3861 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3862 if (GPR_idx != NumGPRs) {
3863 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3864 MachinePointerInfo(), VT,
3866 MemOpChains.push_back(Load.getValue(1));
3867 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3869 ArgOffset += PtrByteSize;
3874 if (GPR_idx == NumGPRs && Size < 8) {
3875 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3876 PtrOff.getValueType());
3877 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3878 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3881 ArgOffset += PtrByteSize;
3884 // Copy entire object into memory. There are cases where gcc-generated
3885 // code assumes it is there, even if it could be put entirely into
3886 // registers. (This is not what the doc says.)
3888 // FIXME: The above statement is likely due to a misunderstanding of the
3889 // documents. All arguments must be copied into the parameter area BY
3890 // THE CALLEE in the event that the callee takes the address of any
3891 // formal argument. That has not yet been implemented. However, it is
3892 // reasonable to use the stack area as a staging area for the register
3895 // Skip this for small aggregates, as we will use the same slot for a
3896 // right-justified copy, below.
3898 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3902 // When a register is available, pass a small aggregate right-justified.
3903 if (Size < 8 && GPR_idx != NumGPRs) {
3904 // The easiest way to get this right-justified in a register
3905 // is to copy the structure into the rightmost portion of a
3906 // local variable slot, then load the whole slot into the
3908 // FIXME: The memcpy seems to produce pretty awful code for
3909 // small aggregates, particularly for packed ones.
3910 // FIXME: It would be preferable to use the slot in the
3911 // parameter save area instead of a new local variable.
3912 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3913 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3914 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3918 // Load the slot into the register.
3919 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3920 MachinePointerInfo(),
3921 false, false, false, 0);
3922 MemOpChains.push_back(Load.getValue(1));
3923 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3925 // Done with this argument.
3926 ArgOffset += PtrByteSize;
3930 // For aggregates larger than PtrByteSize, copy the pieces of the
3931 // object that fit into registers from the parameter save area.
3932 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3933 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3934 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3935 if (GPR_idx != NumGPRs) {
3936 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3937 MachinePointerInfo(),
3938 false, false, false, 0);
3939 MemOpChains.push_back(Load.getValue(1));
3940 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3941 ArgOffset += PtrByteSize;
3943 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3950 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3951 default: llvm_unreachable("Unexpected ValueType for argument!");
3954 if (GPR_idx != NumGPRs) {
3955 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3957 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3958 true, isTailCall, false, MemOpChains,
3959 TailCallArguments, dl);
3961 ArgOffset += PtrByteSize;
3965 if (FPR_idx != NumFPRs) {
3966 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3969 // A single float or an aggregate containing only a single float
3970 // must be passed right-justified in the stack doubleword, and
3971 // in the GPR, if one is available.
3973 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
3974 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3975 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3979 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3980 MachinePointerInfo(), false, false, 0);
3981 MemOpChains.push_back(Store);
3983 // Float varargs are always shadowed in available integer registers
3984 if (GPR_idx != NumGPRs) {
3985 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3986 MachinePointerInfo(), false, false,
3988 MemOpChains.push_back(Load.getValue(1));
3989 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3991 } else if (GPR_idx != NumGPRs)
3992 // If we have any FPRs remaining, we may also have GPRs remaining.
3995 // Single-precision floating-point values are mapped to the
3996 // second (rightmost) word of the stack doubleword.
3997 if (Arg.getValueType() == MVT::f32) {
3998 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3999 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4002 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4003 true, isTailCall, false, MemOpChains,
4004 TailCallArguments, dl);
4013 // These go aligned on the stack, or in the corresponding R registers
4014 // when within range. The Darwin PPC ABI doc claims they also go in
4015 // V registers; in fact gcc does this only for arguments that are
4016 // prototyped, not for those that match the ... We do it for all
4017 // arguments, seems to work.
4018 while (ArgOffset % 16 !=0) {
4019 ArgOffset += PtrByteSize;
4020 if (GPR_idx != NumGPRs)
4023 // We could elide this store in the case where the object fits
4024 // entirely in R registers. Maybe later.
4025 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4026 DAG.getConstant(ArgOffset, PtrVT));
4027 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4028 MachinePointerInfo(), false, false, 0);
4029 MemOpChains.push_back(Store);
4030 if (VR_idx != NumVRs) {
4031 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4032 MachinePointerInfo(),
4033 false, false, false, 0);
4034 MemOpChains.push_back(Load.getValue(1));
4035 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4038 for (unsigned i=0; i<16; i+=PtrByteSize) {
4039 if (GPR_idx == NumGPRs)
4041 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4042 DAG.getConstant(i, PtrVT));
4043 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4044 false, false, false, 0);
4045 MemOpChains.push_back(Load.getValue(1));
4046 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4051 // Non-varargs Altivec params generally go in registers, but have
4052 // stack space allocated at the end.
4053 if (VR_idx != NumVRs) {
4054 // Doesn't have GPR space allocated.
4055 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4057 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4058 true, isTailCall, true, MemOpChains,
4059 TailCallArguments, dl);
4066 if (!MemOpChains.empty())
4067 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4068 &MemOpChains[0], MemOpChains.size());
4070 // Check if this is an indirect call (MTCTR/BCTRL).
4071 // See PrepareCall() for more information about calls through function
4072 // pointers in the 64-bit SVR4 ABI.
4074 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4075 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4076 !isBLACompatibleAddress(Callee, DAG)) {
4077 // Load r2 into a virtual register and store it to the TOC save area.
4078 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4079 // TOC save area offset.
4080 SDValue PtrOff = DAG.getIntPtrConstant(40);
4081 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4082 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4084 // R12 must contain the address of an indirect callee. This does not
4085 // mean the MTCTR instruction must use R12; it's easier to model this
4086 // as an extra parameter, so do that.
4087 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4090 // Build a sequence of copy-to-reg nodes chained together with token chain
4091 // and flag operands which copy the outgoing args into the appropriate regs.
4093 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4094 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4095 RegsToPass[i].second, InFlag);
4096 InFlag = Chain.getValue(1);
4100 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4101 FPOp, true, TailCallArguments);
4103 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4104 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4109 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4110 CallingConv::ID CallConv, bool isVarArg,
4112 const SmallVectorImpl<ISD::OutputArg> &Outs,
4113 const SmallVectorImpl<SDValue> &OutVals,
4114 const SmallVectorImpl<ISD::InputArg> &Ins,
4115 SDLoc dl, SelectionDAG &DAG,
4116 SmallVectorImpl<SDValue> &InVals) const {
4118 unsigned NumOps = Outs.size();
4120 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4121 bool isPPC64 = PtrVT == MVT::i64;
4122 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4124 MachineFunction &MF = DAG.getMachineFunction();
4126 // Mark this function as potentially containing a function that contains a
4127 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4128 // and restoring the callers stack pointer in this functions epilog. This is
4129 // done because by tail calling the called function might overwrite the value
4130 // in this function's (MF) stack pointer stack slot 0(SP).
4131 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4132 CallConv == CallingConv::Fast)
4133 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4135 unsigned nAltivecParamsAtEnd = 0;
4137 // Count how many bytes are to be pushed on the stack, including the linkage
4138 // area, and parameter passing area. We start with 24/48 bytes, which is
4139 // prereserved space for [SP][CR][LR][3 x unused].
4141 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4143 nAltivecParamsAtEnd);
4145 // Calculate by how many bytes the stack has to be adjusted in case of tail
4146 // call optimization.
4147 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4149 // To protect arguments on the stack from being clobbered in a tail call,
4150 // force all the loads to happen before doing any other lowering.
4152 Chain = DAG.getStackArgumentTokenFactor(Chain);
4154 // Adjust the stack pointer for the new arguments...
4155 // These operations are automatically eliminated by the prolog/epilog pass
4156 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4158 SDValue CallSeqStart = Chain;
4160 // Load the return address and frame pointer so it can be move somewhere else
4163 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4166 // Set up a copy of the stack pointer for use loading and storing any
4167 // arguments that may not fit in the registers available for argument
4171 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4173 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4175 // Figure out which arguments are going to go in registers, and which in
4176 // memory. Also, if this is a vararg function, floating point operations
4177 // must be stored to our stack, and loaded into integer regs as well, if
4178 // any integer regs are available for argument passing.
4179 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4180 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4182 static const uint16_t GPR_32[] = { // 32-bit registers.
4183 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4184 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4186 static const uint16_t GPR_64[] = { // 64-bit registers.
4187 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4188 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4190 static const uint16_t *FPR = GetFPR();
4192 static const uint16_t VR[] = {
4193 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4194 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4196 const unsigned NumGPRs = array_lengthof(GPR_32);
4197 const unsigned NumFPRs = 13;
4198 const unsigned NumVRs = array_lengthof(VR);
4200 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4202 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4203 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4205 SmallVector<SDValue, 8> MemOpChains;
4206 for (unsigned i = 0; i != NumOps; ++i) {
4207 SDValue Arg = OutVals[i];
4208 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4210 // PtrOff will be used to store the current argument to the stack if a
4211 // register cannot be found for it.
4214 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4216 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4218 // On PPC64, promote integers to 64-bit values.
4219 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4220 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4221 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4222 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4225 // FIXME memcpy is used way more than necessary. Correctness first.
4226 // Note: "by value" is code for passing a structure by value, not
4228 if (Flags.isByVal()) {
4229 unsigned Size = Flags.getByValSize();
4230 // Very small objects are passed right-justified. Everything else is
4231 // passed left-justified.
4232 if (Size==1 || Size==2) {
4233 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4234 if (GPR_idx != NumGPRs) {
4235 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4236 MachinePointerInfo(), VT,
4238 MemOpChains.push_back(Load.getValue(1));
4239 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4241 ArgOffset += PtrByteSize;
4243 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4244 PtrOff.getValueType());
4245 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4246 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4249 ArgOffset += PtrByteSize;
4253 // Copy entire object into memory. There are cases where gcc-generated
4254 // code assumes it is there, even if it could be put entirely into
4255 // registers. (This is not what the doc says.)
4256 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4260 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4261 // copy the pieces of the object that fit into registers from the
4262 // parameter save area.
4263 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4264 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4265 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4266 if (GPR_idx != NumGPRs) {
4267 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4268 MachinePointerInfo(),
4269 false, false, false, 0);
4270 MemOpChains.push_back(Load.getValue(1));
4271 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4272 ArgOffset += PtrByteSize;
4274 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4281 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4282 default: llvm_unreachable("Unexpected ValueType for argument!");
4285 if (GPR_idx != NumGPRs) {
4286 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4288 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4289 isPPC64, isTailCall, false, MemOpChains,
4290 TailCallArguments, dl);
4292 ArgOffset += PtrByteSize;
4296 if (FPR_idx != NumFPRs) {
4297 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4300 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4301 MachinePointerInfo(), false, false, 0);
4302 MemOpChains.push_back(Store);
4304 // Float varargs are always shadowed in available integer registers
4305 if (GPR_idx != NumGPRs) {
4306 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4307 MachinePointerInfo(), false, false,
4309 MemOpChains.push_back(Load.getValue(1));
4310 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4312 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4313 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4314 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4315 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4316 MachinePointerInfo(),
4317 false, false, false, 0);
4318 MemOpChains.push_back(Load.getValue(1));
4319 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4322 // If we have any FPRs remaining, we may also have GPRs remaining.
4323 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4325 if (GPR_idx != NumGPRs)
4327 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4328 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4332 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4333 isPPC64, isTailCall, false, MemOpChains,
4334 TailCallArguments, dl);
4338 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4345 // These go aligned on the stack, or in the corresponding R registers
4346 // when within range. The Darwin PPC ABI doc claims they also go in
4347 // V registers; in fact gcc does this only for arguments that are
4348 // prototyped, not for those that match the ... We do it for all
4349 // arguments, seems to work.
4350 while (ArgOffset % 16 !=0) {
4351 ArgOffset += PtrByteSize;
4352 if (GPR_idx != NumGPRs)
4355 // We could elide this store in the case where the object fits
4356 // entirely in R registers. Maybe later.
4357 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4358 DAG.getConstant(ArgOffset, PtrVT));
4359 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4360 MachinePointerInfo(), false, false, 0);
4361 MemOpChains.push_back(Store);
4362 if (VR_idx != NumVRs) {
4363 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4364 MachinePointerInfo(),
4365 false, false, false, 0);
4366 MemOpChains.push_back(Load.getValue(1));
4367 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4370 for (unsigned i=0; i<16; i+=PtrByteSize) {
4371 if (GPR_idx == NumGPRs)
4373 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4374 DAG.getConstant(i, PtrVT));
4375 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4376 false, false, false, 0);
4377 MemOpChains.push_back(Load.getValue(1));
4378 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4383 // Non-varargs Altivec params generally go in registers, but have
4384 // stack space allocated at the end.
4385 if (VR_idx != NumVRs) {
4386 // Doesn't have GPR space allocated.
4387 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4388 } else if (nAltivecParamsAtEnd==0) {
4389 // We are emitting Altivec params in order.
4390 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4391 isPPC64, isTailCall, true, MemOpChains,
4392 TailCallArguments, dl);
4398 // If all Altivec parameters fit in registers, as they usually do,
4399 // they get stack space following the non-Altivec parameters. We
4400 // don't track this here because nobody below needs it.
4401 // If there are more Altivec parameters than fit in registers emit
4403 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4405 // Offset is aligned; skip 1st 12 params which go in V registers.
4406 ArgOffset = ((ArgOffset+15)/16)*16;
4408 for (unsigned i = 0; i != NumOps; ++i) {
4409 SDValue Arg = OutVals[i];
4410 EVT ArgType = Outs[i].VT;
4411 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4412 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4415 // We are emitting Altivec params in order.
4416 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4417 isPPC64, isTailCall, true, MemOpChains,
4418 TailCallArguments, dl);
4425 if (!MemOpChains.empty())
4426 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4427 &MemOpChains[0], MemOpChains.size());
4429 // On Darwin, R12 must contain the address of an indirect callee. This does
4430 // not mean the MTCTR instruction must use R12; it's easier to model this as
4431 // an extra parameter, so do that.
4433 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4434 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4435 !isBLACompatibleAddress(Callee, DAG))
4436 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4437 PPC::R12), Callee));
4439 // Build a sequence of copy-to-reg nodes chained together with token chain
4440 // and flag operands which copy the outgoing args into the appropriate regs.
4442 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4443 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4444 RegsToPass[i].second, InFlag);
4445 InFlag = Chain.getValue(1);
4449 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4450 FPOp, true, TailCallArguments);
4452 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4453 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4458 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4459 MachineFunction &MF, bool isVarArg,
4460 const SmallVectorImpl<ISD::OutputArg> &Outs,
4461 LLVMContext &Context) const {
4462 SmallVector<CCValAssign, 16> RVLocs;
4463 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4465 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4469 PPCTargetLowering::LowerReturn(SDValue Chain,
4470 CallingConv::ID CallConv, bool isVarArg,
4471 const SmallVectorImpl<ISD::OutputArg> &Outs,
4472 const SmallVectorImpl<SDValue> &OutVals,
4473 SDLoc dl, SelectionDAG &DAG) const {
4475 SmallVector<CCValAssign, 16> RVLocs;
4476 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4477 getTargetMachine(), RVLocs, *DAG.getContext());
4478 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4481 SmallVector<SDValue, 4> RetOps(1, Chain);
4483 // Copy the result values into the output registers.
4484 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4485 CCValAssign &VA = RVLocs[i];
4486 assert(VA.isRegLoc() && "Can only return in registers!");
4488 SDValue Arg = OutVals[i];
4490 switch (VA.getLocInfo()) {
4491 default: llvm_unreachable("Unknown loc info!");
4492 case CCValAssign::Full: break;
4493 case CCValAssign::AExt:
4494 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4496 case CCValAssign::ZExt:
4497 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4499 case CCValAssign::SExt:
4500 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4504 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4505 Flag = Chain.getValue(1);
4506 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4509 RetOps[0] = Chain; // Update chain.
4511 // Add the flag if we have it.
4513 RetOps.push_back(Flag);
4515 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4516 &RetOps[0], RetOps.size());
4519 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4520 const PPCSubtarget &Subtarget) const {
4521 // When we pop the dynamic allocation we need to restore the SP link.
4524 // Get the corect type for pointers.
4525 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4527 // Construct the stack pointer operand.
4528 bool isPPC64 = Subtarget.isPPC64();
4529 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4530 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4532 // Get the operands for the STACKRESTORE.
4533 SDValue Chain = Op.getOperand(0);
4534 SDValue SaveSP = Op.getOperand(1);
4536 // Load the old link SP.
4537 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4538 MachinePointerInfo(),
4539 false, false, false, 0);
4541 // Restore the stack pointer.
4542 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4544 // Store the old link SP.
4545 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4552 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4553 MachineFunction &MF = DAG.getMachineFunction();
4554 bool isPPC64 = PPCSubTarget.isPPC64();
4555 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4556 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4558 // Get current frame pointer save index. The users of this index will be
4559 // primarily DYNALLOC instructions.
4560 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4561 int RASI = FI->getReturnAddrSaveIndex();
4563 // If the frame pointer save index hasn't been defined yet.
4565 // Find out what the fix offset of the frame pointer save area.
4566 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4567 // Allocate the frame index for frame pointer save area.
4568 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4570 FI->setReturnAddrSaveIndex(RASI);
4572 return DAG.getFrameIndex(RASI, PtrVT);
4576 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4577 MachineFunction &MF = DAG.getMachineFunction();
4578 bool isPPC64 = PPCSubTarget.isPPC64();
4579 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4580 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4582 // Get current frame pointer save index. The users of this index will be
4583 // primarily DYNALLOC instructions.
4584 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4585 int FPSI = FI->getFramePointerSaveIndex();
4587 // If the frame pointer save index hasn't been defined yet.
4589 // Find out what the fix offset of the frame pointer save area.
4590 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4593 // Allocate the frame index for frame pointer save area.
4594 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4596 FI->setFramePointerSaveIndex(FPSI);
4598 return DAG.getFrameIndex(FPSI, PtrVT);
4601 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4603 const PPCSubtarget &Subtarget) const {
4605 SDValue Chain = Op.getOperand(0);
4606 SDValue Size = Op.getOperand(1);
4609 // Get the corect type for pointers.
4610 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4612 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4613 DAG.getConstant(0, PtrVT), Size);
4614 // Construct a node for the frame pointer save index.
4615 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4616 // Build a DYNALLOC node.
4617 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4618 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4619 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4622 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4623 SelectionDAG &DAG) const {
4625 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4626 DAG.getVTList(MVT::i32, MVT::Other),
4627 Op.getOperand(0), Op.getOperand(1));
4630 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4631 SelectionDAG &DAG) const {
4633 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4634 Op.getOperand(0), Op.getOperand(1));
4637 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4639 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4640 // Not FP? Not a fsel.
4641 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4642 !Op.getOperand(2).getValueType().isFloatingPoint())
4645 // We might be able to do better than this under some circumstances, but in
4646 // general, fsel-based lowering of select is a finite-math-only optimization.
4647 // For more information, see section F.3 of the 2.06 ISA specification.
4648 if (!DAG.getTarget().Options.NoInfsFPMath ||
4649 !DAG.getTarget().Options.NoNaNsFPMath)
4652 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4654 EVT ResVT = Op.getValueType();
4655 EVT CmpVT = Op.getOperand(0).getValueType();
4656 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4657 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4660 // If the RHS of the comparison is a 0.0, we don't need to do the
4661 // subtraction at all.
4663 if (isFloatingPointZero(RHS))
4665 default: break; // SETUO etc aren't handled by fsel.
4669 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4670 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4671 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4672 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4673 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4674 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4675 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4678 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4681 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4682 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4683 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4686 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4689 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4690 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4691 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4692 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4697 default: break; // SETUO etc aren't handled by fsel.
4701 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4702 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4703 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4704 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4705 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4706 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4707 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4708 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4711 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4712 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4713 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4714 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4717 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4718 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4719 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4720 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4723 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4724 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4725 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4726 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4729 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4730 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4731 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4732 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4737 // FIXME: Split this code up when LegalizeDAGTypes lands.
4738 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4740 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4741 SDValue Src = Op.getOperand(0);
4742 if (Src.getValueType() == MVT::f32)
4743 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4746 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4747 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4749 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4750 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4755 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4756 "i64 FP_TO_UINT is supported only with FPCVT");
4757 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4763 // Convert the FP value to an int value through memory.
4764 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4765 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4766 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4767 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4768 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4770 // Emit a store to the stack slot.
4773 MachineFunction &MF = DAG.getMachineFunction();
4774 MachineMemOperand *MMO =
4775 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4776 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4777 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4778 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4781 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4782 MPI, false, false, 0);
4784 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4786 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4787 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4788 DAG.getConstant(4, FIPtr.getValueType()));
4789 MPI = MachinePointerInfo();
4792 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4793 false, false, false, 0);
4796 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4797 SelectionDAG &DAG) const {
4799 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4800 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4803 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4804 "UINT_TO_FP is supported only with FPCVT");
4806 // If we have FCFIDS, then use it when converting to single-precision.
4807 // Otherwise, convert to double-precision and then round.
4808 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4809 (Op.getOpcode() == ISD::UINT_TO_FP ?
4810 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4811 (Op.getOpcode() == ISD::UINT_TO_FP ?
4812 PPCISD::FCFIDU : PPCISD::FCFID);
4813 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4814 MVT::f32 : MVT::f64;
4816 if (Op.getOperand(0).getValueType() == MVT::i64) {
4817 SDValue SINT = Op.getOperand(0);
4818 // When converting to single-precision, we actually need to convert
4819 // to double-precision first and then round to single-precision.
4820 // To avoid double-rounding effects during that operation, we have
4821 // to prepare the input operand. Bits that might be truncated when
4822 // converting to double-precision are replaced by a bit that won't
4823 // be lost at this stage, but is below the single-precision rounding
4826 // However, if -enable-unsafe-fp-math is in effect, accept double
4827 // rounding to avoid the extra overhead.
4828 if (Op.getValueType() == MVT::f32 &&
4829 !PPCSubTarget.hasFPCVT() &&
4830 !DAG.getTarget().Options.UnsafeFPMath) {
4832 // Twiddle input to make sure the low 11 bits are zero. (If this
4833 // is the case, we are guaranteed the value will fit into the 53 bit
4834 // mantissa of an IEEE double-precision value without rounding.)
4835 // If any of those low 11 bits were not zero originally, make sure
4836 // bit 12 (value 2048) is set instead, so that the final rounding
4837 // to single-precision gets the correct result.
4838 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4839 SINT, DAG.getConstant(2047, MVT::i64));
4840 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4841 Round, DAG.getConstant(2047, MVT::i64));
4842 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4843 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4844 Round, DAG.getConstant(-2048, MVT::i64));
4846 // However, we cannot use that value unconditionally: if the magnitude
4847 // of the input value is small, the bit-twiddling we did above might
4848 // end up visibly changing the output. Fortunately, in that case, we
4849 // don't need to twiddle bits since the original input will convert
4850 // exactly to double-precision floating-point already. Therefore,
4851 // construct a conditional to use the original value if the top 11
4852 // bits are all sign-bit copies, and use the rounded value computed
4854 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4855 SINT, DAG.getConstant(53, MVT::i32));
4856 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4857 Cond, DAG.getConstant(1, MVT::i64));
4858 Cond = DAG.getSetCC(dl, MVT::i32,
4859 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4861 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4864 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4865 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4867 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4868 FP = DAG.getNode(ISD::FP_ROUND, dl,
4869 MVT::f32, FP, DAG.getIntPtrConstant(0));
4873 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4874 "Unhandled INT_TO_FP type in custom expander!");
4875 // Since we only generate this in 64-bit mode, we can take advantage of
4876 // 64-bit registers. In particular, sign extend the input value into the
4877 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4878 // then lfd it and fcfid it.
4879 MachineFunction &MF = DAG.getMachineFunction();
4880 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4881 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4884 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4885 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4886 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4888 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4889 MachinePointerInfo::getFixedStack(FrameIdx),
4892 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4893 "Expected an i32 store");
4894 MachineMemOperand *MMO =
4895 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4896 MachineMemOperand::MOLoad, 4, 4);
4897 SDValue Ops[] = { Store, FIdx };
4898 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4899 PPCISD::LFIWZX : PPCISD::LFIWAX,
4900 dl, DAG.getVTList(MVT::f64, MVT::Other),
4901 Ops, 2, MVT::i32, MMO);
4903 assert(PPCSubTarget.isPPC64() &&
4904 "i32->FP without LFIWAX supported only on PPC64");
4906 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4907 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4909 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4912 // STD the extended value into the stack slot.
4913 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4914 MachinePointerInfo::getFixedStack(FrameIdx),
4917 // Load the value as a double.
4918 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4919 MachinePointerInfo::getFixedStack(FrameIdx),
4920 false, false, false, 0);
4923 // FCFID it and return it.
4924 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4925 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4926 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4930 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4931 SelectionDAG &DAG) const {
4934 The rounding mode is in bits 30:31 of FPSR, and has the following
4941 FLT_ROUNDS, on the other hand, expects the following:
4948 To perform the conversion, we do:
4949 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4952 MachineFunction &MF = DAG.getMachineFunction();
4953 EVT VT = Op.getValueType();
4954 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4955 SDValue MFFSreg, InFlag;
4957 // Save FP Control Word to register
4959 MVT::f64, // return register
4960 MVT::Glue // unused in this context
4962 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4964 // Save FP register to stack slot
4965 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4966 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4967 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4968 StackSlot, MachinePointerInfo(), false, false,0);
4970 // Load FP Control Word from low 32 bits of stack slot.
4971 SDValue Four = DAG.getConstant(4, PtrVT);
4972 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4973 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4974 false, false, false, 0);
4976 // Transform as necessary
4978 DAG.getNode(ISD::AND, dl, MVT::i32,
4979 CWD, DAG.getConstant(3, MVT::i32));
4981 DAG.getNode(ISD::SRL, dl, MVT::i32,
4982 DAG.getNode(ISD::AND, dl, MVT::i32,
4983 DAG.getNode(ISD::XOR, dl, MVT::i32,
4984 CWD, DAG.getConstant(3, MVT::i32)),
4985 DAG.getConstant(3, MVT::i32)),
4986 DAG.getConstant(1, MVT::i32));
4989 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4991 return DAG.getNode((VT.getSizeInBits() < 16 ?
4992 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
4995 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4996 EVT VT = Op.getValueType();
4997 unsigned BitWidth = VT.getSizeInBits();
4999 assert(Op.getNumOperands() == 3 &&
5000 VT == Op.getOperand(1).getValueType() &&
5003 // Expand into a bunch of logical ops. Note that these ops
5004 // depend on the PPC behavior for oversized shift amounts.
5005 SDValue Lo = Op.getOperand(0);
5006 SDValue Hi = Op.getOperand(1);
5007 SDValue Amt = Op.getOperand(2);
5008 EVT AmtVT = Amt.getValueType();
5010 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5011 DAG.getConstant(BitWidth, AmtVT), Amt);
5012 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5013 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5014 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5015 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5016 DAG.getConstant(-BitWidth, AmtVT));
5017 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5018 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5019 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5020 SDValue OutOps[] = { OutLo, OutHi };
5021 return DAG.getMergeValues(OutOps, 2, dl);
5024 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5025 EVT VT = Op.getValueType();
5027 unsigned BitWidth = VT.getSizeInBits();
5028 assert(Op.getNumOperands() == 3 &&
5029 VT == Op.getOperand(1).getValueType() &&
5032 // Expand into a bunch of logical ops. Note that these ops
5033 // depend on the PPC behavior for oversized shift amounts.
5034 SDValue Lo = Op.getOperand(0);
5035 SDValue Hi = Op.getOperand(1);
5036 SDValue Amt = Op.getOperand(2);
5037 EVT AmtVT = Amt.getValueType();
5039 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5040 DAG.getConstant(BitWidth, AmtVT), Amt);
5041 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5042 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5043 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5044 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5045 DAG.getConstant(-BitWidth, AmtVT));
5046 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5047 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5048 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5049 SDValue OutOps[] = { OutLo, OutHi };
5050 return DAG.getMergeValues(OutOps, 2, dl);
5053 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5055 EVT VT = Op.getValueType();
5056 unsigned BitWidth = VT.getSizeInBits();
5057 assert(Op.getNumOperands() == 3 &&
5058 VT == Op.getOperand(1).getValueType() &&
5061 // Expand into a bunch of logical ops, followed by a select_cc.
5062 SDValue Lo = Op.getOperand(0);
5063 SDValue Hi = Op.getOperand(1);
5064 SDValue Amt = Op.getOperand(2);
5065 EVT AmtVT = Amt.getValueType();
5067 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5068 DAG.getConstant(BitWidth, AmtVT), Amt);
5069 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5070 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5071 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5072 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5073 DAG.getConstant(-BitWidth, AmtVT));
5074 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5075 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5076 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5077 Tmp4, Tmp6, ISD::SETLE);
5078 SDValue OutOps[] = { OutLo, OutHi };
5079 return DAG.getMergeValues(OutOps, 2, dl);
5082 //===----------------------------------------------------------------------===//
5083 // Vector related lowering.
5086 /// BuildSplatI - Build a canonical splati of Val with an element size of
5087 /// SplatSize. Cast the result to VT.
5088 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5089 SelectionDAG &DAG, SDLoc dl) {
5090 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5092 static const EVT VTys[] = { // canonical VT to use for each size.
5093 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5096 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5098 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5102 EVT CanonicalVT = VTys[SplatSize-1];
5104 // Build a canonical splat for this value.
5105 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5106 SmallVector<SDValue, 8> Ops;
5107 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5108 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5109 &Ops[0], Ops.size());
5110 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5113 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5114 /// specified intrinsic ID.
5115 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5116 SelectionDAG &DAG, SDLoc dl,
5117 EVT DestVT = MVT::Other) {
5118 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5119 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5120 DAG.getConstant(IID, MVT::i32), Op);
5123 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5124 /// specified intrinsic ID.
5125 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5126 SelectionDAG &DAG, SDLoc dl,
5127 EVT DestVT = MVT::Other) {
5128 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5129 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5130 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5133 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5134 /// specified intrinsic ID.
5135 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5136 SDValue Op2, SelectionDAG &DAG,
5137 SDLoc dl, EVT DestVT = MVT::Other) {
5138 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5139 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5140 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5144 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5145 /// amount. The result has the specified value type.
5146 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5147 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5148 // Force LHS/RHS to be the right type.
5149 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5150 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5153 for (unsigned i = 0; i != 16; ++i)
5155 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5156 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5159 // If this is a case we can't handle, return null and let the default
5160 // expansion code take care of it. If we CAN select this case, and if it
5161 // selects to a single instruction, return Op. Otherwise, if we can codegen
5162 // this case more efficiently than a constant pool load, lower it to the
5163 // sequence of ops that should be used.
5164 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5165 SelectionDAG &DAG) const {
5167 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5168 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5170 // Check if this is a splat of a constant value.
5171 APInt APSplatBits, APSplatUndef;
5172 unsigned SplatBitSize;
5174 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5175 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5178 unsigned SplatBits = APSplatBits.getZExtValue();
5179 unsigned SplatUndef = APSplatUndef.getZExtValue();
5180 unsigned SplatSize = SplatBitSize / 8;
5182 // First, handle single instruction cases.
5185 if (SplatBits == 0) {
5186 // Canonicalize all zero vectors to be v4i32.
5187 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5188 SDValue Z = DAG.getConstant(0, MVT::i32);
5189 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5190 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5195 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5196 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5198 if (SextVal >= -16 && SextVal <= 15)
5199 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5202 // Two instruction sequences.
5204 // If this value is in the range [-32,30] and is even, use:
5205 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5206 // If this value is in the range [17,31] and is odd, use:
5207 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5208 // If this value is in the range [-31,-17] and is odd, use:
5209 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5210 // Note the last two are three-instruction sequences.
5211 if (SextVal >= -32 && SextVal <= 31) {
5212 // To avoid having these optimizations undone by constant folding,
5213 // we convert to a pseudo that will be expanded later into one of
5215 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5216 EVT VT = Op.getValueType();
5217 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5218 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5219 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5222 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5223 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5225 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5226 // Make -1 and vspltisw -1:
5227 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5229 // Make the VSLW intrinsic, computing 0x8000_0000.
5230 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5233 // xor by OnesV to invert it.
5234 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5235 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5238 // Check to see if this is a wide variety of vsplti*, binop self cases.
5239 static const signed char SplatCsts[] = {
5240 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5241 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5244 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5245 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5246 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5247 int i = SplatCsts[idx];
5249 // Figure out what shift amount will be used by altivec if shifted by i in
5251 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5253 // vsplti + shl self.
5254 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5255 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5256 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5257 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5258 Intrinsic::ppc_altivec_vslw
5260 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5261 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5264 // vsplti + srl self.
5265 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5266 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5267 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5268 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5269 Intrinsic::ppc_altivec_vsrw
5271 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5272 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5275 // vsplti + sra self.
5276 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5277 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5278 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5279 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5280 Intrinsic::ppc_altivec_vsraw
5282 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5283 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5286 // vsplti + rol self.
5287 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5288 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5289 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5290 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5291 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5292 Intrinsic::ppc_altivec_vrlw
5294 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5295 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5298 // t = vsplti c, result = vsldoi t, t, 1
5299 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5300 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5301 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5303 // t = vsplti c, result = vsldoi t, t, 2
5304 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5305 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5306 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5308 // t = vsplti c, result = vsldoi t, t, 3
5309 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5310 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5311 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5318 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5319 /// the specified operations to build the shuffle.
5320 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5321 SDValue RHS, SelectionDAG &DAG,
5323 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5324 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5325 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5328 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5340 if (OpNum == OP_COPY) {
5341 if (LHSID == (1*9+2)*9+3) return LHS;
5342 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5346 SDValue OpLHS, OpRHS;
5347 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5348 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5352 default: llvm_unreachable("Unknown i32 permute!");
5354 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5355 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5356 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5357 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5360 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5361 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5362 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5363 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5366 for (unsigned i = 0; i != 16; ++i)
5367 ShufIdxs[i] = (i&3)+0;
5370 for (unsigned i = 0; i != 16; ++i)
5371 ShufIdxs[i] = (i&3)+4;
5374 for (unsigned i = 0; i != 16; ++i)
5375 ShufIdxs[i] = (i&3)+8;
5378 for (unsigned i = 0; i != 16; ++i)
5379 ShufIdxs[i] = (i&3)+12;
5382 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5384 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5386 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5388 EVT VT = OpLHS.getValueType();
5389 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5390 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5391 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5392 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5395 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5396 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5397 /// return the code it can be lowered into. Worst case, it can always be
5398 /// lowered into a vperm.
5399 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5400 SelectionDAG &DAG) const {
5402 SDValue V1 = Op.getOperand(0);
5403 SDValue V2 = Op.getOperand(1);
5404 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5405 EVT VT = Op.getValueType();
5407 // Cases that are handled by instructions that take permute immediates
5408 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5409 // selected by the instruction selector.
5410 if (V2.getOpcode() == ISD::UNDEF) {
5411 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5412 PPC::isSplatShuffleMask(SVOp, 2) ||
5413 PPC::isSplatShuffleMask(SVOp, 4) ||
5414 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5415 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5416 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5417 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5418 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5419 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5420 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5421 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5422 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5427 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5428 // and produce a fixed permutation. If any of these match, do not lower to
5430 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5431 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5432 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5433 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5434 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5435 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5436 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5437 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5438 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5441 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5442 // perfect shuffle table to emit an optimal matching sequence.
5443 ArrayRef<int> PermMask = SVOp->getMask();
5445 unsigned PFIndexes[4];
5446 bool isFourElementShuffle = true;
5447 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5448 unsigned EltNo = 8; // Start out undef.
5449 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5450 if (PermMask[i*4+j] < 0)
5451 continue; // Undef, ignore it.
5453 unsigned ByteSource = PermMask[i*4+j];
5454 if ((ByteSource & 3) != j) {
5455 isFourElementShuffle = false;
5460 EltNo = ByteSource/4;
5461 } else if (EltNo != ByteSource/4) {
5462 isFourElementShuffle = false;
5466 PFIndexes[i] = EltNo;
5469 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5470 // perfect shuffle vector to determine if it is cost effective to do this as
5471 // discrete instructions, or whether we should use a vperm.
5472 if (isFourElementShuffle) {
5473 // Compute the index in the perfect shuffle table.
5474 unsigned PFTableIndex =
5475 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5477 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5478 unsigned Cost = (PFEntry >> 30);
5480 // Determining when to avoid vperm is tricky. Many things affect the cost
5481 // of vperm, particularly how many times the perm mask needs to be computed.
5482 // For example, if the perm mask can be hoisted out of a loop or is already
5483 // used (perhaps because there are multiple permutes with the same shuffle
5484 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5485 // the loop requires an extra register.
5487 // As a compromise, we only emit discrete instructions if the shuffle can be
5488 // generated in 3 or fewer operations. When we have loop information
5489 // available, if this block is within a loop, we should avoid using vperm
5490 // for 3-operation perms and use a constant pool load instead.
5492 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5495 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5496 // vector that will get spilled to the constant pool.
5497 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5499 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5500 // that it is in input element units, not in bytes. Convert now.
5501 EVT EltVT = V1.getValueType().getVectorElementType();
5502 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5504 SmallVector<SDValue, 16> ResultMask;
5505 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5506 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5508 for (unsigned j = 0; j != BytesPerElement; ++j)
5509 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5513 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5514 &ResultMask[0], ResultMask.size());
5515 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5518 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5519 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5520 /// information about the intrinsic.
5521 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5523 unsigned IntrinsicID =
5524 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5527 switch (IntrinsicID) {
5528 default: return false;
5529 // Comparison predicates.
5530 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5531 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5532 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5533 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5534 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5535 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5536 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5537 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5538 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5539 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5540 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5541 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5542 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5544 // Normal Comparisons.
5545 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5546 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5547 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5548 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5549 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5550 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5551 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5552 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5553 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5554 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5555 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5556 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5557 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5562 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5563 /// lower, do it, otherwise return null.
5564 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5565 SelectionDAG &DAG) const {
5566 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5567 // opcode number of the comparison.
5571 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5572 return SDValue(); // Don't custom lower most intrinsics.
5574 // If this is a non-dot comparison, make the VCMP node and we are done.
5576 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5577 Op.getOperand(1), Op.getOperand(2),
5578 DAG.getConstant(CompareOpc, MVT::i32));
5579 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5582 // Create the PPCISD altivec 'dot' comparison node.
5584 Op.getOperand(2), // LHS
5585 Op.getOperand(3), // RHS
5586 DAG.getConstant(CompareOpc, MVT::i32)
5588 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5589 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5591 // Now that we have the comparison, emit a copy from the CR to a GPR.
5592 // This is flagged to the above dot comparison.
5593 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5594 DAG.getRegister(PPC::CR6, MVT::i32),
5595 CompNode.getValue(1));
5597 // Unpack the result based on how the target uses it.
5598 unsigned BitNo; // Bit # of CR6.
5599 bool InvertBit; // Invert result?
5600 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5601 default: // Can't happen, don't crash on invalid number though.
5602 case 0: // Return the value of the EQ bit of CR6.
5603 BitNo = 0; InvertBit = false;
5605 case 1: // Return the inverted value of the EQ bit of CR6.
5606 BitNo = 0; InvertBit = true;
5608 case 2: // Return the value of the LT bit of CR6.
5609 BitNo = 2; InvertBit = false;
5611 case 3: // Return the inverted value of the LT bit of CR6.
5612 BitNo = 2; InvertBit = true;
5616 // Shift the bit into the low position.
5617 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5618 DAG.getConstant(8-(3-BitNo), MVT::i32));
5620 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5621 DAG.getConstant(1, MVT::i32));
5623 // If we are supposed to, toggle the bit.
5625 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5626 DAG.getConstant(1, MVT::i32));
5630 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5631 SelectionDAG &DAG) const {
5633 // Create a stack slot that is 16-byte aligned.
5634 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5635 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5636 EVT PtrVT = getPointerTy();
5637 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5639 // Store the input value into Value#0 of the stack slot.
5640 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5641 Op.getOperand(0), FIdx, MachinePointerInfo(),
5644 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5645 false, false, false, 0);
5648 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5650 if (Op.getValueType() == MVT::v4i32) {
5651 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5653 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5654 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5656 SDValue RHSSwap = // = vrlw RHS, 16
5657 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5659 // Shrinkify inputs to v8i16.
5660 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5661 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5662 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5664 // Low parts multiplied together, generating 32-bit results (we ignore the
5666 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5667 LHS, RHS, DAG, dl, MVT::v4i32);
5669 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5670 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5671 // Shift the high parts up 16 bits.
5672 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5674 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5675 } else if (Op.getValueType() == MVT::v8i16) {
5676 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5678 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5680 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5681 LHS, RHS, Zero, DAG, dl);
5682 } else if (Op.getValueType() == MVT::v16i8) {
5683 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5685 // Multiply the even 8-bit parts, producing 16-bit sums.
5686 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5687 LHS, RHS, DAG, dl, MVT::v8i16);
5688 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5690 // Multiply the odd 8-bit parts, producing 16-bit sums.
5691 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5692 LHS, RHS, DAG, dl, MVT::v8i16);
5693 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5695 // Merge the results together.
5697 for (unsigned i = 0; i != 8; ++i) {
5699 Ops[i*2+1] = 2*i+1+16;
5701 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5703 llvm_unreachable("Unknown mul to lower!");
5707 /// LowerOperation - Provide custom lowering hooks for some operations.
5709 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5710 switch (Op.getOpcode()) {
5711 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5712 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5713 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5714 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5715 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5716 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5717 case ISD::SETCC: return LowerSETCC(Op, DAG);
5718 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5719 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5721 return LowerVASTART(Op, DAG, PPCSubTarget);
5724 return LowerVAARG(Op, DAG, PPCSubTarget);
5727 return LowerVACOPY(Op, DAG, PPCSubTarget);
5729 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5730 case ISD::DYNAMIC_STACKALLOC:
5731 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5733 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5734 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5736 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5737 case ISD::FP_TO_UINT:
5738 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5740 case ISD::UINT_TO_FP:
5741 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5742 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5744 // Lower 64-bit shifts.
5745 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5746 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5747 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5749 // Vector-related lowering.
5750 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5751 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5752 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5753 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5754 case ISD::MUL: return LowerMUL(Op, DAG);
5756 // For counter-based loop handling.
5757 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5759 // Frame & Return address.
5760 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5761 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5765 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5766 SmallVectorImpl<SDValue>&Results,
5767 SelectionDAG &DAG) const {
5768 const TargetMachine &TM = getTargetMachine();
5770 switch (N->getOpcode()) {
5772 llvm_unreachable("Do not know how to custom type legalize this operation!");
5773 case ISD::INTRINSIC_W_CHAIN: {
5774 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
5775 Intrinsic::ppc_is_decremented_ctr_nonzero)
5778 assert(N->getValueType(0) == MVT::i1 &&
5779 "Unexpected result type for CTR decrement intrinsic");
5780 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
5781 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5782 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
5785 Results.push_back(NewInt);
5786 Results.push_back(NewInt.getValue(1));
5790 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5791 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5794 EVT VT = N->getValueType(0);
5796 if (VT == MVT::i64) {
5797 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5799 Results.push_back(NewNode);
5800 Results.push_back(NewNode.getValue(1));
5804 case ISD::FP_ROUND_INREG: {
5805 assert(N->getValueType(0) == MVT::ppcf128);
5806 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5807 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5808 MVT::f64, N->getOperand(0),
5809 DAG.getIntPtrConstant(0));
5810 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5811 MVT::f64, N->getOperand(0),
5812 DAG.getIntPtrConstant(1));
5814 // Add the two halves of the long double in round-to-zero mode.
5815 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5817 // We know the low half is about to be thrown away, so just use something
5819 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5823 case ISD::FP_TO_SINT:
5824 // LowerFP_TO_INT() can only handle f32 and f64.
5825 if (N->getOperand(0).getValueType() == MVT::ppcf128)
5827 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5833 //===----------------------------------------------------------------------===//
5834 // Other Lowering Code
5835 //===----------------------------------------------------------------------===//
5838 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5839 bool is64bit, unsigned BinOpcode) const {
5840 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5841 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5843 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5844 MachineFunction *F = BB->getParent();
5845 MachineFunction::iterator It = BB;
5848 unsigned dest = MI->getOperand(0).getReg();
5849 unsigned ptrA = MI->getOperand(1).getReg();
5850 unsigned ptrB = MI->getOperand(2).getReg();
5851 unsigned incr = MI->getOperand(3).getReg();
5852 DebugLoc dl = MI->getDebugLoc();
5854 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5855 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5856 F->insert(It, loopMBB);
5857 F->insert(It, exitMBB);
5858 exitMBB->splice(exitMBB->begin(), BB,
5859 llvm::next(MachineBasicBlock::iterator(MI)),
5861 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5863 MachineRegisterInfo &RegInfo = F->getRegInfo();
5864 unsigned TmpReg = (!BinOpcode) ? incr :
5865 RegInfo.createVirtualRegister(
5866 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5867 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5871 // fallthrough --> loopMBB
5872 BB->addSuccessor(loopMBB);
5875 // l[wd]arx dest, ptr
5876 // add r0, dest, incr
5877 // st[wd]cx. r0, ptr
5879 // fallthrough --> exitMBB
5881 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5882 .addReg(ptrA).addReg(ptrB);
5884 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5885 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5886 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5887 BuildMI(BB, dl, TII->get(PPC::BCC))
5888 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5889 BB->addSuccessor(loopMBB);
5890 BB->addSuccessor(exitMBB);
5899 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5900 MachineBasicBlock *BB,
5901 bool is8bit, // operation
5902 unsigned BinOpcode) const {
5903 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5904 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5905 // In 64 bit mode we have to use 64 bits for addresses, even though the
5906 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5907 // registers without caring whether they're 32 or 64, but here we're
5908 // doing actual arithmetic on the addresses.
5909 bool is64bit = PPCSubTarget.isPPC64();
5910 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5912 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5913 MachineFunction *F = BB->getParent();
5914 MachineFunction::iterator It = BB;
5917 unsigned dest = MI->getOperand(0).getReg();
5918 unsigned ptrA = MI->getOperand(1).getReg();
5919 unsigned ptrB = MI->getOperand(2).getReg();
5920 unsigned incr = MI->getOperand(3).getReg();
5921 DebugLoc dl = MI->getDebugLoc();
5923 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5924 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5925 F->insert(It, loopMBB);
5926 F->insert(It, exitMBB);
5927 exitMBB->splice(exitMBB->begin(), BB,
5928 llvm::next(MachineBasicBlock::iterator(MI)),
5930 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5932 MachineRegisterInfo &RegInfo = F->getRegInfo();
5933 const TargetRegisterClass *RC =
5934 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5935 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5936 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5937 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5938 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5939 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5940 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5941 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5942 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5943 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5944 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5945 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5946 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5948 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5952 // fallthrough --> loopMBB
5953 BB->addSuccessor(loopMBB);
5955 // The 4-byte load must be aligned, while a char or short may be
5956 // anywhere in the word. Hence all this nasty bookkeeping code.
5957 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5958 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5959 // xori shift, shift1, 24 [16]
5960 // rlwinm ptr, ptr1, 0, 0, 29
5961 // slw incr2, incr, shift
5962 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5963 // slw mask, mask2, shift
5965 // lwarx tmpDest, ptr
5966 // add tmp, tmpDest, incr2
5967 // andc tmp2, tmpDest, mask
5968 // and tmp3, tmp, mask
5969 // or tmp4, tmp3, tmp2
5972 // fallthrough --> exitMBB
5973 // srw dest, tmpDest, shift
5974 if (ptrA != ZeroReg) {
5975 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5976 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5977 .addReg(ptrA).addReg(ptrB);
5981 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5982 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5983 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5984 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5986 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5987 .addReg(Ptr1Reg).addImm(0).addImm(61);
5989 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5990 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5991 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5992 .addReg(incr).addReg(ShiftReg);
5994 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5996 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5997 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5999 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6000 .addReg(Mask2Reg).addReg(ShiftReg);
6003 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6004 .addReg(ZeroReg).addReg(PtrReg);
6006 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6007 .addReg(Incr2Reg).addReg(TmpDestReg);
6008 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6009 .addReg(TmpDestReg).addReg(MaskReg);
6010 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6011 .addReg(TmpReg).addReg(MaskReg);
6012 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6013 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6014 BuildMI(BB, dl, TII->get(PPC::STWCX))
6015 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6016 BuildMI(BB, dl, TII->get(PPC::BCC))
6017 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6018 BB->addSuccessor(loopMBB);
6019 BB->addSuccessor(exitMBB);
6024 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6029 llvm::MachineBasicBlock*
6030 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6031 MachineBasicBlock *MBB) const {
6032 DebugLoc DL = MI->getDebugLoc();
6033 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6035 MachineFunction *MF = MBB->getParent();
6036 MachineRegisterInfo &MRI = MF->getRegInfo();
6038 const BasicBlock *BB = MBB->getBasicBlock();
6039 MachineFunction::iterator I = MBB;
6043 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6044 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6046 unsigned DstReg = MI->getOperand(0).getReg();
6047 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6048 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6049 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6050 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6052 MVT PVT = getPointerTy();
6053 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6054 "Invalid Pointer Size!");
6055 // For v = setjmp(buf), we generate
6058 // SjLjSetup mainMBB
6064 // buf[LabelOffset] = LR
6068 // v = phi(main, restore)
6071 MachineBasicBlock *thisMBB = MBB;
6072 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6073 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6074 MF->insert(I, mainMBB);
6075 MF->insert(I, sinkMBB);
6077 MachineInstrBuilder MIB;
6079 // Transfer the remainder of BB and its successor edges to sinkMBB.
6080 sinkMBB->splice(sinkMBB->begin(), MBB,
6081 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6082 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6084 // Note that the structure of the jmp_buf used here is not compatible
6085 // with that used by libc, and is not designed to be. Specifically, it
6086 // stores only those 'reserved' registers that LLVM does not otherwise
6087 // understand how to spill. Also, by convention, by the time this
6088 // intrinsic is called, Clang has already stored the frame address in the
6089 // first slot of the buffer and stack address in the third. Following the
6090 // X86 target code, we'll store the jump address in the second slot. We also
6091 // need to save the TOC pointer (R2) to handle jumps between shared
6092 // libraries, and that will be stored in the fourth slot. The thread
6093 // identifier (R13) is not affected.
6096 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6097 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6098 const int64_t BPOffset = 4 * PVT.getStoreSize();
6100 // Prepare IP either in reg.
6101 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6102 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6103 unsigned BufReg = MI->getOperand(1).getReg();
6105 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6106 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6110 MIB.setMemRefs(MMOBegin, MMOEnd);
6113 // Naked functions never have a base pointer, and so we use r1. For all
6114 // other functions, this decision must be delayed until during PEI.
6116 if (MF->getFunction()->getAttributes().hasAttribute(
6117 AttributeSet::FunctionIndex, Attribute::Naked))
6118 BaseReg = PPCSubTarget.isPPC64() ? PPC::X1 : PPC::R1;
6120 BaseReg = PPCSubTarget.isPPC64() ? PPC::BP8 : PPC::BP;
6122 MIB = BuildMI(*thisMBB, MI, DL,
6123 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6127 MIB.setMemRefs(MMOBegin, MMOEnd);
6130 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6131 const PPCRegisterInfo *TRI =
6132 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6133 MIB.addRegMask(TRI->getNoPreservedMask());
6135 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6137 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6139 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6141 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6142 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6146 MIB = BuildMI(mainMBB, DL,
6147 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6150 if (PPCSubTarget.isPPC64()) {
6151 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6153 .addImm(LabelOffset)
6156 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6158 .addImm(LabelOffset)
6162 MIB.setMemRefs(MMOBegin, MMOEnd);
6164 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6165 mainMBB->addSuccessor(sinkMBB);
6168 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6169 TII->get(PPC::PHI), DstReg)
6170 .addReg(mainDstReg).addMBB(mainMBB)
6171 .addReg(restoreDstReg).addMBB(thisMBB);
6173 MI->eraseFromParent();
6178 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6179 MachineBasicBlock *MBB) const {
6180 DebugLoc DL = MI->getDebugLoc();
6181 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6183 MachineFunction *MF = MBB->getParent();
6184 MachineRegisterInfo &MRI = MF->getRegInfo();
6187 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6188 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6190 MVT PVT = getPointerTy();
6191 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6192 "Invalid Pointer Size!");
6194 const TargetRegisterClass *RC =
6195 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6196 unsigned Tmp = MRI.createVirtualRegister(RC);
6197 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6198 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6199 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6200 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6202 MachineInstrBuilder MIB;
6204 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6205 const int64_t SPOffset = 2 * PVT.getStoreSize();
6206 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6207 const int64_t BPOffset = 4 * PVT.getStoreSize();
6209 unsigned BufReg = MI->getOperand(0).getReg();
6211 // Reload FP (the jumped-to function may not have had a
6212 // frame pointer, and if so, then its r31 will be restored
6214 if (PVT == MVT::i64) {
6215 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6219 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6223 MIB.setMemRefs(MMOBegin, MMOEnd);
6226 if (PVT == MVT::i64) {
6227 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6228 .addImm(LabelOffset)
6231 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6232 .addImm(LabelOffset)
6235 MIB.setMemRefs(MMOBegin, MMOEnd);
6238 if (PVT == MVT::i64) {
6239 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6243 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6247 MIB.setMemRefs(MMOBegin, MMOEnd);
6250 if (PVT == MVT::i64) {
6251 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6255 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6259 MIB.setMemRefs(MMOBegin, MMOEnd);
6262 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6263 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6267 MIB.setMemRefs(MMOBegin, MMOEnd);
6271 BuildMI(*MBB, MI, DL,
6272 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6273 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6275 MI->eraseFromParent();
6280 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6281 MachineBasicBlock *BB) const {
6282 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6283 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6284 return emitEHSjLjSetJmp(MI, BB);
6285 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6286 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6287 return emitEHSjLjLongJmp(MI, BB);
6290 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6292 // To "insert" these instructions we actually have to insert their
6293 // control-flow patterns.
6294 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6295 MachineFunction::iterator It = BB;
6298 MachineFunction *F = BB->getParent();
6300 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6301 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6302 SmallVector<MachineOperand, 2> Cond;
6303 Cond.push_back(MI->getOperand(4));
6304 Cond.push_back(MI->getOperand(1));
6306 DebugLoc dl = MI->getDebugLoc();
6307 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6308 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6309 Cond, MI->getOperand(2).getReg(),
6310 MI->getOperand(3).getReg());
6311 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6312 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6313 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6314 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6315 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6318 // The incoming instruction knows the destination vreg to set, the
6319 // condition code register to branch on, the true/false values to
6320 // select between, and a branch opcode to use.
6325 // cmpTY ccX, r1, r2
6327 // fallthrough --> copy0MBB
6328 MachineBasicBlock *thisMBB = BB;
6329 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6330 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6331 unsigned SelectPred = MI->getOperand(4).getImm();
6332 DebugLoc dl = MI->getDebugLoc();
6333 F->insert(It, copy0MBB);
6334 F->insert(It, sinkMBB);
6336 // Transfer the remainder of BB and its successor edges to sinkMBB.
6337 sinkMBB->splice(sinkMBB->begin(), BB,
6338 llvm::next(MachineBasicBlock::iterator(MI)),
6340 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6342 // Next, add the true and fallthrough blocks as its successors.
6343 BB->addSuccessor(copy0MBB);
6344 BB->addSuccessor(sinkMBB);
6346 BuildMI(BB, dl, TII->get(PPC::BCC))
6347 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6350 // %FalseValue = ...
6351 // # fallthrough to sinkMBB
6354 // Update machine-CFG edges
6355 BB->addSuccessor(sinkMBB);
6358 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6361 BuildMI(*BB, BB->begin(), dl,
6362 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6363 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6364 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6366 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6367 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6368 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6369 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6370 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6371 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6372 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6373 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6375 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6376 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6377 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6378 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6379 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6380 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6381 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6382 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6384 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6385 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6386 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6387 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6388 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6389 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6390 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6391 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6393 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6394 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6395 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6396 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6397 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6398 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6399 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6400 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6402 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6403 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6404 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6405 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6406 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6407 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6408 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6409 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6411 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6412 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6413 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6414 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6415 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6416 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6417 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6418 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6420 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6421 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6422 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6423 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6424 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6425 BB = EmitAtomicBinary(MI, BB, false, 0);
6426 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6427 BB = EmitAtomicBinary(MI, BB, true, 0);
6429 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6430 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6431 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6433 unsigned dest = MI->getOperand(0).getReg();
6434 unsigned ptrA = MI->getOperand(1).getReg();
6435 unsigned ptrB = MI->getOperand(2).getReg();
6436 unsigned oldval = MI->getOperand(3).getReg();
6437 unsigned newval = MI->getOperand(4).getReg();
6438 DebugLoc dl = MI->getDebugLoc();
6440 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6441 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6442 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6443 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6444 F->insert(It, loop1MBB);
6445 F->insert(It, loop2MBB);
6446 F->insert(It, midMBB);
6447 F->insert(It, exitMBB);
6448 exitMBB->splice(exitMBB->begin(), BB,
6449 llvm::next(MachineBasicBlock::iterator(MI)),
6451 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6455 // fallthrough --> loopMBB
6456 BB->addSuccessor(loop1MBB);
6459 // l[wd]arx dest, ptr
6460 // cmp[wd] dest, oldval
6463 // st[wd]cx. newval, ptr
6467 // st[wd]cx. dest, ptr
6470 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6471 .addReg(ptrA).addReg(ptrB);
6472 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6473 .addReg(oldval).addReg(dest);
6474 BuildMI(BB, dl, TII->get(PPC::BCC))
6475 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6476 BB->addSuccessor(loop2MBB);
6477 BB->addSuccessor(midMBB);
6480 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6481 .addReg(newval).addReg(ptrA).addReg(ptrB);
6482 BuildMI(BB, dl, TII->get(PPC::BCC))
6483 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6484 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6485 BB->addSuccessor(loop1MBB);
6486 BB->addSuccessor(exitMBB);
6489 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6490 .addReg(dest).addReg(ptrA).addReg(ptrB);
6491 BB->addSuccessor(exitMBB);
6496 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6497 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6498 // We must use 64-bit registers for addresses when targeting 64-bit,
6499 // since we're actually doing arithmetic on them. Other registers
6501 bool is64bit = PPCSubTarget.isPPC64();
6502 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6504 unsigned dest = MI->getOperand(0).getReg();
6505 unsigned ptrA = MI->getOperand(1).getReg();
6506 unsigned ptrB = MI->getOperand(2).getReg();
6507 unsigned oldval = MI->getOperand(3).getReg();
6508 unsigned newval = MI->getOperand(4).getReg();
6509 DebugLoc dl = MI->getDebugLoc();
6511 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6512 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6513 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6514 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6515 F->insert(It, loop1MBB);
6516 F->insert(It, loop2MBB);
6517 F->insert(It, midMBB);
6518 F->insert(It, exitMBB);
6519 exitMBB->splice(exitMBB->begin(), BB,
6520 llvm::next(MachineBasicBlock::iterator(MI)),
6522 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6524 MachineRegisterInfo &RegInfo = F->getRegInfo();
6525 const TargetRegisterClass *RC =
6526 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6527 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6528 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6529 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6530 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6531 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6532 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6533 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6534 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6535 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6536 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6537 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6538 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6539 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6540 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6542 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6543 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6546 // fallthrough --> loopMBB
6547 BB->addSuccessor(loop1MBB);
6549 // The 4-byte load must be aligned, while a char or short may be
6550 // anywhere in the word. Hence all this nasty bookkeeping code.
6551 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6552 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6553 // xori shift, shift1, 24 [16]
6554 // rlwinm ptr, ptr1, 0, 0, 29
6555 // slw newval2, newval, shift
6556 // slw oldval2, oldval,shift
6557 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6558 // slw mask, mask2, shift
6559 // and newval3, newval2, mask
6560 // and oldval3, oldval2, mask
6562 // lwarx tmpDest, ptr
6563 // and tmp, tmpDest, mask
6564 // cmpw tmp, oldval3
6567 // andc tmp2, tmpDest, mask
6568 // or tmp4, tmp2, newval3
6573 // stwcx. tmpDest, ptr
6575 // srw dest, tmpDest, shift
6576 if (ptrA != ZeroReg) {
6577 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6578 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6579 .addReg(ptrA).addReg(ptrB);
6583 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6584 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6585 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6586 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6588 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6589 .addReg(Ptr1Reg).addImm(0).addImm(61);
6591 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6592 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6593 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6594 .addReg(newval).addReg(ShiftReg);
6595 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6596 .addReg(oldval).addReg(ShiftReg);
6598 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6600 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6601 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6602 .addReg(Mask3Reg).addImm(65535);
6604 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6605 .addReg(Mask2Reg).addReg(ShiftReg);
6606 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6607 .addReg(NewVal2Reg).addReg(MaskReg);
6608 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6609 .addReg(OldVal2Reg).addReg(MaskReg);
6612 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6613 .addReg(ZeroReg).addReg(PtrReg);
6614 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6615 .addReg(TmpDestReg).addReg(MaskReg);
6616 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6617 .addReg(TmpReg).addReg(OldVal3Reg);
6618 BuildMI(BB, dl, TII->get(PPC::BCC))
6619 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6620 BB->addSuccessor(loop2MBB);
6621 BB->addSuccessor(midMBB);
6624 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6625 .addReg(TmpDestReg).addReg(MaskReg);
6626 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6627 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6628 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6629 .addReg(ZeroReg).addReg(PtrReg);
6630 BuildMI(BB, dl, TII->get(PPC::BCC))
6631 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6632 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6633 BB->addSuccessor(loop1MBB);
6634 BB->addSuccessor(exitMBB);
6637 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6638 .addReg(ZeroReg).addReg(PtrReg);
6639 BB->addSuccessor(exitMBB);
6644 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6646 } else if (MI->getOpcode() == PPC::FADDrtz) {
6647 // This pseudo performs an FADD with rounding mode temporarily forced
6648 // to round-to-zero. We emit this via custom inserter since the FPSCR
6649 // is not modeled at the SelectionDAG level.
6650 unsigned Dest = MI->getOperand(0).getReg();
6651 unsigned Src1 = MI->getOperand(1).getReg();
6652 unsigned Src2 = MI->getOperand(2).getReg();
6653 DebugLoc dl = MI->getDebugLoc();
6655 MachineRegisterInfo &RegInfo = F->getRegInfo();
6656 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6658 // Save FPSCR value.
6659 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6661 // Set rounding mode to round-to-zero.
6662 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6663 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6665 // Perform addition.
6666 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6668 // Restore FPSCR value.
6669 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6671 llvm_unreachable("Unexpected instr type to insert");
6674 MI->eraseFromParent(); // The pseudo instruction is gone now.
6678 //===----------------------------------------------------------------------===//
6679 // Target Optimization Hooks
6680 //===----------------------------------------------------------------------===//
6682 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6683 DAGCombinerInfo &DCI) const {
6684 if (DCI.isAfterLegalizeVectorOps())
6687 EVT VT = Op.getValueType();
6689 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6690 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6691 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6693 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6694 // For the reciprocal, we need to find the zero of the function:
6695 // F(X) = A X - 1 [which has a zero at X = 1/A]
6697 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6698 // does not require additional intermediate precision]
6700 // Convergence is quadratic, so we essentially double the number of digits
6701 // correct after every iteration. The minimum architected relative
6702 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6703 // 23 digits and double has 52 digits.
6704 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6705 if (VT.getScalarType() == MVT::f64)
6708 SelectionDAG &DAG = DCI.DAG;
6712 DAG.getConstantFP(1.0, VT.getScalarType());
6713 if (VT.isVector()) {
6714 assert(VT.getVectorNumElements() == 4 &&
6715 "Unknown vector type");
6716 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6717 FPOne, FPOne, FPOne, FPOne);
6720 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6721 DCI.AddToWorklist(Est.getNode());
6723 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6724 for (int i = 0; i < Iterations; ++i) {
6725 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6726 DCI.AddToWorklist(NewEst.getNode());
6728 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6729 DCI.AddToWorklist(NewEst.getNode());
6731 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6732 DCI.AddToWorklist(NewEst.getNode());
6734 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6735 DCI.AddToWorklist(Est.getNode());
6744 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6745 DAGCombinerInfo &DCI) const {
6746 if (DCI.isAfterLegalizeVectorOps())
6749 EVT VT = Op.getValueType();
6751 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6752 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6753 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6755 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6756 // For the reciprocal sqrt, we need to find the zero of the function:
6757 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6759 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6760 // As a result, we precompute A/2 prior to the iteration loop.
6762 // Convergence is quadratic, so we essentially double the number of digits
6763 // correct after every iteration. The minimum architected relative
6764 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6765 // 23 digits and double has 52 digits.
6766 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6767 if (VT.getScalarType() == MVT::f64)
6770 SelectionDAG &DAG = DCI.DAG;
6773 SDValue FPThreeHalves =
6774 DAG.getConstantFP(1.5, VT.getScalarType());
6775 if (VT.isVector()) {
6776 assert(VT.getVectorNumElements() == 4 &&
6777 "Unknown vector type");
6778 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6779 FPThreeHalves, FPThreeHalves,
6780 FPThreeHalves, FPThreeHalves);
6783 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6784 DCI.AddToWorklist(Est.getNode());
6786 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6787 // this entire sequence requires only one FP constant.
6788 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6789 DCI.AddToWorklist(HalfArg.getNode());
6791 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6792 DCI.AddToWorklist(HalfArg.getNode());
6794 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6795 for (int i = 0; i < Iterations; ++i) {
6796 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6797 DCI.AddToWorklist(NewEst.getNode());
6799 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6800 DCI.AddToWorklist(NewEst.getNode());
6802 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6803 DCI.AddToWorklist(NewEst.getNode());
6805 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6806 DCI.AddToWorklist(Est.getNode());
6815 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
6816 // not enforce equality of the chain operands.
6817 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
6818 unsigned Bytes, int Dist,
6819 SelectionDAG &DAG) {
6820 EVT VT = LS->getMemoryVT();
6821 if (VT.getSizeInBits() / 8 != Bytes)
6824 SDValue Loc = LS->getBasePtr();
6825 SDValue BaseLoc = Base->getBasePtr();
6826 if (Loc.getOpcode() == ISD::FrameIndex) {
6827 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6829 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6830 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
6831 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
6832 int FS = MFI->getObjectSize(FI);
6833 int BFS = MFI->getObjectSize(BFI);
6834 if (FS != BFS || FS != (int)Bytes) return false;
6835 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
6839 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
6840 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
6843 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6844 const GlobalValue *GV1 = NULL;
6845 const GlobalValue *GV2 = NULL;
6846 int64_t Offset1 = 0;
6847 int64_t Offset2 = 0;
6848 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
6849 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
6850 if (isGA1 && isGA2 && GV1 == GV2)
6851 return Offset1 == (Offset2 + Dist*Bytes);
6855 // Return true is there is a nearyby consecutive load to the one provided
6856 // (regardless of alignment). We search up and down the chain, looking though
6857 // token factors and other loads (but nothing else). As a result, a true
6858 // results indicates that it is safe to create a new consecutive load adjacent
6859 // to the load provided.
6860 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
6861 SDValue Chain = LD->getChain();
6862 EVT VT = LD->getMemoryVT();
6864 SmallSet<SDNode *, 16> LoadRoots;
6865 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
6866 SmallSet<SDNode *, 16> Visited;
6868 // First, search up the chain, branching to follow all token-factor operands.
6869 // If we find a consecutive load, then we're done, otherwise, record all
6870 // nodes just above the top-level loads and token factors.
6871 while (!Queue.empty()) {
6872 SDNode *ChainNext = Queue.pop_back_val();
6873 if (!Visited.insert(ChainNext))
6876 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
6877 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6880 if (!Visited.count(ChainLD->getChain().getNode()))
6881 Queue.push_back(ChainLD->getChain().getNode());
6882 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
6883 for (SDNode::op_iterator O = ChainNext->op_begin(),
6884 OE = ChainNext->op_end(); O != OE; ++O)
6885 if (!Visited.count(O->getNode()))
6886 Queue.push_back(O->getNode());
6888 LoadRoots.insert(ChainNext);
6891 // Second, search down the chain, starting from the top-level nodes recorded
6892 // in the first phase. These top-level nodes are the nodes just above all
6893 // loads and token factors. Starting with their uses, recursively look though
6894 // all loads (just the chain uses) and token factors to find a consecutive
6899 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
6900 IE = LoadRoots.end(); I != IE; ++I) {
6901 Queue.push_back(*I);
6903 while (!Queue.empty()) {
6904 SDNode *LoadRoot = Queue.pop_back_val();
6905 if (!Visited.insert(LoadRoot))
6908 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
6909 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6912 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
6913 UE = LoadRoot->use_end(); UI != UE; ++UI)
6914 if (((isa<LoadSDNode>(*UI) &&
6915 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
6916 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
6917 Queue.push_back(*UI);
6924 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6925 DAGCombinerInfo &DCI) const {
6926 const TargetMachine &TM = getTargetMachine();
6927 SelectionDAG &DAG = DCI.DAG;
6929 switch (N->getOpcode()) {
6932 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6933 if (C->isNullValue()) // 0 << V -> 0.
6934 return N->getOperand(0);
6938 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6939 if (C->isNullValue()) // 0 >>u V -> 0.
6940 return N->getOperand(0);
6944 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6945 if (C->isNullValue() || // 0 >>s V -> 0.
6946 C->isAllOnesValue()) // -1 >>s V -> -1.
6947 return N->getOperand(0);
6951 assert(TM.Options.UnsafeFPMath &&
6952 "Reciprocal estimates require UnsafeFPMath");
6954 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
6956 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
6957 if (RV.getNode() != 0) {
6958 DCI.AddToWorklist(RV.getNode());
6959 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6960 N->getOperand(0), RV);
6962 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
6963 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6965 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6967 if (RV.getNode() != 0) {
6968 DCI.AddToWorklist(RV.getNode());
6969 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
6970 N->getValueType(0), RV);
6971 DCI.AddToWorklist(RV.getNode());
6972 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6973 N->getOperand(0), RV);
6975 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
6976 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6978 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6980 if (RV.getNode() != 0) {
6981 DCI.AddToWorklist(RV.getNode());
6982 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
6983 N->getValueType(0), RV,
6984 N->getOperand(1).getOperand(1));
6985 DCI.AddToWorklist(RV.getNode());
6986 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6987 N->getOperand(0), RV);
6991 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
6992 if (RV.getNode() != 0) {
6993 DCI.AddToWorklist(RV.getNode());
6994 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6995 N->getOperand(0), RV);
7001 assert(TM.Options.UnsafeFPMath &&
7002 "Reciprocal estimates require UnsafeFPMath");
7004 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7006 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7007 if (RV.getNode() != 0) {
7008 DCI.AddToWorklist(RV.getNode());
7009 RV = DAGCombineFastRecip(RV, DCI);
7010 if (RV.getNode() != 0)
7016 case ISD::SINT_TO_FP:
7017 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
7018 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7019 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
7020 // We allow the src/dst to be either f32/f64, but the intermediate
7021 // type must be i64.
7022 if (N->getOperand(0).getValueType() == MVT::i64 &&
7023 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7024 SDValue Val = N->getOperand(0).getOperand(0);
7025 if (Val.getValueType() == MVT::f32) {
7026 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7027 DCI.AddToWorklist(Val.getNode());
7030 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7031 DCI.AddToWorklist(Val.getNode());
7032 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7033 DCI.AddToWorklist(Val.getNode());
7034 if (N->getValueType(0) == MVT::f32) {
7035 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7036 DAG.getIntPtrConstant(0));
7037 DCI.AddToWorklist(Val.getNode());
7040 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7041 // If the intermediate type is i32, we can avoid the load/store here
7048 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7049 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7050 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7051 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7052 N->getOperand(1).getValueType() == MVT::i32 &&
7053 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7054 SDValue Val = N->getOperand(1).getOperand(0);
7055 if (Val.getValueType() == MVT::f32) {
7056 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7057 DCI.AddToWorklist(Val.getNode());
7059 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7060 DCI.AddToWorklist(Val.getNode());
7063 N->getOperand(0), Val, N->getOperand(2),
7064 DAG.getValueType(N->getOperand(1).getValueType())
7067 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
7068 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7069 cast<StoreSDNode>(N)->getMemoryVT(),
7070 cast<StoreSDNode>(N)->getMemOperand());
7071 DCI.AddToWorklist(Val.getNode());
7075 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
7076 if (cast<StoreSDNode>(N)->isUnindexed() &&
7077 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7078 N->getOperand(1).getNode()->hasOneUse() &&
7079 (N->getOperand(1).getValueType() == MVT::i32 ||
7080 N->getOperand(1).getValueType() == MVT::i16 ||
7081 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7082 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7083 N->getOperand(1).getValueType() == MVT::i64))) {
7084 SDValue BSwapOp = N->getOperand(1).getOperand(0);
7085 // Do an any-extend to 32-bits if this is a half-word input.
7086 if (BSwapOp.getValueType() == MVT::i16)
7087 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7090 N->getOperand(0), BSwapOp, N->getOperand(2),
7091 DAG.getValueType(N->getOperand(1).getValueType())
7094 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7095 Ops, array_lengthof(Ops),
7096 cast<StoreSDNode>(N)->getMemoryVT(),
7097 cast<StoreSDNode>(N)->getMemOperand());
7101 LoadSDNode *LD = cast<LoadSDNode>(N);
7102 EVT VT = LD->getValueType(0);
7103 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
7104 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
7105 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7106 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
7107 DCI.getDAGCombineLevel() == AfterLegalizeTypes &&
7108 LD->getAlignment() < ABIAlignment) {
7109 // This is a type-legal unaligned Altivec load.
7110 SDValue Chain = LD->getChain();
7111 SDValue Ptr = LD->getBasePtr();
7113 // This implements the loading of unaligned vectors as described in
7114 // the venerable Apple Velocity Engine overview. Specifically:
7115 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
7116 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
7118 // The general idea is to expand a sequence of one or more unaligned
7119 // loads into a alignment-based permutation-control instruction (lvsl),
7120 // a series of regular vector loads (which always truncate their
7121 // input address to an aligned address), and a series of permutations.
7122 // The results of these permutations are the requested loaded values.
7123 // The trick is that the last "extra" load is not taken from the address
7124 // you might suspect (sizeof(vector) bytes after the last requested
7125 // load), but rather sizeof(vector) - 1 bytes after the last
7126 // requested vector. The point of this is to avoid a page fault if the
7127 // base address happend to be aligned. This works because if the base
7128 // address is aligned, then adding less than a full vector length will
7129 // cause the last vector in the sequence to be (re)loaded. Otherwise,
7130 // the next vector will be fetched as you might suspect was necessary.
7132 // We might be able to reuse the permutation generation from
7133 // a different base address offset from this one by an aligned amount.
7134 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
7135 // optimization later.
7136 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
7137 DAG, dl, MVT::v16i8);
7139 // Refine the alignment of the original load (a "new" load created here
7140 // which was identical to the first except for the alignment would be
7141 // merged with the existing node regardless).
7142 MachineFunction &MF = DAG.getMachineFunction();
7143 MachineMemOperand *MMO =
7144 MF.getMachineMemOperand(LD->getPointerInfo(),
7145 LD->getMemOperand()->getFlags(),
7146 LD->getMemoryVT().getStoreSize(),
7148 LD->refineAlignment(MMO);
7149 SDValue BaseLoad = SDValue(LD, 0);
7151 // Note that the value of IncOffset (which is provided to the next
7152 // load's pointer info offset value, and thus used to calculate the
7153 // alignment), and the value of IncValue (which is actually used to
7154 // increment the pointer value) are different! This is because we
7155 // require the next load to appear to be aligned, even though it
7156 // is actually offset from the base pointer by a lesser amount.
7157 int IncOffset = VT.getSizeInBits() / 8;
7158 int IncValue = IncOffset;
7160 // Walk (both up and down) the chain looking for another load at the real
7161 // (aligned) offset (the alignment of the other load does not matter in
7162 // this case). If found, then do not use the offset reduction trick, as
7163 // that will prevent the loads from being later combined (as they would
7164 // otherwise be duplicates).
7165 if (!findConsecutiveLoad(LD, DAG))
7168 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
7169 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7172 DAG.getLoad(VT, dl, Chain, Ptr,
7173 LD->getPointerInfo().getWithOffset(IncOffset),
7174 LD->isVolatile(), LD->isNonTemporal(),
7175 LD->isInvariant(), ABIAlignment);
7177 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7178 BaseLoad.getValue(1), ExtraLoad.getValue(1));
7180 if (BaseLoad.getValueType() != MVT::v4i32)
7181 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7183 if (ExtraLoad.getValueType() != MVT::v4i32)
7184 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7186 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
7187 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
7189 if (VT != MVT::v4i32)
7190 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7192 // Now we need to be really careful about how we update the users of the
7193 // original load. We cannot just call DCI.CombineTo (or
7194 // DAG.ReplaceAllUsesWith for that matter), because the load still has
7195 // uses created here (the permutation for example) that need to stay.
7196 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7198 SDUse &Use = UI.getUse();
7200 // Note: BaseLoad is checked here because it might not be N, but a
7202 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
7203 User == TF.getNode() || Use.getResNo() > 1) {
7208 SDValue To = Use.getResNo() ? TF : Perm;
7211 SmallVector<SDValue, 8> Ops;
7212 for (SDNode::op_iterator O = User->op_begin(),
7213 OE = User->op_end(); O != OE; ++O) {
7220 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
7223 return SDValue(N, 0);
7227 case ISD::INTRINSIC_WO_CHAIN:
7228 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
7229 Intrinsic::ppc_altivec_lvsl &&
7230 N->getOperand(1)->getOpcode() == ISD::ADD) {
7231 SDValue Add = N->getOperand(1);
7233 if (DAG.MaskedValueIsZero(Add->getOperand(1),
7234 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
7235 Add.getValueType().getScalarType().getSizeInBits()))) {
7236 SDNode *BasePtr = Add->getOperand(0).getNode();
7237 for (SDNode::use_iterator UI = BasePtr->use_begin(),
7238 UE = BasePtr->use_end(); UI != UE; ++UI) {
7239 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7240 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
7241 Intrinsic::ppc_altivec_lvsl) {
7242 // We've found another LVSL, and this address if an aligned
7243 // multiple of that one. The results will be the same, so use the
7244 // one we've just found instead.
7246 return SDValue(*UI, 0);
7252 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7253 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7254 N->getOperand(0).hasOneUse() &&
7255 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7256 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7257 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7258 N->getValueType(0) == MVT::i64))) {
7259 SDValue Load = N->getOperand(0);
7260 LoadSDNode *LD = cast<LoadSDNode>(Load);
7261 // Create the byte-swapping load.
7263 LD->getChain(), // Chain
7264 LD->getBasePtr(), // Ptr
7265 DAG.getValueType(N->getValueType(0)) // VT
7268 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7269 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7270 MVT::i64 : MVT::i32, MVT::Other),
7271 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7273 // If this is an i16 load, insert the truncate.
7274 SDValue ResVal = BSLoad;
7275 if (N->getValueType(0) == MVT::i16)
7276 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7278 // First, combine the bswap away. This makes the value produced by the
7280 DCI.CombineTo(N, ResVal);
7282 // Next, combine the load away, we give it a bogus result value but a real
7283 // chain result. The result value is dead because the bswap is dead.
7284 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7286 // Return N so it doesn't get rechecked!
7287 return SDValue(N, 0);
7291 case PPCISD::VCMP: {
7292 // If a VCMPo node already exists with exactly the same operands as this
7293 // node, use its result instead of this node (VCMPo computes both a CR6 and
7294 // a normal output).
7296 if (!N->getOperand(0).hasOneUse() &&
7297 !N->getOperand(1).hasOneUse() &&
7298 !N->getOperand(2).hasOneUse()) {
7300 // Scan all of the users of the LHS, looking for VCMPo's that match.
7301 SDNode *VCMPoNode = 0;
7303 SDNode *LHSN = N->getOperand(0).getNode();
7304 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7306 if (UI->getOpcode() == PPCISD::VCMPo &&
7307 UI->getOperand(1) == N->getOperand(1) &&
7308 UI->getOperand(2) == N->getOperand(2) &&
7309 UI->getOperand(0) == N->getOperand(0)) {
7314 // If there is no VCMPo node, or if the flag value has a single use, don't
7316 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7319 // Look at the (necessarily single) use of the flag value. If it has a
7320 // chain, this transformation is more complex. Note that multiple things
7321 // could use the value result, which we should ignore.
7322 SDNode *FlagUser = 0;
7323 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7324 FlagUser == 0; ++UI) {
7325 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7327 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7328 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7335 // If the user is a MFOCRF instruction, we know this is safe.
7336 // Otherwise we give up for right now.
7337 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
7338 return SDValue(VCMPoNode, 0);
7343 // If this is a branch on an altivec predicate comparison, lower this so
7344 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
7345 // lowering is done pre-legalize, because the legalizer lowers the predicate
7346 // compare down to code that is difficult to reassemble.
7347 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7348 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7350 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
7351 // value. If so, pass-through the AND to get to the intrinsic.
7352 if (LHS.getOpcode() == ISD::AND &&
7353 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7354 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
7355 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7356 isa<ConstantSDNode>(LHS.getOperand(1)) &&
7357 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
7359 LHS = LHS.getOperand(0);
7361 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7362 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
7363 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7364 isa<ConstantSDNode>(RHS)) {
7365 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
7366 "Counter decrement comparison is not EQ or NE");
7368 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7369 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
7370 (CC == ISD::SETNE && !Val);
7372 // We now need to make the intrinsic dead (it cannot be instruction
7374 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
7375 assert(LHS.getNode()->hasOneUse() &&
7376 "Counter decrement has more than one use");
7378 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7379 N->getOperand(0), N->getOperand(4));
7385 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7386 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7387 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7388 assert(isDot && "Can't compare against a vector result!");
7390 // If this is a comparison against something other than 0/1, then we know
7391 // that the condition is never/always true.
7392 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7393 if (Val != 0 && Val != 1) {
7394 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7395 return N->getOperand(0);
7396 // Always !=, turn it into an unconditional branch.
7397 return DAG.getNode(ISD::BR, dl, MVT::Other,
7398 N->getOperand(0), N->getOperand(4));
7401 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7403 // Create the PPCISD altivec 'dot' comparison node.
7405 LHS.getOperand(2), // LHS of compare
7406 LHS.getOperand(3), // RHS of compare
7407 DAG.getConstant(CompareOpc, MVT::i32)
7409 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7410 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7412 // Unpack the result based on how the target uses it.
7413 PPC::Predicate CompOpc;
7414 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7415 default: // Can't happen, don't crash on invalid number though.
7416 case 0: // Branch on the value of the EQ bit of CR6.
7417 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7419 case 1: // Branch on the inverted value of the EQ bit of CR6.
7420 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7422 case 2: // Branch on the value of the LT bit of CR6.
7423 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7425 case 3: // Branch on the inverted value of the LT bit of CR6.
7426 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7430 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7431 DAG.getConstant(CompOpc, MVT::i32),
7432 DAG.getRegister(PPC::CR6, MVT::i32),
7433 N->getOperand(4), CompNode.getValue(1));
7442 //===----------------------------------------------------------------------===//
7443 // Inline Assembly Support
7444 //===----------------------------------------------------------------------===//
7446 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7449 const SelectionDAG &DAG,
7450 unsigned Depth) const {
7451 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7452 switch (Op.getOpcode()) {
7454 case PPCISD::LBRX: {
7455 // lhbrx is known to have the top bits cleared out.
7456 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7457 KnownZero = 0xFFFF0000;
7460 case ISD::INTRINSIC_WO_CHAIN: {
7461 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7463 case Intrinsic::ppc_altivec_vcmpbfp_p:
7464 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7465 case Intrinsic::ppc_altivec_vcmpequb_p:
7466 case Intrinsic::ppc_altivec_vcmpequh_p:
7467 case Intrinsic::ppc_altivec_vcmpequw_p:
7468 case Intrinsic::ppc_altivec_vcmpgefp_p:
7469 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7470 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7471 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7472 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7473 case Intrinsic::ppc_altivec_vcmpgtub_p:
7474 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7475 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7476 KnownZero = ~1U; // All bits but the low one are known to be zero.
7484 /// getConstraintType - Given a constraint, return the type of
7485 /// constraint it is for this target.
7486 PPCTargetLowering::ConstraintType
7487 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7488 if (Constraint.size() == 1) {
7489 switch (Constraint[0]) {
7496 return C_RegisterClass;
7498 // FIXME: While Z does indicate a memory constraint, it specifically
7499 // indicates an r+r address (used in conjunction with the 'y' modifier
7500 // in the replacement string). Currently, we're forcing the base
7501 // register to be r0 in the asm printer (which is interpreted as zero)
7502 // and forming the complete address in the second register. This is
7507 return TargetLowering::getConstraintType(Constraint);
7510 /// Examine constraint type and operand type and determine a weight value.
7511 /// This object must already have been set up with the operand type
7512 /// and the current alternative constraint selected.
7513 TargetLowering::ConstraintWeight
7514 PPCTargetLowering::getSingleConstraintMatchWeight(
7515 AsmOperandInfo &info, const char *constraint) const {
7516 ConstraintWeight weight = CW_Invalid;
7517 Value *CallOperandVal = info.CallOperandVal;
7518 // If we don't have a value, we can't do a match,
7519 // but allow it at the lowest weight.
7520 if (CallOperandVal == NULL)
7522 Type *type = CallOperandVal->getType();
7523 // Look at the constraint type.
7524 switch (*constraint) {
7526 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7529 if (type->isIntegerTy())
7530 weight = CW_Register;
7533 if (type->isFloatTy())
7534 weight = CW_Register;
7537 if (type->isDoubleTy())
7538 weight = CW_Register;
7541 if (type->isVectorTy())
7542 weight = CW_Register;
7545 weight = CW_Register;
7554 std::pair<unsigned, const TargetRegisterClass*>
7555 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7557 if (Constraint.size() == 1) {
7558 // GCC RS6000 Constraint Letters
7559 switch (Constraint[0]) {
7561 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7562 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7563 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7565 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7566 return std::make_pair(0U, &PPC::G8RCRegClass);
7567 return std::make_pair(0U, &PPC::GPRCRegClass);
7569 if (VT == MVT::f32 || VT == MVT::i32)
7570 return std::make_pair(0U, &PPC::F4RCRegClass);
7571 if (VT == MVT::f64 || VT == MVT::i64)
7572 return std::make_pair(0U, &PPC::F8RCRegClass);
7575 return std::make_pair(0U, &PPC::VRRCRegClass);
7577 return std::make_pair(0U, &PPC::CRRCRegClass);
7581 std::pair<unsigned, const TargetRegisterClass*> R =
7582 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7584 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
7585 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
7586 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
7588 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
7589 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
7590 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
7591 PPC::GPRCRegClass.contains(R.first)) {
7592 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
7593 return std::make_pair(TRI->getMatchingSuperReg(R.first,
7594 PPC::sub_32, &PPC::G8RCRegClass),
7595 &PPC::G8RCRegClass);
7602 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7603 /// vector. If it is invalid, don't add anything to Ops.
7604 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7605 std::string &Constraint,
7606 std::vector<SDValue>&Ops,
7607 SelectionDAG &DAG) const {
7608 SDValue Result(0,0);
7610 // Only support length 1 constraints.
7611 if (Constraint.length() > 1) return;
7613 char Letter = Constraint[0];
7624 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7625 if (!CST) return; // Must be an immediate to match.
7626 unsigned Value = CST->getZExtValue();
7628 default: llvm_unreachable("Unknown constraint letter!");
7629 case 'I': // "I" is a signed 16-bit constant.
7630 if ((short)Value == (int)Value)
7631 Result = DAG.getTargetConstant(Value, Op.getValueType());
7633 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7634 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7635 if ((short)Value == 0)
7636 Result = DAG.getTargetConstant(Value, Op.getValueType());
7638 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7639 if ((Value >> 16) == 0)
7640 Result = DAG.getTargetConstant(Value, Op.getValueType());
7642 case 'M': // "M" is a constant that is greater than 31.
7644 Result = DAG.getTargetConstant(Value, Op.getValueType());
7646 case 'N': // "N" is a positive constant that is an exact power of two.
7647 if ((int)Value > 0 && isPowerOf2_32(Value))
7648 Result = DAG.getTargetConstant(Value, Op.getValueType());
7650 case 'O': // "O" is the constant zero.
7652 Result = DAG.getTargetConstant(Value, Op.getValueType());
7654 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7655 if ((short)-Value == (int)-Value)
7656 Result = DAG.getTargetConstant(Value, Op.getValueType());
7663 if (Result.getNode()) {
7664 Ops.push_back(Result);
7668 // Handle standard constraint letters.
7669 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7672 // isLegalAddressingMode - Return true if the addressing mode represented
7673 // by AM is legal for this target, for a load/store of the specified type.
7674 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7676 // FIXME: PPC does not allow r+i addressing modes for vectors!
7678 // PPC allows a sign-extended 16-bit immediate field.
7679 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7682 // No global is ever allowed as a base.
7686 // PPC only support r+r,
7688 case 0: // "r+i" or just "i", depending on HasBaseReg.
7691 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7693 // Otherwise we have r+r or r+i.
7696 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7698 // Allow 2*r as r+r.
7701 // No other scales are supported.
7708 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7709 SelectionDAG &DAG) const {
7710 MachineFunction &MF = DAG.getMachineFunction();
7711 MachineFrameInfo *MFI = MF.getFrameInfo();
7712 MFI->setReturnAddressIsTaken(true);
7715 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7717 // Make sure the function does not optimize away the store of the RA to
7719 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7720 FuncInfo->setLRStoreRequired();
7721 bool isPPC64 = PPCSubTarget.isPPC64();
7722 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7725 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7728 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7729 isPPC64? MVT::i64 : MVT::i32);
7730 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7731 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7733 MachinePointerInfo(), false, false, false, 0);
7736 // Just load the return address off the stack.
7737 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7738 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7739 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7742 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7743 SelectionDAG &DAG) const {
7745 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7747 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7748 bool isPPC64 = PtrVT == MVT::i64;
7750 MachineFunction &MF = DAG.getMachineFunction();
7751 MachineFrameInfo *MFI = MF.getFrameInfo();
7752 MFI->setFrameAddressIsTaken(true);
7754 // Naked functions never have a frame pointer, and so we use r1. For all
7755 // other functions, this decision must be delayed until during PEI.
7757 if (MF.getFunction()->getAttributes().hasAttribute(
7758 AttributeSet::FunctionIndex, Attribute::Naked))
7759 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7761 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7763 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7766 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7767 FrameAddr, MachinePointerInfo(), false, false,
7773 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7774 // The PowerPC target isn't yet aware of offsets.
7778 /// getOptimalMemOpType - Returns the target specific optimal type for load
7779 /// and store operations as a result of memset, memcpy, and memmove
7780 /// lowering. If DstAlign is zero that means it's safe to destination
7781 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7782 /// means there isn't a need to check it against alignment requirement,
7783 /// probably because the source does not need to be loaded. If 'IsMemset' is
7784 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7785 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7786 /// source is constant so it does not need to be loaded.
7787 /// It returns EVT::Other if the type should be determined using generic
7788 /// target-independent logic.
7789 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7790 unsigned DstAlign, unsigned SrcAlign,
7791 bool IsMemset, bool ZeroMemset,
7793 MachineFunction &MF) const {
7794 if (this->PPCSubTarget.isPPC64()) {
7801 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7803 if (DisablePPCUnaligned)
7806 // PowerPC supports unaligned memory access for simple non-vector types.
7807 // Although accessing unaligned addresses is not as efficient as accessing
7808 // aligned addresses, it is generally more efficient than manual expansion,
7809 // and generally only traps for software emulation when crossing page
7815 if (VT.getSimpleVT().isVector())
7818 if (VT == MVT::ppcf128)
7827 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7828 VT = VT.getScalarType();
7833 switch (VT.getSimpleVT().SimpleTy) {
7844 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7846 return TargetLowering::getSchedulingPreference(N);
7851 // Create a fast isel object.
7853 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
7854 const TargetLibraryInfo *LibInfo) const {
7855 return PPC::createFastISel(FuncInfo, LibInfo);