1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPerfectShuffle.h"
17 #include "PPCTargetMachine.h"
18 #include "MCTargetDesc/PPCPredicates.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/DerivedTypes.h"
39 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
40 CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags,
43 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
54 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
55 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
58 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
59 if (TM.getSubtargetImpl()->isDarwin())
60 return new TargetLoweringObjectFileMachO();
62 return new TargetLoweringObjectFileELF();
65 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
66 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
70 // Use _setjmp/_longjmp instead of setjmp/longjmp.
71 setUseUnderscoreSetJmp(true);
72 setUseUnderscoreLongJmp(true);
74 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
75 // arguments are at least 4/8 bytes aligned.
76 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4);
78 // Set up the register classes.
79 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
80 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
81 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
83 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
85 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
87 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
89 // PowerPC has pre-inc load and store's.
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
101 // This is used in the ppcf128->int sequence. Note it has different semantics
102 // from FP_ROUND: that rounds to nearest, this rounds to zero.
103 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
105 // We do not currently implment this libm ops for PowerPC.
106 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
108 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
109 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
110 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
112 // PowerPC has no SREM/UREM instructions
113 setOperationAction(ISD::SREM, MVT::i32, Expand);
114 setOperationAction(ISD::UREM, MVT::i32, Expand);
115 setOperationAction(ISD::SREM, MVT::i64, Expand);
116 setOperationAction(ISD::UREM, MVT::i64, Expand);
118 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
119 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
120 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
121 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
122 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
123 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
124 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
125 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
126 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
128 // We don't support sin/cos/sqrt/fmod/pow
129 setOperationAction(ISD::FSIN , MVT::f64, Expand);
130 setOperationAction(ISD::FCOS , MVT::f64, Expand);
131 setOperationAction(ISD::FREM , MVT::f64, Expand);
132 setOperationAction(ISD::FPOW , MVT::f64, Expand);
133 setOperationAction(ISD::FMA , MVT::f64, Expand);
134 setOperationAction(ISD::FSIN , MVT::f32, Expand);
135 setOperationAction(ISD::FCOS , MVT::f32, Expand);
136 setOperationAction(ISD::FREM , MVT::f32, Expand);
137 setOperationAction(ISD::FPOW , MVT::f32, Expand);
138 setOperationAction(ISD::FMA , MVT::f32, Expand);
140 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
142 // If we're enabling GP optimizations, use hardware square root
143 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
144 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
145 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
148 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
149 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
151 // PowerPC does not have BSWAP, CTPOP or CTTZ
152 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
153 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
154 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
155 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
156 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
157 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
158 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
159 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
160 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
161 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
163 // PowerPC does not have ROTR
164 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
165 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
167 // PowerPC does not have Select
168 setOperationAction(ISD::SELECT, MVT::i32, Expand);
169 setOperationAction(ISD::SELECT, MVT::i64, Expand);
170 setOperationAction(ISD::SELECT, MVT::f32, Expand);
171 setOperationAction(ISD::SELECT, MVT::f64, Expand);
173 // PowerPC wants to turn select_cc of FP into fsel when possible.
174 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
175 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
177 // PowerPC wants to optimize integer setcc a bit
178 setOperationAction(ISD::SETCC, MVT::i32, Custom);
180 // PowerPC does not have BRCOND which requires SetCC
181 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
183 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
185 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
188 // PowerPC does not have [U|S]INT_TO_FP
189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
190 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
192 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
193 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
194 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
195 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
197 // We cannot sextinreg(i1). Expand to shifts.
198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
200 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
201 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
202 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
203 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
206 // We want to legalize GlobalAddress and ConstantPool nodes into the
207 // appropriate instructions to materialize the address.
208 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
209 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
210 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
211 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
212 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
213 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
214 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
215 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
216 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
217 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
220 setOperationAction(ISD::TRAP, MVT::Other, Legal);
222 // TRAMPOLINE is custom lowered.
223 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
224 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
226 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
227 setOperationAction(ISD::VASTART , MVT::Other, Custom);
229 // VAARG is custom lowered with the 32-bit SVR4 ABI.
230 if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
231 && !TM.getSubtarget<PPCSubtarget>().isPPC64()) {
232 setOperationAction(ISD::VAARG, MVT::Other, Custom);
233 setOperationAction(ISD::VAARG, MVT::i64, Custom);
235 setOperationAction(ISD::VAARG, MVT::Other, Expand);
237 // Use the default implementation.
238 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
239 setOperationAction(ISD::VAEND , MVT::Other, Expand);
240 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
241 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
242 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
243 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
245 // We want to custom lower some of our intrinsics.
246 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
248 // Comparisons that require checking two conditions.
249 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
250 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
251 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
252 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
253 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
254 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
255 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
256 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
257 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
258 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
259 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
260 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
262 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
263 // They also have instructions for converting between i64 and fp.
264 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
265 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
266 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
267 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
268 // This is just the low 32 bits of a (signed) fp->i64 conversion.
269 // We cannot do this with Promote because i64 is not a legal type.
270 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
272 // FIXME: disable this lowered code. This generates 64-bit register values,
273 // and we don't model the fact that the top part is clobbered by calls. We
274 // need to flag these together so that the value isn't live across a call.
275 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
277 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
278 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
281 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
282 // 64-bit PowerPC implementations can support i64 types directly
283 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
284 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
285 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
286 // 64-bit PowerPC wants to expand i128 shifts itself.
287 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
288 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
289 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
291 // 32-bit PowerPC wants to expand i64 shifts itself.
292 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
293 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
294 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
297 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
298 // First set operation action for all vector types to expand. Then we
299 // will selectively turn on ones that can be effectively codegen'd.
300 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
301 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
302 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
304 // add/sub are legal for all supported vector VT's.
305 setOperationAction(ISD::ADD , VT, Legal);
306 setOperationAction(ISD::SUB , VT, Legal);
308 // We promote all shuffles to v16i8.
309 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
310 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
312 // We promote all non-typed operations to v4i32.
313 setOperationAction(ISD::AND , VT, Promote);
314 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
315 setOperationAction(ISD::OR , VT, Promote);
316 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
317 setOperationAction(ISD::XOR , VT, Promote);
318 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
319 setOperationAction(ISD::LOAD , VT, Promote);
320 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
321 setOperationAction(ISD::SELECT, VT, Promote);
322 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
323 setOperationAction(ISD::STORE, VT, Promote);
324 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
326 // No other operations are legal.
327 setOperationAction(ISD::MUL , VT, Expand);
328 setOperationAction(ISD::SDIV, VT, Expand);
329 setOperationAction(ISD::SREM, VT, Expand);
330 setOperationAction(ISD::UDIV, VT, Expand);
331 setOperationAction(ISD::UREM, VT, Expand);
332 setOperationAction(ISD::FDIV, VT, Expand);
333 setOperationAction(ISD::FNEG, VT, Expand);
334 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
335 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
336 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
337 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
338 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
339 setOperationAction(ISD::UDIVREM, VT, Expand);
340 setOperationAction(ISD::SDIVREM, VT, Expand);
341 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
342 setOperationAction(ISD::FPOW, VT, Expand);
343 setOperationAction(ISD::CTPOP, VT, Expand);
344 setOperationAction(ISD::CTLZ, VT, Expand);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
346 setOperationAction(ISD::CTTZ, VT, Expand);
347 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
350 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
351 // with merges, splats, etc.
352 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
354 setOperationAction(ISD::AND , MVT::v4i32, Legal);
355 setOperationAction(ISD::OR , MVT::v4i32, Legal);
356 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
357 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
358 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
359 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
361 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
362 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
363 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
364 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
366 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
367 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
368 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
369 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
371 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
372 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
374 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
375 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
376 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
377 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
380 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
381 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
383 setBooleanContents(ZeroOrOneBooleanContent);
384 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
386 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
387 setStackPointerRegisterToSaveRestore(PPC::X1);
388 setExceptionPointerRegister(PPC::X3);
389 setExceptionSelectorRegister(PPC::X4);
391 setStackPointerRegisterToSaveRestore(PPC::R1);
392 setExceptionPointerRegister(PPC::R3);
393 setExceptionSelectorRegister(PPC::R4);
396 // We have target-specific dag combine patterns for the following nodes:
397 setTargetDAGCombine(ISD::SINT_TO_FP);
398 setTargetDAGCombine(ISD::STORE);
399 setTargetDAGCombine(ISD::BR_CC);
400 setTargetDAGCombine(ISD::BSWAP);
402 // Darwin long double math library functions have $LDBL128 appended.
403 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
404 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
405 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
406 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
407 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
408 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
409 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
410 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
411 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
412 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
413 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
416 setMinFunctionAlignment(2);
417 if (PPCSubTarget.isDarwin())
418 setPrefFunctionAlignment(4);
420 setInsertFencesForAtomic(true);
422 setSchedulingPreference(Sched::Hybrid);
424 computeRegisterProperties();
427 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
428 /// function arguments in the caller parameter area.
429 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
430 const TargetMachine &TM = getTargetMachine();
431 // Darwin passes everything on 4 byte boundary.
432 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
438 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
441 case PPCISD::FSEL: return "PPCISD::FSEL";
442 case PPCISD::FCFID: return "PPCISD::FCFID";
443 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
444 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
445 case PPCISD::STFIWX: return "PPCISD::STFIWX";
446 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
447 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
448 case PPCISD::VPERM: return "PPCISD::VPERM";
449 case PPCISD::Hi: return "PPCISD::Hi";
450 case PPCISD::Lo: return "PPCISD::Lo";
451 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
452 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
453 case PPCISD::LOAD: return "PPCISD::LOAD";
454 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
455 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
456 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
457 case PPCISD::SRL: return "PPCISD::SRL";
458 case PPCISD::SRA: return "PPCISD::SRA";
459 case PPCISD::SHL: return "PPCISD::SHL";
460 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
461 case PPCISD::STD_32: return "PPCISD::STD_32";
462 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
463 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
464 case PPCISD::NOP: return "PPCISD::NOP";
465 case PPCISD::MTCTR: return "PPCISD::MTCTR";
466 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
467 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
468 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
469 case PPCISD::MFCR: return "PPCISD::MFCR";
470 case PPCISD::VCMP: return "PPCISD::VCMP";
471 case PPCISD::VCMPo: return "PPCISD::VCMPo";
472 case PPCISD::LBRX: return "PPCISD::LBRX";
473 case PPCISD::STBRX: return "PPCISD::STBRX";
474 case PPCISD::LARX: return "PPCISD::LARX";
475 case PPCISD::STCX: return "PPCISD::STCX";
476 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
477 case PPCISD::MFFS: return "PPCISD::MFFS";
478 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
479 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
480 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
481 case PPCISD::MTFSF: return "PPCISD::MTFSF";
482 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
486 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
490 //===----------------------------------------------------------------------===//
491 // Node matching predicates, for use by the tblgen matching code.
492 //===----------------------------------------------------------------------===//
494 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
495 static bool isFloatingPointZero(SDValue Op) {
496 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
497 return CFP->getValueAPF().isZero();
498 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
499 // Maybe this has already been legalized into the constant pool?
500 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
501 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
502 return CFP->getValueAPF().isZero();
507 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
508 /// true if Op is undef or if it matches the specified value.
509 static bool isConstantOrUndef(int Op, int Val) {
510 return Op < 0 || Op == Val;
513 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
514 /// VPKUHUM instruction.
515 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
517 for (unsigned i = 0; i != 16; ++i)
518 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
521 for (unsigned i = 0; i != 8; ++i)
522 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
523 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
529 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
530 /// VPKUWUM instruction.
531 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
533 for (unsigned i = 0; i != 16; i += 2)
534 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
535 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
538 for (unsigned i = 0; i != 8; i += 2)
539 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
540 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
541 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
542 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
548 /// isVMerge - Common function, used to match vmrg* shuffles.
550 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
551 unsigned LHSStart, unsigned RHSStart) {
552 assert(N->getValueType(0) == MVT::v16i8 &&
553 "PPC only supports shuffles by bytes!");
554 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
555 "Unsupported merge size!");
557 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
558 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
559 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
560 LHSStart+j+i*UnitSize) ||
561 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
562 RHSStart+j+i*UnitSize))
568 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
569 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
570 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
573 return isVMerge(N, UnitSize, 8, 24);
574 return isVMerge(N, UnitSize, 8, 8);
577 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
578 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
579 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
582 return isVMerge(N, UnitSize, 0, 16);
583 return isVMerge(N, UnitSize, 0, 0);
587 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
588 /// amount, otherwise return -1.
589 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
590 assert(N->getValueType(0) == MVT::v16i8 &&
591 "PPC only supports shuffles by bytes!");
593 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
595 // Find the first non-undef value in the shuffle mask.
597 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
600 if (i == 16) return -1; // all undef.
602 // Otherwise, check to see if the rest of the elements are consecutively
603 // numbered from this value.
604 unsigned ShiftAmt = SVOp->getMaskElt(i);
605 if (ShiftAmt < i) return -1;
609 // Check the rest of the elements to see if they are consecutive.
610 for (++i; i != 16; ++i)
611 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
614 // Check the rest of the elements to see if they are consecutive.
615 for (++i; i != 16; ++i)
616 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
622 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
623 /// specifies a splat of a single element that is suitable for input to
624 /// VSPLTB/VSPLTH/VSPLTW.
625 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
626 assert(N->getValueType(0) == MVT::v16i8 &&
627 (EltSize == 1 || EltSize == 2 || EltSize == 4));
629 // This is a splat operation if each element of the permute is the same, and
630 // if the value doesn't reference the second vector.
631 unsigned ElementBase = N->getMaskElt(0);
633 // FIXME: Handle UNDEF elements too!
634 if (ElementBase >= 16)
637 // Check that the indices are consecutive, in the case of a multi-byte element
638 // splatted with a v16i8 mask.
639 for (unsigned i = 1; i != EltSize; ++i)
640 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
643 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
644 if (N->getMaskElt(i) < 0) continue;
645 for (unsigned j = 0; j != EltSize; ++j)
646 if (N->getMaskElt(i+j) != N->getMaskElt(j))
652 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
654 bool PPC::isAllNegativeZeroVector(SDNode *N) {
655 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
657 APInt APVal, APUndef;
661 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
662 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
663 return CFP->getValueAPF().isNegZero();
668 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
669 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
670 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
671 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
672 assert(isSplatShuffleMask(SVOp, EltSize));
673 return SVOp->getMaskElt(0) / EltSize;
676 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
677 /// by using a vspltis[bhw] instruction of the specified element size, return
678 /// the constant being splatted. The ByteSize field indicates the number of
679 /// bytes of each element [124] -> [bhw].
680 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
683 // If ByteSize of the splat is bigger than the element size of the
684 // build_vector, then we have a case where we are checking for a splat where
685 // multiple elements of the buildvector are folded together into a single
686 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
687 unsigned EltSize = 16/N->getNumOperands();
688 if (EltSize < ByteSize) {
689 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
690 SDValue UniquedVals[4];
691 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
693 // See if all of the elements in the buildvector agree across.
694 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
695 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
696 // If the element isn't a constant, bail fully out.
697 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
700 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
701 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
702 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
703 return SDValue(); // no match.
706 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
707 // either constant or undef values that are identical for each chunk. See
708 // if these chunks can form into a larger vspltis*.
710 // Check to see if all of the leading entries are either 0 or -1. If
711 // neither, then this won't fit into the immediate field.
712 bool LeadingZero = true;
713 bool LeadingOnes = true;
714 for (unsigned i = 0; i != Multiple-1; ++i) {
715 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
717 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
718 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
720 // Finally, check the least significant entry.
722 if (UniquedVals[Multiple-1].getNode() == 0)
723 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
724 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
726 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
729 if (UniquedVals[Multiple-1].getNode() == 0)
730 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
731 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
732 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
733 return DAG.getTargetConstant(Val, MVT::i32);
739 // Check to see if this buildvec has a single non-undef value in its elements.
740 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
741 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
742 if (OpVal.getNode() == 0)
743 OpVal = N->getOperand(i);
744 else if (OpVal != N->getOperand(i))
748 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
750 unsigned ValSizeInBytes = EltSize;
752 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
753 Value = CN->getZExtValue();
754 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
755 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
756 Value = FloatToBits(CN->getValueAPF().convertToFloat());
759 // If the splat value is larger than the element value, then we can never do
760 // this splat. The only case that we could fit the replicated bits into our
761 // immediate field for would be zero, and we prefer to use vxor for it.
762 if (ValSizeInBytes < ByteSize) return SDValue();
764 // If the element value is larger than the splat value, cut it in half and
765 // check to see if the two halves are equal. Continue doing this until we
766 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
767 while (ValSizeInBytes > ByteSize) {
768 ValSizeInBytes >>= 1;
770 // If the top half equals the bottom half, we're still ok.
771 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
772 (Value & ((1 << (8*ValSizeInBytes))-1)))
776 // Properly sign extend the value.
777 int ShAmt = (4-ByteSize)*8;
778 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
780 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
781 if (MaskVal == 0) return SDValue();
783 // Finally, if this value fits in a 5 bit sext field, return it
784 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
785 return DAG.getTargetConstant(MaskVal, MVT::i32);
789 //===----------------------------------------------------------------------===//
790 // Addressing Mode Selection
791 //===----------------------------------------------------------------------===//
793 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
794 /// or 64-bit immediate, and if the value can be accurately represented as a
795 /// sign extension from a 16-bit value. If so, this returns true and the
797 static bool isIntS16Immediate(SDNode *N, short &Imm) {
798 if (N->getOpcode() != ISD::Constant)
801 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
802 if (N->getValueType(0) == MVT::i32)
803 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
805 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
807 static bool isIntS16Immediate(SDValue Op, short &Imm) {
808 return isIntS16Immediate(Op.getNode(), Imm);
812 /// SelectAddressRegReg - Given the specified addressed, check to see if it
813 /// can be represented as an indexed [r+r] operation. Returns false if it
814 /// can be more efficiently represented with [r+imm].
815 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
817 SelectionDAG &DAG) const {
819 if (N.getOpcode() == ISD::ADD) {
820 if (isIntS16Immediate(N.getOperand(1), imm))
822 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
825 Base = N.getOperand(0);
826 Index = N.getOperand(1);
828 } else if (N.getOpcode() == ISD::OR) {
829 if (isIntS16Immediate(N.getOperand(1), imm))
830 return false; // r+i can fold it if we can.
832 // If this is an or of disjoint bitfields, we can codegen this as an add
833 // (for better address arithmetic) if the LHS and RHS of the OR are provably
835 APInt LHSKnownZero, LHSKnownOne;
836 APInt RHSKnownZero, RHSKnownOne;
837 DAG.ComputeMaskedBits(N.getOperand(0),
838 APInt::getAllOnesValue(N.getOperand(0)
839 .getValueSizeInBits()),
840 LHSKnownZero, LHSKnownOne);
842 if (LHSKnownZero.getBoolValue()) {
843 DAG.ComputeMaskedBits(N.getOperand(1),
844 APInt::getAllOnesValue(N.getOperand(1)
845 .getValueSizeInBits()),
846 RHSKnownZero, RHSKnownOne);
847 // If all of the bits are known zero on the LHS or RHS, the add won't
849 if (~(LHSKnownZero | RHSKnownZero) == 0) {
850 Base = N.getOperand(0);
851 Index = N.getOperand(1);
860 /// Returns true if the address N can be represented by a base register plus
861 /// a signed 16-bit displacement [r+imm], and if it is not better
862 /// represented as reg+reg.
863 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
865 SelectionDAG &DAG) const {
866 // FIXME dl should come from parent load or store, not from address
867 DebugLoc dl = N.getDebugLoc();
868 // If this can be more profitably realized as r+r, fail.
869 if (SelectAddressRegReg(N, Disp, Base, DAG))
872 if (N.getOpcode() == ISD::ADD) {
874 if (isIntS16Immediate(N.getOperand(1), imm)) {
875 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
876 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
877 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
879 Base = N.getOperand(0);
881 return true; // [r+i]
882 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
883 // Match LOAD (ADD (X, Lo(G))).
884 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
885 && "Cannot handle constant offsets yet!");
886 Disp = N.getOperand(1).getOperand(0); // The global address.
887 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
888 Disp.getOpcode() == ISD::TargetConstantPool ||
889 Disp.getOpcode() == ISD::TargetJumpTable);
890 Base = N.getOperand(0);
891 return true; // [&g+r]
893 } else if (N.getOpcode() == ISD::OR) {
895 if (isIntS16Immediate(N.getOperand(1), imm)) {
896 // If this is an or of disjoint bitfields, we can codegen this as an add
897 // (for better address arithmetic) if the LHS and RHS of the OR are
898 // provably disjoint.
899 APInt LHSKnownZero, LHSKnownOne;
900 DAG.ComputeMaskedBits(N.getOperand(0),
901 APInt::getAllOnesValue(N.getOperand(0)
902 .getValueSizeInBits()),
903 LHSKnownZero, LHSKnownOne);
905 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
906 // If all of the bits are known zero on the LHS or RHS, the add won't
908 Base = N.getOperand(0);
909 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
913 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
914 // Loading from a constant address.
916 // If this address fits entirely in a 16-bit sext immediate field, codegen
919 if (isIntS16Immediate(CN, Imm)) {
920 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
921 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
922 CN->getValueType(0));
926 // Handle 32-bit sext immediates with LIS + addr mode.
927 if (CN->getValueType(0) == MVT::i32 ||
928 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
929 int Addr = (int)CN->getZExtValue();
931 // Otherwise, break this down into an LIS + disp.
932 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
934 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
935 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
936 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
941 Disp = DAG.getTargetConstant(0, getPointerTy());
942 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
943 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
946 return true; // [r+0]
949 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
950 /// represented as an indexed [r+r] operation.
951 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
953 SelectionDAG &DAG) const {
954 // Check to see if we can easily represent this as an [r+r] address. This
955 // will fail if it thinks that the address is more profitably represented as
956 // reg+imm, e.g. where imm = 0.
957 if (SelectAddressRegReg(N, Base, Index, DAG))
960 // If the operand is an addition, always emit this as [r+r], since this is
961 // better (for code size, and execution, as the memop does the add for free)
962 // than emitting an explicit add.
963 if (N.getOpcode() == ISD::ADD) {
964 Base = N.getOperand(0);
965 Index = N.getOperand(1);
969 // Otherwise, do it the hard way, using R0 as the base register.
970 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
976 /// SelectAddressRegImmShift - Returns true if the address N can be
977 /// represented by a base register plus a signed 14-bit displacement
978 /// [r+imm*4]. Suitable for use by STD and friends.
979 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
981 SelectionDAG &DAG) const {
982 // FIXME dl should come from the parent load or store, not the address
983 DebugLoc dl = N.getDebugLoc();
984 // If this can be more profitably realized as r+r, fail.
985 if (SelectAddressRegReg(N, Disp, Base, DAG))
988 if (N.getOpcode() == ISD::ADD) {
990 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
991 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
992 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
993 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
995 Base = N.getOperand(0);
997 return true; // [r+i]
998 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
999 // Match LOAD (ADD (X, Lo(G))).
1000 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1001 && "Cannot handle constant offsets yet!");
1002 Disp = N.getOperand(1).getOperand(0); // The global address.
1003 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1004 Disp.getOpcode() == ISD::TargetConstantPool ||
1005 Disp.getOpcode() == ISD::TargetJumpTable);
1006 Base = N.getOperand(0);
1007 return true; // [&g+r]
1009 } else if (N.getOpcode() == ISD::OR) {
1011 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1012 // If this is an or of disjoint bitfields, we can codegen this as an add
1013 // (for better address arithmetic) if the LHS and RHS of the OR are
1014 // provably disjoint.
1015 APInt LHSKnownZero, LHSKnownOne;
1016 DAG.ComputeMaskedBits(N.getOperand(0),
1017 APInt::getAllOnesValue(N.getOperand(0)
1018 .getValueSizeInBits()),
1019 LHSKnownZero, LHSKnownOne);
1020 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1021 // If all of the bits are known zero on the LHS or RHS, the add won't
1023 Base = N.getOperand(0);
1024 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1028 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1029 // Loading from a constant address. Verify low two bits are clear.
1030 if ((CN->getZExtValue() & 3) == 0) {
1031 // If this address fits entirely in a 14-bit sext immediate field, codegen
1034 if (isIntS16Immediate(CN, Imm)) {
1035 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1036 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1037 CN->getValueType(0));
1041 // Fold the low-part of 32-bit absolute addresses into addr mode.
1042 if (CN->getValueType(0) == MVT::i32 ||
1043 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1044 int Addr = (int)CN->getZExtValue();
1046 // Otherwise, break this down into an LIS + disp.
1047 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1048 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1049 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1050 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1056 Disp = DAG.getTargetConstant(0, getPointerTy());
1057 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1058 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1061 return true; // [r+0]
1065 /// getPreIndexedAddressParts - returns true by value, base pointer and
1066 /// offset pointer and addressing mode by reference if the node's address
1067 /// can be legally represented as pre-indexed load / store address.
1068 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1070 ISD::MemIndexedMode &AM,
1071 SelectionDAG &DAG) const {
1072 // Disabled by default for now.
1073 if (!EnablePPCPreinc) return false;
1077 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1078 Ptr = LD->getBasePtr();
1079 VT = LD->getMemoryVT();
1081 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1082 Ptr = ST->getBasePtr();
1083 VT = ST->getMemoryVT();
1087 // PowerPC doesn't have preinc load/store instructions for vectors.
1091 // TODO: Check reg+reg first.
1093 // LDU/STU use reg+imm*4, others use reg+imm.
1094 if (VT != MVT::i64) {
1096 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1100 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1104 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1105 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1106 // sext i32 to i64 when addr mode is r+i.
1107 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1108 LD->getExtensionType() == ISD::SEXTLOAD &&
1109 isa<ConstantSDNode>(Offset))
1117 //===----------------------------------------------------------------------===//
1118 // LowerOperation implementation
1119 //===----------------------------------------------------------------------===//
1121 /// GetLabelAccessInfo - Return true if we should reference labels using a
1122 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1123 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1124 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1125 HiOpFlags = PPCII::MO_HA16;
1126 LoOpFlags = PPCII::MO_LO16;
1128 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1129 // non-darwin platform. We don't support PIC on other platforms yet.
1130 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1131 TM.getSubtarget<PPCSubtarget>().isDarwin();
1133 HiOpFlags |= PPCII::MO_PIC_FLAG;
1134 LoOpFlags |= PPCII::MO_PIC_FLAG;
1137 // If this is a reference to a global value that requires a non-lazy-ptr, make
1138 // sure that instruction lowering adds it.
1139 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1140 HiOpFlags |= PPCII::MO_NLP_FLAG;
1141 LoOpFlags |= PPCII::MO_NLP_FLAG;
1143 if (GV->hasHiddenVisibility()) {
1144 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1145 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1152 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1153 SelectionDAG &DAG) {
1154 EVT PtrVT = HiPart.getValueType();
1155 SDValue Zero = DAG.getConstant(0, PtrVT);
1156 DebugLoc DL = HiPart.getDebugLoc();
1158 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1159 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1161 // With PIC, the first instruction is actually "GR+hi(&G)".
1163 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1164 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1166 // Generate non-pic code that has direct accesses to the constant pool.
1167 // The address of the global is just (hi(&g)+lo(&g)).
1168 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1171 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1172 SelectionDAG &DAG) const {
1173 EVT PtrVT = Op.getValueType();
1174 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1175 const Constant *C = CP->getConstVal();
1177 unsigned MOHiFlag, MOLoFlag;
1178 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1180 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1182 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1183 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1186 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1187 EVT PtrVT = Op.getValueType();
1188 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1190 unsigned MOHiFlag, MOLoFlag;
1191 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1192 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1193 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1194 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1197 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1198 SelectionDAG &DAG) const {
1199 EVT PtrVT = Op.getValueType();
1201 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1203 unsigned MOHiFlag, MOLoFlag;
1204 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1205 SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag);
1206 SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag);
1207 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1210 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1211 SelectionDAG &DAG) const {
1212 EVT PtrVT = Op.getValueType();
1213 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1214 DebugLoc DL = GSDN->getDebugLoc();
1215 const GlobalValue *GV = GSDN->getGlobal();
1217 // 64-bit SVR4 ABI code is always position-independent.
1218 // The actual address of the GlobalValue is stored in the TOC.
1219 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1220 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1221 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1222 DAG.getRegister(PPC::X2, MVT::i64));
1225 unsigned MOHiFlag, MOLoFlag;
1226 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1229 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1231 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1233 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1235 // If the global reference is actually to a non-lazy-pointer, we have to do an
1236 // extra load to get the address of the global.
1237 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1238 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1239 false, false, false, 0);
1243 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1244 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1245 DebugLoc dl = Op.getDebugLoc();
1247 // If we're comparing for equality to zero, expose the fact that this is
1248 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1249 // fold the new nodes.
1250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1251 if (C->isNullValue() && CC == ISD::SETEQ) {
1252 EVT VT = Op.getOperand(0).getValueType();
1253 SDValue Zext = Op.getOperand(0);
1254 if (VT.bitsLT(MVT::i32)) {
1256 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1258 unsigned Log2b = Log2_32(VT.getSizeInBits());
1259 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1260 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1261 DAG.getConstant(Log2b, MVT::i32));
1262 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1264 // Leave comparisons against 0 and -1 alone for now, since they're usually
1265 // optimized. FIXME: revisit this when we can custom lower all setcc
1267 if (C->isAllOnesValue() || C->isNullValue())
1271 // If we have an integer seteq/setne, turn it into a compare against zero
1272 // by xor'ing the rhs with the lhs, which is faster than setting a
1273 // condition register, reading it back out, and masking the correct bit. The
1274 // normal approach here uses sub to do this instead of xor. Using xor exposes
1275 // the result to other bit-twiddling opportunities.
1276 EVT LHSVT = Op.getOperand(0).getValueType();
1277 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1278 EVT VT = Op.getValueType();
1279 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1281 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1286 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1287 const PPCSubtarget &Subtarget) const {
1288 SDNode *Node = Op.getNode();
1289 EVT VT = Node->getValueType(0);
1290 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1291 SDValue InChain = Node->getOperand(0);
1292 SDValue VAListPtr = Node->getOperand(1);
1293 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1294 DebugLoc dl = Node->getDebugLoc();
1296 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1299 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1300 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1302 InChain = GprIndex.getValue(1);
1304 if (VT == MVT::i64) {
1305 // Check if GprIndex is even
1306 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1307 DAG.getConstant(1, MVT::i32));
1308 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1309 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1310 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1311 DAG.getConstant(1, MVT::i32));
1312 // Align GprIndex to be even if it isn't
1313 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1317 // fpr index is 1 byte after gpr
1318 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1319 DAG.getConstant(1, MVT::i32));
1322 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1323 FprPtr, MachinePointerInfo(SV), MVT::i8,
1325 InChain = FprIndex.getValue(1);
1327 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1328 DAG.getConstant(8, MVT::i32));
1330 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1331 DAG.getConstant(4, MVT::i32));
1334 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1335 MachinePointerInfo(), false, false,
1337 InChain = OverflowArea.getValue(1);
1339 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1340 MachinePointerInfo(), false, false,
1342 InChain = RegSaveArea.getValue(1);
1344 // select overflow_area if index > 8
1345 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1346 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1348 // adjustment constant gpr_index * 4/8
1349 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1350 VT.isInteger() ? GprIndex : FprIndex,
1351 DAG.getConstant(VT.isInteger() ? 4 : 8,
1354 // OurReg = RegSaveArea + RegConstant
1355 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1358 // Floating types are 32 bytes into RegSaveArea
1359 if (VT.isFloatingPoint())
1360 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1361 DAG.getConstant(32, MVT::i32));
1363 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1364 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1365 VT.isInteger() ? GprIndex : FprIndex,
1366 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1369 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1370 VT.isInteger() ? VAListPtr : FprPtr,
1371 MachinePointerInfo(SV),
1372 MVT::i8, false, false, 0);
1374 // determine if we should load from reg_save_area or overflow_area
1375 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1377 // increase overflow_area by 4/8 if gpr/fpr > 8
1378 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1379 DAG.getConstant(VT.isInteger() ? 4 : 8,
1382 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1385 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1387 MachinePointerInfo(),
1388 MVT::i32, false, false, 0);
1390 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1391 false, false, false, 0);
1394 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1395 SelectionDAG &DAG) const {
1396 return Op.getOperand(0);
1399 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1400 SelectionDAG &DAG) const {
1401 SDValue Chain = Op.getOperand(0);
1402 SDValue Trmp = Op.getOperand(1); // trampoline
1403 SDValue FPtr = Op.getOperand(2); // nested function
1404 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1405 DebugLoc dl = Op.getDebugLoc();
1407 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1408 bool isPPC64 = (PtrVT == MVT::i64);
1410 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1413 TargetLowering::ArgListTy Args;
1414 TargetLowering::ArgListEntry Entry;
1416 Entry.Ty = IntPtrTy;
1417 Entry.Node = Trmp; Args.push_back(Entry);
1419 // TrampSize == (isPPC64 ? 48 : 40);
1420 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1421 isPPC64 ? MVT::i64 : MVT::i32);
1422 Args.push_back(Entry);
1424 Entry.Node = FPtr; Args.push_back(Entry);
1425 Entry.Node = Nest; Args.push_back(Entry);
1427 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1428 std::pair<SDValue, SDValue> CallResult =
1429 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
1430 false, false, false, false, 0, CallingConv::C, false,
1431 /*isReturnValueUsed=*/true,
1432 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1435 return CallResult.second;
1438 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1439 const PPCSubtarget &Subtarget) const {
1440 MachineFunction &MF = DAG.getMachineFunction();
1441 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1443 DebugLoc dl = Op.getDebugLoc();
1445 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1446 // vastart just stores the address of the VarArgsFrameIndex slot into the
1447 // memory location argument.
1448 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1449 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1450 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1451 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1452 MachinePointerInfo(SV),
1456 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1457 // We suppose the given va_list is already allocated.
1460 // char gpr; /* index into the array of 8 GPRs
1461 // * stored in the register save area
1462 // * gpr=0 corresponds to r3,
1463 // * gpr=1 to r4, etc.
1465 // char fpr; /* index into the array of 8 FPRs
1466 // * stored in the register save area
1467 // * fpr=0 corresponds to f1,
1468 // * fpr=1 to f2, etc.
1470 // char *overflow_arg_area;
1471 // /* location on stack that holds
1472 // * the next overflow argument
1474 // char *reg_save_area;
1475 // /* where r3:r10 and f1:f8 (if saved)
1481 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1482 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1485 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1487 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1489 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1492 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1493 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1495 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1496 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1498 uint64_t FPROffset = 1;
1499 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1501 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1503 // Store first byte : number of int regs
1504 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1506 MachinePointerInfo(SV),
1507 MVT::i8, false, false, 0);
1508 uint64_t nextOffset = FPROffset;
1509 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1512 // Store second byte : number of float regs
1513 SDValue secondStore =
1514 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1515 MachinePointerInfo(SV, nextOffset), MVT::i8,
1517 nextOffset += StackOffset;
1518 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1520 // Store second word : arguments given on stack
1521 SDValue thirdStore =
1522 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1523 MachinePointerInfo(SV, nextOffset),
1525 nextOffset += FrameOffset;
1526 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1528 // Store third word : arguments given in registers
1529 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1530 MachinePointerInfo(SV, nextOffset),
1535 #include "PPCGenCallingConv.inc"
1537 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1538 CCValAssign::LocInfo &LocInfo,
1539 ISD::ArgFlagsTy &ArgFlags,
1544 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1546 CCValAssign::LocInfo &LocInfo,
1547 ISD::ArgFlagsTy &ArgFlags,
1549 static const unsigned ArgRegs[] = {
1550 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1551 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1553 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1555 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1557 // Skip one register if the first unallocated register has an even register
1558 // number and there are still argument registers available which have not been
1559 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1560 // need to skip a register if RegNum is odd.
1561 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1562 State.AllocateReg(ArgRegs[RegNum]);
1565 // Always return false here, as this function only makes sure that the first
1566 // unallocated register has an odd register number and does not actually
1567 // allocate a register for the current argument.
1571 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1573 CCValAssign::LocInfo &LocInfo,
1574 ISD::ArgFlagsTy &ArgFlags,
1576 static const unsigned ArgRegs[] = {
1577 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1581 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1583 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1585 // If there is only one Floating-point register left we need to put both f64
1586 // values of a split ppc_fp128 value on the stack.
1587 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1588 State.AllocateReg(ArgRegs[RegNum]);
1591 // Always return false here, as this function only makes sure that the two f64
1592 // values a ppc_fp128 value is split into are both passed in registers or both
1593 // passed on the stack and does not actually allocate a register for the
1594 // current argument.
1598 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1600 static const unsigned *GetFPR() {
1601 static const unsigned FPR[] = {
1602 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1603 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1609 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1611 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1612 unsigned PtrByteSize) {
1613 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1614 if (Flags.isByVal())
1615 ArgSize = Flags.getByValSize();
1616 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1622 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1623 CallingConv::ID CallConv, bool isVarArg,
1624 const SmallVectorImpl<ISD::InputArg>
1626 DebugLoc dl, SelectionDAG &DAG,
1627 SmallVectorImpl<SDValue> &InVals)
1629 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1630 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1633 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1639 PPCTargetLowering::LowerFormalArguments_SVR4(
1641 CallingConv::ID CallConv, bool isVarArg,
1642 const SmallVectorImpl<ISD::InputArg>
1644 DebugLoc dl, SelectionDAG &DAG,
1645 SmallVectorImpl<SDValue> &InVals) const {
1647 // 32-bit SVR4 ABI Stack Frame Layout:
1648 // +-----------------------------------+
1649 // +--> | Back chain |
1650 // | +-----------------------------------+
1651 // | | Floating-point register save area |
1652 // | +-----------------------------------+
1653 // | | General register save area |
1654 // | +-----------------------------------+
1655 // | | CR save word |
1656 // | +-----------------------------------+
1657 // | | VRSAVE save word |
1658 // | +-----------------------------------+
1659 // | | Alignment padding |
1660 // | +-----------------------------------+
1661 // | | Vector register save area |
1662 // | +-----------------------------------+
1663 // | | Local variable space |
1664 // | +-----------------------------------+
1665 // | | Parameter list area |
1666 // | +-----------------------------------+
1667 // | | LR save word |
1668 // | +-----------------------------------+
1669 // SP--> +--- | Back chain |
1670 // +-----------------------------------+
1673 // System V Application Binary Interface PowerPC Processor Supplement
1674 // AltiVec Technology Programming Interface Manual
1676 MachineFunction &MF = DAG.getMachineFunction();
1677 MachineFrameInfo *MFI = MF.getFrameInfo();
1678 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1680 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1681 // Potential tail calls could cause overwriting of argument stack slots.
1682 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1683 (CallConv == CallingConv::Fast));
1684 unsigned PtrByteSize = 4;
1686 // Assign locations to all of the incoming arguments.
1687 SmallVector<CCValAssign, 16> ArgLocs;
1688 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1689 getTargetMachine(), ArgLocs, *DAG.getContext());
1691 // Reserve space for the linkage area on the stack.
1692 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1694 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1696 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1697 CCValAssign &VA = ArgLocs[i];
1699 // Arguments stored in registers.
1700 if (VA.isRegLoc()) {
1701 TargetRegisterClass *RC;
1702 EVT ValVT = VA.getValVT();
1704 switch (ValVT.getSimpleVT().SimpleTy) {
1706 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1708 RC = PPC::GPRCRegisterClass;
1711 RC = PPC::F4RCRegisterClass;
1714 RC = PPC::F8RCRegisterClass;
1720 RC = PPC::VRRCRegisterClass;
1724 // Transform the arguments stored in physical registers into virtual ones.
1725 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1726 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1728 InVals.push_back(ArgValue);
1730 // Argument stored in memory.
1731 assert(VA.isMemLoc());
1733 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1734 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1737 // Create load nodes to retrieve arguments from the stack.
1738 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1739 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1740 MachinePointerInfo(),
1741 false, false, false, 0));
1745 // Assign locations to all of the incoming aggregate by value arguments.
1746 // Aggregates passed by value are stored in the local variable space of the
1747 // caller's stack frame, right above the parameter list area.
1748 SmallVector<CCValAssign, 16> ByValArgLocs;
1749 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1750 getTargetMachine(), ByValArgLocs, *DAG.getContext());
1752 // Reserve stack space for the allocations in CCInfo.
1753 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1755 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1757 // Area that is at least reserved in the caller of this function.
1758 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1760 // Set the size that is at least reserved in caller of this function. Tail
1761 // call optimized function's reserved stack space needs to be aligned so that
1762 // taking the difference between two stack areas will result in an aligned
1764 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1767 std::max(MinReservedArea,
1768 PPCFrameLowering::getMinCallFrameSize(false, false));
1770 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
1771 getStackAlignment();
1772 unsigned AlignMask = TargetAlign-1;
1773 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1775 FI->setMinReservedArea(MinReservedArea);
1777 SmallVector<SDValue, 8> MemOps;
1779 // If the function takes variable number of arguments, make a frame index for
1780 // the start of the first vararg value... for expansion of llvm.va_start.
1782 static const unsigned GPArgRegs[] = {
1783 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1784 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1786 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1788 static const unsigned FPArgRegs[] = {
1789 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1792 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1794 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
1796 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
1799 // Make room for NumGPArgRegs and NumFPArgRegs.
1800 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1801 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1803 FuncInfo->setVarArgsStackOffset(
1804 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1805 CCInfo.getNextStackOffset(), true));
1807 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
1808 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1810 // The fixed integer arguments of a variadic function are stored to the
1811 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
1812 // the result of va_next.
1813 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1814 // Get an existing live-in vreg, or add a new one.
1815 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
1817 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1819 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1820 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1821 MachinePointerInfo(), false, false, 0);
1822 MemOps.push_back(Store);
1823 // Increment the address by four for the next argument to store
1824 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1825 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1828 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1830 // The double arguments are stored to the VarArgsFrameIndex
1832 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1833 // Get an existing live-in vreg, or add a new one.
1834 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
1836 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1838 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1839 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1840 MachinePointerInfo(), false, false, 0);
1841 MemOps.push_back(Store);
1842 // Increment the address by eight for the next argument to store
1843 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1845 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1849 if (!MemOps.empty())
1850 Chain = DAG.getNode(ISD::TokenFactor, dl,
1851 MVT::Other, &MemOps[0], MemOps.size());
1857 PPCTargetLowering::LowerFormalArguments_Darwin(
1859 CallingConv::ID CallConv, bool isVarArg,
1860 const SmallVectorImpl<ISD::InputArg>
1862 DebugLoc dl, SelectionDAG &DAG,
1863 SmallVectorImpl<SDValue> &InVals) const {
1864 // TODO: add description of PPC stack frame format, or at least some docs.
1866 MachineFunction &MF = DAG.getMachineFunction();
1867 MachineFrameInfo *MFI = MF.getFrameInfo();
1868 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1870 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1871 bool isPPC64 = PtrVT == MVT::i64;
1872 // Potential tail calls could cause overwriting of argument stack slots.
1873 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1874 (CallConv == CallingConv::Fast));
1875 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1877 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
1878 // Area that is at least reserved in caller of this function.
1879 unsigned MinReservedArea = ArgOffset;
1881 static const unsigned GPR_32[] = { // 32-bit registers.
1882 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1883 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1885 static const unsigned GPR_64[] = { // 64-bit registers.
1886 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1887 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1890 static const unsigned *FPR = GetFPR();
1892 static const unsigned VR[] = {
1893 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1894 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1897 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1898 const unsigned Num_FPR_Regs = 13;
1899 const unsigned Num_VR_Regs = array_lengthof( VR);
1901 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1903 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1905 // In 32-bit non-varargs functions, the stack space for vectors is after the
1906 // stack space for non-vectors. We do not use this space unless we have
1907 // too many vectors to fit in registers, something that only occurs in
1908 // constructed examples:), but we have to walk the arglist to figure
1909 // that out...for the pathological case, compute VecArgOffset as the
1910 // start of the vector parameter area. Computing VecArgOffset is the
1911 // entire point of the following loop.
1912 unsigned VecArgOffset = ArgOffset;
1913 if (!isVarArg && !isPPC64) {
1914 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1916 EVT ObjectVT = Ins[ArgNo].VT;
1917 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1919 if (Flags.isByVal()) {
1920 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1921 unsigned ObjSize = Flags.getByValSize();
1923 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1924 VecArgOffset += ArgSize;
1928 switch(ObjectVT.getSimpleVT().SimpleTy) {
1929 default: llvm_unreachable("Unhandled argument type!");
1932 VecArgOffset += isPPC64 ? 8 : 4;
1934 case MVT::i64: // PPC64
1942 // Nothing to do, we're only looking at Nonvector args here.
1947 // We've found where the vector parameter area in memory is. Skip the
1948 // first 12 parameters; these don't use that memory.
1949 VecArgOffset = ((VecArgOffset+15)/16)*16;
1950 VecArgOffset += 12*16;
1952 // Add DAG nodes to load the arguments or copy them out of registers. On
1953 // entry to a function on PPC, the arguments start after the linkage area,
1954 // although the first ones are often in registers.
1956 SmallVector<SDValue, 8> MemOps;
1957 unsigned nAltivecParamsAtEnd = 0;
1958 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1960 bool needsLoad = false;
1961 EVT ObjectVT = Ins[ArgNo].VT;
1962 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1963 unsigned ArgSize = ObjSize;
1964 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1966 unsigned CurArgOffset = ArgOffset;
1968 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1969 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1970 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1971 if (isVarArg || isPPC64) {
1972 MinReservedArea = ((MinReservedArea+15)/16)*16;
1973 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1976 } else nAltivecParamsAtEnd++;
1978 // Calculate min reserved area.
1979 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1983 // FIXME the codegen can be much improved in some cases.
1984 // We do not have to keep everything in memory.
1985 if (Flags.isByVal()) {
1986 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1987 ObjSize = Flags.getByValSize();
1988 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1989 // Objects of size 1 and 2 are right justified, everything else is
1990 // left justified. This means the memory address is adjusted forwards.
1991 if (ObjSize==1 || ObjSize==2) {
1992 CurArgOffset = CurArgOffset + (4 - ObjSize);
1994 // The value of the object is its address.
1995 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
1996 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1997 InVals.push_back(FIN);
1998 if (ObjSize==1 || ObjSize==2) {
1999 if (GPR_idx != Num_GPR_Regs) {
2002 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2004 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2005 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2006 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2007 MachinePointerInfo(),
2008 ObjSize==1 ? MVT::i8 : MVT::i16,
2010 MemOps.push_back(Store);
2014 ArgOffset += PtrByteSize;
2018 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2019 // Store whatever pieces of the object are in registers
2020 // to memory. ArgVal will be address of the beginning of
2022 if (GPR_idx != Num_GPR_Regs) {
2025 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2027 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2028 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2029 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2030 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2031 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2032 MachinePointerInfo(),
2034 MemOps.push_back(Store);
2036 ArgOffset += PtrByteSize;
2038 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2045 switch (ObjectVT.getSimpleVT().SimpleTy) {
2046 default: llvm_unreachable("Unhandled argument type!");
2049 if (GPR_idx != Num_GPR_Regs) {
2050 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2051 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2055 ArgSize = PtrByteSize;
2057 // All int arguments reserve stack space in the Darwin ABI.
2058 ArgOffset += PtrByteSize;
2062 case MVT::i64: // PPC64
2063 if (GPR_idx != Num_GPR_Regs) {
2064 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2065 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2067 if (ObjectVT == MVT::i32) {
2068 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2069 // value to MVT::i64 and then truncate to the correct register size.
2071 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2072 DAG.getValueType(ObjectVT));
2073 else if (Flags.isZExt())
2074 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2075 DAG.getValueType(ObjectVT));
2077 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2083 ArgSize = PtrByteSize;
2085 // All int arguments reserve stack space in the Darwin ABI.
2091 // Every 4 bytes of argument space consumes one of the GPRs available for
2092 // argument passing.
2093 if (GPR_idx != Num_GPR_Regs) {
2095 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2098 if (FPR_idx != Num_FPR_Regs) {
2101 if (ObjectVT == MVT::f32)
2102 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2104 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2106 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2112 // All FP arguments reserve stack space in the Darwin ABI.
2113 ArgOffset += isPPC64 ? 8 : ObjSize;
2119 // Note that vector arguments in registers don't reserve stack space,
2120 // except in varargs functions.
2121 if (VR_idx != Num_VR_Regs) {
2122 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2123 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2125 while ((ArgOffset % 16) != 0) {
2126 ArgOffset += PtrByteSize;
2127 if (GPR_idx != Num_GPR_Regs)
2131 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2135 if (!isVarArg && !isPPC64) {
2136 // Vectors go after all the nonvectors.
2137 CurArgOffset = VecArgOffset;
2140 // Vectors are aligned.
2141 ArgOffset = ((ArgOffset+15)/16)*16;
2142 CurArgOffset = ArgOffset;
2150 // We need to load the argument to a virtual register if we determined above
2151 // that we ran out of physical registers of the appropriate type.
2153 int FI = MFI->CreateFixedObject(ObjSize,
2154 CurArgOffset + (ArgSize - ObjSize),
2156 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2157 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2158 false, false, false, 0);
2161 InVals.push_back(ArgVal);
2164 // Set the size that is at least reserved in caller of this function. Tail
2165 // call optimized function's reserved stack space needs to be aligned so that
2166 // taking the difference between two stack areas will result in an aligned
2168 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2169 // Add the Altivec parameters at the end, if needed.
2170 if (nAltivecParamsAtEnd) {
2171 MinReservedArea = ((MinReservedArea+15)/16)*16;
2172 MinReservedArea += 16*nAltivecParamsAtEnd;
2175 std::max(MinReservedArea,
2176 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2177 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2178 getStackAlignment();
2179 unsigned AlignMask = TargetAlign-1;
2180 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2181 FI->setMinReservedArea(MinReservedArea);
2183 // If the function takes variable number of arguments, make a frame index for
2184 // the start of the first vararg value... for expansion of llvm.va_start.
2186 int Depth = ArgOffset;
2188 FuncInfo->setVarArgsFrameIndex(
2189 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2191 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2193 // If this function is vararg, store any remaining integer argument regs
2194 // to their spots on the stack so that they may be loaded by deferencing the
2195 // result of va_next.
2196 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2200 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2202 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2204 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2205 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2206 MachinePointerInfo(), false, false, 0);
2207 MemOps.push_back(Store);
2208 // Increment the address by four for the next argument to store
2209 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2210 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2214 if (!MemOps.empty())
2215 Chain = DAG.getNode(ISD::TokenFactor, dl,
2216 MVT::Other, &MemOps[0], MemOps.size());
2221 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2222 /// linkage area for the Darwin ABI.
2224 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2228 const SmallVectorImpl<ISD::OutputArg>
2230 const SmallVectorImpl<SDValue> &OutVals,
2231 unsigned &nAltivecParamsAtEnd) {
2232 // Count how many bytes are to be pushed on the stack, including the linkage
2233 // area, and parameter passing area. We start with 24/48 bytes, which is
2234 // prereserved space for [SP][CR][LR][3 x unused].
2235 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2236 unsigned NumOps = Outs.size();
2237 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2239 // Add up all the space actually used.
2240 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2241 // they all go in registers, but we must reserve stack space for them for
2242 // possible use by the caller. In varargs or 64-bit calls, parameters are
2243 // assigned stack space in order, with padding so Altivec parameters are
2245 nAltivecParamsAtEnd = 0;
2246 for (unsigned i = 0; i != NumOps; ++i) {
2247 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2248 EVT ArgVT = Outs[i].VT;
2249 // Varargs Altivec parameters are padded to a 16 byte boundary.
2250 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2251 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2252 if (!isVarArg && !isPPC64) {
2253 // Non-varargs Altivec parameters go after all the non-Altivec
2254 // parameters; handle those later so we know how much padding we need.
2255 nAltivecParamsAtEnd++;
2258 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2259 NumBytes = ((NumBytes+15)/16)*16;
2261 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2264 // Allow for Altivec parameters at the end, if needed.
2265 if (nAltivecParamsAtEnd) {
2266 NumBytes = ((NumBytes+15)/16)*16;
2267 NumBytes += 16*nAltivecParamsAtEnd;
2270 // The prolog code of the callee may store up to 8 GPR argument registers to
2271 // the stack, allowing va_start to index over them in memory if its varargs.
2272 // Because we cannot tell if this is needed on the caller side, we have to
2273 // conservatively assume that it is needed. As such, make sure we have at
2274 // least enough stack space for the caller to store the 8 GPRs.
2275 NumBytes = std::max(NumBytes,
2276 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2278 // Tail call needs the stack to be aligned.
2279 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2280 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2281 getFrameLowering()->getStackAlignment();
2282 unsigned AlignMask = TargetAlign-1;
2283 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2289 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2290 /// adjusted to accommodate the arguments for the tailcall.
2291 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2292 unsigned ParamSize) {
2294 if (!isTailCall) return 0;
2296 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2297 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2298 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2299 // Remember only if the new adjustement is bigger.
2300 if (SPDiff < FI->getTailCallSPDelta())
2301 FI->setTailCallSPDelta(SPDiff);
2306 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2307 /// for tail call optimization. Targets which want to do tail call
2308 /// optimization should implement this function.
2310 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2311 CallingConv::ID CalleeCC,
2313 const SmallVectorImpl<ISD::InputArg> &Ins,
2314 SelectionDAG& DAG) const {
2315 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2318 // Variable argument functions are not supported.
2322 MachineFunction &MF = DAG.getMachineFunction();
2323 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2324 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2325 // Functions containing by val parameters are not supported.
2326 for (unsigned i = 0; i != Ins.size(); i++) {
2327 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2328 if (Flags.isByVal()) return false;
2331 // Non PIC/GOT tail calls are supported.
2332 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2335 // At the moment we can only do local tail calls (in same module, hidden
2336 // or protected) if we are generating PIC.
2337 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2338 return G->getGlobal()->hasHiddenVisibility()
2339 || G->getGlobal()->hasProtectedVisibility();
2345 /// isCallCompatibleAddress - Return the immediate to use if the specified
2346 /// 32-bit value is representable in the immediate field of a BxA instruction.
2347 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2348 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2351 int Addr = C->getZExtValue();
2352 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2353 (Addr << 6 >> 6) != Addr)
2354 return 0; // Top 6 bits have to be sext of immediate.
2356 return DAG.getConstant((int)C->getZExtValue() >> 2,
2357 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2362 struct TailCallArgumentInfo {
2367 TailCallArgumentInfo() : FrameIdx(0) {}
2372 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2374 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2376 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2377 SmallVector<SDValue, 8> &MemOpChains,
2379 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2380 SDValue Arg = TailCallArgs[i].Arg;
2381 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2382 int FI = TailCallArgs[i].FrameIdx;
2383 // Store relative to framepointer.
2384 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2385 MachinePointerInfo::getFixedStack(FI),
2390 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2391 /// the appropriate stack slot for the tail call optimized function call.
2392 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2393 MachineFunction &MF,
2402 // Calculate the new stack slot for the return address.
2403 int SlotSize = isPPC64 ? 8 : 4;
2404 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2406 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2407 NewRetAddrLoc, true);
2408 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2409 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2410 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2411 MachinePointerInfo::getFixedStack(NewRetAddr),
2414 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2415 // slot as the FP is never overwritten.
2418 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2419 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2421 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2422 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2423 MachinePointerInfo::getFixedStack(NewFPIdx),
2430 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2431 /// the position of the argument.
2433 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2434 SDValue Arg, int SPDiff, unsigned ArgOffset,
2435 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2436 int Offset = ArgOffset + SPDiff;
2437 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2438 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2439 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2440 SDValue FIN = DAG.getFrameIndex(FI, VT);
2441 TailCallArgumentInfo Info;
2443 Info.FrameIdxOp = FIN;
2445 TailCallArguments.push_back(Info);
2448 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2449 /// stack slot. Returns the chain as result and the loaded frame pointers in
2450 /// LROpOut/FPOpout. Used when tail calling.
2451 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2457 DebugLoc dl) const {
2459 // Load the LR and FP stack slot for later adjusting.
2460 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2461 LROpOut = getReturnAddrFrameIndex(DAG);
2462 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2463 false, false, false, 0);
2464 Chain = SDValue(LROpOut.getNode(), 1);
2466 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2467 // slot as the FP is never overwritten.
2469 FPOpOut = getFramePointerFrameIndex(DAG);
2470 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
2471 false, false, false, 0);
2472 Chain = SDValue(FPOpOut.getNode(), 1);
2478 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2479 /// by "Src" to address "Dst" of size "Size". Alignment information is
2480 /// specified by the specific parameter attribute. The copy will be passed as
2481 /// a byval function parameter.
2482 /// Sometimes what we are copying is the end of a larger object, the part that
2483 /// does not fit in registers.
2485 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2486 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2488 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2489 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2490 false, false, MachinePointerInfo(0),
2491 MachinePointerInfo(0));
2494 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2497 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2498 SDValue Arg, SDValue PtrOff, int SPDiff,
2499 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2500 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2501 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
2503 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2508 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2510 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2511 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2512 DAG.getConstant(ArgOffset, PtrVT));
2514 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2515 MachinePointerInfo(), false, false, 0));
2516 // Calculate and remember argument location.
2517 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2522 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2523 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2524 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2525 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2526 MachineFunction &MF = DAG.getMachineFunction();
2528 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2529 // might overwrite each other in case of tail call optimization.
2530 SmallVector<SDValue, 8> MemOpChains2;
2531 // Do not flag preceding copytoreg stuff together with the following stuff.
2533 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2535 if (!MemOpChains2.empty())
2536 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2537 &MemOpChains2[0], MemOpChains2.size());
2539 // Store the return address to the appropriate stack slot.
2540 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2541 isPPC64, isDarwinABI, dl);
2543 // Emit callseq_end just before tailcall node.
2544 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2545 DAG.getIntPtrConstant(0, true), InFlag);
2546 InFlag = Chain.getValue(1);
2550 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2551 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2552 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2553 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2554 const PPCSubtarget &PPCSubTarget) {
2556 bool isPPC64 = PPCSubTarget.isPPC64();
2557 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
2559 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2560 NodeTys.push_back(MVT::Other); // Returns a chain
2561 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
2563 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2565 bool needIndirectCall = true;
2566 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
2567 // If this is an absolute destination address, use the munged value.
2568 Callee = SDValue(Dest, 0);
2569 needIndirectCall = false;
2572 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2573 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
2574 // Use indirect calls for ALL functions calls in JIT mode, since the
2575 // far-call stubs may be outside relocation limits for a BL instruction.
2576 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
2577 unsigned OpFlags = 0;
2578 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2579 (PPCSubTarget.getTargetTriple().isMacOSX() &&
2580 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
2581 (G->getGlobal()->isDeclaration() ||
2582 G->getGlobal()->isWeakForLinker())) {
2583 // PC-relative references to external symbols should go through $stub,
2584 // unless we're building with the leopard linker or later, which
2585 // automatically synthesizes these stubs.
2586 OpFlags = PPCII::MO_DARWIN_STUB;
2589 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
2590 // every direct call is) turn it into a TargetGlobalAddress /
2591 // TargetExternalSymbol node so that legalize doesn't hack it.
2592 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2593 Callee.getValueType(),
2595 needIndirectCall = false;
2599 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2600 unsigned char OpFlags = 0;
2602 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2603 (PPCSubTarget.getTargetTriple().isMacOSX() &&
2604 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
2605 // PC-relative references to external symbols should go through $stub,
2606 // unless we're building with the leopard linker or later, which
2607 // automatically synthesizes these stubs.
2608 OpFlags = PPCII::MO_DARWIN_STUB;
2611 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
2613 needIndirectCall = false;
2616 if (needIndirectCall) {
2617 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2618 // to do the call, we can't use PPCISD::CALL.
2619 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2621 if (isSVR4ABI && isPPC64) {
2622 // Function pointers in the 64-bit SVR4 ABI do not point to the function
2623 // entry point, but to the function descriptor (the function entry point
2624 // address is part of the function descriptor though).
2625 // The function descriptor is a three doubleword structure with the
2626 // following fields: function entry point, TOC base address and
2627 // environment pointer.
2628 // Thus for a call through a function pointer, the following actions need
2630 // 1. Save the TOC of the caller in the TOC save area of its stack
2631 // frame (this is done in LowerCall_Darwin()).
2632 // 2. Load the address of the function entry point from the function
2634 // 3. Load the TOC of the callee from the function descriptor into r2.
2635 // 4. Load the environment pointer from the function descriptor into
2637 // 5. Branch to the function entry point address.
2638 // 6. On return of the callee, the TOC of the caller needs to be
2639 // restored (this is done in FinishCall()).
2641 // All those operations are flagged together to ensure that no other
2642 // operations can be scheduled in between. E.g. without flagging the
2643 // operations together, a TOC access in the caller could be scheduled
2644 // between the load of the callee TOC and the branch to the callee, which
2645 // results in the TOC access going through the TOC of the callee instead
2646 // of going through the TOC of the caller, which leads to incorrect code.
2648 // Load the address of the function entry point from the function
2650 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
2651 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2652 InFlag.getNode() ? 3 : 2);
2653 Chain = LoadFuncPtr.getValue(1);
2654 InFlag = LoadFuncPtr.getValue(2);
2656 // Load environment pointer into r11.
2657 // Offset of the environment pointer within the function descriptor.
2658 SDValue PtrOff = DAG.getIntPtrConstant(16);
2660 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2661 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2663 Chain = LoadEnvPtr.getValue(1);
2664 InFlag = LoadEnvPtr.getValue(2);
2666 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2668 Chain = EnvVal.getValue(0);
2669 InFlag = EnvVal.getValue(1);
2671 // Load TOC of the callee into r2. We are using a target-specific load
2672 // with r2 hard coded, because the result of a target-independent load
2673 // would never go directly into r2, since r2 is a reserved register (which
2674 // prevents the register allocator from allocating it), resulting in an
2675 // additional register being allocated and an unnecessary move instruction
2677 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2678 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2680 Chain = LoadTOCPtr.getValue(0);
2681 InFlag = LoadTOCPtr.getValue(1);
2683 MTCTROps[0] = Chain;
2684 MTCTROps[1] = LoadFuncPtr;
2685 MTCTROps[2] = InFlag;
2688 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2689 2 + (InFlag.getNode() != 0));
2690 InFlag = Chain.getValue(1);
2693 NodeTys.push_back(MVT::Other);
2694 NodeTys.push_back(MVT::Glue);
2695 Ops.push_back(Chain);
2696 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2698 // Add CTR register as callee so a bctr can be emitted later.
2700 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
2703 // If this is a direct call, pass the chain and the callee.
2704 if (Callee.getNode()) {
2705 Ops.push_back(Chain);
2706 Ops.push_back(Callee);
2708 // If this is a tail call add stack pointer delta.
2710 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2712 // Add argument registers to the end of the list so that they are known live
2714 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2715 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2716 RegsToPass[i].second.getValueType()));
2722 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2723 CallingConv::ID CallConv, bool isVarArg,
2724 const SmallVectorImpl<ISD::InputArg> &Ins,
2725 DebugLoc dl, SelectionDAG &DAG,
2726 SmallVectorImpl<SDValue> &InVals) const {
2728 SmallVector<CCValAssign, 16> RVLocs;
2729 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2730 getTargetMachine(), RVLocs, *DAG.getContext());
2731 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2733 // Copy all of the result registers out of their specified physreg.
2734 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2735 CCValAssign &VA = RVLocs[i];
2736 EVT VT = VA.getValVT();
2737 assert(VA.isRegLoc() && "Can only return in registers!");
2738 Chain = DAG.getCopyFromReg(Chain, dl,
2739 VA.getLocReg(), VT, InFlag).getValue(1);
2740 InVals.push_back(Chain.getValue(0));
2741 InFlag = Chain.getValue(2);
2748 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2749 bool isTailCall, bool isVarArg,
2751 SmallVector<std::pair<unsigned, SDValue>, 8>
2753 SDValue InFlag, SDValue Chain,
2755 int SPDiff, unsigned NumBytes,
2756 const SmallVectorImpl<ISD::InputArg> &Ins,
2757 SmallVectorImpl<SDValue> &InVals) const {
2758 std::vector<EVT> NodeTys;
2759 SmallVector<SDValue, 8> Ops;
2760 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2761 isTailCall, RegsToPass, Ops, NodeTys,
2764 // When performing tail call optimization the callee pops its arguments off
2765 // the stack. Account for this here so these bytes can be pushed back on in
2766 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2767 int BytesCalleePops =
2768 (CallConv == CallingConv::Fast &&
2769 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
2771 if (InFlag.getNode())
2772 Ops.push_back(InFlag);
2776 // If this is the first return lowered for this function, add the regs
2777 // to the liveout set for the function.
2778 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2779 SmallVector<CCValAssign, 16> RVLocs;
2780 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2781 getTargetMachine(), RVLocs, *DAG.getContext());
2782 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2783 for (unsigned i = 0; i != RVLocs.size(); ++i)
2784 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2787 assert(((Callee.getOpcode() == ISD::Register &&
2788 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2789 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2790 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2791 isa<ConstantSDNode>(Callee)) &&
2792 "Expecting an global address, external symbol, absolute value or register");
2794 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2797 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2798 InFlag = Chain.getValue(1);
2800 // Add a NOP immediately after the branch instruction when using the 64-bit
2801 // SVR4 ABI. At link time, if caller and callee are in a different module and
2802 // thus have a different TOC, the call will be replaced with a call to a stub
2803 // function which saves the current TOC, loads the TOC of the callee and
2804 // branches to the callee. The NOP will be replaced with a load instruction
2805 // which restores the TOC of the caller from the TOC save slot of the current
2806 // stack frame. If caller and callee belong to the same module (and have the
2807 // same TOC), the NOP will remain unchanged.
2808 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2809 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2810 if (CallOpc == PPCISD::BCTRL_SVR4) {
2811 // This is a call through a function pointer.
2812 // Restore the caller TOC from the save area into R2.
2813 // See PrepareCall() for more information about calls through function
2814 // pointers in the 64-bit SVR4 ABI.
2815 // We are using a target-specific load with r2 hard coded, because the
2816 // result of a target-independent load would never go directly into r2,
2817 // since r2 is a reserved register (which prevents the register allocator
2818 // from allocating it), resulting in an additional register being
2819 // allocated and an unnecessary move instruction being generated.
2820 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2821 InFlag = Chain.getValue(1);
2823 // Otherwise insert NOP.
2824 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Glue, InFlag);
2828 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2829 DAG.getIntPtrConstant(BytesCalleePops, true),
2832 InFlag = Chain.getValue(1);
2834 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2835 Ins, dl, DAG, InVals);
2839 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2840 CallingConv::ID CallConv, bool isVarArg,
2842 const SmallVectorImpl<ISD::OutputArg> &Outs,
2843 const SmallVectorImpl<SDValue> &OutVals,
2844 const SmallVectorImpl<ISD::InputArg> &Ins,
2845 DebugLoc dl, SelectionDAG &DAG,
2846 SmallVectorImpl<SDValue> &InVals) const {
2848 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2851 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
2852 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2853 isTailCall, Outs, OutVals, Ins,
2856 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2857 isTailCall, Outs, OutVals, Ins,
2862 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2863 CallingConv::ID CallConv, bool isVarArg,
2865 const SmallVectorImpl<ISD::OutputArg> &Outs,
2866 const SmallVectorImpl<SDValue> &OutVals,
2867 const SmallVectorImpl<ISD::InputArg> &Ins,
2868 DebugLoc dl, SelectionDAG &DAG,
2869 SmallVectorImpl<SDValue> &InVals) const {
2870 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2871 // of the 32-bit SVR4 ABI stack frame layout.
2873 assert((CallConv == CallingConv::C ||
2874 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2876 unsigned PtrByteSize = 4;
2878 MachineFunction &MF = DAG.getMachineFunction();
2880 // Mark this function as potentially containing a function that contains a
2881 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2882 // and restoring the callers stack pointer in this functions epilog. This is
2883 // done because by tail calling the called function might overwrite the value
2884 // in this function's (MF) stack pointer stack slot 0(SP).
2885 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2886 CallConv == CallingConv::Fast)
2887 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2889 // Count how many bytes are to be pushed on the stack, including the linkage
2890 // area, parameter list area and the part of the local variable space which
2891 // contains copies of aggregates which are passed by value.
2893 // Assign locations to all of the outgoing arguments.
2894 SmallVector<CCValAssign, 16> ArgLocs;
2895 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2896 getTargetMachine(), ArgLocs, *DAG.getContext());
2898 // Reserve space for the linkage area on the stack.
2899 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2902 // Handle fixed and variable vector arguments differently.
2903 // Fixed vector arguments go into registers as long as registers are
2904 // available. Variable vector arguments always go into memory.
2905 unsigned NumArgs = Outs.size();
2907 for (unsigned i = 0; i != NumArgs; ++i) {
2908 MVT ArgVT = Outs[i].VT;
2909 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2912 if (Outs[i].IsFixed) {
2913 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2916 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2922 errs() << "Call operand #" << i << " has unhandled type "
2923 << EVT(ArgVT).getEVTString() << "\n";
2925 llvm_unreachable(0);
2929 // All arguments are treated the same.
2930 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2933 // Assign locations to all of the outgoing aggregate by value arguments.
2934 SmallVector<CCValAssign, 16> ByValArgLocs;
2935 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2936 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2938 // Reserve stack space for the allocations in CCInfo.
2939 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2941 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2943 // Size of the linkage area, parameter list area and the part of the local
2944 // space variable where copies of aggregates which are passed by value are
2946 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2948 // Calculate by how many bytes the stack has to be adjusted in case of tail
2949 // call optimization.
2950 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2952 // Adjust the stack pointer for the new arguments...
2953 // These operations are automatically eliminated by the prolog/epilog pass
2954 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2955 SDValue CallSeqStart = Chain;
2957 // Load the return address and frame pointer so it can be moved somewhere else
2960 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2963 // Set up a copy of the stack pointer for use loading and storing any
2964 // arguments that may not fit in the registers available for argument
2966 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2968 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2969 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2970 SmallVector<SDValue, 8> MemOpChains;
2972 bool seenFloatArg = false;
2973 // Walk the register/memloc assignments, inserting copies/loads.
2974 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2977 CCValAssign &VA = ArgLocs[i];
2978 SDValue Arg = OutVals[i];
2979 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2981 if (Flags.isByVal()) {
2982 // Argument is an aggregate which is passed by value, thus we need to
2983 // create a copy of it in the local variable space of the current stack
2984 // frame (which is the stack frame of the caller) and pass the address of
2985 // this copy to the callee.
2986 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2987 CCValAssign &ByValVA = ByValArgLocs[j++];
2988 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2990 // Memory reserved in the local variable space of the callers stack frame.
2991 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2993 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2994 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2996 // Create a copy of the argument in the local area of the current
2998 SDValue MemcpyCall =
2999 CreateCopyOfByValArgument(Arg, PtrOff,
3000 CallSeqStart.getNode()->getOperand(0),
3003 // This must go outside the CALLSEQ_START..END.
3004 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3005 CallSeqStart.getNode()->getOperand(1));
3006 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3007 NewCallSeqStart.getNode());
3008 Chain = CallSeqStart = NewCallSeqStart;
3010 // Pass the address of the aggregate copy on the stack either in a
3011 // physical register or in the parameter list area of the current stack
3012 // frame to the callee.
3016 if (VA.isRegLoc()) {
3017 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3018 // Put argument in a physical register.
3019 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3021 // Put argument in the parameter list area of the current stack frame.
3022 assert(VA.isMemLoc());
3023 unsigned LocMemOffset = VA.getLocMemOffset();
3026 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3027 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3029 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3030 MachinePointerInfo(),
3033 // Calculate and remember argument location.
3034 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3040 if (!MemOpChains.empty())
3041 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3042 &MemOpChains[0], MemOpChains.size());
3044 // Set CR6 to true if this is a vararg call with floating args passed in
3047 SDValue SetCR(DAG.getMachineNode(seenFloatArg ? PPC::CRSET : PPC::CRUNSET,
3049 RegsToPass.push_back(std::make_pair(unsigned(PPC::CR1EQ), SetCR));
3052 // Build a sequence of copy-to-reg nodes chained together with token chain
3053 // and flag operands which copy the outgoing args into the appropriate regs.
3055 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3056 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3057 RegsToPass[i].second, InFlag);
3058 InFlag = Chain.getValue(1);
3062 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3063 false, TailCallArguments);
3065 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3066 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3071 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
3072 CallingConv::ID CallConv, bool isVarArg,
3074 const SmallVectorImpl<ISD::OutputArg> &Outs,
3075 const SmallVectorImpl<SDValue> &OutVals,
3076 const SmallVectorImpl<ISD::InputArg> &Ins,
3077 DebugLoc dl, SelectionDAG &DAG,
3078 SmallVectorImpl<SDValue> &InVals) const {
3080 unsigned NumOps = Outs.size();
3082 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3083 bool isPPC64 = PtrVT == MVT::i64;
3084 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3086 MachineFunction &MF = DAG.getMachineFunction();
3088 // Mark this function as potentially containing a function that contains a
3089 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3090 // and restoring the callers stack pointer in this functions epilog. This is
3091 // done because by tail calling the called function might overwrite the value
3092 // in this function's (MF) stack pointer stack slot 0(SP).
3093 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3094 CallConv == CallingConv::Fast)
3095 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3097 unsigned nAltivecParamsAtEnd = 0;
3099 // Count how many bytes are to be pushed on the stack, including the linkage
3100 // area, and parameter passing area. We start with 24/48 bytes, which is
3101 // prereserved space for [SP][CR][LR][3 x unused].
3103 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
3105 nAltivecParamsAtEnd);
3107 // Calculate by how many bytes the stack has to be adjusted in case of tail
3108 // call optimization.
3109 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3111 // To protect arguments on the stack from being clobbered in a tail call,
3112 // force all the loads to happen before doing any other lowering.
3114 Chain = DAG.getStackArgumentTokenFactor(Chain);
3116 // Adjust the stack pointer for the new arguments...
3117 // These operations are automatically eliminated by the prolog/epilog pass
3118 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3119 SDValue CallSeqStart = Chain;
3121 // Load the return address and frame pointer so it can be move somewhere else
3124 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3127 // Set up a copy of the stack pointer for use loading and storing any
3128 // arguments that may not fit in the registers available for argument
3132 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3134 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3136 // Figure out which arguments are going to go in registers, and which in
3137 // memory. Also, if this is a vararg function, floating point operations
3138 // must be stored to our stack, and loaded into integer regs as well, if
3139 // any integer regs are available for argument passing.
3140 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
3141 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3143 static const unsigned GPR_32[] = { // 32-bit registers.
3144 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3145 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3147 static const unsigned GPR_64[] = { // 64-bit registers.
3148 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3149 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3151 static const unsigned *FPR = GetFPR();
3153 static const unsigned VR[] = {
3154 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3155 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3157 const unsigned NumGPRs = array_lengthof(GPR_32);
3158 const unsigned NumFPRs = 13;
3159 const unsigned NumVRs = array_lengthof(VR);
3161 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
3163 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3164 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3166 SmallVector<SDValue, 8> MemOpChains;
3167 for (unsigned i = 0; i != NumOps; ++i) {
3168 SDValue Arg = OutVals[i];
3169 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3171 // PtrOff will be used to store the current argument to the stack if a
3172 // register cannot be found for it.
3175 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3177 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3179 // On PPC64, promote integers to 64-bit values.
3180 if (isPPC64 && Arg.getValueType() == MVT::i32) {
3181 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3182 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3183 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3186 // FIXME memcpy is used way more than necessary. Correctness first.
3187 if (Flags.isByVal()) {
3188 unsigned Size = Flags.getByValSize();
3189 if (Size==1 || Size==2) {
3190 // Very small objects are passed right-justified.
3191 // Everything else is passed left-justified.
3192 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3193 if (GPR_idx != NumGPRs) {
3194 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3195 MachinePointerInfo(), VT,
3197 MemOpChains.push_back(Load.getValue(1));
3198 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3200 ArgOffset += PtrByteSize;
3202 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3203 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3204 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3205 CallSeqStart.getNode()->getOperand(0),
3207 // This must go outside the CALLSEQ_START..END.
3208 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3209 CallSeqStart.getNode()->getOperand(1));
3210 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3211 NewCallSeqStart.getNode());
3212 Chain = CallSeqStart = NewCallSeqStart;
3213 ArgOffset += PtrByteSize;
3217 // Copy entire object into memory. There are cases where gcc-generated
3218 // code assumes it is there, even if it could be put entirely into
3219 // registers. (This is not what the doc says.)
3220 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3221 CallSeqStart.getNode()->getOperand(0),
3223 // This must go outside the CALLSEQ_START..END.
3224 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3225 CallSeqStart.getNode()->getOperand(1));
3226 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3227 Chain = CallSeqStart = NewCallSeqStart;
3228 // And copy the pieces of it that fit into registers.
3229 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3230 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3231 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3232 if (GPR_idx != NumGPRs) {
3233 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3234 MachinePointerInfo(),
3235 false, false, false, 0);
3236 MemOpChains.push_back(Load.getValue(1));
3237 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3238 ArgOffset += PtrByteSize;
3240 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3247 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3248 default: llvm_unreachable("Unexpected ValueType for argument!");
3251 if (GPR_idx != NumGPRs) {
3252 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3254 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3255 isPPC64, isTailCall, false, MemOpChains,
3256 TailCallArguments, dl);
3258 ArgOffset += PtrByteSize;
3262 if (FPR_idx != NumFPRs) {
3263 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3266 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3267 MachinePointerInfo(), false, false, 0);
3268 MemOpChains.push_back(Store);
3270 // Float varargs are always shadowed in available integer registers
3271 if (GPR_idx != NumGPRs) {
3272 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3273 MachinePointerInfo(), false, false,
3275 MemOpChains.push_back(Load.getValue(1));
3276 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3278 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3279 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3280 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3281 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3282 MachinePointerInfo(),
3283 false, false, false, 0);
3284 MemOpChains.push_back(Load.getValue(1));
3285 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3288 // If we have any FPRs remaining, we may also have GPRs remaining.
3289 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3291 if (GPR_idx != NumGPRs)
3293 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3294 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3298 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3299 isPPC64, isTailCall, false, MemOpChains,
3300 TailCallArguments, dl);
3305 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3312 // These go aligned on the stack, or in the corresponding R registers
3313 // when within range. The Darwin PPC ABI doc claims they also go in
3314 // V registers; in fact gcc does this only for arguments that are
3315 // prototyped, not for those that match the ... We do it for all
3316 // arguments, seems to work.
3317 while (ArgOffset % 16 !=0) {
3318 ArgOffset += PtrByteSize;
3319 if (GPR_idx != NumGPRs)
3322 // We could elide this store in the case where the object fits
3323 // entirely in R registers. Maybe later.
3324 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3325 DAG.getConstant(ArgOffset, PtrVT));
3326 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3327 MachinePointerInfo(), false, false, 0);
3328 MemOpChains.push_back(Store);
3329 if (VR_idx != NumVRs) {
3330 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3331 MachinePointerInfo(),
3332 false, false, false, 0);
3333 MemOpChains.push_back(Load.getValue(1));
3334 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3337 for (unsigned i=0; i<16; i+=PtrByteSize) {
3338 if (GPR_idx == NumGPRs)
3340 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3341 DAG.getConstant(i, PtrVT));
3342 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3343 false, false, false, 0);
3344 MemOpChains.push_back(Load.getValue(1));
3345 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3350 // Non-varargs Altivec params generally go in registers, but have
3351 // stack space allocated at the end.
3352 if (VR_idx != NumVRs) {
3353 // Doesn't have GPR space allocated.
3354 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3355 } else if (nAltivecParamsAtEnd==0) {
3356 // We are emitting Altivec params in order.
3357 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3358 isPPC64, isTailCall, true, MemOpChains,
3359 TailCallArguments, dl);
3365 // If all Altivec parameters fit in registers, as they usually do,
3366 // they get stack space following the non-Altivec parameters. We
3367 // don't track this here because nobody below needs it.
3368 // If there are more Altivec parameters than fit in registers emit
3370 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3372 // Offset is aligned; skip 1st 12 params which go in V registers.
3373 ArgOffset = ((ArgOffset+15)/16)*16;
3375 for (unsigned i = 0; i != NumOps; ++i) {
3376 SDValue Arg = OutVals[i];
3377 EVT ArgType = Outs[i].VT;
3378 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3379 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3382 // We are emitting Altivec params in order.
3383 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3384 isPPC64, isTailCall, true, MemOpChains,
3385 TailCallArguments, dl);
3392 if (!MemOpChains.empty())
3393 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3394 &MemOpChains[0], MemOpChains.size());
3396 // Check if this is an indirect call (MTCTR/BCTRL).
3397 // See PrepareCall() for more information about calls through function
3398 // pointers in the 64-bit SVR4 ABI.
3399 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3400 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3401 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3402 !isBLACompatibleAddress(Callee, DAG)) {
3403 // Load r2 into a virtual register and store it to the TOC save area.
3404 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3405 // TOC save area offset.
3406 SDValue PtrOff = DAG.getIntPtrConstant(40);
3407 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3408 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
3412 // On Darwin, R12 must contain the address of an indirect callee. This does
3413 // not mean the MTCTR instruction must use R12; it's easier to model this as
3414 // an extra parameter, so do that.
3416 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3417 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3418 !isBLACompatibleAddress(Callee, DAG))
3419 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
3420 PPC::R12), Callee));
3422 // Build a sequence of copy-to-reg nodes chained together with token chain
3423 // and flag operands which copy the outgoing args into the appropriate regs.
3425 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3426 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3427 RegsToPass[i].second, InFlag);
3428 InFlag = Chain.getValue(1);
3432 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3433 FPOp, true, TailCallArguments);
3435 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3436 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3441 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3442 MachineFunction &MF, bool isVarArg,
3443 const SmallVectorImpl<ISD::OutputArg> &Outs,
3444 LLVMContext &Context) const {
3445 SmallVector<CCValAssign, 16> RVLocs;
3446 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3448 return CCInfo.CheckReturn(Outs, RetCC_PPC);
3452 PPCTargetLowering::LowerReturn(SDValue Chain,
3453 CallingConv::ID CallConv, bool isVarArg,
3454 const SmallVectorImpl<ISD::OutputArg> &Outs,
3455 const SmallVectorImpl<SDValue> &OutVals,
3456 DebugLoc dl, SelectionDAG &DAG) const {
3458 SmallVector<CCValAssign, 16> RVLocs;
3459 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3460 getTargetMachine(), RVLocs, *DAG.getContext());
3461 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3463 // If this is the first return lowered for this function, add the regs to the
3464 // liveout set for the function.
3465 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3466 for (unsigned i = 0; i != RVLocs.size(); ++i)
3467 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3472 // Copy the result values into the output registers.
3473 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3474 CCValAssign &VA = RVLocs[i];
3475 assert(VA.isRegLoc() && "Can only return in registers!");
3476 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3478 Flag = Chain.getValue(1);
3482 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3484 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3487 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3488 const PPCSubtarget &Subtarget) const {
3489 // When we pop the dynamic allocation we need to restore the SP link.
3490 DebugLoc dl = Op.getDebugLoc();
3492 // Get the corect type for pointers.
3493 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3495 // Construct the stack pointer operand.
3496 bool isPPC64 = Subtarget.isPPC64();
3497 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3498 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3500 // Get the operands for the STACKRESTORE.
3501 SDValue Chain = Op.getOperand(0);
3502 SDValue SaveSP = Op.getOperand(1);
3504 // Load the old link SP.
3505 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
3506 MachinePointerInfo(),
3507 false, false, false, 0);
3509 // Restore the stack pointer.
3510 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3512 // Store the old link SP.
3513 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
3520 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3521 MachineFunction &MF = DAG.getMachineFunction();
3522 bool isPPC64 = PPCSubTarget.isPPC64();
3523 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3524 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3526 // Get current frame pointer save index. The users of this index will be
3527 // primarily DYNALLOC instructions.
3528 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3529 int RASI = FI->getReturnAddrSaveIndex();
3531 // If the frame pointer save index hasn't been defined yet.
3533 // Find out what the fix offset of the frame pointer save area.
3534 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
3535 // Allocate the frame index for frame pointer save area.
3536 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
3538 FI->setReturnAddrSaveIndex(RASI);
3540 return DAG.getFrameIndex(RASI, PtrVT);
3544 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3545 MachineFunction &MF = DAG.getMachineFunction();
3546 bool isPPC64 = PPCSubTarget.isPPC64();
3547 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3548 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3550 // Get current frame pointer save index. The users of this index will be
3551 // primarily DYNALLOC instructions.
3552 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3553 int FPSI = FI->getFramePointerSaveIndex();
3555 // If the frame pointer save index hasn't been defined yet.
3557 // Find out what the fix offset of the frame pointer save area.
3558 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
3561 // Allocate the frame index for frame pointer save area.
3562 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
3564 FI->setFramePointerSaveIndex(FPSI);
3566 return DAG.getFrameIndex(FPSI, PtrVT);
3569 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3571 const PPCSubtarget &Subtarget) const {
3573 SDValue Chain = Op.getOperand(0);
3574 SDValue Size = Op.getOperand(1);
3575 DebugLoc dl = Op.getDebugLoc();
3577 // Get the corect type for pointers.
3578 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3580 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3581 DAG.getConstant(0, PtrVT), Size);
3582 // Construct a node for the frame pointer save index.
3583 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3584 // Build a DYNALLOC node.
3585 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3586 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3587 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3590 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3592 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3593 // Not FP? Not a fsel.
3594 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3595 !Op.getOperand(2).getValueType().isFloatingPoint())
3598 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3600 // Cannot handle SETEQ/SETNE.
3601 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3603 EVT ResVT = Op.getValueType();
3604 EVT CmpVT = Op.getOperand(0).getValueType();
3605 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3606 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3607 DebugLoc dl = Op.getDebugLoc();
3609 // If the RHS of the comparison is a 0.0, we don't need to do the
3610 // subtraction at all.
3611 if (isFloatingPointZero(RHS))
3613 default: break; // SETUO etc aren't handled by fsel.
3616 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3619 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3620 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3621 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3624 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3627 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3628 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3629 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3630 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3635 default: break; // SETUO etc aren't handled by fsel.
3638 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3639 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3640 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3641 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3644 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3645 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3646 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3647 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3650 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3651 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3652 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3653 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3656 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3657 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3658 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3659 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3664 // FIXME: Split this code up when LegalizeDAGTypes lands.
3665 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3666 DebugLoc dl) const {
3667 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3668 SDValue Src = Op.getOperand(0);
3669 if (Src.getValueType() == MVT::f32)
3670 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3673 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3674 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3676 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3681 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3685 // Convert the FP value to an int value through memory.
3686 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3688 // Emit a store to the stack slot.
3689 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
3690 MachinePointerInfo(), false, false, 0);
3692 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3694 if (Op.getValueType() == MVT::i32)
3695 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3696 DAG.getConstant(4, FIPtr.getValueType()));
3697 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
3698 false, false, false, 0);
3701 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
3702 SelectionDAG &DAG) const {
3703 DebugLoc dl = Op.getDebugLoc();
3704 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3705 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3708 if (Op.getOperand(0).getValueType() == MVT::i64) {
3709 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
3710 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3711 if (Op.getValueType() == MVT::f32)
3712 FP = DAG.getNode(ISD::FP_ROUND, dl,
3713 MVT::f32, FP, DAG.getIntPtrConstant(0));
3717 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3718 "Unhandled SINT_TO_FP type in custom expander!");
3719 // Since we only generate this in 64-bit mode, we can take advantage of
3720 // 64-bit registers. In particular, sign extend the input value into the
3721 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3722 // then lfd it and fcfid it.
3723 MachineFunction &MF = DAG.getMachineFunction();
3724 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3725 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3726 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3727 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3729 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3732 // STD the extended value into the stack slot.
3733 MachineMemOperand *MMO =
3734 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
3735 MachineMemOperand::MOStore, 8, 8);
3736 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3738 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3739 Ops, 4, MVT::i64, MMO);
3740 // Load the value as a double.
3741 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
3742 false, false, false, 0);
3744 // FCFID it and return it.
3745 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3746 if (Op.getValueType() == MVT::f32)
3747 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3751 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3752 SelectionDAG &DAG) const {
3753 DebugLoc dl = Op.getDebugLoc();
3755 The rounding mode is in bits 30:31 of FPSR, and has the following
3762 FLT_ROUNDS, on the other hand, expects the following:
3769 To perform the conversion, we do:
3770 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3773 MachineFunction &MF = DAG.getMachineFunction();
3774 EVT VT = Op.getValueType();
3775 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3776 std::vector<EVT> NodeTys;
3777 SDValue MFFSreg, InFlag;
3779 // Save FP Control Word to register
3780 NodeTys.push_back(MVT::f64); // return register
3781 NodeTys.push_back(MVT::Glue); // unused in this context
3782 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3784 // Save FP register to stack slot
3785 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3786 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3787 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3788 StackSlot, MachinePointerInfo(), false, false,0);
3790 // Load FP Control Word from low 32 bits of stack slot.
3791 SDValue Four = DAG.getConstant(4, PtrVT);
3792 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3793 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
3794 false, false, false, 0);
3796 // Transform as necessary
3798 DAG.getNode(ISD::AND, dl, MVT::i32,
3799 CWD, DAG.getConstant(3, MVT::i32));
3801 DAG.getNode(ISD::SRL, dl, MVT::i32,
3802 DAG.getNode(ISD::AND, dl, MVT::i32,
3803 DAG.getNode(ISD::XOR, dl, MVT::i32,
3804 CWD, DAG.getConstant(3, MVT::i32)),
3805 DAG.getConstant(3, MVT::i32)),
3806 DAG.getConstant(1, MVT::i32));
3809 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3811 return DAG.getNode((VT.getSizeInBits() < 16 ?
3812 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3815 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3816 EVT VT = Op.getValueType();
3817 unsigned BitWidth = VT.getSizeInBits();
3818 DebugLoc dl = Op.getDebugLoc();
3819 assert(Op.getNumOperands() == 3 &&
3820 VT == Op.getOperand(1).getValueType() &&
3823 // Expand into a bunch of logical ops. Note that these ops
3824 // depend on the PPC behavior for oversized shift amounts.
3825 SDValue Lo = Op.getOperand(0);
3826 SDValue Hi = Op.getOperand(1);
3827 SDValue Amt = Op.getOperand(2);
3828 EVT AmtVT = Amt.getValueType();
3830 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3831 DAG.getConstant(BitWidth, AmtVT), Amt);
3832 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3833 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3834 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3835 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3836 DAG.getConstant(-BitWidth, AmtVT));
3837 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3838 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3839 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3840 SDValue OutOps[] = { OutLo, OutHi };
3841 return DAG.getMergeValues(OutOps, 2, dl);
3844 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3845 EVT VT = Op.getValueType();
3846 DebugLoc dl = Op.getDebugLoc();
3847 unsigned BitWidth = VT.getSizeInBits();
3848 assert(Op.getNumOperands() == 3 &&
3849 VT == Op.getOperand(1).getValueType() &&
3852 // Expand into a bunch of logical ops. Note that these ops
3853 // depend on the PPC behavior for oversized shift amounts.
3854 SDValue Lo = Op.getOperand(0);
3855 SDValue Hi = Op.getOperand(1);
3856 SDValue Amt = Op.getOperand(2);
3857 EVT AmtVT = Amt.getValueType();
3859 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3860 DAG.getConstant(BitWidth, AmtVT), Amt);
3861 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3862 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3863 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3864 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3865 DAG.getConstant(-BitWidth, AmtVT));
3866 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3867 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3868 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3869 SDValue OutOps[] = { OutLo, OutHi };
3870 return DAG.getMergeValues(OutOps, 2, dl);
3873 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
3874 DebugLoc dl = Op.getDebugLoc();
3875 EVT VT = Op.getValueType();
3876 unsigned BitWidth = VT.getSizeInBits();
3877 assert(Op.getNumOperands() == 3 &&
3878 VT == Op.getOperand(1).getValueType() &&
3881 // Expand into a bunch of logical ops, followed by a select_cc.
3882 SDValue Lo = Op.getOperand(0);
3883 SDValue Hi = Op.getOperand(1);
3884 SDValue Amt = Op.getOperand(2);
3885 EVT AmtVT = Amt.getValueType();
3887 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3888 DAG.getConstant(BitWidth, AmtVT), Amt);
3889 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3890 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3891 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3892 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3893 DAG.getConstant(-BitWidth, AmtVT));
3894 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3895 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3896 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3897 Tmp4, Tmp6, ISD::SETLE);
3898 SDValue OutOps[] = { OutLo, OutHi };
3899 return DAG.getMergeValues(OutOps, 2, dl);
3902 //===----------------------------------------------------------------------===//
3903 // Vector related lowering.
3906 /// BuildSplatI - Build a canonical splati of Val with an element size of
3907 /// SplatSize. Cast the result to VT.
3908 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3909 SelectionDAG &DAG, DebugLoc dl) {
3910 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3912 static const EVT VTys[] = { // canonical VT to use for each size.
3913 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3916 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3918 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3922 EVT CanonicalVT = VTys[SplatSize-1];
3924 // Build a canonical splat for this value.
3925 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3926 SmallVector<SDValue, 8> Ops;
3927 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3928 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3929 &Ops[0], Ops.size());
3930 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
3933 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3934 /// specified intrinsic ID.
3935 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3936 SelectionDAG &DAG, DebugLoc dl,
3937 EVT DestVT = MVT::Other) {
3938 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3939 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3940 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3943 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3944 /// specified intrinsic ID.
3945 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3946 SDValue Op2, SelectionDAG &DAG,
3947 DebugLoc dl, EVT DestVT = MVT::Other) {
3948 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3949 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3950 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3954 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3955 /// amount. The result has the specified value type.
3956 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3957 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3958 // Force LHS/RHS to be the right type.
3959 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
3960 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
3963 for (unsigned i = 0; i != 16; ++i)
3965 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3966 return DAG.getNode(ISD::BITCAST, dl, VT, T);
3969 // If this is a case we can't handle, return null and let the default
3970 // expansion code take care of it. If we CAN select this case, and if it
3971 // selects to a single instruction, return Op. Otherwise, if we can codegen
3972 // this case more efficiently than a constant pool load, lower it to the
3973 // sequence of ops that should be used.
3974 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3975 SelectionDAG &DAG) const {
3976 DebugLoc dl = Op.getDebugLoc();
3977 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3978 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3980 // Check if this is a splat of a constant value.
3981 APInt APSplatBits, APSplatUndef;
3982 unsigned SplatBitSize;
3984 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3985 HasAnyUndefs, 0, true) || SplatBitSize > 32)
3988 unsigned SplatBits = APSplatBits.getZExtValue();
3989 unsigned SplatUndef = APSplatUndef.getZExtValue();
3990 unsigned SplatSize = SplatBitSize / 8;
3992 // First, handle single instruction cases.
3995 if (SplatBits == 0) {
3996 // Canonicalize all zero vectors to be v4i32.
3997 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3998 SDValue Z = DAG.getConstant(0, MVT::i32);
3999 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
4000 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
4005 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
4006 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
4008 if (SextVal >= -16 && SextVal <= 15)
4009 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
4012 // Two instruction sequences.
4014 // If this value is in the range [-32,30] and is even, use:
4015 // tmp = VSPLTI[bhw], result = add tmp, tmp
4016 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
4017 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
4018 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
4019 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4022 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
4023 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
4025 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
4026 // Make -1 and vspltisw -1:
4027 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
4029 // Make the VSLW intrinsic, computing 0x8000_0000.
4030 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
4033 // xor by OnesV to invert it.
4034 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
4035 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4038 // Check to see if this is a wide variety of vsplti*, binop self cases.
4039 static const signed char SplatCsts[] = {
4040 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
4041 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
4044 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
4045 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
4046 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
4047 int i = SplatCsts[idx];
4049 // Figure out what shift amount will be used by altivec if shifted by i in
4051 unsigned TypeShiftAmt = i & (SplatBitSize-1);
4053 // vsplti + shl self.
4054 if (SextVal == (i << (int)TypeShiftAmt)) {
4055 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4056 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4057 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
4058 Intrinsic::ppc_altivec_vslw
4060 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4061 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4064 // vsplti + srl self.
4065 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
4066 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4067 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4068 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
4069 Intrinsic::ppc_altivec_vsrw
4071 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4072 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4075 // vsplti + sra self.
4076 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
4077 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4078 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4079 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
4080 Intrinsic::ppc_altivec_vsraw
4082 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4083 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4086 // vsplti + rol self.
4087 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
4088 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
4089 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4090 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4091 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
4092 Intrinsic::ppc_altivec_vrlw
4094 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4095 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4098 // t = vsplti c, result = vsldoi t, t, 1
4099 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) {
4100 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4101 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
4103 // t = vsplti c, result = vsldoi t, t, 2
4104 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) {
4105 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4106 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
4108 // t = vsplti c, result = vsldoi t, t, 3
4109 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
4110 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4111 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
4115 // Three instruction sequences.
4117 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
4118 if (SextVal >= 0 && SextVal <= 31) {
4119 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
4120 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
4121 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
4122 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
4124 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
4125 if (SextVal >= -31 && SextVal <= 0) {
4126 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
4127 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
4128 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
4129 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
4135 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4136 /// the specified operations to build the shuffle.
4137 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4138 SDValue RHS, SelectionDAG &DAG,
4140 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4141 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4142 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4145 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4157 if (OpNum == OP_COPY) {
4158 if (LHSID == (1*9+2)*9+3) return LHS;
4159 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4163 SDValue OpLHS, OpRHS;
4164 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4165 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4169 default: llvm_unreachable("Unknown i32 permute!");
4171 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
4172 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
4173 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
4174 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
4177 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
4178 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
4179 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
4180 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
4183 for (unsigned i = 0; i != 16; ++i)
4184 ShufIdxs[i] = (i&3)+0;
4187 for (unsigned i = 0; i != 16; ++i)
4188 ShufIdxs[i] = (i&3)+4;
4191 for (unsigned i = 0; i != 16; ++i)
4192 ShufIdxs[i] = (i&3)+8;
4195 for (unsigned i = 0; i != 16; ++i)
4196 ShufIdxs[i] = (i&3)+12;
4199 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4201 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4203 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4205 EVT VT = OpLHS.getValueType();
4206 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
4207 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
4208 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
4209 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4212 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
4213 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
4214 /// return the code it can be lowered into. Worst case, it can always be
4215 /// lowered into a vperm.
4216 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4217 SelectionDAG &DAG) const {
4218 DebugLoc dl = Op.getDebugLoc();
4219 SDValue V1 = Op.getOperand(0);
4220 SDValue V2 = Op.getOperand(1);
4221 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4222 EVT VT = Op.getValueType();
4224 // Cases that are handled by instructions that take permute immediates
4225 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4226 // selected by the instruction selector.
4227 if (V2.getOpcode() == ISD::UNDEF) {
4228 if (PPC::isSplatShuffleMask(SVOp, 1) ||
4229 PPC::isSplatShuffleMask(SVOp, 2) ||
4230 PPC::isSplatShuffleMask(SVOp, 4) ||
4231 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4232 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4233 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4234 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4235 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4236 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4237 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4238 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4239 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4244 // Altivec has a variety of "shuffle immediates" that take two vector inputs
4245 // and produce a fixed permutation. If any of these match, do not lower to
4247 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4248 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4249 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4250 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4251 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4252 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4253 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4254 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4255 PPC::isVMRGHShuffleMask(SVOp, 4, false))
4258 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
4259 // perfect shuffle table to emit an optimal matching sequence.
4260 ArrayRef<int> PermMask = SVOp->getMask();
4262 unsigned PFIndexes[4];
4263 bool isFourElementShuffle = true;
4264 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4265 unsigned EltNo = 8; // Start out undef.
4266 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
4267 if (PermMask[i*4+j] < 0)
4268 continue; // Undef, ignore it.
4270 unsigned ByteSource = PermMask[i*4+j];
4271 if ((ByteSource & 3) != j) {
4272 isFourElementShuffle = false;
4277 EltNo = ByteSource/4;
4278 } else if (EltNo != ByteSource/4) {
4279 isFourElementShuffle = false;
4283 PFIndexes[i] = EltNo;
4286 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4287 // perfect shuffle vector to determine if it is cost effective to do this as
4288 // discrete instructions, or whether we should use a vperm.
4289 if (isFourElementShuffle) {
4290 // Compute the index in the perfect shuffle table.
4291 unsigned PFTableIndex =
4292 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4294 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4295 unsigned Cost = (PFEntry >> 30);
4297 // Determining when to avoid vperm is tricky. Many things affect the cost
4298 // of vperm, particularly how many times the perm mask needs to be computed.
4299 // For example, if the perm mask can be hoisted out of a loop or is already
4300 // used (perhaps because there are multiple permutes with the same shuffle
4301 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
4302 // the loop requires an extra register.
4304 // As a compromise, we only emit discrete instructions if the shuffle can be
4305 // generated in 3 or fewer operations. When we have loop information
4306 // available, if this block is within a loop, we should avoid using vperm
4307 // for 3-operation perms and use a constant pool load instead.
4309 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4312 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4313 // vector that will get spilled to the constant pool.
4314 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4316 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4317 // that it is in input element units, not in bytes. Convert now.
4318 EVT EltVT = V1.getValueType().getVectorElementType();
4319 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4321 SmallVector<SDValue, 16> ResultMask;
4322 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4323 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4325 for (unsigned j = 0; j != BytesPerElement; ++j)
4326 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4330 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4331 &ResultMask[0], ResultMask.size());
4332 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4335 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4336 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4337 /// information about the intrinsic.
4338 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4340 unsigned IntrinsicID =
4341 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4344 switch (IntrinsicID) {
4345 default: return false;
4346 // Comparison predicates.
4347 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4348 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4349 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4350 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4351 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4352 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4353 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4354 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4355 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4356 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4357 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4358 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4359 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4361 // Normal Comparisons.
4362 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4363 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4364 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4365 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4366 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4367 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4368 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4369 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4370 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4371 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4372 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4373 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4374 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4379 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4380 /// lower, do it, otherwise return null.
4381 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4382 SelectionDAG &DAG) const {
4383 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4384 // opcode number of the comparison.
4385 DebugLoc dl = Op.getDebugLoc();
4388 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4389 return SDValue(); // Don't custom lower most intrinsics.
4391 // If this is a non-dot comparison, make the VCMP node and we are done.
4393 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4394 Op.getOperand(1), Op.getOperand(2),
4395 DAG.getConstant(CompareOpc, MVT::i32));
4396 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
4399 // Create the PPCISD altivec 'dot' comparison node.
4401 Op.getOperand(2), // LHS
4402 Op.getOperand(3), // RHS
4403 DAG.getConstant(CompareOpc, MVT::i32)
4405 std::vector<EVT> VTs;
4406 VTs.push_back(Op.getOperand(2).getValueType());
4407 VTs.push_back(MVT::Glue);
4408 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4410 // Now that we have the comparison, emit a copy from the CR to a GPR.
4411 // This is flagged to the above dot comparison.
4412 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4413 DAG.getRegister(PPC::CR6, MVT::i32),
4414 CompNode.getValue(1));
4416 // Unpack the result based on how the target uses it.
4417 unsigned BitNo; // Bit # of CR6.
4418 bool InvertBit; // Invert result?
4419 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4420 default: // Can't happen, don't crash on invalid number though.
4421 case 0: // Return the value of the EQ bit of CR6.
4422 BitNo = 0; InvertBit = false;
4424 case 1: // Return the inverted value of the EQ bit of CR6.
4425 BitNo = 0; InvertBit = true;
4427 case 2: // Return the value of the LT bit of CR6.
4428 BitNo = 2; InvertBit = false;
4430 case 3: // Return the inverted value of the LT bit of CR6.
4431 BitNo = 2; InvertBit = true;
4435 // Shift the bit into the low position.
4436 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4437 DAG.getConstant(8-(3-BitNo), MVT::i32));
4439 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4440 DAG.getConstant(1, MVT::i32));
4442 // If we are supposed to, toggle the bit.
4444 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4445 DAG.getConstant(1, MVT::i32));
4449 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4450 SelectionDAG &DAG) const {
4451 DebugLoc dl = Op.getDebugLoc();
4452 // Create a stack slot that is 16-byte aligned.
4453 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4454 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4455 EVT PtrVT = getPointerTy();
4456 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4458 // Store the input value into Value#0 of the stack slot.
4459 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4460 Op.getOperand(0), FIdx, MachinePointerInfo(),
4463 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
4464 false, false, false, 0);
4467 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
4468 DebugLoc dl = Op.getDebugLoc();
4469 if (Op.getValueType() == MVT::v4i32) {
4470 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4472 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4473 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4475 SDValue RHSSwap = // = vrlw RHS, 16
4476 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4478 // Shrinkify inputs to v8i16.
4479 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
4480 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
4481 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
4483 // Low parts multiplied together, generating 32-bit results (we ignore the
4485 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4486 LHS, RHS, DAG, dl, MVT::v4i32);
4488 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4489 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4490 // Shift the high parts up 16 bits.
4491 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4493 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4494 } else if (Op.getValueType() == MVT::v8i16) {
4495 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4497 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4499 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4500 LHS, RHS, Zero, DAG, dl);
4501 } else if (Op.getValueType() == MVT::v16i8) {
4502 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4504 // Multiply the even 8-bit parts, producing 16-bit sums.
4505 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4506 LHS, RHS, DAG, dl, MVT::v8i16);
4507 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
4509 // Multiply the odd 8-bit parts, producing 16-bit sums.
4510 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4511 LHS, RHS, DAG, dl, MVT::v8i16);
4512 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
4514 // Merge the results together.
4516 for (unsigned i = 0; i != 8; ++i) {
4518 Ops[i*2+1] = 2*i+1+16;
4520 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4522 llvm_unreachable("Unknown mul to lower!");
4526 /// LowerOperation - Provide custom lowering hooks for some operations.
4528 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4529 switch (Op.getOpcode()) {
4530 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4531 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4532 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4533 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4534 case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for PPC");
4535 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4536 case ISD::SETCC: return LowerSETCC(Op, DAG);
4537 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
4538 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
4540 return LowerVASTART(Op, DAG, PPCSubTarget);
4543 return LowerVAARG(Op, DAG, PPCSubTarget);
4545 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4546 case ISD::DYNAMIC_STACKALLOC:
4547 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4549 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4550 case ISD::FP_TO_UINT:
4551 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4553 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4554 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4556 // Lower 64-bit shifts.
4557 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4558 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4559 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4561 // Vector-related lowering.
4562 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4563 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4564 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4565 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4566 case ISD::MUL: return LowerMUL(Op, DAG);
4568 // Frame & Return address.
4569 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4570 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4574 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4575 SmallVectorImpl<SDValue>&Results,
4576 SelectionDAG &DAG) const {
4577 const TargetMachine &TM = getTargetMachine();
4578 DebugLoc dl = N->getDebugLoc();
4579 switch (N->getOpcode()) {
4581 llvm_unreachable("Do not know how to custom type legalize this operation!");
4583 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
4584 || TM.getSubtarget<PPCSubtarget>().isPPC64())
4587 EVT VT = N->getValueType(0);
4589 if (VT == MVT::i64) {
4590 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
4592 Results.push_back(NewNode);
4593 Results.push_back(NewNode.getValue(1));
4597 case ISD::FP_ROUND_INREG: {
4598 assert(N->getValueType(0) == MVT::ppcf128);
4599 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4600 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4601 MVT::f64, N->getOperand(0),
4602 DAG.getIntPtrConstant(0));
4603 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4604 MVT::f64, N->getOperand(0),
4605 DAG.getIntPtrConstant(1));
4607 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4608 // of the long double, and puts FPSCR back the way it was. We do not
4609 // actually model FPSCR.
4610 std::vector<EVT> NodeTys;
4611 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4613 NodeTys.push_back(MVT::f64); // Return register
4614 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns
4615 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4616 MFFSreg = Result.getValue(0);
4617 InFlag = Result.getValue(1);
4620 NodeTys.push_back(MVT::Glue); // Returns a flag
4621 Ops[0] = DAG.getConstant(31, MVT::i32);
4623 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4624 InFlag = Result.getValue(0);
4627 NodeTys.push_back(MVT::Glue); // Returns a flag
4628 Ops[0] = DAG.getConstant(30, MVT::i32);
4630 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4631 InFlag = Result.getValue(0);
4634 NodeTys.push_back(MVT::f64); // result of add
4635 NodeTys.push_back(MVT::Glue); // Returns a flag
4639 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4640 FPreg = Result.getValue(0);
4641 InFlag = Result.getValue(1);
4644 NodeTys.push_back(MVT::f64);
4645 Ops[0] = DAG.getConstant(1, MVT::i32);
4649 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4650 FPreg = Result.getValue(0);
4652 // We know the low half is about to be thrown away, so just use something
4654 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4658 case ISD::FP_TO_SINT:
4659 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4665 //===----------------------------------------------------------------------===//
4666 // Other Lowering Code
4667 //===----------------------------------------------------------------------===//
4670 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4671 bool is64bit, unsigned BinOpcode) const {
4672 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4673 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4675 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4676 MachineFunction *F = BB->getParent();
4677 MachineFunction::iterator It = BB;
4680 unsigned dest = MI->getOperand(0).getReg();
4681 unsigned ptrA = MI->getOperand(1).getReg();
4682 unsigned ptrB = MI->getOperand(2).getReg();
4683 unsigned incr = MI->getOperand(3).getReg();
4684 DebugLoc dl = MI->getDebugLoc();
4686 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4687 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4688 F->insert(It, loopMBB);
4689 F->insert(It, exitMBB);
4690 exitMBB->splice(exitMBB->begin(), BB,
4691 llvm::next(MachineBasicBlock::iterator(MI)),
4693 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4695 MachineRegisterInfo &RegInfo = F->getRegInfo();
4696 unsigned TmpReg = (!BinOpcode) ? incr :
4697 RegInfo.createVirtualRegister(
4698 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4699 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4703 // fallthrough --> loopMBB
4704 BB->addSuccessor(loopMBB);
4707 // l[wd]arx dest, ptr
4708 // add r0, dest, incr
4709 // st[wd]cx. r0, ptr
4711 // fallthrough --> exitMBB
4713 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4714 .addReg(ptrA).addReg(ptrB);
4716 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4717 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4718 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4719 BuildMI(BB, dl, TII->get(PPC::BCC))
4720 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4721 BB->addSuccessor(loopMBB);
4722 BB->addSuccessor(exitMBB);
4731 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4732 MachineBasicBlock *BB,
4733 bool is8bit, // operation
4734 unsigned BinOpcode) const {
4735 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4736 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4737 // In 64 bit mode we have to use 64 bits for addresses, even though the
4738 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4739 // registers without caring whether they're 32 or 64, but here we're
4740 // doing actual arithmetic on the addresses.
4741 bool is64bit = PPCSubTarget.isPPC64();
4742 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
4744 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4745 MachineFunction *F = BB->getParent();
4746 MachineFunction::iterator It = BB;
4749 unsigned dest = MI->getOperand(0).getReg();
4750 unsigned ptrA = MI->getOperand(1).getReg();
4751 unsigned ptrB = MI->getOperand(2).getReg();
4752 unsigned incr = MI->getOperand(3).getReg();
4753 DebugLoc dl = MI->getDebugLoc();
4755 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4756 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4757 F->insert(It, loopMBB);
4758 F->insert(It, exitMBB);
4759 exitMBB->splice(exitMBB->begin(), BB,
4760 llvm::next(MachineBasicBlock::iterator(MI)),
4762 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4764 MachineRegisterInfo &RegInfo = F->getRegInfo();
4765 const TargetRegisterClass *RC =
4766 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4767 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4768 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4769 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4770 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4771 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4772 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4773 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4774 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4775 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4776 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4777 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4778 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4780 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4784 // fallthrough --> loopMBB
4785 BB->addSuccessor(loopMBB);
4787 // The 4-byte load must be aligned, while a char or short may be
4788 // anywhere in the word. Hence all this nasty bookkeeping code.
4789 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4790 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4791 // xori shift, shift1, 24 [16]
4792 // rlwinm ptr, ptr1, 0, 0, 29
4793 // slw incr2, incr, shift
4794 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4795 // slw mask, mask2, shift
4797 // lwarx tmpDest, ptr
4798 // add tmp, tmpDest, incr2
4799 // andc tmp2, tmpDest, mask
4800 // and tmp3, tmp, mask
4801 // or tmp4, tmp3, tmp2
4804 // fallthrough --> exitMBB
4805 // srw dest, tmpDest, shift
4806 if (ptrA != ZeroReg) {
4807 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4808 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4809 .addReg(ptrA).addReg(ptrB);
4813 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4814 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4815 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4816 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4818 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4819 .addReg(Ptr1Reg).addImm(0).addImm(61);
4821 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4822 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4823 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4824 .addReg(incr).addReg(ShiftReg);
4826 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4828 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4829 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4831 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4832 .addReg(Mask2Reg).addReg(ShiftReg);
4835 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4836 .addReg(ZeroReg).addReg(PtrReg);
4838 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4839 .addReg(Incr2Reg).addReg(TmpDestReg);
4840 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4841 .addReg(TmpDestReg).addReg(MaskReg);
4842 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4843 .addReg(TmpReg).addReg(MaskReg);
4844 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4845 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4846 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4847 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
4848 BuildMI(BB, dl, TII->get(PPC::BCC))
4849 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4850 BB->addSuccessor(loopMBB);
4851 BB->addSuccessor(exitMBB);
4856 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
4862 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4863 MachineBasicBlock *BB) const {
4864 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4866 // To "insert" these instructions we actually have to insert their
4867 // control-flow patterns.
4868 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4869 MachineFunction::iterator It = BB;
4872 MachineFunction *F = BB->getParent();
4874 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4875 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4876 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4877 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4878 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4880 // The incoming instruction knows the destination vreg to set, the
4881 // condition code register to branch on, the true/false values to
4882 // select between, and a branch opcode to use.
4887 // cmpTY ccX, r1, r2
4889 // fallthrough --> copy0MBB
4890 MachineBasicBlock *thisMBB = BB;
4891 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4892 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4893 unsigned SelectPred = MI->getOperand(4).getImm();
4894 DebugLoc dl = MI->getDebugLoc();
4895 F->insert(It, copy0MBB);
4896 F->insert(It, sinkMBB);
4898 // Transfer the remainder of BB and its successor edges to sinkMBB.
4899 sinkMBB->splice(sinkMBB->begin(), BB,
4900 llvm::next(MachineBasicBlock::iterator(MI)),
4902 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4904 // Next, add the true and fallthrough blocks as its successors.
4905 BB->addSuccessor(copy0MBB);
4906 BB->addSuccessor(sinkMBB);
4908 BuildMI(BB, dl, TII->get(PPC::BCC))
4909 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4912 // %FalseValue = ...
4913 // # fallthrough to sinkMBB
4916 // Update machine-CFG edges
4917 BB->addSuccessor(sinkMBB);
4920 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4923 BuildMI(*BB, BB->begin(), dl,
4924 TII->get(PPC::PHI), MI->getOperand(0).getReg())
4925 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4926 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4928 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4929 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4930 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4931 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4932 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4933 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4934 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4935 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4937 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4938 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4939 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4940 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4941 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4942 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4943 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4944 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4946 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4947 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4948 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4949 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4950 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4951 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4952 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4953 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4955 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4956 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4957 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4958 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4959 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4960 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4961 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4962 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4964 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4965 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4966 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4967 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4968 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4969 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4970 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4971 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4973 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4974 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4975 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4976 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4977 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4978 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4979 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4980 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4982 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4983 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4984 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4985 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4986 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4987 BB = EmitAtomicBinary(MI, BB, false, 0);
4988 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4989 BB = EmitAtomicBinary(MI, BB, true, 0);
4991 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4992 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4993 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4995 unsigned dest = MI->getOperand(0).getReg();
4996 unsigned ptrA = MI->getOperand(1).getReg();
4997 unsigned ptrB = MI->getOperand(2).getReg();
4998 unsigned oldval = MI->getOperand(3).getReg();
4999 unsigned newval = MI->getOperand(4).getReg();
5000 DebugLoc dl = MI->getDebugLoc();
5002 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
5003 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
5004 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
5005 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5006 F->insert(It, loop1MBB);
5007 F->insert(It, loop2MBB);
5008 F->insert(It, midMBB);
5009 F->insert(It, exitMBB);
5010 exitMBB->splice(exitMBB->begin(), BB,
5011 llvm::next(MachineBasicBlock::iterator(MI)),
5013 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5017 // fallthrough --> loopMBB
5018 BB->addSuccessor(loop1MBB);
5021 // l[wd]arx dest, ptr
5022 // cmp[wd] dest, oldval
5025 // st[wd]cx. newval, ptr
5029 // st[wd]cx. dest, ptr
5032 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5033 .addReg(ptrA).addReg(ptrB);
5034 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
5035 .addReg(oldval).addReg(dest);
5036 BuildMI(BB, dl, TII->get(PPC::BCC))
5037 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5038 BB->addSuccessor(loop2MBB);
5039 BB->addSuccessor(midMBB);
5042 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5043 .addReg(newval).addReg(ptrA).addReg(ptrB);
5044 BuildMI(BB, dl, TII->get(PPC::BCC))
5045 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5046 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5047 BB->addSuccessor(loop1MBB);
5048 BB->addSuccessor(exitMBB);
5051 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5052 .addReg(dest).addReg(ptrA).addReg(ptrB);
5053 BB->addSuccessor(exitMBB);
5058 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
5059 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
5060 // We must use 64-bit registers for addresses when targeting 64-bit,
5061 // since we're actually doing arithmetic on them. Other registers
5063 bool is64bit = PPCSubTarget.isPPC64();
5064 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
5066 unsigned dest = MI->getOperand(0).getReg();
5067 unsigned ptrA = MI->getOperand(1).getReg();
5068 unsigned ptrB = MI->getOperand(2).getReg();
5069 unsigned oldval = MI->getOperand(3).getReg();
5070 unsigned newval = MI->getOperand(4).getReg();
5071 DebugLoc dl = MI->getDebugLoc();
5073 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
5074 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
5075 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
5076 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5077 F->insert(It, loop1MBB);
5078 F->insert(It, loop2MBB);
5079 F->insert(It, midMBB);
5080 F->insert(It, exitMBB);
5081 exitMBB->splice(exitMBB->begin(), BB,
5082 llvm::next(MachineBasicBlock::iterator(MI)),
5084 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5086 MachineRegisterInfo &RegInfo = F->getRegInfo();
5087 const TargetRegisterClass *RC =
5088 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5089 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5090 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5091 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5092 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5093 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
5094 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
5095 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
5096 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
5097 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5098 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5099 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5100 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5101 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5102 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5104 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
5105 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
5108 // fallthrough --> loopMBB
5109 BB->addSuccessor(loop1MBB);
5111 // The 4-byte load must be aligned, while a char or short may be
5112 // anywhere in the word. Hence all this nasty bookkeeping code.
5113 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5114 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5115 // xori shift, shift1, 24 [16]
5116 // rlwinm ptr, ptr1, 0, 0, 29
5117 // slw newval2, newval, shift
5118 // slw oldval2, oldval,shift
5119 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5120 // slw mask, mask2, shift
5121 // and newval3, newval2, mask
5122 // and oldval3, oldval2, mask
5124 // lwarx tmpDest, ptr
5125 // and tmp, tmpDest, mask
5126 // cmpw tmp, oldval3
5129 // andc tmp2, tmpDest, mask
5130 // or tmp4, tmp2, newval3
5135 // stwcx. tmpDest, ptr
5137 // srw dest, tmpDest, shift
5138 if (ptrA != ZeroReg) {
5139 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5140 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5141 .addReg(ptrA).addReg(ptrB);
5145 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5146 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5147 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5148 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5150 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5151 .addReg(Ptr1Reg).addImm(0).addImm(61);
5153 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5154 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5155 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
5156 .addReg(newval).addReg(ShiftReg);
5157 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
5158 .addReg(oldval).addReg(ShiftReg);
5160 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5162 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5163 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
5164 .addReg(Mask3Reg).addImm(65535);
5166 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5167 .addReg(Mask2Reg).addReg(ShiftReg);
5168 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
5169 .addReg(NewVal2Reg).addReg(MaskReg);
5170 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
5171 .addReg(OldVal2Reg).addReg(MaskReg);
5174 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5175 .addReg(ZeroReg).addReg(PtrReg);
5176 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
5177 .addReg(TmpDestReg).addReg(MaskReg);
5178 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
5179 .addReg(TmpReg).addReg(OldVal3Reg);
5180 BuildMI(BB, dl, TII->get(PPC::BCC))
5181 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5182 BB->addSuccessor(loop2MBB);
5183 BB->addSuccessor(midMBB);
5186 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
5187 .addReg(TmpDestReg).addReg(MaskReg);
5188 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
5189 .addReg(Tmp2Reg).addReg(NewVal3Reg);
5190 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
5191 .addReg(ZeroReg).addReg(PtrReg);
5192 BuildMI(BB, dl, TII->get(PPC::BCC))
5193 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5194 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5195 BB->addSuccessor(loop1MBB);
5196 BB->addSuccessor(exitMBB);
5199 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
5200 .addReg(ZeroReg).addReg(PtrReg);
5201 BB->addSuccessor(exitMBB);
5206 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
5209 llvm_unreachable("Unexpected instr type to insert");
5212 MI->eraseFromParent(); // The pseudo instruction is gone now.
5216 //===----------------------------------------------------------------------===//
5217 // Target Optimization Hooks
5218 //===----------------------------------------------------------------------===//
5220 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
5221 DAGCombinerInfo &DCI) const {
5222 const TargetMachine &TM = getTargetMachine();
5223 SelectionDAG &DAG = DCI.DAG;
5224 DebugLoc dl = N->getDebugLoc();
5225 switch (N->getOpcode()) {
5228 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5229 if (C->isNullValue()) // 0 << V -> 0.
5230 return N->getOperand(0);
5234 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5235 if (C->isNullValue()) // 0 >>u V -> 0.
5236 return N->getOperand(0);
5240 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5241 if (C->isNullValue() || // 0 >>s V -> 0.
5242 C->isAllOnesValue()) // -1 >>s V -> -1.
5243 return N->getOperand(0);
5247 case ISD::SINT_TO_FP:
5248 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5249 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5250 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5251 // We allow the src/dst to be either f32/f64, but the intermediate
5252 // type must be i64.
5253 if (N->getOperand(0).getValueType() == MVT::i64 &&
5254 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5255 SDValue Val = N->getOperand(0).getOperand(0);
5256 if (Val.getValueType() == MVT::f32) {
5257 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5258 DCI.AddToWorklist(Val.getNode());
5261 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5262 DCI.AddToWorklist(Val.getNode());
5263 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5264 DCI.AddToWorklist(Val.getNode());
5265 if (N->getValueType(0) == MVT::f32) {
5266 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5267 DAG.getIntPtrConstant(0));
5268 DCI.AddToWorklist(Val.getNode());
5271 } else if (N->getOperand(0).getValueType() == MVT::i32) {
5272 // If the intermediate type is i32, we can avoid the load/store here
5279 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5280 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5281 !cast<StoreSDNode>(N)->isTruncatingStore() &&
5282 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5283 N->getOperand(1).getValueType() == MVT::i32 &&
5284 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5285 SDValue Val = N->getOperand(1).getOperand(0);
5286 if (Val.getValueType() == MVT::f32) {
5287 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5288 DCI.AddToWorklist(Val.getNode());
5290 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5291 DCI.AddToWorklist(Val.getNode());
5293 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5294 N->getOperand(2), N->getOperand(3));
5295 DCI.AddToWorklist(Val.getNode());
5299 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
5300 if (cast<StoreSDNode>(N)->isUnindexed() &&
5301 N->getOperand(1).getOpcode() == ISD::BSWAP &&
5302 N->getOperand(1).getNode()->hasOneUse() &&
5303 (N->getOperand(1).getValueType() == MVT::i32 ||
5304 N->getOperand(1).getValueType() == MVT::i16)) {
5305 SDValue BSwapOp = N->getOperand(1).getOperand(0);
5306 // Do an any-extend to 32-bits if this is a half-word input.
5307 if (BSwapOp.getValueType() == MVT::i16)
5308 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5311 N->getOperand(0), BSwapOp, N->getOperand(2),
5312 DAG.getValueType(N->getOperand(1).getValueType())
5315 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5316 Ops, array_lengthof(Ops),
5317 cast<StoreSDNode>(N)->getMemoryVT(),
5318 cast<StoreSDNode>(N)->getMemOperand());
5322 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5323 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5324 N->getOperand(0).hasOneUse() &&
5325 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5326 SDValue Load = N->getOperand(0);
5327 LoadSDNode *LD = cast<LoadSDNode>(Load);
5328 // Create the byte-swapping load.
5330 LD->getChain(), // Chain
5331 LD->getBasePtr(), // Ptr
5332 DAG.getValueType(N->getValueType(0)) // VT
5335 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5336 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5337 LD->getMemoryVT(), LD->getMemOperand());
5339 // If this is an i16 load, insert the truncate.
5340 SDValue ResVal = BSLoad;
5341 if (N->getValueType(0) == MVT::i16)
5342 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5344 // First, combine the bswap away. This makes the value produced by the
5346 DCI.CombineTo(N, ResVal);
5348 // Next, combine the load away, we give it a bogus result value but a real
5349 // chain result. The result value is dead because the bswap is dead.
5350 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5352 // Return N so it doesn't get rechecked!
5353 return SDValue(N, 0);
5357 case PPCISD::VCMP: {
5358 // If a VCMPo node already exists with exactly the same operands as this
5359 // node, use its result instead of this node (VCMPo computes both a CR6 and
5360 // a normal output).
5362 if (!N->getOperand(0).hasOneUse() &&
5363 !N->getOperand(1).hasOneUse() &&
5364 !N->getOperand(2).hasOneUse()) {
5366 // Scan all of the users of the LHS, looking for VCMPo's that match.
5367 SDNode *VCMPoNode = 0;
5369 SDNode *LHSN = N->getOperand(0).getNode();
5370 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5372 if (UI->getOpcode() == PPCISD::VCMPo &&
5373 UI->getOperand(1) == N->getOperand(1) &&
5374 UI->getOperand(2) == N->getOperand(2) &&
5375 UI->getOperand(0) == N->getOperand(0)) {
5380 // If there is no VCMPo node, or if the flag value has a single use, don't
5382 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5385 // Look at the (necessarily single) use of the flag value. If it has a
5386 // chain, this transformation is more complex. Note that multiple things
5387 // could use the value result, which we should ignore.
5388 SDNode *FlagUser = 0;
5389 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5390 FlagUser == 0; ++UI) {
5391 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5393 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5394 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5401 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5402 // give up for right now.
5403 if (FlagUser->getOpcode() == PPCISD::MFCR)
5404 return SDValue(VCMPoNode, 0);
5409 // If this is a branch on an altivec predicate comparison, lower this so
5410 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5411 // lowering is done pre-legalize, because the legalizer lowers the predicate
5412 // compare down to code that is difficult to reassemble.
5413 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5414 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5418 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5419 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5420 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5421 assert(isDot && "Can't compare against a vector result!");
5423 // If this is a comparison against something other than 0/1, then we know
5424 // that the condition is never/always true.
5425 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5426 if (Val != 0 && Val != 1) {
5427 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5428 return N->getOperand(0);
5429 // Always !=, turn it into an unconditional branch.
5430 return DAG.getNode(ISD::BR, dl, MVT::Other,
5431 N->getOperand(0), N->getOperand(4));
5434 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5436 // Create the PPCISD altivec 'dot' comparison node.
5437 std::vector<EVT> VTs;
5439 LHS.getOperand(2), // LHS of compare
5440 LHS.getOperand(3), // RHS of compare
5441 DAG.getConstant(CompareOpc, MVT::i32)
5443 VTs.push_back(LHS.getOperand(2).getValueType());
5444 VTs.push_back(MVT::Glue);
5445 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5447 // Unpack the result based on how the target uses it.
5448 PPC::Predicate CompOpc;
5449 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5450 default: // Can't happen, don't crash on invalid number though.
5451 case 0: // Branch on the value of the EQ bit of CR6.
5452 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5454 case 1: // Branch on the inverted value of the EQ bit of CR6.
5455 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5457 case 2: // Branch on the value of the LT bit of CR6.
5458 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5460 case 3: // Branch on the inverted value of the LT bit of CR6.
5461 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5465 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5466 DAG.getConstant(CompOpc, MVT::i32),
5467 DAG.getRegister(PPC::CR6, MVT::i32),
5468 N->getOperand(4), CompNode.getValue(1));
5477 //===----------------------------------------------------------------------===//
5478 // Inline Assembly Support
5479 //===----------------------------------------------------------------------===//
5481 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5485 const SelectionDAG &DAG,
5486 unsigned Depth) const {
5487 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5488 switch (Op.getOpcode()) {
5490 case PPCISD::LBRX: {
5491 // lhbrx is known to have the top bits cleared out.
5492 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5493 KnownZero = 0xFFFF0000;
5496 case ISD::INTRINSIC_WO_CHAIN: {
5497 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5499 case Intrinsic::ppc_altivec_vcmpbfp_p:
5500 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5501 case Intrinsic::ppc_altivec_vcmpequb_p:
5502 case Intrinsic::ppc_altivec_vcmpequh_p:
5503 case Intrinsic::ppc_altivec_vcmpequw_p:
5504 case Intrinsic::ppc_altivec_vcmpgefp_p:
5505 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5506 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5507 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5508 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5509 case Intrinsic::ppc_altivec_vcmpgtub_p:
5510 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5511 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5512 KnownZero = ~1U; // All bits but the low one are known to be zero.
5520 /// getConstraintType - Given a constraint, return the type of
5521 /// constraint it is for this target.
5522 PPCTargetLowering::ConstraintType
5523 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5524 if (Constraint.size() == 1) {
5525 switch (Constraint[0]) {
5532 return C_RegisterClass;
5535 return TargetLowering::getConstraintType(Constraint);
5538 /// Examine constraint type and operand type and determine a weight value.
5539 /// This object must already have been set up with the operand type
5540 /// and the current alternative constraint selected.
5541 TargetLowering::ConstraintWeight
5542 PPCTargetLowering::getSingleConstraintMatchWeight(
5543 AsmOperandInfo &info, const char *constraint) const {
5544 ConstraintWeight weight = CW_Invalid;
5545 Value *CallOperandVal = info.CallOperandVal;
5546 // If we don't have a value, we can't do a match,
5547 // but allow it at the lowest weight.
5548 if (CallOperandVal == NULL)
5550 Type *type = CallOperandVal->getType();
5551 // Look at the constraint type.
5552 switch (*constraint) {
5554 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5557 if (type->isIntegerTy())
5558 weight = CW_Register;
5561 if (type->isFloatTy())
5562 weight = CW_Register;
5565 if (type->isDoubleTy())
5566 weight = CW_Register;
5569 if (type->isVectorTy())
5570 weight = CW_Register;
5573 weight = CW_Register;
5579 std::pair<unsigned, const TargetRegisterClass*>
5580 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5582 if (Constraint.size() == 1) {
5583 // GCC RS6000 Constraint Letters
5584 switch (Constraint[0]) {
5587 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5588 return std::make_pair(0U, PPC::G8RCRegisterClass);
5589 return std::make_pair(0U, PPC::GPRCRegisterClass);
5592 return std::make_pair(0U, PPC::F4RCRegisterClass);
5593 else if (VT == MVT::f64)
5594 return std::make_pair(0U, PPC::F8RCRegisterClass);
5597 return std::make_pair(0U, PPC::VRRCRegisterClass);
5599 return std::make_pair(0U, PPC::CRRCRegisterClass);
5603 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5607 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5608 /// vector. If it is invalid, don't add anything to Ops.
5609 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5610 std::string &Constraint,
5611 std::vector<SDValue>&Ops,
5612 SelectionDAG &DAG) const {
5613 SDValue Result(0,0);
5615 // Only support length 1 constraints.
5616 if (Constraint.length() > 1) return;
5618 char Letter = Constraint[0];
5629 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5630 if (!CST) return; // Must be an immediate to match.
5631 unsigned Value = CST->getZExtValue();
5633 default: llvm_unreachable("Unknown constraint letter!");
5634 case 'I': // "I" is a signed 16-bit constant.
5635 if ((short)Value == (int)Value)
5636 Result = DAG.getTargetConstant(Value, Op.getValueType());
5638 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5639 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5640 if ((short)Value == 0)
5641 Result = DAG.getTargetConstant(Value, Op.getValueType());
5643 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5644 if ((Value >> 16) == 0)
5645 Result = DAG.getTargetConstant(Value, Op.getValueType());
5647 case 'M': // "M" is a constant that is greater than 31.
5649 Result = DAG.getTargetConstant(Value, Op.getValueType());
5651 case 'N': // "N" is a positive constant that is an exact power of two.
5652 if ((int)Value > 0 && isPowerOf2_32(Value))
5653 Result = DAG.getTargetConstant(Value, Op.getValueType());
5655 case 'O': // "O" is the constant zero.
5657 Result = DAG.getTargetConstant(Value, Op.getValueType());
5659 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5660 if ((short)-Value == (int)-Value)
5661 Result = DAG.getTargetConstant(Value, Op.getValueType());
5668 if (Result.getNode()) {
5669 Ops.push_back(Result);
5673 // Handle standard constraint letters.
5674 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5677 // isLegalAddressingMode - Return true if the addressing mode represented
5678 // by AM is legal for this target, for a load/store of the specified type.
5679 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5681 // FIXME: PPC does not allow r+i addressing modes for vectors!
5683 // PPC allows a sign-extended 16-bit immediate field.
5684 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5687 // No global is ever allowed as a base.
5691 // PPC only support r+r,
5693 case 0: // "r+i" or just "i", depending on HasBaseReg.
5696 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5698 // Otherwise we have r+r or r+i.
5701 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5703 // Allow 2*r as r+r.
5706 // No other scales are supported.
5713 /// isLegalAddressImmediate - Return true if the integer value can be used
5714 /// as the offset of the target addressing mode for load / store of the
5716 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
5717 // PPC allows a sign-extended 16-bit immediate field.
5718 return (V > -(1 << 16) && V < (1 << 16)-1);
5721 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5725 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
5726 SelectionDAG &DAG) const {
5727 MachineFunction &MF = DAG.getMachineFunction();
5728 MachineFrameInfo *MFI = MF.getFrameInfo();
5729 MFI->setReturnAddressIsTaken(true);
5731 DebugLoc dl = Op.getDebugLoc();
5732 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5734 // Make sure the function does not optimize away the store of the RA to
5736 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5737 FuncInfo->setLRStoreRequired();
5738 bool isPPC64 = PPCSubTarget.isPPC64();
5739 bool isDarwinABI = PPCSubTarget.isDarwinABI();
5742 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5745 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
5746 isPPC64? MVT::i64 : MVT::i32);
5747 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5748 DAG.getNode(ISD::ADD, dl, getPointerTy(),
5750 MachinePointerInfo(), false, false, false, 0);
5753 // Just load the return address off the stack.
5754 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5755 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5756 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
5759 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
5760 SelectionDAG &DAG) const {
5761 DebugLoc dl = Op.getDebugLoc();
5762 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5764 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5765 bool isPPC64 = PtrVT == MVT::i64;
5767 MachineFunction &MF = DAG.getMachineFunction();
5768 MachineFrameInfo *MFI = MF.getFrameInfo();
5769 MFI->setFrameAddressIsTaken(true);
5770 bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) ||
5771 MFI->hasVarSizedObjects()) &&
5772 MFI->getStackSize() &&
5773 !MF.getFunction()->hasFnAttr(Attribute::Naked);
5774 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
5775 (is31 ? PPC::R31 : PPC::R1);
5776 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
5779 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
5780 FrameAddr, MachinePointerInfo(), false, false,
5786 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5787 // The PowerPC target isn't yet aware of offsets.
5791 /// getOptimalMemOpType - Returns the target specific optimal type for load
5792 /// and store operations as a result of memset, memcpy, and memmove
5793 /// lowering. If DstAlign is zero that means it's safe to destination
5794 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
5795 /// means there isn't a need to check it against alignment requirement,
5796 /// probably because the source does not need to be loaded. If
5797 /// 'IsZeroVal' is true, that means it's safe to return a
5798 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
5799 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
5800 /// constant so it does not need to be loaded.
5801 /// It returns EVT::Other if the type should be determined using generic
5802 /// target-independent logic.
5803 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
5804 unsigned DstAlign, unsigned SrcAlign,
5807 MachineFunction &MF) const {
5808 if (this->PPCSubTarget.isPPC64()) {