1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/DerivedTypes.h"
41 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
42 CCValAssign::LocInfo &LocInfo,
43 ISD::ArgFlagsTy &ArgFlags,
45 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
56 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
57 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
63 return new TargetLoweringObjectFileELF();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
78 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
79 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
81 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
85 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
87 // PowerPC has pre-inc load and store's.
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 // This is used in the ppcf128->int sequence. Note it has different semantics
100 // from FP_ROUND: that rounds to nearest, this rounds to zero.
101 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
103 // PowerPC has no SREM/UREM instructions
104 setOperationAction(ISD::SREM, MVT::i32, Expand);
105 setOperationAction(ISD::UREM, MVT::i32, Expand);
106 setOperationAction(ISD::SREM, MVT::i64, Expand);
107 setOperationAction(ISD::UREM, MVT::i64, Expand);
109 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
110 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
112 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
113 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
114 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
115 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
116 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
119 // We don't support sin/cos/sqrt/fmod/pow
120 setOperationAction(ISD::FSIN , MVT::f64, Expand);
121 setOperationAction(ISD::FCOS , MVT::f64, Expand);
122 setOperationAction(ISD::FREM , MVT::f64, Expand);
123 setOperationAction(ISD::FPOW , MVT::f64, Expand);
124 setOperationAction(ISD::FSIN , MVT::f32, Expand);
125 setOperationAction(ISD::FCOS , MVT::f32, Expand);
126 setOperationAction(ISD::FREM , MVT::f32, Expand);
127 setOperationAction(ISD::FPOW , MVT::f32, Expand);
129 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
131 // If we're enabling GP optimizations, use hardware square root
132 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
133 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
134 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
137 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
138 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
140 // PowerPC does not have BSWAP, CTPOP or CTTZ
141 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
142 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
143 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
144 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
145 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
146 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
148 // PowerPC does not have ROTR
149 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
150 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
152 // PowerPC does not have Select
153 setOperationAction(ISD::SELECT, MVT::i32, Expand);
154 setOperationAction(ISD::SELECT, MVT::i64, Expand);
155 setOperationAction(ISD::SELECT, MVT::f32, Expand);
156 setOperationAction(ISD::SELECT, MVT::f64, Expand);
158 // PowerPC wants to turn select_cc of FP into fsel when possible.
159 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
160 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
162 // PowerPC wants to optimize integer setcc a bit
163 setOperationAction(ISD::SETCC, MVT::i32, Custom);
165 // PowerPC does not have BRCOND which requires SetCC
166 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
168 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
170 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
171 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
173 // PowerPC does not have [U|S]INT_TO_FP
174 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
175 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
177 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
178 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
179 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
180 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
182 // We cannot sextinreg(i1). Expand to shifts.
183 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
185 // Support label based line numbers.
186 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
187 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
189 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
190 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
192 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
195 // We want to legalize GlobalAddress and ConstantPool nodes into the
196 // appropriate instructions to materialize the address.
197 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
199 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
200 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
201 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
202 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
203 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
204 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
206 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
209 setOperationAction(ISD::TRAP, MVT::Other, Legal);
211 // TRAMPOLINE is custom lowered.
212 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
214 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
215 setOperationAction(ISD::VASTART , MVT::Other, Custom);
217 // VAARG is custom lowered with the 32-bit SVR4 ABI.
218 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
219 && !TM.getSubtarget<PPCSubtarget>().isPPC64())
220 setOperationAction(ISD::VAARG, MVT::Other, Custom);
222 setOperationAction(ISD::VAARG, MVT::Other, Expand);
224 // Use the default implementation.
225 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
226 setOperationAction(ISD::VAEND , MVT::Other, Expand);
227 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
228 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
229 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
230 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
232 // We want to custom lower some of our intrinsics.
233 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
235 // Comparisons that require checking two conditions.
236 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
243 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
244 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
247 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
249 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
250 // They also have instructions for converting between i64 and fp.
251 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
252 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
253 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
254 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
255 // This is just the low 32 bits of a (signed) fp->i64 conversion.
256 // We cannot do this with Promote because i64 is not a legal type.
257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
259 // FIXME: disable this lowered code. This generates 64-bit register values,
260 // and we don't model the fact that the top part is clobbered by calls. We
261 // need to flag these together so that the value isn't live across a call.
262 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
264 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
265 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
268 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
269 // 64-bit PowerPC implementations can support i64 types directly
270 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
271 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
272 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
273 // 64-bit PowerPC wants to expand i128 shifts itself.
274 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
275 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
276 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
278 // 32-bit PowerPC wants to expand i64 shifts itself.
279 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
280 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
281 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
284 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
285 // First set operation action for all vector types to expand. Then we
286 // will selectively turn on ones that can be effectively codegen'd.
287 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
288 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
289 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
291 // add/sub are legal for all supported vector VT's.
292 setOperationAction(ISD::ADD , VT, Legal);
293 setOperationAction(ISD::SUB , VT, Legal);
295 // We promote all shuffles to v16i8.
296 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
297 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
299 // We promote all non-typed operations to v4i32.
300 setOperationAction(ISD::AND , VT, Promote);
301 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
302 setOperationAction(ISD::OR , VT, Promote);
303 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
304 setOperationAction(ISD::XOR , VT, Promote);
305 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
306 setOperationAction(ISD::LOAD , VT, Promote);
307 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
308 setOperationAction(ISD::SELECT, VT, Promote);
309 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
310 setOperationAction(ISD::STORE, VT, Promote);
311 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
313 // No other operations are legal.
314 setOperationAction(ISD::MUL , VT, Expand);
315 setOperationAction(ISD::SDIV, VT, Expand);
316 setOperationAction(ISD::SREM, VT, Expand);
317 setOperationAction(ISD::UDIV, VT, Expand);
318 setOperationAction(ISD::UREM, VT, Expand);
319 setOperationAction(ISD::FDIV, VT, Expand);
320 setOperationAction(ISD::FNEG, VT, Expand);
321 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
323 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
324 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
326 setOperationAction(ISD::UDIVREM, VT, Expand);
327 setOperationAction(ISD::SDIVREM, VT, Expand);
328 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
329 setOperationAction(ISD::FPOW, VT, Expand);
330 setOperationAction(ISD::CTPOP, VT, Expand);
331 setOperationAction(ISD::CTLZ, VT, Expand);
332 setOperationAction(ISD::CTTZ, VT, Expand);
335 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
336 // with merges, splats, etc.
337 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
339 setOperationAction(ISD::AND , MVT::v4i32, Legal);
340 setOperationAction(ISD::OR , MVT::v4i32, Legal);
341 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
342 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
343 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
344 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
346 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
347 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
348 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
349 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
351 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
352 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
353 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
354 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
356 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
357 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
359 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
360 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
361 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
362 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
365 setShiftAmountType(MVT::i32);
366 setBooleanContents(ZeroOrOneBooleanContent);
368 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
369 setStackPointerRegisterToSaveRestore(PPC::X1);
370 setExceptionPointerRegister(PPC::X3);
371 setExceptionSelectorRegister(PPC::X4);
373 setStackPointerRegisterToSaveRestore(PPC::R1);
374 setExceptionPointerRegister(PPC::R3);
375 setExceptionSelectorRegister(PPC::R4);
378 // We have target-specific dag combine patterns for the following nodes:
379 setTargetDAGCombine(ISD::SINT_TO_FP);
380 setTargetDAGCombine(ISD::STORE);
381 setTargetDAGCombine(ISD::BR_CC);
382 setTargetDAGCombine(ISD::BSWAP);
384 // Darwin long double math library functions have $LDBL128 appended.
385 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
386 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
387 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
388 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
389 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
390 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
391 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
392 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
393 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
394 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
395 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
398 computeRegisterProperties();
401 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
402 /// function arguments in the caller parameter area.
403 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
404 TargetMachine &TM = getTargetMachine();
405 // Darwin passes everything on 4 byte boundary.
406 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
412 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
415 case PPCISD::FSEL: return "PPCISD::FSEL";
416 case PPCISD::FCFID: return "PPCISD::FCFID";
417 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
418 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
419 case PPCISD::STFIWX: return "PPCISD::STFIWX";
420 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
421 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
422 case PPCISD::VPERM: return "PPCISD::VPERM";
423 case PPCISD::Hi: return "PPCISD::Hi";
424 case PPCISD::Lo: return "PPCISD::Lo";
425 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
426 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
427 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
428 case PPCISD::SRL: return "PPCISD::SRL";
429 case PPCISD::SRA: return "PPCISD::SRA";
430 case PPCISD::SHL: return "PPCISD::SHL";
431 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
432 case PPCISD::STD_32: return "PPCISD::STD_32";
433 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
434 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
435 case PPCISD::NOP: return "PPCISD::NOP";
436 case PPCISD::MTCTR: return "PPCISD::MTCTR";
437 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
438 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
439 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
440 case PPCISD::MFCR: return "PPCISD::MFCR";
441 case PPCISD::VCMP: return "PPCISD::VCMP";
442 case PPCISD::VCMPo: return "PPCISD::VCMPo";
443 case PPCISD::LBRX: return "PPCISD::LBRX";
444 case PPCISD::STBRX: return "PPCISD::STBRX";
445 case PPCISD::LARX: return "PPCISD::LARX";
446 case PPCISD::STCX: return "PPCISD::STCX";
447 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
448 case PPCISD::MFFS: return "PPCISD::MFFS";
449 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
450 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
451 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
452 case PPCISD::MTFSF: return "PPCISD::MTFSF";
453 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
457 MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
461 /// getFunctionAlignment - Return the Log2 alignment of this function.
462 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
463 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
464 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
469 //===----------------------------------------------------------------------===//
470 // Node matching predicates, for use by the tblgen matching code.
471 //===----------------------------------------------------------------------===//
473 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
474 static bool isFloatingPointZero(SDValue Op) {
475 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
476 return CFP->getValueAPF().isZero();
477 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
478 // Maybe this has already been legalized into the constant pool?
479 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
480 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
481 return CFP->getValueAPF().isZero();
486 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
487 /// true if Op is undef or if it matches the specified value.
488 static bool isConstantOrUndef(int Op, int Val) {
489 return Op < 0 || Op == Val;
492 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
493 /// VPKUHUM instruction.
494 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
496 for (unsigned i = 0; i != 16; ++i)
497 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
500 for (unsigned i = 0; i != 8; ++i)
501 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
502 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
508 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
509 /// VPKUWUM instruction.
510 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
512 for (unsigned i = 0; i != 16; i += 2)
513 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
514 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
517 for (unsigned i = 0; i != 8; i += 2)
518 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
519 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
520 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
521 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
527 /// isVMerge - Common function, used to match vmrg* shuffles.
529 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
530 unsigned LHSStart, unsigned RHSStart) {
531 assert(N->getValueType(0) == MVT::v16i8 &&
532 "PPC only supports shuffles by bytes!");
533 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
534 "Unsupported merge size!");
536 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
537 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
538 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
539 LHSStart+j+i*UnitSize) ||
540 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
541 RHSStart+j+i*UnitSize))
547 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
548 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
549 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
552 return isVMerge(N, UnitSize, 8, 24);
553 return isVMerge(N, UnitSize, 8, 8);
556 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
557 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
558 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
561 return isVMerge(N, UnitSize, 0, 16);
562 return isVMerge(N, UnitSize, 0, 0);
566 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
567 /// amount, otherwise return -1.
568 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
569 assert(N->getValueType(0) == MVT::v16i8 &&
570 "PPC only supports shuffles by bytes!");
572 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
574 // Find the first non-undef value in the shuffle mask.
576 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
579 if (i == 16) return -1; // all undef.
581 // Otherwise, check to see if the rest of the elements are consecutively
582 // numbered from this value.
583 unsigned ShiftAmt = SVOp->getMaskElt(i);
584 if (ShiftAmt < i) return -1;
588 // Check the rest of the elements to see if they are consecutive.
589 for (++i; i != 16; ++i)
590 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
593 // Check the rest of the elements to see if they are consecutive.
594 for (++i; i != 16; ++i)
595 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
601 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
602 /// specifies a splat of a single element that is suitable for input to
603 /// VSPLTB/VSPLTH/VSPLTW.
604 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
605 assert(N->getValueType(0) == MVT::v16i8 &&
606 (EltSize == 1 || EltSize == 2 || EltSize == 4));
608 // This is a splat operation if each element of the permute is the same, and
609 // if the value doesn't reference the second vector.
610 unsigned ElementBase = N->getMaskElt(0);
612 // FIXME: Handle UNDEF elements too!
613 if (ElementBase >= 16)
616 // Check that the indices are consecutive, in the case of a multi-byte element
617 // splatted with a v16i8 mask.
618 for (unsigned i = 1; i != EltSize; ++i)
619 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
622 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
623 if (N->getMaskElt(i) < 0) continue;
624 for (unsigned j = 0; j != EltSize; ++j)
625 if (N->getMaskElt(i+j) != N->getMaskElt(j))
631 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
633 bool PPC::isAllNegativeZeroVector(SDNode *N) {
634 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
636 APInt APVal, APUndef;
640 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
641 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
642 return CFP->getValueAPF().isNegZero();
647 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
648 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
649 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
650 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
651 assert(isSplatShuffleMask(SVOp, EltSize));
652 return SVOp->getMaskElt(0) / EltSize;
655 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
656 /// by using a vspltis[bhw] instruction of the specified element size, return
657 /// the constant being splatted. The ByteSize field indicates the number of
658 /// bytes of each element [124] -> [bhw].
659 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
662 // If ByteSize of the splat is bigger than the element size of the
663 // build_vector, then we have a case where we are checking for a splat where
664 // multiple elements of the buildvector are folded together into a single
665 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
666 unsigned EltSize = 16/N->getNumOperands();
667 if (EltSize < ByteSize) {
668 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
669 SDValue UniquedVals[4];
670 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
672 // See if all of the elements in the buildvector agree across.
673 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
674 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
675 // If the element isn't a constant, bail fully out.
676 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
679 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
680 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
681 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
682 return SDValue(); // no match.
685 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
686 // either constant or undef values that are identical for each chunk. See
687 // if these chunks can form into a larger vspltis*.
689 // Check to see if all of the leading entries are either 0 or -1. If
690 // neither, then this won't fit into the immediate field.
691 bool LeadingZero = true;
692 bool LeadingOnes = true;
693 for (unsigned i = 0; i != Multiple-1; ++i) {
694 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
696 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
697 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
699 // Finally, check the least significant entry.
701 if (UniquedVals[Multiple-1].getNode() == 0)
702 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
703 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
705 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
708 if (UniquedVals[Multiple-1].getNode() == 0)
709 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
710 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
711 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
712 return DAG.getTargetConstant(Val, MVT::i32);
718 // Check to see if this buildvec has a single non-undef value in its elements.
719 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
720 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
721 if (OpVal.getNode() == 0)
722 OpVal = N->getOperand(i);
723 else if (OpVal != N->getOperand(i))
727 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
729 unsigned ValSizeInBytes = EltSize;
731 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
732 Value = CN->getZExtValue();
733 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
734 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
735 Value = FloatToBits(CN->getValueAPF().convertToFloat());
738 // If the splat value is larger than the element value, then we can never do
739 // this splat. The only case that we could fit the replicated bits into our
740 // immediate field for would be zero, and we prefer to use vxor for it.
741 if (ValSizeInBytes < ByteSize) return SDValue();
743 // If the element value is larger than the splat value, cut it in half and
744 // check to see if the two halves are equal. Continue doing this until we
745 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
746 while (ValSizeInBytes > ByteSize) {
747 ValSizeInBytes >>= 1;
749 // If the top half equals the bottom half, we're still ok.
750 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
751 (Value & ((1 << (8*ValSizeInBytes))-1)))
755 // Properly sign extend the value.
756 int ShAmt = (4-ByteSize)*8;
757 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
759 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
760 if (MaskVal == 0) return SDValue();
762 // Finally, if this value fits in a 5 bit sext field, return it
763 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
764 return DAG.getTargetConstant(MaskVal, MVT::i32);
768 //===----------------------------------------------------------------------===//
769 // Addressing Mode Selection
770 //===----------------------------------------------------------------------===//
772 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
773 /// or 64-bit immediate, and if the value can be accurately represented as a
774 /// sign extension from a 16-bit value. If so, this returns true and the
776 static bool isIntS16Immediate(SDNode *N, short &Imm) {
777 if (N->getOpcode() != ISD::Constant)
780 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
781 if (N->getValueType(0) == MVT::i32)
782 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
784 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
786 static bool isIntS16Immediate(SDValue Op, short &Imm) {
787 return isIntS16Immediate(Op.getNode(), Imm);
791 /// SelectAddressRegReg - Given the specified addressed, check to see if it
792 /// can be represented as an indexed [r+r] operation. Returns false if it
793 /// can be more efficiently represented with [r+imm].
794 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
796 SelectionDAG &DAG) const {
798 if (N.getOpcode() == ISD::ADD) {
799 if (isIntS16Immediate(N.getOperand(1), imm))
801 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
804 Base = N.getOperand(0);
805 Index = N.getOperand(1);
807 } else if (N.getOpcode() == ISD::OR) {
808 if (isIntS16Immediate(N.getOperand(1), imm))
809 return false; // r+i can fold it if we can.
811 // If this is an or of disjoint bitfields, we can codegen this as an add
812 // (for better address arithmetic) if the LHS and RHS of the OR are provably
814 APInt LHSKnownZero, LHSKnownOne;
815 APInt RHSKnownZero, RHSKnownOne;
816 DAG.ComputeMaskedBits(N.getOperand(0),
817 APInt::getAllOnesValue(N.getOperand(0)
818 .getValueSizeInBits()),
819 LHSKnownZero, LHSKnownOne);
821 if (LHSKnownZero.getBoolValue()) {
822 DAG.ComputeMaskedBits(N.getOperand(1),
823 APInt::getAllOnesValue(N.getOperand(1)
824 .getValueSizeInBits()),
825 RHSKnownZero, RHSKnownOne);
826 // If all of the bits are known zero on the LHS or RHS, the add won't
828 if (~(LHSKnownZero | RHSKnownZero) == 0) {
829 Base = N.getOperand(0);
830 Index = N.getOperand(1);
839 /// Returns true if the address N can be represented by a base register plus
840 /// a signed 16-bit displacement [r+imm], and if it is not better
841 /// represented as reg+reg.
842 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
844 SelectionDAG &DAG) const {
845 // FIXME dl should come from parent load or store, not from address
846 DebugLoc dl = N.getDebugLoc();
847 // If this can be more profitably realized as r+r, fail.
848 if (SelectAddressRegReg(N, Disp, Base, DAG))
851 if (N.getOpcode() == ISD::ADD) {
853 if (isIntS16Immediate(N.getOperand(1), imm)) {
854 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
855 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
856 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
858 Base = N.getOperand(0);
860 return true; // [r+i]
861 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
862 // Match LOAD (ADD (X, Lo(G))).
863 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
864 && "Cannot handle constant offsets yet!");
865 Disp = N.getOperand(1).getOperand(0); // The global address.
866 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
867 Disp.getOpcode() == ISD::TargetConstantPool ||
868 Disp.getOpcode() == ISD::TargetJumpTable);
869 Base = N.getOperand(0);
870 return true; // [&g+r]
872 } else if (N.getOpcode() == ISD::OR) {
874 if (isIntS16Immediate(N.getOperand(1), imm)) {
875 // If this is an or of disjoint bitfields, we can codegen this as an add
876 // (for better address arithmetic) if the LHS and RHS of the OR are
877 // provably disjoint.
878 APInt LHSKnownZero, LHSKnownOne;
879 DAG.ComputeMaskedBits(N.getOperand(0),
880 APInt::getAllOnesValue(N.getOperand(0)
881 .getValueSizeInBits()),
882 LHSKnownZero, LHSKnownOne);
884 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
885 // If all of the bits are known zero on the LHS or RHS, the add won't
887 Base = N.getOperand(0);
888 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
892 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
893 // Loading from a constant address.
895 // If this address fits entirely in a 16-bit sext immediate field, codegen
898 if (isIntS16Immediate(CN, Imm)) {
899 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
900 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
904 // Handle 32-bit sext immediates with LIS + addr mode.
905 if (CN->getValueType(0) == MVT::i32 ||
906 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
907 int Addr = (int)CN->getZExtValue();
909 // Otherwise, break this down into an LIS + disp.
910 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
912 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
913 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
914 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
919 Disp = DAG.getTargetConstant(0, getPointerTy());
920 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
921 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
924 return true; // [r+0]
927 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
928 /// represented as an indexed [r+r] operation.
929 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
931 SelectionDAG &DAG) const {
932 // Check to see if we can easily represent this as an [r+r] address. This
933 // will fail if it thinks that the address is more profitably represented as
934 // reg+imm, e.g. where imm = 0.
935 if (SelectAddressRegReg(N, Base, Index, DAG))
938 // If the operand is an addition, always emit this as [r+r], since this is
939 // better (for code size, and execution, as the memop does the add for free)
940 // than emitting an explicit add.
941 if (N.getOpcode() == ISD::ADD) {
942 Base = N.getOperand(0);
943 Index = N.getOperand(1);
947 // Otherwise, do it the hard way, using R0 as the base register.
948 Base = DAG.getRegister(PPC::R0, N.getValueType());
953 /// SelectAddressRegImmShift - Returns true if the address N can be
954 /// represented by a base register plus a signed 14-bit displacement
955 /// [r+imm*4]. Suitable for use by STD and friends.
956 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
958 SelectionDAG &DAG) const {
959 // FIXME dl should come from the parent load or store, not the address
960 DebugLoc dl = N.getDebugLoc();
961 // If this can be more profitably realized as r+r, fail.
962 if (SelectAddressRegReg(N, Disp, Base, DAG))
965 if (N.getOpcode() == ISD::ADD) {
967 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
968 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
969 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
970 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
972 Base = N.getOperand(0);
974 return true; // [r+i]
975 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
976 // Match LOAD (ADD (X, Lo(G))).
977 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
978 && "Cannot handle constant offsets yet!");
979 Disp = N.getOperand(1).getOperand(0); // The global address.
980 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
981 Disp.getOpcode() == ISD::TargetConstantPool ||
982 Disp.getOpcode() == ISD::TargetJumpTable);
983 Base = N.getOperand(0);
984 return true; // [&g+r]
986 } else if (N.getOpcode() == ISD::OR) {
988 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
989 // If this is an or of disjoint bitfields, we can codegen this as an add
990 // (for better address arithmetic) if the LHS and RHS of the OR are
991 // provably disjoint.
992 APInt LHSKnownZero, LHSKnownOne;
993 DAG.ComputeMaskedBits(N.getOperand(0),
994 APInt::getAllOnesValue(N.getOperand(0)
995 .getValueSizeInBits()),
996 LHSKnownZero, LHSKnownOne);
997 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
998 // If all of the bits are known zero on the LHS or RHS, the add won't
1000 Base = N.getOperand(0);
1001 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1005 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1006 // Loading from a constant address. Verify low two bits are clear.
1007 if ((CN->getZExtValue() & 3) == 0) {
1008 // If this address fits entirely in a 14-bit sext immediate field, codegen
1011 if (isIntS16Immediate(CN, Imm)) {
1012 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1013 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1017 // Fold the low-part of 32-bit absolute addresses into addr mode.
1018 if (CN->getValueType(0) == MVT::i32 ||
1019 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1020 int Addr = (int)CN->getZExtValue();
1022 // Otherwise, break this down into an LIS + disp.
1023 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1024 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1025 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1026 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1032 Disp = DAG.getTargetConstant(0, getPointerTy());
1033 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1034 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1037 return true; // [r+0]
1041 /// getPreIndexedAddressParts - returns true by value, base pointer and
1042 /// offset pointer and addressing mode by reference if the node's address
1043 /// can be legally represented as pre-indexed load / store address.
1044 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1046 ISD::MemIndexedMode &AM,
1047 SelectionDAG &DAG) const {
1048 // Disabled by default for now.
1049 if (!EnablePPCPreinc) return false;
1053 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1054 Ptr = LD->getBasePtr();
1055 VT = LD->getMemoryVT();
1057 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1059 Ptr = ST->getBasePtr();
1060 VT = ST->getMemoryVT();
1064 // PowerPC doesn't have preinc load/store instructions for vectors.
1068 // TODO: Check reg+reg first.
1070 // LDU/STU use reg+imm*4, others use reg+imm.
1071 if (VT != MVT::i64) {
1073 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1077 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1081 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1082 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1083 // sext i32 to i64 when addr mode is r+i.
1084 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1085 LD->getExtensionType() == ISD::SEXTLOAD &&
1086 isa<ConstantSDNode>(Offset))
1094 //===----------------------------------------------------------------------===//
1095 // LowerOperation implementation
1096 //===----------------------------------------------------------------------===//
1098 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1099 SelectionDAG &DAG) {
1100 EVT PtrVT = Op.getValueType();
1101 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1102 Constant *C = CP->getConstVal();
1103 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1104 SDValue Zero = DAG.getConstant(0, PtrVT);
1105 // FIXME there isn't really any debug info here
1106 DebugLoc dl = Op.getDebugLoc();
1108 const TargetMachine &TM = DAG.getTarget();
1110 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
1111 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
1113 // If this is a non-darwin platform, we don't support non-static relo models
1115 if (TM.getRelocationModel() == Reloc::Static ||
1116 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1117 // Generate non-pic code that has direct accesses to the constant pool.
1118 // The address of the global is just (hi(&g)+lo(&g)).
1119 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1122 if (TM.getRelocationModel() == Reloc::PIC_) {
1123 // With PIC, the first instruction is actually "GR+hi(&G)".
1124 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1125 DAG.getNode(PPCISD::GlobalBaseReg,
1126 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1129 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1133 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1134 EVT PtrVT = Op.getValueType();
1135 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1136 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1137 SDValue Zero = DAG.getConstant(0, PtrVT);
1138 // FIXME there isn't really any debug loc here
1139 DebugLoc dl = Op.getDebugLoc();
1141 const TargetMachine &TM = DAG.getTarget();
1143 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
1144 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
1146 // If this is a non-darwin platform, we don't support non-static relo models
1148 if (TM.getRelocationModel() == Reloc::Static ||
1149 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1150 // Generate non-pic code that has direct accesses to the constant pool.
1151 // The address of the global is just (hi(&g)+lo(&g)).
1152 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1155 if (TM.getRelocationModel() == Reloc::PIC_) {
1156 // With PIC, the first instruction is actually "GR+hi(&G)".
1157 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1158 DAG.getNode(PPCISD::GlobalBaseReg,
1159 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1162 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1166 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1167 SelectionDAG &DAG) {
1168 llvm_unreachable("TLS not implemented for PPC.");
1169 return SDValue(); // Not reached
1172 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
1173 EVT PtrVT = Op.getValueType();
1174 DebugLoc DL = Op.getDebugLoc();
1176 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1177 SDValue TgtBA = DAG.getBlockAddress(BA, DL, /*isTarget=*/true);
1178 SDValue Zero = DAG.getConstant(0, PtrVT);
1179 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero);
1180 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero);
1182 // If this is a non-darwin platform, we don't support non-static relo models
1184 const TargetMachine &TM = DAG.getTarget();
1185 if (TM.getRelocationModel() == Reloc::Static ||
1186 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1187 // Generate non-pic code that has direct accesses to globals.
1188 // The address of the global is just (hi(&g)+lo(&g)).
1189 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1192 if (TM.getRelocationModel() == Reloc::PIC_) {
1193 // With PIC, the first instruction is actually "GR+hi(&G)".
1194 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1195 DAG.getNode(PPCISD::GlobalBaseReg,
1196 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1199 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1202 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1203 SelectionDAG &DAG) {
1204 EVT PtrVT = Op.getValueType();
1205 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1206 GlobalValue *GV = GSDN->getGlobal();
1207 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1208 SDValue Zero = DAG.getConstant(0, PtrVT);
1209 // FIXME there isn't really any debug info here
1210 DebugLoc dl = GSDN->getDebugLoc();
1212 const TargetMachine &TM = DAG.getTarget();
1214 // 64-bit SVR4 ABI code is always position-independent.
1215 // The actual address of the GlobalValue is stored in the TOC.
1216 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1217 return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA,
1218 DAG.getRegister(PPC::X2, MVT::i64));
1221 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1222 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1224 // If this is a non-darwin platform, we don't support non-static relo models
1226 if (TM.getRelocationModel() == Reloc::Static ||
1227 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1228 // Generate non-pic code that has direct accesses to globals.
1229 // The address of the global is just (hi(&g)+lo(&g)).
1230 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1233 if (TM.getRelocationModel() == Reloc::PIC_) {
1234 // With PIC, the first instruction is actually "GR+hi(&G)".
1235 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1236 DAG.getNode(PPCISD::GlobalBaseReg,
1237 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1240 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1242 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM))
1245 // If the global is weak or external, we have to go through the lazy
1247 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
1250 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1251 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1252 DebugLoc dl = Op.getDebugLoc();
1254 // If we're comparing for equality to zero, expose the fact that this is
1255 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1256 // fold the new nodes.
1257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1258 if (C->isNullValue() && CC == ISD::SETEQ) {
1259 EVT VT = Op.getOperand(0).getValueType();
1260 SDValue Zext = Op.getOperand(0);
1261 if (VT.bitsLT(MVT::i32)) {
1263 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1265 unsigned Log2b = Log2_32(VT.getSizeInBits());
1266 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1267 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1268 DAG.getConstant(Log2b, MVT::i32));
1269 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1271 // Leave comparisons against 0 and -1 alone for now, since they're usually
1272 // optimized. FIXME: revisit this when we can custom lower all setcc
1274 if (C->isAllOnesValue() || C->isNullValue())
1278 // If we have an integer seteq/setne, turn it into a compare against zero
1279 // by xor'ing the rhs with the lhs, which is faster than setting a
1280 // condition register, reading it back out, and masking the correct bit. The
1281 // normal approach here uses sub to do this instead of xor. Using xor exposes
1282 // the result to other bit-twiddling opportunities.
1283 EVT LHSVT = Op.getOperand(0).getValueType();
1284 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1285 EVT VT = Op.getValueType();
1286 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1288 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1293 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1294 int VarArgsFrameIndex,
1295 int VarArgsStackOffset,
1296 unsigned VarArgsNumGPR,
1297 unsigned VarArgsNumFPR,
1298 const PPCSubtarget &Subtarget) {
1300 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1301 return SDValue(); // Not reached
1304 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1305 SDValue Chain = Op.getOperand(0);
1306 SDValue Trmp = Op.getOperand(1); // trampoline
1307 SDValue FPtr = Op.getOperand(2); // nested function
1308 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1309 DebugLoc dl = Op.getDebugLoc();
1311 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1312 bool isPPC64 = (PtrVT == MVT::i64);
1313 const Type *IntPtrTy =
1314 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1317 TargetLowering::ArgListTy Args;
1318 TargetLowering::ArgListEntry Entry;
1320 Entry.Ty = IntPtrTy;
1321 Entry.Node = Trmp; Args.push_back(Entry);
1323 // TrampSize == (isPPC64 ? 48 : 40);
1324 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1325 isPPC64 ? MVT::i64 : MVT::i32);
1326 Args.push_back(Entry);
1328 Entry.Node = FPtr; Args.push_back(Entry);
1329 Entry.Node = Nest; Args.push_back(Entry);
1331 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1332 std::pair<SDValue, SDValue> CallResult =
1333 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
1334 false, false, false, false, 0, CallingConv::C, false,
1335 /*isReturnValueUsed=*/true,
1336 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1340 { CallResult.first, CallResult.second };
1342 return DAG.getMergeValues(Ops, 2, dl);
1345 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1346 int VarArgsFrameIndex,
1347 int VarArgsStackOffset,
1348 unsigned VarArgsNumGPR,
1349 unsigned VarArgsNumFPR,
1350 const PPCSubtarget &Subtarget) {
1351 DebugLoc dl = Op.getDebugLoc();
1353 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1354 // vastart just stores the address of the VarArgsFrameIndex slot into the
1355 // memory location argument.
1356 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1357 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1358 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1359 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1362 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1363 // We suppose the given va_list is already allocated.
1366 // char gpr; /* index into the array of 8 GPRs
1367 // * stored in the register save area
1368 // * gpr=0 corresponds to r3,
1369 // * gpr=1 to r4, etc.
1371 // char fpr; /* index into the array of 8 FPRs
1372 // * stored in the register save area
1373 // * fpr=0 corresponds to f1,
1374 // * fpr=1 to f2, etc.
1376 // char *overflow_arg_area;
1377 // /* location on stack that holds
1378 // * the next overflow argument
1380 // char *reg_save_area;
1381 // /* where r3:r10 and f1:f8 (if saved)
1387 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32);
1388 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32);
1391 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1393 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1394 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1396 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1397 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1399 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1400 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1402 uint64_t FPROffset = 1;
1403 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1405 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1407 // Store first byte : number of int regs
1408 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1409 Op.getOperand(1), SV, 0, MVT::i8);
1410 uint64_t nextOffset = FPROffset;
1411 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1414 // Store second byte : number of float regs
1415 SDValue secondStore =
1416 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8);
1417 nextOffset += StackOffset;
1418 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1420 // Store second word : arguments given on stack
1421 SDValue thirdStore =
1422 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
1423 nextOffset += FrameOffset;
1424 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1426 // Store third word : arguments given in registers
1427 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset);
1431 #include "PPCGenCallingConv.inc"
1433 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
1434 CCValAssign::LocInfo &LocInfo,
1435 ISD::ArgFlagsTy &ArgFlags,
1440 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
1442 CCValAssign::LocInfo &LocInfo,
1443 ISD::ArgFlagsTy &ArgFlags,
1445 static const unsigned ArgRegs[] = {
1446 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1447 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1449 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1451 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1453 // Skip one register if the first unallocated register has an even register
1454 // number and there are still argument registers available which have not been
1455 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1456 // need to skip a register if RegNum is odd.
1457 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1458 State.AllocateReg(ArgRegs[RegNum]);
1461 // Always return false here, as this function only makes sure that the first
1462 // unallocated register has an odd register number and does not actually
1463 // allocate a register for the current argument.
1467 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
1469 CCValAssign::LocInfo &LocInfo,
1470 ISD::ArgFlagsTy &ArgFlags,
1472 static const unsigned ArgRegs[] = {
1473 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1477 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1479 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1481 // If there is only one Floating-point register left we need to put both f64
1482 // values of a split ppc_fp128 value on the stack.
1483 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1484 State.AllocateReg(ArgRegs[RegNum]);
1487 // Always return false here, as this function only makes sure that the two f64
1488 // values a ppc_fp128 value is split into are both passed in registers or both
1489 // passed on the stack and does not actually allocate a register for the
1490 // current argument.
1494 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1496 static const unsigned *GetFPR() {
1497 static const unsigned FPR[] = {
1498 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1499 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1505 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1507 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1508 unsigned PtrByteSize) {
1509 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1510 if (Flags.isByVal())
1511 ArgSize = Flags.getByValSize();
1512 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1518 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1519 CallingConv::ID CallConv, bool isVarArg,
1520 const SmallVectorImpl<ISD::InputArg>
1522 DebugLoc dl, SelectionDAG &DAG,
1523 SmallVectorImpl<SDValue> &InVals) {
1524 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1525 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1528 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1534 PPCTargetLowering::LowerFormalArguments_SVR4(
1536 CallingConv::ID CallConv, bool isVarArg,
1537 const SmallVectorImpl<ISD::InputArg>
1539 DebugLoc dl, SelectionDAG &DAG,
1540 SmallVectorImpl<SDValue> &InVals) {
1542 // 32-bit SVR4 ABI Stack Frame Layout:
1543 // +-----------------------------------+
1544 // +--> | Back chain |
1545 // | +-----------------------------------+
1546 // | | Floating-point register save area |
1547 // | +-----------------------------------+
1548 // | | General register save area |
1549 // | +-----------------------------------+
1550 // | | CR save word |
1551 // | +-----------------------------------+
1552 // | | VRSAVE save word |
1553 // | +-----------------------------------+
1554 // | | Alignment padding |
1555 // | +-----------------------------------+
1556 // | | Vector register save area |
1557 // | +-----------------------------------+
1558 // | | Local variable space |
1559 // | +-----------------------------------+
1560 // | | Parameter list area |
1561 // | +-----------------------------------+
1562 // | | LR save word |
1563 // | +-----------------------------------+
1564 // SP--> +--- | Back chain |
1565 // +-----------------------------------+
1568 // System V Application Binary Interface PowerPC Processor Supplement
1569 // AltiVec Technology Programming Interface Manual
1571 MachineFunction &MF = DAG.getMachineFunction();
1572 MachineFrameInfo *MFI = MF.getFrameInfo();
1574 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1575 // Potential tail calls could cause overwriting of argument stack slots.
1576 bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast));
1577 unsigned PtrByteSize = 4;
1579 // Assign locations to all of the incoming arguments.
1580 SmallVector<CCValAssign, 16> ArgLocs;
1581 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1584 // Reserve space for the linkage area on the stack.
1585 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
1587 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1589 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1590 CCValAssign &VA = ArgLocs[i];
1592 // Arguments stored in registers.
1593 if (VA.isRegLoc()) {
1594 TargetRegisterClass *RC;
1595 EVT ValVT = VA.getValVT();
1597 switch (ValVT.getSimpleVT().SimpleTy) {
1599 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1601 RC = PPC::GPRCRegisterClass;
1604 RC = PPC::F4RCRegisterClass;
1607 RC = PPC::F8RCRegisterClass;
1613 RC = PPC::VRRCRegisterClass;
1617 // Transform the arguments stored in physical registers into virtual ones.
1618 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1619 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1621 InVals.push_back(ArgValue);
1623 // Argument stored in memory.
1624 assert(VA.isMemLoc());
1626 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1627 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1628 isImmutable, false);
1630 // Create load nodes to retrieve arguments from the stack.
1631 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1632 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1636 // Assign locations to all of the incoming aggregate by value arguments.
1637 // Aggregates passed by value are stored in the local variable space of the
1638 // caller's stack frame, right above the parameter list area.
1639 SmallVector<CCValAssign, 16> ByValArgLocs;
1640 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1641 ByValArgLocs, *DAG.getContext());
1643 // Reserve stack space for the allocations in CCInfo.
1644 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1646 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1648 // Area that is at least reserved in the caller of this function.
1649 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1651 // Set the size that is at least reserved in caller of this function. Tail
1652 // call optimized function's reserved stack space needs to be aligned so that
1653 // taking the difference between two stack areas will result in an aligned
1655 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1658 std::max(MinReservedArea,
1659 PPCFrameInfo::getMinCallFrameSize(false, false));
1661 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1662 getStackAlignment();
1663 unsigned AlignMask = TargetAlign-1;
1664 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1666 FI->setMinReservedArea(MinReservedArea);
1668 SmallVector<SDValue, 8> MemOps;
1670 // If the function takes variable number of arguments, make a frame index for
1671 // the start of the first vararg value... for expansion of llvm.va_start.
1673 static const unsigned GPArgRegs[] = {
1674 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1675 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1677 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1679 static const unsigned FPArgRegs[] = {
1680 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1683 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1685 VarArgsNumGPR = CCInfo.getFirstUnallocated(GPArgRegs, NumGPArgRegs);
1686 VarArgsNumFPR = CCInfo.getFirstUnallocated(FPArgRegs, NumFPArgRegs);
1688 // Make room for NumGPArgRegs and NumFPArgRegs.
1689 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1690 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1692 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1693 CCInfo.getNextStackOffset(),
1696 VarArgsFrameIndex = MFI->CreateStackObject(Depth, 8, false);
1697 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1699 // The fixed integer arguments of a variadic function are
1700 // stored to the VarArgsFrameIndex on the stack.
1701 unsigned GPRIndex = 0;
1702 for (; GPRIndex != VarArgsNumGPR; ++GPRIndex) {
1703 SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT);
1704 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0);
1705 MemOps.push_back(Store);
1706 // Increment the address by four for the next argument to store
1707 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1708 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1711 // If this function is vararg, store any remaining integer argument regs
1712 // to their spots on the stack so that they may be loaded by deferencing the
1713 // result of va_next.
1714 for (; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1715 unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1717 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1718 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1719 MemOps.push_back(Store);
1720 // Increment the address by four for the next argument to store
1721 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1722 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1725 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1728 // The double arguments are stored to the VarArgsFrameIndex
1730 unsigned FPRIndex = 0;
1731 for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) {
1732 SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
1733 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0);
1734 MemOps.push_back(Store);
1735 // Increment the address by eight for the next argument to store
1736 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1738 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1741 for (; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1742 unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1744 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1745 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1746 MemOps.push_back(Store);
1747 // Increment the address by eight for the next argument to store
1748 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1750 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1754 if (!MemOps.empty())
1755 Chain = DAG.getNode(ISD::TokenFactor, dl,
1756 MVT::Other, &MemOps[0], MemOps.size());
1762 PPCTargetLowering::LowerFormalArguments_Darwin(
1764 CallingConv::ID CallConv, bool isVarArg,
1765 const SmallVectorImpl<ISD::InputArg>
1767 DebugLoc dl, SelectionDAG &DAG,
1768 SmallVectorImpl<SDValue> &InVals) {
1769 // TODO: add description of PPC stack frame format, or at least some docs.
1771 MachineFunction &MF = DAG.getMachineFunction();
1772 MachineFrameInfo *MFI = MF.getFrameInfo();
1774 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1775 bool isPPC64 = PtrVT == MVT::i64;
1776 // Potential tail calls could cause overwriting of argument stack slots.
1777 bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast));
1778 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1780 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
1781 // Area that is at least reserved in caller of this function.
1782 unsigned MinReservedArea = ArgOffset;
1784 static const unsigned GPR_32[] = { // 32-bit registers.
1785 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1786 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1788 static const unsigned GPR_64[] = { // 64-bit registers.
1789 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1790 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1793 static const unsigned *FPR = GetFPR();
1795 static const unsigned VR[] = {
1796 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1797 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1800 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1801 const unsigned Num_FPR_Regs = 13;
1802 const unsigned Num_VR_Regs = array_lengthof( VR);
1804 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1806 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1808 // In 32-bit non-varargs functions, the stack space for vectors is after the
1809 // stack space for non-vectors. We do not use this space unless we have
1810 // too many vectors to fit in registers, something that only occurs in
1811 // constructed examples:), but we have to walk the arglist to figure
1812 // that out...for the pathological case, compute VecArgOffset as the
1813 // start of the vector parameter area. Computing VecArgOffset is the
1814 // entire point of the following loop.
1815 unsigned VecArgOffset = ArgOffset;
1816 if (!isVarArg && !isPPC64) {
1817 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1819 EVT ObjectVT = Ins[ArgNo].VT;
1820 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1821 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1823 if (Flags.isByVal()) {
1824 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1825 ObjSize = Flags.getByValSize();
1827 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1828 VecArgOffset += ArgSize;
1832 switch(ObjectVT.getSimpleVT().SimpleTy) {
1833 default: llvm_unreachable("Unhandled argument type!");
1836 VecArgOffset += isPPC64 ? 8 : 4;
1838 case MVT::i64: // PPC64
1846 // Nothing to do, we're only looking at Nonvector args here.
1851 // We've found where the vector parameter area in memory is. Skip the
1852 // first 12 parameters; these don't use that memory.
1853 VecArgOffset = ((VecArgOffset+15)/16)*16;
1854 VecArgOffset += 12*16;
1856 // Add DAG nodes to load the arguments or copy them out of registers. On
1857 // entry to a function on PPC, the arguments start after the linkage area,
1858 // although the first ones are often in registers.
1860 SmallVector<SDValue, 8> MemOps;
1861 unsigned nAltivecParamsAtEnd = 0;
1862 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1864 bool needsLoad = false;
1865 EVT ObjectVT = Ins[ArgNo].VT;
1866 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1867 unsigned ArgSize = ObjSize;
1868 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1870 unsigned CurArgOffset = ArgOffset;
1872 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1873 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1874 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1875 if (isVarArg || isPPC64) {
1876 MinReservedArea = ((MinReservedArea+15)/16)*16;
1877 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1880 } else nAltivecParamsAtEnd++;
1882 // Calculate min reserved area.
1883 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1887 // FIXME the codegen can be much improved in some cases.
1888 // We do not have to keep everything in memory.
1889 if (Flags.isByVal()) {
1890 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1891 ObjSize = Flags.getByValSize();
1892 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1893 // Objects of size 1 and 2 are right justified, everything else is
1894 // left justified. This means the memory address is adjusted forwards.
1895 if (ObjSize==1 || ObjSize==2) {
1896 CurArgOffset = CurArgOffset + (4 - ObjSize);
1898 // The value of the object is its address.
1899 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true, false);
1900 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1901 InVals.push_back(FIN);
1902 if (ObjSize==1 || ObjSize==2) {
1903 if (GPR_idx != Num_GPR_Regs) {
1904 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1905 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1906 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1907 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1908 MemOps.push_back(Store);
1912 ArgOffset += PtrByteSize;
1916 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1917 // Store whatever pieces of the object are in registers
1918 // to memory. ArgVal will be address of the beginning of
1920 if (GPR_idx != Num_GPR_Regs) {
1921 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1922 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true, false);
1923 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1924 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1925 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1926 MemOps.push_back(Store);
1928 ArgOffset += PtrByteSize;
1930 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1937 switch (ObjectVT.getSimpleVT().SimpleTy) {
1938 default: llvm_unreachable("Unhandled argument type!");
1941 if (GPR_idx != Num_GPR_Regs) {
1942 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1943 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1947 ArgSize = PtrByteSize;
1949 // All int arguments reserve stack space in the Darwin ABI.
1950 ArgOffset += PtrByteSize;
1954 case MVT::i64: // PPC64
1955 if (GPR_idx != Num_GPR_Regs) {
1956 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1957 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1959 if (ObjectVT == MVT::i32) {
1960 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1961 // value to MVT::i64 and then truncate to the correct register size.
1963 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1964 DAG.getValueType(ObjectVT));
1965 else if (Flags.isZExt())
1966 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1967 DAG.getValueType(ObjectVT));
1969 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1975 ArgSize = PtrByteSize;
1977 // All int arguments reserve stack space in the Darwin ABI.
1983 // Every 4 bytes of argument space consumes one of the GPRs available for
1984 // argument passing.
1985 if (GPR_idx != Num_GPR_Regs) {
1987 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1990 if (FPR_idx != Num_FPR_Regs) {
1993 if (ObjectVT == MVT::f32)
1994 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1996 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1998 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2004 // All FP arguments reserve stack space in the Darwin ABI.
2005 ArgOffset += isPPC64 ? 8 : ObjSize;
2011 // Note that vector arguments in registers don't reserve stack space,
2012 // except in varargs functions.
2013 if (VR_idx != Num_VR_Regs) {
2014 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2015 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2017 while ((ArgOffset % 16) != 0) {
2018 ArgOffset += PtrByteSize;
2019 if (GPR_idx != Num_GPR_Regs)
2023 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2027 if (!isVarArg && !isPPC64) {
2028 // Vectors go after all the nonvectors.
2029 CurArgOffset = VecArgOffset;
2032 // Vectors are aligned.
2033 ArgOffset = ((ArgOffset+15)/16)*16;
2034 CurArgOffset = ArgOffset;
2042 // We need to load the argument to a virtual register if we determined above
2043 // that we ran out of physical registers of the appropriate type.
2045 int FI = MFI->CreateFixedObject(ObjSize,
2046 CurArgOffset + (ArgSize - ObjSize),
2047 isImmutable, false);
2048 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2049 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0);
2052 InVals.push_back(ArgVal);
2055 // Set the size that is at least reserved in caller of this function. Tail
2056 // call optimized function's reserved stack space needs to be aligned so that
2057 // taking the difference between two stack areas will result in an aligned
2059 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2060 // Add the Altivec parameters at the end, if needed.
2061 if (nAltivecParamsAtEnd) {
2062 MinReservedArea = ((MinReservedArea+15)/16)*16;
2063 MinReservedArea += 16*nAltivecParamsAtEnd;
2066 std::max(MinReservedArea,
2067 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2068 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2069 getStackAlignment();
2070 unsigned AlignMask = TargetAlign-1;
2071 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2072 FI->setMinReservedArea(MinReservedArea);
2074 // If the function takes variable number of arguments, make a frame index for
2075 // the start of the first vararg value... for expansion of llvm.va_start.
2077 int Depth = ArgOffset;
2079 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2080 Depth, true, false);
2081 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
2083 // If this function is vararg, store any remaining integer argument regs
2084 // to their spots on the stack so that they may be loaded by deferencing the
2085 // result of va_next.
2086 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2090 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2092 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2094 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2095 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
2096 MemOps.push_back(Store);
2097 // Increment the address by four for the next argument to store
2098 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2099 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2103 if (!MemOps.empty())
2104 Chain = DAG.getNode(ISD::TokenFactor, dl,
2105 MVT::Other, &MemOps[0], MemOps.size());
2110 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2111 /// linkage area for the Darwin ABI.
2113 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2117 const SmallVectorImpl<ISD::OutputArg>
2119 unsigned &nAltivecParamsAtEnd) {
2120 // Count how many bytes are to be pushed on the stack, including the linkage
2121 // area, and parameter passing area. We start with 24/48 bytes, which is
2122 // prereserved space for [SP][CR][LR][3 x unused].
2123 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true);
2124 unsigned NumOps = Outs.size();
2125 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2127 // Add up all the space actually used.
2128 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2129 // they all go in registers, but we must reserve stack space for them for
2130 // possible use by the caller. In varargs or 64-bit calls, parameters are
2131 // assigned stack space in order, with padding so Altivec parameters are
2133 nAltivecParamsAtEnd = 0;
2134 for (unsigned i = 0; i != NumOps; ++i) {
2135 SDValue Arg = Outs[i].Val;
2136 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2137 EVT ArgVT = Arg.getValueType();
2138 // Varargs Altivec parameters are padded to a 16 byte boundary.
2139 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2140 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2141 if (!isVarArg && !isPPC64) {
2142 // Non-varargs Altivec parameters go after all the non-Altivec
2143 // parameters; handle those later so we know how much padding we need.
2144 nAltivecParamsAtEnd++;
2147 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2148 NumBytes = ((NumBytes+15)/16)*16;
2150 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2153 // Allow for Altivec parameters at the end, if needed.
2154 if (nAltivecParamsAtEnd) {
2155 NumBytes = ((NumBytes+15)/16)*16;
2156 NumBytes += 16*nAltivecParamsAtEnd;
2159 // The prolog code of the callee may store up to 8 GPR argument registers to
2160 // the stack, allowing va_start to index over them in memory if its varargs.
2161 // Because we cannot tell if this is needed on the caller side, we have to
2162 // conservatively assume that it is needed. As such, make sure we have at
2163 // least enough stack space for the caller to store the 8 GPRs.
2164 NumBytes = std::max(NumBytes,
2165 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2167 // Tail call needs the stack to be aligned.
2168 if (CC==CallingConv::Fast && PerformTailCallOpt) {
2169 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2170 getStackAlignment();
2171 unsigned AlignMask = TargetAlign-1;
2172 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2178 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2179 /// adjusted to accomodate the arguments for the tailcall.
2180 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
2181 unsigned ParamSize) {
2183 if (!IsTailCall) return 0;
2185 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2186 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2187 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2188 // Remember only if the new adjustement is bigger.
2189 if (SPDiff < FI->getTailCallSPDelta())
2190 FI->setTailCallSPDelta(SPDiff);
2195 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2196 /// for tail call optimization. Targets which want to do tail call
2197 /// optimization should implement this function.
2199 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2200 CallingConv::ID CalleeCC,
2202 const SmallVectorImpl<ISD::InputArg> &Ins,
2203 SelectionDAG& DAG) const {
2204 // Variable argument functions are not supported.
2208 MachineFunction &MF = DAG.getMachineFunction();
2209 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2210 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2211 // Functions containing by val parameters are not supported.
2212 for (unsigned i = 0; i != Ins.size(); i++) {
2213 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2214 if (Flags.isByVal()) return false;
2217 // Non PIC/GOT tail calls are supported.
2218 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2221 // At the moment we can only do local tail calls (in same module, hidden
2222 // or protected) if we are generating PIC.
2223 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2224 return G->getGlobal()->hasHiddenVisibility()
2225 || G->getGlobal()->hasProtectedVisibility();
2231 /// isCallCompatibleAddress - Return the immediate to use if the specified
2232 /// 32-bit value is representable in the immediate field of a BxA instruction.
2233 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2234 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2237 int Addr = C->getZExtValue();
2238 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2239 (Addr << 6 >> 6) != Addr)
2240 return 0; // Top 6 bits have to be sext of immediate.
2242 return DAG.getConstant((int)C->getZExtValue() >> 2,
2243 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2248 struct TailCallArgumentInfo {
2253 TailCallArgumentInfo() : FrameIdx(0) {}
2258 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2260 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2262 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2263 SmallVector<SDValue, 8> &MemOpChains,
2265 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2266 SDValue Arg = TailCallArgs[i].Arg;
2267 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2268 int FI = TailCallArgs[i].FrameIdx;
2269 // Store relative to framepointer.
2270 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2271 PseudoSourceValue::getFixedStack(FI),
2276 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2277 /// the appropriate stack slot for the tail call optimized function call.
2278 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2279 MachineFunction &MF,
2288 // Calculate the new stack slot for the return address.
2289 int SlotSize = isPPC64 ? 8 : 4;
2290 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2292 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2295 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2296 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2297 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2298 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
2300 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2301 // slot as the FP is never overwritten.
2304 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2305 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2307 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2308 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2309 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
2315 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2316 /// the position of the argument.
2318 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2319 SDValue Arg, int SPDiff, unsigned ArgOffset,
2320 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2321 int Offset = ArgOffset + SPDiff;
2322 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2323 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true,false);
2324 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2325 SDValue FIN = DAG.getFrameIndex(FI, VT);
2326 TailCallArgumentInfo Info;
2328 Info.FrameIdxOp = FIN;
2330 TailCallArguments.push_back(Info);
2333 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2334 /// stack slot. Returns the chain as result and the loaded frame pointers in
2335 /// LROpOut/FPOpout. Used when tail calling.
2336 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2344 // Load the LR and FP stack slot for later adjusting.
2345 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2346 LROpOut = getReturnAddrFrameIndex(DAG);
2347 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
2348 Chain = SDValue(LROpOut.getNode(), 1);
2350 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2351 // slot as the FP is never overwritten.
2353 FPOpOut = getFramePointerFrameIndex(DAG);
2354 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
2355 Chain = SDValue(FPOpOut.getNode(), 1);
2361 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2362 /// by "Src" to address "Dst" of size "Size". Alignment information is
2363 /// specified by the specific parameter attribute. The copy will be passed as
2364 /// a byval function parameter.
2365 /// Sometimes what we are copying is the end of a larger object, the part that
2366 /// does not fit in registers.
2368 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2369 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2371 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2372 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2373 false, NULL, 0, NULL, 0);
2376 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2379 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2380 SDValue Arg, SDValue PtrOff, int SPDiff,
2381 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2382 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2383 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2385 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2390 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2392 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2393 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2394 DAG.getConstant(ArgOffset, PtrVT));
2396 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
2397 // Calculate and remember argument location.
2398 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2403 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2404 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2405 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2406 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2407 MachineFunction &MF = DAG.getMachineFunction();
2409 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2410 // might overwrite each other in case of tail call optimization.
2411 SmallVector<SDValue, 8> MemOpChains2;
2412 // Do not flag preceeding copytoreg stuff together with the following stuff.
2414 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2416 if (!MemOpChains2.empty())
2417 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2418 &MemOpChains2[0], MemOpChains2.size());
2420 // Store the return address to the appropriate stack slot.
2421 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2422 isPPC64, isDarwinABI, dl);
2424 // Emit callseq_end just before tailcall node.
2425 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2426 DAG.getIntPtrConstant(0, true), InFlag);
2427 InFlag = Chain.getValue(1);
2431 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2432 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2433 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2434 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2436 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2437 NodeTys.push_back(MVT::Other); // Returns a chain
2438 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2440 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2442 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2443 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2444 // node so that legalize doesn't hack it.
2445 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2446 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2447 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2448 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2449 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2450 // If this is an absolute destination address, use the munged value.
2451 Callee = SDValue(Dest, 0);
2453 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2454 // to do the call, we can't use PPCISD::CALL.
2455 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2456 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2457 2 + (InFlag.getNode() != 0));
2458 InFlag = Chain.getValue(1);
2461 NodeTys.push_back(MVT::Other);
2462 NodeTys.push_back(MVT::Flag);
2463 Ops.push_back(Chain);
2464 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2466 // Add CTR register as callee so a bctr can be emitted later.
2468 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2471 // If this is a direct call, pass the chain and the callee.
2472 if (Callee.getNode()) {
2473 Ops.push_back(Chain);
2474 Ops.push_back(Callee);
2476 // If this is a tail call add stack pointer delta.
2478 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2480 // Add argument registers to the end of the list so that they are known live
2482 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2483 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2484 RegsToPass[i].second.getValueType()));
2490 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2491 CallingConv::ID CallConv, bool isVarArg,
2492 const SmallVectorImpl<ISD::InputArg> &Ins,
2493 DebugLoc dl, SelectionDAG &DAG,
2494 SmallVectorImpl<SDValue> &InVals) {
2496 SmallVector<CCValAssign, 16> RVLocs;
2497 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2498 RVLocs, *DAG.getContext());
2499 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2501 // Copy all of the result registers out of their specified physreg.
2502 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2503 CCValAssign &VA = RVLocs[i];
2504 EVT VT = VA.getValVT();
2505 assert(VA.isRegLoc() && "Can only return in registers!");
2506 Chain = DAG.getCopyFromReg(Chain, dl,
2507 VA.getLocReg(), VT, InFlag).getValue(1);
2508 InVals.push_back(Chain.getValue(0));
2509 InFlag = Chain.getValue(2);
2516 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2517 bool isTailCall, bool isVarArg,
2519 SmallVector<std::pair<unsigned, SDValue>, 8>
2521 SDValue InFlag, SDValue Chain,
2523 int SPDiff, unsigned NumBytes,
2524 const SmallVectorImpl<ISD::InputArg> &Ins,
2525 SmallVectorImpl<SDValue> &InVals) {
2526 std::vector<EVT> NodeTys;
2527 SmallVector<SDValue, 8> Ops;
2528 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2529 isTailCall, RegsToPass, Ops, NodeTys,
2530 PPCSubTarget.isSVR4ABI());
2532 // When performing tail call optimization the callee pops its arguments off
2533 // the stack. Account for this here so these bytes can be pushed back on in
2534 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2535 int BytesCalleePops =
2536 (CallConv==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2538 if (InFlag.getNode())
2539 Ops.push_back(InFlag);
2543 // If this is the first return lowered for this function, add the regs
2544 // to the liveout set for the function.
2545 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2546 SmallVector<CCValAssign, 16> RVLocs;
2547 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2549 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2550 for (unsigned i = 0; i != RVLocs.size(); ++i)
2551 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2554 assert(((Callee.getOpcode() == ISD::Register &&
2555 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2556 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2557 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2558 isa<ConstantSDNode>(Callee)) &&
2559 "Expecting an global address, external symbol, absolute value or register");
2561 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2564 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2565 InFlag = Chain.getValue(1);
2567 // Add a NOP immediately after the branch instruction when using the 64-bit
2568 // SVR4 ABI. At link time, if caller and callee are in a different module and
2569 // thus have a different TOC, the call will be replaced with a call to a stub
2570 // function which saves the current TOC, loads the TOC of the callee and
2571 // branches to the callee. The NOP will be replaced with a load instruction
2572 // which restores the TOC of the caller from the TOC save slot of the current
2573 // stack frame. If caller and callee belong to the same module (and have the
2574 // same TOC), the NOP will remain unchanged.
2575 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2577 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag);
2580 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2581 DAG.getIntPtrConstant(BytesCalleePops, true),
2584 InFlag = Chain.getValue(1);
2586 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2587 Ins, dl, DAG, InVals);
2591 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2592 CallingConv::ID CallConv, bool isVarArg,
2594 const SmallVectorImpl<ISD::OutputArg> &Outs,
2595 const SmallVectorImpl<ISD::InputArg> &Ins,
2596 DebugLoc dl, SelectionDAG &DAG,
2597 SmallVectorImpl<SDValue> &InVals) {
2598 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
2599 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2600 isTailCall, Outs, Ins,
2603 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2604 isTailCall, Outs, Ins,
2610 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2611 CallingConv::ID CallConv, bool isVarArg,
2613 const SmallVectorImpl<ISD::OutputArg> &Outs,
2614 const SmallVectorImpl<ISD::InputArg> &Ins,
2615 DebugLoc dl, SelectionDAG &DAG,
2616 SmallVectorImpl<SDValue> &InVals) {
2617 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2618 // of the 32-bit SVR4 ABI stack frame layout.
2620 assert((!isTailCall ||
2621 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
2622 "IsEligibleForTailCallOptimization missed a case!");
2624 assert((CallConv == CallingConv::C ||
2625 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2627 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2628 unsigned PtrByteSize = 4;
2630 MachineFunction &MF = DAG.getMachineFunction();
2632 // Mark this function as potentially containing a function that contains a
2633 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2634 // and restoring the callers stack pointer in this functions epilog. This is
2635 // done because by tail calling the called function might overwrite the value
2636 // in this function's (MF) stack pointer stack slot 0(SP).
2637 if (PerformTailCallOpt && CallConv==CallingConv::Fast)
2638 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2640 // Count how many bytes are to be pushed on the stack, including the linkage
2641 // area, parameter list area and the part of the local variable space which
2642 // contains copies of aggregates which are passed by value.
2644 // Assign locations to all of the outgoing arguments.
2645 SmallVector<CCValAssign, 16> ArgLocs;
2646 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2647 ArgLocs, *DAG.getContext());
2649 // Reserve space for the linkage area on the stack.
2650 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
2653 // Handle fixed and variable vector arguments differently.
2654 // Fixed vector arguments go into registers as long as registers are
2655 // available. Variable vector arguments always go into memory.
2656 unsigned NumArgs = Outs.size();
2658 for (unsigned i = 0; i != NumArgs; ++i) {
2659 EVT ArgVT = Outs[i].Val.getValueType();
2660 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2663 if (Outs[i].IsFixed) {
2664 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2667 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2673 errs() << "Call operand #" << i << " has unhandled type "
2674 << ArgVT.getEVTString() << "\n";
2676 llvm_unreachable(0);
2680 // All arguments are treated the same.
2681 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2684 // Assign locations to all of the outgoing aggregate by value arguments.
2685 SmallVector<CCValAssign, 16> ByValArgLocs;
2686 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2689 // Reserve stack space for the allocations in CCInfo.
2690 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2692 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2694 // Size of the linkage area, parameter list area and the part of the local
2695 // space variable where copies of aggregates which are passed by value are
2697 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2699 // Calculate by how many bytes the stack has to be adjusted in case of tail
2700 // call optimization.
2701 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2703 // Adjust the stack pointer for the new arguments...
2704 // These operations are automatically eliminated by the prolog/epilog pass
2705 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2706 SDValue CallSeqStart = Chain;
2708 // Load the return address and frame pointer so it can be moved somewhere else
2711 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2714 // Set up a copy of the stack pointer for use loading and storing any
2715 // arguments that may not fit in the registers available for argument
2717 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2719 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2720 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2721 SmallVector<SDValue, 8> MemOpChains;
2723 // Walk the register/memloc assignments, inserting copies/loads.
2724 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2727 CCValAssign &VA = ArgLocs[i];
2728 SDValue Arg = Outs[i].Val;
2729 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2731 if (Flags.isByVal()) {
2732 // Argument is an aggregate which is passed by value, thus we need to
2733 // create a copy of it in the local variable space of the current stack
2734 // frame (which is the stack frame of the caller) and pass the address of
2735 // this copy to the callee.
2736 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2737 CCValAssign &ByValVA = ByValArgLocs[j++];
2738 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2740 // Memory reserved in the local variable space of the callers stack frame.
2741 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2743 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2744 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2746 // Create a copy of the argument in the local area of the current
2748 SDValue MemcpyCall =
2749 CreateCopyOfByValArgument(Arg, PtrOff,
2750 CallSeqStart.getNode()->getOperand(0),
2753 // This must go outside the CALLSEQ_START..END.
2754 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2755 CallSeqStart.getNode()->getOperand(1));
2756 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2757 NewCallSeqStart.getNode());
2758 Chain = CallSeqStart = NewCallSeqStart;
2760 // Pass the address of the aggregate copy on the stack either in a
2761 // physical register or in the parameter list area of the current stack
2762 // frame to the callee.
2766 if (VA.isRegLoc()) {
2767 // Put argument in a physical register.
2768 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2770 // Put argument in the parameter list area of the current stack frame.
2771 assert(VA.isMemLoc());
2772 unsigned LocMemOffset = VA.getLocMemOffset();
2775 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2776 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2778 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2779 PseudoSourceValue::getStack(), LocMemOffset));
2781 // Calculate and remember argument location.
2782 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2788 if (!MemOpChains.empty())
2789 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2790 &MemOpChains[0], MemOpChains.size());
2792 // Build a sequence of copy-to-reg nodes chained together with token chain
2793 // and flag operands which copy the outgoing args into the appropriate regs.
2795 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2796 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2797 RegsToPass[i].second, InFlag);
2798 InFlag = Chain.getValue(1);
2801 // Set CR6 to true if this is a vararg call.
2803 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0);
2804 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2805 InFlag = Chain.getValue(1);
2809 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2810 false, TailCallArguments);
2813 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
2814 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
2819 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
2820 CallingConv::ID CallConv, bool isVarArg,
2822 const SmallVectorImpl<ISD::OutputArg> &Outs,
2823 const SmallVectorImpl<ISD::InputArg> &Ins,
2824 DebugLoc dl, SelectionDAG &DAG,
2825 SmallVectorImpl<SDValue> &InVals) {
2827 unsigned NumOps = Outs.size();
2829 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2830 bool isPPC64 = PtrVT == MVT::i64;
2831 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2833 MachineFunction &MF = DAG.getMachineFunction();
2835 // Mark this function as potentially containing a function that contains a
2836 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2837 // and restoring the callers stack pointer in this functions epilog. This is
2838 // done because by tail calling the called function might overwrite the value
2839 // in this function's (MF) stack pointer stack slot 0(SP).
2840 if (PerformTailCallOpt && CallConv==CallingConv::Fast)
2841 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2843 unsigned nAltivecParamsAtEnd = 0;
2845 // Count how many bytes are to be pushed on the stack, including the linkage
2846 // area, and parameter passing area. We start with 24/48 bytes, which is
2847 // prereserved space for [SP][CR][LR][3 x unused].
2849 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2851 nAltivecParamsAtEnd);
2853 // Calculate by how many bytes the stack has to be adjusted in case of tail
2854 // call optimization.
2855 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2857 // To protect arguments on the stack from being clobbered in a tail call,
2858 // force all the loads to happen before doing any other lowering.
2860 Chain = DAG.getStackArgumentTokenFactor(Chain);
2862 // Adjust the stack pointer for the new arguments...
2863 // These operations are automatically eliminated by the prolog/epilog pass
2864 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2865 SDValue CallSeqStart = Chain;
2867 // Load the return address and frame pointer so it can be move somewhere else
2870 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2873 // Set up a copy of the stack pointer for use loading and storing any
2874 // arguments that may not fit in the registers available for argument
2878 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2880 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2882 // Figure out which arguments are going to go in registers, and which in
2883 // memory. Also, if this is a vararg function, floating point operations
2884 // must be stored to our stack, and loaded into integer regs as well, if
2885 // any integer regs are available for argument passing.
2886 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
2887 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2889 static const unsigned GPR_32[] = { // 32-bit registers.
2890 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2891 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2893 static const unsigned GPR_64[] = { // 64-bit registers.
2894 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2895 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2897 static const unsigned *FPR = GetFPR();
2899 static const unsigned VR[] = {
2900 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2901 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2903 const unsigned NumGPRs = array_lengthof(GPR_32);
2904 const unsigned NumFPRs = 13;
2905 const unsigned NumVRs = array_lengthof(VR);
2907 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2909 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2910 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2912 SmallVector<SDValue, 8> MemOpChains;
2913 for (unsigned i = 0; i != NumOps; ++i) {
2914 SDValue Arg = Outs[i].Val;
2915 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2917 // PtrOff will be used to store the current argument to the stack if a
2918 // register cannot be found for it.
2921 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2923 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
2925 // On PPC64, promote integers to 64-bit values.
2926 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2927 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2928 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2929 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
2932 // FIXME memcpy is used way more than necessary. Correctness first.
2933 if (Flags.isByVal()) {
2934 unsigned Size = Flags.getByValSize();
2935 if (Size==1 || Size==2) {
2936 // Very small objects are passed right-justified.
2937 // Everything else is passed left-justified.
2938 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2939 if (GPR_idx != NumGPRs) {
2940 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
2942 MemOpChains.push_back(Load.getValue(1));
2943 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2945 ArgOffset += PtrByteSize;
2947 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2948 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
2949 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2950 CallSeqStart.getNode()->getOperand(0),
2952 // This must go outside the CALLSEQ_START..END.
2953 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2954 CallSeqStart.getNode()->getOperand(1));
2955 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2956 NewCallSeqStart.getNode());
2957 Chain = CallSeqStart = NewCallSeqStart;
2958 ArgOffset += PtrByteSize;
2962 // Copy entire object into memory. There are cases where gcc-generated
2963 // code assumes it is there, even if it could be put entirely into
2964 // registers. (This is not what the doc says.)
2965 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2966 CallSeqStart.getNode()->getOperand(0),
2968 // This must go outside the CALLSEQ_START..END.
2969 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2970 CallSeqStart.getNode()->getOperand(1));
2971 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2972 Chain = CallSeqStart = NewCallSeqStart;
2973 // And copy the pieces of it that fit into registers.
2974 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2975 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
2976 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2977 if (GPR_idx != NumGPRs) {
2978 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
2979 MemOpChains.push_back(Load.getValue(1));
2980 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2981 ArgOffset += PtrByteSize;
2983 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2990 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
2991 default: llvm_unreachable("Unexpected ValueType for argument!");
2994 if (GPR_idx != NumGPRs) {
2995 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2997 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2998 isPPC64, isTailCall, false, MemOpChains,
2999 TailCallArguments, dl);
3001 ArgOffset += PtrByteSize;
3005 if (FPR_idx != NumFPRs) {
3006 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3009 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
3010 MemOpChains.push_back(Store);
3012 // Float varargs are always shadowed in available integer registers
3013 if (GPR_idx != NumGPRs) {
3014 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
3015 MemOpChains.push_back(Load.getValue(1));
3016 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3018 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3019 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3020 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3021 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
3022 MemOpChains.push_back(Load.getValue(1));
3023 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3026 // If we have any FPRs remaining, we may also have GPRs remaining.
3027 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3029 if (GPR_idx != NumGPRs)
3031 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3032 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3036 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3037 isPPC64, isTailCall, false, MemOpChains,
3038 TailCallArguments, dl);
3043 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3050 // These go aligned on the stack, or in the corresponding R registers
3051 // when within range. The Darwin PPC ABI doc claims they also go in
3052 // V registers; in fact gcc does this only for arguments that are
3053 // prototyped, not for those that match the ... We do it for all
3054 // arguments, seems to work.
3055 while (ArgOffset % 16 !=0) {
3056 ArgOffset += PtrByteSize;
3057 if (GPR_idx != NumGPRs)
3060 // We could elide this store in the case where the object fits
3061 // entirely in R registers. Maybe later.
3062 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3063 DAG.getConstant(ArgOffset, PtrVT));
3064 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
3065 MemOpChains.push_back(Store);
3066 if (VR_idx != NumVRs) {
3067 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
3068 MemOpChains.push_back(Load.getValue(1));
3069 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3072 for (unsigned i=0; i<16; i+=PtrByteSize) {
3073 if (GPR_idx == NumGPRs)
3075 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3076 DAG.getConstant(i, PtrVT));
3077 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
3078 MemOpChains.push_back(Load.getValue(1));
3079 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3084 // Non-varargs Altivec params generally go in registers, but have
3085 // stack space allocated at the end.
3086 if (VR_idx != NumVRs) {
3087 // Doesn't have GPR space allocated.
3088 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3089 } else if (nAltivecParamsAtEnd==0) {
3090 // We are emitting Altivec params in order.
3091 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3092 isPPC64, isTailCall, true, MemOpChains,
3093 TailCallArguments, dl);
3099 // If all Altivec parameters fit in registers, as they usually do,
3100 // they get stack space following the non-Altivec parameters. We
3101 // don't track this here because nobody below needs it.
3102 // If there are more Altivec parameters than fit in registers emit
3104 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3106 // Offset is aligned; skip 1st 12 params which go in V registers.
3107 ArgOffset = ((ArgOffset+15)/16)*16;
3109 for (unsigned i = 0; i != NumOps; ++i) {
3110 SDValue Arg = Outs[i].Val;
3111 EVT ArgType = Arg.getValueType();
3112 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3113 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3116 // We are emitting Altivec params in order.
3117 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3118 isPPC64, isTailCall, true, MemOpChains,
3119 TailCallArguments, dl);
3126 if (!MemOpChains.empty())
3127 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3128 &MemOpChains[0], MemOpChains.size());
3130 // Build a sequence of copy-to-reg nodes chained together with token chain
3131 // and flag operands which copy the outgoing args into the appropriate regs.
3133 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3134 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3135 RegsToPass[i].second, InFlag);
3136 InFlag = Chain.getValue(1);
3140 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3141 FPOp, true, TailCallArguments);
3144 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3145 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3150 PPCTargetLowering::LowerReturn(SDValue Chain,
3151 CallingConv::ID CallConv, bool isVarArg,
3152 const SmallVectorImpl<ISD::OutputArg> &Outs,
3153 DebugLoc dl, SelectionDAG &DAG) {
3155 SmallVector<CCValAssign, 16> RVLocs;
3156 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3157 RVLocs, *DAG.getContext());
3158 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3160 // If this is the first return lowered for this function, add the regs to the
3161 // liveout set for the function.
3162 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3163 for (unsigned i = 0; i != RVLocs.size(); ++i)
3164 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3169 // Copy the result values into the output registers.
3170 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3171 CCValAssign &VA = RVLocs[i];
3172 assert(VA.isRegLoc() && "Can only return in registers!");
3173 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3175 Flag = Chain.getValue(1);
3179 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3181 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3184 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3185 const PPCSubtarget &Subtarget) {
3186 // When we pop the dynamic allocation we need to restore the SP link.
3187 DebugLoc dl = Op.getDebugLoc();
3189 // Get the corect type for pointers.
3190 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3192 // Construct the stack pointer operand.
3193 bool IsPPC64 = Subtarget.isPPC64();
3194 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
3195 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3197 // Get the operands for the STACKRESTORE.
3198 SDValue Chain = Op.getOperand(0);
3199 SDValue SaveSP = Op.getOperand(1);
3201 // Load the old link SP.
3202 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
3204 // Restore the stack pointer.
3205 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3207 // Store the old link SP.
3208 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
3214 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3215 MachineFunction &MF = DAG.getMachineFunction();
3216 bool IsPPC64 = PPCSubTarget.isPPC64();
3217 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3218 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3220 // Get current frame pointer save index. The users of this index will be
3221 // primarily DYNALLOC instructions.
3222 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3223 int RASI = FI->getReturnAddrSaveIndex();
3225 // If the frame pointer save index hasn't been defined yet.
3227 // Find out what the fix offset of the frame pointer save area.
3228 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
3229 // Allocate the frame index for frame pointer save area.
3230 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset,
3233 FI->setReturnAddrSaveIndex(RASI);
3235 return DAG.getFrameIndex(RASI, PtrVT);
3239 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3240 MachineFunction &MF = DAG.getMachineFunction();
3241 bool IsPPC64 = PPCSubTarget.isPPC64();
3242 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3243 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3245 // Get current frame pointer save index. The users of this index will be
3246 // primarily DYNALLOC instructions.
3247 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3248 int FPSI = FI->getFramePointerSaveIndex();
3250 // If the frame pointer save index hasn't been defined yet.
3252 // Find out what the fix offset of the frame pointer save area.
3253 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
3256 // Allocate the frame index for frame pointer save area.
3257 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset,
3260 FI->setFramePointerSaveIndex(FPSI);
3262 return DAG.getFrameIndex(FPSI, PtrVT);
3265 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3267 const PPCSubtarget &Subtarget) {
3269 SDValue Chain = Op.getOperand(0);
3270 SDValue Size = Op.getOperand(1);
3271 DebugLoc dl = Op.getDebugLoc();
3273 // Get the corect type for pointers.
3274 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3276 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3277 DAG.getConstant(0, PtrVT), Size);
3278 // Construct a node for the frame pointer save index.
3279 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3280 // Build a DYNALLOC node.
3281 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3282 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3283 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3286 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3288 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
3289 // Not FP? Not a fsel.
3290 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3291 !Op.getOperand(2).getValueType().isFloatingPoint())
3294 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3296 // Cannot handle SETEQ/SETNE.
3297 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3299 EVT ResVT = Op.getValueType();
3300 EVT CmpVT = Op.getOperand(0).getValueType();
3301 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3302 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3303 DebugLoc dl = Op.getDebugLoc();
3305 // If the RHS of the comparison is a 0.0, we don't need to do the
3306 // subtraction at all.
3307 if (isFloatingPointZero(RHS))
3309 default: break; // SETUO etc aren't handled by fsel.
3312 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3315 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3316 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3317 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3320 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3323 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3324 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3325 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3326 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3331 default: break; // SETUO etc aren't handled by fsel.
3334 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3335 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3336 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3337 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3340 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3341 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3342 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3343 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3346 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3347 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3348 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3349 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3352 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3353 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3354 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3355 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3360 // FIXME: Split this code up when LegalizeDAGTypes lands.
3361 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3363 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3364 SDValue Src = Op.getOperand(0);
3365 if (Src.getValueType() == MVT::f32)
3366 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3369 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3370 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3372 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3377 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3381 // Convert the FP value to an int value through memory.
3382 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3384 // Emit a store to the stack slot.
3385 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
3387 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3389 if (Op.getValueType() == MVT::i32)
3390 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3391 DAG.getConstant(4, FIPtr.getValueType()));
3392 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
3395 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3396 DebugLoc dl = Op.getDebugLoc();
3397 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3398 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3401 if (Op.getOperand(0).getValueType() == MVT::i64) {
3402 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
3403 MVT::f64, Op.getOperand(0));
3404 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3405 if (Op.getValueType() == MVT::f32)
3406 FP = DAG.getNode(ISD::FP_ROUND, dl,
3407 MVT::f32, FP, DAG.getIntPtrConstant(0));
3411 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3412 "Unhandled SINT_TO_FP type in custom expander!");
3413 // Since we only generate this in 64-bit mode, we can take advantage of
3414 // 64-bit registers. In particular, sign extend the input value into the
3415 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3416 // then lfd it and fcfid it.
3417 MachineFunction &MF = DAG.getMachineFunction();
3418 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3419 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3420 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3421 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3423 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3426 // STD the extended value into the stack slot.
3427 MachineMemOperand *MMO =
3428 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
3429 MachineMemOperand::MOStore, 0, 8, 8);
3430 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3432 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3433 Ops, 4, MVT::i64, MMO);
3434 // Load the value as a double.
3435 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
3437 // FCFID it and return it.
3438 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3439 if (Op.getValueType() == MVT::f32)
3440 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3444 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
3445 DebugLoc dl = Op.getDebugLoc();
3447 The rounding mode is in bits 30:31 of FPSR, and has the following
3454 FLT_ROUNDS, on the other hand, expects the following:
3461 To perform the conversion, we do:
3462 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3465 MachineFunction &MF = DAG.getMachineFunction();
3466 EVT VT = Op.getValueType();
3467 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3468 std::vector<EVT> NodeTys;
3469 SDValue MFFSreg, InFlag;
3471 // Save FP Control Word to register
3472 NodeTys.push_back(MVT::f64); // return register
3473 NodeTys.push_back(MVT::Flag); // unused in this context
3474 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3476 // Save FP register to stack slot
3477 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3478 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3479 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3480 StackSlot, NULL, 0);
3482 // Load FP Control Word from low 32 bits of stack slot.
3483 SDValue Four = DAG.getConstant(4, PtrVT);
3484 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3485 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
3487 // Transform as necessary
3489 DAG.getNode(ISD::AND, dl, MVT::i32,
3490 CWD, DAG.getConstant(3, MVT::i32));
3492 DAG.getNode(ISD::SRL, dl, MVT::i32,
3493 DAG.getNode(ISD::AND, dl, MVT::i32,
3494 DAG.getNode(ISD::XOR, dl, MVT::i32,
3495 CWD, DAG.getConstant(3, MVT::i32)),
3496 DAG.getConstant(3, MVT::i32)),
3497 DAG.getConstant(1, MVT::i32));
3500 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3502 return DAG.getNode((VT.getSizeInBits() < 16 ?
3503 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3506 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
3507 EVT VT = Op.getValueType();
3508 unsigned BitWidth = VT.getSizeInBits();
3509 DebugLoc dl = Op.getDebugLoc();
3510 assert(Op.getNumOperands() == 3 &&
3511 VT == Op.getOperand(1).getValueType() &&
3514 // Expand into a bunch of logical ops. Note that these ops
3515 // depend on the PPC behavior for oversized shift amounts.
3516 SDValue Lo = Op.getOperand(0);
3517 SDValue Hi = Op.getOperand(1);
3518 SDValue Amt = Op.getOperand(2);
3519 EVT AmtVT = Amt.getValueType();
3521 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3522 DAG.getConstant(BitWidth, AmtVT), Amt);
3523 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3524 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3525 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3526 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3527 DAG.getConstant(-BitWidth, AmtVT));
3528 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3529 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3530 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3531 SDValue OutOps[] = { OutLo, OutHi };
3532 return DAG.getMergeValues(OutOps, 2, dl);
3535 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3536 EVT VT = Op.getValueType();
3537 DebugLoc dl = Op.getDebugLoc();
3538 unsigned BitWidth = VT.getSizeInBits();
3539 assert(Op.getNumOperands() == 3 &&
3540 VT == Op.getOperand(1).getValueType() &&
3543 // Expand into a bunch of logical ops. Note that these ops
3544 // depend on the PPC behavior for oversized shift amounts.
3545 SDValue Lo = Op.getOperand(0);
3546 SDValue Hi = Op.getOperand(1);
3547 SDValue Amt = Op.getOperand(2);
3548 EVT AmtVT = Amt.getValueType();
3550 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3551 DAG.getConstant(BitWidth, AmtVT), Amt);
3552 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3553 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3554 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3555 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3556 DAG.getConstant(-BitWidth, AmtVT));
3557 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3558 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3559 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3560 SDValue OutOps[] = { OutLo, OutHi };
3561 return DAG.getMergeValues(OutOps, 2, dl);
3564 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3565 DebugLoc dl = Op.getDebugLoc();
3566 EVT VT = Op.getValueType();
3567 unsigned BitWidth = VT.getSizeInBits();
3568 assert(Op.getNumOperands() == 3 &&
3569 VT == Op.getOperand(1).getValueType() &&
3572 // Expand into a bunch of logical ops, followed by a select_cc.
3573 SDValue Lo = Op.getOperand(0);
3574 SDValue Hi = Op.getOperand(1);
3575 SDValue Amt = Op.getOperand(2);
3576 EVT AmtVT = Amt.getValueType();
3578 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3579 DAG.getConstant(BitWidth, AmtVT), Amt);
3580 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3581 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3582 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3583 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3584 DAG.getConstant(-BitWidth, AmtVT));
3585 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3586 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3587 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3588 Tmp4, Tmp6, ISD::SETLE);
3589 SDValue OutOps[] = { OutLo, OutHi };
3590 return DAG.getMergeValues(OutOps, 2, dl);
3593 //===----------------------------------------------------------------------===//
3594 // Vector related lowering.
3597 /// BuildSplatI - Build a canonical splati of Val with an element size of
3598 /// SplatSize. Cast the result to VT.
3599 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3600 SelectionDAG &DAG, DebugLoc dl) {
3601 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3603 static const EVT VTys[] = { // canonical VT to use for each size.
3604 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3607 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3609 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3613 EVT CanonicalVT = VTys[SplatSize-1];
3615 // Build a canonical splat for this value.
3616 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3617 SmallVector<SDValue, 8> Ops;
3618 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3619 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3620 &Ops[0], Ops.size());
3621 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3624 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3625 /// specified intrinsic ID.
3626 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3627 SelectionDAG &DAG, DebugLoc dl,
3628 EVT DestVT = MVT::Other) {
3629 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3630 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3631 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3634 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3635 /// specified intrinsic ID.
3636 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3637 SDValue Op2, SelectionDAG &DAG,
3638 DebugLoc dl, EVT DestVT = MVT::Other) {
3639 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3640 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3641 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3645 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3646 /// amount. The result has the specified value type.
3647 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3648 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3649 // Force LHS/RHS to be the right type.
3650 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3651 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3654 for (unsigned i = 0; i != 16; ++i)
3656 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3657 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3660 // If this is a case we can't handle, return null and let the default
3661 // expansion code take care of it. If we CAN select this case, and if it
3662 // selects to a single instruction, return Op. Otherwise, if we can codegen
3663 // this case more efficiently than a constant pool load, lower it to the
3664 // sequence of ops that should be used.
3665 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3666 DebugLoc dl = Op.getDebugLoc();
3667 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3668 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3670 // Check if this is a splat of a constant value.
3671 APInt APSplatBits, APSplatUndef;
3672 unsigned SplatBitSize;
3674 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3675 HasAnyUndefs, 0, true) || SplatBitSize > 32)
3678 unsigned SplatBits = APSplatBits.getZExtValue();
3679 unsigned SplatUndef = APSplatUndef.getZExtValue();
3680 unsigned SplatSize = SplatBitSize / 8;
3682 // First, handle single instruction cases.
3685 if (SplatBits == 0) {
3686 // Canonicalize all zero vectors to be v4i32.
3687 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3688 SDValue Z = DAG.getConstant(0, MVT::i32);
3689 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3690 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3695 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3696 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3698 if (SextVal >= -16 && SextVal <= 15)
3699 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3702 // Two instruction sequences.
3704 // If this value is in the range [-32,30] and is even, use:
3705 // tmp = VSPLTI[bhw], result = add tmp, tmp
3706 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3707 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3708 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3709 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3712 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3713 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3715 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3716 // Make -1 and vspltisw -1:
3717 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3719 // Make the VSLW intrinsic, computing 0x8000_0000.
3720 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3723 // xor by OnesV to invert it.
3724 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3725 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3728 // Check to see if this is a wide variety of vsplti*, binop self cases.
3729 static const signed char SplatCsts[] = {
3730 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3731 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3734 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3735 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3736 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3737 int i = SplatCsts[idx];
3739 // Figure out what shift amount will be used by altivec if shifted by i in
3741 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3743 // vsplti + shl self.
3744 if (SextVal == (i << (int)TypeShiftAmt)) {
3745 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3746 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3747 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3748 Intrinsic::ppc_altivec_vslw
3750 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3751 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3754 // vsplti + srl self.
3755 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3756 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3757 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3758 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3759 Intrinsic::ppc_altivec_vsrw
3761 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3762 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3765 // vsplti + sra self.
3766 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3767 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3768 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3769 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3770 Intrinsic::ppc_altivec_vsraw
3772 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3773 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3776 // vsplti + rol self.
3777 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3778 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3779 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3780 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3781 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3782 Intrinsic::ppc_altivec_vrlw
3784 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3785 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3788 // t = vsplti c, result = vsldoi t, t, 1
3789 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3790 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3791 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3793 // t = vsplti c, result = vsldoi t, t, 2
3794 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3795 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3796 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3798 // t = vsplti c, result = vsldoi t, t, 3
3799 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3800 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3801 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3805 // Three instruction sequences.
3807 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3808 if (SextVal >= 0 && SextVal <= 31) {
3809 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3810 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3811 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3812 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3814 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3815 if (SextVal >= -31 && SextVal <= 0) {
3816 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3817 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3818 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3819 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3825 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3826 /// the specified operations to build the shuffle.
3827 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3828 SDValue RHS, SelectionDAG &DAG,
3830 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3831 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3832 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3835 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3847 if (OpNum == OP_COPY) {
3848 if (LHSID == (1*9+2)*9+3) return LHS;
3849 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3853 SDValue OpLHS, OpRHS;
3854 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3855 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3859 default: llvm_unreachable("Unknown i32 permute!");
3861 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3862 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3863 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3864 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3867 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3868 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3869 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3870 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3873 for (unsigned i = 0; i != 16; ++i)
3874 ShufIdxs[i] = (i&3)+0;
3877 for (unsigned i = 0; i != 16; ++i)
3878 ShufIdxs[i] = (i&3)+4;
3881 for (unsigned i = 0; i != 16; ++i)
3882 ShufIdxs[i] = (i&3)+8;
3885 for (unsigned i = 0; i != 16; ++i)
3886 ShufIdxs[i] = (i&3)+12;
3889 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
3891 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
3893 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
3895 EVT VT = OpLHS.getValueType();
3896 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
3897 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
3898 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
3899 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3902 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3903 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3904 /// return the code it can be lowered into. Worst case, it can always be
3905 /// lowered into a vperm.
3906 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
3907 SelectionDAG &DAG) {
3908 DebugLoc dl = Op.getDebugLoc();
3909 SDValue V1 = Op.getOperand(0);
3910 SDValue V2 = Op.getOperand(1);
3911 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
3912 EVT VT = Op.getValueType();
3914 // Cases that are handled by instructions that take permute immediates
3915 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3916 // selected by the instruction selector.
3917 if (V2.getOpcode() == ISD::UNDEF) {
3918 if (PPC::isSplatShuffleMask(SVOp, 1) ||
3919 PPC::isSplatShuffleMask(SVOp, 2) ||
3920 PPC::isSplatShuffleMask(SVOp, 4) ||
3921 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
3922 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
3923 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
3924 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
3925 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
3926 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
3927 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
3928 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
3929 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
3934 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3935 // and produce a fixed permutation. If any of these match, do not lower to
3937 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
3938 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
3939 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
3940 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
3941 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
3942 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
3943 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
3944 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
3945 PPC::isVMRGHShuffleMask(SVOp, 4, false))
3948 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3949 // perfect shuffle table to emit an optimal matching sequence.
3950 SmallVector<int, 16> PermMask;
3951 SVOp->getMask(PermMask);
3953 unsigned PFIndexes[4];
3954 bool isFourElementShuffle = true;
3955 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3956 unsigned EltNo = 8; // Start out undef.
3957 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3958 if (PermMask[i*4+j] < 0)
3959 continue; // Undef, ignore it.
3961 unsigned ByteSource = PermMask[i*4+j];
3962 if ((ByteSource & 3) != j) {
3963 isFourElementShuffle = false;
3968 EltNo = ByteSource/4;
3969 } else if (EltNo != ByteSource/4) {
3970 isFourElementShuffle = false;
3974 PFIndexes[i] = EltNo;
3977 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3978 // perfect shuffle vector to determine if it is cost effective to do this as
3979 // discrete instructions, or whether we should use a vperm.
3980 if (isFourElementShuffle) {
3981 // Compute the index in the perfect shuffle table.
3982 unsigned PFTableIndex =
3983 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3985 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3986 unsigned Cost = (PFEntry >> 30);
3988 // Determining when to avoid vperm is tricky. Many things affect the cost
3989 // of vperm, particularly how many times the perm mask needs to be computed.
3990 // For example, if the perm mask can be hoisted out of a loop or is already
3991 // used (perhaps because there are multiple permutes with the same shuffle
3992 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3993 // the loop requires an extra register.
3995 // As a compromise, we only emit discrete instructions if the shuffle can be
3996 // generated in 3 or fewer operations. When we have loop information
3997 // available, if this block is within a loop, we should avoid using vperm
3998 // for 3-operation perms and use a constant pool load instead.
4000 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4003 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4004 // vector that will get spilled to the constant pool.
4005 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4007 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4008 // that it is in input element units, not in bytes. Convert now.
4009 EVT EltVT = V1.getValueType().getVectorElementType();
4010 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4012 SmallVector<SDValue, 16> ResultMask;
4013 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4014 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4016 for (unsigned j = 0; j != BytesPerElement; ++j)
4017 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4021 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4022 &ResultMask[0], ResultMask.size());
4023 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4026 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4027 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4028 /// information about the intrinsic.
4029 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4031 unsigned IntrinsicID =
4032 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4035 switch (IntrinsicID) {
4036 default: return false;
4037 // Comparison predicates.
4038 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4039 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4040 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4041 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4042 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4043 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4044 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4045 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4046 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4047 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4048 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4049 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4050 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4052 // Normal Comparisons.
4053 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4054 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4055 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4056 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4057 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4058 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4059 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4060 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4061 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4062 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4063 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4064 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4065 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4070 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4071 /// lower, do it, otherwise return null.
4072 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4073 SelectionDAG &DAG) {
4074 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4075 // opcode number of the comparison.
4076 DebugLoc dl = Op.getDebugLoc();
4079 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4080 return SDValue(); // Don't custom lower most intrinsics.
4082 // If this is a non-dot comparison, make the VCMP node and we are done.
4084 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4085 Op.getOperand(1), Op.getOperand(2),
4086 DAG.getConstant(CompareOpc, MVT::i32));
4087 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
4090 // Create the PPCISD altivec 'dot' comparison node.
4092 Op.getOperand(2), // LHS
4093 Op.getOperand(3), // RHS
4094 DAG.getConstant(CompareOpc, MVT::i32)
4096 std::vector<EVT> VTs;
4097 VTs.push_back(Op.getOperand(2).getValueType());
4098 VTs.push_back(MVT::Flag);
4099 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4101 // Now that we have the comparison, emit a copy from the CR to a GPR.
4102 // This is flagged to the above dot comparison.
4103 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4104 DAG.getRegister(PPC::CR6, MVT::i32),
4105 CompNode.getValue(1));
4107 // Unpack the result based on how the target uses it.
4108 unsigned BitNo; // Bit # of CR6.
4109 bool InvertBit; // Invert result?
4110 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4111 default: // Can't happen, don't crash on invalid number though.
4112 case 0: // Return the value of the EQ bit of CR6.
4113 BitNo = 0; InvertBit = false;
4115 case 1: // Return the inverted value of the EQ bit of CR6.
4116 BitNo = 0; InvertBit = true;
4118 case 2: // Return the value of the LT bit of CR6.
4119 BitNo = 2; InvertBit = false;
4121 case 3: // Return the inverted value of the LT bit of CR6.
4122 BitNo = 2; InvertBit = true;
4126 // Shift the bit into the low position.
4127 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4128 DAG.getConstant(8-(3-BitNo), MVT::i32));
4130 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4131 DAG.getConstant(1, MVT::i32));
4133 // If we are supposed to, toggle the bit.
4135 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4136 DAG.getConstant(1, MVT::i32));
4140 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4141 SelectionDAG &DAG) {
4142 DebugLoc dl = Op.getDebugLoc();
4143 // Create a stack slot that is 16-byte aligned.
4144 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4145 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4146 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4147 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4149 // Store the input value into Value#0 of the stack slot.
4150 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4151 Op.getOperand(0), FIdx, NULL, 0);
4153 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0);
4156 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
4157 DebugLoc dl = Op.getDebugLoc();
4158 if (Op.getValueType() == MVT::v4i32) {
4159 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4161 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4162 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4164 SDValue RHSSwap = // = vrlw RHS, 16
4165 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4167 // Shrinkify inputs to v8i16.
4168 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
4169 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
4170 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
4172 // Low parts multiplied together, generating 32-bit results (we ignore the
4174 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4175 LHS, RHS, DAG, dl, MVT::v4i32);
4177 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4178 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4179 // Shift the high parts up 16 bits.
4180 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4182 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4183 } else if (Op.getValueType() == MVT::v8i16) {
4184 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4186 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4188 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4189 LHS, RHS, Zero, DAG, dl);
4190 } else if (Op.getValueType() == MVT::v16i8) {
4191 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4193 // Multiply the even 8-bit parts, producing 16-bit sums.
4194 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4195 LHS, RHS, DAG, dl, MVT::v8i16);
4196 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
4198 // Multiply the odd 8-bit parts, producing 16-bit sums.
4199 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4200 LHS, RHS, DAG, dl, MVT::v8i16);
4201 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
4203 // Merge the results together.
4205 for (unsigned i = 0; i != 8; ++i) {
4207 Ops[i*2+1] = 2*i+1+16;
4209 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4211 llvm_unreachable("Unknown mul to lower!");
4215 /// LowerOperation - Provide custom lowering hooks for some operations.
4217 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4218 switch (Op.getOpcode()) {
4219 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4220 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4221 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4222 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4223 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4224 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4225 case ISD::SETCC: return LowerSETCC(Op, DAG);
4226 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4228 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4229 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4232 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4233 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4235 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4236 case ISD::DYNAMIC_STACKALLOC:
4237 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4239 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4240 case ISD::FP_TO_UINT:
4241 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4243 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4244 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4246 // Lower 64-bit shifts.
4247 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4248 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4249 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4251 // Vector-related lowering.
4252 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4253 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4254 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4255 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4256 case ISD::MUL: return LowerMUL(Op, DAG);
4258 // Frame & Return address.
4259 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4260 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4265 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4266 SmallVectorImpl<SDValue>&Results,
4267 SelectionDAG &DAG) {
4268 DebugLoc dl = N->getDebugLoc();
4269 switch (N->getOpcode()) {
4271 assert(false && "Do not know how to custom type legalize this operation!");
4273 case ISD::FP_ROUND_INREG: {
4274 assert(N->getValueType(0) == MVT::ppcf128);
4275 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4276 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4277 MVT::f64, N->getOperand(0),
4278 DAG.getIntPtrConstant(0));
4279 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4280 MVT::f64, N->getOperand(0),
4281 DAG.getIntPtrConstant(1));
4283 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4284 // of the long double, and puts FPSCR back the way it was. We do not
4285 // actually model FPSCR.
4286 std::vector<EVT> NodeTys;
4287 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4289 NodeTys.push_back(MVT::f64); // Return register
4290 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
4291 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4292 MFFSreg = Result.getValue(0);
4293 InFlag = Result.getValue(1);
4296 NodeTys.push_back(MVT::Flag); // Returns a flag
4297 Ops[0] = DAG.getConstant(31, MVT::i32);
4299 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4300 InFlag = Result.getValue(0);
4303 NodeTys.push_back(MVT::Flag); // Returns a flag
4304 Ops[0] = DAG.getConstant(30, MVT::i32);
4306 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4307 InFlag = Result.getValue(0);
4310 NodeTys.push_back(MVT::f64); // result of add
4311 NodeTys.push_back(MVT::Flag); // Returns a flag
4315 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4316 FPreg = Result.getValue(0);
4317 InFlag = Result.getValue(1);
4320 NodeTys.push_back(MVT::f64);
4321 Ops[0] = DAG.getConstant(1, MVT::i32);
4325 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4326 FPreg = Result.getValue(0);
4328 // We know the low half is about to be thrown away, so just use something
4330 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4334 case ISD::FP_TO_SINT:
4335 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4341 //===----------------------------------------------------------------------===//
4342 // Other Lowering Code
4343 //===----------------------------------------------------------------------===//
4346 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4347 bool is64bit, unsigned BinOpcode) const {
4348 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4349 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4351 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4352 MachineFunction *F = BB->getParent();
4353 MachineFunction::iterator It = BB;
4356 unsigned dest = MI->getOperand(0).getReg();
4357 unsigned ptrA = MI->getOperand(1).getReg();
4358 unsigned ptrB = MI->getOperand(2).getReg();
4359 unsigned incr = MI->getOperand(3).getReg();
4360 DebugLoc dl = MI->getDebugLoc();
4362 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4363 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4364 F->insert(It, loopMBB);
4365 F->insert(It, exitMBB);
4366 exitMBB->transferSuccessors(BB);
4368 MachineRegisterInfo &RegInfo = F->getRegInfo();
4369 unsigned TmpReg = (!BinOpcode) ? incr :
4370 RegInfo.createVirtualRegister(
4371 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4372 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4376 // fallthrough --> loopMBB
4377 BB->addSuccessor(loopMBB);
4380 // l[wd]arx dest, ptr
4381 // add r0, dest, incr
4382 // st[wd]cx. r0, ptr
4384 // fallthrough --> exitMBB
4386 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4387 .addReg(ptrA).addReg(ptrB);
4389 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4390 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4391 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4392 BuildMI(BB, dl, TII->get(PPC::BCC))
4393 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4394 BB->addSuccessor(loopMBB);
4395 BB->addSuccessor(exitMBB);
4404 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4405 MachineBasicBlock *BB,
4406 bool is8bit, // operation
4407 unsigned BinOpcode) const {
4408 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4409 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4410 // In 64 bit mode we have to use 64 bits for addresses, even though the
4411 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4412 // registers without caring whether they're 32 or 64, but here we're
4413 // doing actual arithmetic on the addresses.
4414 bool is64bit = PPCSubTarget.isPPC64();
4416 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4417 MachineFunction *F = BB->getParent();
4418 MachineFunction::iterator It = BB;
4421 unsigned dest = MI->getOperand(0).getReg();
4422 unsigned ptrA = MI->getOperand(1).getReg();
4423 unsigned ptrB = MI->getOperand(2).getReg();
4424 unsigned incr = MI->getOperand(3).getReg();
4425 DebugLoc dl = MI->getDebugLoc();
4427 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4428 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4429 F->insert(It, loopMBB);
4430 F->insert(It, exitMBB);
4431 exitMBB->transferSuccessors(BB);
4433 MachineRegisterInfo &RegInfo = F->getRegInfo();
4434 const TargetRegisterClass *RC =
4435 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4436 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4437 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4438 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4439 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4440 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4441 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4442 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4443 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4444 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4445 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4446 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4447 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4449 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4453 // fallthrough --> loopMBB
4454 BB->addSuccessor(loopMBB);
4456 // The 4-byte load must be aligned, while a char or short may be
4457 // anywhere in the word. Hence all this nasty bookkeeping code.
4458 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4459 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4460 // xori shift, shift1, 24 [16]
4461 // rlwinm ptr, ptr1, 0, 0, 29
4462 // slw incr2, incr, shift
4463 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4464 // slw mask, mask2, shift
4466 // lwarx tmpDest, ptr
4467 // add tmp, tmpDest, incr2
4468 // andc tmp2, tmpDest, mask
4469 // and tmp3, tmp, mask
4470 // or tmp4, tmp3, tmp2
4473 // fallthrough --> exitMBB
4474 // srw dest, tmpDest, shift
4476 if (ptrA!=PPC::R0) {
4477 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4478 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4479 .addReg(ptrA).addReg(ptrB);
4483 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4484 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4485 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4486 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4488 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4489 .addReg(Ptr1Reg).addImm(0).addImm(61);
4491 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4492 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4493 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4494 .addReg(incr).addReg(ShiftReg);
4496 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4498 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4499 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4501 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4502 .addReg(Mask2Reg).addReg(ShiftReg);
4505 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4506 .addReg(PPC::R0).addReg(PtrReg);
4508 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4509 .addReg(Incr2Reg).addReg(TmpDestReg);
4510 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4511 .addReg(TmpDestReg).addReg(MaskReg);
4512 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4513 .addReg(TmpReg).addReg(MaskReg);
4514 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4515 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4516 BuildMI(BB, dl, TII->get(PPC::STWCX))
4517 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4518 BuildMI(BB, dl, TII->get(PPC::BCC))
4519 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4520 BB->addSuccessor(loopMBB);
4521 BB->addSuccessor(exitMBB);
4526 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4531 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4532 MachineBasicBlock *BB,
4533 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
4534 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4536 // To "insert" these instructions we actually have to insert their
4537 // control-flow patterns.
4538 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4539 MachineFunction::iterator It = BB;
4542 MachineFunction *F = BB->getParent();
4544 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4545 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4546 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4547 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4548 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4550 // The incoming instruction knows the destination vreg to set, the
4551 // condition code register to branch on, the true/false values to
4552 // select between, and a branch opcode to use.
4557 // cmpTY ccX, r1, r2
4559 // fallthrough --> copy0MBB
4560 MachineBasicBlock *thisMBB = BB;
4561 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4562 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4563 unsigned SelectPred = MI->getOperand(4).getImm();
4564 DebugLoc dl = MI->getDebugLoc();
4565 BuildMI(BB, dl, TII->get(PPC::BCC))
4566 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4567 F->insert(It, copy0MBB);
4568 F->insert(It, sinkMBB);
4569 // Update machine-CFG edges by first adding all successors of the current
4570 // block to the new block which will contain the Phi node for the select.
4571 // Also inform sdisel of the edge changes.
4572 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
4573 E = BB->succ_end(); I != E; ++I) {
4574 EM->insert(std::make_pair(*I, sinkMBB));
4575 sinkMBB->addSuccessor(*I);
4577 // Next, remove all successors of the current block, and add the true
4578 // and fallthrough blocks as its successors.
4579 while (!BB->succ_empty())
4580 BB->removeSuccessor(BB->succ_begin());
4581 // Next, add the true and fallthrough blocks as its successors.
4582 BB->addSuccessor(copy0MBB);
4583 BB->addSuccessor(sinkMBB);
4586 // %FalseValue = ...
4587 // # fallthrough to sinkMBB
4590 // Update machine-CFG edges
4591 BB->addSuccessor(sinkMBB);
4594 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4597 BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4598 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4599 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4601 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4602 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4603 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4604 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4605 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4606 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4607 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4608 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4610 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4611 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4612 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4613 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4614 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4615 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4616 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4617 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4619 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4620 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4621 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4622 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4623 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4624 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4625 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4626 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4628 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4629 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4630 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4631 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4632 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4633 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4634 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4635 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4637 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4638 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4639 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4640 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4641 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4642 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4643 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4644 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4646 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4647 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4648 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4649 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4650 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4651 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4652 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4653 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4655 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4656 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4657 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4658 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4659 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4660 BB = EmitAtomicBinary(MI, BB, false, 0);
4661 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4662 BB = EmitAtomicBinary(MI, BB, true, 0);
4664 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4665 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4666 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4668 unsigned dest = MI->getOperand(0).getReg();
4669 unsigned ptrA = MI->getOperand(1).getReg();
4670 unsigned ptrB = MI->getOperand(2).getReg();
4671 unsigned oldval = MI->getOperand(3).getReg();
4672 unsigned newval = MI->getOperand(4).getReg();
4673 DebugLoc dl = MI->getDebugLoc();
4675 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4676 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4677 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4678 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4679 F->insert(It, loop1MBB);
4680 F->insert(It, loop2MBB);
4681 F->insert(It, midMBB);
4682 F->insert(It, exitMBB);
4683 exitMBB->transferSuccessors(BB);
4687 // fallthrough --> loopMBB
4688 BB->addSuccessor(loop1MBB);
4691 // l[wd]arx dest, ptr
4692 // cmp[wd] dest, oldval
4695 // st[wd]cx. newval, ptr
4699 // st[wd]cx. dest, ptr
4702 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4703 .addReg(ptrA).addReg(ptrB);
4704 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4705 .addReg(oldval).addReg(dest);
4706 BuildMI(BB, dl, TII->get(PPC::BCC))
4707 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4708 BB->addSuccessor(loop2MBB);
4709 BB->addSuccessor(midMBB);
4712 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4713 .addReg(newval).addReg(ptrA).addReg(ptrB);
4714 BuildMI(BB, dl, TII->get(PPC::BCC))
4715 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4716 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4717 BB->addSuccessor(loop1MBB);
4718 BB->addSuccessor(exitMBB);
4721 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4722 .addReg(dest).addReg(ptrA).addReg(ptrB);
4723 BB->addSuccessor(exitMBB);
4728 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4729 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4730 // We must use 64-bit registers for addresses when targeting 64-bit,
4731 // since we're actually doing arithmetic on them. Other registers
4733 bool is64bit = PPCSubTarget.isPPC64();
4734 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4736 unsigned dest = MI->getOperand(0).getReg();
4737 unsigned ptrA = MI->getOperand(1).getReg();
4738 unsigned ptrB = MI->getOperand(2).getReg();
4739 unsigned oldval = MI->getOperand(3).getReg();
4740 unsigned newval = MI->getOperand(4).getReg();
4741 DebugLoc dl = MI->getDebugLoc();
4743 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4744 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4745 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4746 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4747 F->insert(It, loop1MBB);
4748 F->insert(It, loop2MBB);
4749 F->insert(It, midMBB);
4750 F->insert(It, exitMBB);
4751 exitMBB->transferSuccessors(BB);
4753 MachineRegisterInfo &RegInfo = F->getRegInfo();
4754 const TargetRegisterClass *RC =
4755 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4756 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4757 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4758 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4759 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4760 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4761 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4762 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4763 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4764 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4765 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4766 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4767 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4768 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4769 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4771 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4774 // fallthrough --> loopMBB
4775 BB->addSuccessor(loop1MBB);
4777 // The 4-byte load must be aligned, while a char or short may be
4778 // anywhere in the word. Hence all this nasty bookkeeping code.
4779 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4780 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4781 // xori shift, shift1, 24 [16]
4782 // rlwinm ptr, ptr1, 0, 0, 29
4783 // slw newval2, newval, shift
4784 // slw oldval2, oldval,shift
4785 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4786 // slw mask, mask2, shift
4787 // and newval3, newval2, mask
4788 // and oldval3, oldval2, mask
4790 // lwarx tmpDest, ptr
4791 // and tmp, tmpDest, mask
4792 // cmpw tmp, oldval3
4795 // andc tmp2, tmpDest, mask
4796 // or tmp4, tmp2, newval3
4801 // stwcx. tmpDest, ptr
4803 // srw dest, tmpDest, shift
4804 if (ptrA!=PPC::R0) {
4805 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4806 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4807 .addReg(ptrA).addReg(ptrB);
4811 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4812 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4813 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4814 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4816 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4817 .addReg(Ptr1Reg).addImm(0).addImm(61);
4819 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4820 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4821 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4822 .addReg(newval).addReg(ShiftReg);
4823 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4824 .addReg(oldval).addReg(ShiftReg);
4826 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4828 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4829 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4830 .addReg(Mask3Reg).addImm(65535);
4832 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4833 .addReg(Mask2Reg).addReg(ShiftReg);
4834 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
4835 .addReg(NewVal2Reg).addReg(MaskReg);
4836 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
4837 .addReg(OldVal2Reg).addReg(MaskReg);
4840 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4841 .addReg(PPC::R0).addReg(PtrReg);
4842 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
4843 .addReg(TmpDestReg).addReg(MaskReg);
4844 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
4845 .addReg(TmpReg).addReg(OldVal3Reg);
4846 BuildMI(BB, dl, TII->get(PPC::BCC))
4847 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4848 BB->addSuccessor(loop2MBB);
4849 BB->addSuccessor(midMBB);
4852 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
4853 .addReg(TmpDestReg).addReg(MaskReg);
4854 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
4855 .addReg(Tmp2Reg).addReg(NewVal3Reg);
4856 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4857 .addReg(PPC::R0).addReg(PtrReg);
4858 BuildMI(BB, dl, TII->get(PPC::BCC))
4859 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4860 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4861 BB->addSuccessor(loop1MBB);
4862 BB->addSuccessor(exitMBB);
4865 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4866 .addReg(PPC::R0).addReg(PtrReg);
4867 BB->addSuccessor(exitMBB);
4872 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4874 llvm_unreachable("Unexpected instr type to insert");
4877 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4881 //===----------------------------------------------------------------------===//
4882 // Target Optimization Hooks
4883 //===----------------------------------------------------------------------===//
4885 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4886 DAGCombinerInfo &DCI) const {
4887 TargetMachine &TM = getTargetMachine();
4888 SelectionDAG &DAG = DCI.DAG;
4889 DebugLoc dl = N->getDebugLoc();
4890 switch (N->getOpcode()) {
4893 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4894 if (C->getZExtValue() == 0) // 0 << V -> 0.
4895 return N->getOperand(0);
4899 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4900 if (C->getZExtValue() == 0) // 0 >>u V -> 0.
4901 return N->getOperand(0);
4905 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4906 if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
4907 C->isAllOnesValue()) // -1 >>s V -> -1.
4908 return N->getOperand(0);
4912 case ISD::SINT_TO_FP:
4913 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4914 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4915 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4916 // We allow the src/dst to be either f32/f64, but the intermediate
4917 // type must be i64.
4918 if (N->getOperand(0).getValueType() == MVT::i64 &&
4919 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4920 SDValue Val = N->getOperand(0).getOperand(0);
4921 if (Val.getValueType() == MVT::f32) {
4922 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4923 DCI.AddToWorklist(Val.getNode());
4926 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
4927 DCI.AddToWorklist(Val.getNode());
4928 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
4929 DCI.AddToWorklist(Val.getNode());
4930 if (N->getValueType(0) == MVT::f32) {
4931 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
4932 DAG.getIntPtrConstant(0));
4933 DCI.AddToWorklist(Val.getNode());
4936 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4937 // If the intermediate type is i32, we can avoid the load/store here
4944 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4945 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4946 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4947 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4948 N->getOperand(1).getValueType() == MVT::i32 &&
4949 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4950 SDValue Val = N->getOperand(1).getOperand(0);
4951 if (Val.getValueType() == MVT::f32) {
4952 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4953 DCI.AddToWorklist(Val.getNode());
4955 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
4956 DCI.AddToWorklist(Val.getNode());
4958 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
4959 N->getOperand(2), N->getOperand(3));
4960 DCI.AddToWorklist(Val.getNode());
4964 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4965 if (cast<StoreSDNode>(N)->isUnindexed() &&
4966 N->getOperand(1).getOpcode() == ISD::BSWAP &&
4967 N->getOperand(1).getNode()->hasOneUse() &&
4968 (N->getOperand(1).getValueType() == MVT::i32 ||
4969 N->getOperand(1).getValueType() == MVT::i16)) {
4970 SDValue BSwapOp = N->getOperand(1).getOperand(0);
4971 // Do an any-extend to 32-bits if this is a half-word input.
4972 if (BSwapOp.getValueType() == MVT::i16)
4973 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
4976 N->getOperand(0), BSwapOp, N->getOperand(2),
4977 DAG.getValueType(N->getOperand(1).getValueType())
4980 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
4981 Ops, array_lengthof(Ops),
4982 cast<StoreSDNode>(N)->getMemoryVT(),
4983 cast<StoreSDNode>(N)->getMemOperand());
4987 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4988 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
4989 N->getOperand(0).hasOneUse() &&
4990 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4991 SDValue Load = N->getOperand(0);
4992 LoadSDNode *LD = cast<LoadSDNode>(Load);
4993 // Create the byte-swapping load.
4995 LD->getChain(), // Chain
4996 LD->getBasePtr(), // Ptr
4997 DAG.getValueType(N->getValueType(0)) // VT
5000 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5001 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5002 LD->getMemoryVT(), LD->getMemOperand());
5004 // If this is an i16 load, insert the truncate.
5005 SDValue ResVal = BSLoad;
5006 if (N->getValueType(0) == MVT::i16)
5007 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5009 // First, combine the bswap away. This makes the value produced by the
5011 DCI.CombineTo(N, ResVal);
5013 // Next, combine the load away, we give it a bogus result value but a real
5014 // chain result. The result value is dead because the bswap is dead.
5015 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5017 // Return N so it doesn't get rechecked!
5018 return SDValue(N, 0);
5022 case PPCISD::VCMP: {
5023 // If a VCMPo node already exists with exactly the same operands as this
5024 // node, use its result instead of this node (VCMPo computes both a CR6 and
5025 // a normal output).
5027 if (!N->getOperand(0).hasOneUse() &&
5028 !N->getOperand(1).hasOneUse() &&
5029 !N->getOperand(2).hasOneUse()) {
5031 // Scan all of the users of the LHS, looking for VCMPo's that match.
5032 SDNode *VCMPoNode = 0;
5034 SDNode *LHSN = N->getOperand(0).getNode();
5035 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5037 if (UI->getOpcode() == PPCISD::VCMPo &&
5038 UI->getOperand(1) == N->getOperand(1) &&
5039 UI->getOperand(2) == N->getOperand(2) &&
5040 UI->getOperand(0) == N->getOperand(0)) {
5045 // If there is no VCMPo node, or if the flag value has a single use, don't
5047 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5050 // Look at the (necessarily single) use of the flag value. If it has a
5051 // chain, this transformation is more complex. Note that multiple things
5052 // could use the value result, which we should ignore.
5053 SDNode *FlagUser = 0;
5054 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5055 FlagUser == 0; ++UI) {
5056 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5058 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5059 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5066 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5067 // give up for right now.
5068 if (FlagUser->getOpcode() == PPCISD::MFCR)
5069 return SDValue(VCMPoNode, 0);
5074 // If this is a branch on an altivec predicate comparison, lower this so
5075 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5076 // lowering is done pre-legalize, because the legalizer lowers the predicate
5077 // compare down to code that is difficult to reassemble.
5078 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5079 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5083 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5084 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5085 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5086 assert(isDot && "Can't compare against a vector result!");
5088 // If this is a comparison against something other than 0/1, then we know
5089 // that the condition is never/always true.
5090 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5091 if (Val != 0 && Val != 1) {
5092 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5093 return N->getOperand(0);
5094 // Always !=, turn it into an unconditional branch.
5095 return DAG.getNode(ISD::BR, dl, MVT::Other,
5096 N->getOperand(0), N->getOperand(4));
5099 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5101 // Create the PPCISD altivec 'dot' comparison node.
5102 std::vector<EVT> VTs;
5104 LHS.getOperand(2), // LHS of compare
5105 LHS.getOperand(3), // RHS of compare
5106 DAG.getConstant(CompareOpc, MVT::i32)
5108 VTs.push_back(LHS.getOperand(2).getValueType());
5109 VTs.push_back(MVT::Flag);
5110 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5112 // Unpack the result based on how the target uses it.
5113 PPC::Predicate CompOpc;
5114 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5115 default: // Can't happen, don't crash on invalid number though.
5116 case 0: // Branch on the value of the EQ bit of CR6.
5117 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5119 case 1: // Branch on the inverted value of the EQ bit of CR6.
5120 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5122 case 2: // Branch on the value of the LT bit of CR6.
5123 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5125 case 3: // Branch on the inverted value of the LT bit of CR6.
5126 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5130 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5131 DAG.getConstant(CompOpc, MVT::i32),
5132 DAG.getRegister(PPC::CR6, MVT::i32),
5133 N->getOperand(4), CompNode.getValue(1));
5142 //===----------------------------------------------------------------------===//
5143 // Inline Assembly Support
5144 //===----------------------------------------------------------------------===//
5146 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5150 const SelectionDAG &DAG,
5151 unsigned Depth) const {
5152 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5153 switch (Op.getOpcode()) {
5155 case PPCISD::LBRX: {
5156 // lhbrx is known to have the top bits cleared out.
5157 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5158 KnownZero = 0xFFFF0000;
5161 case ISD::INTRINSIC_WO_CHAIN: {
5162 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5164 case Intrinsic::ppc_altivec_vcmpbfp_p:
5165 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5166 case Intrinsic::ppc_altivec_vcmpequb_p:
5167 case Intrinsic::ppc_altivec_vcmpequh_p:
5168 case Intrinsic::ppc_altivec_vcmpequw_p:
5169 case Intrinsic::ppc_altivec_vcmpgefp_p:
5170 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5171 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5172 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5173 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5174 case Intrinsic::ppc_altivec_vcmpgtub_p:
5175 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5176 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5177 KnownZero = ~1U; // All bits but the low one are known to be zero.
5185 /// getConstraintType - Given a constraint, return the type of
5186 /// constraint it is for this target.
5187 PPCTargetLowering::ConstraintType
5188 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5189 if (Constraint.size() == 1) {
5190 switch (Constraint[0]) {
5197 return C_RegisterClass;
5200 return TargetLowering::getConstraintType(Constraint);
5203 std::pair<unsigned, const TargetRegisterClass*>
5204 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5206 if (Constraint.size() == 1) {
5207 // GCC RS6000 Constraint Letters
5208 switch (Constraint[0]) {
5211 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5212 return std::make_pair(0U, PPC::G8RCRegisterClass);
5213 return std::make_pair(0U, PPC::GPRCRegisterClass);
5216 return std::make_pair(0U, PPC::F4RCRegisterClass);
5217 else if (VT == MVT::f64)
5218 return std::make_pair(0U, PPC::F8RCRegisterClass);
5221 return std::make_pair(0U, PPC::VRRCRegisterClass);
5223 return std::make_pair(0U, PPC::CRRCRegisterClass);
5227 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5231 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5232 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
5233 /// it means one of the asm constraint of the inline asm instruction being
5234 /// processed is 'm'.
5235 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5237 std::vector<SDValue>&Ops,
5238 SelectionDAG &DAG) const {
5239 SDValue Result(0,0);
5250 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5251 if (!CST) return; // Must be an immediate to match.
5252 unsigned Value = CST->getZExtValue();
5254 default: llvm_unreachable("Unknown constraint letter!");
5255 case 'I': // "I" is a signed 16-bit constant.
5256 if ((short)Value == (int)Value)
5257 Result = DAG.getTargetConstant(Value, Op.getValueType());
5259 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5260 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5261 if ((short)Value == 0)
5262 Result = DAG.getTargetConstant(Value, Op.getValueType());
5264 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5265 if ((Value >> 16) == 0)
5266 Result = DAG.getTargetConstant(Value, Op.getValueType());
5268 case 'M': // "M" is a constant that is greater than 31.
5270 Result = DAG.getTargetConstant(Value, Op.getValueType());
5272 case 'N': // "N" is a positive constant that is an exact power of two.
5273 if ((int)Value > 0 && isPowerOf2_32(Value))
5274 Result = DAG.getTargetConstant(Value, Op.getValueType());
5276 case 'O': // "O" is the constant zero.
5278 Result = DAG.getTargetConstant(Value, Op.getValueType());
5280 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5281 if ((short)-Value == (int)-Value)
5282 Result = DAG.getTargetConstant(Value, Op.getValueType());
5289 if (Result.getNode()) {
5290 Ops.push_back(Result);
5294 // Handle standard constraint letters.
5295 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
5298 // isLegalAddressingMode - Return true if the addressing mode represented
5299 // by AM is legal for this target, for a load/store of the specified type.
5300 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5301 const Type *Ty) const {
5302 // FIXME: PPC does not allow r+i addressing modes for vectors!
5304 // PPC allows a sign-extended 16-bit immediate field.
5305 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5308 // No global is ever allowed as a base.
5312 // PPC only support r+r,
5314 case 0: // "r+i" or just "i", depending on HasBaseReg.
5317 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5319 // Otherwise we have r+r or r+i.
5322 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5324 // Allow 2*r as r+r.
5327 // No other scales are supported.
5334 /// isLegalAddressImmediate - Return true if the integer value can be used
5335 /// as the offset of the target addressing mode for load / store of the
5337 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5338 // PPC allows a sign-extended 16-bit immediate field.
5339 return (V > -(1 << 16) && V < (1 << 16)-1);
5342 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5346 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5347 DebugLoc dl = Op.getDebugLoc();
5348 // Depths > 0 not supported yet!
5349 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5352 MachineFunction &MF = DAG.getMachineFunction();
5353 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5355 // Just load the return address off the stack.
5356 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5358 // Make sure the function really does not optimize away the store of the RA
5360 FuncInfo->setLRStoreRequired();
5361 return DAG.getLoad(getPointerTy(), dl,
5362 DAG.getEntryNode(), RetAddrFI, NULL, 0);
5365 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5366 DebugLoc dl = Op.getDebugLoc();
5367 // Depths > 0 not supported yet!
5368 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5371 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5372 bool isPPC64 = PtrVT == MVT::i64;
5374 MachineFunction &MF = DAG.getMachineFunction();
5375 MachineFrameInfo *MFI = MF.getFrameInfo();
5376 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
5377 && MFI->getStackSize();
5380 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
5383 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
5388 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5389 // The PowerPC target isn't yet aware of offsets.
5393 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
5394 bool isSrcConst, bool isSrcStr,
5395 SelectionDAG &DAG) const {
5396 if (this->PPCSubTarget.isPPC64()) {