1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
49 // FIXME: Remove this once the bug has been fixed!
50 extern cl::opt<bool> ANDIGlueBug;
52 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
53 if (TM.getSubtargetImpl()->isDarwin())
54 return new TargetLoweringObjectFileMachO();
56 if (TM.getSubtargetImpl()->isSVR4ABI())
57 return new PPC64LinuxTargetObjectFile();
59 return new TargetLoweringObjectFileELF();
62 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
63 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
64 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget->isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget->useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget->hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget->hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget->hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget->hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget->hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget->hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget->useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget->useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget->useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget->isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget->isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget->has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (PPCSubTarget.hasFPCVT()) {
371 if (Subtarget->has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget->use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget->hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::CTPOP, VT, Expand);
463 setOperationAction(ISD::CTLZ, VT, Expand);
464 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
465 setOperationAction(ISD::CTTZ, VT, Expand);
466 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
467 setOperationAction(ISD::VSELECT, VT, Expand);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
470 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
471 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
472 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
473 setTruncStoreAction(VT, InnerVT, Expand);
475 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
476 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
480 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
481 // with merges, splats, etc.
482 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
484 setOperationAction(ISD::AND , MVT::v4i32, Legal);
485 setOperationAction(ISD::OR , MVT::v4i32, Legal);
486 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
487 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
488 setOperationAction(ISD::SELECT, MVT::v4i32,
489 Subtarget->useCRBits() ? Legal : Expand);
490 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
491 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
494 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
496 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
497 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
498 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
500 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
501 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
505 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
506 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
508 if (TM.Options.UnsafeFPMath) {
509 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
510 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
513 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
514 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
515 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
517 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
520 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
525 // Altivec does not contain unordered floating-point compare instructions
526 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
527 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
533 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget->has64BitSupport()) {
538 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
539 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
542 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
543 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
544 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
545 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
547 setBooleanContents(ZeroOrOneBooleanContent);
548 // Altivec instructions set fields to all zeros or all ones.
549 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
552 setStackPointerRegisterToSaveRestore(PPC::X1);
553 setExceptionPointerRegister(PPC::X3);
554 setExceptionSelectorRegister(PPC::X4);
556 setStackPointerRegisterToSaveRestore(PPC::R1);
557 setExceptionPointerRegister(PPC::R3);
558 setExceptionSelectorRegister(PPC::R4);
561 // We have target-specific dag combine patterns for the following nodes:
562 setTargetDAGCombine(ISD::SINT_TO_FP);
563 setTargetDAGCombine(ISD::LOAD);
564 setTargetDAGCombine(ISD::STORE);
565 setTargetDAGCombine(ISD::BR_CC);
566 if (Subtarget->useCRBits())
567 setTargetDAGCombine(ISD::BRCOND);
568 setTargetDAGCombine(ISD::BSWAP);
569 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
571 setTargetDAGCombine(ISD::SIGN_EXTEND);
572 setTargetDAGCombine(ISD::ZERO_EXTEND);
573 setTargetDAGCombine(ISD::ANY_EXTEND);
575 if (Subtarget->useCRBits()) {
576 setTargetDAGCombine(ISD::TRUNCATE);
577 setTargetDAGCombine(ISD::SETCC);
578 setTargetDAGCombine(ISD::SELECT_CC);
581 // Use reciprocal estimates.
582 if (TM.Options.UnsafeFPMath) {
583 setTargetDAGCombine(ISD::FDIV);
584 setTargetDAGCombine(ISD::FSQRT);
587 // Darwin long double math library functions have $LDBL128 appended.
588 if (Subtarget->isDarwin()) {
589 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
590 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
591 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
592 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
593 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
594 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
595 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
596 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
597 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
598 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
601 // With 32 condition bits, we don't need to sink (and duplicate) compares
602 // aggressively in CodeGenPrep.
603 if (Subtarget->useCRBits())
604 setHasMultipleConditionRegisters();
606 setMinFunctionAlignment(2);
607 if (PPCSubTarget.isDarwin())
608 setPrefFunctionAlignment(4);
610 if (isPPC64 && Subtarget->isJITCodeModel())
611 // Temporary workaround for the inability of PPC64 JIT to handle jump
613 setSupportJumpTables(false);
615 setInsertFencesForAtomic(true);
617 if (Subtarget->enableMachineScheduler())
618 setSchedulingPreference(Sched::Source);
620 setSchedulingPreference(Sched::Hybrid);
622 computeRegisterProperties();
624 // The Freescale cores does better with aggressive inlining of memcpy and
625 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
626 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
627 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
628 MaxStoresPerMemset = 32;
629 MaxStoresPerMemsetOptSize = 16;
630 MaxStoresPerMemcpy = 32;
631 MaxStoresPerMemcpyOptSize = 8;
632 MaxStoresPerMemmove = 32;
633 MaxStoresPerMemmoveOptSize = 8;
635 setPrefFunctionAlignment(4);
639 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
640 /// the desired ByVal argument alignment.
641 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
642 unsigned MaxMaxAlign) {
643 if (MaxAlign == MaxMaxAlign)
645 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
646 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
648 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
650 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
651 unsigned EltAlign = 0;
652 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
653 if (EltAlign > MaxAlign)
655 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
656 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
657 unsigned EltAlign = 0;
658 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
659 if (EltAlign > MaxAlign)
661 if (MaxAlign == MaxMaxAlign)
667 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
668 /// function arguments in the caller parameter area.
669 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
670 // Darwin passes everything on 4 byte boundary.
671 if (PPCSubTarget.isDarwin())
674 // 16byte and wider vectors are passed on 16byte boundary.
675 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
676 unsigned Align = PPCSubTarget.isPPC64() ? 8 : 4;
677 if (PPCSubTarget.hasAltivec() || PPCSubTarget.hasQPX())
678 getMaxByValAlign(Ty, Align, PPCSubTarget.hasQPX() ? 32 : 16);
682 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
685 case PPCISD::FSEL: return "PPCISD::FSEL";
686 case PPCISD::FCFID: return "PPCISD::FCFID";
687 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
688 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
689 case PPCISD::FRE: return "PPCISD::FRE";
690 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
691 case PPCISD::STFIWX: return "PPCISD::STFIWX";
692 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
693 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
694 case PPCISD::VPERM: return "PPCISD::VPERM";
695 case PPCISD::Hi: return "PPCISD::Hi";
696 case PPCISD::Lo: return "PPCISD::Lo";
697 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
698 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
699 case PPCISD::LOAD: return "PPCISD::LOAD";
700 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
701 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
702 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
703 case PPCISD::SRL: return "PPCISD::SRL";
704 case PPCISD::SRA: return "PPCISD::SRA";
705 case PPCISD::SHL: return "PPCISD::SHL";
706 case PPCISD::CALL: return "PPCISD::CALL";
707 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
708 case PPCISD::MTCTR: return "PPCISD::MTCTR";
709 case PPCISD::BCTRL: return "PPCISD::BCTRL";
710 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
711 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
712 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
713 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
714 case PPCISD::VCMP: return "PPCISD::VCMP";
715 case PPCISD::VCMPo: return "PPCISD::VCMPo";
716 case PPCISD::LBRX: return "PPCISD::LBRX";
717 case PPCISD::STBRX: return "PPCISD::STBRX";
718 case PPCISD::LARX: return "PPCISD::LARX";
719 case PPCISD::STCX: return "PPCISD::STCX";
720 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
721 case PPCISD::BDNZ: return "PPCISD::BDNZ";
722 case PPCISD::BDZ: return "PPCISD::BDZ";
723 case PPCISD::MFFS: return "PPCISD::MFFS";
724 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
725 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
726 case PPCISD::CR6SET: return "PPCISD::CR6SET";
727 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
728 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
729 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
730 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
731 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
732 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
733 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
734 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
735 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
736 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
737 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
738 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
739 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
740 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
741 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
742 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
743 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
744 case PPCISD::SC: return "PPCISD::SC";
748 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
750 return PPCSubTarget.useCRBits() ? MVT::i1 : MVT::i32;
751 return VT.changeVectorElementTypeToInteger();
754 //===----------------------------------------------------------------------===//
755 // Node matching predicates, for use by the tblgen matching code.
756 //===----------------------------------------------------------------------===//
758 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
759 static bool isFloatingPointZero(SDValue Op) {
760 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
761 return CFP->getValueAPF().isZero();
762 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
763 // Maybe this has already been legalized into the constant pool?
764 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
765 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
766 return CFP->getValueAPF().isZero();
771 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
772 /// true if Op is undef or if it matches the specified value.
773 static bool isConstantOrUndef(int Op, int Val) {
774 return Op < 0 || Op == Val;
777 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
778 /// VPKUHUM instruction.
779 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
781 for (unsigned i = 0; i != 16; ++i)
782 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
785 for (unsigned i = 0; i != 8; ++i)
786 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
787 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
793 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
794 /// VPKUWUM instruction.
795 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
797 for (unsigned i = 0; i != 16; i += 2)
798 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
799 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
802 for (unsigned i = 0; i != 8; i += 2)
803 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
804 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
805 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
806 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
812 /// isVMerge - Common function, used to match vmrg* shuffles.
814 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
815 unsigned LHSStart, unsigned RHSStart) {
816 assert(N->getValueType(0) == MVT::v16i8 &&
817 "PPC only supports shuffles by bytes!");
818 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
819 "Unsupported merge size!");
821 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
822 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
823 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
824 LHSStart+j+i*UnitSize) ||
825 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
826 RHSStart+j+i*UnitSize))
832 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
833 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
834 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
837 return isVMerge(N, UnitSize, 8, 24);
838 return isVMerge(N, UnitSize, 8, 8);
841 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
842 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
843 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
846 return isVMerge(N, UnitSize, 0, 16);
847 return isVMerge(N, UnitSize, 0, 0);
851 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
852 /// amount, otherwise return -1.
853 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
854 assert(N->getValueType(0) == MVT::v16i8 &&
855 "PPC only supports shuffles by bytes!");
857 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
859 // Find the first non-undef value in the shuffle mask.
861 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
864 if (i == 16) return -1; // all undef.
866 // Otherwise, check to see if the rest of the elements are consecutively
867 // numbered from this value.
868 unsigned ShiftAmt = SVOp->getMaskElt(i);
869 if (ShiftAmt < i) return -1;
873 // Check the rest of the elements to see if they are consecutive.
874 for (++i; i != 16; ++i)
875 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
878 // Check the rest of the elements to see if they are consecutive.
879 for (++i; i != 16; ++i)
880 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
886 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
887 /// specifies a splat of a single element that is suitable for input to
888 /// VSPLTB/VSPLTH/VSPLTW.
889 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
890 assert(N->getValueType(0) == MVT::v16i8 &&
891 (EltSize == 1 || EltSize == 2 || EltSize == 4));
893 // This is a splat operation if each element of the permute is the same, and
894 // if the value doesn't reference the second vector.
895 unsigned ElementBase = N->getMaskElt(0);
897 // FIXME: Handle UNDEF elements too!
898 if (ElementBase >= 16)
901 // Check that the indices are consecutive, in the case of a multi-byte element
902 // splatted with a v16i8 mask.
903 for (unsigned i = 1; i != EltSize; ++i)
904 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
907 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
908 if (N->getMaskElt(i) < 0) continue;
909 for (unsigned j = 0; j != EltSize; ++j)
910 if (N->getMaskElt(i+j) != N->getMaskElt(j))
916 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
918 bool PPC::isAllNegativeZeroVector(SDNode *N) {
919 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
921 APInt APVal, APUndef;
925 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
926 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
927 return CFP->getValueAPF().isNegZero();
932 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
933 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
934 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
935 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
936 assert(isSplatShuffleMask(SVOp, EltSize));
937 return SVOp->getMaskElt(0) / EltSize;
940 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
941 /// by using a vspltis[bhw] instruction of the specified element size, return
942 /// the constant being splatted. The ByteSize field indicates the number of
943 /// bytes of each element [124] -> [bhw].
944 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
947 // If ByteSize of the splat is bigger than the element size of the
948 // build_vector, then we have a case where we are checking for a splat where
949 // multiple elements of the buildvector are folded together into a single
950 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
951 unsigned EltSize = 16/N->getNumOperands();
952 if (EltSize < ByteSize) {
953 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
954 SDValue UniquedVals[4];
955 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
957 // See if all of the elements in the buildvector agree across.
958 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
959 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
960 // If the element isn't a constant, bail fully out.
961 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
964 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
965 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
966 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
967 return SDValue(); // no match.
970 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
971 // either constant or undef values that are identical for each chunk. See
972 // if these chunks can form into a larger vspltis*.
974 // Check to see if all of the leading entries are either 0 or -1. If
975 // neither, then this won't fit into the immediate field.
976 bool LeadingZero = true;
977 bool LeadingOnes = true;
978 for (unsigned i = 0; i != Multiple-1; ++i) {
979 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
981 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
982 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
984 // Finally, check the least significant entry.
986 if (UniquedVals[Multiple-1].getNode() == 0)
987 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
988 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
990 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
993 if (UniquedVals[Multiple-1].getNode() == 0)
994 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
995 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
996 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
997 return DAG.getTargetConstant(Val, MVT::i32);
1003 // Check to see if this buildvec has a single non-undef value in its elements.
1004 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1005 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1006 if (OpVal.getNode() == 0)
1007 OpVal = N->getOperand(i);
1008 else if (OpVal != N->getOperand(i))
1012 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
1014 unsigned ValSizeInBytes = EltSize;
1016 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1017 Value = CN->getZExtValue();
1018 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1019 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1020 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1023 // If the splat value is larger than the element value, then we can never do
1024 // this splat. The only case that we could fit the replicated bits into our
1025 // immediate field for would be zero, and we prefer to use vxor for it.
1026 if (ValSizeInBytes < ByteSize) return SDValue();
1028 // If the element value is larger than the splat value, cut it in half and
1029 // check to see if the two halves are equal. Continue doing this until we
1030 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1031 while (ValSizeInBytes > ByteSize) {
1032 ValSizeInBytes >>= 1;
1034 // If the top half equals the bottom half, we're still ok.
1035 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1036 (Value & ((1 << (8*ValSizeInBytes))-1)))
1040 // Properly sign extend the value.
1041 int MaskVal = SignExtend32(Value, ByteSize * 8);
1043 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1044 if (MaskVal == 0) return SDValue();
1046 // Finally, if this value fits in a 5 bit sext field, return it
1047 if (SignExtend32<5>(MaskVal) == MaskVal)
1048 return DAG.getTargetConstant(MaskVal, MVT::i32);
1052 //===----------------------------------------------------------------------===//
1053 // Addressing Mode Selection
1054 //===----------------------------------------------------------------------===//
1056 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1057 /// or 64-bit immediate, and if the value can be accurately represented as a
1058 /// sign extension from a 16-bit value. If so, this returns true and the
1060 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1061 if (N->getOpcode() != ISD::Constant)
1064 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1065 if (N->getValueType(0) == MVT::i32)
1066 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1068 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1070 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1071 return isIntS16Immediate(Op.getNode(), Imm);
1075 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1076 /// can be represented as an indexed [r+r] operation. Returns false if it
1077 /// can be more efficiently represented with [r+imm].
1078 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1080 SelectionDAG &DAG) const {
1082 if (N.getOpcode() == ISD::ADD) {
1083 if (isIntS16Immediate(N.getOperand(1), imm))
1084 return false; // r+i
1085 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1086 return false; // r+i
1088 Base = N.getOperand(0);
1089 Index = N.getOperand(1);
1091 } else if (N.getOpcode() == ISD::OR) {
1092 if (isIntS16Immediate(N.getOperand(1), imm))
1093 return false; // r+i can fold it if we can.
1095 // If this is an or of disjoint bitfields, we can codegen this as an add
1096 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1098 APInt LHSKnownZero, LHSKnownOne;
1099 APInt RHSKnownZero, RHSKnownOne;
1100 DAG.ComputeMaskedBits(N.getOperand(0),
1101 LHSKnownZero, LHSKnownOne);
1103 if (LHSKnownZero.getBoolValue()) {
1104 DAG.ComputeMaskedBits(N.getOperand(1),
1105 RHSKnownZero, RHSKnownOne);
1106 // If all of the bits are known zero on the LHS or RHS, the add won't
1108 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1109 Base = N.getOperand(0);
1110 Index = N.getOperand(1);
1119 // If we happen to be doing an i64 load or store into a stack slot that has
1120 // less than a 4-byte alignment, then the frame-index elimination may need to
1121 // use an indexed load or store instruction (because the offset may not be a
1122 // multiple of 4). The extra register needed to hold the offset comes from the
1123 // register scavenger, and it is possible that the scavenger will need to use
1124 // an emergency spill slot. As a result, we need to make sure that a spill slot
1125 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1127 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1128 // FIXME: This does not handle the LWA case.
1132 // NOTE: We'll exclude negative FIs here, which come from argument
1133 // lowering, because there are no known test cases triggering this problem
1134 // using packed structures (or similar). We can remove this exclusion if
1135 // we find such a test case. The reason why this is so test-case driven is
1136 // because this entire 'fixup' is only to prevent crashes (from the
1137 // register scavenger) on not-really-valid inputs. For example, if we have:
1139 // %b = bitcast i1* %a to i64*
1140 // store i64* a, i64 b
1141 // then the store should really be marked as 'align 1', but is not. If it
1142 // were marked as 'align 1' then the indexed form would have been
1143 // instruction-selected initially, and the problem this 'fixup' is preventing
1144 // won't happen regardless.
1148 MachineFunction &MF = DAG.getMachineFunction();
1149 MachineFrameInfo *MFI = MF.getFrameInfo();
1151 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1155 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1156 FuncInfo->setHasNonRISpills();
1159 /// Returns true if the address N can be represented by a base register plus
1160 /// a signed 16-bit displacement [r+imm], and if it is not better
1161 /// represented as reg+reg. If Aligned is true, only accept displacements
1162 /// suitable for STD and friends, i.e. multiples of 4.
1163 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1166 bool Aligned) const {
1167 // FIXME dl should come from parent load or store, not from address
1169 // If this can be more profitably realized as r+r, fail.
1170 if (SelectAddressRegReg(N, Disp, Base, DAG))
1173 if (N.getOpcode() == ISD::ADD) {
1175 if (isIntS16Immediate(N.getOperand(1), imm) &&
1176 (!Aligned || (imm & 3) == 0)) {
1177 Disp = DAG.getTargetConstant(imm, N.getValueType());
1178 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1179 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1180 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1182 Base = N.getOperand(0);
1184 return true; // [r+i]
1185 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1186 // Match LOAD (ADD (X, Lo(G))).
1187 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1188 && "Cannot handle constant offsets yet!");
1189 Disp = N.getOperand(1).getOperand(0); // The global address.
1190 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1191 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1192 Disp.getOpcode() == ISD::TargetConstantPool ||
1193 Disp.getOpcode() == ISD::TargetJumpTable);
1194 Base = N.getOperand(0);
1195 return true; // [&g+r]
1197 } else if (N.getOpcode() == ISD::OR) {
1199 if (isIntS16Immediate(N.getOperand(1), imm) &&
1200 (!Aligned || (imm & 3) == 0)) {
1201 // If this is an or of disjoint bitfields, we can codegen this as an add
1202 // (for better address arithmetic) if the LHS and RHS of the OR are
1203 // provably disjoint.
1204 APInt LHSKnownZero, LHSKnownOne;
1205 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1207 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1208 // If all of the bits are known zero on the LHS or RHS, the add won't
1210 Base = N.getOperand(0);
1211 Disp = DAG.getTargetConstant(imm, N.getValueType());
1215 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1216 // Loading from a constant address.
1218 // If this address fits entirely in a 16-bit sext immediate field, codegen
1221 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1222 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1223 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1224 CN->getValueType(0));
1228 // Handle 32-bit sext immediates with LIS + addr mode.
1229 if ((CN->getValueType(0) == MVT::i32 ||
1230 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1231 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1232 int Addr = (int)CN->getZExtValue();
1234 // Otherwise, break this down into an LIS + disp.
1235 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1237 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1238 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1239 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1244 Disp = DAG.getTargetConstant(0, getPointerTy());
1245 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1246 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1247 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1250 return true; // [r+0]
1253 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1254 /// represented as an indexed [r+r] operation.
1255 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1257 SelectionDAG &DAG) const {
1258 // Check to see if we can easily represent this as an [r+r] address. This
1259 // will fail if it thinks that the address is more profitably represented as
1260 // reg+imm, e.g. where imm = 0.
1261 if (SelectAddressRegReg(N, Base, Index, DAG))
1264 // If the operand is an addition, always emit this as [r+r], since this is
1265 // better (for code size, and execution, as the memop does the add for free)
1266 // than emitting an explicit add.
1267 if (N.getOpcode() == ISD::ADD) {
1268 Base = N.getOperand(0);
1269 Index = N.getOperand(1);
1273 // Otherwise, do it the hard way, using R0 as the base register.
1274 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1280 /// getPreIndexedAddressParts - returns true by value, base pointer and
1281 /// offset pointer and addressing mode by reference if the node's address
1282 /// can be legally represented as pre-indexed load / store address.
1283 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1285 ISD::MemIndexedMode &AM,
1286 SelectionDAG &DAG) const {
1287 if (DisablePPCPreinc) return false;
1293 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1294 Ptr = LD->getBasePtr();
1295 VT = LD->getMemoryVT();
1296 Alignment = LD->getAlignment();
1297 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1298 Ptr = ST->getBasePtr();
1299 VT = ST->getMemoryVT();
1300 Alignment = ST->getAlignment();
1305 // PowerPC doesn't have preinc load/store instructions for vectors.
1309 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1311 // Common code will reject creating a pre-inc form if the base pointer
1312 // is a frame index, or if N is a store and the base pointer is either
1313 // the same as or a predecessor of the value being stored. Check for
1314 // those situations here, and try with swapped Base/Offset instead.
1317 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1320 SDValue Val = cast<StoreSDNode>(N)->getValue();
1321 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1326 std::swap(Base, Offset);
1332 // LDU/STU can only handle immediates that are a multiple of 4.
1333 if (VT != MVT::i64) {
1334 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1337 // LDU/STU need an address with at least 4-byte alignment.
1341 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1345 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1346 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1347 // sext i32 to i64 when addr mode is r+i.
1348 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1349 LD->getExtensionType() == ISD::SEXTLOAD &&
1350 isa<ConstantSDNode>(Offset))
1358 //===----------------------------------------------------------------------===//
1359 // LowerOperation implementation
1360 //===----------------------------------------------------------------------===//
1362 /// GetLabelAccessInfo - Return true if we should reference labels using a
1363 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1364 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1365 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1366 HiOpFlags = PPCII::MO_HA;
1367 LoOpFlags = PPCII::MO_LO;
1369 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1370 // non-darwin platform. We don't support PIC on other platforms yet.
1371 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1372 TM.getSubtarget<PPCSubtarget>().isDarwin();
1374 HiOpFlags |= PPCII::MO_PIC_FLAG;
1375 LoOpFlags |= PPCII::MO_PIC_FLAG;
1378 // If this is a reference to a global value that requires a non-lazy-ptr, make
1379 // sure that instruction lowering adds it.
1380 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1381 HiOpFlags |= PPCII::MO_NLP_FLAG;
1382 LoOpFlags |= PPCII::MO_NLP_FLAG;
1384 if (GV->hasHiddenVisibility()) {
1385 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1386 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1393 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1394 SelectionDAG &DAG) {
1395 EVT PtrVT = HiPart.getValueType();
1396 SDValue Zero = DAG.getConstant(0, PtrVT);
1399 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1400 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1402 // With PIC, the first instruction is actually "GR+hi(&G)".
1404 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1405 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1407 // Generate non-pic code that has direct accesses to the constant pool.
1408 // The address of the global is just (hi(&g)+lo(&g)).
1409 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1412 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1413 SelectionDAG &DAG) const {
1414 EVT PtrVT = Op.getValueType();
1415 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1416 const Constant *C = CP->getConstVal();
1418 // 64-bit SVR4 ABI code is always position-independent.
1419 // The actual address of the GlobalValue is stored in the TOC.
1420 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1421 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1422 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1423 DAG.getRegister(PPC::X2, MVT::i64));
1426 unsigned MOHiFlag, MOLoFlag;
1427 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1429 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1431 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1432 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1435 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1436 EVT PtrVT = Op.getValueType();
1437 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1439 // 64-bit SVR4 ABI code is always position-independent.
1440 // The actual address of the GlobalValue is stored in the TOC.
1441 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1442 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1443 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1444 DAG.getRegister(PPC::X2, MVT::i64));
1447 unsigned MOHiFlag, MOLoFlag;
1448 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1449 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1450 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1451 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1454 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1455 SelectionDAG &DAG) const {
1456 EVT PtrVT = Op.getValueType();
1458 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1460 unsigned MOHiFlag, MOLoFlag;
1461 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1462 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1463 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1464 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1467 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1468 SelectionDAG &DAG) const {
1470 // FIXME: TLS addresses currently use medium model code sequences,
1471 // which is the most useful form. Eventually support for small and
1472 // large models could be added if users need it, at the cost of
1473 // additional complexity.
1474 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1476 const GlobalValue *GV = GA->getGlobal();
1477 EVT PtrVT = getPointerTy();
1478 bool is64bit = PPCSubTarget.isPPC64();
1480 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1482 if (Model == TLSModel::LocalExec) {
1483 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1484 PPCII::MO_TPREL_HA);
1485 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1486 PPCII::MO_TPREL_LO);
1487 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1488 is64bit ? MVT::i64 : MVT::i32);
1489 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1490 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1493 if (Model == TLSModel::InitialExec) {
1494 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1495 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1499 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1500 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1501 PtrVT, GOTReg, TGA);
1503 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1504 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1505 PtrVT, TGA, GOTPtr);
1506 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1509 if (Model == TLSModel::GeneralDynamic) {
1510 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1511 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1512 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1514 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1517 // We need a chain node, and don't have one handy. The underlying
1518 // call has no side effects, so using the function entry node
1520 SDValue Chain = DAG.getEntryNode();
1521 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1522 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1523 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1524 PtrVT, ParmReg, TGA);
1525 // The return value from GET_TLS_ADDR really is in X3 already, but
1526 // some hacks are needed here to tie everything together. The extra
1527 // copies dissolve during subsequent transforms.
1528 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1529 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1532 if (Model == TLSModel::LocalDynamic) {
1533 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1534 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1535 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1537 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1540 // We need a chain node, and don't have one handy. The underlying
1541 // call has no side effects, so using the function entry node
1543 SDValue Chain = DAG.getEntryNode();
1544 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1545 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1546 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1547 PtrVT, ParmReg, TGA);
1548 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1549 // some hacks are needed here to tie everything together. The extra
1550 // copies dissolve during subsequent transforms.
1551 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1552 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1553 Chain, ParmReg, TGA);
1554 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1557 llvm_unreachable("Unknown TLS model!");
1560 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1561 SelectionDAG &DAG) const {
1562 EVT PtrVT = Op.getValueType();
1563 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1565 const GlobalValue *GV = GSDN->getGlobal();
1567 // 64-bit SVR4 ABI code is always position-independent.
1568 // The actual address of the GlobalValue is stored in the TOC.
1569 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1570 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1571 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1572 DAG.getRegister(PPC::X2, MVT::i64));
1575 unsigned MOHiFlag, MOLoFlag;
1576 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1579 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1581 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1583 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1585 // If the global reference is actually to a non-lazy-pointer, we have to do an
1586 // extra load to get the address of the global.
1587 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1588 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1589 false, false, false, 0);
1593 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1594 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1597 // If we're comparing for equality to zero, expose the fact that this is
1598 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1599 // fold the new nodes.
1600 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1601 if (C->isNullValue() && CC == ISD::SETEQ) {
1602 EVT VT = Op.getOperand(0).getValueType();
1603 SDValue Zext = Op.getOperand(0);
1604 if (VT.bitsLT(MVT::i32)) {
1606 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1608 unsigned Log2b = Log2_32(VT.getSizeInBits());
1609 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1610 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1611 DAG.getConstant(Log2b, MVT::i32));
1612 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1614 // Leave comparisons against 0 and -1 alone for now, since they're usually
1615 // optimized. FIXME: revisit this when we can custom lower all setcc
1617 if (C->isAllOnesValue() || C->isNullValue())
1621 // If we have an integer seteq/setne, turn it into a compare against zero
1622 // by xor'ing the rhs with the lhs, which is faster than setting a
1623 // condition register, reading it back out, and masking the correct bit. The
1624 // normal approach here uses sub to do this instead of xor. Using xor exposes
1625 // the result to other bit-twiddling opportunities.
1626 EVT LHSVT = Op.getOperand(0).getValueType();
1627 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1628 EVT VT = Op.getValueType();
1629 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1631 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1636 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1637 const PPCSubtarget &Subtarget) const {
1638 SDNode *Node = Op.getNode();
1639 EVT VT = Node->getValueType(0);
1640 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1641 SDValue InChain = Node->getOperand(0);
1642 SDValue VAListPtr = Node->getOperand(1);
1643 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1646 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1649 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1650 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1652 InChain = GprIndex.getValue(1);
1654 if (VT == MVT::i64) {
1655 // Check if GprIndex is even
1656 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1657 DAG.getConstant(1, MVT::i32));
1658 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1659 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1660 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1661 DAG.getConstant(1, MVT::i32));
1662 // Align GprIndex to be even if it isn't
1663 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1667 // fpr index is 1 byte after gpr
1668 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1669 DAG.getConstant(1, MVT::i32));
1672 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1673 FprPtr, MachinePointerInfo(SV), MVT::i8,
1675 InChain = FprIndex.getValue(1);
1677 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1678 DAG.getConstant(8, MVT::i32));
1680 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1681 DAG.getConstant(4, MVT::i32));
1684 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1685 MachinePointerInfo(), false, false,
1687 InChain = OverflowArea.getValue(1);
1689 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1690 MachinePointerInfo(), false, false,
1692 InChain = RegSaveArea.getValue(1);
1694 // select overflow_area if index > 8
1695 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1696 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1698 // adjustment constant gpr_index * 4/8
1699 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1700 VT.isInteger() ? GprIndex : FprIndex,
1701 DAG.getConstant(VT.isInteger() ? 4 : 8,
1704 // OurReg = RegSaveArea + RegConstant
1705 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1708 // Floating types are 32 bytes into RegSaveArea
1709 if (VT.isFloatingPoint())
1710 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1711 DAG.getConstant(32, MVT::i32));
1713 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1714 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1715 VT.isInteger() ? GprIndex : FprIndex,
1716 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1719 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1720 VT.isInteger() ? VAListPtr : FprPtr,
1721 MachinePointerInfo(SV),
1722 MVT::i8, false, false, 0);
1724 // determine if we should load from reg_save_area or overflow_area
1725 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1727 // increase overflow_area by 4/8 if gpr/fpr > 8
1728 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1729 DAG.getConstant(VT.isInteger() ? 4 : 8,
1732 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1735 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1737 MachinePointerInfo(),
1738 MVT::i32, false, false, 0);
1740 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1741 false, false, false, 0);
1744 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1745 const PPCSubtarget &Subtarget) const {
1746 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1748 // We have to copy the entire va_list struct:
1749 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1750 return DAG.getMemcpy(Op.getOperand(0), Op,
1751 Op.getOperand(1), Op.getOperand(2),
1752 DAG.getConstant(12, MVT::i32), 8, false, true,
1753 MachinePointerInfo(), MachinePointerInfo());
1756 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1757 SelectionDAG &DAG) const {
1758 return Op.getOperand(0);
1761 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1762 SelectionDAG &DAG) const {
1763 SDValue Chain = Op.getOperand(0);
1764 SDValue Trmp = Op.getOperand(1); // trampoline
1765 SDValue FPtr = Op.getOperand(2); // nested function
1766 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1769 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1770 bool isPPC64 = (PtrVT == MVT::i64);
1772 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1775 TargetLowering::ArgListTy Args;
1776 TargetLowering::ArgListEntry Entry;
1778 Entry.Ty = IntPtrTy;
1779 Entry.Node = Trmp; Args.push_back(Entry);
1781 // TrampSize == (isPPC64 ? 48 : 40);
1782 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1783 isPPC64 ? MVT::i64 : MVT::i32);
1784 Args.push_back(Entry);
1786 Entry.Node = FPtr; Args.push_back(Entry);
1787 Entry.Node = Nest; Args.push_back(Entry);
1789 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1790 TargetLowering::CallLoweringInfo CLI(Chain,
1791 Type::getVoidTy(*DAG.getContext()),
1792 false, false, false, false, 0,
1794 /*isTailCall=*/false,
1795 /*doesNotRet=*/false,
1796 /*isReturnValueUsed=*/true,
1797 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1799 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1801 return CallResult.second;
1804 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1805 const PPCSubtarget &Subtarget) const {
1806 MachineFunction &MF = DAG.getMachineFunction();
1807 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1811 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1812 // vastart just stores the address of the VarArgsFrameIndex slot into the
1813 // memory location argument.
1814 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1815 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1816 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1817 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1818 MachinePointerInfo(SV),
1822 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1823 // We suppose the given va_list is already allocated.
1826 // char gpr; /* index into the array of 8 GPRs
1827 // * stored in the register save area
1828 // * gpr=0 corresponds to r3,
1829 // * gpr=1 to r4, etc.
1831 // char fpr; /* index into the array of 8 FPRs
1832 // * stored in the register save area
1833 // * fpr=0 corresponds to f1,
1834 // * fpr=1 to f2, etc.
1836 // char *overflow_arg_area;
1837 // /* location on stack that holds
1838 // * the next overflow argument
1840 // char *reg_save_area;
1841 // /* where r3:r10 and f1:f8 (if saved)
1847 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1848 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1851 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1853 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1855 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1858 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1859 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1861 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1862 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1864 uint64_t FPROffset = 1;
1865 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1867 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1869 // Store first byte : number of int regs
1870 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1872 MachinePointerInfo(SV),
1873 MVT::i8, false, false, 0);
1874 uint64_t nextOffset = FPROffset;
1875 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1878 // Store second byte : number of float regs
1879 SDValue secondStore =
1880 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1881 MachinePointerInfo(SV, nextOffset), MVT::i8,
1883 nextOffset += StackOffset;
1884 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1886 // Store second word : arguments given on stack
1887 SDValue thirdStore =
1888 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1889 MachinePointerInfo(SV, nextOffset),
1891 nextOffset += FrameOffset;
1892 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1894 // Store third word : arguments given in registers
1895 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1896 MachinePointerInfo(SV, nextOffset),
1901 #include "PPCGenCallingConv.inc"
1903 // Function whose sole purpose is to kill compiler warnings
1904 // stemming from unused functions included from PPCGenCallingConv.inc.
1905 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
1906 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
1909 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1910 CCValAssign::LocInfo &LocInfo,
1911 ISD::ArgFlagsTy &ArgFlags,
1916 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1918 CCValAssign::LocInfo &LocInfo,
1919 ISD::ArgFlagsTy &ArgFlags,
1921 static const uint16_t ArgRegs[] = {
1922 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1923 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1925 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1927 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1929 // Skip one register if the first unallocated register has an even register
1930 // number and there are still argument registers available which have not been
1931 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1932 // need to skip a register if RegNum is odd.
1933 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1934 State.AllocateReg(ArgRegs[RegNum]);
1937 // Always return false here, as this function only makes sure that the first
1938 // unallocated register has an odd register number and does not actually
1939 // allocate a register for the current argument.
1943 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1945 CCValAssign::LocInfo &LocInfo,
1946 ISD::ArgFlagsTy &ArgFlags,
1948 static const uint16_t ArgRegs[] = {
1949 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1953 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1955 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1957 // If there is only one Floating-point register left we need to put both f64
1958 // values of a split ppc_fp128 value on the stack.
1959 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1960 State.AllocateReg(ArgRegs[RegNum]);
1963 // Always return false here, as this function only makes sure that the two f64
1964 // values a ppc_fp128 value is split into are both passed in registers or both
1965 // passed on the stack and does not actually allocate a register for the
1966 // current argument.
1970 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1972 static const uint16_t *GetFPR() {
1973 static const uint16_t FPR[] = {
1974 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1975 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1981 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1983 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1984 unsigned PtrByteSize) {
1985 unsigned ArgSize = ArgVT.getStoreSize();
1986 if (Flags.isByVal())
1987 ArgSize = Flags.getByValSize();
1988 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1994 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1995 CallingConv::ID CallConv, bool isVarArg,
1996 const SmallVectorImpl<ISD::InputArg>
1998 SDLoc dl, SelectionDAG &DAG,
1999 SmallVectorImpl<SDValue> &InVals)
2001 if (PPCSubTarget.isSVR4ABI()) {
2002 if (PPCSubTarget.isPPC64())
2003 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2006 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2009 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2015 PPCTargetLowering::LowerFormalArguments_32SVR4(
2017 CallingConv::ID CallConv, bool isVarArg,
2018 const SmallVectorImpl<ISD::InputArg>
2020 SDLoc dl, SelectionDAG &DAG,
2021 SmallVectorImpl<SDValue> &InVals) const {
2023 // 32-bit SVR4 ABI Stack Frame Layout:
2024 // +-----------------------------------+
2025 // +--> | Back chain |
2026 // | +-----------------------------------+
2027 // | | Floating-point register save area |
2028 // | +-----------------------------------+
2029 // | | General register save area |
2030 // | +-----------------------------------+
2031 // | | CR save word |
2032 // | +-----------------------------------+
2033 // | | VRSAVE save word |
2034 // | +-----------------------------------+
2035 // | | Alignment padding |
2036 // | +-----------------------------------+
2037 // | | Vector register save area |
2038 // | +-----------------------------------+
2039 // | | Local variable space |
2040 // | +-----------------------------------+
2041 // | | Parameter list area |
2042 // | +-----------------------------------+
2043 // | | LR save word |
2044 // | +-----------------------------------+
2045 // SP--> +--- | Back chain |
2046 // +-----------------------------------+
2049 // System V Application Binary Interface PowerPC Processor Supplement
2050 // AltiVec Technology Programming Interface Manual
2052 MachineFunction &MF = DAG.getMachineFunction();
2053 MachineFrameInfo *MFI = MF.getFrameInfo();
2054 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2056 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2057 // Potential tail calls could cause overwriting of argument stack slots.
2058 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2059 (CallConv == CallingConv::Fast));
2060 unsigned PtrByteSize = 4;
2062 // Assign locations to all of the incoming arguments.
2063 SmallVector<CCValAssign, 16> ArgLocs;
2064 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2065 getTargetMachine(), ArgLocs, *DAG.getContext());
2067 // Reserve space for the linkage area on the stack.
2068 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2070 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2072 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2073 CCValAssign &VA = ArgLocs[i];
2075 // Arguments stored in registers.
2076 if (VA.isRegLoc()) {
2077 const TargetRegisterClass *RC;
2078 EVT ValVT = VA.getValVT();
2080 switch (ValVT.getSimpleVT().SimpleTy) {
2082 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2085 RC = &PPC::GPRCRegClass;
2088 RC = &PPC::F4RCRegClass;
2091 RC = &PPC::F8RCRegClass;
2097 RC = &PPC::VRRCRegClass;
2101 // Transform the arguments stored in physical registers into virtual ones.
2102 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2103 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2104 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2106 if (ValVT == MVT::i1)
2107 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2109 InVals.push_back(ArgValue);
2111 // Argument stored in memory.
2112 assert(VA.isMemLoc());
2114 unsigned ArgSize = VA.getLocVT().getStoreSize();
2115 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2118 // Create load nodes to retrieve arguments from the stack.
2119 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2120 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2121 MachinePointerInfo(),
2122 false, false, false, 0));
2126 // Assign locations to all of the incoming aggregate by value arguments.
2127 // Aggregates passed by value are stored in the local variable space of the
2128 // caller's stack frame, right above the parameter list area.
2129 SmallVector<CCValAssign, 16> ByValArgLocs;
2130 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2131 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2133 // Reserve stack space for the allocations in CCInfo.
2134 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2136 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2138 // Area that is at least reserved in the caller of this function.
2139 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2141 // Set the size that is at least reserved in caller of this function. Tail
2142 // call optimized function's reserved stack space needs to be aligned so that
2143 // taking the difference between two stack areas will result in an aligned
2145 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2148 std::max(MinReservedArea,
2149 PPCFrameLowering::getMinCallFrameSize(false, false));
2151 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2152 getStackAlignment();
2153 unsigned AlignMask = TargetAlign-1;
2154 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2156 FI->setMinReservedArea(MinReservedArea);
2158 SmallVector<SDValue, 8> MemOps;
2160 // If the function takes variable number of arguments, make a frame index for
2161 // the start of the first vararg value... for expansion of llvm.va_start.
2163 static const uint16_t GPArgRegs[] = {
2164 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2165 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2167 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2169 static const uint16_t FPArgRegs[] = {
2170 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2173 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2175 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2177 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2180 // Make room for NumGPArgRegs and NumFPArgRegs.
2181 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2182 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2184 FuncInfo->setVarArgsStackOffset(
2185 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2186 CCInfo.getNextStackOffset(), true));
2188 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2189 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2191 // The fixed integer arguments of a variadic function are stored to the
2192 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2193 // the result of va_next.
2194 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2195 // Get an existing live-in vreg, or add a new one.
2196 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2198 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2200 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2201 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2202 MachinePointerInfo(), false, false, 0);
2203 MemOps.push_back(Store);
2204 // Increment the address by four for the next argument to store
2205 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2206 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2209 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2211 // The double arguments are stored to the VarArgsFrameIndex
2213 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2214 // Get an existing live-in vreg, or add a new one.
2215 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2217 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2219 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2220 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2221 MachinePointerInfo(), false, false, 0);
2222 MemOps.push_back(Store);
2223 // Increment the address by eight for the next argument to store
2224 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2226 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2230 if (!MemOps.empty())
2231 Chain = DAG.getNode(ISD::TokenFactor, dl,
2232 MVT::Other, &MemOps[0], MemOps.size());
2237 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2238 // value to MVT::i64 and then truncate to the correct register size.
2240 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2241 SelectionDAG &DAG, SDValue ArgVal,
2244 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2245 DAG.getValueType(ObjectVT));
2246 else if (Flags.isZExt())
2247 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2248 DAG.getValueType(ObjectVT));
2250 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2253 // Set the size that is at least reserved in caller of this function. Tail
2254 // call optimized functions' reserved stack space needs to be aligned so that
2255 // taking the difference between two stack areas will result in an aligned
2258 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2259 unsigned nAltivecParamsAtEnd,
2260 unsigned MinReservedArea,
2261 bool isPPC64) const {
2262 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2263 // Add the Altivec parameters at the end, if needed.
2264 if (nAltivecParamsAtEnd) {
2265 MinReservedArea = ((MinReservedArea+15)/16)*16;
2266 MinReservedArea += 16*nAltivecParamsAtEnd;
2269 std::max(MinReservedArea,
2270 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2271 unsigned TargetAlign
2272 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2273 getStackAlignment();
2274 unsigned AlignMask = TargetAlign-1;
2275 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2276 FI->setMinReservedArea(MinReservedArea);
2280 PPCTargetLowering::LowerFormalArguments_64SVR4(
2282 CallingConv::ID CallConv, bool isVarArg,
2283 const SmallVectorImpl<ISD::InputArg>
2285 SDLoc dl, SelectionDAG &DAG,
2286 SmallVectorImpl<SDValue> &InVals) const {
2287 // TODO: add description of PPC stack frame format, or at least some docs.
2289 MachineFunction &MF = DAG.getMachineFunction();
2290 MachineFrameInfo *MFI = MF.getFrameInfo();
2291 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2293 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2294 // Potential tail calls could cause overwriting of argument stack slots.
2295 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2296 (CallConv == CallingConv::Fast));
2297 unsigned PtrByteSize = 8;
2299 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2300 // Area that is at least reserved in caller of this function.
2301 unsigned MinReservedArea = ArgOffset;
2303 static const uint16_t GPR[] = {
2304 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2305 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2308 static const uint16_t *FPR = GetFPR();
2310 static const uint16_t VR[] = {
2311 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2312 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2315 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2316 const unsigned Num_FPR_Regs = 13;
2317 const unsigned Num_VR_Regs = array_lengthof(VR);
2319 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2321 // Add DAG nodes to load the arguments or copy them out of registers. On
2322 // entry to a function on PPC, the arguments start after the linkage area,
2323 // although the first ones are often in registers.
2325 SmallVector<SDValue, 8> MemOps;
2326 unsigned nAltivecParamsAtEnd = 0;
2327 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2328 unsigned CurArgIdx = 0;
2329 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2331 bool needsLoad = false;
2332 EVT ObjectVT = Ins[ArgNo].VT;
2333 unsigned ObjSize = ObjectVT.getStoreSize();
2334 unsigned ArgSize = ObjSize;
2335 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2336 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2337 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2339 unsigned CurArgOffset = ArgOffset;
2341 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2342 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2343 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2345 MinReservedArea = ((MinReservedArea+15)/16)*16;
2346 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2350 nAltivecParamsAtEnd++;
2352 // Calculate min reserved area.
2353 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2357 // FIXME the codegen can be much improved in some cases.
2358 // We do not have to keep everything in memory.
2359 if (Flags.isByVal()) {
2360 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2361 ObjSize = Flags.getByValSize();
2362 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2363 // Empty aggregate parameters do not take up registers. Examples:
2367 // etc. However, we have to provide a place-holder in InVals, so
2368 // pretend we have an 8-byte item at the current address for that
2371 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2372 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2373 InVals.push_back(FIN);
2377 unsigned BVAlign = Flags.getByValAlign();
2379 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2380 CurArgOffset = ArgOffset;
2383 // All aggregates smaller than 8 bytes must be passed right-justified.
2384 if (ObjSize < PtrByteSize)
2385 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2386 // The value of the object is its address.
2387 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2388 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2389 InVals.push_back(FIN);
2392 if (GPR_idx != Num_GPR_Regs) {
2393 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2394 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2397 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2398 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2399 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2400 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2401 MachinePointerInfo(FuncArg),
2402 ObjType, false, false, 0);
2404 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2405 // store the whole register as-is to the parameter save area
2406 // slot. The address of the parameter was already calculated
2407 // above (InVals.push_back(FIN)) to be the right-justified
2408 // offset within the slot. For this store, we need a new
2409 // frame index that points at the beginning of the slot.
2410 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2411 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2412 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2413 MachinePointerInfo(FuncArg),
2417 MemOps.push_back(Store);
2420 // Whether we copied from a register or not, advance the offset
2421 // into the parameter save area by a full doubleword.
2422 ArgOffset += PtrByteSize;
2426 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2427 // Store whatever pieces of the object are in registers
2428 // to memory. ArgOffset will be the address of the beginning
2430 if (GPR_idx != Num_GPR_Regs) {
2432 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2433 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2434 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2435 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2436 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2437 MachinePointerInfo(FuncArg, j),
2439 MemOps.push_back(Store);
2441 ArgOffset += PtrByteSize;
2443 ArgOffset += ArgSize - j;
2450 switch (ObjectVT.getSimpleVT().SimpleTy) {
2451 default: llvm_unreachable("Unhandled argument type!");
2455 if (GPR_idx != Num_GPR_Regs) {
2456 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2457 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2459 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2460 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2461 // value to MVT::i64 and then truncate to the correct register size.
2462 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2467 ArgSize = PtrByteSize;
2474 // Every 8 bytes of argument space consumes one of the GPRs available for
2475 // argument passing.
2476 if (GPR_idx != Num_GPR_Regs) {
2479 if (FPR_idx != Num_FPR_Regs) {
2482 if (ObjectVT == MVT::f32)
2483 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2485 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2487 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2491 ArgSize = PtrByteSize;
2500 // Note that vector arguments in registers don't reserve stack space,
2501 // except in varargs functions.
2502 if (VR_idx != Num_VR_Regs) {
2503 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2504 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2506 while ((ArgOffset % 16) != 0) {
2507 ArgOffset += PtrByteSize;
2508 if (GPR_idx != Num_GPR_Regs)
2512 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2516 // Vectors are aligned.
2517 ArgOffset = ((ArgOffset+15)/16)*16;
2518 CurArgOffset = ArgOffset;
2525 // We need to load the argument to a virtual register if we determined
2526 // above that we ran out of physical registers of the appropriate type.
2528 int FI = MFI->CreateFixedObject(ObjSize,
2529 CurArgOffset + (ArgSize - ObjSize),
2531 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2532 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2533 false, false, false, 0);
2536 InVals.push_back(ArgVal);
2539 // Set the size that is at least reserved in caller of this function. Tail
2540 // call optimized functions' reserved stack space needs to be aligned so that
2541 // taking the difference between two stack areas will result in an aligned
2543 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2545 // If the function takes variable number of arguments, make a frame index for
2546 // the start of the first vararg value... for expansion of llvm.va_start.
2548 int Depth = ArgOffset;
2550 FuncInfo->setVarArgsFrameIndex(
2551 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2552 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2554 // If this function is vararg, store any remaining integer argument regs
2555 // to their spots on the stack so that they may be loaded by deferencing the
2556 // result of va_next.
2557 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2558 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2559 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2560 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2561 MachinePointerInfo(), false, false, 0);
2562 MemOps.push_back(Store);
2563 // Increment the address by four for the next argument to store
2564 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2565 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2569 if (!MemOps.empty())
2570 Chain = DAG.getNode(ISD::TokenFactor, dl,
2571 MVT::Other, &MemOps[0], MemOps.size());
2577 PPCTargetLowering::LowerFormalArguments_Darwin(
2579 CallingConv::ID CallConv, bool isVarArg,
2580 const SmallVectorImpl<ISD::InputArg>
2582 SDLoc dl, SelectionDAG &DAG,
2583 SmallVectorImpl<SDValue> &InVals) const {
2584 // TODO: add description of PPC stack frame format, or at least some docs.
2586 MachineFunction &MF = DAG.getMachineFunction();
2587 MachineFrameInfo *MFI = MF.getFrameInfo();
2588 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2590 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2591 bool isPPC64 = PtrVT == MVT::i64;
2592 // Potential tail calls could cause overwriting of argument stack slots.
2593 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2594 (CallConv == CallingConv::Fast));
2595 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2597 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2598 // Area that is at least reserved in caller of this function.
2599 unsigned MinReservedArea = ArgOffset;
2601 static const uint16_t GPR_32[] = { // 32-bit registers.
2602 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2603 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2605 static const uint16_t GPR_64[] = { // 64-bit registers.
2606 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2607 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2610 static const uint16_t *FPR = GetFPR();
2612 static const uint16_t VR[] = {
2613 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2614 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2617 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2618 const unsigned Num_FPR_Regs = 13;
2619 const unsigned Num_VR_Regs = array_lengthof( VR);
2621 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2623 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2625 // In 32-bit non-varargs functions, the stack space for vectors is after the
2626 // stack space for non-vectors. We do not use this space unless we have
2627 // too many vectors to fit in registers, something that only occurs in
2628 // constructed examples:), but we have to walk the arglist to figure
2629 // that out...for the pathological case, compute VecArgOffset as the
2630 // start of the vector parameter area. Computing VecArgOffset is the
2631 // entire point of the following loop.
2632 unsigned VecArgOffset = ArgOffset;
2633 if (!isVarArg && !isPPC64) {
2634 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2636 EVT ObjectVT = Ins[ArgNo].VT;
2637 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2639 if (Flags.isByVal()) {
2640 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2641 unsigned ObjSize = Flags.getByValSize();
2643 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2644 VecArgOffset += ArgSize;
2648 switch(ObjectVT.getSimpleVT().SimpleTy) {
2649 default: llvm_unreachable("Unhandled argument type!");
2655 case MVT::i64: // PPC64
2657 // FIXME: We are guaranteed to be !isPPC64 at this point.
2658 // Does MVT::i64 apply?
2665 // Nothing to do, we're only looking at Nonvector args here.
2670 // We've found where the vector parameter area in memory is. Skip the
2671 // first 12 parameters; these don't use that memory.
2672 VecArgOffset = ((VecArgOffset+15)/16)*16;
2673 VecArgOffset += 12*16;
2675 // Add DAG nodes to load the arguments or copy them out of registers. On
2676 // entry to a function on PPC, the arguments start after the linkage area,
2677 // although the first ones are often in registers.
2679 SmallVector<SDValue, 8> MemOps;
2680 unsigned nAltivecParamsAtEnd = 0;
2681 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2682 unsigned CurArgIdx = 0;
2683 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2685 bool needsLoad = false;
2686 EVT ObjectVT = Ins[ArgNo].VT;
2687 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2688 unsigned ArgSize = ObjSize;
2689 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2690 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2691 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2693 unsigned CurArgOffset = ArgOffset;
2695 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2696 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2697 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2698 if (isVarArg || isPPC64) {
2699 MinReservedArea = ((MinReservedArea+15)/16)*16;
2700 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2703 } else nAltivecParamsAtEnd++;
2705 // Calculate min reserved area.
2706 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2710 // FIXME the codegen can be much improved in some cases.
2711 // We do not have to keep everything in memory.
2712 if (Flags.isByVal()) {
2713 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2714 ObjSize = Flags.getByValSize();
2715 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2716 // Objects of size 1 and 2 are right justified, everything else is
2717 // left justified. This means the memory address is adjusted forwards.
2718 if (ObjSize==1 || ObjSize==2) {
2719 CurArgOffset = CurArgOffset + (4 - ObjSize);
2721 // The value of the object is its address.
2722 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2723 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2724 InVals.push_back(FIN);
2725 if (ObjSize==1 || ObjSize==2) {
2726 if (GPR_idx != Num_GPR_Regs) {
2729 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2731 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2732 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2733 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2734 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2735 MachinePointerInfo(FuncArg),
2736 ObjType, false, false, 0);
2737 MemOps.push_back(Store);
2741 ArgOffset += PtrByteSize;
2745 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2746 // Store whatever pieces of the object are in registers
2747 // to memory. ArgOffset will be the address of the beginning
2749 if (GPR_idx != Num_GPR_Regs) {
2752 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2754 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2755 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2756 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2757 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2758 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2759 MachinePointerInfo(FuncArg, j),
2761 MemOps.push_back(Store);
2763 ArgOffset += PtrByteSize;
2765 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2772 switch (ObjectVT.getSimpleVT().SimpleTy) {
2773 default: llvm_unreachable("Unhandled argument type!");
2777 if (GPR_idx != Num_GPR_Regs) {
2778 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2779 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2783 ArgSize = PtrByteSize;
2785 // All int arguments reserve stack space in the Darwin ABI.
2786 ArgOffset += PtrByteSize;
2790 case MVT::i64: // PPC64
2791 if (GPR_idx != Num_GPR_Regs) {
2792 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2793 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2795 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2796 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2797 // value to MVT::i64 and then truncate to the correct register size.
2798 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2803 ArgSize = PtrByteSize;
2805 // All int arguments reserve stack space in the Darwin ABI.
2811 // Every 4 bytes of argument space consumes one of the GPRs available for
2812 // argument passing.
2813 if (GPR_idx != Num_GPR_Regs) {
2815 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2818 if (FPR_idx != Num_FPR_Regs) {
2821 if (ObjectVT == MVT::f32)
2822 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2824 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2826 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2832 // All FP arguments reserve stack space in the Darwin ABI.
2833 ArgOffset += isPPC64 ? 8 : ObjSize;
2839 // Note that vector arguments in registers don't reserve stack space,
2840 // except in varargs functions.
2841 if (VR_idx != Num_VR_Regs) {
2842 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2843 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2845 while ((ArgOffset % 16) != 0) {
2846 ArgOffset += PtrByteSize;
2847 if (GPR_idx != Num_GPR_Regs)
2851 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2855 if (!isVarArg && !isPPC64) {
2856 // Vectors go after all the nonvectors.
2857 CurArgOffset = VecArgOffset;
2860 // Vectors are aligned.
2861 ArgOffset = ((ArgOffset+15)/16)*16;
2862 CurArgOffset = ArgOffset;
2870 // We need to load the argument to a virtual register if we determined above
2871 // that we ran out of physical registers of the appropriate type.
2873 int FI = MFI->CreateFixedObject(ObjSize,
2874 CurArgOffset + (ArgSize - ObjSize),
2876 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2877 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2878 false, false, false, 0);
2881 InVals.push_back(ArgVal);
2884 // Set the size that is at least reserved in caller of this function. Tail
2885 // call optimized functions' reserved stack space needs to be aligned so that
2886 // taking the difference between two stack areas will result in an aligned
2888 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2890 // If the function takes variable number of arguments, make a frame index for
2891 // the start of the first vararg value... for expansion of llvm.va_start.
2893 int Depth = ArgOffset;
2895 FuncInfo->setVarArgsFrameIndex(
2896 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2898 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2900 // If this function is vararg, store any remaining integer argument regs
2901 // to their spots on the stack so that they may be loaded by deferencing the
2902 // result of va_next.
2903 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2907 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2909 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2911 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2912 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2913 MachinePointerInfo(), false, false, 0);
2914 MemOps.push_back(Store);
2915 // Increment the address by four for the next argument to store
2916 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2917 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2921 if (!MemOps.empty())
2922 Chain = DAG.getNode(ISD::TokenFactor, dl,
2923 MVT::Other, &MemOps[0], MemOps.size());
2928 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2929 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2931 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2935 const SmallVectorImpl<ISD::OutputArg>
2937 const SmallVectorImpl<SDValue> &OutVals,
2938 unsigned &nAltivecParamsAtEnd) {
2939 // Count how many bytes are to be pushed on the stack, including the linkage
2940 // area, and parameter passing area. We start with 24/48 bytes, which is
2941 // prereserved space for [SP][CR][LR][3 x unused].
2942 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2943 unsigned NumOps = Outs.size();
2944 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2946 // Add up all the space actually used.
2947 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2948 // they all go in registers, but we must reserve stack space for them for
2949 // possible use by the caller. In varargs or 64-bit calls, parameters are
2950 // assigned stack space in order, with padding so Altivec parameters are
2952 nAltivecParamsAtEnd = 0;
2953 for (unsigned i = 0; i != NumOps; ++i) {
2954 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2955 EVT ArgVT = Outs[i].VT;
2956 // Varargs Altivec parameters are padded to a 16 byte boundary.
2957 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2958 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2959 if (!isVarArg && !isPPC64) {
2960 // Non-varargs Altivec parameters go after all the non-Altivec
2961 // parameters; handle those later so we know how much padding we need.
2962 nAltivecParamsAtEnd++;
2965 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2966 NumBytes = ((NumBytes+15)/16)*16;
2968 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2971 // Allow for Altivec parameters at the end, if needed.
2972 if (nAltivecParamsAtEnd) {
2973 NumBytes = ((NumBytes+15)/16)*16;
2974 NumBytes += 16*nAltivecParamsAtEnd;
2977 // The prolog code of the callee may store up to 8 GPR argument registers to
2978 // the stack, allowing va_start to index over them in memory if its varargs.
2979 // Because we cannot tell if this is needed on the caller side, we have to
2980 // conservatively assume that it is needed. As such, make sure we have at
2981 // least enough stack space for the caller to store the 8 GPRs.
2982 NumBytes = std::max(NumBytes,
2983 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2985 // Tail call needs the stack to be aligned.
2986 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2987 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2988 getFrameLowering()->getStackAlignment();
2989 unsigned AlignMask = TargetAlign-1;
2990 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2996 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2997 /// adjusted to accommodate the arguments for the tailcall.
2998 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2999 unsigned ParamSize) {
3001 if (!isTailCall) return 0;
3003 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3004 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3005 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3006 // Remember only if the new adjustement is bigger.
3007 if (SPDiff < FI->getTailCallSPDelta())
3008 FI->setTailCallSPDelta(SPDiff);
3013 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3014 /// for tail call optimization. Targets which want to do tail call
3015 /// optimization should implement this function.
3017 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3018 CallingConv::ID CalleeCC,
3020 const SmallVectorImpl<ISD::InputArg> &Ins,
3021 SelectionDAG& DAG) const {
3022 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3025 // Variable argument functions are not supported.
3029 MachineFunction &MF = DAG.getMachineFunction();
3030 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3031 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3032 // Functions containing by val parameters are not supported.
3033 for (unsigned i = 0; i != Ins.size(); i++) {
3034 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3035 if (Flags.isByVal()) return false;
3038 // Non-PIC/GOT tail calls are supported.
3039 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3042 // At the moment we can only do local tail calls (in same module, hidden
3043 // or protected) if we are generating PIC.
3044 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3045 return G->getGlobal()->hasHiddenVisibility()
3046 || G->getGlobal()->hasProtectedVisibility();
3052 /// isCallCompatibleAddress - Return the immediate to use if the specified
3053 /// 32-bit value is representable in the immediate field of a BxA instruction.
3054 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3055 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3058 int Addr = C->getZExtValue();
3059 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3060 SignExtend32<26>(Addr) != Addr)
3061 return 0; // Top 6 bits have to be sext of immediate.
3063 return DAG.getConstant((int)C->getZExtValue() >> 2,
3064 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3069 struct TailCallArgumentInfo {
3074 TailCallArgumentInfo() : FrameIdx(0) {}
3079 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3081 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3083 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3084 SmallVectorImpl<SDValue> &MemOpChains,
3086 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3087 SDValue Arg = TailCallArgs[i].Arg;
3088 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3089 int FI = TailCallArgs[i].FrameIdx;
3090 // Store relative to framepointer.
3091 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3092 MachinePointerInfo::getFixedStack(FI),
3097 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3098 /// the appropriate stack slot for the tail call optimized function call.
3099 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3100 MachineFunction &MF,
3109 // Calculate the new stack slot for the return address.
3110 int SlotSize = isPPC64 ? 8 : 4;
3111 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3113 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3114 NewRetAddrLoc, true);
3115 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3116 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3117 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3118 MachinePointerInfo::getFixedStack(NewRetAddr),
3121 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3122 // slot as the FP is never overwritten.
3125 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3126 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3128 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3129 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3130 MachinePointerInfo::getFixedStack(NewFPIdx),
3137 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3138 /// the position of the argument.
3140 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3141 SDValue Arg, int SPDiff, unsigned ArgOffset,
3142 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3143 int Offset = ArgOffset + SPDiff;
3144 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3145 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3146 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3147 SDValue FIN = DAG.getFrameIndex(FI, VT);
3148 TailCallArgumentInfo Info;
3150 Info.FrameIdxOp = FIN;
3152 TailCallArguments.push_back(Info);
3155 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3156 /// stack slot. Returns the chain as result and the loaded frame pointers in
3157 /// LROpOut/FPOpout. Used when tail calling.
3158 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3166 // Load the LR and FP stack slot for later adjusting.
3167 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3168 LROpOut = getReturnAddrFrameIndex(DAG);
3169 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3170 false, false, false, 0);
3171 Chain = SDValue(LROpOut.getNode(), 1);
3173 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3174 // slot as the FP is never overwritten.
3176 FPOpOut = getFramePointerFrameIndex(DAG);
3177 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3178 false, false, false, 0);
3179 Chain = SDValue(FPOpOut.getNode(), 1);
3185 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3186 /// by "Src" to address "Dst" of size "Size". Alignment information is
3187 /// specified by the specific parameter attribute. The copy will be passed as
3188 /// a byval function parameter.
3189 /// Sometimes what we are copying is the end of a larger object, the part that
3190 /// does not fit in registers.
3192 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3193 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3195 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3196 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3197 false, false, MachinePointerInfo(0),
3198 MachinePointerInfo(0));
3201 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3204 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3205 SDValue Arg, SDValue PtrOff, int SPDiff,
3206 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3207 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3208 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3210 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3215 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3217 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3218 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3219 DAG.getConstant(ArgOffset, PtrVT));
3221 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3222 MachinePointerInfo(), false, false, 0));
3223 // Calculate and remember argument location.
3224 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3229 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3230 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3231 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3232 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3233 MachineFunction &MF = DAG.getMachineFunction();
3235 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3236 // might overwrite each other in case of tail call optimization.
3237 SmallVector<SDValue, 8> MemOpChains2;
3238 // Do not flag preceding copytoreg stuff together with the following stuff.
3240 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3242 if (!MemOpChains2.empty())
3243 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3244 &MemOpChains2[0], MemOpChains2.size());
3246 // Store the return address to the appropriate stack slot.
3247 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3248 isPPC64, isDarwinABI, dl);
3250 // Emit callseq_end just before tailcall node.
3251 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3252 DAG.getIntPtrConstant(0, true), InFlag, dl);
3253 InFlag = Chain.getValue(1);
3257 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3258 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3259 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3260 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3261 const PPCSubtarget &PPCSubTarget) {
3263 bool isPPC64 = PPCSubTarget.isPPC64();
3264 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3266 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3267 NodeTys.push_back(MVT::Other); // Returns a chain
3268 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3270 unsigned CallOpc = PPCISD::CALL;
3272 bool needIndirectCall = true;
3273 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3274 // If this is an absolute destination address, use the munged value.
3275 Callee = SDValue(Dest, 0);
3276 needIndirectCall = false;
3279 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3280 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3281 // Use indirect calls for ALL functions calls in JIT mode, since the
3282 // far-call stubs may be outside relocation limits for a BL instruction.
3283 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3284 unsigned OpFlags = 0;
3285 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3286 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3287 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3288 (G->getGlobal()->isDeclaration() ||
3289 G->getGlobal()->isWeakForLinker())) {
3290 // PC-relative references to external symbols should go through $stub,
3291 // unless we're building with the leopard linker or later, which
3292 // automatically synthesizes these stubs.
3293 OpFlags = PPCII::MO_DARWIN_STUB;
3296 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3297 // every direct call is) turn it into a TargetGlobalAddress /
3298 // TargetExternalSymbol node so that legalize doesn't hack it.
3299 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3300 Callee.getValueType(),
3302 needIndirectCall = false;
3306 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3307 unsigned char OpFlags = 0;
3309 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3310 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3311 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3312 // PC-relative references to external symbols should go through $stub,
3313 // unless we're building with the leopard linker or later, which
3314 // automatically synthesizes these stubs.
3315 OpFlags = PPCII::MO_DARWIN_STUB;
3318 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3320 needIndirectCall = false;
3323 if (needIndirectCall) {
3324 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3325 // to do the call, we can't use PPCISD::CALL.
3326 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3328 if (isSVR4ABI && isPPC64) {
3329 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3330 // entry point, but to the function descriptor (the function entry point
3331 // address is part of the function descriptor though).
3332 // The function descriptor is a three doubleword structure with the
3333 // following fields: function entry point, TOC base address and
3334 // environment pointer.
3335 // Thus for a call through a function pointer, the following actions need
3337 // 1. Save the TOC of the caller in the TOC save area of its stack
3338 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3339 // 2. Load the address of the function entry point from the function
3341 // 3. Load the TOC of the callee from the function descriptor into r2.
3342 // 4. Load the environment pointer from the function descriptor into
3344 // 5. Branch to the function entry point address.
3345 // 6. On return of the callee, the TOC of the caller needs to be
3346 // restored (this is done in FinishCall()).
3348 // All those operations are flagged together to ensure that no other
3349 // operations can be scheduled in between. E.g. without flagging the
3350 // operations together, a TOC access in the caller could be scheduled
3351 // between the load of the callee TOC and the branch to the callee, which
3352 // results in the TOC access going through the TOC of the callee instead
3353 // of going through the TOC of the caller, which leads to incorrect code.
3355 // Load the address of the function entry point from the function
3357 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3358 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3359 InFlag.getNode() ? 3 : 2);
3360 Chain = LoadFuncPtr.getValue(1);
3361 InFlag = LoadFuncPtr.getValue(2);
3363 // Load environment pointer into r11.
3364 // Offset of the environment pointer within the function descriptor.
3365 SDValue PtrOff = DAG.getIntPtrConstant(16);
3367 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3368 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3370 Chain = LoadEnvPtr.getValue(1);
3371 InFlag = LoadEnvPtr.getValue(2);
3373 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3375 Chain = EnvVal.getValue(0);
3376 InFlag = EnvVal.getValue(1);
3378 // Load TOC of the callee into r2. We are using a target-specific load
3379 // with r2 hard coded, because the result of a target-independent load
3380 // would never go directly into r2, since r2 is a reserved register (which
3381 // prevents the register allocator from allocating it), resulting in an
3382 // additional register being allocated and an unnecessary move instruction
3384 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3385 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3387 Chain = LoadTOCPtr.getValue(0);
3388 InFlag = LoadTOCPtr.getValue(1);
3390 MTCTROps[0] = Chain;
3391 MTCTROps[1] = LoadFuncPtr;
3392 MTCTROps[2] = InFlag;
3395 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3396 2 + (InFlag.getNode() != 0));
3397 InFlag = Chain.getValue(1);
3400 NodeTys.push_back(MVT::Other);
3401 NodeTys.push_back(MVT::Glue);
3402 Ops.push_back(Chain);
3403 CallOpc = PPCISD::BCTRL;
3405 // Add use of X11 (holding environment pointer)
3406 if (isSVR4ABI && isPPC64)
3407 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3408 // Add CTR register as callee so a bctr can be emitted later.
3410 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3413 // If this is a direct call, pass the chain and the callee.
3414 if (Callee.getNode()) {
3415 Ops.push_back(Chain);
3416 Ops.push_back(Callee);
3418 // If this is a tail call add stack pointer delta.
3420 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3422 // Add argument registers to the end of the list so that they are known live
3424 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3425 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3426 RegsToPass[i].second.getValueType()));
3432 bool isLocalCall(const SDValue &Callee)
3434 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3435 return !G->getGlobal()->isDeclaration() &&
3436 !G->getGlobal()->isWeakForLinker();
3441 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3442 CallingConv::ID CallConv, bool isVarArg,
3443 const SmallVectorImpl<ISD::InputArg> &Ins,
3444 SDLoc dl, SelectionDAG &DAG,
3445 SmallVectorImpl<SDValue> &InVals) const {
3447 SmallVector<CCValAssign, 16> RVLocs;
3448 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3449 getTargetMachine(), RVLocs, *DAG.getContext());
3450 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3452 // Copy all of the result registers out of their specified physreg.
3453 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3454 CCValAssign &VA = RVLocs[i];
3455 assert(VA.isRegLoc() && "Can only return in registers!");
3457 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3458 VA.getLocReg(), VA.getLocVT(), InFlag);
3459 Chain = Val.getValue(1);
3460 InFlag = Val.getValue(2);
3462 switch (VA.getLocInfo()) {
3463 default: llvm_unreachable("Unknown loc info!");
3464 case CCValAssign::Full: break;
3465 case CCValAssign::AExt:
3466 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3468 case CCValAssign::ZExt:
3469 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3470 DAG.getValueType(VA.getValVT()));
3471 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3473 case CCValAssign::SExt:
3474 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3475 DAG.getValueType(VA.getValVT()));
3476 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3480 InVals.push_back(Val);
3487 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3488 bool isTailCall, bool isVarArg,
3490 SmallVector<std::pair<unsigned, SDValue>, 8>
3492 SDValue InFlag, SDValue Chain,
3494 int SPDiff, unsigned NumBytes,
3495 const SmallVectorImpl<ISD::InputArg> &Ins,
3496 SmallVectorImpl<SDValue> &InVals) const {
3497 std::vector<EVT> NodeTys;
3498 SmallVector<SDValue, 8> Ops;
3499 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3500 isTailCall, RegsToPass, Ops, NodeTys,
3503 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3504 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3505 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3507 // When performing tail call optimization the callee pops its arguments off
3508 // the stack. Account for this here so these bytes can be pushed back on in
3509 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3510 int BytesCalleePops =
3511 (CallConv == CallingConv::Fast &&
3512 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3514 // Add a register mask operand representing the call-preserved registers.
3515 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3516 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3517 assert(Mask && "Missing call preserved mask for calling convention");
3518 Ops.push_back(DAG.getRegisterMask(Mask));
3520 if (InFlag.getNode())
3521 Ops.push_back(InFlag);
3525 assert(((Callee.getOpcode() == ISD::Register &&
3526 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3527 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3528 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3529 isa<ConstantSDNode>(Callee)) &&
3530 "Expecting an global address, external symbol, absolute value or register");
3532 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3535 // Add a NOP immediately after the branch instruction when using the 64-bit
3536 // SVR4 ABI. At link time, if caller and callee are in a different module and
3537 // thus have a different TOC, the call will be replaced with a call to a stub
3538 // function which saves the current TOC, loads the TOC of the callee and
3539 // branches to the callee. The NOP will be replaced with a load instruction
3540 // which restores the TOC of the caller from the TOC save slot of the current
3541 // stack frame. If caller and callee belong to the same module (and have the
3542 // same TOC), the NOP will remain unchanged.
3544 bool needsTOCRestore = false;
3545 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3546 if (CallOpc == PPCISD::BCTRL) {
3547 // This is a call through a function pointer.
3548 // Restore the caller TOC from the save area into R2.
3549 // See PrepareCall() for more information about calls through function
3550 // pointers in the 64-bit SVR4 ABI.
3551 // We are using a target-specific load with r2 hard coded, because the
3552 // result of a target-independent load would never go directly into r2,
3553 // since r2 is a reserved register (which prevents the register allocator
3554 // from allocating it), resulting in an additional register being
3555 // allocated and an unnecessary move instruction being generated.
3556 needsTOCRestore = true;
3557 } else if ((CallOpc == PPCISD::CALL) &&
3558 (!isLocalCall(Callee) ||
3559 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3560 // Otherwise insert NOP for non-local calls.
3561 CallOpc = PPCISD::CALL_NOP;
3565 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3566 InFlag = Chain.getValue(1);
3568 if (needsTOCRestore) {
3569 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3570 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3571 InFlag = Chain.getValue(1);
3574 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3575 DAG.getIntPtrConstant(BytesCalleePops, true),
3578 InFlag = Chain.getValue(1);
3580 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3581 Ins, dl, DAG, InVals);
3585 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3586 SmallVectorImpl<SDValue> &InVals) const {
3587 SelectionDAG &DAG = CLI.DAG;
3589 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3590 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3591 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3592 SDValue Chain = CLI.Chain;
3593 SDValue Callee = CLI.Callee;
3594 bool &isTailCall = CLI.IsTailCall;
3595 CallingConv::ID CallConv = CLI.CallConv;
3596 bool isVarArg = CLI.IsVarArg;
3599 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3602 if (PPCSubTarget.isSVR4ABI()) {
3603 if (PPCSubTarget.isPPC64())
3604 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3605 isTailCall, Outs, OutVals, Ins,
3608 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3609 isTailCall, Outs, OutVals, Ins,
3613 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3614 isTailCall, Outs, OutVals, Ins,
3619 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3620 CallingConv::ID CallConv, bool isVarArg,
3622 const SmallVectorImpl<ISD::OutputArg> &Outs,
3623 const SmallVectorImpl<SDValue> &OutVals,
3624 const SmallVectorImpl<ISD::InputArg> &Ins,
3625 SDLoc dl, SelectionDAG &DAG,
3626 SmallVectorImpl<SDValue> &InVals) const {
3627 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3628 // of the 32-bit SVR4 ABI stack frame layout.
3630 assert((CallConv == CallingConv::C ||
3631 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3633 unsigned PtrByteSize = 4;
3635 MachineFunction &MF = DAG.getMachineFunction();
3637 // Mark this function as potentially containing a function that contains a
3638 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3639 // and restoring the callers stack pointer in this functions epilog. This is
3640 // done because by tail calling the called function might overwrite the value
3641 // in this function's (MF) stack pointer stack slot 0(SP).
3642 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3643 CallConv == CallingConv::Fast)
3644 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3646 // Count how many bytes are to be pushed on the stack, including the linkage
3647 // area, parameter list area and the part of the local variable space which
3648 // contains copies of aggregates which are passed by value.
3650 // Assign locations to all of the outgoing arguments.
3651 SmallVector<CCValAssign, 16> ArgLocs;
3652 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3653 getTargetMachine(), ArgLocs, *DAG.getContext());
3655 // Reserve space for the linkage area on the stack.
3656 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3659 // Handle fixed and variable vector arguments differently.
3660 // Fixed vector arguments go into registers as long as registers are
3661 // available. Variable vector arguments always go into memory.
3662 unsigned NumArgs = Outs.size();
3664 for (unsigned i = 0; i != NumArgs; ++i) {
3665 MVT ArgVT = Outs[i].VT;
3666 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3669 if (Outs[i].IsFixed) {
3670 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3673 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3679 errs() << "Call operand #" << i << " has unhandled type "
3680 << EVT(ArgVT).getEVTString() << "\n";
3682 llvm_unreachable(0);
3686 // All arguments are treated the same.
3687 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3690 // Assign locations to all of the outgoing aggregate by value arguments.
3691 SmallVector<CCValAssign, 16> ByValArgLocs;
3692 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3693 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3695 // Reserve stack space for the allocations in CCInfo.
3696 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3698 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3700 // Size of the linkage area, parameter list area and the part of the local
3701 // space variable where copies of aggregates which are passed by value are
3703 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3705 // Calculate by how many bytes the stack has to be adjusted in case of tail
3706 // call optimization.
3707 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3709 // Adjust the stack pointer for the new arguments...
3710 // These operations are automatically eliminated by the prolog/epilog pass
3711 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3713 SDValue CallSeqStart = Chain;
3715 // Load the return address and frame pointer so it can be moved somewhere else
3718 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3721 // Set up a copy of the stack pointer for use loading and storing any
3722 // arguments that may not fit in the registers available for argument
3724 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3726 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3727 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3728 SmallVector<SDValue, 8> MemOpChains;
3730 bool seenFloatArg = false;
3731 // Walk the register/memloc assignments, inserting copies/loads.
3732 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3735 CCValAssign &VA = ArgLocs[i];
3736 SDValue Arg = OutVals[i];
3737 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3739 if (Flags.isByVal()) {
3740 // Argument is an aggregate which is passed by value, thus we need to
3741 // create a copy of it in the local variable space of the current stack
3742 // frame (which is the stack frame of the caller) and pass the address of
3743 // this copy to the callee.
3744 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3745 CCValAssign &ByValVA = ByValArgLocs[j++];
3746 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3748 // Memory reserved in the local variable space of the callers stack frame.
3749 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3751 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3752 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3754 // Create a copy of the argument in the local area of the current
3756 SDValue MemcpyCall =
3757 CreateCopyOfByValArgument(Arg, PtrOff,
3758 CallSeqStart.getNode()->getOperand(0),
3761 // This must go outside the CALLSEQ_START..END.
3762 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3763 CallSeqStart.getNode()->getOperand(1),
3765 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3766 NewCallSeqStart.getNode());
3767 Chain = CallSeqStart = NewCallSeqStart;
3769 // Pass the address of the aggregate copy on the stack either in a
3770 // physical register or in the parameter list area of the current stack
3771 // frame to the callee.
3775 if (VA.isRegLoc()) {
3776 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3777 // Put argument in a physical register.
3778 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3780 // Put argument in the parameter list area of the current stack frame.
3781 assert(VA.isMemLoc());
3782 unsigned LocMemOffset = VA.getLocMemOffset();
3785 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3786 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3788 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3789 MachinePointerInfo(),
3792 // Calculate and remember argument location.
3793 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3799 if (!MemOpChains.empty())
3800 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3801 &MemOpChains[0], MemOpChains.size());
3803 // Build a sequence of copy-to-reg nodes chained together with token chain
3804 // and flag operands which copy the outgoing args into the appropriate regs.
3806 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3807 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3808 RegsToPass[i].second, InFlag);
3809 InFlag = Chain.getValue(1);
3812 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3815 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3816 SDValue Ops[] = { Chain, InFlag };
3818 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3819 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3821 InFlag = Chain.getValue(1);
3825 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3826 false, TailCallArguments);
3828 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3829 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3833 // Copy an argument into memory, being careful to do this outside the
3834 // call sequence for the call to which the argument belongs.
3836 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3837 SDValue CallSeqStart,
3838 ISD::ArgFlagsTy Flags,
3841 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3842 CallSeqStart.getNode()->getOperand(0),
3844 // The MEMCPY must go outside the CALLSEQ_START..END.
3845 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3846 CallSeqStart.getNode()->getOperand(1),
3848 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3849 NewCallSeqStart.getNode());
3850 return NewCallSeqStart;
3854 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3855 CallingConv::ID CallConv, bool isVarArg,
3857 const SmallVectorImpl<ISD::OutputArg> &Outs,
3858 const SmallVectorImpl<SDValue> &OutVals,
3859 const SmallVectorImpl<ISD::InputArg> &Ins,
3860 SDLoc dl, SelectionDAG &DAG,
3861 SmallVectorImpl<SDValue> &InVals) const {
3863 unsigned NumOps = Outs.size();
3865 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3866 unsigned PtrByteSize = 8;
3868 MachineFunction &MF = DAG.getMachineFunction();
3870 // Mark this function as potentially containing a function that contains a
3871 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3872 // and restoring the callers stack pointer in this functions epilog. This is
3873 // done because by tail calling the called function might overwrite the value
3874 // in this function's (MF) stack pointer stack slot 0(SP).
3875 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3876 CallConv == CallingConv::Fast)
3877 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3879 unsigned nAltivecParamsAtEnd = 0;
3881 // Count how many bytes are to be pushed on the stack, including the linkage
3882 // area, and parameter passing area. We start with at least 48 bytes, which
3883 // is reserved space for [SP][CR][LR][3 x unused].
3884 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3887 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3888 Outs, OutVals, nAltivecParamsAtEnd);
3890 // Calculate by how many bytes the stack has to be adjusted in case of tail
3891 // call optimization.
3892 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3894 // To protect arguments on the stack from being clobbered in a tail call,
3895 // force all the loads to happen before doing any other lowering.
3897 Chain = DAG.getStackArgumentTokenFactor(Chain);
3899 // Adjust the stack pointer for the new arguments...
3900 // These operations are automatically eliminated by the prolog/epilog pass
3901 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3903 SDValue CallSeqStart = Chain;
3905 // Load the return address and frame pointer so it can be move somewhere else
3908 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3911 // Set up a copy of the stack pointer for use loading and storing any
3912 // arguments that may not fit in the registers available for argument
3914 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3916 // Figure out which arguments are going to go in registers, and which in
3917 // memory. Also, if this is a vararg function, floating point operations
3918 // must be stored to our stack, and loaded into integer regs as well, if
3919 // any integer regs are available for argument passing.
3920 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3921 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3923 static const uint16_t GPR[] = {
3924 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3925 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3927 static const uint16_t *FPR = GetFPR();
3929 static const uint16_t VR[] = {
3930 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3931 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3933 const unsigned NumGPRs = array_lengthof(GPR);
3934 const unsigned NumFPRs = 13;
3935 const unsigned NumVRs = array_lengthof(VR);
3937 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3938 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3940 SmallVector<SDValue, 8> MemOpChains;
3941 for (unsigned i = 0; i != NumOps; ++i) {
3942 SDValue Arg = OutVals[i];
3943 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3945 // PtrOff will be used to store the current argument to the stack if a
3946 // register cannot be found for it.
3949 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3951 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3953 // Promote integers to 64-bit values.
3954 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
3955 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3956 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3957 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3960 // FIXME memcpy is used way more than necessary. Correctness first.
3961 // Note: "by value" is code for passing a structure by value, not
3963 if (Flags.isByVal()) {
3964 // Note: Size includes alignment padding, so
3965 // struct x { short a; char b; }
3966 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3967 // These are the proper values we need for right-justifying the
3968 // aggregate in a parameter register.
3969 unsigned Size = Flags.getByValSize();
3971 // An empty aggregate parameter takes up no storage and no
3976 unsigned BVAlign = Flags.getByValAlign();
3978 if (BVAlign % PtrByteSize != 0)
3980 "ByVal alignment is not a multiple of the pointer size");
3982 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
3985 // All aggregates smaller than 8 bytes must be passed right-justified.
3986 if (Size==1 || Size==2 || Size==4) {
3987 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3988 if (GPR_idx != NumGPRs) {
3989 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3990 MachinePointerInfo(), VT,
3992 MemOpChains.push_back(Load.getValue(1));
3993 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3995 ArgOffset += PtrByteSize;
4000 if (GPR_idx == NumGPRs && Size < 8) {
4001 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4002 PtrOff.getValueType());
4003 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4004 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4007 ArgOffset += PtrByteSize;
4010 // Copy entire object into memory. There are cases where gcc-generated
4011 // code assumes it is there, even if it could be put entirely into
4012 // registers. (This is not what the doc says.)
4014 // FIXME: The above statement is likely due to a misunderstanding of the
4015 // documents. All arguments must be copied into the parameter area BY
4016 // THE CALLEE in the event that the callee takes the address of any
4017 // formal argument. That has not yet been implemented. However, it is
4018 // reasonable to use the stack area as a staging area for the register
4021 // Skip this for small aggregates, as we will use the same slot for a
4022 // right-justified copy, below.
4024 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4028 // When a register is available, pass a small aggregate right-justified.
4029 if (Size < 8 && GPR_idx != NumGPRs) {
4030 // The easiest way to get this right-justified in a register
4031 // is to copy the structure into the rightmost portion of a
4032 // local variable slot, then load the whole slot into the
4034 // FIXME: The memcpy seems to produce pretty awful code for
4035 // small aggregates, particularly for packed ones.
4036 // FIXME: It would be preferable to use the slot in the
4037 // parameter save area instead of a new local variable.
4038 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4039 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4040 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4044 // Load the slot into the register.
4045 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4046 MachinePointerInfo(),
4047 false, false, false, 0);
4048 MemOpChains.push_back(Load.getValue(1));
4049 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4051 // Done with this argument.
4052 ArgOffset += PtrByteSize;
4056 // For aggregates larger than PtrByteSize, copy the pieces of the
4057 // object that fit into registers from the parameter save area.
4058 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4059 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4060 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4061 if (GPR_idx != NumGPRs) {
4062 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4063 MachinePointerInfo(),
4064 false, false, false, 0);
4065 MemOpChains.push_back(Load.getValue(1));
4066 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4067 ArgOffset += PtrByteSize;
4069 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4076 switch (Arg.getSimpleValueType().SimpleTy) {
4077 default: llvm_unreachable("Unexpected ValueType for argument!");
4081 if (GPR_idx != NumGPRs) {
4082 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4084 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4085 true, isTailCall, false, MemOpChains,
4086 TailCallArguments, dl);
4088 ArgOffset += PtrByteSize;
4092 if (FPR_idx != NumFPRs) {
4093 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4096 // A single float or an aggregate containing only a single float
4097 // must be passed right-justified in the stack doubleword, and
4098 // in the GPR, if one is available.
4100 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
4101 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4102 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4106 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4107 MachinePointerInfo(), false, false, 0);
4108 MemOpChains.push_back(Store);
4110 // Float varargs are always shadowed in available integer registers
4111 if (GPR_idx != NumGPRs) {
4112 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4113 MachinePointerInfo(), false, false,
4115 MemOpChains.push_back(Load.getValue(1));
4116 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4118 } else if (GPR_idx != NumGPRs)
4119 // If we have any FPRs remaining, we may also have GPRs remaining.
4122 // Single-precision floating-point values are mapped to the
4123 // second (rightmost) word of the stack doubleword.
4124 if (Arg.getValueType() == MVT::f32) {
4125 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4126 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4129 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4130 true, isTailCall, false, MemOpChains,
4131 TailCallArguments, dl);
4140 // These go aligned on the stack, or in the corresponding R registers
4141 // when within range. The Darwin PPC ABI doc claims they also go in
4142 // V registers; in fact gcc does this only for arguments that are
4143 // prototyped, not for those that match the ... We do it for all
4144 // arguments, seems to work.
4145 while (ArgOffset % 16 !=0) {
4146 ArgOffset += PtrByteSize;
4147 if (GPR_idx != NumGPRs)
4150 // We could elide this store in the case where the object fits
4151 // entirely in R registers. Maybe later.
4152 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4153 DAG.getConstant(ArgOffset, PtrVT));
4154 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4155 MachinePointerInfo(), false, false, 0);
4156 MemOpChains.push_back(Store);
4157 if (VR_idx != NumVRs) {
4158 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4159 MachinePointerInfo(),
4160 false, false, false, 0);
4161 MemOpChains.push_back(Load.getValue(1));
4162 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4165 for (unsigned i=0; i<16; i+=PtrByteSize) {
4166 if (GPR_idx == NumGPRs)
4168 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4169 DAG.getConstant(i, PtrVT));
4170 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4171 false, false, false, 0);
4172 MemOpChains.push_back(Load.getValue(1));
4173 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4178 // Non-varargs Altivec params generally go in registers, but have
4179 // stack space allocated at the end.
4180 if (VR_idx != NumVRs) {
4181 // Doesn't have GPR space allocated.
4182 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4184 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4185 true, isTailCall, true, MemOpChains,
4186 TailCallArguments, dl);
4193 if (!MemOpChains.empty())
4194 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4195 &MemOpChains[0], MemOpChains.size());
4197 // Check if this is an indirect call (MTCTR/BCTRL).
4198 // See PrepareCall() for more information about calls through function
4199 // pointers in the 64-bit SVR4 ABI.
4201 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4202 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4203 !isBLACompatibleAddress(Callee, DAG)) {
4204 // Load r2 into a virtual register and store it to the TOC save area.
4205 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4206 // TOC save area offset.
4207 SDValue PtrOff = DAG.getIntPtrConstant(40);
4208 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4209 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4211 // R12 must contain the address of an indirect callee. This does not
4212 // mean the MTCTR instruction must use R12; it's easier to model this
4213 // as an extra parameter, so do that.
4214 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4217 // Build a sequence of copy-to-reg nodes chained together with token chain
4218 // and flag operands which copy the outgoing args into the appropriate regs.
4220 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4221 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4222 RegsToPass[i].second, InFlag);
4223 InFlag = Chain.getValue(1);
4227 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4228 FPOp, true, TailCallArguments);
4230 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4231 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4236 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4237 CallingConv::ID CallConv, bool isVarArg,
4239 const SmallVectorImpl<ISD::OutputArg> &Outs,
4240 const SmallVectorImpl<SDValue> &OutVals,
4241 const SmallVectorImpl<ISD::InputArg> &Ins,
4242 SDLoc dl, SelectionDAG &DAG,
4243 SmallVectorImpl<SDValue> &InVals) const {
4245 unsigned NumOps = Outs.size();
4247 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4248 bool isPPC64 = PtrVT == MVT::i64;
4249 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4251 MachineFunction &MF = DAG.getMachineFunction();
4253 // Mark this function as potentially containing a function that contains a
4254 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4255 // and restoring the callers stack pointer in this functions epilog. This is
4256 // done because by tail calling the called function might overwrite the value
4257 // in this function's (MF) stack pointer stack slot 0(SP).
4258 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4259 CallConv == CallingConv::Fast)
4260 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4262 unsigned nAltivecParamsAtEnd = 0;
4264 // Count how many bytes are to be pushed on the stack, including the linkage
4265 // area, and parameter passing area. We start with 24/48 bytes, which is
4266 // prereserved space for [SP][CR][LR][3 x unused].
4268 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4270 nAltivecParamsAtEnd);
4272 // Calculate by how many bytes the stack has to be adjusted in case of tail
4273 // call optimization.
4274 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4276 // To protect arguments on the stack from being clobbered in a tail call,
4277 // force all the loads to happen before doing any other lowering.
4279 Chain = DAG.getStackArgumentTokenFactor(Chain);
4281 // Adjust the stack pointer for the new arguments...
4282 // These operations are automatically eliminated by the prolog/epilog pass
4283 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4285 SDValue CallSeqStart = Chain;
4287 // Load the return address and frame pointer so it can be move somewhere else
4290 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4293 // Set up a copy of the stack pointer for use loading and storing any
4294 // arguments that may not fit in the registers available for argument
4298 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4300 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4302 // Figure out which arguments are going to go in registers, and which in
4303 // memory. Also, if this is a vararg function, floating point operations
4304 // must be stored to our stack, and loaded into integer regs as well, if
4305 // any integer regs are available for argument passing.
4306 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4307 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4309 static const uint16_t GPR_32[] = { // 32-bit registers.
4310 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4311 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4313 static const uint16_t GPR_64[] = { // 64-bit registers.
4314 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4315 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4317 static const uint16_t *FPR = GetFPR();
4319 static const uint16_t VR[] = {
4320 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4321 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4323 const unsigned NumGPRs = array_lengthof(GPR_32);
4324 const unsigned NumFPRs = 13;
4325 const unsigned NumVRs = array_lengthof(VR);
4327 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4329 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4330 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4332 SmallVector<SDValue, 8> MemOpChains;
4333 for (unsigned i = 0; i != NumOps; ++i) {
4334 SDValue Arg = OutVals[i];
4335 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4337 // PtrOff will be used to store the current argument to the stack if a
4338 // register cannot be found for it.
4341 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4343 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4345 // On PPC64, promote integers to 64-bit values.
4346 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4347 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4348 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4349 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4352 // FIXME memcpy is used way more than necessary. Correctness first.
4353 // Note: "by value" is code for passing a structure by value, not
4355 if (Flags.isByVal()) {
4356 unsigned Size = Flags.getByValSize();
4357 // Very small objects are passed right-justified. Everything else is
4358 // passed left-justified.
4359 if (Size==1 || Size==2) {
4360 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4361 if (GPR_idx != NumGPRs) {
4362 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4363 MachinePointerInfo(), VT,
4365 MemOpChains.push_back(Load.getValue(1));
4366 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4368 ArgOffset += PtrByteSize;
4370 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4371 PtrOff.getValueType());
4372 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4373 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4376 ArgOffset += PtrByteSize;
4380 // Copy entire object into memory. There are cases where gcc-generated
4381 // code assumes it is there, even if it could be put entirely into
4382 // registers. (This is not what the doc says.)
4383 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4387 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4388 // copy the pieces of the object that fit into registers from the
4389 // parameter save area.
4390 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4391 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4392 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4393 if (GPR_idx != NumGPRs) {
4394 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4395 MachinePointerInfo(),
4396 false, false, false, 0);
4397 MemOpChains.push_back(Load.getValue(1));
4398 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4399 ArgOffset += PtrByteSize;
4401 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4408 switch (Arg.getSimpleValueType().SimpleTy) {
4409 default: llvm_unreachable("Unexpected ValueType for argument!");
4413 if (GPR_idx != NumGPRs) {
4414 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4416 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4417 isPPC64, isTailCall, false, MemOpChains,
4418 TailCallArguments, dl);
4420 ArgOffset += PtrByteSize;
4424 if (FPR_idx != NumFPRs) {
4425 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4428 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4429 MachinePointerInfo(), false, false, 0);
4430 MemOpChains.push_back(Store);
4432 // Float varargs are always shadowed in available integer registers
4433 if (GPR_idx != NumGPRs) {
4434 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4435 MachinePointerInfo(), false, false,
4437 MemOpChains.push_back(Load.getValue(1));
4438 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4440 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4441 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4442 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4443 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4444 MachinePointerInfo(),
4445 false, false, false, 0);
4446 MemOpChains.push_back(Load.getValue(1));
4447 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4450 // If we have any FPRs remaining, we may also have GPRs remaining.
4451 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4453 if (GPR_idx != NumGPRs)
4455 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4456 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4460 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4461 isPPC64, isTailCall, false, MemOpChains,
4462 TailCallArguments, dl);
4466 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4473 // These go aligned on the stack, or in the corresponding R registers
4474 // when within range. The Darwin PPC ABI doc claims they also go in
4475 // V registers; in fact gcc does this only for arguments that are
4476 // prototyped, not for those that match the ... We do it for all
4477 // arguments, seems to work.
4478 while (ArgOffset % 16 !=0) {
4479 ArgOffset += PtrByteSize;
4480 if (GPR_idx != NumGPRs)
4483 // We could elide this store in the case where the object fits
4484 // entirely in R registers. Maybe later.
4485 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4486 DAG.getConstant(ArgOffset, PtrVT));
4487 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4488 MachinePointerInfo(), false, false, 0);
4489 MemOpChains.push_back(Store);
4490 if (VR_idx != NumVRs) {
4491 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4492 MachinePointerInfo(),
4493 false, false, false, 0);
4494 MemOpChains.push_back(Load.getValue(1));
4495 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4498 for (unsigned i=0; i<16; i+=PtrByteSize) {
4499 if (GPR_idx == NumGPRs)
4501 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4502 DAG.getConstant(i, PtrVT));
4503 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4504 false, false, false, 0);
4505 MemOpChains.push_back(Load.getValue(1));
4506 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4511 // Non-varargs Altivec params generally go in registers, but have
4512 // stack space allocated at the end.
4513 if (VR_idx != NumVRs) {
4514 // Doesn't have GPR space allocated.
4515 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4516 } else if (nAltivecParamsAtEnd==0) {
4517 // We are emitting Altivec params in order.
4518 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4519 isPPC64, isTailCall, true, MemOpChains,
4520 TailCallArguments, dl);
4526 // If all Altivec parameters fit in registers, as they usually do,
4527 // they get stack space following the non-Altivec parameters. We
4528 // don't track this here because nobody below needs it.
4529 // If there are more Altivec parameters than fit in registers emit
4531 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4533 // Offset is aligned; skip 1st 12 params which go in V registers.
4534 ArgOffset = ((ArgOffset+15)/16)*16;
4536 for (unsigned i = 0; i != NumOps; ++i) {
4537 SDValue Arg = OutVals[i];
4538 EVT ArgType = Outs[i].VT;
4539 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4540 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4543 // We are emitting Altivec params in order.
4544 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4545 isPPC64, isTailCall, true, MemOpChains,
4546 TailCallArguments, dl);
4553 if (!MemOpChains.empty())
4554 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4555 &MemOpChains[0], MemOpChains.size());
4557 // On Darwin, R12 must contain the address of an indirect callee. This does
4558 // not mean the MTCTR instruction must use R12; it's easier to model this as
4559 // an extra parameter, so do that.
4561 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4562 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4563 !isBLACompatibleAddress(Callee, DAG))
4564 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4565 PPC::R12), Callee));
4567 // Build a sequence of copy-to-reg nodes chained together with token chain
4568 // and flag operands which copy the outgoing args into the appropriate regs.
4570 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4571 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4572 RegsToPass[i].second, InFlag);
4573 InFlag = Chain.getValue(1);
4577 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4578 FPOp, true, TailCallArguments);
4580 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4581 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4586 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4587 MachineFunction &MF, bool isVarArg,
4588 const SmallVectorImpl<ISD::OutputArg> &Outs,
4589 LLVMContext &Context) const {
4590 SmallVector<CCValAssign, 16> RVLocs;
4591 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4593 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4597 PPCTargetLowering::LowerReturn(SDValue Chain,
4598 CallingConv::ID CallConv, bool isVarArg,
4599 const SmallVectorImpl<ISD::OutputArg> &Outs,
4600 const SmallVectorImpl<SDValue> &OutVals,
4601 SDLoc dl, SelectionDAG &DAG) const {
4603 SmallVector<CCValAssign, 16> RVLocs;
4604 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4605 getTargetMachine(), RVLocs, *DAG.getContext());
4606 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4609 SmallVector<SDValue, 4> RetOps(1, Chain);
4611 // Copy the result values into the output registers.
4612 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4613 CCValAssign &VA = RVLocs[i];
4614 assert(VA.isRegLoc() && "Can only return in registers!");
4616 SDValue Arg = OutVals[i];
4618 switch (VA.getLocInfo()) {
4619 default: llvm_unreachable("Unknown loc info!");
4620 case CCValAssign::Full: break;
4621 case CCValAssign::AExt:
4622 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4624 case CCValAssign::ZExt:
4625 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4627 case CCValAssign::SExt:
4628 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4632 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4633 Flag = Chain.getValue(1);
4634 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4637 RetOps[0] = Chain; // Update chain.
4639 // Add the flag if we have it.
4641 RetOps.push_back(Flag);
4643 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4644 &RetOps[0], RetOps.size());
4647 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4648 const PPCSubtarget &Subtarget) const {
4649 // When we pop the dynamic allocation we need to restore the SP link.
4652 // Get the corect type for pointers.
4653 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4655 // Construct the stack pointer operand.
4656 bool isPPC64 = Subtarget.isPPC64();
4657 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4658 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4660 // Get the operands for the STACKRESTORE.
4661 SDValue Chain = Op.getOperand(0);
4662 SDValue SaveSP = Op.getOperand(1);
4664 // Load the old link SP.
4665 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4666 MachinePointerInfo(),
4667 false, false, false, 0);
4669 // Restore the stack pointer.
4670 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4672 // Store the old link SP.
4673 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4680 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4681 MachineFunction &MF = DAG.getMachineFunction();
4682 bool isPPC64 = PPCSubTarget.isPPC64();
4683 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4684 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4686 // Get current frame pointer save index. The users of this index will be
4687 // primarily DYNALLOC instructions.
4688 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4689 int RASI = FI->getReturnAddrSaveIndex();
4691 // If the frame pointer save index hasn't been defined yet.
4693 // Find out what the fix offset of the frame pointer save area.
4694 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4695 // Allocate the frame index for frame pointer save area.
4696 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4698 FI->setReturnAddrSaveIndex(RASI);
4700 return DAG.getFrameIndex(RASI, PtrVT);
4704 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4705 MachineFunction &MF = DAG.getMachineFunction();
4706 bool isPPC64 = PPCSubTarget.isPPC64();
4707 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4708 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4710 // Get current frame pointer save index. The users of this index will be
4711 // primarily DYNALLOC instructions.
4712 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4713 int FPSI = FI->getFramePointerSaveIndex();
4715 // If the frame pointer save index hasn't been defined yet.
4717 // Find out what the fix offset of the frame pointer save area.
4718 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4721 // Allocate the frame index for frame pointer save area.
4722 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4724 FI->setFramePointerSaveIndex(FPSI);
4726 return DAG.getFrameIndex(FPSI, PtrVT);
4729 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4731 const PPCSubtarget &Subtarget) const {
4733 SDValue Chain = Op.getOperand(0);
4734 SDValue Size = Op.getOperand(1);
4737 // Get the corect type for pointers.
4738 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4740 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4741 DAG.getConstant(0, PtrVT), Size);
4742 // Construct a node for the frame pointer save index.
4743 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4744 // Build a DYNALLOC node.
4745 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4746 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4747 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4750 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4751 SelectionDAG &DAG) const {
4753 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4754 DAG.getVTList(MVT::i32, MVT::Other),
4755 Op.getOperand(0), Op.getOperand(1));
4758 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4759 SelectionDAG &DAG) const {
4761 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4762 Op.getOperand(0), Op.getOperand(1));
4765 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4766 assert(Op.getValueType() == MVT::i1 &&
4767 "Custom lowering only for i1 loads");
4769 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4772 LoadSDNode *LD = cast<LoadSDNode>(Op);
4774 SDValue Chain = LD->getChain();
4775 SDValue BasePtr = LD->getBasePtr();
4776 MachineMemOperand *MMO = LD->getMemOperand();
4778 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4779 BasePtr, MVT::i8, MMO);
4780 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4782 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4783 return DAG.getMergeValues(Ops, 2, dl);
4786 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4787 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4788 "Custom lowering only for i1 stores");
4790 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4793 StoreSDNode *ST = cast<StoreSDNode>(Op);
4795 SDValue Chain = ST->getChain();
4796 SDValue BasePtr = ST->getBasePtr();
4797 SDValue Value = ST->getValue();
4798 MachineMemOperand *MMO = ST->getMemOperand();
4800 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4801 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4804 // FIXME: Remove this once the ANDI glue bug is fixed:
4805 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4806 assert(Op.getValueType() == MVT::i1 &&
4807 "Custom lowering only for i1 results");
4810 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
4814 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4816 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4817 // Not FP? Not a fsel.
4818 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4819 !Op.getOperand(2).getValueType().isFloatingPoint())
4822 // We might be able to do better than this under some circumstances, but in
4823 // general, fsel-based lowering of select is a finite-math-only optimization.
4824 // For more information, see section F.3 of the 2.06 ISA specification.
4825 if (!DAG.getTarget().Options.NoInfsFPMath ||
4826 !DAG.getTarget().Options.NoNaNsFPMath)
4829 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4831 EVT ResVT = Op.getValueType();
4832 EVT CmpVT = Op.getOperand(0).getValueType();
4833 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4834 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4837 // If the RHS of the comparison is a 0.0, we don't need to do the
4838 // subtraction at all.
4840 if (isFloatingPointZero(RHS))
4842 default: break; // SETUO etc aren't handled by fsel.
4846 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4847 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4848 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4849 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4850 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4851 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4852 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4855 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4858 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4859 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4860 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4863 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4866 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4867 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4868 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4869 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4874 default: break; // SETUO etc aren't handled by fsel.
4878 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4879 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4880 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4881 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4882 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4883 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4884 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4885 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4888 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4889 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4890 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4891 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4894 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4895 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4896 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4897 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4900 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4901 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4902 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4903 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4906 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4907 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4908 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4909 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4914 // FIXME: Split this code up when LegalizeDAGTypes lands.
4915 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4917 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4918 SDValue Src = Op.getOperand(0);
4919 if (Src.getValueType() == MVT::f32)
4920 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4923 switch (Op.getSimpleValueType().SimpleTy) {
4924 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4926 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4927 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4932 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4933 "i64 FP_TO_UINT is supported only with FPCVT");
4934 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4940 // Convert the FP value to an int value through memory.
4941 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4942 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4943 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4944 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4945 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4947 // Emit a store to the stack slot.
4950 MachineFunction &MF = DAG.getMachineFunction();
4951 MachineMemOperand *MMO =
4952 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4953 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4954 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4955 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4958 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4959 MPI, false, false, 0);
4961 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4963 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4964 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4965 DAG.getConstant(4, FIPtr.getValueType()));
4966 MPI = MachinePointerInfo();
4969 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4970 false, false, false, 0);
4973 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4974 SelectionDAG &DAG) const {
4976 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4977 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4980 if (Op.getOperand(0).getValueType() == MVT::i1)
4981 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
4982 DAG.getConstantFP(1.0, Op.getValueType()),
4983 DAG.getConstantFP(0.0, Op.getValueType()));
4985 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4986 "UINT_TO_FP is supported only with FPCVT");
4988 // If we have FCFIDS, then use it when converting to single-precision.
4989 // Otherwise, convert to double-precision and then round.
4990 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4991 (Op.getOpcode() == ISD::UINT_TO_FP ?
4992 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4993 (Op.getOpcode() == ISD::UINT_TO_FP ?
4994 PPCISD::FCFIDU : PPCISD::FCFID);
4995 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4996 MVT::f32 : MVT::f64;
4998 if (Op.getOperand(0).getValueType() == MVT::i64) {
4999 SDValue SINT = Op.getOperand(0);
5000 // When converting to single-precision, we actually need to convert
5001 // to double-precision first and then round to single-precision.
5002 // To avoid double-rounding effects during that operation, we have
5003 // to prepare the input operand. Bits that might be truncated when
5004 // converting to double-precision are replaced by a bit that won't
5005 // be lost at this stage, but is below the single-precision rounding
5008 // However, if -enable-unsafe-fp-math is in effect, accept double
5009 // rounding to avoid the extra overhead.
5010 if (Op.getValueType() == MVT::f32 &&
5011 !PPCSubTarget.hasFPCVT() &&
5012 !DAG.getTarget().Options.UnsafeFPMath) {
5014 // Twiddle input to make sure the low 11 bits are zero. (If this
5015 // is the case, we are guaranteed the value will fit into the 53 bit
5016 // mantissa of an IEEE double-precision value without rounding.)
5017 // If any of those low 11 bits were not zero originally, make sure
5018 // bit 12 (value 2048) is set instead, so that the final rounding
5019 // to single-precision gets the correct result.
5020 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5021 SINT, DAG.getConstant(2047, MVT::i64));
5022 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5023 Round, DAG.getConstant(2047, MVT::i64));
5024 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5025 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5026 Round, DAG.getConstant(-2048, MVT::i64));
5028 // However, we cannot use that value unconditionally: if the magnitude
5029 // of the input value is small, the bit-twiddling we did above might
5030 // end up visibly changing the output. Fortunately, in that case, we
5031 // don't need to twiddle bits since the original input will convert
5032 // exactly to double-precision floating-point already. Therefore,
5033 // construct a conditional to use the original value if the top 11
5034 // bits are all sign-bit copies, and use the rounded value computed
5036 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5037 SINT, DAG.getConstant(53, MVT::i32));
5038 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5039 Cond, DAG.getConstant(1, MVT::i64));
5040 Cond = DAG.getSetCC(dl, MVT::i32,
5041 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5043 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5046 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5047 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5049 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
5050 FP = DAG.getNode(ISD::FP_ROUND, dl,
5051 MVT::f32, FP, DAG.getIntPtrConstant(0));
5055 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5056 "Unhandled INT_TO_FP type in custom expander!");
5057 // Since we only generate this in 64-bit mode, we can take advantage of
5058 // 64-bit registers. In particular, sign extend the input value into the
5059 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5060 // then lfd it and fcfid it.
5061 MachineFunction &MF = DAG.getMachineFunction();
5062 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5063 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5066 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
5067 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5068 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5070 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5071 MachinePointerInfo::getFixedStack(FrameIdx),
5074 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5075 "Expected an i32 store");
5076 MachineMemOperand *MMO =
5077 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5078 MachineMemOperand::MOLoad, 4, 4);
5079 SDValue Ops[] = { Store, FIdx };
5080 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5081 PPCISD::LFIWZX : PPCISD::LFIWAX,
5082 dl, DAG.getVTList(MVT::f64, MVT::Other),
5083 Ops, 2, MVT::i32, MMO);
5085 assert(PPCSubTarget.isPPC64() &&
5086 "i32->FP without LFIWAX supported only on PPC64");
5088 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5089 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5091 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5094 // STD the extended value into the stack slot.
5095 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5096 MachinePointerInfo::getFixedStack(FrameIdx),
5099 // Load the value as a double.
5100 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5101 MachinePointerInfo::getFixedStack(FrameIdx),
5102 false, false, false, 0);
5105 // FCFID it and return it.
5106 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5107 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
5108 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5112 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5113 SelectionDAG &DAG) const {
5116 The rounding mode is in bits 30:31 of FPSR, and has the following
5123 FLT_ROUNDS, on the other hand, expects the following:
5130 To perform the conversion, we do:
5131 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5134 MachineFunction &MF = DAG.getMachineFunction();
5135 EVT VT = Op.getValueType();
5136 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5137 SDValue MFFSreg, InFlag;
5139 // Save FP Control Word to register
5141 MVT::f64, // return register
5142 MVT::Glue // unused in this context
5144 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
5146 // Save FP register to stack slot
5147 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5148 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5149 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5150 StackSlot, MachinePointerInfo(), false, false,0);
5152 // Load FP Control Word from low 32 bits of stack slot.
5153 SDValue Four = DAG.getConstant(4, PtrVT);
5154 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5155 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5156 false, false, false, 0);
5158 // Transform as necessary
5160 DAG.getNode(ISD::AND, dl, MVT::i32,
5161 CWD, DAG.getConstant(3, MVT::i32));
5163 DAG.getNode(ISD::SRL, dl, MVT::i32,
5164 DAG.getNode(ISD::AND, dl, MVT::i32,
5165 DAG.getNode(ISD::XOR, dl, MVT::i32,
5166 CWD, DAG.getConstant(3, MVT::i32)),
5167 DAG.getConstant(3, MVT::i32)),
5168 DAG.getConstant(1, MVT::i32));
5171 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5173 return DAG.getNode((VT.getSizeInBits() < 16 ?
5174 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5177 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5178 EVT VT = Op.getValueType();
5179 unsigned BitWidth = VT.getSizeInBits();
5181 assert(Op.getNumOperands() == 3 &&
5182 VT == Op.getOperand(1).getValueType() &&
5185 // Expand into a bunch of logical ops. Note that these ops
5186 // depend on the PPC behavior for oversized shift amounts.
5187 SDValue Lo = Op.getOperand(0);
5188 SDValue Hi = Op.getOperand(1);
5189 SDValue Amt = Op.getOperand(2);
5190 EVT AmtVT = Amt.getValueType();
5192 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5193 DAG.getConstant(BitWidth, AmtVT), Amt);
5194 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5195 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5196 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5197 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5198 DAG.getConstant(-BitWidth, AmtVT));
5199 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5200 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5201 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5202 SDValue OutOps[] = { OutLo, OutHi };
5203 return DAG.getMergeValues(OutOps, 2, dl);
5206 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5207 EVT VT = Op.getValueType();
5209 unsigned BitWidth = VT.getSizeInBits();
5210 assert(Op.getNumOperands() == 3 &&
5211 VT == Op.getOperand(1).getValueType() &&
5214 // Expand into a bunch of logical ops. Note that these ops
5215 // depend on the PPC behavior for oversized shift amounts.
5216 SDValue Lo = Op.getOperand(0);
5217 SDValue Hi = Op.getOperand(1);
5218 SDValue Amt = Op.getOperand(2);
5219 EVT AmtVT = Amt.getValueType();
5221 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5222 DAG.getConstant(BitWidth, AmtVT), Amt);
5223 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5224 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5225 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5226 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5227 DAG.getConstant(-BitWidth, AmtVT));
5228 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5229 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5230 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5231 SDValue OutOps[] = { OutLo, OutHi };
5232 return DAG.getMergeValues(OutOps, 2, dl);
5235 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5237 EVT VT = Op.getValueType();
5238 unsigned BitWidth = VT.getSizeInBits();
5239 assert(Op.getNumOperands() == 3 &&
5240 VT == Op.getOperand(1).getValueType() &&
5243 // Expand into a bunch of logical ops, followed by a select_cc.
5244 SDValue Lo = Op.getOperand(0);
5245 SDValue Hi = Op.getOperand(1);
5246 SDValue Amt = Op.getOperand(2);
5247 EVT AmtVT = Amt.getValueType();
5249 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5250 DAG.getConstant(BitWidth, AmtVT), Amt);
5251 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5252 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5253 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5254 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5255 DAG.getConstant(-BitWidth, AmtVT));
5256 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5257 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5258 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5259 Tmp4, Tmp6, ISD::SETLE);
5260 SDValue OutOps[] = { OutLo, OutHi };
5261 return DAG.getMergeValues(OutOps, 2, dl);
5264 //===----------------------------------------------------------------------===//
5265 // Vector related lowering.
5268 /// BuildSplatI - Build a canonical splati of Val with an element size of
5269 /// SplatSize. Cast the result to VT.
5270 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5271 SelectionDAG &DAG, SDLoc dl) {
5272 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5274 static const EVT VTys[] = { // canonical VT to use for each size.
5275 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5278 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5280 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5284 EVT CanonicalVT = VTys[SplatSize-1];
5286 // Build a canonical splat for this value.
5287 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5288 SmallVector<SDValue, 8> Ops;
5289 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5290 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5291 &Ops[0], Ops.size());
5292 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5295 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5296 /// specified intrinsic ID.
5297 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5298 SelectionDAG &DAG, SDLoc dl,
5299 EVT DestVT = MVT::Other) {
5300 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5301 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5302 DAG.getConstant(IID, MVT::i32), Op);
5305 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5306 /// specified intrinsic ID.
5307 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5308 SelectionDAG &DAG, SDLoc dl,
5309 EVT DestVT = MVT::Other) {
5310 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5311 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5312 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5315 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5316 /// specified intrinsic ID.
5317 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5318 SDValue Op2, SelectionDAG &DAG,
5319 SDLoc dl, EVT DestVT = MVT::Other) {
5320 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5321 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5322 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5326 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5327 /// amount. The result has the specified value type.
5328 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5329 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5330 // Force LHS/RHS to be the right type.
5331 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5332 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5335 for (unsigned i = 0; i != 16; ++i)
5337 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5338 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5341 // If this is a case we can't handle, return null and let the default
5342 // expansion code take care of it. If we CAN select this case, and if it
5343 // selects to a single instruction, return Op. Otherwise, if we can codegen
5344 // this case more efficiently than a constant pool load, lower it to the
5345 // sequence of ops that should be used.
5346 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5347 SelectionDAG &DAG) const {
5349 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5350 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5352 // Check if this is a splat of a constant value.
5353 APInt APSplatBits, APSplatUndef;
5354 unsigned SplatBitSize;
5356 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5357 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5360 unsigned SplatBits = APSplatBits.getZExtValue();
5361 unsigned SplatUndef = APSplatUndef.getZExtValue();
5362 unsigned SplatSize = SplatBitSize / 8;
5364 // First, handle single instruction cases.
5367 if (SplatBits == 0) {
5368 // Canonicalize all zero vectors to be v4i32.
5369 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5370 SDValue Z = DAG.getConstant(0, MVT::i32);
5371 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5372 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5377 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5378 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5380 if (SextVal >= -16 && SextVal <= 15)
5381 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5384 // Two instruction sequences.
5386 // If this value is in the range [-32,30] and is even, use:
5387 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5388 // If this value is in the range [17,31] and is odd, use:
5389 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5390 // If this value is in the range [-31,-17] and is odd, use:
5391 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5392 // Note the last two are three-instruction sequences.
5393 if (SextVal >= -32 && SextVal <= 31) {
5394 // To avoid having these optimizations undone by constant folding,
5395 // we convert to a pseudo that will be expanded later into one of
5397 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5398 EVT VT = Op.getValueType();
5399 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5400 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5401 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5404 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5405 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5407 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5408 // Make -1 and vspltisw -1:
5409 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5411 // Make the VSLW intrinsic, computing 0x8000_0000.
5412 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5415 // xor by OnesV to invert it.
5416 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5417 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5420 // Check to see if this is a wide variety of vsplti*, binop self cases.
5421 static const signed char SplatCsts[] = {
5422 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5423 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5426 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5427 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5428 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5429 int i = SplatCsts[idx];
5431 // Figure out what shift amount will be used by altivec if shifted by i in
5433 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5435 // vsplti + shl self.
5436 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5437 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5438 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5439 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5440 Intrinsic::ppc_altivec_vslw
5442 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5443 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5446 // vsplti + srl self.
5447 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5448 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5449 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5450 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5451 Intrinsic::ppc_altivec_vsrw
5453 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5454 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5457 // vsplti + sra self.
5458 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5459 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5460 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5461 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5462 Intrinsic::ppc_altivec_vsraw
5464 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5465 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5468 // vsplti + rol self.
5469 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5470 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5471 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5472 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5473 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5474 Intrinsic::ppc_altivec_vrlw
5476 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5477 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5480 // t = vsplti c, result = vsldoi t, t, 1
5481 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5482 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5483 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5485 // t = vsplti c, result = vsldoi t, t, 2
5486 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5487 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5488 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5490 // t = vsplti c, result = vsldoi t, t, 3
5491 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5492 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5493 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5500 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5501 /// the specified operations to build the shuffle.
5502 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5503 SDValue RHS, SelectionDAG &DAG,
5505 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5506 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5507 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5510 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5522 if (OpNum == OP_COPY) {
5523 if (LHSID == (1*9+2)*9+3) return LHS;
5524 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5528 SDValue OpLHS, OpRHS;
5529 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5530 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5534 default: llvm_unreachable("Unknown i32 permute!");
5536 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5537 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5538 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5539 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5542 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5543 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5544 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5545 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5548 for (unsigned i = 0; i != 16; ++i)
5549 ShufIdxs[i] = (i&3)+0;
5552 for (unsigned i = 0; i != 16; ++i)
5553 ShufIdxs[i] = (i&3)+4;
5556 for (unsigned i = 0; i != 16; ++i)
5557 ShufIdxs[i] = (i&3)+8;
5560 for (unsigned i = 0; i != 16; ++i)
5561 ShufIdxs[i] = (i&3)+12;
5564 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5566 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5568 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5570 EVT VT = OpLHS.getValueType();
5571 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5572 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5573 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5574 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5577 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5578 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5579 /// return the code it can be lowered into. Worst case, it can always be
5580 /// lowered into a vperm.
5581 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5582 SelectionDAG &DAG) const {
5584 SDValue V1 = Op.getOperand(0);
5585 SDValue V2 = Op.getOperand(1);
5586 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5587 EVT VT = Op.getValueType();
5589 // Cases that are handled by instructions that take permute immediates
5590 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5591 // selected by the instruction selector.
5592 if (V2.getOpcode() == ISD::UNDEF) {
5593 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5594 PPC::isSplatShuffleMask(SVOp, 2) ||
5595 PPC::isSplatShuffleMask(SVOp, 4) ||
5596 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5597 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5598 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5599 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5600 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5601 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5602 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5603 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5604 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5609 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5610 // and produce a fixed permutation. If any of these match, do not lower to
5612 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5613 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5614 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5615 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5616 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5617 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5618 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5619 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5620 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5623 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5624 // perfect shuffle table to emit an optimal matching sequence.
5625 ArrayRef<int> PermMask = SVOp->getMask();
5627 unsigned PFIndexes[4];
5628 bool isFourElementShuffle = true;
5629 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5630 unsigned EltNo = 8; // Start out undef.
5631 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5632 if (PermMask[i*4+j] < 0)
5633 continue; // Undef, ignore it.
5635 unsigned ByteSource = PermMask[i*4+j];
5636 if ((ByteSource & 3) != j) {
5637 isFourElementShuffle = false;
5642 EltNo = ByteSource/4;
5643 } else if (EltNo != ByteSource/4) {
5644 isFourElementShuffle = false;
5648 PFIndexes[i] = EltNo;
5651 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5652 // perfect shuffle vector to determine if it is cost effective to do this as
5653 // discrete instructions, or whether we should use a vperm.
5654 if (isFourElementShuffle) {
5655 // Compute the index in the perfect shuffle table.
5656 unsigned PFTableIndex =
5657 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5659 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5660 unsigned Cost = (PFEntry >> 30);
5662 // Determining when to avoid vperm is tricky. Many things affect the cost
5663 // of vperm, particularly how many times the perm mask needs to be computed.
5664 // For example, if the perm mask can be hoisted out of a loop or is already
5665 // used (perhaps because there are multiple permutes with the same shuffle
5666 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5667 // the loop requires an extra register.
5669 // As a compromise, we only emit discrete instructions if the shuffle can be
5670 // generated in 3 or fewer operations. When we have loop information
5671 // available, if this block is within a loop, we should avoid using vperm
5672 // for 3-operation perms and use a constant pool load instead.
5674 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5677 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5678 // vector that will get spilled to the constant pool.
5679 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5681 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5682 // that it is in input element units, not in bytes. Convert now.
5683 EVT EltVT = V1.getValueType().getVectorElementType();
5684 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5686 SmallVector<SDValue, 16> ResultMask;
5687 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5688 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5690 for (unsigned j = 0; j != BytesPerElement; ++j)
5691 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5695 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5696 &ResultMask[0], ResultMask.size());
5697 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5700 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5701 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5702 /// information about the intrinsic.
5703 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5705 unsigned IntrinsicID =
5706 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5709 switch (IntrinsicID) {
5710 default: return false;
5711 // Comparison predicates.
5712 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5713 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5714 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5715 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5716 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5717 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5718 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5719 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5720 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5721 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5722 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5723 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5724 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5726 // Normal Comparisons.
5727 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5728 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5729 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5730 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5731 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5732 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5733 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5734 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5735 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5736 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5737 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5738 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5739 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5744 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5745 /// lower, do it, otherwise return null.
5746 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5747 SelectionDAG &DAG) const {
5748 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5749 // opcode number of the comparison.
5753 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5754 return SDValue(); // Don't custom lower most intrinsics.
5756 // If this is a non-dot comparison, make the VCMP node and we are done.
5758 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5759 Op.getOperand(1), Op.getOperand(2),
5760 DAG.getConstant(CompareOpc, MVT::i32));
5761 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5764 // Create the PPCISD altivec 'dot' comparison node.
5766 Op.getOperand(2), // LHS
5767 Op.getOperand(3), // RHS
5768 DAG.getConstant(CompareOpc, MVT::i32)
5770 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5771 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5773 // Now that we have the comparison, emit a copy from the CR to a GPR.
5774 // This is flagged to the above dot comparison.
5775 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5776 DAG.getRegister(PPC::CR6, MVT::i32),
5777 CompNode.getValue(1));
5779 // Unpack the result based on how the target uses it.
5780 unsigned BitNo; // Bit # of CR6.
5781 bool InvertBit; // Invert result?
5782 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5783 default: // Can't happen, don't crash on invalid number though.
5784 case 0: // Return the value of the EQ bit of CR6.
5785 BitNo = 0; InvertBit = false;
5787 case 1: // Return the inverted value of the EQ bit of CR6.
5788 BitNo = 0; InvertBit = true;
5790 case 2: // Return the value of the LT bit of CR6.
5791 BitNo = 2; InvertBit = false;
5793 case 3: // Return the inverted value of the LT bit of CR6.
5794 BitNo = 2; InvertBit = true;
5798 // Shift the bit into the low position.
5799 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5800 DAG.getConstant(8-(3-BitNo), MVT::i32));
5802 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5803 DAG.getConstant(1, MVT::i32));
5805 // If we are supposed to, toggle the bit.
5807 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5808 DAG.getConstant(1, MVT::i32));
5812 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5813 SelectionDAG &DAG) const {
5815 // Create a stack slot that is 16-byte aligned.
5816 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5817 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5818 EVT PtrVT = getPointerTy();
5819 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5821 // Store the input value into Value#0 of the stack slot.
5822 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5823 Op.getOperand(0), FIdx, MachinePointerInfo(),
5826 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5827 false, false, false, 0);
5830 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5832 if (Op.getValueType() == MVT::v4i32) {
5833 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5835 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5836 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5838 SDValue RHSSwap = // = vrlw RHS, 16
5839 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5841 // Shrinkify inputs to v8i16.
5842 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5843 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5844 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5846 // Low parts multiplied together, generating 32-bit results (we ignore the
5848 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5849 LHS, RHS, DAG, dl, MVT::v4i32);
5851 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5852 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5853 // Shift the high parts up 16 bits.
5854 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5856 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5857 } else if (Op.getValueType() == MVT::v8i16) {
5858 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5860 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5862 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5863 LHS, RHS, Zero, DAG, dl);
5864 } else if (Op.getValueType() == MVT::v16i8) {
5865 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5867 // Multiply the even 8-bit parts, producing 16-bit sums.
5868 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5869 LHS, RHS, DAG, dl, MVT::v8i16);
5870 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5872 // Multiply the odd 8-bit parts, producing 16-bit sums.
5873 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5874 LHS, RHS, DAG, dl, MVT::v8i16);
5875 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5877 // Merge the results together.
5879 for (unsigned i = 0; i != 8; ++i) {
5881 Ops[i*2+1] = 2*i+1+16;
5883 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5885 llvm_unreachable("Unknown mul to lower!");
5889 /// LowerOperation - Provide custom lowering hooks for some operations.
5891 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5892 switch (Op.getOpcode()) {
5893 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5894 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5895 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5896 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5897 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5898 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5899 case ISD::SETCC: return LowerSETCC(Op, DAG);
5900 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5901 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5903 return LowerVASTART(Op, DAG, PPCSubTarget);
5906 return LowerVAARG(Op, DAG, PPCSubTarget);
5909 return LowerVACOPY(Op, DAG, PPCSubTarget);
5911 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5912 case ISD::DYNAMIC_STACKALLOC:
5913 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5915 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5916 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5918 case ISD::LOAD: return LowerLOAD(Op, DAG);
5919 case ISD::STORE: return LowerSTORE(Op, DAG);
5920 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
5921 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5922 case ISD::FP_TO_UINT:
5923 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5925 case ISD::UINT_TO_FP:
5926 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5927 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5929 // Lower 64-bit shifts.
5930 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5931 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5932 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5934 // Vector-related lowering.
5935 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5936 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5937 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5938 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5939 case ISD::MUL: return LowerMUL(Op, DAG);
5941 // For counter-based loop handling.
5942 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5944 // Frame & Return address.
5945 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5946 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5950 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5951 SmallVectorImpl<SDValue>&Results,
5952 SelectionDAG &DAG) const {
5953 const TargetMachine &TM = getTargetMachine();
5955 switch (N->getOpcode()) {
5957 llvm_unreachable("Do not know how to custom type legalize this operation!");
5958 case ISD::INTRINSIC_W_CHAIN: {
5959 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
5960 Intrinsic::ppc_is_decremented_ctr_nonzero)
5963 assert(N->getValueType(0) == MVT::i1 &&
5964 "Unexpected result type for CTR decrement intrinsic");
5965 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
5966 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5967 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
5970 Results.push_back(NewInt);
5971 Results.push_back(NewInt.getValue(1));
5975 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5976 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5979 EVT VT = N->getValueType(0);
5981 if (VT == MVT::i64) {
5982 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5984 Results.push_back(NewNode);
5985 Results.push_back(NewNode.getValue(1));
5989 case ISD::FP_ROUND_INREG: {
5990 assert(N->getValueType(0) == MVT::ppcf128);
5991 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5992 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5993 MVT::f64, N->getOperand(0),
5994 DAG.getIntPtrConstant(0));
5995 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5996 MVT::f64, N->getOperand(0),
5997 DAG.getIntPtrConstant(1));
5999 // Add the two halves of the long double in round-to-zero mode.
6000 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6002 // We know the low half is about to be thrown away, so just use something
6004 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6008 case ISD::FP_TO_SINT:
6009 // LowerFP_TO_INT() can only handle f32 and f64.
6010 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6012 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6018 //===----------------------------------------------------------------------===//
6019 // Other Lowering Code
6020 //===----------------------------------------------------------------------===//
6023 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6024 bool is64bit, unsigned BinOpcode) const {
6025 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6026 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6028 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6029 MachineFunction *F = BB->getParent();
6030 MachineFunction::iterator It = BB;
6033 unsigned dest = MI->getOperand(0).getReg();
6034 unsigned ptrA = MI->getOperand(1).getReg();
6035 unsigned ptrB = MI->getOperand(2).getReg();
6036 unsigned incr = MI->getOperand(3).getReg();
6037 DebugLoc dl = MI->getDebugLoc();
6039 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6040 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6041 F->insert(It, loopMBB);
6042 F->insert(It, exitMBB);
6043 exitMBB->splice(exitMBB->begin(), BB,
6044 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6045 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6047 MachineRegisterInfo &RegInfo = F->getRegInfo();
6048 unsigned TmpReg = (!BinOpcode) ? incr :
6049 RegInfo.createVirtualRegister(
6050 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6051 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6055 // fallthrough --> loopMBB
6056 BB->addSuccessor(loopMBB);
6059 // l[wd]arx dest, ptr
6060 // add r0, dest, incr
6061 // st[wd]cx. r0, ptr
6063 // fallthrough --> exitMBB
6065 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6066 .addReg(ptrA).addReg(ptrB);
6068 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6069 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6070 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6071 BuildMI(BB, dl, TII->get(PPC::BCC))
6072 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6073 BB->addSuccessor(loopMBB);
6074 BB->addSuccessor(exitMBB);
6083 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6084 MachineBasicBlock *BB,
6085 bool is8bit, // operation
6086 unsigned BinOpcode) const {
6087 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6088 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6089 // In 64 bit mode we have to use 64 bits for addresses, even though the
6090 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6091 // registers without caring whether they're 32 or 64, but here we're
6092 // doing actual arithmetic on the addresses.
6093 bool is64bit = PPCSubTarget.isPPC64();
6094 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6096 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6097 MachineFunction *F = BB->getParent();
6098 MachineFunction::iterator It = BB;
6101 unsigned dest = MI->getOperand(0).getReg();
6102 unsigned ptrA = MI->getOperand(1).getReg();
6103 unsigned ptrB = MI->getOperand(2).getReg();
6104 unsigned incr = MI->getOperand(3).getReg();
6105 DebugLoc dl = MI->getDebugLoc();
6107 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6108 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6109 F->insert(It, loopMBB);
6110 F->insert(It, exitMBB);
6111 exitMBB->splice(exitMBB->begin(), BB,
6112 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6113 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6115 MachineRegisterInfo &RegInfo = F->getRegInfo();
6116 const TargetRegisterClass *RC =
6117 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6118 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6119 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6120 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6121 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6122 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6123 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6124 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6125 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6126 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6127 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6128 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6129 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6131 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6135 // fallthrough --> loopMBB
6136 BB->addSuccessor(loopMBB);
6138 // The 4-byte load must be aligned, while a char or short may be
6139 // anywhere in the word. Hence all this nasty bookkeeping code.
6140 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6141 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6142 // xori shift, shift1, 24 [16]
6143 // rlwinm ptr, ptr1, 0, 0, 29
6144 // slw incr2, incr, shift
6145 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6146 // slw mask, mask2, shift
6148 // lwarx tmpDest, ptr
6149 // add tmp, tmpDest, incr2
6150 // andc tmp2, tmpDest, mask
6151 // and tmp3, tmp, mask
6152 // or tmp4, tmp3, tmp2
6155 // fallthrough --> exitMBB
6156 // srw dest, tmpDest, shift
6157 if (ptrA != ZeroReg) {
6158 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6159 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6160 .addReg(ptrA).addReg(ptrB);
6164 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6165 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6166 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6167 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6169 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6170 .addReg(Ptr1Reg).addImm(0).addImm(61);
6172 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6173 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6174 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6175 .addReg(incr).addReg(ShiftReg);
6177 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6179 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6180 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6182 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6183 .addReg(Mask2Reg).addReg(ShiftReg);
6186 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6187 .addReg(ZeroReg).addReg(PtrReg);
6189 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6190 .addReg(Incr2Reg).addReg(TmpDestReg);
6191 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6192 .addReg(TmpDestReg).addReg(MaskReg);
6193 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6194 .addReg(TmpReg).addReg(MaskReg);
6195 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6196 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6197 BuildMI(BB, dl, TII->get(PPC::STWCX))
6198 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6199 BuildMI(BB, dl, TII->get(PPC::BCC))
6200 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6201 BB->addSuccessor(loopMBB);
6202 BB->addSuccessor(exitMBB);
6207 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6212 llvm::MachineBasicBlock*
6213 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6214 MachineBasicBlock *MBB) const {
6215 DebugLoc DL = MI->getDebugLoc();
6216 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6218 MachineFunction *MF = MBB->getParent();
6219 MachineRegisterInfo &MRI = MF->getRegInfo();
6221 const BasicBlock *BB = MBB->getBasicBlock();
6222 MachineFunction::iterator I = MBB;
6226 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6227 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6229 unsigned DstReg = MI->getOperand(0).getReg();
6230 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6231 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6232 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6233 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6235 MVT PVT = getPointerTy();
6236 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6237 "Invalid Pointer Size!");
6238 // For v = setjmp(buf), we generate
6241 // SjLjSetup mainMBB
6247 // buf[LabelOffset] = LR
6251 // v = phi(main, restore)
6254 MachineBasicBlock *thisMBB = MBB;
6255 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6256 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6257 MF->insert(I, mainMBB);
6258 MF->insert(I, sinkMBB);
6260 MachineInstrBuilder MIB;
6262 // Transfer the remainder of BB and its successor edges to sinkMBB.
6263 sinkMBB->splice(sinkMBB->begin(), MBB,
6264 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6265 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6267 // Note that the structure of the jmp_buf used here is not compatible
6268 // with that used by libc, and is not designed to be. Specifically, it
6269 // stores only those 'reserved' registers that LLVM does not otherwise
6270 // understand how to spill. Also, by convention, by the time this
6271 // intrinsic is called, Clang has already stored the frame address in the
6272 // first slot of the buffer and stack address in the third. Following the
6273 // X86 target code, we'll store the jump address in the second slot. We also
6274 // need to save the TOC pointer (R2) to handle jumps between shared
6275 // libraries, and that will be stored in the fourth slot. The thread
6276 // identifier (R13) is not affected.
6279 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6280 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6281 const int64_t BPOffset = 4 * PVT.getStoreSize();
6283 // Prepare IP either in reg.
6284 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6285 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6286 unsigned BufReg = MI->getOperand(1).getReg();
6288 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6289 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6293 MIB.setMemRefs(MMOBegin, MMOEnd);
6296 // Naked functions never have a base pointer, and so we use r1. For all
6297 // other functions, this decision must be delayed until during PEI.
6299 if (MF->getFunction()->getAttributes().hasAttribute(
6300 AttributeSet::FunctionIndex, Attribute::Naked))
6301 BaseReg = PPCSubTarget.isPPC64() ? PPC::X1 : PPC::R1;
6303 BaseReg = PPCSubTarget.isPPC64() ? PPC::BP8 : PPC::BP;
6305 MIB = BuildMI(*thisMBB, MI, DL,
6306 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6310 MIB.setMemRefs(MMOBegin, MMOEnd);
6313 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6314 const PPCRegisterInfo *TRI =
6315 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6316 MIB.addRegMask(TRI->getNoPreservedMask());
6318 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6320 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6322 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6324 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6325 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6329 MIB = BuildMI(mainMBB, DL,
6330 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6333 if (PPCSubTarget.isPPC64()) {
6334 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6336 .addImm(LabelOffset)
6339 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6341 .addImm(LabelOffset)
6345 MIB.setMemRefs(MMOBegin, MMOEnd);
6347 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6348 mainMBB->addSuccessor(sinkMBB);
6351 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6352 TII->get(PPC::PHI), DstReg)
6353 .addReg(mainDstReg).addMBB(mainMBB)
6354 .addReg(restoreDstReg).addMBB(thisMBB);
6356 MI->eraseFromParent();
6361 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6362 MachineBasicBlock *MBB) const {
6363 DebugLoc DL = MI->getDebugLoc();
6364 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6366 MachineFunction *MF = MBB->getParent();
6367 MachineRegisterInfo &MRI = MF->getRegInfo();
6370 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6371 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6373 MVT PVT = getPointerTy();
6374 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6375 "Invalid Pointer Size!");
6377 const TargetRegisterClass *RC =
6378 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6379 unsigned Tmp = MRI.createVirtualRegister(RC);
6380 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6381 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6382 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6383 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6385 MachineInstrBuilder MIB;
6387 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6388 const int64_t SPOffset = 2 * PVT.getStoreSize();
6389 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6390 const int64_t BPOffset = 4 * PVT.getStoreSize();
6392 unsigned BufReg = MI->getOperand(0).getReg();
6394 // Reload FP (the jumped-to function may not have had a
6395 // frame pointer, and if so, then its r31 will be restored
6397 if (PVT == MVT::i64) {
6398 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6402 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6406 MIB.setMemRefs(MMOBegin, MMOEnd);
6409 if (PVT == MVT::i64) {
6410 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6411 .addImm(LabelOffset)
6414 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6415 .addImm(LabelOffset)
6418 MIB.setMemRefs(MMOBegin, MMOEnd);
6421 if (PVT == MVT::i64) {
6422 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6426 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6430 MIB.setMemRefs(MMOBegin, MMOEnd);
6433 if (PVT == MVT::i64) {
6434 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6438 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6442 MIB.setMemRefs(MMOBegin, MMOEnd);
6445 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6446 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6450 MIB.setMemRefs(MMOBegin, MMOEnd);
6454 BuildMI(*MBB, MI, DL,
6455 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6456 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6458 MI->eraseFromParent();
6463 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6464 MachineBasicBlock *BB) const {
6465 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6466 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6467 return emitEHSjLjSetJmp(MI, BB);
6468 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6469 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6470 return emitEHSjLjLongJmp(MI, BB);
6473 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6475 // To "insert" these instructions we actually have to insert their
6476 // control-flow patterns.
6477 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6478 MachineFunction::iterator It = BB;
6481 MachineFunction *F = BB->getParent();
6483 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6484 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6485 MI->getOpcode() == PPC::SELECT_I4 ||
6486 MI->getOpcode() == PPC::SELECT_I8)) {
6487 SmallVector<MachineOperand, 2> Cond;
6488 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6489 MI->getOpcode() == PPC::SELECT_CC_I8)
6490 Cond.push_back(MI->getOperand(4));
6492 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6493 Cond.push_back(MI->getOperand(1));
6495 DebugLoc dl = MI->getDebugLoc();
6496 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6497 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6498 Cond, MI->getOperand(2).getReg(),
6499 MI->getOperand(3).getReg());
6500 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6501 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6502 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6503 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6504 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6505 MI->getOpcode() == PPC::SELECT_I4 ||
6506 MI->getOpcode() == PPC::SELECT_I8 ||
6507 MI->getOpcode() == PPC::SELECT_F4 ||
6508 MI->getOpcode() == PPC::SELECT_F8 ||
6509 MI->getOpcode() == PPC::SELECT_VRRC) {
6510 // The incoming instruction knows the destination vreg to set, the
6511 // condition code register to branch on, the true/false values to
6512 // select between, and a branch opcode to use.
6517 // cmpTY ccX, r1, r2
6519 // fallthrough --> copy0MBB
6520 MachineBasicBlock *thisMBB = BB;
6521 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6522 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6523 DebugLoc dl = MI->getDebugLoc();
6524 F->insert(It, copy0MBB);
6525 F->insert(It, sinkMBB);
6527 // Transfer the remainder of BB and its successor edges to sinkMBB.
6528 sinkMBB->splice(sinkMBB->begin(), BB,
6529 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6530 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6532 // Next, add the true and fallthrough blocks as its successors.
6533 BB->addSuccessor(copy0MBB);
6534 BB->addSuccessor(sinkMBB);
6536 if (MI->getOpcode() == PPC::SELECT_I4 ||
6537 MI->getOpcode() == PPC::SELECT_I8 ||
6538 MI->getOpcode() == PPC::SELECT_F4 ||
6539 MI->getOpcode() == PPC::SELECT_F8 ||
6540 MI->getOpcode() == PPC::SELECT_VRRC) {
6541 BuildMI(BB, dl, TII->get(PPC::BC))
6542 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6544 unsigned SelectPred = MI->getOperand(4).getImm();
6545 BuildMI(BB, dl, TII->get(PPC::BCC))
6546 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6550 // %FalseValue = ...
6551 // # fallthrough to sinkMBB
6554 // Update machine-CFG edges
6555 BB->addSuccessor(sinkMBB);
6558 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6561 BuildMI(*BB, BB->begin(), dl,
6562 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6563 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6564 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6566 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6567 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6568 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6569 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6570 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6571 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6572 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6573 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6575 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6576 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6577 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6578 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6579 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6580 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6581 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6582 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6584 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6585 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6586 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6587 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6588 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6589 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6590 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6591 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6593 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6594 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6595 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6596 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6597 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6598 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6599 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6600 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6602 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6603 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6604 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6605 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6606 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6607 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6608 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6609 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6611 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6612 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6613 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6614 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6615 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6616 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6617 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6618 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6620 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6621 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6622 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6623 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6624 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6625 BB = EmitAtomicBinary(MI, BB, false, 0);
6626 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6627 BB = EmitAtomicBinary(MI, BB, true, 0);
6629 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6630 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6631 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6633 unsigned dest = MI->getOperand(0).getReg();
6634 unsigned ptrA = MI->getOperand(1).getReg();
6635 unsigned ptrB = MI->getOperand(2).getReg();
6636 unsigned oldval = MI->getOperand(3).getReg();
6637 unsigned newval = MI->getOperand(4).getReg();
6638 DebugLoc dl = MI->getDebugLoc();
6640 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6641 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6642 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6643 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6644 F->insert(It, loop1MBB);
6645 F->insert(It, loop2MBB);
6646 F->insert(It, midMBB);
6647 F->insert(It, exitMBB);
6648 exitMBB->splice(exitMBB->begin(), BB,
6649 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6650 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6654 // fallthrough --> loopMBB
6655 BB->addSuccessor(loop1MBB);
6658 // l[wd]arx dest, ptr
6659 // cmp[wd] dest, oldval
6662 // st[wd]cx. newval, ptr
6666 // st[wd]cx. dest, ptr
6669 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6670 .addReg(ptrA).addReg(ptrB);
6671 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6672 .addReg(oldval).addReg(dest);
6673 BuildMI(BB, dl, TII->get(PPC::BCC))
6674 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6675 BB->addSuccessor(loop2MBB);
6676 BB->addSuccessor(midMBB);
6679 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6680 .addReg(newval).addReg(ptrA).addReg(ptrB);
6681 BuildMI(BB, dl, TII->get(PPC::BCC))
6682 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6683 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6684 BB->addSuccessor(loop1MBB);
6685 BB->addSuccessor(exitMBB);
6688 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6689 .addReg(dest).addReg(ptrA).addReg(ptrB);
6690 BB->addSuccessor(exitMBB);
6695 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6696 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6697 // We must use 64-bit registers for addresses when targeting 64-bit,
6698 // since we're actually doing arithmetic on them. Other registers
6700 bool is64bit = PPCSubTarget.isPPC64();
6701 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6703 unsigned dest = MI->getOperand(0).getReg();
6704 unsigned ptrA = MI->getOperand(1).getReg();
6705 unsigned ptrB = MI->getOperand(2).getReg();
6706 unsigned oldval = MI->getOperand(3).getReg();
6707 unsigned newval = MI->getOperand(4).getReg();
6708 DebugLoc dl = MI->getDebugLoc();
6710 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6711 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6712 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6713 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6714 F->insert(It, loop1MBB);
6715 F->insert(It, loop2MBB);
6716 F->insert(It, midMBB);
6717 F->insert(It, exitMBB);
6718 exitMBB->splice(exitMBB->begin(), BB,
6719 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6720 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6722 MachineRegisterInfo &RegInfo = F->getRegInfo();
6723 const TargetRegisterClass *RC =
6724 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6725 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6726 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6727 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6728 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6729 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6730 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6731 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6732 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6733 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6734 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6735 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6736 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6737 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6738 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6740 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6741 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6744 // fallthrough --> loopMBB
6745 BB->addSuccessor(loop1MBB);
6747 // The 4-byte load must be aligned, while a char or short may be
6748 // anywhere in the word. Hence all this nasty bookkeeping code.
6749 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6750 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6751 // xori shift, shift1, 24 [16]
6752 // rlwinm ptr, ptr1, 0, 0, 29
6753 // slw newval2, newval, shift
6754 // slw oldval2, oldval,shift
6755 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6756 // slw mask, mask2, shift
6757 // and newval3, newval2, mask
6758 // and oldval3, oldval2, mask
6760 // lwarx tmpDest, ptr
6761 // and tmp, tmpDest, mask
6762 // cmpw tmp, oldval3
6765 // andc tmp2, tmpDest, mask
6766 // or tmp4, tmp2, newval3
6771 // stwcx. tmpDest, ptr
6773 // srw dest, tmpDest, shift
6774 if (ptrA != ZeroReg) {
6775 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6776 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6777 .addReg(ptrA).addReg(ptrB);
6781 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6782 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6783 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6784 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6786 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6787 .addReg(Ptr1Reg).addImm(0).addImm(61);
6789 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6790 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6791 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6792 .addReg(newval).addReg(ShiftReg);
6793 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6794 .addReg(oldval).addReg(ShiftReg);
6796 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6798 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6799 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6800 .addReg(Mask3Reg).addImm(65535);
6802 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6803 .addReg(Mask2Reg).addReg(ShiftReg);
6804 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6805 .addReg(NewVal2Reg).addReg(MaskReg);
6806 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6807 .addReg(OldVal2Reg).addReg(MaskReg);
6810 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6811 .addReg(ZeroReg).addReg(PtrReg);
6812 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6813 .addReg(TmpDestReg).addReg(MaskReg);
6814 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6815 .addReg(TmpReg).addReg(OldVal3Reg);
6816 BuildMI(BB, dl, TII->get(PPC::BCC))
6817 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6818 BB->addSuccessor(loop2MBB);
6819 BB->addSuccessor(midMBB);
6822 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6823 .addReg(TmpDestReg).addReg(MaskReg);
6824 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6825 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6826 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6827 .addReg(ZeroReg).addReg(PtrReg);
6828 BuildMI(BB, dl, TII->get(PPC::BCC))
6829 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6830 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6831 BB->addSuccessor(loop1MBB);
6832 BB->addSuccessor(exitMBB);
6835 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6836 .addReg(ZeroReg).addReg(PtrReg);
6837 BB->addSuccessor(exitMBB);
6842 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6844 } else if (MI->getOpcode() == PPC::FADDrtz) {
6845 // This pseudo performs an FADD with rounding mode temporarily forced
6846 // to round-to-zero. We emit this via custom inserter since the FPSCR
6847 // is not modeled at the SelectionDAG level.
6848 unsigned Dest = MI->getOperand(0).getReg();
6849 unsigned Src1 = MI->getOperand(1).getReg();
6850 unsigned Src2 = MI->getOperand(2).getReg();
6851 DebugLoc dl = MI->getDebugLoc();
6853 MachineRegisterInfo &RegInfo = F->getRegInfo();
6854 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6856 // Save FPSCR value.
6857 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6859 // Set rounding mode to round-to-zero.
6860 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6861 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6863 // Perform addition.
6864 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6866 // Restore FPSCR value.
6867 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6868 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
6869 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
6870 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
6871 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
6872 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
6873 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
6874 PPC::ANDIo8 : PPC::ANDIo;
6875 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
6876 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
6878 MachineRegisterInfo &RegInfo = F->getRegInfo();
6879 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
6880 &PPC::GPRCRegClass :
6881 &PPC::G8RCRegClass);
6883 DebugLoc dl = MI->getDebugLoc();
6884 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
6885 .addReg(MI->getOperand(1).getReg()).addImm(1);
6886 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
6887 MI->getOperand(0).getReg())
6888 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
6890 llvm_unreachable("Unexpected instr type to insert");
6893 MI->eraseFromParent(); // The pseudo instruction is gone now.
6897 //===----------------------------------------------------------------------===//
6898 // Target Optimization Hooks
6899 //===----------------------------------------------------------------------===//
6901 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6902 DAGCombinerInfo &DCI) const {
6903 if (DCI.isAfterLegalizeVectorOps())
6906 EVT VT = Op.getValueType();
6908 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6909 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6910 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6912 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6913 // For the reciprocal, we need to find the zero of the function:
6914 // F(X) = A X - 1 [which has a zero at X = 1/A]
6916 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6917 // does not require additional intermediate precision]
6919 // Convergence is quadratic, so we essentially double the number of digits
6920 // correct after every iteration. The minimum architected relative
6921 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6922 // 23 digits and double has 52 digits.
6923 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6924 if (VT.getScalarType() == MVT::f64)
6927 SelectionDAG &DAG = DCI.DAG;
6931 DAG.getConstantFP(1.0, VT.getScalarType());
6932 if (VT.isVector()) {
6933 assert(VT.getVectorNumElements() == 4 &&
6934 "Unknown vector type");
6935 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6936 FPOne, FPOne, FPOne, FPOne);
6939 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6940 DCI.AddToWorklist(Est.getNode());
6942 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6943 for (int i = 0; i < Iterations; ++i) {
6944 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6945 DCI.AddToWorklist(NewEst.getNode());
6947 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6948 DCI.AddToWorklist(NewEst.getNode());
6950 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6951 DCI.AddToWorklist(NewEst.getNode());
6953 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6954 DCI.AddToWorklist(Est.getNode());
6963 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6964 DAGCombinerInfo &DCI) const {
6965 if (DCI.isAfterLegalizeVectorOps())
6968 EVT VT = Op.getValueType();
6970 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6971 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6972 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6974 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6975 // For the reciprocal sqrt, we need to find the zero of the function:
6976 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6978 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6979 // As a result, we precompute A/2 prior to the iteration loop.
6981 // Convergence is quadratic, so we essentially double the number of digits
6982 // correct after every iteration. The minimum architected relative
6983 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6984 // 23 digits and double has 52 digits.
6985 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6986 if (VT.getScalarType() == MVT::f64)
6989 SelectionDAG &DAG = DCI.DAG;
6992 SDValue FPThreeHalves =
6993 DAG.getConstantFP(1.5, VT.getScalarType());
6994 if (VT.isVector()) {
6995 assert(VT.getVectorNumElements() == 4 &&
6996 "Unknown vector type");
6997 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6998 FPThreeHalves, FPThreeHalves,
6999 FPThreeHalves, FPThreeHalves);
7002 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7003 DCI.AddToWorklist(Est.getNode());
7005 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7006 // this entire sequence requires only one FP constant.
7007 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7008 DCI.AddToWorklist(HalfArg.getNode());
7010 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7011 DCI.AddToWorklist(HalfArg.getNode());
7013 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7014 for (int i = 0; i < Iterations; ++i) {
7015 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7016 DCI.AddToWorklist(NewEst.getNode());
7018 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7019 DCI.AddToWorklist(NewEst.getNode());
7021 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7022 DCI.AddToWorklist(NewEst.getNode());
7024 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7025 DCI.AddToWorklist(Est.getNode());
7034 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7035 // not enforce equality of the chain operands.
7036 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7037 unsigned Bytes, int Dist,
7038 SelectionDAG &DAG) {
7039 EVT VT = LS->getMemoryVT();
7040 if (VT.getSizeInBits() / 8 != Bytes)
7043 SDValue Loc = LS->getBasePtr();
7044 SDValue BaseLoc = Base->getBasePtr();
7045 if (Loc.getOpcode() == ISD::FrameIndex) {
7046 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7048 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7049 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7050 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7051 int FS = MFI->getObjectSize(FI);
7052 int BFS = MFI->getObjectSize(BFI);
7053 if (FS != BFS || FS != (int)Bytes) return false;
7054 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7058 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7059 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7063 const GlobalValue *GV1 = NULL;
7064 const GlobalValue *GV2 = NULL;
7065 int64_t Offset1 = 0;
7066 int64_t Offset2 = 0;
7067 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7068 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7069 if (isGA1 && isGA2 && GV1 == GV2)
7070 return Offset1 == (Offset2 + Dist*Bytes);
7074 // Return true is there is a nearyby consecutive load to the one provided
7075 // (regardless of alignment). We search up and down the chain, looking though
7076 // token factors and other loads (but nothing else). As a result, a true
7077 // results indicates that it is safe to create a new consecutive load adjacent
7078 // to the load provided.
7079 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7080 SDValue Chain = LD->getChain();
7081 EVT VT = LD->getMemoryVT();
7083 SmallSet<SDNode *, 16> LoadRoots;
7084 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7085 SmallSet<SDNode *, 16> Visited;
7087 // First, search up the chain, branching to follow all token-factor operands.
7088 // If we find a consecutive load, then we're done, otherwise, record all
7089 // nodes just above the top-level loads and token factors.
7090 while (!Queue.empty()) {
7091 SDNode *ChainNext = Queue.pop_back_val();
7092 if (!Visited.insert(ChainNext))
7095 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7096 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7099 if (!Visited.count(ChainLD->getChain().getNode()))
7100 Queue.push_back(ChainLD->getChain().getNode());
7101 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7102 for (SDNode::op_iterator O = ChainNext->op_begin(),
7103 OE = ChainNext->op_end(); O != OE; ++O)
7104 if (!Visited.count(O->getNode()))
7105 Queue.push_back(O->getNode());
7107 LoadRoots.insert(ChainNext);
7110 // Second, search down the chain, starting from the top-level nodes recorded
7111 // in the first phase. These top-level nodes are the nodes just above all
7112 // loads and token factors. Starting with their uses, recursively look though
7113 // all loads (just the chain uses) and token factors to find a consecutive
7118 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7119 IE = LoadRoots.end(); I != IE; ++I) {
7120 Queue.push_back(*I);
7122 while (!Queue.empty()) {
7123 SDNode *LoadRoot = Queue.pop_back_val();
7124 if (!Visited.insert(LoadRoot))
7127 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7128 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7131 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7132 UE = LoadRoot->use_end(); UI != UE; ++UI)
7133 if (((isa<LoadSDNode>(*UI) &&
7134 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7135 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7136 Queue.push_back(*UI);
7143 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7144 DAGCombinerInfo &DCI) const {
7145 SelectionDAG &DAG = DCI.DAG;
7148 assert(PPCSubTarget.useCRBits() &&
7149 "Expecting to be tracking CR bits");
7150 // If we're tracking CR bits, we need to be careful that we don't have:
7151 // trunc(binary-ops(zext(x), zext(y)))
7153 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7154 // such that we're unnecessarily moving things into GPRs when it would be
7155 // better to keep them in CR bits.
7157 // Note that trunc here can be an actual i1 trunc, or can be the effective
7158 // truncation that comes from a setcc or select_cc.
7159 if (N->getOpcode() == ISD::TRUNCATE &&
7160 N->getValueType(0) != MVT::i1)
7163 if (N->getOperand(0).getValueType() != MVT::i32 &&
7164 N->getOperand(0).getValueType() != MVT::i64)
7167 if (N->getOpcode() == ISD::SETCC ||
7168 N->getOpcode() == ISD::SELECT_CC) {
7169 // If we're looking at a comparison, then we need to make sure that the
7170 // high bits (all except for the first) don't matter the result.
7172 cast<CondCodeSDNode>(N->getOperand(
7173 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7174 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7176 if (ISD::isSignedIntSetCC(CC)) {
7177 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7178 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7180 } else if (ISD::isUnsignedIntSetCC(CC)) {
7181 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7182 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7183 !DAG.MaskedValueIsZero(N->getOperand(1),
7184 APInt::getHighBitsSet(OpBits, OpBits-1)))
7187 // This is neither a signed nor an unsigned comparison, just make sure
7188 // that the high bits are equal.
7189 APInt Op1Zero, Op1One;
7190 APInt Op2Zero, Op2One;
7191 DAG.ComputeMaskedBits(N->getOperand(0), Op1Zero, Op1One);
7192 DAG.ComputeMaskedBits(N->getOperand(1), Op2Zero, Op2One);
7194 // We don't really care about what is known about the first bit (if
7195 // anything), so clear it in all masks prior to comparing them.
7196 Op1Zero.clearBit(0); Op1One.clearBit(0);
7197 Op2Zero.clearBit(0); Op2One.clearBit(0);
7199 if (Op1Zero != Op2Zero || Op1One != Op2One)
7204 // We now know that the higher-order bits are irrelevant, we just need to
7205 // make sure that all of the intermediate operations are bit operations, and
7206 // all inputs are extensions.
7207 if (N->getOperand(0).getOpcode() != ISD::AND &&
7208 N->getOperand(0).getOpcode() != ISD::OR &&
7209 N->getOperand(0).getOpcode() != ISD::XOR &&
7210 N->getOperand(0).getOpcode() != ISD::SELECT &&
7211 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7212 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7213 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7214 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7215 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7218 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7219 N->getOperand(1).getOpcode() != ISD::AND &&
7220 N->getOperand(1).getOpcode() != ISD::OR &&
7221 N->getOperand(1).getOpcode() != ISD::XOR &&
7222 N->getOperand(1).getOpcode() != ISD::SELECT &&
7223 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7224 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7225 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7226 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7227 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7230 SmallVector<SDValue, 4> Inputs;
7231 SmallVector<SDValue, 8> BinOps, PromOps;
7232 SmallPtrSet<SDNode *, 16> Visited;
7234 for (unsigned i = 0; i < 2; ++i) {
7235 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7236 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7237 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7238 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7239 isa<ConstantSDNode>(N->getOperand(i)))
7240 Inputs.push_back(N->getOperand(i));
7242 BinOps.push_back(N->getOperand(i));
7244 if (N->getOpcode() == ISD::TRUNCATE)
7248 // Visit all inputs, collect all binary operations (and, or, xor and
7249 // select) that are all fed by extensions.
7250 while (!BinOps.empty()) {
7251 SDValue BinOp = BinOps.back();
7254 if (!Visited.insert(BinOp.getNode()))
7257 PromOps.push_back(BinOp);
7259 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7260 // The condition of the select is not promoted.
7261 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7263 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7266 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7267 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7268 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7269 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7270 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7271 Inputs.push_back(BinOp.getOperand(i));
7272 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7273 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7274 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7275 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7276 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7277 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7278 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7279 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7280 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7281 BinOps.push_back(BinOp.getOperand(i));
7283 // We have an input that is not an extension or another binary
7284 // operation; we'll abort this transformation.
7290 // Make sure that this is a self-contained cluster of operations (which
7291 // is not quite the same thing as saying that everything has only one
7293 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7294 if (isa<ConstantSDNode>(Inputs[i]))
7297 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7298 UE = Inputs[i].getNode()->use_end();
7301 if (User != N && !Visited.count(User))
7304 // Make sure that we're not going to promote the non-output-value
7305 // operand(s) or SELECT or SELECT_CC.
7306 // FIXME: Although we could sometimes handle this, and it does occur in
7307 // practice that one of the condition inputs to the select is also one of
7308 // the outputs, we currently can't deal with this.
7309 if (User->getOpcode() == ISD::SELECT) {
7310 if (User->getOperand(0) == Inputs[i])
7312 } else if (User->getOpcode() == ISD::SELECT_CC) {
7313 if (User->getOperand(0) == Inputs[i] ||
7314 User->getOperand(1) == Inputs[i])
7320 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7321 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7322 UE = PromOps[i].getNode()->use_end();
7325 if (User != N && !Visited.count(User))
7328 // Make sure that we're not going to promote the non-output-value
7329 // operand(s) or SELECT or SELECT_CC.
7330 // FIXME: Although we could sometimes handle this, and it does occur in
7331 // practice that one of the condition inputs to the select is also one of
7332 // the outputs, we currently can't deal with this.
7333 if (User->getOpcode() == ISD::SELECT) {
7334 if (User->getOperand(0) == PromOps[i])
7336 } else if (User->getOpcode() == ISD::SELECT_CC) {
7337 if (User->getOperand(0) == PromOps[i] ||
7338 User->getOperand(1) == PromOps[i])
7344 // Replace all inputs with the extension operand.
7345 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7346 // Constants may have users outside the cluster of to-be-promoted nodes,
7347 // and so we need to replace those as we do the promotions.
7348 if (isa<ConstantSDNode>(Inputs[i]))
7351 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7354 // Replace all operations (these are all the same, but have a different
7355 // (i1) return type). DAG.getNode will validate that the types of
7356 // a binary operator match, so go through the list in reverse so that
7357 // we've likely promoted both operands first. Any intermediate truncations or
7358 // extensions disappear.
7359 while (!PromOps.empty()) {
7360 SDValue PromOp = PromOps.back();
7363 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7364 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7365 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7366 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7367 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7368 PromOp.getOperand(0).getValueType() != MVT::i1) {
7369 // The operand is not yet ready (see comment below).
7370 PromOps.insert(PromOps.begin(), PromOp);
7374 SDValue RepValue = PromOp.getOperand(0);
7375 if (isa<ConstantSDNode>(RepValue))
7376 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7378 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7383 switch (PromOp.getOpcode()) {
7384 default: C = 0; break;
7385 case ISD::SELECT: C = 1; break;
7386 case ISD::SELECT_CC: C = 2; break;
7389 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7390 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7391 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7392 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7393 // The to-be-promoted operands of this node have not yet been
7394 // promoted (this should be rare because we're going through the
7395 // list backward, but if one of the operands has several users in
7396 // this cluster of to-be-promoted nodes, it is possible).
7397 PromOps.insert(PromOps.begin(), PromOp);
7401 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7402 PromOp.getNode()->op_end());
7404 // If there are any constant inputs, make sure they're replaced now.
7405 for (unsigned i = 0; i < 2; ++i)
7406 if (isa<ConstantSDNode>(Ops[C+i]))
7407 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7409 DAG.ReplaceAllUsesOfValueWith(PromOp,
7410 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1,
7411 Ops.data(), Ops.size()));
7414 // Now we're left with the initial truncation itself.
7415 if (N->getOpcode() == ISD::TRUNCATE)
7416 return N->getOperand(0);
7418 // Otherwise, this is a comparison. The operands to be compared have just
7419 // changed type (to i1), but everything else is the same.
7420 return SDValue(N, 0);
7423 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7424 DAGCombinerInfo &DCI) const {
7425 SelectionDAG &DAG = DCI.DAG;
7428 // If we're tracking CR bits, we need to be careful that we don't have:
7429 // zext(binary-ops(trunc(x), trunc(y)))
7431 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7432 // such that we're unnecessarily moving things into CR bits that can more
7433 // efficiently stay in GPRs. Note that if we're not certain that the high
7434 // bits are set as required by the final extension, we still may need to do
7435 // some masking to get the proper behavior.
7437 // This same functionality is important on PPC64 when dealing with
7438 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7439 // the return values of functions. Because it is so similar, it is handled
7442 if (N->getValueType(0) != MVT::i32 &&
7443 N->getValueType(0) != MVT::i64)
7446 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7447 PPCSubTarget.useCRBits()) ||
7448 (N->getOperand(0).getValueType() == MVT::i32 &&
7449 PPCSubTarget.isPPC64())))
7452 if (N->getOperand(0).getOpcode() != ISD::AND &&
7453 N->getOperand(0).getOpcode() != ISD::OR &&
7454 N->getOperand(0).getOpcode() != ISD::XOR &&
7455 N->getOperand(0).getOpcode() != ISD::SELECT &&
7456 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7459 SmallVector<SDValue, 4> Inputs;
7460 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7461 SmallPtrSet<SDNode *, 16> Visited;
7463 // Visit all inputs, collect all binary operations (and, or, xor and
7464 // select) that are all fed by truncations.
7465 while (!BinOps.empty()) {
7466 SDValue BinOp = BinOps.back();
7469 if (!Visited.insert(BinOp.getNode()))
7472 PromOps.push_back(BinOp);
7474 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7475 // The condition of the select is not promoted.
7476 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7478 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7481 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7482 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7483 Inputs.push_back(BinOp.getOperand(i));
7484 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7485 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7486 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7487 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7488 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7489 BinOps.push_back(BinOp.getOperand(i));
7491 // We have an input that is not a truncation or another binary
7492 // operation; we'll abort this transformation.
7498 // Make sure that this is a self-contained cluster of operations (which
7499 // is not quite the same thing as saying that everything has only one
7501 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7502 if (isa<ConstantSDNode>(Inputs[i]))
7505 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7506 UE = Inputs[i].getNode()->use_end();
7509 if (User != N && !Visited.count(User))
7512 // Make sure that we're not going to promote the non-output-value
7513 // operand(s) or SELECT or SELECT_CC.
7514 // FIXME: Although we could sometimes handle this, and it does occur in
7515 // practice that one of the condition inputs to the select is also one of
7516 // the outputs, we currently can't deal with this.
7517 if (User->getOpcode() == ISD::SELECT) {
7518 if (User->getOperand(0) == Inputs[i])
7520 } else if (User->getOpcode() == ISD::SELECT_CC) {
7521 if (User->getOperand(0) == Inputs[i] ||
7522 User->getOperand(1) == Inputs[i])
7528 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7529 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7530 UE = PromOps[i].getNode()->use_end();
7533 if (User != N && !Visited.count(User))
7536 // Make sure that we're not going to promote the non-output-value
7537 // operand(s) or SELECT or SELECT_CC.
7538 // FIXME: Although we could sometimes handle this, and it does occur in
7539 // practice that one of the condition inputs to the select is also one of
7540 // the outputs, we currently can't deal with this.
7541 if (User->getOpcode() == ISD::SELECT) {
7542 if (User->getOperand(0) == PromOps[i])
7544 } else if (User->getOpcode() == ISD::SELECT_CC) {
7545 if (User->getOperand(0) == PromOps[i] ||
7546 User->getOperand(1) == PromOps[i])
7552 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7553 bool ReallyNeedsExt = false;
7554 if (N->getOpcode() != ISD::ANY_EXTEND) {
7555 // If all of the inputs are not already sign/zero extended, then
7556 // we'll still need to do that at the end.
7557 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7558 if (isa<ConstantSDNode>(Inputs[i]))
7562 Inputs[i].getOperand(0).getValueSizeInBits();
7563 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7565 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7566 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7567 APInt::getHighBitsSet(OpBits,
7568 OpBits-PromBits))) ||
7569 (N->getOpcode() == ISD::SIGN_EXTEND &&
7570 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7571 (OpBits-(PromBits-1)))) {
7572 ReallyNeedsExt = true;
7578 // Replace all inputs, either with the truncation operand, or a
7579 // truncation or extension to the final output type.
7580 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7581 // Constant inputs need to be replaced with the to-be-promoted nodes that
7582 // use them because they might have users outside of the cluster of
7584 if (isa<ConstantSDNode>(Inputs[i]))
7587 SDValue InSrc = Inputs[i].getOperand(0);
7588 if (Inputs[i].getValueType() == N->getValueType(0))
7589 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7590 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7591 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7592 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7593 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7594 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7595 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7597 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7598 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7601 // Replace all operations (these are all the same, but have a different
7602 // (promoted) return type). DAG.getNode will validate that the types of
7603 // a binary operator match, so go through the list in reverse so that
7604 // we've likely promoted both operands first.
7605 while (!PromOps.empty()) {
7606 SDValue PromOp = PromOps.back();
7610 switch (PromOp.getOpcode()) {
7611 default: C = 0; break;
7612 case ISD::SELECT: C = 1; break;
7613 case ISD::SELECT_CC: C = 2; break;
7616 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7617 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7618 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7619 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7620 // The to-be-promoted operands of this node have not yet been
7621 // promoted (this should be rare because we're going through the
7622 // list backward, but if one of the operands has several users in
7623 // this cluster of to-be-promoted nodes, it is possible).
7624 PromOps.insert(PromOps.begin(), PromOp);
7628 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7629 PromOp.getNode()->op_end());
7631 // If this node has constant inputs, then they'll need to be promoted here.
7632 for (unsigned i = 0; i < 2; ++i) {
7633 if (!isa<ConstantSDNode>(Ops[C+i]))
7635 if (Ops[C+i].getValueType() == N->getValueType(0))
7638 if (N->getOpcode() == ISD::SIGN_EXTEND)
7639 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7640 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7641 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7643 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7646 DAG.ReplaceAllUsesOfValueWith(PromOp,
7647 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0),
7648 Ops.data(), Ops.size()));
7651 // Now we're left with the initial extension itself.
7652 if (!ReallyNeedsExt)
7653 return N->getOperand(0);
7655 // To zero extend, just mask off everything except for the first bit (in the
7657 if (N->getOpcode() == ISD::ZERO_EXTEND)
7658 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7659 DAG.getConstant(APInt::getLowBitsSet(
7660 N->getValueSizeInBits(0), PromBits),
7661 N->getValueType(0)));
7663 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7664 "Invalid extension type");
7665 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7667 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7668 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7669 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7670 N->getOperand(0), ShiftCst), ShiftCst);
7673 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7674 DAGCombinerInfo &DCI) const {
7675 const TargetMachine &TM = getTargetMachine();
7676 SelectionDAG &DAG = DCI.DAG;
7678 switch (N->getOpcode()) {
7681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7682 if (C->isNullValue()) // 0 << V -> 0.
7683 return N->getOperand(0);
7687 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7688 if (C->isNullValue()) // 0 >>u V -> 0.
7689 return N->getOperand(0);
7693 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7694 if (C->isNullValue() || // 0 >>s V -> 0.
7695 C->isAllOnesValue()) // -1 >>s V -> -1.
7696 return N->getOperand(0);
7699 case ISD::SIGN_EXTEND:
7700 case ISD::ZERO_EXTEND:
7701 case ISD::ANY_EXTEND:
7702 return DAGCombineExtBoolTrunc(N, DCI);
7705 case ISD::SELECT_CC:
7706 return DAGCombineTruncBoolExt(N, DCI);
7708 assert(TM.Options.UnsafeFPMath &&
7709 "Reciprocal estimates require UnsafeFPMath");
7711 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7713 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7714 if (RV.getNode() != 0) {
7715 DCI.AddToWorklist(RV.getNode());
7716 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7717 N->getOperand(0), RV);
7719 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7720 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7722 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7724 if (RV.getNode() != 0) {
7725 DCI.AddToWorklist(RV.getNode());
7726 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7727 N->getValueType(0), RV);
7728 DCI.AddToWorklist(RV.getNode());
7729 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7730 N->getOperand(0), RV);
7732 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7733 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7735 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7737 if (RV.getNode() != 0) {
7738 DCI.AddToWorklist(RV.getNode());
7739 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7740 N->getValueType(0), RV,
7741 N->getOperand(1).getOperand(1));
7742 DCI.AddToWorklist(RV.getNode());
7743 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7744 N->getOperand(0), RV);
7748 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7749 if (RV.getNode() != 0) {
7750 DCI.AddToWorklist(RV.getNode());
7751 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7752 N->getOperand(0), RV);
7758 assert(TM.Options.UnsafeFPMath &&
7759 "Reciprocal estimates require UnsafeFPMath");
7761 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7763 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7764 if (RV.getNode() != 0) {
7765 DCI.AddToWorklist(RV.getNode());
7766 RV = DAGCombineFastRecip(RV, DCI);
7767 if (RV.getNode() != 0) {
7768 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
7769 // this case and force the answer to 0.
7771 EVT VT = RV.getValueType();
7773 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
7774 if (VT.isVector()) {
7775 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
7776 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
7780 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
7781 N->getOperand(0), Zero, ISD::SETEQ);
7782 DCI.AddToWorklist(ZeroCmp.getNode());
7783 DCI.AddToWorklist(RV.getNode());
7785 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
7793 case ISD::SINT_TO_FP:
7794 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
7795 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7796 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
7797 // We allow the src/dst to be either f32/f64, but the intermediate
7798 // type must be i64.
7799 if (N->getOperand(0).getValueType() == MVT::i64 &&
7800 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7801 SDValue Val = N->getOperand(0).getOperand(0);
7802 if (Val.getValueType() == MVT::f32) {
7803 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7804 DCI.AddToWorklist(Val.getNode());
7807 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7808 DCI.AddToWorklist(Val.getNode());
7809 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7810 DCI.AddToWorklist(Val.getNode());
7811 if (N->getValueType(0) == MVT::f32) {
7812 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7813 DAG.getIntPtrConstant(0));
7814 DCI.AddToWorklist(Val.getNode());
7817 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7818 // If the intermediate type is i32, we can avoid the load/store here
7825 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7826 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7827 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7828 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7829 N->getOperand(1).getValueType() == MVT::i32 &&
7830 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7831 SDValue Val = N->getOperand(1).getOperand(0);
7832 if (Val.getValueType() == MVT::f32) {
7833 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7834 DCI.AddToWorklist(Val.getNode());
7836 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7837 DCI.AddToWorklist(Val.getNode());
7840 N->getOperand(0), Val, N->getOperand(2),
7841 DAG.getValueType(N->getOperand(1).getValueType())
7844 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
7845 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7846 cast<StoreSDNode>(N)->getMemoryVT(),
7847 cast<StoreSDNode>(N)->getMemOperand());
7848 DCI.AddToWorklist(Val.getNode());
7852 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
7853 if (cast<StoreSDNode>(N)->isUnindexed() &&
7854 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7855 N->getOperand(1).getNode()->hasOneUse() &&
7856 (N->getOperand(1).getValueType() == MVT::i32 ||
7857 N->getOperand(1).getValueType() == MVT::i16 ||
7858 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7859 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7860 N->getOperand(1).getValueType() == MVT::i64))) {
7861 SDValue BSwapOp = N->getOperand(1).getOperand(0);
7862 // Do an any-extend to 32-bits if this is a half-word input.
7863 if (BSwapOp.getValueType() == MVT::i16)
7864 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7867 N->getOperand(0), BSwapOp, N->getOperand(2),
7868 DAG.getValueType(N->getOperand(1).getValueType())
7871 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7872 Ops, array_lengthof(Ops),
7873 cast<StoreSDNode>(N)->getMemoryVT(),
7874 cast<StoreSDNode>(N)->getMemOperand());
7878 LoadSDNode *LD = cast<LoadSDNode>(N);
7879 EVT VT = LD->getValueType(0);
7880 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
7881 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
7882 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7883 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
7884 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
7885 VT == MVT::v4i32 || VT == MVT::v4f32) &&
7886 LD->getAlignment() < ABIAlignment) {
7887 // This is a type-legal unaligned Altivec load.
7888 SDValue Chain = LD->getChain();
7889 SDValue Ptr = LD->getBasePtr();
7891 // This implements the loading of unaligned vectors as described in
7892 // the venerable Apple Velocity Engine overview. Specifically:
7893 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
7894 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
7896 // The general idea is to expand a sequence of one or more unaligned
7897 // loads into a alignment-based permutation-control instruction (lvsl),
7898 // a series of regular vector loads (which always truncate their
7899 // input address to an aligned address), and a series of permutations.
7900 // The results of these permutations are the requested loaded values.
7901 // The trick is that the last "extra" load is not taken from the address
7902 // you might suspect (sizeof(vector) bytes after the last requested
7903 // load), but rather sizeof(vector) - 1 bytes after the last
7904 // requested vector. The point of this is to avoid a page fault if the
7905 // base address happened to be aligned. This works because if the base
7906 // address is aligned, then adding less than a full vector length will
7907 // cause the last vector in the sequence to be (re)loaded. Otherwise,
7908 // the next vector will be fetched as you might suspect was necessary.
7910 // We might be able to reuse the permutation generation from
7911 // a different base address offset from this one by an aligned amount.
7912 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
7913 // optimization later.
7914 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
7915 DAG, dl, MVT::v16i8);
7917 // Refine the alignment of the original load (a "new" load created here
7918 // which was identical to the first except for the alignment would be
7919 // merged with the existing node regardless).
7920 MachineFunction &MF = DAG.getMachineFunction();
7921 MachineMemOperand *MMO =
7922 MF.getMachineMemOperand(LD->getPointerInfo(),
7923 LD->getMemOperand()->getFlags(),
7924 LD->getMemoryVT().getStoreSize(),
7926 LD->refineAlignment(MMO);
7927 SDValue BaseLoad = SDValue(LD, 0);
7929 // Note that the value of IncOffset (which is provided to the next
7930 // load's pointer info offset value, and thus used to calculate the
7931 // alignment), and the value of IncValue (which is actually used to
7932 // increment the pointer value) are different! This is because we
7933 // require the next load to appear to be aligned, even though it
7934 // is actually offset from the base pointer by a lesser amount.
7935 int IncOffset = VT.getSizeInBits() / 8;
7936 int IncValue = IncOffset;
7938 // Walk (both up and down) the chain looking for another load at the real
7939 // (aligned) offset (the alignment of the other load does not matter in
7940 // this case). If found, then do not use the offset reduction trick, as
7941 // that will prevent the loads from being later combined (as they would
7942 // otherwise be duplicates).
7943 if (!findConsecutiveLoad(LD, DAG))
7946 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
7947 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7950 DAG.getLoad(VT, dl, Chain, Ptr,
7951 LD->getPointerInfo().getWithOffset(IncOffset),
7952 LD->isVolatile(), LD->isNonTemporal(),
7953 LD->isInvariant(), ABIAlignment);
7955 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7956 BaseLoad.getValue(1), ExtraLoad.getValue(1));
7958 if (BaseLoad.getValueType() != MVT::v4i32)
7959 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7961 if (ExtraLoad.getValueType() != MVT::v4i32)
7962 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7964 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
7965 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
7967 if (VT != MVT::v4i32)
7968 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7970 // Now we need to be really careful about how we update the users of the
7971 // original load. We cannot just call DCI.CombineTo (or
7972 // DAG.ReplaceAllUsesWith for that matter), because the load still has
7973 // uses created here (the permutation for example) that need to stay.
7974 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7976 SDUse &Use = UI.getUse();
7978 // Note: BaseLoad is checked here because it might not be N, but a
7980 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
7981 User == TF.getNode() || Use.getResNo() > 1) {
7986 SDValue To = Use.getResNo() ? TF : Perm;
7989 SmallVector<SDValue, 8> Ops;
7990 for (SDNode::op_iterator O = User->op_begin(),
7991 OE = User->op_end(); O != OE; ++O) {
7998 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
8001 return SDValue(N, 0);
8005 case ISD::INTRINSIC_WO_CHAIN:
8006 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
8007 Intrinsic::ppc_altivec_lvsl &&
8008 N->getOperand(1)->getOpcode() == ISD::ADD) {
8009 SDValue Add = N->getOperand(1);
8011 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8012 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8013 Add.getValueType().getScalarType().getSizeInBits()))) {
8014 SDNode *BasePtr = Add->getOperand(0).getNode();
8015 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8016 UE = BasePtr->use_end(); UI != UE; ++UI) {
8017 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8018 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8019 Intrinsic::ppc_altivec_lvsl) {
8020 // We've found another LVSL, and this address if an aligned
8021 // multiple of that one. The results will be the same, so use the
8022 // one we've just found instead.
8024 return SDValue(*UI, 0);
8032 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8033 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8034 N->getOperand(0).hasOneUse() &&
8035 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8036 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8037 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8038 N->getValueType(0) == MVT::i64))) {
8039 SDValue Load = N->getOperand(0);
8040 LoadSDNode *LD = cast<LoadSDNode>(Load);
8041 // Create the byte-swapping load.
8043 LD->getChain(), // Chain
8044 LD->getBasePtr(), // Ptr
8045 DAG.getValueType(N->getValueType(0)) // VT
8048 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8049 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8050 MVT::i64 : MVT::i32, MVT::Other),
8051 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
8053 // If this is an i16 load, insert the truncate.
8054 SDValue ResVal = BSLoad;
8055 if (N->getValueType(0) == MVT::i16)
8056 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8058 // First, combine the bswap away. This makes the value produced by the
8060 DCI.CombineTo(N, ResVal);
8062 // Next, combine the load away, we give it a bogus result value but a real
8063 // chain result. The result value is dead because the bswap is dead.
8064 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8066 // Return N so it doesn't get rechecked!
8067 return SDValue(N, 0);
8071 case PPCISD::VCMP: {
8072 // If a VCMPo node already exists with exactly the same operands as this
8073 // node, use its result instead of this node (VCMPo computes both a CR6 and
8074 // a normal output).
8076 if (!N->getOperand(0).hasOneUse() &&
8077 !N->getOperand(1).hasOneUse() &&
8078 !N->getOperand(2).hasOneUse()) {
8080 // Scan all of the users of the LHS, looking for VCMPo's that match.
8081 SDNode *VCMPoNode = 0;
8083 SDNode *LHSN = N->getOperand(0).getNode();
8084 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8086 if (UI->getOpcode() == PPCISD::VCMPo &&
8087 UI->getOperand(1) == N->getOperand(1) &&
8088 UI->getOperand(2) == N->getOperand(2) &&
8089 UI->getOperand(0) == N->getOperand(0)) {
8094 // If there is no VCMPo node, or if the flag value has a single use, don't
8096 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8099 // Look at the (necessarily single) use of the flag value. If it has a
8100 // chain, this transformation is more complex. Note that multiple things
8101 // could use the value result, which we should ignore.
8102 SDNode *FlagUser = 0;
8103 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8104 FlagUser == 0; ++UI) {
8105 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8107 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8108 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8115 // If the user is a MFOCRF instruction, we know this is safe.
8116 // Otherwise we give up for right now.
8117 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8118 return SDValue(VCMPoNode, 0);
8123 SDValue Cond = N->getOperand(1);
8124 SDValue Target = N->getOperand(2);
8126 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8127 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8128 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8130 // We now need to make the intrinsic dead (it cannot be instruction
8132 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8133 assert(Cond.getNode()->hasOneUse() &&
8134 "Counter decrement has more than one use");
8136 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8137 N->getOperand(0), Target);
8142 // If this is a branch on an altivec predicate comparison, lower this so
8143 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8144 // lowering is done pre-legalize, because the legalizer lowers the predicate
8145 // compare down to code that is difficult to reassemble.
8146 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8147 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8149 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8150 // value. If so, pass-through the AND to get to the intrinsic.
8151 if (LHS.getOpcode() == ISD::AND &&
8152 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8153 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8154 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8155 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8156 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8158 LHS = LHS.getOperand(0);
8160 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8161 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8162 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8163 isa<ConstantSDNode>(RHS)) {
8164 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8165 "Counter decrement comparison is not EQ or NE");
8167 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8168 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8169 (CC == ISD::SETNE && !Val);
8171 // We now need to make the intrinsic dead (it cannot be instruction
8173 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8174 assert(LHS.getNode()->hasOneUse() &&
8175 "Counter decrement has more than one use");
8177 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8178 N->getOperand(0), N->getOperand(4));
8184 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8185 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8186 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8187 assert(isDot && "Can't compare against a vector result!");
8189 // If this is a comparison against something other than 0/1, then we know
8190 // that the condition is never/always true.
8191 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8192 if (Val != 0 && Val != 1) {
8193 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8194 return N->getOperand(0);
8195 // Always !=, turn it into an unconditional branch.
8196 return DAG.getNode(ISD::BR, dl, MVT::Other,
8197 N->getOperand(0), N->getOperand(4));
8200 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8202 // Create the PPCISD altivec 'dot' comparison node.
8204 LHS.getOperand(2), // LHS of compare
8205 LHS.getOperand(3), // RHS of compare
8206 DAG.getConstant(CompareOpc, MVT::i32)
8208 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8209 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
8211 // Unpack the result based on how the target uses it.
8212 PPC::Predicate CompOpc;
8213 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8214 default: // Can't happen, don't crash on invalid number though.
8215 case 0: // Branch on the value of the EQ bit of CR6.
8216 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8218 case 1: // Branch on the inverted value of the EQ bit of CR6.
8219 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8221 case 2: // Branch on the value of the LT bit of CR6.
8222 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8224 case 3: // Branch on the inverted value of the LT bit of CR6.
8225 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8229 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8230 DAG.getConstant(CompOpc, MVT::i32),
8231 DAG.getRegister(PPC::CR6, MVT::i32),
8232 N->getOperand(4), CompNode.getValue(1));
8241 //===----------------------------------------------------------------------===//
8242 // Inline Assembly Support
8243 //===----------------------------------------------------------------------===//
8245 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8248 const SelectionDAG &DAG,
8249 unsigned Depth) const {
8250 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8251 switch (Op.getOpcode()) {
8253 case PPCISD::LBRX: {
8254 // lhbrx is known to have the top bits cleared out.
8255 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8256 KnownZero = 0xFFFF0000;
8259 case ISD::INTRINSIC_WO_CHAIN: {
8260 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8262 case Intrinsic::ppc_altivec_vcmpbfp_p:
8263 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8264 case Intrinsic::ppc_altivec_vcmpequb_p:
8265 case Intrinsic::ppc_altivec_vcmpequh_p:
8266 case Intrinsic::ppc_altivec_vcmpequw_p:
8267 case Intrinsic::ppc_altivec_vcmpgefp_p:
8268 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8269 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8270 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8271 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8272 case Intrinsic::ppc_altivec_vcmpgtub_p:
8273 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8274 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8275 KnownZero = ~1U; // All bits but the low one are known to be zero.
8283 /// getConstraintType - Given a constraint, return the type of
8284 /// constraint it is for this target.
8285 PPCTargetLowering::ConstraintType
8286 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8287 if (Constraint.size() == 1) {
8288 switch (Constraint[0]) {
8295 return C_RegisterClass;
8297 // FIXME: While Z does indicate a memory constraint, it specifically
8298 // indicates an r+r address (used in conjunction with the 'y' modifier
8299 // in the replacement string). Currently, we're forcing the base
8300 // register to be r0 in the asm printer (which is interpreted as zero)
8301 // and forming the complete address in the second register. This is
8305 } else if (Constraint == "wc") { // individual CR bits.
8306 return C_RegisterClass;
8308 return TargetLowering::getConstraintType(Constraint);
8311 /// Examine constraint type and operand type and determine a weight value.
8312 /// This object must already have been set up with the operand type
8313 /// and the current alternative constraint selected.
8314 TargetLowering::ConstraintWeight
8315 PPCTargetLowering::getSingleConstraintMatchWeight(
8316 AsmOperandInfo &info, const char *constraint) const {
8317 ConstraintWeight weight = CW_Invalid;
8318 Value *CallOperandVal = info.CallOperandVal;
8319 // If we don't have a value, we can't do a match,
8320 // but allow it at the lowest weight.
8321 if (CallOperandVal == NULL)
8323 Type *type = CallOperandVal->getType();
8325 // Look at the constraint type.
8326 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8327 return CW_Register; // an individual CR bit.
8329 switch (*constraint) {
8331 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8334 if (type->isIntegerTy())
8335 weight = CW_Register;
8338 if (type->isFloatTy())
8339 weight = CW_Register;
8342 if (type->isDoubleTy())
8343 weight = CW_Register;
8346 if (type->isVectorTy())
8347 weight = CW_Register;
8350 weight = CW_Register;
8359 std::pair<unsigned, const TargetRegisterClass*>
8360 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8362 if (Constraint.size() == 1) {
8363 // GCC RS6000 Constraint Letters
8364 switch (Constraint[0]) {
8366 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
8367 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8368 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8370 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
8371 return std::make_pair(0U, &PPC::G8RCRegClass);
8372 return std::make_pair(0U, &PPC::GPRCRegClass);
8374 if (VT == MVT::f32 || VT == MVT::i32)
8375 return std::make_pair(0U, &PPC::F4RCRegClass);
8376 if (VT == MVT::f64 || VT == MVT::i64)
8377 return std::make_pair(0U, &PPC::F8RCRegClass);
8380 return std::make_pair(0U, &PPC::VRRCRegClass);
8382 return std::make_pair(0U, &PPC::CRRCRegClass);
8384 } else if (Constraint == "wc") { // an individual CR bit.
8385 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8388 std::pair<unsigned, const TargetRegisterClass*> R =
8389 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8391 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8392 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8393 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8395 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8396 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8397 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
8398 PPC::GPRCRegClass.contains(R.first)) {
8399 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8400 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8401 PPC::sub_32, &PPC::G8RCRegClass),
8402 &PPC::G8RCRegClass);
8409 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8410 /// vector. If it is invalid, don't add anything to Ops.
8411 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8412 std::string &Constraint,
8413 std::vector<SDValue>&Ops,
8414 SelectionDAG &DAG) const {
8415 SDValue Result(0,0);
8417 // Only support length 1 constraints.
8418 if (Constraint.length() > 1) return;
8420 char Letter = Constraint[0];
8431 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8432 if (!CST) return; // Must be an immediate to match.
8433 unsigned Value = CST->getZExtValue();
8435 default: llvm_unreachable("Unknown constraint letter!");
8436 case 'I': // "I" is a signed 16-bit constant.
8437 if ((short)Value == (int)Value)
8438 Result = DAG.getTargetConstant(Value, Op.getValueType());
8440 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8441 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8442 if ((short)Value == 0)
8443 Result = DAG.getTargetConstant(Value, Op.getValueType());
8445 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8446 if ((Value >> 16) == 0)
8447 Result = DAG.getTargetConstant(Value, Op.getValueType());
8449 case 'M': // "M" is a constant that is greater than 31.
8451 Result = DAG.getTargetConstant(Value, Op.getValueType());
8453 case 'N': // "N" is a positive constant that is an exact power of two.
8454 if ((int)Value > 0 && isPowerOf2_32(Value))
8455 Result = DAG.getTargetConstant(Value, Op.getValueType());
8457 case 'O': // "O" is the constant zero.
8459 Result = DAG.getTargetConstant(Value, Op.getValueType());
8461 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8462 if ((short)-Value == (int)-Value)
8463 Result = DAG.getTargetConstant(Value, Op.getValueType());
8470 if (Result.getNode()) {
8471 Ops.push_back(Result);
8475 // Handle standard constraint letters.
8476 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8479 // isLegalAddressingMode - Return true if the addressing mode represented
8480 // by AM is legal for this target, for a load/store of the specified type.
8481 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8483 // FIXME: PPC does not allow r+i addressing modes for vectors!
8485 // PPC allows a sign-extended 16-bit immediate field.
8486 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8489 // No global is ever allowed as a base.
8493 // PPC only support r+r,
8495 case 0: // "r+i" or just "i", depending on HasBaseReg.
8498 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8500 // Otherwise we have r+r or r+i.
8503 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8505 // Allow 2*r as r+r.
8508 // No other scales are supported.
8515 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8516 SelectionDAG &DAG) const {
8517 MachineFunction &MF = DAG.getMachineFunction();
8518 MachineFrameInfo *MFI = MF.getFrameInfo();
8519 MFI->setReturnAddressIsTaken(true);
8521 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8525 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8527 // Make sure the function does not optimize away the store of the RA to
8529 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8530 FuncInfo->setLRStoreRequired();
8531 bool isPPC64 = PPCSubTarget.isPPC64();
8532 bool isDarwinABI = PPCSubTarget.isDarwinABI();
8535 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8538 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8539 isPPC64? MVT::i64 : MVT::i32);
8540 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8541 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8543 MachinePointerInfo(), false, false, false, 0);
8546 // Just load the return address off the stack.
8547 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8548 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8549 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8552 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8553 SelectionDAG &DAG) const {
8555 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8557 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8558 bool isPPC64 = PtrVT == MVT::i64;
8560 MachineFunction &MF = DAG.getMachineFunction();
8561 MachineFrameInfo *MFI = MF.getFrameInfo();
8562 MFI->setFrameAddressIsTaken(true);
8564 // Naked functions never have a frame pointer, and so we use r1. For all
8565 // other functions, this decision must be delayed until during PEI.
8567 if (MF.getFunction()->getAttributes().hasAttribute(
8568 AttributeSet::FunctionIndex, Attribute::Naked))
8569 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8571 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8573 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8576 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8577 FrameAddr, MachinePointerInfo(), false, false,
8583 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8584 // The PowerPC target isn't yet aware of offsets.
8588 /// getOptimalMemOpType - Returns the target specific optimal type for load
8589 /// and store operations as a result of memset, memcpy, and memmove
8590 /// lowering. If DstAlign is zero that means it's safe to destination
8591 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8592 /// means there isn't a need to check it against alignment requirement,
8593 /// probably because the source does not need to be loaded. If 'IsMemset' is
8594 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8595 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8596 /// source is constant so it does not need to be loaded.
8597 /// It returns EVT::Other if the type should be determined using generic
8598 /// target-independent logic.
8599 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8600 unsigned DstAlign, unsigned SrcAlign,
8601 bool IsMemset, bool ZeroMemset,
8603 MachineFunction &MF) const {
8604 if (this->PPCSubTarget.isPPC64()) {
8611 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8614 if (DisablePPCUnaligned)
8617 // PowerPC supports unaligned memory access for simple non-vector types.
8618 // Although accessing unaligned addresses is not as efficient as accessing
8619 // aligned addresses, it is generally more efficient than manual expansion,
8620 // and generally only traps for software emulation when crossing page
8626 if (VT.getSimpleVT().isVector())
8629 if (VT == MVT::ppcf128)
8638 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8639 VT = VT.getScalarType();
8644 switch (VT.getSimpleVT().SimpleTy) {
8655 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
8656 if (DisableILPPref || PPCSubTarget.enableMachineScheduler())
8657 return TargetLowering::getSchedulingPreference(N);
8662 // Create a fast isel object.
8664 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
8665 const TargetLibraryInfo *LibInfo) const {
8666 return PPC::createFastISel(FuncInfo, LibInfo);