1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // PPCGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "ppcfastisel"
18 #include "MCTargetDesc/PPCPredicates.h"
19 #include "PPCISelLowering.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/IntrinsicInst.h"
34 #include "llvm/IR/Operator.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/GetElementPtrTypeIterator.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetMachine.h"
40 //===----------------------------------------------------------------------===//
43 // FastLowerArguments: Handle simple cases.
44 // PPCMaterializeGV: Handle TLS.
45 // SelectCall: Handle function pointers.
46 // SelectCall: Handle multi-register return values.
47 // SelectCall: Optimize away nops for local calls.
48 // processCallArgs: Handle bit-converted arguments.
49 // finishCall: Handle multi-register return values.
50 // PPCComputeAddress: Handle parameter references as FrameIndex's.
51 // PPCEmitCmp: Handle immediate as operand 1.
52 // SelectCall: Handle small byval arguments.
53 // SelectIntrinsicCall: Implement.
54 // SelectSelect: Implement.
55 // Consider factoring isTypeLegal into the base class.
56 // Implement switches and jump tables.
58 //===----------------------------------------------------------------------===//
63 typedef struct Address {
76 // Innocuous defaults for our address.
78 : BaseType(RegBase), Offset(0) {
83 class PPCFastISel : public FastISel {
85 const TargetMachine &TM;
86 const TargetInstrInfo &TII;
87 const TargetLowering &TLI;
88 const PPCSubtarget &PPCSubTarget;
92 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
93 const TargetLibraryInfo *LibInfo)
94 : FastISel(FuncInfo, LibInfo),
95 TM(FuncInfo.MF->getTarget()),
96 TII(*TM.getInstrInfo()),
97 TLI(*TM.getTargetLowering()),
99 *((static_cast<const PPCTargetMachine *>(&TM))->getSubtargetImpl())
101 Context(&FuncInfo.Fn->getContext()) { }
103 // Backend specific FastISel code.
105 virtual bool TargetSelectInstruction(const Instruction *I);
106 virtual unsigned TargetMaterializeConstant(const Constant *C);
107 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
108 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
110 virtual bool FastLowerArguments();
111 virtual unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm);
112 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
113 const TargetRegisterClass *RC,
114 unsigned Op0, bool Op0IsKill,
116 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
117 const TargetRegisterClass *RC,
118 unsigned Op0, bool Op0IsKill);
119 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
120 const TargetRegisterClass *RC,
121 unsigned Op0, bool Op0IsKill,
122 unsigned Op1, bool Op1IsKill);
124 // Instruction selection routines.
126 bool SelectLoad(const Instruction *I);
127 bool SelectStore(const Instruction *I);
128 bool SelectBranch(const Instruction *I);
129 bool SelectIndirectBr(const Instruction *I);
130 bool SelectCmp(const Instruction *I);
131 bool SelectFPExt(const Instruction *I);
132 bool SelectFPTrunc(const Instruction *I);
133 bool SelectIToFP(const Instruction *I, bool IsSigned);
134 bool SelectFPToI(const Instruction *I, bool IsSigned);
135 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
136 bool SelectCall(const Instruction *I);
137 bool SelectRet(const Instruction *I);
138 bool SelectTrunc(const Instruction *I);
139 bool SelectIntExt(const Instruction *I);
143 bool isTypeLegal(Type *Ty, MVT &VT);
144 bool isLoadTypeLegal(Type *Ty, MVT &VT);
145 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
146 bool isZExt, unsigned DestReg);
147 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
148 const TargetRegisterClass *RC, bool IsZExt = true,
149 unsigned FP64LoadOpc = PPC::LFD);
150 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
151 bool PPCComputeAddress(const Value *Obj, Address &Addr);
152 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
154 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
155 unsigned DestReg, bool IsZExt);
156 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
157 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
158 unsigned PPCMaterializeInt(const Constant *C, MVT VT);
159 unsigned PPCMaterialize32BitInt(int64_t Imm,
160 const TargetRegisterClass *RC);
161 unsigned PPCMaterialize64BitInt(int64_t Imm,
162 const TargetRegisterClass *RC);
163 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
164 unsigned SrcReg, bool IsSigned);
165 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
167 // Call handling routines.
169 bool processCallArgs(SmallVectorImpl<Value*> &Args,
170 SmallVectorImpl<unsigned> &ArgRegs,
171 SmallVectorImpl<MVT> &ArgVTs,
172 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
173 SmallVectorImpl<unsigned> &RegArgs,
177 void finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
178 const Instruction *I, CallingConv::ID CC,
179 unsigned &NumBytes, bool IsVarArg);
180 CCAssignFn *usePPC32CCs(unsigned Flag);
183 #include "PPCGenFastISel.inc"
187 } // end anonymous namespace
189 #include "PPCGenCallingConv.inc"
191 // Function whose sole purpose is to kill compiler warnings
192 // stemming from unused functions included from PPCGenCallingConv.inc.
193 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
195 return CC_PPC32_SVR4;
197 return CC_PPC32_SVR4_ByVal;
199 return CC_PPC32_SVR4_VarArg;
204 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
206 // These are not representable with any single compare.
207 case CmpInst::FCMP_FALSE:
208 case CmpInst::FCMP_UEQ:
209 case CmpInst::FCMP_UGT:
210 case CmpInst::FCMP_UGE:
211 case CmpInst::FCMP_ULT:
212 case CmpInst::FCMP_ULE:
213 case CmpInst::FCMP_UNE:
214 case CmpInst::FCMP_TRUE:
216 return Optional<PPC::Predicate>();
218 case CmpInst::FCMP_OEQ:
219 case CmpInst::ICMP_EQ:
222 case CmpInst::FCMP_OGT:
223 case CmpInst::ICMP_UGT:
224 case CmpInst::ICMP_SGT:
227 case CmpInst::FCMP_OGE:
228 case CmpInst::ICMP_UGE:
229 case CmpInst::ICMP_SGE:
232 case CmpInst::FCMP_OLT:
233 case CmpInst::ICMP_ULT:
234 case CmpInst::ICMP_SLT:
237 case CmpInst::FCMP_OLE:
238 case CmpInst::ICMP_ULE:
239 case CmpInst::ICMP_SLE:
242 case CmpInst::FCMP_ONE:
243 case CmpInst::ICMP_NE:
246 case CmpInst::FCMP_ORD:
249 case CmpInst::FCMP_UNO:
254 // Determine whether the type Ty is simple enough to be handled by
255 // fast-isel, and return its equivalent machine type in VT.
256 // FIXME: Copied directly from ARM -- factor into base class?
257 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
258 EVT Evt = TLI.getValueType(Ty, true);
260 // Only handle simple types.
261 if (Evt == MVT::Other || !Evt.isSimple()) return false;
262 VT = Evt.getSimpleVT();
264 // Handle all legal types, i.e. a register that will directly hold this
266 return TLI.isTypeLegal(VT);
269 // Determine whether the type Ty is simple enough to be handled by
270 // fast-isel as a load target, and return its equivalent machine type in VT.
271 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
272 if (isTypeLegal(Ty, VT)) return true;
274 // If this is a type than can be sign or zero-extended to a basic operation
275 // go ahead and accept it now.
276 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
283 // Given a value Obj, create an Address object Addr that represents its
284 // address. Return false if we can't handle it.
285 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
286 const User *U = NULL;
287 unsigned Opcode = Instruction::UserOp1;
288 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
289 // Don't walk into other basic blocks unless the object is an alloca from
290 // another block, otherwise it may not have a virtual register assigned.
291 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
292 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
293 Opcode = I->getOpcode();
296 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
297 Opcode = C->getOpcode();
304 case Instruction::BitCast:
305 // Look through bitcasts.
306 return PPCComputeAddress(U->getOperand(0), Addr);
307 case Instruction::IntToPtr:
308 // Look past no-op inttoptrs.
309 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
310 return PPCComputeAddress(U->getOperand(0), Addr);
312 case Instruction::PtrToInt:
313 // Look past no-op ptrtoints.
314 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
315 return PPCComputeAddress(U->getOperand(0), Addr);
317 case Instruction::GetElementPtr: {
318 Address SavedAddr = Addr;
319 long TmpOffset = Addr.Offset;
321 // Iterate through the GEP folding the constants into offsets where
323 gep_type_iterator GTI = gep_type_begin(U);
324 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
325 II != IE; ++II, ++GTI) {
326 const Value *Op = *II;
327 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
328 const StructLayout *SL = DL.getStructLayout(STy);
329 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
330 TmpOffset += SL->getElementOffset(Idx);
332 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
334 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
335 // Constant-offset addressing.
336 TmpOffset += CI->getSExtValue() * S;
339 if (canFoldAddIntoGEP(U, Op)) {
340 // A compatible add with a constant operand. Fold the constant.
342 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
343 TmpOffset += CI->getSExtValue() * S;
344 // Iterate on the other operand.
345 Op = cast<AddOperator>(Op)->getOperand(0);
349 goto unsupported_gep;
354 // Try to grab the base operand now.
355 Addr.Offset = TmpOffset;
356 if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
358 // We failed, restore everything and try the other options.
364 case Instruction::Alloca: {
365 const AllocaInst *AI = cast<AllocaInst>(Obj);
366 DenseMap<const AllocaInst*, int>::iterator SI =
367 FuncInfo.StaticAllocaMap.find(AI);
368 if (SI != FuncInfo.StaticAllocaMap.end()) {
369 Addr.BaseType = Address::FrameIndexBase;
370 Addr.Base.FI = SI->second;
377 // FIXME: References to parameters fall through to the behavior
378 // below. They should be able to reference a frame index since
379 // they are stored to the stack, so we can get "ld rx, offset(r1)"
380 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
381 // just contain the parameter. Try to handle this with a FI.
383 // Try to get this in a register if nothing else has worked.
384 if (Addr.Base.Reg == 0)
385 Addr.Base.Reg = getRegForValue(Obj);
387 // Prevent assignment of base register to X0, which is inappropriate
388 // for loads and stores alike.
389 if (Addr.Base.Reg != 0)
390 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
392 return Addr.Base.Reg != 0;
395 // Fix up some addresses that can't be used directly. For example, if
396 // an offset won't fit in an instruction field, we may need to move it
397 // into an index register.
398 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
399 unsigned &IndexReg) {
401 // Check whether the offset fits in the instruction field.
402 if (!isInt<16>(Addr.Offset))
405 // If this is a stack pointer and the offset needs to be simplified then
406 // put the alloca address into a register, set the base type back to
407 // register and continue. This should almost never happen.
408 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
409 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
410 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
411 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
412 Addr.Base.Reg = ResultReg;
413 Addr.BaseType = Address::RegBase;
417 IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context)
418 : Type::getInt64Ty(*Context));
419 const ConstantInt *Offset =
420 ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
421 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
422 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
426 // Emit a load instruction if possible, returning true if we succeeded,
427 // otherwise false. See commentary below for how the register class of
428 // the load is determined.
429 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
430 const TargetRegisterClass *RC,
431 bool IsZExt, unsigned FP64LoadOpc) {
433 bool UseOffset = true;
435 // If ResultReg is given, it determines the register class of the load.
436 // Otherwise, RC is the register class to use. If the result of the
437 // load isn't anticipated in this block, both may be zero, in which
438 // case we must make a conservative guess. In particular, don't assign
439 // R0 or X0 to the result register, as the result may be used in a load,
440 // store, add-immediate, or isel that won't permit this. (Though
441 // perhaps the spill and reload of live-exit values would handle this?)
442 const TargetRegisterClass *UseRC =
443 (ResultReg ? MRI.getRegClass(ResultReg) :
445 (VT == MVT::f64 ? &PPC::F8RCRegClass :
446 (VT == MVT::f32 ? &PPC::F4RCRegClass :
447 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
448 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
450 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
452 switch (VT.SimpleTy) {
453 default: // e.g., vector types not handled
456 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
460 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) :
461 (Is32BitInt ? PPC::LHA : PPC::LHA8));
465 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) :
466 (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
467 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
472 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
473 "64-bit load with 32-bit target??");
474 UseOffset = ((Addr.Offset & 3) == 0);
484 // If necessary, materialize the offset into a register and use
485 // the indexed form. Also handle stack pointers with special needs.
486 unsigned IndexReg = 0;
487 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
489 ResultReg = createResultReg(UseRC);
491 // Note: If we still have a frame index here, we know the offset is
492 // in range, as otherwise PPCSimplifyAddress would have converted it
494 if (Addr.BaseType == Address::FrameIndexBase) {
496 MachineMemOperand *MMO =
497 FuncInfo.MF->getMachineMemOperand(
498 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
499 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
500 MFI.getObjectAlignment(Addr.Base.FI));
502 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
503 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
505 // Base reg with offset in range.
506 } else if (UseOffset) {
508 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
509 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
513 // Get the RR opcode corresponding to the RI one. FIXME: It would be
514 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
515 // is hard to get at.
517 default: llvm_unreachable("Unexpected opcode!");
518 case PPC::LBZ: Opc = PPC::LBZX; break;
519 case PPC::LBZ8: Opc = PPC::LBZX8; break;
520 case PPC::LHZ: Opc = PPC::LHZX; break;
521 case PPC::LHZ8: Opc = PPC::LHZX8; break;
522 case PPC::LHA: Opc = PPC::LHAX; break;
523 case PPC::LHA8: Opc = PPC::LHAX8; break;
524 case PPC::LWZ: Opc = PPC::LWZX; break;
525 case PPC::LWZ8: Opc = PPC::LWZX8; break;
526 case PPC::LWA: Opc = PPC::LWAX; break;
527 case PPC::LWA_32: Opc = PPC::LWAX_32; break;
528 case PPC::LD: Opc = PPC::LDX; break;
529 case PPC::LFS: Opc = PPC::LFSX; break;
530 case PPC::LFD: Opc = PPC::LFDX; break;
532 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
533 .addReg(Addr.Base.Reg).addReg(IndexReg);
539 // Attempt to fast-select a load instruction.
540 bool PPCFastISel::SelectLoad(const Instruction *I) {
541 // FIXME: No atomic loads are supported.
542 if (cast<LoadInst>(I)->isAtomic())
545 // Verify we have a legal type before going any further.
547 if (!isLoadTypeLegal(I->getType(), VT))
550 // See if we can handle this address.
552 if (!PPCComputeAddress(I->getOperand(0), Addr))
555 // Look at the currently assigned register for this instruction
556 // to determine the required register class. This is necessary
557 // to constrain RA from using R0/X0 when this is not legal.
558 unsigned AssignedReg = FuncInfo.ValueMap[I];
559 const TargetRegisterClass *RC =
560 AssignedReg ? MRI.getRegClass(AssignedReg) : 0;
562 unsigned ResultReg = 0;
563 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
565 UpdateValueMap(I, ResultReg);
569 // Emit a store instruction to store SrcReg at Addr.
570 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
571 assert(SrcReg && "Nothing to store!");
573 bool UseOffset = true;
575 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
576 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
578 switch (VT.SimpleTy) {
579 default: // e.g., vector types not handled
582 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
585 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
588 assert(Is32BitInt && "Not GPRC for i32??");
593 UseOffset = ((Addr.Offset & 3) == 0);
603 // If necessary, materialize the offset into a register and use
604 // the indexed form. Also handle stack pointers with special needs.
605 unsigned IndexReg = 0;
606 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
608 // Note: If we still have a frame index here, we know the offset is
609 // in range, as otherwise PPCSimplifyAddress would have converted it
611 if (Addr.BaseType == Address::FrameIndexBase) {
612 MachineMemOperand *MMO =
613 FuncInfo.MF->getMachineMemOperand(
614 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
615 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
616 MFI.getObjectAlignment(Addr.Base.FI));
618 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
621 .addFrameIndex(Addr.Base.FI)
624 // Base reg with offset in range.
625 } else if (UseOffset)
626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
627 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
631 // Get the RR opcode corresponding to the RI one. FIXME: It would be
632 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
633 // is hard to get at.
635 default: llvm_unreachable("Unexpected opcode!");
636 case PPC::STB: Opc = PPC::STBX; break;
637 case PPC::STH : Opc = PPC::STHX; break;
638 case PPC::STW : Opc = PPC::STWX; break;
639 case PPC::STB8: Opc = PPC::STBX8; break;
640 case PPC::STH8: Opc = PPC::STHX8; break;
641 case PPC::STW8: Opc = PPC::STWX8; break;
642 case PPC::STD: Opc = PPC::STDX; break;
643 case PPC::STFS: Opc = PPC::STFSX; break;
644 case PPC::STFD: Opc = PPC::STFDX; break;
646 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
647 .addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg);
653 // Attempt to fast-select a store instruction.
654 bool PPCFastISel::SelectStore(const Instruction *I) {
655 Value *Op0 = I->getOperand(0);
658 // FIXME: No atomics loads are supported.
659 if (cast<StoreInst>(I)->isAtomic())
662 // Verify we have a legal type before going any further.
664 if (!isLoadTypeLegal(Op0->getType(), VT))
667 // Get the value to be stored into a register.
668 SrcReg = getRegForValue(Op0);
672 // See if we can handle this address.
674 if (!PPCComputeAddress(I->getOperand(1), Addr))
677 if (!PPCEmitStore(VT, SrcReg, Addr))
683 // Attempt to fast-select a branch instruction.
684 bool PPCFastISel::SelectBranch(const Instruction *I) {
685 const BranchInst *BI = cast<BranchInst>(I);
686 MachineBasicBlock *BrBB = FuncInfo.MBB;
687 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
688 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
690 // For now, just try the simplest case where it's fed by a compare.
691 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
692 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
696 PPC::Predicate PPCPred = OptPPCPred.getValue();
698 // Take advantage of fall-through opportunities.
699 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
701 PPCPred = PPC::InvertPredicate(PPCPred);
704 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
706 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
710 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
711 .addImm(PPCPred).addReg(CondReg).addMBB(TBB);
712 FastEmitBranch(FBB, DbgLoc);
713 FuncInfo.MBB->addSuccessor(TBB);
716 } else if (const ConstantInt *CI =
717 dyn_cast<ConstantInt>(BI->getCondition())) {
718 uint64_t Imm = CI->getZExtValue();
719 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
720 FastEmitBranch(Target, DbgLoc);
724 // FIXME: ARM looks for a case where the block containing the compare
725 // has been split from the block containing the branch. If this happens,
726 // there is a vreg available containing the result of the compare. I'm
727 // not sure we can do much, as we've lost the predicate information with
728 // the compare instruction -- we have a 4-bit CR but don't know which bit
733 // Attempt to emit a compare of the two source values. Signed and unsigned
734 // comparisons are supported. Return false if we can't handle it.
735 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
736 bool IsZExt, unsigned DestReg) {
737 Type *Ty = SrcValue1->getType();
738 EVT SrcEVT = TLI.getValueType(Ty, true);
739 if (!SrcEVT.isSimple())
741 MVT SrcVT = SrcEVT.getSimpleVT();
743 if (SrcVT == MVT::i1 && PPCSubTarget.useCRBits())
746 // See if operand 2 is an immediate encodeable in the compare.
747 // FIXME: Operands are not in canonical order at -O0, so an immediate
748 // operand in position 1 is a lost opportunity for now. We are
749 // similar to ARM in this regard.
753 // Only 16-bit integer constants can be represented in compares for
754 // PowerPC. Others will be materialized into a register.
755 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
756 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
757 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
758 const APInt &CIVal = ConstInt->getValue();
759 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
760 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
766 bool NeedsExt = false;
767 switch (SrcVT.SimpleTy) {
768 default: return false;
770 CmpOpc = PPC::FCMPUS;
773 CmpOpc = PPC::FCMPUD;
779 // Intentional fall-through.
782 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
784 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
788 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
790 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
794 unsigned SrcReg1 = getRegForValue(SrcValue1);
798 unsigned SrcReg2 = 0;
800 SrcReg2 = getRegForValue(SrcValue2);
806 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
807 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
812 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
813 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
820 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
821 .addReg(SrcReg1).addReg(SrcReg2);
823 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
824 .addReg(SrcReg1).addImm(Imm);
829 // Attempt to fast-select a floating-point extend instruction.
830 bool PPCFastISel::SelectFPExt(const Instruction *I) {
831 Value *Src = I->getOperand(0);
832 EVT SrcVT = TLI.getValueType(Src->getType(), true);
833 EVT DestVT = TLI.getValueType(I->getType(), true);
835 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
838 unsigned SrcReg = getRegForValue(Src);
842 // No code is generated for a FP extend.
843 UpdateValueMap(I, SrcReg);
847 // Attempt to fast-select a floating-point truncate instruction.
848 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
849 Value *Src = I->getOperand(0);
850 EVT SrcVT = TLI.getValueType(Src->getType(), true);
851 EVT DestVT = TLI.getValueType(I->getType(), true);
853 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
856 unsigned SrcReg = getRegForValue(Src);
860 // Round the result to single precision.
861 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
862 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
865 UpdateValueMap(I, DestReg);
869 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
870 // FIXME: When direct register moves are implemented (see PowerISA 2.08),
871 // those should be used instead of moving via a stack slot when the
872 // subtarget permits.
873 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
874 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
875 // case to 8 bytes which produces tighter code but wastes stack space.
876 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
879 // If necessary, extend 32-bit int to 64-bit.
880 if (SrcVT == MVT::i32) {
881 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
882 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
887 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
889 Addr.BaseType = Address::FrameIndexBase;
890 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
892 // Store the value from the GPR.
893 if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
896 // Load the integer value into an FPR. The kind of load used depends
897 // on a number of conditions.
898 unsigned LoadOpc = PPC::LFD;
900 if (SrcVT == MVT::i32) {
903 LoadOpc = PPC::LFIWZX;
904 else if (PPCSubTarget.hasLFIWAX())
905 LoadOpc = PPC::LFIWAX;
908 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
909 unsigned ResultReg = 0;
910 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
916 // Attempt to fast-select an integer-to-floating-point conversion.
917 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
919 Type *DstTy = I->getType();
920 if (!isTypeLegal(DstTy, DstVT))
923 if (DstVT != MVT::f32 && DstVT != MVT::f64)
926 Value *Src = I->getOperand(0);
927 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
928 if (!SrcEVT.isSimple())
931 MVT SrcVT = SrcEVT.getSimpleVT();
933 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
934 SrcVT != MVT::i32 && SrcVT != MVT::i64)
937 unsigned SrcReg = getRegForValue(Src);
941 // We can only lower an unsigned convert if we have the newer
942 // floating-point conversion operations.
943 if (!IsSigned && !PPCSubTarget.hasFPCVT())
946 // FIXME: For now we require the newer floating-point conversion operations
947 // (which are present only on P7 and A2 server models) when converting
948 // to single-precision float. Otherwise we have to generate a lot of
949 // fiddly code to avoid double rounding. If necessary, the fiddly code
950 // can be found in PPCTargetLowering::LowerINT_TO_FP().
951 if (DstVT == MVT::f32 && !PPCSubTarget.hasFPCVT())
954 // Extend the input if necessary.
955 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
956 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
957 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
963 // Move the integer value to an FPR.
964 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
968 // Determine the opcode for the conversion.
969 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
970 unsigned DestReg = createResultReg(RC);
973 if (DstVT == MVT::f32)
974 Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
976 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
978 // Generate the convert.
979 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
982 UpdateValueMap(I, DestReg);
986 // Move the floating-point value in SrcReg into an integer destination
987 // register, and return the register (or zero if we can't handle it).
988 // FIXME: When direct register moves are implemented (see PowerISA 2.08),
989 // those should be used instead of moving via a stack slot when the
990 // subtarget permits.
991 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
992 unsigned SrcReg, bool IsSigned) {
993 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
994 // Note that if have STFIWX available, we could use a 4-byte stack
995 // slot for i32, but this being fast-isel we'll just go with the
996 // easiest code gen possible.
998 Addr.BaseType = Address::FrameIndexBase;
999 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1001 // Store the value from the FPR.
1002 if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1005 // Reload it into a GPR. If we want an i32, modify the address
1006 // to have a 4-byte offset so we load from the right place.
1010 // Look at the currently assigned register for this instruction
1011 // to determine the required register class.
1012 unsigned AssignedReg = FuncInfo.ValueMap[I];
1013 const TargetRegisterClass *RC =
1014 AssignedReg ? MRI.getRegClass(AssignedReg) : 0;
1016 unsigned ResultReg = 0;
1017 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1023 // Attempt to fast-select a floating-point-to-integer conversion.
1024 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1026 Type *DstTy = I->getType();
1027 if (!isTypeLegal(DstTy, DstVT))
1030 if (DstVT != MVT::i32 && DstVT != MVT::i64)
1033 Value *Src = I->getOperand(0);
1034 Type *SrcTy = Src->getType();
1035 if (!isTypeLegal(SrcTy, SrcVT))
1038 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1041 unsigned SrcReg = getRegForValue(Src);
1045 // Convert f32 to f64 if necessary. This is just a meaningless copy
1046 // to get the register class right. COPY_TO_REGCLASS is needed since
1047 // a COPY from F4RC to F8RC is converted to a F4RC-F4RC copy downstream.
1048 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1049 if (InRC == &PPC::F4RCRegClass) {
1050 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1051 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1052 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg)
1053 .addReg(SrcReg).addImm(PPC::F8RCRegClassID);
1057 // Determine the opcode for the conversion, which takes place
1058 // entirely within FPRs.
1059 unsigned DestReg = createResultReg(&PPC::F8RCRegClass);
1062 if (DstVT == MVT::i32)
1066 Opc = PPCSubTarget.hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1068 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1070 // Generate the convert.
1071 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1074 // Now move the integer value from a float register to an integer register.
1075 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1079 UpdateValueMap(I, IntReg);
1083 // Attempt to fast-select a binary integer operation that isn't already
1084 // handled automatically.
1085 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1086 EVT DestVT = TLI.getValueType(I->getType(), true);
1088 // We can get here in the case when we have a binary operation on a non-legal
1089 // type and the target independent selector doesn't know how to handle it.
1090 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1093 // Look at the currently assigned register for this instruction
1094 // to determine the required register class. If there is no register,
1095 // make a conservative choice (don't assign R0).
1096 unsigned AssignedReg = FuncInfo.ValueMap[I];
1097 const TargetRegisterClass *RC =
1098 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1099 &PPC::GPRC_and_GPRC_NOR0RegClass);
1100 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1103 switch (ISDOpcode) {
1104 default: return false;
1106 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1109 Opc = IsGPRC ? PPC::OR : PPC::OR8;
1112 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1116 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1117 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1118 if (SrcReg1 == 0) return false;
1120 // Handle case of small immediate operand.
1121 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1122 const APInt &CIVal = ConstInt->getValue();
1123 int Imm = (int)CIVal.getSExtValue();
1125 if (isInt<16>(Imm)) {
1128 llvm_unreachable("Missing case!");
1131 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1135 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1148 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1157 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1164 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1168 UpdateValueMap(I, ResultReg);
1175 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1176 if (SrcReg2 == 0) return false;
1178 // Reverse operands for subtract-from.
1179 if (ISDOpcode == ISD::SUB)
1180 std::swap(SrcReg1, SrcReg2);
1182 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1183 .addReg(SrcReg1).addReg(SrcReg2);
1184 UpdateValueMap(I, ResultReg);
1188 // Handle arguments to a call that we're attempting to fast-select.
1189 // Return false if the arguments are too complex for us at the moment.
1190 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1191 SmallVectorImpl<unsigned> &ArgRegs,
1192 SmallVectorImpl<MVT> &ArgVTs,
1193 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1194 SmallVectorImpl<unsigned> &RegArgs,
1198 SmallVector<CCValAssign, 16> ArgLocs;
1199 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1200 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1202 // Bail out if we can't handle any of the arguments.
1203 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1204 CCValAssign &VA = ArgLocs[I];
1205 MVT ArgVT = ArgVTs[VA.getValNo()];
1207 // Skip vector arguments for now, as well as long double and
1208 // uint128_t, and anything that isn't passed in a register.
1209 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1210 !VA.isRegLoc() || VA.needsCustom())
1213 // Skip bit-converted arguments for now.
1214 if (VA.getLocInfo() == CCValAssign::BCvt)
1218 // Get a count of how many bytes are to be pushed onto the stack.
1219 NumBytes = CCInfo.getNextStackOffset();
1221 // Issue CALLSEQ_START.
1222 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1223 TII.get(TII.getCallFrameSetupOpcode()))
1226 // Prepare to assign register arguments. Every argument uses up a
1227 // GPR protocol register even if it's passed in a floating-point
1229 unsigned NextGPR = PPC::X3;
1230 unsigned NextFPR = PPC::F1;
1232 // Process arguments.
1233 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1234 CCValAssign &VA = ArgLocs[I];
1235 unsigned Arg = ArgRegs[VA.getValNo()];
1236 MVT ArgVT = ArgVTs[VA.getValNo()];
1238 // Handle argument promotion and bitcasts.
1239 switch (VA.getLocInfo()) {
1241 llvm_unreachable("Unknown loc info!");
1242 case CCValAssign::Full:
1244 case CCValAssign::SExt: {
1245 MVT DestVT = VA.getLocVT();
1246 const TargetRegisterClass *RC =
1247 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1248 unsigned TmpReg = createResultReg(RC);
1249 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1250 llvm_unreachable("Failed to emit a sext!");
1255 case CCValAssign::AExt:
1256 case CCValAssign::ZExt: {
1257 MVT DestVT = VA.getLocVT();
1258 const TargetRegisterClass *RC =
1259 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1260 unsigned TmpReg = createResultReg(RC);
1261 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1262 llvm_unreachable("Failed to emit a zext!");
1267 case CCValAssign::BCvt: {
1268 // FIXME: Not yet handled.
1269 llvm_unreachable("Should have bailed before getting here!");
1274 // Copy this argument to the appropriate register.
1276 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1282 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1283 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1284 RegArgs.push_back(ArgReg);
1290 // For a call that we've determined we can fast-select, finish the
1291 // call sequence and generate a copy to obtain the return value (if any).
1292 void PPCFastISel::finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1293 const Instruction *I, CallingConv::ID CC,
1294 unsigned &NumBytes, bool IsVarArg) {
1295 // Issue CallSEQ_END.
1296 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1297 TII.get(TII.getCallFrameDestroyOpcode()))
1298 .addImm(NumBytes).addImm(0);
1300 // Next, generate a copy to obtain the return value.
1301 // FIXME: No multi-register return values yet, though I don't foresee
1302 // any real difficulties there.
1303 if (RetVT != MVT::isVoid) {
1304 SmallVector<CCValAssign, 16> RVLocs;
1305 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
1306 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1307 CCValAssign &VA = RVLocs[0];
1308 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1309 assert(VA.isRegLoc() && "Can only return in registers!");
1311 MVT DestVT = VA.getValVT();
1312 MVT CopyVT = DestVT;
1314 // Ints smaller than a register still arrive in a full 64-bit
1315 // register, so make sure we recognize this.
1316 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1319 unsigned SourcePhysReg = VA.getLocReg();
1320 unsigned ResultReg = 0;
1322 if (RetVT == CopyVT) {
1323 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1324 ResultReg = createResultReg(CpyRC);
1326 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1327 TII.get(TargetOpcode::COPY), ResultReg)
1328 .addReg(SourcePhysReg);
1330 // If necessary, round the floating result to single precision.
1331 } else if (CopyVT == MVT::f64) {
1332 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1333 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1334 ResultReg).addReg(SourcePhysReg);
1336 // If only the low half of a general register is needed, generate
1337 // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1338 // used along the fast-isel path (not lowered), and downstream logic
1339 // also doesn't like a direct subreg copy on a physical reg.)
1340 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1341 ResultReg = createResultReg(&PPC::GPRCRegClass);
1342 // Convert physical register from G8RC to GPRC.
1343 SourcePhysReg -= PPC::X0 - PPC::R0;
1344 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1345 TII.get(TargetOpcode::COPY), ResultReg)
1346 .addReg(SourcePhysReg);
1349 assert(ResultReg && "ResultReg unset!");
1350 UsedRegs.push_back(SourcePhysReg);
1351 UpdateValueMap(I, ResultReg);
1355 // Attempt to fast-select a call instruction.
1356 bool PPCFastISel::SelectCall(const Instruction *I) {
1357 const CallInst *CI = cast<CallInst>(I);
1358 const Value *Callee = CI->getCalledValue();
1360 // Can't handle inline asm.
1361 if (isa<InlineAsm>(Callee))
1364 // Allow SelectionDAG isel to handle tail calls.
1365 if (CI->isTailCall())
1368 // Obtain calling convention.
1369 ImmutableCallSite CS(CI);
1370 CallingConv::ID CC = CS.getCallingConv();
1372 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1373 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1374 bool IsVarArg = FTy->isVarArg();
1376 // Not ready for varargs yet.
1380 // Handle simple calls for now, with legal return types and
1381 // those that can be extended.
1382 Type *RetTy = I->getType();
1384 if (RetTy->isVoidTy())
1385 RetVT = MVT::isVoid;
1386 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1390 // FIXME: No multi-register return values yet.
1391 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1392 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1393 RetVT != MVT::f64) {
1394 SmallVector<CCValAssign, 16> RVLocs;
1395 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
1396 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1397 if (RVLocs.size() > 1)
1401 // Bail early if more than 8 arguments, as we only currently
1402 // handle arguments passed in registers.
1403 unsigned NumArgs = CS.arg_size();
1407 // Set up the argument vectors.
1408 SmallVector<Value*, 8> Args;
1409 SmallVector<unsigned, 8> ArgRegs;
1410 SmallVector<MVT, 8> ArgVTs;
1411 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1413 Args.reserve(NumArgs);
1414 ArgRegs.reserve(NumArgs);
1415 ArgVTs.reserve(NumArgs);
1416 ArgFlags.reserve(NumArgs);
1418 for (ImmutableCallSite::arg_iterator II = CS.arg_begin(), IE = CS.arg_end();
1420 // FIXME: ARM does something for intrinsic calls here, check into that.
1422 unsigned AttrIdx = II - CS.arg_begin() + 1;
1424 // Only handle easy calls for now. It would be reasonably easy
1425 // to handle <= 8-byte structures passed ByVal in registers, but we
1426 // have to ensure they are right-justified in the register.
1427 if (CS.paramHasAttr(AttrIdx, Attribute::InReg) ||
1428 CS.paramHasAttr(AttrIdx, Attribute::StructRet) ||
1429 CS.paramHasAttr(AttrIdx, Attribute::Nest) ||
1430 CS.paramHasAttr(AttrIdx, Attribute::ByVal))
1433 ISD::ArgFlagsTy Flags;
1434 if (CS.paramHasAttr(AttrIdx, Attribute::SExt))
1436 if (CS.paramHasAttr(AttrIdx, Attribute::ZExt))
1439 Type *ArgTy = (*II)->getType();
1441 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1444 if (ArgVT.isVector())
1447 unsigned Arg = getRegForValue(*II);
1451 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
1452 Flags.setOrigAlign(OriginalAlignment);
1454 Args.push_back(*II);
1455 ArgRegs.push_back(Arg);
1456 ArgVTs.push_back(ArgVT);
1457 ArgFlags.push_back(Flags);
1460 // Process the arguments.
1461 SmallVector<unsigned, 8> RegArgs;
1464 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1465 RegArgs, CC, NumBytes, IsVarArg))
1468 // FIXME: No handling for function pointers yet. This requires
1469 // implementing the function descriptor (OPD) setup.
1470 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1474 // Build direct call with NOP for TOC restore.
1475 // FIXME: We can and should optimize away the NOP for local calls.
1476 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1477 TII.get(PPC::BL8_NOP));
1479 MIB.addGlobalAddress(GV);
1481 // Add implicit physical register uses to the call.
1482 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1483 MIB.addReg(RegArgs[II], RegState::Implicit);
1485 // Add a register mask with the call-preserved registers. Proper
1486 // defs for return values will be added by setPhysRegsDeadExcept().
1487 MIB.addRegMask(TRI.getCallPreservedMask(CC));
1489 // Finish off the call including any return values.
1490 SmallVector<unsigned, 4> UsedRegs;
1491 finishCall(RetVT, UsedRegs, I, CC, NumBytes, IsVarArg);
1493 // Set all unused physregs defs as dead.
1494 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1499 // Attempt to fast-select a return instruction.
1500 bool PPCFastISel::SelectRet(const Instruction *I) {
1502 if (!FuncInfo.CanLowerReturn)
1505 const ReturnInst *Ret = cast<ReturnInst>(I);
1506 const Function &F = *I->getParent()->getParent();
1508 // Build a list of return value registers.
1509 SmallVector<unsigned, 4> RetRegs;
1510 CallingConv::ID CC = F.getCallingConv();
1512 if (Ret->getNumOperands() > 0) {
1513 SmallVector<ISD::OutputArg, 4> Outs;
1514 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1516 // Analyze operands of the call, assigning locations to each operand.
1517 SmallVector<CCValAssign, 16> ValLocs;
1518 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, *Context);
1519 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1520 const Value *RV = Ret->getOperand(0);
1522 // FIXME: Only one output register for now.
1523 if (ValLocs.size() > 1)
1526 // Special case for returning a constant integer of any size.
1527 // Materialize the constant as an i64 and copy it to the return
1528 // register. This avoids an unnecessary extend or truncate.
1529 if (isa<ConstantInt>(*RV)) {
1530 const Constant *C = cast<Constant>(RV);
1531 unsigned SrcReg = PPCMaterializeInt(C, MVT::i64);
1532 unsigned RetReg = ValLocs[0].getLocReg();
1533 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1534 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1535 RetRegs.push_back(RetReg);
1538 unsigned Reg = getRegForValue(RV);
1543 // Copy the result values into the output registers.
1544 for (unsigned i = 0; i < ValLocs.size(); ++i) {
1546 CCValAssign &VA = ValLocs[i];
1547 assert(VA.isRegLoc() && "Can only return in registers!");
1548 RetRegs.push_back(VA.getLocReg());
1549 unsigned SrcReg = Reg + VA.getValNo();
1551 EVT RVEVT = TLI.getValueType(RV->getType());
1552 if (!RVEVT.isSimple())
1554 MVT RVVT = RVEVT.getSimpleVT();
1555 MVT DestVT = VA.getLocVT();
1557 if (RVVT != DestVT && RVVT != MVT::i8 &&
1558 RVVT != MVT::i16 && RVVT != MVT::i32)
1561 if (RVVT != DestVT) {
1562 switch (VA.getLocInfo()) {
1564 llvm_unreachable("Unknown loc info!");
1565 case CCValAssign::Full:
1566 llvm_unreachable("Full value assign but types don't match?");
1567 case CCValAssign::AExt:
1568 case CCValAssign::ZExt: {
1569 const TargetRegisterClass *RC =
1570 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1571 unsigned TmpReg = createResultReg(RC);
1572 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1577 case CCValAssign::SExt: {
1578 const TargetRegisterClass *RC =
1579 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1580 unsigned TmpReg = createResultReg(RC);
1581 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1589 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1590 TII.get(TargetOpcode::COPY), RetRegs[i])
1596 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1599 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1600 MIB.addReg(RetRegs[i], RegState::Implicit);
1605 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1606 // signed and zero extensions are supported. Return false if we
1608 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1609 unsigned DestReg, bool IsZExt) {
1610 if (DestVT != MVT::i32 && DestVT != MVT::i64)
1612 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1615 // Signed extensions use EXTSB, EXTSH, EXTSW.
1618 if (SrcVT == MVT::i8)
1619 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1620 else if (SrcVT == MVT::i16)
1621 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1623 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1624 Opc = PPC::EXTSW_32_64;
1626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1629 // Unsigned 32-bit extensions use RLWINM.
1630 } else if (DestVT == MVT::i32) {
1632 if (SrcVT == MVT::i8)
1635 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1638 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1640 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1642 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1645 if (SrcVT == MVT::i8)
1647 else if (SrcVT == MVT::i16)
1651 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1652 TII.get(PPC::RLDICL_32_64), DestReg)
1653 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1659 // Attempt to fast-select an indirect branch instruction.
1660 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1661 unsigned AddrReg = getRegForValue(I->getOperand(0));
1665 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1667 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
1669 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1670 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1671 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1676 // Attempt to fast-select an integer truncate instruction.
1677 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1678 Value *Src = I->getOperand(0);
1679 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1680 EVT DestVT = TLI.getValueType(I->getType(), true);
1682 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1685 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1688 unsigned SrcReg = getRegForValue(Src);
1692 // The only interesting case is when we need to switch register classes.
1693 if (SrcVT == MVT::i64) {
1694 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1695 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1696 TII.get(TargetOpcode::COPY),
1697 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1701 UpdateValueMap(I, SrcReg);
1705 // Attempt to fast-select an integer extend instruction.
1706 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1707 Type *DestTy = I->getType();
1708 Value *Src = I->getOperand(0);
1709 Type *SrcTy = Src->getType();
1711 bool IsZExt = isa<ZExtInst>(I);
1712 unsigned SrcReg = getRegForValue(Src);
1713 if (!SrcReg) return false;
1715 EVT SrcEVT, DestEVT;
1716 SrcEVT = TLI.getValueType(SrcTy, true);
1717 DestEVT = TLI.getValueType(DestTy, true);
1718 if (!SrcEVT.isSimple())
1720 if (!DestEVT.isSimple())
1723 MVT SrcVT = SrcEVT.getSimpleVT();
1724 MVT DestVT = DestEVT.getSimpleVT();
1726 // If we know the register class needed for the result of this
1727 // instruction, use it. Otherwise pick the register class of the
1728 // correct size that does not contain X0/R0, since we don't know
1729 // whether downstream uses permit that assignment.
1730 unsigned AssignedReg = FuncInfo.ValueMap[I];
1731 const TargetRegisterClass *RC =
1732 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1733 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1734 &PPC::GPRC_and_GPRC_NOR0RegClass));
1735 unsigned ResultReg = createResultReg(RC);
1737 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1740 UpdateValueMap(I, ResultReg);
1744 // Attempt to fast-select an instruction that wasn't handled by
1745 // the table-generated machinery.
1746 bool PPCFastISel::TargetSelectInstruction(const Instruction *I) {
1748 switch (I->getOpcode()) {
1749 case Instruction::Load:
1750 return SelectLoad(I);
1751 case Instruction::Store:
1752 return SelectStore(I);
1753 case Instruction::Br:
1754 return SelectBranch(I);
1755 case Instruction::IndirectBr:
1756 return SelectIndirectBr(I);
1757 case Instruction::FPExt:
1758 return SelectFPExt(I);
1759 case Instruction::FPTrunc:
1760 return SelectFPTrunc(I);
1761 case Instruction::SIToFP:
1762 return SelectIToFP(I, /*IsSigned*/ true);
1763 case Instruction::UIToFP:
1764 return SelectIToFP(I, /*IsSigned*/ false);
1765 case Instruction::FPToSI:
1766 return SelectFPToI(I, /*IsSigned*/ true);
1767 case Instruction::FPToUI:
1768 return SelectFPToI(I, /*IsSigned*/ false);
1769 case Instruction::Add:
1770 return SelectBinaryIntOp(I, ISD::ADD);
1771 case Instruction::Or:
1772 return SelectBinaryIntOp(I, ISD::OR);
1773 case Instruction::Sub:
1774 return SelectBinaryIntOp(I, ISD::SUB);
1775 case Instruction::Call:
1776 if (dyn_cast<IntrinsicInst>(I))
1778 return SelectCall(I);
1779 case Instruction::Ret:
1780 return SelectRet(I);
1781 case Instruction::Trunc:
1782 return SelectTrunc(I);
1783 case Instruction::ZExt:
1784 case Instruction::SExt:
1785 return SelectIntExt(I);
1786 // Here add other flavors of Instruction::XXX that automated
1787 // cases don't catch. For example, switches are terminators
1788 // that aren't yet handled.
1795 // Materialize a floating-point constant into a register, and return
1796 // the register number (or zero if we failed to handle it).
1797 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1798 // No plans to handle long double here.
1799 if (VT != MVT::f32 && VT != MVT::f64)
1802 // All FP constants are loaded from the constant pool.
1803 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
1804 assert(Align > 0 && "Unexpectedly missing alignment information!");
1805 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1806 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
1807 CodeModel::Model CModel = TM.getCodeModel();
1809 MachineMemOperand *MMO =
1810 FuncInfo.MF->getMachineMemOperand(
1811 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
1812 (VT == MVT::f32) ? 4 : 8, Align);
1814 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
1815 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1817 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
1818 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
1819 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
1821 .addConstantPoolIndex(Idx).addReg(PPC::X2);
1822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1823 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
1825 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
1826 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1827 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
1828 // But for large code model, we must generate a LDtocL followed
1830 if (CModel == CodeModel::Large) {
1831 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1832 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1833 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
1834 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1835 .addImm(0).addReg(TmpReg2);
1837 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1838 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
1840 .addMemOperand(MMO);
1846 // Materialize the address of a global value into a register, and return
1847 // the register number (or zero if we failed to handle it).
1848 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
1849 assert(VT == MVT::i64 && "Non-address!");
1850 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
1851 unsigned DestReg = createResultReg(RC);
1853 // Global values may be plain old object addresses, TLS object
1854 // addresses, constant pool entries, or jump tables. How we generate
1855 // code for these may depend on small, medium, or large code model.
1856 CodeModel::Model CModel = TM.getCodeModel();
1858 // FIXME: Jump tables are not yet required because fast-isel doesn't
1859 // handle switches; if that changes, we need them as well. For now,
1860 // what follows assumes everything's a generic (or TLS) global address.
1861 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
1863 // If GV is an alias, use the aliasee for determining thread-locality.
1864 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
1865 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false));
1868 // FIXME: We don't yet handle the complexity of TLS.
1869 bool IsTLS = GVar && GVar->isThreadLocal();
1873 // For small code model, generate a simple TOC load.
1874 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
1875 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
1877 .addGlobalAddress(GV)
1880 // If the address is an externally defined symbol, a symbol with
1881 // common or externally available linkage, a function address, or a
1882 // jump table address (not yet needed), or if we are generating code
1883 // for large code model, we generate:
1884 // LDtocL(GV, ADDIStocHA(%X2, GV))
1885 // Otherwise we generate:
1886 // ADDItocL(ADDIStocHA(%X2, GV), GV)
1887 // Either way, start with the ADDIStocHA:
1888 unsigned HighPartReg = createResultReg(RC);
1889 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1890 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
1892 // !GVar implies a function address. An external variable is one
1893 // without an initializer.
1894 // If/when switches are implemented, jump tables should be handled
1895 // on the "if" path here.
1896 if (CModel == CodeModel::Large || !GVar || !GVar->hasInitializer() ||
1897 GVar->hasCommonLinkage() || GVar->hasAvailableExternallyLinkage())
1898 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1899 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
1901 // Otherwise generate the ADDItocL.
1902 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
1903 DestReg).addReg(HighPartReg).addGlobalAddress(GV);
1909 // Materialize a 32-bit integer constant into a register, and return
1910 // the register number (or zero if we failed to handle it).
1911 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
1912 const TargetRegisterClass *RC) {
1913 unsigned Lo = Imm & 0xFFFF;
1914 unsigned Hi = (Imm >> 16) & 0xFFFF;
1916 unsigned ResultReg = createResultReg(RC);
1917 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1920 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1921 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
1924 // Both Lo and Hi have nonzero bits.
1925 unsigned TmpReg = createResultReg(RC);
1926 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1927 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
1929 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1930 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
1931 .addReg(TmpReg).addImm(Lo);
1934 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1935 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
1941 // Materialize a 64-bit integer constant into a register, and return
1942 // the register number (or zero if we failed to handle it).
1943 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
1944 const TargetRegisterClass *RC) {
1945 unsigned Remainder = 0;
1948 // If the value doesn't fit in 32 bits, see if we can shift it
1949 // so that it fits in 32 bits.
1950 if (!isInt<32>(Imm)) {
1951 Shift = countTrailingZeros<uint64_t>(Imm);
1952 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
1954 if (isInt<32>(ImmSh))
1963 // Handle the high-order 32 bits (if shifted) or the whole 32 bits
1964 // (if not shifted).
1965 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
1969 // If upper 32 bits were not zero, we've built them and need to shift
1973 TmpReg2 = createResultReg(RC);
1974 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
1975 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
1979 unsigned TmpReg3, Hi, Lo;
1980 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
1981 TmpReg3 = createResultReg(RC);
1982 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
1983 TmpReg3).addReg(TmpReg2).addImm(Hi);
1987 if ((Lo = Remainder & 0xFFFF)) {
1988 unsigned ResultReg = createResultReg(RC);
1989 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
1990 ResultReg).addReg(TmpReg3).addImm(Lo);
1998 // Materialize an integer constant into a register, and return
1999 // the register number (or zero if we failed to handle it).
2000 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) {
2001 // If we're using CR bit registers for i1 values, handle that as a special
2003 if (VT == MVT::i1 && PPCSubTarget.useCRBits()) {
2004 const ConstantInt *CI = cast<ConstantInt>(C);
2005 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2006 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2007 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2011 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2012 VT != MVT::i8 && VT != MVT::i1)
2015 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2016 &PPC::GPRCRegClass);
2018 // If the constant is in range, use a load-immediate.
2019 const ConstantInt *CI = cast<ConstantInt>(C);
2020 if (isInt<16>(CI->getSExtValue())) {
2021 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2022 unsigned ImmReg = createResultReg(RC);
2023 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2024 .addImm(CI->getSExtValue());
2028 // Construct the constant piecewise.
2029 int64_t Imm = CI->getZExtValue();
2032 return PPCMaterialize64BitInt(Imm, RC);
2033 else if (VT == MVT::i32)
2034 return PPCMaterialize32BitInt(Imm, RC);
2039 // Materialize a constant into a register, and return the register
2040 // number (or zero if we failed to handle it).
2041 unsigned PPCFastISel::TargetMaterializeConstant(const Constant *C) {
2042 EVT CEVT = TLI.getValueType(C->getType(), true);
2044 // Only handle simple types.
2045 if (!CEVT.isSimple()) return 0;
2046 MVT VT = CEVT.getSimpleVT();
2048 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2049 return PPCMaterializeFP(CFP, VT);
2050 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2051 return PPCMaterializeGV(GV, VT);
2052 else if (isa<ConstantInt>(C))
2053 return PPCMaterializeInt(C, VT);
2058 // Materialize the address created by an alloca into a register, and
2059 // return the register number (or zero if we failed to handle it).
2060 unsigned PPCFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
2061 // Don't handle dynamic allocas.
2062 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2065 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2067 DenseMap<const AllocaInst*, int>::iterator SI =
2068 FuncInfo.StaticAllocaMap.find(AI);
2070 if (SI != FuncInfo.StaticAllocaMap.end()) {
2071 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2072 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2073 ResultReg).addFrameIndex(SI->second).addImm(0);
2080 // Fold loads into extends when possible.
2081 // FIXME: We can have multiple redundant extend/trunc instructions
2082 // following a load. The folding only picks up one. Extend this
2083 // to check subsequent instructions for the same pattern and remove
2084 // them. Thus ResultReg should be the def reg for the last redundant
2085 // instruction in a chain, and all intervening instructions can be
2086 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2087 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2088 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2089 const LoadInst *LI) {
2090 // Verify we have a legal type before going any further.
2092 if (!isLoadTypeLegal(LI->getType(), VT))
2095 // Combine load followed by zero- or sign-extend.
2096 bool IsZExt = false;
2097 switch(MI->getOpcode()) {
2102 case PPC::RLDICL_32_64: {
2104 unsigned MB = MI->getOperand(3).getImm();
2105 if ((VT == MVT::i8 && MB <= 56) ||
2106 (VT == MVT::i16 && MB <= 48) ||
2107 (VT == MVT::i32 && MB <= 32))
2113 case PPC::RLWINM8: {
2115 unsigned MB = MI->getOperand(3).getImm();
2116 if ((VT == MVT::i8 && MB <= 24) ||
2117 (VT == MVT::i16 && MB <= 16))
2124 case PPC::EXTSB8_32_64:
2125 /* There is no sign-extending load-byte instruction. */
2130 case PPC::EXTSH8_32_64: {
2131 if (VT != MVT::i16 && VT != MVT::i8)
2137 case PPC::EXTSW_32_64: {
2138 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2144 // See if we can handle this address.
2146 if (!PPCComputeAddress(LI->getOperand(0), Addr))
2149 unsigned ResultReg = MI->getOperand(0).getReg();
2151 if (!PPCEmitLoad(VT, ResultReg, Addr, 0, IsZExt))
2154 MI->eraseFromParent();
2158 // Attempt to lower call arguments in a faster way than done by
2159 // the selection DAG code.
2160 bool PPCFastISel::FastLowerArguments() {
2161 // Defer to normal argument lowering for now. It's reasonably
2162 // efficient. Consider doing something like ARM to handle the
2163 // case where all args fit in registers, no varargs, no float
2168 // Handle materializing integer constants into a register. This is not
2169 // automatically generated for PowerPC, so must be explicitly created here.
2170 unsigned PPCFastISel::FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2172 if (Opc != ISD::Constant)
2175 // If we're using CR bit registers for i1 values, handle that as a special
2177 if (VT == MVT::i1 && PPCSubTarget.useCRBits()) {
2178 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2180 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2184 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2185 VT != MVT::i8 && VT != MVT::i1)
2188 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2189 &PPC::GPRCRegClass);
2191 return PPCMaterialize64BitInt(Imm, RC);
2193 return PPCMaterialize32BitInt(Imm, RC);
2196 // Override for ADDI and ADDI8 to set the correct register class
2197 // on RHS operand 0. The automatic infrastructure naively assumes
2198 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2199 // for these cases. At the moment, none of the other automatically
2200 // generated RI instructions require special treatment. However, once
2201 // SelectSelect is implemented, "isel" requires similar handling.
2203 // Also be conservative about the output register class. Avoid
2204 // assigning R0 or X0 to the output register for GPRC and G8RC
2205 // register classes, as any such result could be used in ADDI, etc.,
2206 // where those regs have another meaning.
2207 unsigned PPCFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
2208 const TargetRegisterClass *RC,
2209 unsigned Op0, bool Op0IsKill,
2211 if (MachineInstOpcode == PPC::ADDI)
2212 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2213 else if (MachineInstOpcode == PPC::ADDI8)
2214 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2216 const TargetRegisterClass *UseRC =
2217 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2218 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2220 return FastISel::FastEmitInst_ri(MachineInstOpcode, UseRC,
2221 Op0, Op0IsKill, Imm);
2224 // Override for instructions with one register operand to avoid use of
2225 // R0/X0. The automatic infrastructure isn't aware of the context so
2226 // we must be conservative.
2227 unsigned PPCFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
2228 const TargetRegisterClass* RC,
2229 unsigned Op0, bool Op0IsKill) {
2230 const TargetRegisterClass *UseRC =
2231 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2232 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2234 return FastISel::FastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2237 // Override for instructions with two register operands to avoid use
2238 // of R0/X0. The automatic infrastructure isn't aware of the context
2239 // so we must be conservative.
2240 unsigned PPCFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
2241 const TargetRegisterClass* RC,
2242 unsigned Op0, bool Op0IsKill,
2243 unsigned Op1, bool Op1IsKill) {
2244 const TargetRegisterClass *UseRC =
2245 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2246 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2248 return FastISel::FastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2253 // Create the fast instruction selector for PowerPC64 ELF.
2254 FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
2255 const TargetLibraryInfo *LibInfo) {
2256 const TargetMachine &TM = FuncInfo.MF->getTarget();
2258 // Only available on 64-bit ELF for now.
2259 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
2260 if (Subtarget->isPPC64() && Subtarget->isSVR4ABI())
2261 return new PPCFastISel(FuncInfo, LibInfo);