1 //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the PowerPC 32- and 64-bit
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
18 class CCIfNotSubtarget<string F, CCAction A>
19 : CCIf<!strconcat("!State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
21 //===----------------------------------------------------------------------===//
22 // Return Value Calling Convention
23 //===----------------------------------------------------------------------===//
25 // Return-value convention for PowerPC
26 def RetCC_PPC : CallingConv<[
27 // On PPC64, integer return values are always promoted to i64
28 CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
29 CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
31 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
32 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
33 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
35 // Floating point types returned as "direct" go into F1 .. F8; note that
36 // only the ELFv2 ABI fully utilizes all these registers.
37 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
38 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
40 // Vector types returned as "direct" go into V2 .. V9; note that only the
41 // ELFv2 ABI fully utilizes all these registers.
42 CCIfType<[v16i8, v8i16, v4i32, v4f32],
43 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>,
44 CCIfType<[v2f64, v2i64],
45 CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>
49 // Note that we don't currently have calling conventions for 64-bit
50 // PowerPC, but handle all the complexities of the ABI in the lowering
51 // logic. FIXME: See if the logic can be simplified with use of CCs.
52 // This may require some extensions to current table generation.
54 // Simple calling convention for 64-bit ELF PowerPC fast isel.
55 // Only handle ints and floats. All ints are promoted to i64.
56 // Vector types and quadword ints are not handled.
57 def CC_PPC64_ELF_FIS : CallingConv<[
58 CCIfType<[i1], CCPromoteToType<i64>>,
59 CCIfType<[i8], CCPromoteToType<i64>>,
60 CCIfType<[i16], CCPromoteToType<i64>>,
61 CCIfType<[i32], CCPromoteToType<i64>>,
62 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
63 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
66 // Simple return-value convention for 64-bit ELF PowerPC fast isel.
67 // All small ints are promoted to i64. Vector types, quadword ints,
68 // and multiple register returns are "supported" to avoid compile
69 // errors, but none are handled by the fast selector.
70 def RetCC_PPC64_ELF_FIS : CallingConv<[
71 CCIfType<[i1], CCPromoteToType<i64>>,
72 CCIfType<[i8], CCPromoteToType<i64>>,
73 CCIfType<[i16], CCPromoteToType<i64>>,
74 CCIfType<[i32], CCPromoteToType<i64>>,
75 CCIfType<[i64], CCAssignToReg<[X3, X4]>>,
76 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
77 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
78 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
79 CCIfType<[v16i8, v8i16, v4i32, v4f32],
80 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>,
81 CCIfType<[v2f64, v2i64],
82 CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>
85 //===----------------------------------------------------------------------===//
86 // PowerPC System V Release 4 32-bit ABI
87 //===----------------------------------------------------------------------===//
89 def CC_PPC32_SVR4_Common : CallingConv<[
90 CCIfType<[i1], CCPromoteToType<i32>>,
92 // The ABI requires i64 to be passed in two adjacent registers with the first
93 // register having an odd register number.
94 CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
96 // The first 8 integer arguments are passed in integer registers.
97 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
99 // Make sure the i64 words from a long double are either both passed in
100 // registers or both passed on the stack.
101 CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
103 // FP values are passed in F1 - F8.
104 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
106 // Split arguments have an alignment of 8 bytes on the stack.
107 CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
109 CCIfType<[i32], CCAssignToStack<4, 4>>,
111 // Floats are stored in double precision format, thus they have the same
112 // alignment and size as doubles.
113 CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
115 // Vectors get 16-byte stack slots that are 16-byte aligned.
116 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>
119 // This calling convention puts vector arguments always on the stack. It is used
120 // to assign vector arguments which belong to the variable portion of the
121 // parameter list of a variable argument function.
122 def CC_PPC32_SVR4_VarArg : CallingConv<[
123 CCDelegateTo<CC_PPC32_SVR4_Common>
126 // In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
127 // put vector arguments in vector registers before putting them on the stack.
128 def CC_PPC32_SVR4 : CallingConv<[
129 // The first 12 Vector arguments are passed in AltiVec registers.
130 CCIfType<[v16i8, v8i16, v4i32, v4f32],
131 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
132 CCIfType<[v2f64, v2i64],
133 CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9,
134 VSH10, VSH11, VSH12, VSH13]>>,
136 CCDelegateTo<CC_PPC32_SVR4_Common>
139 // Helper "calling convention" to handle aggregate by value arguments.
140 // Aggregate by value arguments are always placed in the local variable space
141 // of the caller. This calling convention is only used to assign those stack
142 // offsets in the callers stack frame.
144 // Still, the address of the aggregate copy in the callers stack frame is passed
145 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
146 // caller to the callee. The location for the address argument is assigned by
147 // the CC_PPC32_SVR4 calling convention.
149 // The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
150 // not passed by value.
152 def CC_PPC32_SVR4_ByVal : CallingConv<[
153 CCIfByVal<CCPassByVal<4, 4>>,
155 CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
158 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
159 V28, V29, V30, V31)>;
161 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
162 R21, R22, R23, R24, R25, R26, R27, R28,
163 R29, R30, R31, F14, F15, F16, F17, F18,
164 F19, F20, F21, F22, F23, F24, F25, F26,
165 F27, F28, F29, F30, F31, CR2, CR3, CR4
168 def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
170 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
171 R21, R22, R23, R24, R25, R26, R27, R28,
172 R29, R30, R31, F14, F15, F16, F17, F18,
173 F19, F20, F21, F22, F23, F24, F25, F26,
174 F27, F28, F29, F30, F31, CR2, CR3, CR4
177 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
179 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
180 X21, X22, X23, X24, X25, X26, X27, X28,
181 X29, X30, X31, F14, F15, F16, F17, F18,
182 F19, F20, F21, F22, F23, F24, F25, F26,
183 F27, F28, F29, F30, F31, CR2, CR3, CR4
186 def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
188 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
189 X21, X22, X23, X24, X25, X26, X27, X28,
190 X29, X30, X31, F14, F15, F16, F17, F18,
191 F19, F20, F21, F22, F23, F24, F25, F26,
192 F27, F28, F29, F30, F31, CR2, CR3, CR4
196 def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
198 def CSR_NoRegs : CalleeSavedRegs<(add)>;