1 //===-- PPCCTRLoops.cpp - Identify and generate CTR loops -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass identifies loops where we can generate the PPC branch instructions
11 // that decrement and test the count register (CTR) (bdnz and friends).
12 // This pass is based on the HexagonHardwareLoops pass.
14 // The pattern that defines the induction variable can changed depending on
15 // prior optimizations. For example, the IndVarSimplify phase run by 'opt'
16 // normalizes induction variables, and the Loop Strength Reduction pass
17 // run by 'llc' may also make changes to the induction variable.
18 // The pattern detected by this phase is due to running Strength Reduction.
20 // Criteria for CTR loops:
21 // - Countable loops (w/ ind. var for a trip count)
22 // - Assumes loops are normalized by IndVarSimplify
23 // - Try inner-most loops first
24 // - No nested CTR loops.
25 // - No function calls in loops.
27 // Note: As with unconverted loops, PPCBranchSelector must be run after this
28 // pass in order to convert long-displacement jumps into jump pairs.
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "ctrloops"
34 #include "MCTargetDesc/PPCPredicates.h"
35 #include "PPCTargetMachine.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/Statistic.h"
38 #include "llvm/CodeGen/MachineDominators.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineFunctionPass.h"
41 #include "llvm/CodeGen/MachineInstrBuilder.h"
42 #include "llvm/CodeGen/MachineLoopInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/Passes.h"
45 #include "llvm/CodeGen/RegisterScavenging.h"
46 #include "llvm/IR/Constants.h"
47 #include "llvm/PassSupport.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
55 STATISTIC(NumCTRLoops, "Number of loops converted to CTR loops");
58 void initializePPCCTRLoopsPass(PassRegistry&);
63 struct PPCCTRLoops : public MachineFunctionPass {
65 MachineRegisterInfo *MRI;
66 const TargetInstrInfo *TII;
69 static char ID; // Pass identification, replacement for typeid
71 PPCCTRLoops() : MachineFunctionPass(ID) {
72 initializePPCCTRLoopsPass(*PassRegistry::getPassRegistry());
75 virtual bool runOnMachineFunction(MachineFunction &MF);
77 const char *getPassName() const { return "PPC CTR Loops"; }
79 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
81 AU.addRequired<MachineDominatorTree>();
82 AU.addPreserved<MachineDominatorTree>();
83 AU.addRequired<MachineLoopInfo>();
84 AU.addPreserved<MachineLoopInfo>();
85 MachineFunctionPass::getAnalysisUsage(AU);
89 /// getCanonicalInductionVariable - Check to see if the loop has a canonical
90 /// induction variable.
91 /// Should be defined in MachineLoop. Based upon version in class Loop.
92 void getCanonicalInductionVariable(MachineLoop *L,
93 SmallVector<MachineInstr *, 4> &IVars,
94 SmallVector<MachineInstr *, 4> &IOps) const;
96 /// getTripCount - Return a loop-invariant LLVM register indicating the
97 /// number of times the loop will be executed. If the trip-count cannot
98 /// be determined, this return null.
99 CountValue *getTripCount(MachineLoop *L,
100 SmallVector<MachineInstr *, 2> &OldInsts) const;
102 /// isInductionOperation - Return true if the instruction matches the
103 /// pattern for an opertion that defines an induction variable.
104 bool isInductionOperation(const MachineInstr *MI, unsigned IVReg) const;
106 /// isInvalidOperation - Return true if the instruction is not valid within
108 bool isInvalidLoopOperation(const MachineInstr *MI) const;
110 /// containsInavlidInstruction - Return true if the loop contains an
111 /// instruction that inhibits using the CTR loop.
112 bool containsInvalidInstruction(MachineLoop *L) const;
114 /// converToCTRLoop - Given a loop, check if we can convert it to a
115 /// CTR loop. If so, then perform the conversion and return true.
116 bool convertToCTRLoop(MachineLoop *L);
118 /// isDead - Return true if the instruction is now dead.
119 bool isDead(const MachineInstr *MI,
120 SmallVector<MachineInstr *, 1> &DeadPhis) const;
122 /// removeIfDead - Remove the instruction if it is now dead.
123 void removeIfDead(MachineInstr *MI);
126 char PPCCTRLoops::ID = 0;
129 // CountValue class - Abstraction for a trip count of a loop. A
130 // smaller vesrsion of the MachineOperand class without the concerns
131 // of changing the operand representation.
134 enum CountValueType {
143 Values(unsigned r) : RegNum(r) {}
144 Values(int64_t i) : ImmVal(i) {}
149 CountValue(unsigned r, bool neg) : Kind(CV_Register), Contents(r),
151 explicit CountValue(int64_t i) : Kind(CV_Immediate), Contents(i),
153 CountValueType getType() const { return Kind; }
154 bool isReg() const { return Kind == CV_Register; }
155 bool isImm() const { return Kind == CV_Immediate; }
156 bool isNeg() const { return isNegative; }
158 unsigned getReg() const {
159 assert(isReg() && "Wrong CountValue accessor");
160 return Contents.RegNum;
162 void setReg(unsigned Val) {
163 Contents.RegNum = Val;
165 int64_t getImm() const {
166 assert(isImm() && "Wrong CountValue accessor");
168 return -Contents.ImmVal;
170 return Contents.ImmVal;
172 void setImm(int64_t Val) {
173 Contents.ImmVal = Val;
176 void print(raw_ostream &OS, const TargetMachine *TM = 0) const {
177 if (isReg()) { OS << PrintReg(getReg()); }
178 if (isImm()) { OS << getImm(); }
181 } // end anonymous namespace
183 INITIALIZE_PASS_BEGIN(PPCCTRLoops, "ppc-ctr-loops", "PowerPC CTR Loops",
185 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
186 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
187 INITIALIZE_PASS_END(PPCCTRLoops, "ppc-ctr-loops", "PowerPC CTR Loops",
190 /// isCompareEquals - Returns true if the instruction is a compare equals
191 /// instruction with an immediate operand.
192 static bool isCompareEqualsImm(const MachineInstr *MI, bool &SignedCmp) {
193 if (MI->getOpcode() == PPC::CMPWI || MI->getOpcode() == PPC::CMPDI) {
196 } else if (MI->getOpcode() == PPC::CMPLWI || MI->getOpcode() == PPC::CMPLDI) {
205 /// createPPCCTRLoops - Factory for creating
206 /// the CTR loop phase.
207 FunctionPass *llvm::createPPCCTRLoops() {
208 return new PPCCTRLoops();
212 bool PPCCTRLoops::runOnMachineFunction(MachineFunction &MF) {
213 DEBUG(dbgs() << "********* PPC CTR Loops *********\n");
215 bool Changed = false;
217 // get the loop information
218 MLI = &getAnalysis<MachineLoopInfo>();
219 // get the register information
220 MRI = &MF.getRegInfo();
221 // the target specific instructio info.
222 TII = MF.getTarget().getInstrInfo();
224 for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end();
227 if (!L->getParentLoop()) {
228 Changed |= convertToCTRLoop(L);
235 /// getCanonicalInductionVariable - Check to see if the loop has a canonical
236 /// induction variable. We check for a simple recurrence pattern - an
237 /// integer recurrence that decrements by one each time through the loop and
238 /// ends at zero. If so, return the phi node that corresponds to it.
240 /// Based upon the similar code in LoopInfo except this code is specific to
242 /// This method assumes that the IndVarSimplify pass has been run by 'opt'.
245 PPCCTRLoops::getCanonicalInductionVariable(MachineLoop *L,
246 SmallVector<MachineInstr *, 4> &IVars,
247 SmallVector<MachineInstr *, 4> &IOps) const {
248 MachineBasicBlock *TopMBB = L->getTopBlock();
249 MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();
250 assert(PI != TopMBB->pred_end() &&
251 "Loop must have more than one incoming edge!");
252 MachineBasicBlock *Backedge = *PI++;
253 if (PI == TopMBB->pred_end()) return; // dead loop
254 MachineBasicBlock *Incoming = *PI++;
255 if (PI != TopMBB->pred_end()) return; // multiple backedges?
257 // make sure there is one incoming and one backedge and determine which
259 if (L->contains(Incoming)) {
260 if (L->contains(Backedge))
262 std::swap(Incoming, Backedge);
263 } else if (!L->contains(Backedge))
266 // Loop over all of the PHI nodes, looking for a canonical induction variable:
267 // - The PHI node is "reg1 = PHI reg2, BB1, reg3, BB2".
268 // - The recurrence comes from the backedge.
269 // - the definition is an induction operatio.n
270 for (MachineBasicBlock::iterator I = TopMBB->begin(), E = TopMBB->end();
271 I != E && I->isPHI(); ++I) {
272 MachineInstr *MPhi = &*I;
273 unsigned DefReg = MPhi->getOperand(0).getReg();
274 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
275 // Check each operand for the value from the backedge.
276 MachineBasicBlock *MBB = MPhi->getOperand(i+1).getMBB();
277 if (L->contains(MBB)) { // operands comes from the backedge
278 // Check if the definition is an induction operation.
279 MachineInstr *DI = MRI->getVRegDef(MPhi->getOperand(i).getReg());
280 if (isInductionOperation(DI, DefReg)) {
282 IVars.push_back(MPhi);
290 /// getTripCount - Return a loop-invariant LLVM value indicating the
291 /// number of times the loop will be executed. The trip count can
292 /// be either a register or a constant value. If the trip-count
293 /// cannot be determined, this returns null.
295 /// We find the trip count from the phi instruction that defines the
296 /// induction variable. We follow the links to the CMP instruction
297 /// to get the trip count.
299 /// Based upon getTripCount in LoopInfo.
301 CountValue *PPCCTRLoops::getTripCount(MachineLoop *L,
302 SmallVector<MachineInstr *, 2> &OldInsts) const {
303 MachineBasicBlock *LastMBB = L->getExitingBlock();
304 // Don't generate a CTR loop if the loop has more than one exit.
308 MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
309 if (LastI->getOpcode() != PPC::BCC)
312 // We need to make sure that this compare is defining the condition
313 // register actually used by the terminating branch.
315 unsigned PredReg = LastI->getOperand(1).getReg();
316 DEBUG(dbgs() << "Examining loop with first terminator: " << *LastI);
318 unsigned PredCond = LastI->getOperand(0).getImm();
319 if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
322 // Check that the loop has a induction variable.
323 SmallVector<MachineInstr *, 4> IVars, IOps;
324 getCanonicalInductionVariable(L, IVars, IOps);
325 for (unsigned i = 0; i < IVars.size(); ++i) {
326 MachineInstr *IOp = IOps[i];
327 MachineInstr *IV_Inst = IVars[i];
329 // Canonical loops will end with a 'cmpwi/cmpdi cr, IV, Imm',
330 // if Imm is 0, get the count from the PHI opnd
331 // if Imm is -M, than M is the count
332 // Otherwise, Imm is the count
333 MachineOperand *IV_Opnd;
334 const MachineOperand *InitialValue;
335 if (!L->contains(IV_Inst->getOperand(2).getMBB())) {
336 InitialValue = &IV_Inst->getOperand(1);
337 IV_Opnd = &IV_Inst->getOperand(3);
339 InitialValue = &IV_Inst->getOperand(3);
340 IV_Opnd = &IV_Inst->getOperand(1);
343 DEBUG(dbgs() << "Considering:\n");
344 DEBUG(dbgs() << " induction operation: " << *IOp);
345 DEBUG(dbgs() << " induction variable: " << *IV_Inst);
346 DEBUG(dbgs() << " initial value: " << *InitialValue << "\n");
348 // Look for the cmp instruction to determine if we
349 // can get a useful trip count. The trip count can
350 // be either a register or an immediate. The location
351 // of the value depends upon the type (reg or imm).
352 for (MachineRegisterInfo::reg_iterator
353 RI = MRI->reg_begin(IV_Opnd->getReg()), RE = MRI->reg_end();
355 IV_Opnd = &RI.getOperand();
357 MachineInstr *MI = IV_Opnd->getParent();
358 if (L->contains(MI) && isCompareEqualsImm(MI, SignedCmp) &&
359 MI->getOperand(0).getReg() == PredReg) {
361 OldInsts.push_back(MI);
362 OldInsts.push_back(IOp);
364 DEBUG(dbgs() << " compare: " << *MI);
366 const MachineOperand &MO = MI->getOperand(2);
367 assert(MO.isImm() && "IV Cmp Operand should be an immediate");
371 ImmVal = (short) MO.getImm();
373 ImmVal = MO.getImm();
375 const MachineInstr *IV_DefInstr = MRI->getVRegDef(IV_Opnd->getReg());
376 assert(L->contains(IV_DefInstr->getParent()) &&
377 "IV definition should occurs in loop");
378 int64_t iv_value = (short) IV_DefInstr->getOperand(2).getImm();
380 assert(InitialValue->isReg() && "Expecting register for init value");
381 unsigned InitialValueReg = InitialValue->getReg();
383 const MachineInstr *DefInstr = MRI->getVRegDef(InitialValueReg);
385 // Here we need to look for an immediate load (an li or lis/ori pair).
386 if (DefInstr && (DefInstr->getOpcode() == PPC::ORI8 ||
387 DefInstr->getOpcode() == PPC::ORI)) {
388 int64_t start = (short) DefInstr->getOperand(2).getImm();
389 const MachineInstr *DefInstr2 =
390 MRI->getVRegDef(DefInstr->getOperand(0).getReg());
391 if (DefInstr2 && (DefInstr2->getOpcode() == PPC::LIS8 ||
392 DefInstr2->getOpcode() == PPC::LIS)) {
393 DEBUG(dbgs() << " initial constant: " << *DefInstr);
394 DEBUG(dbgs() << " initial constant: " << *DefInstr2);
396 start |= int64_t(short(DefInstr2->getOperand(1).getImm())) << 16;
398 int64_t count = ImmVal - start;
399 if ((count % iv_value) != 0) {
402 return new CountValue(count/iv_value);
404 } else if (DefInstr && (DefInstr->getOpcode() == PPC::LI8 ||
405 DefInstr->getOpcode() == PPC::LI)) {
406 DEBUG(dbgs() << " initial constant: " << *DefInstr);
408 int64_t count = ImmVal - int64_t(short(DefInstr->getOperand(1).getImm()));
409 if ((count % iv_value) != 0) {
412 return new CountValue(count/iv_value);
413 } else if (iv_value == 1 || iv_value == -1) {
414 // We can't determine a constant starting value.
416 return new CountValue(InitialValueReg, iv_value > 0);
418 // FIXME: handle non-zero end value.
420 // FIXME: handle non-unit increments (we might not want to introduce division
421 // but we can handle some 2^n cases with shifts).
429 /// isInductionOperation - return true if the operation is matches the
430 /// pattern that defines an induction variable:
434 PPCCTRLoops::isInductionOperation(const MachineInstr *MI,
435 unsigned IVReg) const {
436 return ((MI->getOpcode() == PPC::ADDI || MI->getOpcode() == PPC::ADDI8) &&
437 MI->getOperand(1).isReg() && // could be a frame index instead
438 MI->getOperand(1).getReg() == IVReg);
441 /// isInvalidOperation - Return true if the operation is invalid within
444 PPCCTRLoops::isInvalidLoopOperation(const MachineInstr *MI) const {
446 // call is not allowed because the callee may use a CTR loop
447 if (MI->getDesc().isCall()) {
450 // check if the instruction defines a CTR loop register
451 // (this will also catch nested CTR loops)
452 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
453 const MachineOperand &MO = MI->getOperand(i);
454 if (MO.isReg() && MO.isDef() &&
455 (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8)) {
462 /// containsInvalidInstruction - Return true if the loop contains
463 /// an instruction that inhibits the use of the CTR loop function.
465 bool PPCCTRLoops::containsInvalidInstruction(MachineLoop *L) const {
466 const std::vector<MachineBasicBlock*> Blocks = L->getBlocks();
467 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
468 MachineBasicBlock *MBB = Blocks[i];
469 for (MachineBasicBlock::iterator
470 MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) {
471 const MachineInstr *MI = &*MII;
472 if (isInvalidLoopOperation(MI)) {
480 /// isDead returns true if the instruction is dead
481 /// (this was essentially copied from DeadMachineInstructionElim::isDead, but
482 /// with special cases for inline asm, physical registers and instructions with
483 /// side effects removed)
484 bool PPCCTRLoops::isDead(const MachineInstr *MI,
485 SmallVector<MachineInstr *, 1> &DeadPhis) const {
486 // Examine each operand.
487 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
488 const MachineOperand &MO = MI->getOperand(i);
489 if (MO.isReg() && MO.isDef()) {
490 unsigned Reg = MO.getReg();
491 if (!MRI->use_nodbg_empty(Reg)) {
492 // This instruction has users, but if the only user is the phi node for the
493 // parent block, and the only use of that phi node is this instruction, then
494 // this instruction is dead: both it (and the phi node) can be removed.
495 MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg);
496 if (llvm::next(I) == MRI->use_end() &&
497 I.getOperand().getParent()->isPHI()) {
498 MachineInstr *OnePhi = I.getOperand().getParent();
500 for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {
501 const MachineOperand &OPO = OnePhi->getOperand(j);
502 if (OPO.isReg() && OPO.isDef()) {
503 unsigned OPReg = OPO.getReg();
505 MachineRegisterInfo::use_iterator nextJ;
506 for (MachineRegisterInfo::use_iterator J = MRI->use_begin(OPReg),
507 E = MRI->use_end(); J!=E; J=nextJ) {
508 nextJ = llvm::next(J);
509 MachineOperand& Use = J.getOperand();
510 MachineInstr *UseMI = Use.getParent();
513 // The phi node has a user that is not MI, bail...
520 DeadPhis.push_back(OnePhi);
522 // This def has a non-debug use. Don't delete the instruction!
529 // If there are no defs with uses, the instruction is dead.
533 void PPCCTRLoops::removeIfDead(MachineInstr *MI) {
534 // This procedure was essentially copied from DeadMachineInstructionElim
536 SmallVector<MachineInstr *, 1> DeadPhis;
537 if (isDead(MI, DeadPhis)) {
538 DEBUG(dbgs() << "CTR looping will remove: " << *MI);
540 // It is possible that some DBG_VALUE instructions refer to this
541 // instruction. Examine each def operand for such references;
542 // if found, mark the DBG_VALUE as undef (but don't delete it).
543 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
544 const MachineOperand &MO = MI->getOperand(i);
545 if (!MO.isReg() || !MO.isDef())
547 unsigned Reg = MO.getReg();
548 MachineRegisterInfo::use_iterator nextI;
549 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
550 E = MRI->use_end(); I!=E; I=nextI) {
551 nextI = llvm::next(I); // I is invalidated by the setReg
552 MachineOperand& Use = I.getOperand();
553 MachineInstr *UseMI = Use.getParent();
556 if (Use.isDebug()) // this might also be a instr -> phi -> instr case
557 // which can also be removed.
558 UseMI->getOperand(0).setReg(0U);
562 MI->eraseFromParent();
563 for (unsigned i = 0; i < DeadPhis.size(); ++i) {
564 DeadPhis[i]->eraseFromParent();
569 /// converToCTRLoop - check if the loop is a candidate for
570 /// converting to a CTR loop. If so, then perform the
573 /// This function works on innermost loops first. A loop can
574 /// be converted if it is a counting loop; either a register
575 /// value or an immediate.
577 /// The code makes several assumptions about the representation
578 /// of the loop in llvm.
579 bool PPCCTRLoops::convertToCTRLoop(MachineLoop *L) {
580 bool Changed = false;
581 // Process nested loops first.
582 for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
583 Changed |= convertToCTRLoop(*I);
585 // If a nested loop has been converted, then we can't convert this loop.
590 SmallVector<MachineInstr *, 2> OldInsts;
591 // Are we able to determine the trip count for the loop?
592 CountValue *TripCount = getTripCount(L, OldInsts);
593 if (TripCount == 0) {
594 DEBUG(dbgs() << "failed to get trip count!\n");
597 // Does the loop contain any invalid instructions?
598 if (containsInvalidInstruction(L)) {
601 MachineBasicBlock *Preheader = L->getLoopPreheader();
602 // No preheader means there's not place for the loop instr.
603 if (Preheader == 0) {
606 MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();
609 if (InsertPos != Preheader->end())
610 dl = InsertPos->getDebugLoc();
612 MachineBasicBlock *LastMBB = L->getExitingBlock();
613 // Don't generate CTR loop if the loop has more than one exit.
617 MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
619 // Determine the loop start.
620 MachineBasicBlock *LoopStart = L->getTopBlock();
621 if (L->getLoopLatch() != LastMBB) {
622 // When the exit and latch are not the same, use the latch block as the
624 // The loop start address is used only after the 1st iteration, and the loop
625 // latch may contains instrs. that need to be executed after the 1st iter.
626 LoopStart = L->getLoopLatch();
627 // Make sure the latch is a successor of the exit, otherwise it won't work.
628 if (!LastMBB->isSuccessor(LoopStart)) {
633 // Convert the loop to a CTR loop
634 DEBUG(dbgs() << "Change to CTR loop at "; L->dump());
636 MachineFunction *MF = LastMBB->getParent();
637 const PPCSubtarget &Subtarget = MF->getTarget().getSubtarget<PPCSubtarget>();
638 bool isPPC64 = Subtarget.isPPC64();
640 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
641 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
642 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
645 if (TripCount->isReg()) {
646 // Create a copy of the loop count register.
647 const TargetRegisterClass *SrcRC =
648 MF->getRegInfo().getRegClass(TripCount->getReg());
649 CountReg = MF->getRegInfo().createVirtualRegister(RC);
650 unsigned CopyOp = (isPPC64 && SrcRC == GPRC) ?
651 (unsigned) PPC::EXTSW_32_64 :
652 (unsigned) TargetOpcode::COPY;
653 BuildMI(*Preheader, InsertPos, dl,
654 TII->get(CopyOp), CountReg).addReg(TripCount->getReg());
655 if (TripCount->isNeg()) {
656 unsigned CountReg1 = CountReg;
657 CountReg = MF->getRegInfo().createVirtualRegister(RC);
658 BuildMI(*Preheader, InsertPos, dl,
659 TII->get(isPPC64 ? PPC::NEG8 : PPC::NEG),
660 CountReg).addReg(CountReg1);
663 assert(TripCount->isImm() && "Expecting immedate vaule for trip count");
664 // Put the trip count in a register for transfer into the count register.
666 int64_t CountImm = TripCount->getImm();
667 assert(!TripCount->isNeg() && "Constant trip count must be positive");
669 CountReg = MF->getRegInfo().createVirtualRegister(RC);
670 if (CountImm > 0xFFFF) {
671 BuildMI(*Preheader, InsertPos, dl,
672 TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS),
673 CountReg).addImm(CountImm >> 16);
674 unsigned CountReg1 = CountReg;
675 CountReg = MF->getRegInfo().createVirtualRegister(RC);
676 BuildMI(*Preheader, InsertPos, dl,
677 TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI),
678 CountReg).addReg(CountReg1).addImm(CountImm & 0xFFFF);
680 BuildMI(*Preheader, InsertPos, dl,
681 TII->get(isPPC64 ? PPC::LI8 : PPC::LI),
682 CountReg).addImm(CountImm);
686 // Add the mtctr instruction to the beginning of the loop.
687 BuildMI(*Preheader, InsertPos, dl,
688 TII->get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(CountReg,
689 TripCount->isImm() ? RegState::Kill : 0);
691 // Make sure the loop start always has a reference in the CFG. We need to
692 // create a BlockAddress operand to get this mechanism to work both the
693 // MachineBasicBlock and BasicBlock objects need the flag set.
694 LoopStart->setHasAddressTaken();
695 // This line is needed to set the hasAddressTaken flag on the BasicBlock
697 BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
699 // Replace the loop branch with a bdnz instruction.
700 dl = LastI->getDebugLoc();
701 const std::vector<MachineBasicBlock*> Blocks = L->getBlocks();
702 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
703 MachineBasicBlock *MBB = Blocks[i];
704 if (MBB != Preheader)
705 MBB->addLiveIn(isPPC64 ? PPC::CTR8 : PPC::CTR);
708 // The loop ends with either:
709 // - a conditional branch followed by an unconditional branch, or
710 // - a conditional branch to the loop start.
711 assert(LastI->getOpcode() == PPC::BCC &&
712 "loop end must start with a BCC instruction");
713 // Either the BCC branches to the beginning of the loop, or it
714 // branches out of the loop and there is an unconditional branch
715 // to the start of the loop.
716 MachineBasicBlock *BranchTarget = LastI->getOperand(2).getMBB();
717 BuildMI(*LastMBB, LastI, dl,
718 TII->get((BranchTarget == LoopStart) ?
719 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
720 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(BranchTarget);
722 // Conditional branch; just delete it.
723 DEBUG(dbgs() << "Removing old branch: " << *LastI);
724 LastMBB->erase(LastI);
728 // The induction operation (add) and the comparison (cmpwi) may now be
729 // unneeded. If these are unneeded, then remove them.
730 for (unsigned i = 0; i < OldInsts.size(); ++i)
731 removeIfDead(OldInsts[i]);