lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
  50
  51 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  52                                         "Enable 64-bit instructions">;
  53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  54                               "Enable 64-bit registers usage for ppc32 [beta]">;
  55 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  56                               "Use condition-register bits individually">;
  57 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  58                                         "Enable Altivec instructions">;
  59 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
  60                                         "Enable SPE instructions">;
  61 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  62                                         "Enable the MFOCRF instruction">;
  63 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  64                                         "Enable the fsqrt instruction">;
  65 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  66                                         "Enable the fcpsgn instruction">;
  67 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  68                                         "Enable the fre instruction">;
  69 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  70                                         "Enable the fres instruction">;
  71 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  72                                         "Enable the frsqrte instruction">;
  73 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  74                                         "Enable the frsqrtes instruction">;
  75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  76                               "Assume higher precision reciprocal estimates">;
  77 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  78                                         "Enable the stfiwx instruction">;
  79 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
  80                                         "Enable the lfiwax instruction">;
  81 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
  82                                         "Enable the fri[mnpz] instructions">;
  83 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
  84   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
  85 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  86                                         "Enable the isel instruction">;
  87 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
  88                                         "Enable the popcnt[dw] instructions">;
  89 def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
  90                                         "Enable the bpermd instruction">;
  91 def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
  92                                         "Enable extended divide instructions">;
  93 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
  94                                         "Enable the ldbrx instruction">;
  95 def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
  96                                         "Enable the cmpb instruction">;
  97 def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
  98                                         "Enable icbt instruction">;
  99 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
 100                                         "Enable Book E instructions",
 101                                         [FeatureICBT]>;
 102 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
 103                               "Has only the msync instruction instead of sync",
 104                               [FeatureBookE]>;
 105 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
 106                                         "Enable E500/E500mc instructions">;
 107 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
 108                                         "Enable PPC 4xx instructions">;
 109 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
 110                                         "Enable PPC 6xx instructions">;
 111 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
 112                                         "Enable QPX instructions">;
 113 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
 114                                         "Enable VSX instructions",
 115                                         [FeatureAltivec]>;
 116 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
 117                                         "Enable POWER8 Altivec instructions",
 118                                         [FeatureAltivec]>;
 119 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
 120                                        "Enable POWER8 Crypto instructions",
 121                                        [FeatureP8Altivec]>;
 122 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
 123                                         "Enable POWER8 vector instructions",
 124                                         [FeatureVSX, FeatureP8Altivec]>;
 125 def FeatureDirectMove :
 126   SubtargetFeature<"direct-move", "HasDirectMove", "true",
 127                    "Enable Power8 direct move instructions",
 128                    [FeatureVSX]>;
 129 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
 130                                              "HasPartwordAtomics", "true",
 131                                              "Enable l[bh]arx and st[bh]cx.">;
 132 def FeatureInvariantFunctionDescriptors :
 133   SubtargetFeature<"invariant-function-descriptors",
 134                    "HasInvariantFunctionDescriptors", "true",
 135                    "Assume function descriptors are invariant">;
 136 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
 137                                   "Enable Hardware Transactional Memory instructions">;
 138
 139 def DeprecatedMFTB   : SubtargetFeature<"", "DeprecatedMFTB", "true",
 140                                         "Treat mftb as deprecated">;
 141 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 142   "Treat vector data stream cache control instructions as deprecated">;
 143
 144 /*  Since new processors generally contain a superset of features of those that
 145     came before them, the idea is to make implementations of new processors
 146     less error prone and easier to read.
 147     Namely:
 148         list<SubtargetFeature> Power8FeatureList = ...
 149         list<SubtargetFeature> FutureProcessorSpecificFeatureList =
 150             [ features that Power8 does not support ]
 151         list<SubtargetFeature> FutureProcessorFeatureList =
 152             !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
 153
 154     Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
 155     well as providing a single point of definition if the feature set will be
 156     used elsewhere.
 157 */
 158 def ProcessorFeatures {
 159   list<SubtargetFeature> Power7FeatureList =
 160       [DirectivePwr7, FeatureAltivec, FeatureVSX,
 161        FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 162        FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 163        FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 164        FeatureFPRND, FeatureFPCVT, FeatureISEL,
 165        FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
 166        Feature64Bit /*, Feature64BitRegs */, FeaturePartwordAtomic,
 167        FeatureBPERMD, FeatureExtDiv,
 168        DeprecatedMFTB, DeprecatedDST];
 169   list<SubtargetFeature> Power8SpecificFeatures =
 170       [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
 171        FeatureHTM, FeatureDirectMove, FeatureICBT];
 172   list<SubtargetFeature> Power8FeatureList =
 173       !listconcat(Power7FeatureList, Power8SpecificFeatures);
 174 }
 175
 176 // Note: Future features to add when support is extended to more
 177 // recent ISA levels:
 178 //
 179 // DFP          p6, p6x, p7        decimal floating-point instructions
 180 // POPCNTB      p5 through p7      popcntb and related instructions
 181
 182 //===----------------------------------------------------------------------===//
 183 // Classes used for relation maps.
 184 //===----------------------------------------------------------------------===//
 185 // RecFormRel - Filter class used to relate non-record-form instructions with
 186 // their record-form variants.
 187 class RecFormRel;
 188
 189 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 190 // FMA instruction forms with their corresponding factor-killing forms.
 191 class AltVSXFMARel {
 192   bit IsVSXFMAAlt = 0;
 193 }
 194
 195 //===----------------------------------------------------------------------===//
 196 // Relation Map Definitions.
 197 //===----------------------------------------------------------------------===//
 198
 199 def getRecordFormOpcode : InstrMapping {
 200   let FilterClass = "RecFormRel";
 201   // Instructions with the same BaseName and Interpretation64Bit values
 202   // form a row.
 203   let RowFields = ["BaseName", "Interpretation64Bit"];
 204   // Instructions with the same RC value form a column.
 205   let ColFields = ["RC"];
 206   // The key column are the non-record-form instructions.
 207   let KeyCol = ["0"];
 208   // Value columns RC=1
 209   let ValueCols = [["1"]];
 210 }
 211
 212 def getNonRecordFormOpcode : InstrMapping {
 213   let FilterClass = "RecFormRel";
 214   // Instructions with the same BaseName and Interpretation64Bit values
 215   // form a row.
 216   let RowFields = ["BaseName", "Interpretation64Bit"];
 217   // Instructions with the same RC value form a column.
 218   let ColFields = ["RC"];
 219   // The key column are the record-form instructions.
 220   let KeyCol = ["1"];
 221   // Value columns are RC=0
 222   let ValueCols = [["0"]];
 223 }
 224
 225 def getAltVSXFMAOpcode : InstrMapping {
 226   let FilterClass = "AltVSXFMARel";
 227   // Instructions with the same BaseName and Interpretation64Bit values
 228   // form a row.
 229   let RowFields = ["BaseName"];
 230   // Instructions with the same RC value form a column.
 231   let ColFields = ["IsVSXFMAAlt"];
 232   // The key column are the (default) addend-killing instructions.
 233   let KeyCol = ["0"];
 234   // Value columns IsVSXFMAAlt=1
 235   let ValueCols = [["1"]];
 236 }
 237
 238 //===----------------------------------------------------------------------===//
 239 // Register File Description
 240 //===----------------------------------------------------------------------===//
 241
 242 include "PPCRegisterInfo.td"
 243 include "PPCSchedule.td"
 244 include "PPCInstrInfo.td"
 245
 246 //===----------------------------------------------------------------------===//
 247 // PowerPC processors supported.
 248 //
 249
 250 def : Processor<"generic", G3Itineraries, [Directive32]>;
 251 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 252                                           FeatureFRES, FeatureFRSQRTE,
 253                                           FeatureICBT, FeatureBookE,
 254                                           FeatureMSYNC, DeprecatedMFTB]>;
 255 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 256                                           FeatureFRES, FeatureFRSQRTE,
 257                                           FeatureICBT, FeatureBookE,
 258                                           FeatureMSYNC, DeprecatedMFTB]>;
 259 def : Processor<"601", G3Itineraries, [Directive601]>;
 260 def : Processor<"602", G3Itineraries, [Directive602]>;
 261 def : Processor<"603", G3Itineraries, [Directive603,
 262                                        FeatureFRES, FeatureFRSQRTE]>;
 263 def : Processor<"603e", G3Itineraries, [Directive603,
 264                                         FeatureFRES, FeatureFRSQRTE]>;
 265 def : Processor<"603ev", G3Itineraries, [Directive603,
 266                                          FeatureFRES, FeatureFRSQRTE]>;
 267 def : Processor<"604", G3Itineraries, [Directive604,
 268                                        FeatureFRES, FeatureFRSQRTE]>;
 269 def : Processor<"604e", G3Itineraries, [Directive604,
 270                                         FeatureFRES, FeatureFRSQRTE]>;
 271 def : Processor<"620", G3Itineraries, [Directive620,
 272                                        FeatureFRES, FeatureFRSQRTE]>;
 273 def : Processor<"750", G4Itineraries, [Directive750,
 274                                        FeatureFRES, FeatureFRSQRTE]>;
 275 def : Processor<"g3", G3Itineraries, [Directive750,
 276                                       FeatureFRES, FeatureFRSQRTE]>;
 277 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 278                                         FeatureFRES, FeatureFRSQRTE]>;
 279 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 280                                       FeatureFRES, FeatureFRSQRTE]>;
 281 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 282                                             FeatureFRES, FeatureFRSQRTE]>;
 283 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 284                                            FeatureFRES, FeatureFRSQRTE]>;
 285
 286 def : ProcessorModel<"970", G5Model,
 287                   [Directive970, FeatureAltivec,
 288                    FeatureMFOCRF, FeatureFSqrt,
 289                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 290                    Feature64Bit /*, Feature64BitRegs */]>;
 291 def : ProcessorModel<"g5", G5Model,
 292                   [Directive970, FeatureAltivec,
 293                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 294                    FeatureFRES, FeatureFRSQRTE,
 295                    Feature64Bit /*, Feature64BitRegs */,
 296                    DeprecatedMFTB, DeprecatedDST]>;
 297 def : ProcessorModel<"e500mc", PPCE500mcModel,
 298                   [DirectiveE500mc, FeatureMFOCRF,
 299                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 300                    FeatureISEL, DeprecatedMFTB]>;
 301 def : ProcessorModel<"e5500", PPCE5500Model,
 302                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 303                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 304                    FeatureISEL, DeprecatedMFTB]>;
 305 def : ProcessorModel<"a2", PPCA2Model,
 306                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 307                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 308                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 309                    FeatureSTFIWX, FeatureLFIWAX,
 310                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 311                    FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
 312                /*, Feature64BitRegs */, DeprecatedMFTB]>;
 313 def : ProcessorModel<"a2q", PPCA2Model,
 314                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 315                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 316                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 317                    FeatureSTFIWX, FeatureLFIWAX,
 318                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 319                    FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
 320                /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
 321 def : ProcessorModel<"pwr3", G5Model,
 322                   [DirectivePwr3, FeatureAltivec,
 323                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 324                    FeatureSTFIWX, Feature64Bit]>;
 325 def : ProcessorModel<"pwr4", G5Model,
 326                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 327                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 328                    FeatureSTFIWX, Feature64Bit]>;
 329 def : ProcessorModel<"pwr5", G5Model,
 330                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 331                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 332                    FeatureFRSQRTE, FeatureFRSQRTES,
 333                    FeatureSTFIWX, Feature64Bit,
 334                    DeprecatedMFTB, DeprecatedDST]>;
 335 def : ProcessorModel<"pwr5x", G5Model,
 336                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 337                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 338                    FeatureFRSQRTE, FeatureFRSQRTES,
 339                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 340                    DeprecatedMFTB, DeprecatedDST]>;
 341 def : ProcessorModel<"pwr6", G5Model,
 342                   [DirectivePwr6, FeatureAltivec,
 343                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 344                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 345                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 346                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 347                    DeprecatedMFTB, DeprecatedDST]>;
 348 def : ProcessorModel<"pwr6x", G5Model,
 349                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 350                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 351                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 352                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 353                    FeatureFPRND, Feature64Bit,
 354                    DeprecatedMFTB, DeprecatedDST]>;
 355 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
 356 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
 357 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 358 def : ProcessorModel<"ppc64", G5Model,
 359                   [Directive64, FeatureAltivec,
 360                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 361                    FeatureFRSQRTE, FeatureSTFIWX,
 362                    Feature64Bit /*, Feature64BitRegs */]>;
 363 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
 364
 365 //===----------------------------------------------------------------------===//
 366 // Calling Conventions
 367 //===----------------------------------------------------------------------===//
 368
 369 include "PPCCallingConv.td"
 370
 371 def PPCInstrInfo : InstrInfo {
 372   let isLittleEndianEncoding = 1;
 373
 374   // FIXME: Unset this when no longer needed!
 375   let decodePositionallyEncodedOperands = 1;
 376
 377   let noNamedPositionallyEncodedOperands = 1;
 378 }
 379
 380 def PPCAsmParser : AsmParser {
 381   let ShouldEmitMatchRegisterName = 0;
 382 }
 383
 384 def PPCAsmParserVariant : AsmParserVariant {
 385   int Variant = 0;
 386
 387   // We do not use hard coded registers in asm strings.  However, some
 388   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 389   // so that those are not misinterpreted as registers.
 390   string RegisterPrefix = "%";
 391 }
 392
 393 def PPC : Target {
 394   // Information about the instructions.
 395   let InstructionSet = PPCInstrInfo;
 396
 397   let AssemblyParsers = [PPCAsmParser];
 398   let AssemblyParserVariants = [PPCAsmParserVariant];
 399 }