1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCBaseInfo.h"
17 #include "MCTargetDesc/PPCFixupKinds.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
28 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
31 class PPCMCCodeEmitter : public MCCodeEmitter {
32 PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
33 void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
35 const MCSubtargetInfo &STI;
39 PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
41 : STI(sti), TT(STI.getTargetTriple()) {
44 ~PPCMCCodeEmitter() {}
46 bool is64BitMode() const {
47 return (STI.getFeatureBits() & PPC::Feature64Bit) != 0;
50 bool isSVR4ABI() const {
51 return TT.isMacOSX() == 0;
54 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
55 SmallVectorImpl<MCFixup> &Fixups) const;
56 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
57 SmallVectorImpl<MCFixup> &Fixups) const;
58 unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
59 SmallVectorImpl<MCFixup> &Fixups) const;
60 unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
61 SmallVectorImpl<MCFixup> &Fixups) const;
62 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
63 SmallVectorImpl<MCFixup> &Fixups) const;
64 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
65 SmallVectorImpl<MCFixup> &Fixups) const;
66 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
67 SmallVectorImpl<MCFixup> &Fixups) const;
68 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
69 SmallVectorImpl<MCFixup> &Fixups) const;
71 /// getMachineOpValue - Return binary encoding of operand. If the machine
72 /// operand requires relocation, record the relocation and return zero.
73 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
74 SmallVectorImpl<MCFixup> &Fixups) const;
76 // getBinaryCodeForInstr - TableGen'erated function for getting the
77 // binary encoding for an instruction.
78 uint64_t getBinaryCodeForInstr(const MCInst &MI,
79 SmallVectorImpl<MCFixup> &Fixups) const;
80 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
81 SmallVectorImpl<MCFixup> &Fixups) const {
82 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
84 // BL8_NOP etc. all have a size of 8 because of the following 'nop'.
85 unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
86 unsigned Opcode = MI.getOpcode();
87 if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
88 Opcode == PPC::BL8_NOP_TLSGD || Opcode == PPC::BL8_NOP_TLSLD)
91 // Output the constant in big endian byte order.
92 int ShiftValue = (Size * 8) - 8;
93 for (unsigned i = 0; i != Size; ++i) {
94 OS << (char)(Bits >> ShiftValue);
98 ++MCNumEmitted; // Keep track of the # of mi's emitted.
103 } // end anonymous namespace
105 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
106 const MCRegisterInfo &MRI,
107 const MCSubtargetInfo &STI,
109 return new PPCMCCodeEmitter(MCII, STI, Ctx);
112 unsigned PPCMCCodeEmitter::
113 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
114 SmallVectorImpl<MCFixup> &Fixups) const {
115 const MCOperand &MO = MI.getOperand(OpNo);
116 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
118 // Add a fixup for the branch target.
119 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
120 (MCFixupKind)PPC::fixup_ppc_br24));
122 // For special TLS calls, add another fixup for the symbol. Apparently
123 // BL8_NOP, BL8_NOP_TLSGD, and BL8_NOP_TLSLD are sufficiently
124 // similar that TblGen will not generate a separate case for the latter
125 // two, so this is the only way to get the extra fixup generated.
126 unsigned Opcode = MI.getOpcode();
127 if (Opcode == PPC::BL8_NOP_TLSGD || Opcode == PPC::BL8_NOP_TLSLD) {
128 const MCOperand &MO2 = MI.getOperand(OpNo+1);
129 Fixups.push_back(MCFixup::Create(0, MO2.getExpr(),
130 (MCFixupKind)PPC::fixup_ppc_nofixup));
135 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
136 SmallVectorImpl<MCFixup> &Fixups) const {
137 const MCOperand &MO = MI.getOperand(OpNo);
138 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
140 // Add a fixup for the branch target.
141 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
142 (MCFixupKind)PPC::fixup_ppc_brcond14));
146 unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
147 SmallVectorImpl<MCFixup> &Fixups) const {
148 const MCOperand &MO = MI.getOperand(OpNo);
149 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
151 // Add a fixup for the branch target.
152 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
153 (MCFixupKind)PPC::fixup_ppc_ha16));
157 unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
158 SmallVectorImpl<MCFixup> &Fixups) const {
159 const MCOperand &MO = MI.getOperand(OpNo);
160 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
162 // Add a fixup for the branch target.
163 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
164 (MCFixupKind)PPC::fixup_ppc_lo16));
168 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
169 SmallVectorImpl<MCFixup> &Fixups) const {
170 // Encode (imm, reg) as a memri, which has the low 16-bits as the
171 // displacement and the next 5 bits as the register #.
172 assert(MI.getOperand(OpNo+1).isReg());
173 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
175 const MCOperand &MO = MI.getOperand(OpNo);
177 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
179 // Add a fixup for the displacement field.
180 if (isSVR4ABI() && is64BitMode())
181 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
182 (MCFixupKind)PPC::fixup_ppc_toc16));
184 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
185 (MCFixupKind)PPC::fixup_ppc_lo16));
190 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
191 SmallVectorImpl<MCFixup> &Fixups) const {
192 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
193 // displacement and the next 5 bits as the register #.
194 assert(MI.getOperand(OpNo+1).isReg());
195 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
197 const MCOperand &MO = MI.getOperand(OpNo);
199 return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
201 // Add a fixup for the branch target.
202 if (isSVR4ABI() && is64BitMode())
203 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
204 (MCFixupKind)PPC::fixup_ppc_toc16_ds));
206 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
207 (MCFixupKind)PPC::fixup_ppc_lo14));
212 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
213 SmallVectorImpl<MCFixup> &Fixups) const {
214 const MCOperand &MO = MI.getOperand(OpNo);
215 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
217 // Add a fixup for the TLS register, which simply provides a relocation
218 // hint to the linker that this statement is part of a relocation sequence.
219 // Return the thread-pointer register's encoding.
220 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
221 (MCFixupKind)PPC::fixup_ppc_tlsreg));
222 return getPPCRegisterNumbering(PPC::X13);
225 unsigned PPCMCCodeEmitter::
226 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
227 SmallVectorImpl<MCFixup> &Fixups) const {
228 const MCOperand &MO = MI.getOperand(OpNo);
229 assert((MI.getOpcode() == PPC::MTCRF ||
230 MI.getOpcode() == PPC::MFOCRF ||
231 MI.getOpcode() == PPC::MTCRF8) &&
232 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
233 return 0x80 >> getPPCRegisterNumbering(MO.getReg());
237 unsigned PPCMCCodeEmitter::
238 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
239 SmallVectorImpl<MCFixup> &Fixups) const {
241 // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
242 // The GPR operand should come through here though.
243 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
244 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
245 return getPPCRegisterNumbering(MO.getReg());
249 "Relocation required in an instruction that we cannot encode!");
254 #include "PPCGenMCCodeEmitter.inc"