1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an PPC MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "PPCInstPrinter.h"
16 #include "MCTargetDesc/PPCBaseInfo.h"
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/raw_ostream.h"
23 #define GET_INSTRUCTION_NAME
24 #include "PPCGenAsmWriter.inc"
26 StringRef PPCInstPrinter::getOpcodeName(unsigned Opcode) const {
27 return getInstructionName(Opcode);
30 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
31 OS << getRegisterName(RegNo);
34 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
36 // Check for slwi/srwi mnemonics.
37 if (MI->getOpcode() == PPC::RLWINM) {
38 unsigned char SH = MI->getOperand(2).getImm();
39 unsigned char MB = MI->getOperand(3).getImm();
40 unsigned char ME = MI->getOperand(4).getImm();
41 bool useSubstituteMnemonic = false;
42 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
43 O << "\tslwi "; useSubstituteMnemonic = true;
45 if (SH <= 31 && MB == (32-SH) && ME == 31) {
46 O << "\tsrwi "; useSubstituteMnemonic = true;
49 if (useSubstituteMnemonic) {
50 printOperand(MI, 0, O);
52 printOperand(MI, 1, O);
53 O << ", " << (unsigned int)SH;
55 if (CommentStream) printAnnotation(O, Annot);
60 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
61 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
63 printOperand(MI, 0, O);
65 printOperand(MI, 1, O);
66 if (CommentStream) printAnnotation(O, Annot);
70 if (MI->getOpcode() == PPC::RLDICR) {
71 unsigned char SH = MI->getOperand(2).getImm();
72 unsigned char ME = MI->getOperand(3).getImm();
73 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
76 printOperand(MI, 0, O);
78 printOperand(MI, 1, O);
79 O << ", " << (unsigned int)SH;
80 if (CommentStream) printAnnotation(O, Annot);
85 printInstruction(MI, O);
86 if (CommentStream) printAnnotation(O, Annot);
90 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
92 const char *Modifier) {
93 assert(Modifier && "Must specify 'cc' or 'reg' as predicate op modifier!");
94 unsigned Code = MI->getOperand(OpNo).getImm();
95 if (StringRef(Modifier) == "cc") {
96 switch ((PPC::Predicate)Code) {
97 default: assert(0 && "Invalid predicate");
98 case PPC::PRED_ALWAYS: return; // Don't print anything for always.
99 case PPC::PRED_LT: O << "lt"; return;
100 case PPC::PRED_LE: O << "le"; return;
101 case PPC::PRED_EQ: O << "eq"; return;
102 case PPC::PRED_GE: O << "ge"; return;
103 case PPC::PRED_GT: O << "gt"; return;
104 case PPC::PRED_NE: O << "ne"; return;
105 case PPC::PRED_UN: O << "un"; return;
106 case PPC::PRED_NU: O << "nu"; return;
110 assert(StringRef(Modifier) == "reg" &&
111 "Need to specify 'cc' or 'reg' as predicate op modifier!");
112 // Don't print the register for 'always'.
113 if (Code == PPC::PRED_ALWAYS) return;
114 printOperand(MI, OpNo+1, O);
117 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
119 char Value = MI->getOperand(OpNo).getImm();
120 Value = (Value << (32-5)) >> (32-5);
124 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
126 unsigned char Value = MI->getOperand(OpNo).getImm();
127 assert(Value <= 31 && "Invalid u5imm argument!");
128 O << (unsigned int)Value;
131 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
133 unsigned char Value = MI->getOperand(OpNo).getImm();
134 assert(Value <= 63 && "Invalid u6imm argument!");
135 O << (unsigned int)Value;
138 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
140 O << (short)MI->getOperand(OpNo).getImm();
143 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
145 O << (unsigned short)MI->getOperand(OpNo).getImm();
148 void PPCInstPrinter::printS16X4ImmOperand(const MCInst *MI, unsigned OpNo,
150 if (MI->getOperand(OpNo).isImm())
151 O << (short)(MI->getOperand(OpNo).getImm()*4);
153 printOperand(MI, OpNo, O);
156 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
158 if (!MI->getOperand(OpNo).isImm())
159 return printOperand(MI, OpNo, O);
161 // Branches can take an immediate operand. This is used by the branch
162 // selection pass to print $+8, an eight byte displacement from the PC.
164 printAbsAddrOperand(MI, OpNo, O);
167 void PPCInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,
169 O << (int)MI->getOperand(OpNo).getImm()*4;
173 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
175 unsigned CCReg = MI->getOperand(OpNo).getReg();
178 default: assert(0 && "Unknown CR register");
179 case PPC::CR0: RegNo = 0; break;
180 case PPC::CR1: RegNo = 1; break;
181 case PPC::CR2: RegNo = 2; break;
182 case PPC::CR3: RegNo = 3; break;
183 case PPC::CR4: RegNo = 4; break;
184 case PPC::CR5: RegNo = 5; break;
185 case PPC::CR6: RegNo = 6; break;
186 case PPC::CR7: RegNo = 7; break;
188 O << (0x80 >> RegNo);
191 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
193 printSymbolLo(MI, OpNo, O);
195 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
198 printOperand(MI, OpNo+1, O);
202 void PPCInstPrinter::printMemRegImmShifted(const MCInst *MI, unsigned OpNo,
204 if (MI->getOperand(OpNo).isImm())
205 printS16X4ImmOperand(MI, OpNo, O);
207 printSymbolLo(MI, OpNo, O);
210 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
213 printOperand(MI, OpNo+1, O);
218 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
220 // When used as the base register, r0 reads constant zero rather than
221 // the value contained in the register. For this reason, the darwin
222 // assembler requires that we print r0 as 0 (no r) when used as the base.
223 if (MI->getOperand(OpNo).getReg() == PPC::R0)
226 printOperand(MI, OpNo, O);
228 printOperand(MI, OpNo+1, O);
233 /// stripRegisterPrefix - This method strips the character prefix from a
234 /// register name so that only the number is left. Used by for linux asm.
235 static const char *stripRegisterPrefix(const char *RegName) {
236 switch (RegName[0]) {
239 case 'v': return RegName + 1;
240 case 'c': if (RegName[1] == 'r') return RegName + 2;
246 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
248 const MCOperand &Op = MI->getOperand(OpNo);
250 const char *RegName = getRegisterName(Op.getReg());
251 // The linux and AIX assembler does not take register prefixes.
252 if (!isDarwinSyntax())
253 RegName = stripRegisterPrefix(RegName);
264 assert(Op.isExpr() && "unknown operand kind in printOperand");
268 void PPCInstPrinter::printSymbolLo(const MCInst *MI, unsigned OpNo,
270 if (MI->getOperand(OpNo).isImm())
271 return printS16ImmOperand(MI, OpNo, O);
273 // FIXME: This is a terrible hack because we can't encode lo16() as an operand
274 // flag of a subtraction. See the FIXME in GetSymbolRef in PPCMCInstLower.
275 if (MI->getOperand(OpNo).isExpr() &&
276 isa<MCBinaryExpr>(MI->getOperand(OpNo).getExpr())) {
278 printOperand(MI, OpNo, O);
281 printOperand(MI, OpNo, O);
285 void PPCInstPrinter::printSymbolHi(const MCInst *MI, unsigned OpNo,
287 if (MI->getOperand(OpNo).isImm())
288 return printS16ImmOperand(MI, OpNo, O);
290 // FIXME: This is a terrible hack because we can't encode lo16() as an operand
291 // flag of a subtraction. See the FIXME in GetSymbolRef in PPCMCInstLower.
292 if (MI->getOperand(OpNo).isExpr() &&
293 isa<MCBinaryExpr>(MI->getOperand(OpNo).getExpr())) {
295 printOperand(MI, OpNo, O);
298 printOperand(MI, OpNo, O);