1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSymbolELF.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MCTargetAsmParser.h"
30 #include "llvm/Support/SourceMgr.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
36 static const MCPhysReg RRegs[32] = {
37 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
38 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
39 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
40 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44 PPC::R28, PPC::R29, PPC::R30, PPC::R31
46 static const MCPhysReg RRegsNoR0[32] = {
48 PPC::R1, PPC::R2, PPC::R3,
49 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
50 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
51 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55 PPC::R28, PPC::R29, PPC::R30, PPC::R31
57 static const MCPhysReg XRegs[32] = {
58 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
59 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
60 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
61 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65 PPC::X28, PPC::X29, PPC::X30, PPC::X31
67 static const MCPhysReg XRegsNoX0[32] = {
69 PPC::X1, PPC::X2, PPC::X3,
70 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
71 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
72 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76 PPC::X28, PPC::X29, PPC::X30, PPC::X31
78 static const MCPhysReg FRegs[32] = {
79 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
80 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
81 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
82 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86 PPC::F28, PPC::F29, PPC::F30, PPC::F31
88 static const MCPhysReg VRegs[32] = {
89 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
90 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
91 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
92 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96 PPC::V28, PPC::V29, PPC::V30, PPC::V31
98 static const MCPhysReg VSRegs[64] = {
99 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
100 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
101 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
102 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
108 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
109 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
110 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
111 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
117 static const MCPhysReg VSFRegs[64] = {
118 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
119 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
120 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
121 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
127 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
128 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
129 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
130 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
136 static const MCPhysReg VSSRegs[64] = {
137 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
138 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
139 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
140 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
141 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
142 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
143 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
144 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
146 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
147 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
148 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
149 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
150 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
151 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
152 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
153 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
155 static unsigned QFRegs[32] = {
156 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
157 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
158 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
159 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
160 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
161 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
162 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
163 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
165 static const MCPhysReg CRBITRegs[32] = {
166 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
167 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
168 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
169 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
170 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
171 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
172 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
173 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
175 static const MCPhysReg CRRegs[8] = {
176 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
177 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
180 // Evaluate an expression containing condition register
181 // or condition register field symbols. Returns positive
182 // value on success, or -1 on error.
184 EvaluateCRExpr(const MCExpr *E) {
185 switch (E->getKind()) {
189 case MCExpr::Constant: {
190 int64_t Res = cast<MCConstantExpr>(E)->getValue();
191 return Res < 0 ? -1 : Res;
194 case MCExpr::SymbolRef: {
195 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
196 StringRef Name = SRE->getSymbol().getName();
198 if (Name == "lt") return 0;
199 if (Name == "gt") return 1;
200 if (Name == "eq") return 2;
201 if (Name == "so") return 3;
202 if (Name == "un") return 3;
204 if (Name == "cr0") return 0;
205 if (Name == "cr1") return 1;
206 if (Name == "cr2") return 2;
207 if (Name == "cr3") return 3;
208 if (Name == "cr4") return 4;
209 if (Name == "cr5") return 5;
210 if (Name == "cr6") return 6;
211 if (Name == "cr7") return 7;
219 case MCExpr::Binary: {
220 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
221 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
222 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
225 if (LHSVal < 0 || RHSVal < 0)
228 switch (BE->getOpcode()) {
230 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
231 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
234 return Res < 0 ? -1 : Res;
238 llvm_unreachable("Invalid expression kind!");
245 class PPCAsmParser : public MCTargetAsmParser {
246 MCSubtargetInfo &STI;
247 const MCInstrInfo &MII;
251 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
252 bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
254 bool isPPC64() const { return IsPPC64; }
255 bool isDarwin() const { return IsDarwin; }
257 bool MatchRegisterName(const AsmToken &Tok,
258 unsigned &RegNo, int64_t &IntVal);
260 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
262 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
263 PPCMCExpr::VariantKind &Variant);
264 const MCExpr *FixupVariantKind(const MCExpr *E);
265 bool ParseExpression(const MCExpr *&EVal);
266 bool ParseDarwinExpression(const MCExpr *&EVal);
268 bool ParseOperand(OperandVector &Operands);
270 bool ParseDirectiveWord(unsigned Size, SMLoc L);
271 bool ParseDirectiveTC(unsigned Size, SMLoc L);
272 bool ParseDirectiveMachine(SMLoc L);
273 bool ParseDarwinDirectiveMachine(SMLoc L);
274 bool ParseDirectiveAbiVersion(SMLoc L);
275 bool ParseDirectiveLocalEntry(SMLoc L);
277 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
278 OperandVector &Operands, MCStreamer &Out,
280 FeatureBitset &ErrorMissingFeature,
281 bool MatchingInlineAsm) override;
283 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
285 /// @name Auto-generated Match Functions
288 #define GET_ASSEMBLER_HEADER
289 #include "PPCGenAsmMatcher.inc"
295 PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &, const MCInstrInfo &MII,
296 const MCTargetOptions &Options)
297 : MCTargetAsmParser(), STI(STI), MII(MII) {
298 // Check for 64-bit vs. 32-bit pointer mode.
299 Triple TheTriple(STI.getTargetTriple());
300 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
301 TheTriple.getArch() == Triple::ppc64le);
302 IsDarwin = TheTriple.isMacOSX();
303 // Initialize the set of available features.
304 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
307 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
308 SMLoc NameLoc, OperandVector &Operands) override;
310 bool ParseDirective(AsmToken DirectiveID) override;
312 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
313 unsigned Kind) override;
315 const MCExpr *applyModifierToExpr(const MCExpr *E,
316 MCSymbolRefExpr::VariantKind,
317 MCContext &Ctx) override;
320 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
322 struct PPCOperand : public MCParsedAsmOperand {
331 SMLoc StartLoc, EndLoc;
345 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
349 const MCSymbolRefExpr *Sym;
356 struct TLSRegOp TLSReg;
359 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
361 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
363 StartLoc = o.StartLoc;
371 case ContextImmediate:
383 /// getStartLoc - Get the location of the first token of this operand.
384 SMLoc getStartLoc() const override { return StartLoc; }
386 /// getEndLoc - Get the location of the last token of this operand.
387 SMLoc getEndLoc() const override { return EndLoc; }
389 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
390 bool isPPC64() const { return IsPPC64; }
392 int64_t getImm() const {
393 assert(Kind == Immediate && "Invalid access!");
396 int64_t getImmS16Context() const {
397 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
398 if (Kind == Immediate)
400 return static_cast<int16_t>(Imm.Val);
402 int64_t getImmU16Context() const {
403 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
407 const MCExpr *getExpr() const {
408 assert(Kind == Expression && "Invalid access!");
412 int64_t getExprCRVal() const {
413 assert(Kind == Expression && "Invalid access!");
417 const MCExpr *getTLSReg() const {
418 assert(Kind == TLSRegister && "Invalid access!");
422 unsigned getReg() const override {
423 assert(isRegNumber() && "Invalid access!");
424 return (unsigned) Imm.Val;
427 unsigned getVSReg() const {
428 assert(isVSRegNumber() && "Invalid access!");
429 return (unsigned) Imm.Val;
432 unsigned getCCReg() const {
433 assert(isCCRegNumber() && "Invalid access!");
434 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
437 unsigned getCRBit() const {
438 assert(isCRBitNumber() && "Invalid access!");
439 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
442 unsigned getCRBitMask() const {
443 assert(isCRBitMask() && "Invalid access!");
444 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
447 bool isToken() const override { return Kind == Token; }
448 bool isImm() const override { return Kind == Immediate || Kind == Expression; }
449 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
450 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
451 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
452 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
453 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
454 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
455 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
456 bool isU6ImmX2() const { return Kind == Immediate &&
457 isUInt<6>(getImm()) &&
458 (getImm() & 1) == 0; }
459 bool isU7ImmX4() const { return Kind == Immediate &&
460 isUInt<7>(getImm()) &&
461 (getImm() & 3) == 0; }
462 bool isU8ImmX8() const { return Kind == Immediate &&
463 isUInt<8>(getImm()) &&
464 (getImm() & 7) == 0; }
466 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
467 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
468 bool isU16Imm() const {
473 case ContextImmediate:
474 return isUInt<16>(getImmU16Context());
479 bool isS16Imm() const {
484 case ContextImmediate:
485 return isInt<16>(getImmS16Context());
490 bool isS16ImmX4() const { return Kind == Expression ||
491 (Kind == Immediate && isInt<16>(getImm()) &&
492 (getImm() & 3) == 0); }
493 bool isS17Imm() const {
498 case ContextImmediate:
499 return isInt<17>(getImmS16Context());
504 bool isTLSReg() const { return Kind == TLSRegister; }
505 bool isDirectBr() const {
506 if (Kind == Expression)
508 if (Kind != Immediate)
510 // Operand must be 64-bit aligned, signed 27-bit immediate.
511 if ((getImm() & 3) != 0)
513 if (isInt<26>(getImm()))
516 // In 32-bit mode, large 32-bit quantities wrap around.
517 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
522 bool isCondBr() const { return Kind == Expression ||
523 (Kind == Immediate && isInt<16>(getImm()) &&
524 (getImm() & 3) == 0); }
525 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
526 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
527 bool isCCRegNumber() const { return (Kind == Expression
528 && isUInt<3>(getExprCRVal())) ||
530 && isUInt<3>(getImm())); }
531 bool isCRBitNumber() const { return (Kind == Expression
532 && isUInt<5>(getExprCRVal())) ||
534 && isUInt<5>(getImm())); }
535 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
536 isPowerOf2_32(getImm()); }
537 bool isMem() const override { return false; }
538 bool isReg() const override { return false; }
540 void addRegOperands(MCInst &Inst, unsigned N) const {
541 llvm_unreachable("addRegOperands");
544 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
545 assert(N == 1 && "Invalid number of operands!");
546 Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
549 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
550 assert(N == 1 && "Invalid number of operands!");
551 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
554 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
555 assert(N == 1 && "Invalid number of operands!");
556 Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
559 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
560 assert(N == 1 && "Invalid number of operands!");
561 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
564 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
566 addRegG8RCOperands(Inst, N);
568 addRegGPRCOperands(Inst, N);
571 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
573 addRegG8RCNoX0Operands(Inst, N);
575 addRegGPRCNoR0Operands(Inst, N);
578 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
579 assert(N == 1 && "Invalid number of operands!");
580 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
583 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
584 assert(N == 1 && "Invalid number of operands!");
585 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
588 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
589 assert(N == 1 && "Invalid number of operands!");
590 Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
593 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
594 assert(N == 1 && "Invalid number of operands!");
595 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
598 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
599 assert(N == 1 && "Invalid number of operands!");
600 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
603 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
604 assert(N == 1 && "Invalid number of operands!");
605 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
608 void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
609 assert(N == 1 && "Invalid number of operands!");
610 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
613 void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
614 assert(N == 1 && "Invalid number of operands!");
615 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
618 void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
619 assert(N == 1 && "Invalid number of operands!");
620 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
623 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
624 assert(N == 1 && "Invalid number of operands!");
625 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
628 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
629 assert(N == 1 && "Invalid number of operands!");
630 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
633 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
634 assert(N == 1 && "Invalid number of operands!");
635 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
638 void addImmOperands(MCInst &Inst, unsigned N) const {
639 assert(N == 1 && "Invalid number of operands!");
640 if (Kind == Immediate)
641 Inst.addOperand(MCOperand::createImm(getImm()));
643 Inst.addOperand(MCOperand::createExpr(getExpr()));
646 void addS16ImmOperands(MCInst &Inst, unsigned N) const {
647 assert(N == 1 && "Invalid number of operands!");
650 Inst.addOperand(MCOperand::createImm(getImm()));
652 case ContextImmediate:
653 Inst.addOperand(MCOperand::createImm(getImmS16Context()));
656 Inst.addOperand(MCOperand::createExpr(getExpr()));
661 void addU16ImmOperands(MCInst &Inst, unsigned N) const {
662 assert(N == 1 && "Invalid number of operands!");
665 Inst.addOperand(MCOperand::createImm(getImm()));
667 case ContextImmediate:
668 Inst.addOperand(MCOperand::createImm(getImmU16Context()));
671 Inst.addOperand(MCOperand::createExpr(getExpr()));
676 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
677 assert(N == 1 && "Invalid number of operands!");
678 if (Kind == Immediate)
679 Inst.addOperand(MCOperand::createImm(getImm() / 4));
681 Inst.addOperand(MCOperand::createExpr(getExpr()));
684 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
685 assert(N == 1 && "Invalid number of operands!");
686 Inst.addOperand(MCOperand::createExpr(getTLSReg()));
689 StringRef getToken() const {
690 assert(Kind == Token && "Invalid access!");
691 return StringRef(Tok.Data, Tok.Length);
694 void print(raw_ostream &OS) const override;
696 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
698 auto Op = make_unique<PPCOperand>(Token);
699 Op->Tok.Data = Str.data();
700 Op->Tok.Length = Str.size();
703 Op->IsPPC64 = IsPPC64;
707 static std::unique_ptr<PPCOperand>
708 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
709 // Allocate extra memory for the string and copy it.
710 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
711 // deleter which will destroy them by simply using "delete", not correctly
712 // calling operator delete on this extra memory after calling the dtor
714 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
715 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
716 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
717 Op->Tok.Length = Str.size();
718 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
721 Op->IsPPC64 = IsPPC64;
725 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
727 auto Op = make_unique<PPCOperand>(Immediate);
731 Op->IsPPC64 = IsPPC64;
735 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
736 SMLoc E, bool IsPPC64) {
737 auto Op = make_unique<PPCOperand>(Expression);
739 Op->Expr.CRVal = EvaluateCRExpr(Val);
742 Op->IsPPC64 = IsPPC64;
746 static std::unique_ptr<PPCOperand>
747 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
748 auto Op = make_unique<PPCOperand>(TLSRegister);
749 Op->TLSReg.Sym = Sym;
752 Op->IsPPC64 = IsPPC64;
756 static std::unique_ptr<PPCOperand>
757 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
758 auto Op = make_unique<PPCOperand>(ContextImmediate);
762 Op->IsPPC64 = IsPPC64;
766 static std::unique_ptr<PPCOperand>
767 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
768 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
769 return CreateImm(CE->getValue(), S, E, IsPPC64);
771 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
772 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
773 return CreateTLSReg(SRE, S, E, IsPPC64);
775 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
777 if (TE->evaluateAsConstant(Res))
778 return CreateContextImm(Res, S, E, IsPPC64);
781 return CreateExpr(Val, S, E, IsPPC64);
785 } // end anonymous namespace.
787 void PPCOperand::print(raw_ostream &OS) const {
790 OS << "'" << getToken() << "'";
793 case ContextImmediate:
806 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
808 Inst.addOperand(MCOperand::createImm(-Op.getImm()));
811 const MCExpr *Expr = Op.getExpr();
812 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
813 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
814 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
817 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
818 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
819 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
820 BinExpr->getLHS(), Ctx);
821 Inst.addOperand(MCOperand::createExpr(NE));
825 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
828 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
829 const OperandVector &Operands) {
830 int Opcode = Inst.getOpcode();
837 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
838 PPC::DCBT : PPC::DCBTST);
839 TmpInst.addOperand(MCOperand::createImm(
840 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
841 TmpInst.addOperand(Inst.getOperand(0));
842 TmpInst.addOperand(Inst.getOperand(1));
849 TmpInst.setOpcode(PPC::DCBT);
850 TmpInst.addOperand(Inst.getOperand(2));
851 TmpInst.addOperand(Inst.getOperand(0));
852 TmpInst.addOperand(Inst.getOperand(1));
857 case PPC::DCBTSTDS: {
859 TmpInst.setOpcode(PPC::DCBTST);
860 TmpInst.addOperand(Inst.getOperand(2));
861 TmpInst.addOperand(Inst.getOperand(0));
862 TmpInst.addOperand(Inst.getOperand(1));
868 TmpInst.setOpcode(PPC::LA);
869 TmpInst.addOperand(Inst.getOperand(0));
870 TmpInst.addOperand(Inst.getOperand(2));
871 TmpInst.addOperand(Inst.getOperand(1));
877 TmpInst.setOpcode(PPC::ADDI);
878 TmpInst.addOperand(Inst.getOperand(0));
879 TmpInst.addOperand(Inst.getOperand(1));
880 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
886 TmpInst.setOpcode(PPC::ADDIS);
887 TmpInst.addOperand(Inst.getOperand(0));
888 TmpInst.addOperand(Inst.getOperand(1));
889 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
895 TmpInst.setOpcode(PPC::ADDIC);
896 TmpInst.addOperand(Inst.getOperand(0));
897 TmpInst.addOperand(Inst.getOperand(1));
898 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
904 TmpInst.setOpcode(PPC::ADDICo);
905 TmpInst.addOperand(Inst.getOperand(0));
906 TmpInst.addOperand(Inst.getOperand(1));
907 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
914 int64_t N = Inst.getOperand(2).getImm();
915 int64_t B = Inst.getOperand(3).getImm();
916 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
917 TmpInst.addOperand(Inst.getOperand(0));
918 TmpInst.addOperand(Inst.getOperand(1));
919 TmpInst.addOperand(MCOperand::createImm(B));
920 TmpInst.addOperand(MCOperand::createImm(0));
921 TmpInst.addOperand(MCOperand::createImm(N - 1));
928 int64_t N = Inst.getOperand(2).getImm();
929 int64_t B = Inst.getOperand(3).getImm();
930 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
931 TmpInst.addOperand(Inst.getOperand(0));
932 TmpInst.addOperand(Inst.getOperand(1));
933 TmpInst.addOperand(MCOperand::createImm(B + N));
934 TmpInst.addOperand(MCOperand::createImm(32 - N));
935 TmpInst.addOperand(MCOperand::createImm(31));
942 int64_t N = Inst.getOperand(2).getImm();
943 int64_t B = Inst.getOperand(3).getImm();
944 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
945 TmpInst.addOperand(Inst.getOperand(0));
946 TmpInst.addOperand(Inst.getOperand(0));
947 TmpInst.addOperand(Inst.getOperand(1));
948 TmpInst.addOperand(MCOperand::createImm(32 - B));
949 TmpInst.addOperand(MCOperand::createImm(B));
950 TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
957 int64_t N = Inst.getOperand(2).getImm();
958 int64_t B = Inst.getOperand(3).getImm();
959 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
960 TmpInst.addOperand(Inst.getOperand(0));
961 TmpInst.addOperand(Inst.getOperand(0));
962 TmpInst.addOperand(Inst.getOperand(1));
963 TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
964 TmpInst.addOperand(MCOperand::createImm(B));
965 TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
972 int64_t N = Inst.getOperand(2).getImm();
973 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
974 TmpInst.addOperand(Inst.getOperand(0));
975 TmpInst.addOperand(Inst.getOperand(1));
976 TmpInst.addOperand(MCOperand::createImm(32 - N));
977 TmpInst.addOperand(MCOperand::createImm(0));
978 TmpInst.addOperand(MCOperand::createImm(31));
985 int64_t N = Inst.getOperand(2).getImm();
986 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
987 TmpInst.addOperand(Inst.getOperand(0));
988 TmpInst.addOperand(Inst.getOperand(1));
989 TmpInst.addOperand(MCOperand::createImm(N));
990 TmpInst.addOperand(MCOperand::createImm(0));
991 TmpInst.addOperand(MCOperand::createImm(31 - N));
998 int64_t N = Inst.getOperand(2).getImm();
999 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1000 TmpInst.addOperand(Inst.getOperand(0));
1001 TmpInst.addOperand(Inst.getOperand(1));
1002 TmpInst.addOperand(MCOperand::createImm(32 - N));
1003 TmpInst.addOperand(MCOperand::createImm(N));
1004 TmpInst.addOperand(MCOperand::createImm(31));
1009 case PPC::CLRRWIo: {
1011 int64_t N = Inst.getOperand(2).getImm();
1012 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1013 TmpInst.addOperand(Inst.getOperand(0));
1014 TmpInst.addOperand(Inst.getOperand(1));
1015 TmpInst.addOperand(MCOperand::createImm(0));
1016 TmpInst.addOperand(MCOperand::createImm(0));
1017 TmpInst.addOperand(MCOperand::createImm(31 - N));
1022 case PPC::CLRLSLWIo: {
1024 int64_t B = Inst.getOperand(2).getImm();
1025 int64_t N = Inst.getOperand(3).getImm();
1026 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1027 TmpInst.addOperand(Inst.getOperand(0));
1028 TmpInst.addOperand(Inst.getOperand(1));
1029 TmpInst.addOperand(MCOperand::createImm(N));
1030 TmpInst.addOperand(MCOperand::createImm(B - N));
1031 TmpInst.addOperand(MCOperand::createImm(31 - N));
1036 case PPC::EXTLDIo: {
1038 int64_t N = Inst.getOperand(2).getImm();
1039 int64_t B = Inst.getOperand(3).getImm();
1040 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1041 TmpInst.addOperand(Inst.getOperand(0));
1042 TmpInst.addOperand(Inst.getOperand(1));
1043 TmpInst.addOperand(MCOperand::createImm(B));
1044 TmpInst.addOperand(MCOperand::createImm(N - 1));
1049 case PPC::EXTRDIo: {
1051 int64_t N = Inst.getOperand(2).getImm();
1052 int64_t B = Inst.getOperand(3).getImm();
1053 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1054 TmpInst.addOperand(Inst.getOperand(0));
1055 TmpInst.addOperand(Inst.getOperand(1));
1056 TmpInst.addOperand(MCOperand::createImm(B + N));
1057 TmpInst.addOperand(MCOperand::createImm(64 - N));
1062 case PPC::INSRDIo: {
1064 int64_t N = Inst.getOperand(2).getImm();
1065 int64_t B = Inst.getOperand(3).getImm();
1066 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1067 TmpInst.addOperand(Inst.getOperand(0));
1068 TmpInst.addOperand(Inst.getOperand(0));
1069 TmpInst.addOperand(Inst.getOperand(1));
1070 TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1071 TmpInst.addOperand(MCOperand::createImm(B));
1076 case PPC::ROTRDIo: {
1078 int64_t N = Inst.getOperand(2).getImm();
1079 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1080 TmpInst.addOperand(Inst.getOperand(0));
1081 TmpInst.addOperand(Inst.getOperand(1));
1082 TmpInst.addOperand(MCOperand::createImm(64 - N));
1083 TmpInst.addOperand(MCOperand::createImm(0));
1090 int64_t N = Inst.getOperand(2).getImm();
1091 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1092 TmpInst.addOperand(Inst.getOperand(0));
1093 TmpInst.addOperand(Inst.getOperand(1));
1094 TmpInst.addOperand(MCOperand::createImm(N));
1095 TmpInst.addOperand(MCOperand::createImm(63 - N));
1102 int64_t N = Inst.getOperand(2).getImm();
1103 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1104 TmpInst.addOperand(Inst.getOperand(0));
1105 TmpInst.addOperand(Inst.getOperand(1));
1106 TmpInst.addOperand(MCOperand::createImm(64 - N));
1107 TmpInst.addOperand(MCOperand::createImm(N));
1112 case PPC::CLRRDIo: {
1114 int64_t N = Inst.getOperand(2).getImm();
1115 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1116 TmpInst.addOperand(Inst.getOperand(0));
1117 TmpInst.addOperand(Inst.getOperand(1));
1118 TmpInst.addOperand(MCOperand::createImm(0));
1119 TmpInst.addOperand(MCOperand::createImm(63 - N));
1124 case PPC::CLRLSLDIo: {
1126 int64_t B = Inst.getOperand(2).getImm();
1127 int64_t N = Inst.getOperand(3).getImm();
1128 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1129 TmpInst.addOperand(Inst.getOperand(0));
1130 TmpInst.addOperand(Inst.getOperand(1));
1131 TmpInst.addOperand(MCOperand::createImm(N));
1132 TmpInst.addOperand(MCOperand::createImm(B - N));
1137 case PPC::RLWINMobm: {
1139 int64_t BM = Inst.getOperand(3).getImm();
1140 if (!isRunOfOnes(BM, MB, ME))
1144 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1145 TmpInst.addOperand(Inst.getOperand(0));
1146 TmpInst.addOperand(Inst.getOperand(1));
1147 TmpInst.addOperand(Inst.getOperand(2));
1148 TmpInst.addOperand(MCOperand::createImm(MB));
1149 TmpInst.addOperand(MCOperand::createImm(ME));
1154 case PPC::RLWIMIobm: {
1156 int64_t BM = Inst.getOperand(3).getImm();
1157 if (!isRunOfOnes(BM, MB, ME))
1161 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1162 TmpInst.addOperand(Inst.getOperand(0));
1163 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1164 TmpInst.addOperand(Inst.getOperand(1));
1165 TmpInst.addOperand(Inst.getOperand(2));
1166 TmpInst.addOperand(MCOperand::createImm(MB));
1167 TmpInst.addOperand(MCOperand::createImm(ME));
1172 case PPC::RLWNMobm: {
1174 int64_t BM = Inst.getOperand(3).getImm();
1175 if (!isRunOfOnes(BM, MB, ME))
1179 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1180 TmpInst.addOperand(Inst.getOperand(0));
1181 TmpInst.addOperand(Inst.getOperand(1));
1182 TmpInst.addOperand(Inst.getOperand(2));
1183 TmpInst.addOperand(MCOperand::createImm(MB));
1184 TmpInst.addOperand(MCOperand::createImm(ME));
1189 if (STI.getFeatureBits()[PPC::FeatureMFTB]) {
1190 assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1191 Inst.setOpcode(PPC::MFSPR);
1198 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1199 OperandVector &Operands,
1200 MCStreamer &Out, uint64_t &ErrorInfo,
1201 FeatureBitset &ErrorMissingFeature,
1202 bool MatchingInlineAsm) {
1205 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, ErrorMissingFeature, MatchingInlineAsm)) {
1207 // Post-process instructions (typically extended mnemonics)
1208 ProcessInstruction(Inst, Operands);
1210 Out.EmitInstruction(Inst, STI);
1212 case Match_MissingFeature:
1213 return Error(IDLoc, "instruction use requires an option to be enabled");
1214 case Match_MnemonicFail:
1215 return Error(IDLoc, "unrecognized instruction mnemonic");
1216 case Match_InvalidOperand: {
1217 SMLoc ErrorLoc = IDLoc;
1218 if (ErrorInfo != ~0ULL) {
1219 if (ErrorInfo >= Operands.size())
1220 return Error(IDLoc, "too few operands for instruction");
1222 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1223 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1226 return Error(ErrorLoc, "invalid operand for instruction");
1230 llvm_unreachable("Implement any new match types added!");
1234 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1235 if (Tok.is(AsmToken::Identifier)) {
1236 StringRef Name = Tok.getString();
1238 if (Name.equals_lower("lr")) {
1239 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1242 } else if (Name.equals_lower("ctr")) {
1243 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1246 } else if (Name.equals_lower("vrsave")) {
1247 RegNo = PPC::VRSAVE;
1250 } else if (Name.startswith_lower("r") &&
1251 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1252 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1254 } else if (Name.startswith_lower("f") &&
1255 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1256 RegNo = FRegs[IntVal];
1258 } else if (Name.startswith_lower("vs") &&
1259 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1260 RegNo = VSRegs[IntVal];
1262 } else if (Name.startswith_lower("v") &&
1263 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1264 RegNo = VRegs[IntVal];
1266 } else if (Name.startswith_lower("q") &&
1267 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1268 RegNo = QFRegs[IntVal];
1270 } else if (Name.startswith_lower("cr") &&
1271 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1272 RegNo = CRRegs[IntVal];
1281 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1282 MCAsmParser &Parser = getParser();
1283 const AsmToken &Tok = Parser.getTok();
1284 StartLoc = Tok.getLoc();
1285 EndLoc = Tok.getEndLoc();
1289 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1290 Parser.Lex(); // Eat identifier token.
1294 return Error(StartLoc, "invalid register name");
1297 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1298 /// the expression and check for VK_PPC_LO/HI/HA
1299 /// symbol variants. If all symbols with modifier use the same
1300 /// variant, return the corresponding PPCMCExpr::VariantKind,
1301 /// and a modified expression using the default symbol variant.
1302 /// Otherwise, return NULL.
1303 const MCExpr *PPCAsmParser::
1304 ExtractModifierFromExpr(const MCExpr *E,
1305 PPCMCExpr::VariantKind &Variant) {
1306 MCContext &Context = getParser().getContext();
1307 Variant = PPCMCExpr::VK_PPC_None;
1309 switch (E->getKind()) {
1310 case MCExpr::Target:
1311 case MCExpr::Constant:
1314 case MCExpr::SymbolRef: {
1315 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1317 switch (SRE->getKind()) {
1318 case MCSymbolRefExpr::VK_PPC_LO:
1319 Variant = PPCMCExpr::VK_PPC_LO;
1321 case MCSymbolRefExpr::VK_PPC_HI:
1322 Variant = PPCMCExpr::VK_PPC_HI;
1324 case MCSymbolRefExpr::VK_PPC_HA:
1325 Variant = PPCMCExpr::VK_PPC_HA;
1327 case MCSymbolRefExpr::VK_PPC_HIGHER:
1328 Variant = PPCMCExpr::VK_PPC_HIGHER;
1330 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1331 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1333 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1334 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1336 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1337 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1343 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1346 case MCExpr::Unary: {
1347 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1348 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1351 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1354 case MCExpr::Binary: {
1355 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1356 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1357 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1358 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1363 if (!LHS) LHS = BE->getLHS();
1364 if (!RHS) RHS = BE->getRHS();
1366 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1367 Variant = RHSVariant;
1368 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1369 Variant = LHSVariant;
1370 else if (LHSVariant == RHSVariant)
1371 Variant = LHSVariant;
1375 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1379 llvm_unreachable("Invalid expression kind!");
1382 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1383 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1384 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1385 /// FIXME: This is a hack.
1386 const MCExpr *PPCAsmParser::
1387 FixupVariantKind(const MCExpr *E) {
1388 MCContext &Context = getParser().getContext();
1390 switch (E->getKind()) {
1391 case MCExpr::Target:
1392 case MCExpr::Constant:
1395 case MCExpr::SymbolRef: {
1396 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1397 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1399 switch (SRE->getKind()) {
1400 case MCSymbolRefExpr::VK_TLSGD:
1401 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1403 case MCSymbolRefExpr::VK_TLSLD:
1404 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1409 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1412 case MCExpr::Unary: {
1413 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1414 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1415 if (Sub == UE->getSubExpr())
1417 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1420 case MCExpr::Binary: {
1421 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1422 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1423 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1424 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1426 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1430 llvm_unreachable("Invalid expression kind!");
1433 /// ParseExpression. This differs from the default "parseExpression" in that
1434 /// it handles modifiers.
1436 ParseExpression(const MCExpr *&EVal) {
1439 return ParseDarwinExpression(EVal);
1442 // Handle \code @l/@ha \endcode
1443 if (getParser().parseExpression(EVal))
1446 EVal = FixupVariantKind(EVal);
1448 PPCMCExpr::VariantKind Variant;
1449 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1451 EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1456 /// ParseDarwinExpression. (MachO Platforms)
1457 /// This differs from the default "parseExpression" in that it handles detection
1458 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1459 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1460 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1461 /// for this to be done at a higher level.
1463 ParseDarwinExpression(const MCExpr *&EVal) {
1464 MCAsmParser &Parser = getParser();
1465 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1466 switch (getLexer().getKind()) {
1469 case AsmToken::Identifier:
1470 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1471 // something starting with any other char should be part of the
1472 // asm syntax. If handwritten asm includes an identifier like lo16,
1473 // then all bets are off - but no-one would do that, right?
1474 StringRef poss = Parser.getTok().getString();
1475 if (poss.equals_lower("lo16")) {
1476 Variant = PPCMCExpr::VK_PPC_LO;
1477 } else if (poss.equals_lower("hi16")) {
1478 Variant = PPCMCExpr::VK_PPC_HI;
1479 } else if (poss.equals_lower("ha16")) {
1480 Variant = PPCMCExpr::VK_PPC_HA;
1482 if (Variant != PPCMCExpr::VK_PPC_None) {
1483 Parser.Lex(); // Eat the xx16
1484 if (getLexer().isNot(AsmToken::LParen))
1485 return Error(Parser.getTok().getLoc(), "expected '('");
1486 Parser.Lex(); // Eat the '('
1491 if (getParser().parseExpression(EVal))
1494 if (Variant != PPCMCExpr::VK_PPC_None) {
1495 if (getLexer().isNot(AsmToken::RParen))
1496 return Error(Parser.getTok().getLoc(), "expected ')'");
1497 Parser.Lex(); // Eat the ')'
1498 EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1504 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1506 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1507 MCAsmParser &Parser = getParser();
1508 SMLoc S = Parser.getTok().getLoc();
1509 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1512 // Attempt to parse the next token as an immediate
1513 switch (getLexer().getKind()) {
1514 // Special handling for register names. These are interpreted
1515 // as immediates corresponding to the register number.
1516 case AsmToken::Percent:
1517 Parser.Lex(); // Eat the '%'.
1520 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1521 Parser.Lex(); // Eat the identifier token.
1522 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1525 return Error(S, "invalid register name");
1527 case AsmToken::Identifier:
1528 // Note that non-register-name identifiers from the compiler will begin
1529 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1530 // identifiers like r31foo - so we fall through in the event that parsing
1531 // a register name fails.
1535 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1536 Parser.Lex(); // Eat the identifier token.
1537 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1541 // Fall-through to process non-register-name identifiers as expression.
1542 // All other expressions
1543 case AsmToken::LParen:
1544 case AsmToken::Plus:
1545 case AsmToken::Minus:
1546 case AsmToken::Integer:
1548 case AsmToken::Dollar:
1549 case AsmToken::Exclaim:
1550 case AsmToken::Tilde:
1551 if (!ParseExpression(EVal))
1555 return Error(S, "unknown operand");
1558 // Push the parsed operand into the list of operands
1559 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1561 // Check whether this is a TLS call expression
1562 bool TLSCall = false;
1563 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1564 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1566 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1567 const MCExpr *TLSSym;
1569 Parser.Lex(); // Eat the '('.
1570 S = Parser.getTok().getLoc();
1571 if (ParseExpression(TLSSym))
1572 return Error(S, "invalid TLS call expression");
1573 if (getLexer().isNot(AsmToken::RParen))
1574 return Error(Parser.getTok().getLoc(), "missing ')'");
1575 E = Parser.getTok().getLoc();
1576 Parser.Lex(); // Eat the ')'.
1578 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1581 // Otherwise, check for D-form memory operands
1582 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1583 Parser.Lex(); // Eat the '('.
1584 S = Parser.getTok().getLoc();
1587 switch (getLexer().getKind()) {
1588 case AsmToken::Percent:
1589 Parser.Lex(); // Eat the '%'.
1591 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1592 return Error(S, "invalid register name");
1593 Parser.Lex(); // Eat the identifier token.
1596 case AsmToken::Integer:
1598 if (getParser().parseAbsoluteExpression(IntVal) ||
1599 IntVal < 0 || IntVal > 31)
1600 return Error(S, "invalid register number");
1602 return Error(S, "unexpected integer value");
1606 case AsmToken::Identifier:
1609 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1610 Parser.Lex(); // Eat the identifier token.
1617 return Error(S, "invalid memory operand");
1620 if (getLexer().isNot(AsmToken::RParen))
1621 return Error(Parser.getTok().getLoc(), "missing ')'");
1622 E = Parser.getTok().getLoc();
1623 Parser.Lex(); // Eat the ')'.
1625 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1631 /// Parse an instruction mnemonic followed by its operands.
1632 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1633 SMLoc NameLoc, OperandVector &Operands) {
1634 // The first operand is the token for the instruction name.
1635 // If the next character is a '+' or '-', we need to add it to the
1636 // instruction name, to match what TableGen is doing.
1637 std::string NewOpcode;
1638 if (getLexer().is(AsmToken::Plus)) {
1644 if (getLexer().is(AsmToken::Minus)) {
1650 // If the instruction ends in a '.', we need to create a separate
1651 // token for it, to match what TableGen is doing.
1652 size_t Dot = Name.find('.');
1653 StringRef Mnemonic = Name.slice(0, Dot);
1654 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1656 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1658 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1659 if (Dot != StringRef::npos) {
1660 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1661 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1662 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1664 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1666 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1669 // If there are no more operands then finish
1670 if (getLexer().is(AsmToken::EndOfStatement))
1673 // Parse the first operand
1674 if (ParseOperand(Operands))
1677 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1678 getLexer().is(AsmToken::Comma)) {
1679 // Consume the comma token
1682 // Parse the next operand
1683 if (ParseOperand(Operands))
1687 // We'll now deal with an unfortunate special case: the syntax for the dcbt
1688 // and dcbtst instructions differs for server vs. embedded cores.
1689 // The syntax for dcbt is:
1690 // dcbt ra, rb, th [server]
1691 // dcbt th, ra, rb [embedded]
1692 // where th can be omitted when it is 0. dcbtst is the same. We take the
1693 // server form to be the default, so swap the operands if we're parsing for
1694 // an embedded core (they'll be swapped again upon printing).
1695 if (STI.getFeatureBits()[PPC::FeatureBookE] &&
1696 Operands.size() == 4 &&
1697 (Name == "dcbt" || Name == "dcbtst")) {
1698 std::swap(Operands[1], Operands[3]);
1699 std::swap(Operands[2], Operands[1]);
1705 /// ParseDirective parses the PPC specific directives
1706 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1707 StringRef IDVal = DirectiveID.getIdentifier();
1709 if (IDVal == ".word")
1710 return ParseDirectiveWord(2, DirectiveID.getLoc());
1711 if (IDVal == ".llong")
1712 return ParseDirectiveWord(8, DirectiveID.getLoc());
1714 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1715 if (IDVal == ".machine")
1716 return ParseDirectiveMachine(DirectiveID.getLoc());
1717 if (IDVal == ".abiversion")
1718 return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1719 if (IDVal == ".localentry")
1720 return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1722 if (IDVal == ".machine")
1723 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1728 /// ParseDirectiveWord
1729 /// ::= .word [ expression (, expression)* ]
1730 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1731 MCAsmParser &Parser = getParser();
1732 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1734 const MCExpr *Value;
1735 if (getParser().parseExpression(Value))
1738 getParser().getStreamer().EmitValue(Value, Size);
1740 if (getLexer().is(AsmToken::EndOfStatement))
1743 if (getLexer().isNot(AsmToken::Comma))
1744 return Error(L, "unexpected token in directive");
1753 /// ParseDirectiveTC
1754 /// ::= .tc [ symbol (, expression)* ]
1755 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1756 MCAsmParser &Parser = getParser();
1757 // Skip TC symbol, which is only used with XCOFF.
1758 while (getLexer().isNot(AsmToken::EndOfStatement)
1759 && getLexer().isNot(AsmToken::Comma))
1761 if (getLexer().isNot(AsmToken::Comma)) {
1762 Error(L, "unexpected token in directive");
1767 // Align to word size.
1768 getParser().getStreamer().EmitValueToAlignment(Size);
1770 // Emit expressions.
1771 return ParseDirectiveWord(Size, L);
1774 /// ParseDirectiveMachine (ELF platforms)
1775 /// ::= .machine [ cpu | "push" | "pop" ]
1776 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1777 MCAsmParser &Parser = getParser();
1778 if (getLexer().isNot(AsmToken::Identifier) &&
1779 getLexer().isNot(AsmToken::String)) {
1780 Error(L, "unexpected token in directive");
1784 StringRef CPU = Parser.getTok().getIdentifier();
1787 // FIXME: Right now, the parser always allows any available
1788 // instruction, so the .machine directive is not useful.
1789 // Implement ".machine any" (by doing nothing) for the benefit
1790 // of existing assembler code. Likewise, we can then implement
1791 // ".machine push" and ".machine pop" as no-op.
1792 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1793 Error(L, "unrecognized machine type");
1797 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1798 Error(L, "unexpected token in directive");
1801 PPCTargetStreamer &TStreamer =
1802 *static_cast<PPCTargetStreamer *>(
1803 getParser().getStreamer().getTargetStreamer());
1804 TStreamer.emitMachine(CPU);
1809 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1810 /// ::= .machine cpu-identifier
1811 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1812 MCAsmParser &Parser = getParser();
1813 if (getLexer().isNot(AsmToken::Identifier) &&
1814 getLexer().isNot(AsmToken::String)) {
1815 Error(L, "unexpected token in directive");
1819 StringRef CPU = Parser.getTok().getIdentifier();
1822 // FIXME: this is only the 'default' set of cpu variants.
1823 // However we don't act on this information at present, this is simply
1824 // allowing parsing to proceed with minimal sanity checking.
1825 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1826 Error(L, "unrecognized cpu type");
1830 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1831 Error(L, "wrong cpu type specified for 64bit");
1834 if (!isPPC64() && CPU == "ppc64") {
1835 Error(L, "wrong cpu type specified for 32bit");
1839 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1840 Error(L, "unexpected token in directive");
1847 /// ParseDirectiveAbiVersion
1848 /// ::= .abiversion constant-expression
1849 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1851 if (getParser().parseAbsoluteExpression(AbiVersion)){
1852 Error(L, "expected constant expression");
1855 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1856 Error(L, "unexpected token in directive");
1860 PPCTargetStreamer &TStreamer =
1861 *static_cast<PPCTargetStreamer *>(
1862 getParser().getStreamer().getTargetStreamer());
1863 TStreamer.emitAbiVersion(AbiVersion);
1868 /// ParseDirectiveLocalEntry
1869 /// ::= .localentry symbol, expression
1870 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1872 if (getParser().parseIdentifier(Name)) {
1873 Error(L, "expected identifier in directive");
1876 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1878 if (getLexer().isNot(AsmToken::Comma)) {
1879 Error(L, "unexpected token in directive");
1885 if (getParser().parseExpression(Expr)) {
1886 Error(L, "expected expression");
1890 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1891 Error(L, "unexpected token in directive");
1895 PPCTargetStreamer &TStreamer =
1896 *static_cast<PPCTargetStreamer *>(
1897 getParser().getStreamer().getTargetStreamer());
1898 TStreamer.emitLocalEntry(Sym, Expr);
1905 /// Force static initialization.
1906 extern "C" void LLVMInitializePowerPCAsmParser() {
1907 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1908 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1909 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1912 #define GET_REGISTER_MATCHER
1913 #define GET_MATCHER_IMPLEMENTATION
1914 #include "PPCGenAsmMatcher.inc"
1916 // Define this matcher function after the auto-generated include so we
1917 // have the match class enum definitions.
1918 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1920 // If the kind is a token for a literal immediate, check if our asm
1921 // operand matches. This is for InstAliases which have a fixed-value
1922 // immediate in the syntax.
1925 case MCK_0: ImmVal = 0; break;
1926 case MCK_1: ImmVal = 1; break;
1927 case MCK_2: ImmVal = 2; break;
1928 case MCK_3: ImmVal = 3; break;
1929 case MCK_4: ImmVal = 4; break;
1930 case MCK_5: ImmVal = 5; break;
1931 case MCK_6: ImmVal = 6; break;
1932 case MCK_7: ImmVal = 7; break;
1933 default: return Match_InvalidOperand;
1936 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1937 if (Op.isImm() && Op.getImm() == ImmVal)
1938 return Match_Success;
1940 return Match_InvalidOperand;
1944 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1945 MCSymbolRefExpr::VariantKind Variant,
1948 case MCSymbolRefExpr::VK_PPC_LO:
1949 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1950 case MCSymbolRefExpr::VK_PPC_HI:
1951 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1952 case MCSymbolRefExpr::VK_PPC_HA:
1953 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1954 case MCSymbolRefExpr::VK_PPC_HIGHER:
1955 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1956 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1957 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1958 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1959 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1960 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1961 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);