1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
35 static const MCPhysReg RRegs[32] = {
36 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
37 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
38 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
39 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
40 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
41 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
42 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
43 PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 static const MCPhysReg RRegsNoR0[32] = {
47 PPC::R1, PPC::R2, PPC::R3,
48 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
49 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
50 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
51 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
52 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
53 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
54 PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 static const MCPhysReg XRegs[32] = {
57 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
58 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
59 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
60 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
61 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
62 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
63 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
64 PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 static const MCPhysReg XRegsNoX0[32] = {
68 PPC::X1, PPC::X2, PPC::X3,
69 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
70 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
71 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
72 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
73 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
74 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
75 PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 static const MCPhysReg FRegs[32] = {
78 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
79 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
80 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
81 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
82 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
83 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
84 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
85 PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 static const MCPhysReg VRegs[32] = {
88 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
89 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
90 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
91 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
92 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
93 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
94 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
95 PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 static const MCPhysReg VSRegs[64] = {
98 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
99 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
100 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
101 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
102 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
103 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
104 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
105 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
108 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
109 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
110 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
111 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
112 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
113 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
114 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 static const MCPhysReg VSFRegs[64] = {
117 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
118 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
119 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
120 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
121 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
122 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
123 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
124 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
127 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
128 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
129 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
130 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
131 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
132 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
133 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 static unsigned QFRegs[32] = {
136 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
137 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
138 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
139 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
140 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
141 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
142 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
143 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
145 static const MCPhysReg CRBITRegs[32] = {
146 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
147 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
148 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
149 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
150 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
151 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
152 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
153 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
155 static const MCPhysReg CRRegs[8] = {
156 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
157 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
160 // Evaluate an expression containing condition register
161 // or condition register field symbols. Returns positive
162 // value on success, or -1 on error.
164 EvaluateCRExpr(const MCExpr *E) {
165 switch (E->getKind()) {
169 case MCExpr::Constant: {
170 int64_t Res = cast<MCConstantExpr>(E)->getValue();
171 return Res < 0 ? -1 : Res;
174 case MCExpr::SymbolRef: {
175 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
176 StringRef Name = SRE->getSymbol().getName();
178 if (Name == "lt") return 0;
179 if (Name == "gt") return 1;
180 if (Name == "eq") return 2;
181 if (Name == "so") return 3;
182 if (Name == "un") return 3;
184 if (Name == "cr0") return 0;
185 if (Name == "cr1") return 1;
186 if (Name == "cr2") return 2;
187 if (Name == "cr3") return 3;
188 if (Name == "cr4") return 4;
189 if (Name == "cr5") return 5;
190 if (Name == "cr6") return 6;
191 if (Name == "cr7") return 7;
199 case MCExpr::Binary: {
200 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
201 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
202 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
205 if (LHSVal < 0 || RHSVal < 0)
208 switch (BE->getOpcode()) {
210 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
211 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
214 return Res < 0 ? -1 : Res;
218 llvm_unreachable("Invalid expression kind!");
225 class PPCAsmParser : public MCTargetAsmParser {
226 MCSubtargetInfo &STI;
227 const MCInstrInfo &MII;
231 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
232 bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
234 bool isPPC64() const { return IsPPC64; }
235 bool isDarwin() const { return IsDarwin; }
237 bool MatchRegisterName(const AsmToken &Tok,
238 unsigned &RegNo, int64_t &IntVal);
240 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
242 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
243 PPCMCExpr::VariantKind &Variant);
244 const MCExpr *FixupVariantKind(const MCExpr *E);
245 bool ParseExpression(const MCExpr *&EVal);
246 bool ParseDarwinExpression(const MCExpr *&EVal);
248 bool ParseOperand(OperandVector &Operands);
250 bool ParseDirectiveWord(unsigned Size, SMLoc L);
251 bool ParseDirectiveTC(unsigned Size, SMLoc L);
252 bool ParseDirectiveMachine(SMLoc L);
253 bool ParseDarwinDirectiveMachine(SMLoc L);
254 bool ParseDirectiveAbiVersion(SMLoc L);
255 bool ParseDirectiveLocalEntry(SMLoc L);
257 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
258 OperandVector &Operands, MCStreamer &Out,
260 bool MatchingInlineAsm) override;
262 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
264 /// @name Auto-generated Match Functions
267 #define GET_ASSEMBLER_HEADER
268 #include "PPCGenAsmMatcher.inc"
274 PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &, const MCInstrInfo &MII,
275 const MCTargetOptions &Options)
276 : MCTargetAsmParser(), STI(STI), MII(MII) {
277 // Check for 64-bit vs. 32-bit pointer mode.
278 Triple TheTriple(STI.getTargetTriple());
279 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
280 TheTriple.getArch() == Triple::ppc64le);
281 IsDarwin = TheTriple.isMacOSX();
282 // Initialize the set of available features.
283 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
286 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
287 SMLoc NameLoc, OperandVector &Operands) override;
289 bool ParseDirective(AsmToken DirectiveID) override;
291 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
292 unsigned Kind) override;
294 const MCExpr *applyModifierToExpr(const MCExpr *E,
295 MCSymbolRefExpr::VariantKind,
296 MCContext &Ctx) override;
299 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
301 struct PPCOperand : public MCParsedAsmOperand {
310 SMLoc StartLoc, EndLoc;
324 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
328 const MCSymbolRefExpr *Sym;
335 struct TLSRegOp TLSReg;
338 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
340 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
342 StartLoc = o.StartLoc;
350 case ContextImmediate:
362 /// getStartLoc - Get the location of the first token of this operand.
363 SMLoc getStartLoc() const override { return StartLoc; }
365 /// getEndLoc - Get the location of the last token of this operand.
366 SMLoc getEndLoc() const override { return EndLoc; }
368 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
369 bool isPPC64() const { return IsPPC64; }
371 int64_t getImm() const {
372 assert(Kind == Immediate && "Invalid access!");
375 int64_t getImmS16Context() const {
376 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
377 if (Kind == Immediate)
379 return static_cast<int16_t>(Imm.Val);
381 int64_t getImmU16Context() const {
382 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
386 const MCExpr *getExpr() const {
387 assert(Kind == Expression && "Invalid access!");
391 int64_t getExprCRVal() const {
392 assert(Kind == Expression && "Invalid access!");
396 const MCExpr *getTLSReg() const {
397 assert(Kind == TLSRegister && "Invalid access!");
401 unsigned getReg() const override {
402 assert(isRegNumber() && "Invalid access!");
403 return (unsigned) Imm.Val;
406 unsigned getVSReg() const {
407 assert(isVSRegNumber() && "Invalid access!");
408 return (unsigned) Imm.Val;
411 unsigned getCCReg() const {
412 assert(isCCRegNumber() && "Invalid access!");
413 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
416 unsigned getCRBit() const {
417 assert(isCRBitNumber() && "Invalid access!");
418 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
421 unsigned getCRBitMask() const {
422 assert(isCRBitMask() && "Invalid access!");
423 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
426 bool isToken() const override { return Kind == Token; }
427 bool isImm() const override { return Kind == Immediate || Kind == Expression; }
428 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
429 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
430 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
431 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
432 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
433 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
434 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
435 bool isU6ImmX2() const { return Kind == Immediate &&
436 isUInt<6>(getImm()) &&
437 (getImm() & 1) == 0; }
438 bool isU7ImmX4() const { return Kind == Immediate &&
439 isUInt<7>(getImm()) &&
440 (getImm() & 3) == 0; }
441 bool isU8ImmX8() const { return Kind == Immediate &&
442 isUInt<8>(getImm()) &&
443 (getImm() & 7) == 0; }
444 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
445 bool isU16Imm() const {
450 case ContextImmediate:
451 return isUInt<16>(getImmU16Context());
456 bool isS16Imm() const {
461 case ContextImmediate:
462 return isInt<16>(getImmS16Context());
467 bool isS16ImmX4() const { return Kind == Expression ||
468 (Kind == Immediate && isInt<16>(getImm()) &&
469 (getImm() & 3) == 0); }
470 bool isS17Imm() const {
475 case ContextImmediate:
476 return isInt<17>(getImmS16Context());
481 bool isTLSReg() const { return Kind == TLSRegister; }
482 bool isDirectBr() const {
483 if (Kind == Expression)
485 if (Kind != Immediate)
487 // Operand must be 64-bit aligned, signed 27-bit immediate.
488 if ((getImm() & 3) != 0)
490 if (isInt<26>(getImm()))
493 // In 32-bit mode, large 32-bit quantities wrap around.
494 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
499 bool isCondBr() const { return Kind == Expression ||
500 (Kind == Immediate && isInt<16>(getImm()) &&
501 (getImm() & 3) == 0); }
502 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
503 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
504 bool isCCRegNumber() const { return (Kind == Expression
505 && isUInt<3>(getExprCRVal())) ||
507 && isUInt<3>(getImm())); }
508 bool isCRBitNumber() const { return (Kind == Expression
509 && isUInt<5>(getExprCRVal())) ||
511 && isUInt<5>(getImm())); }
512 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
513 isPowerOf2_32(getImm()); }
514 bool isMem() const override { return false; }
515 bool isReg() const override { return false; }
517 void addRegOperands(MCInst &Inst, unsigned N) const {
518 llvm_unreachable("addRegOperands");
521 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
522 assert(N == 1 && "Invalid number of operands!");
523 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
526 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
527 assert(N == 1 && "Invalid number of operands!");
528 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
531 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
532 assert(N == 1 && "Invalid number of operands!");
533 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
536 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
537 assert(N == 1 && "Invalid number of operands!");
538 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
541 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
543 addRegG8RCOperands(Inst, N);
545 addRegGPRCOperands(Inst, N);
548 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
550 addRegG8RCNoX0Operands(Inst, N);
552 addRegGPRCNoR0Operands(Inst, N);
555 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
556 assert(N == 1 && "Invalid number of operands!");
557 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
560 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
561 assert(N == 1 && "Invalid number of operands!");
562 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
565 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
566 assert(N == 1 && "Invalid number of operands!");
567 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
570 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
571 assert(N == 1 && "Invalid number of operands!");
572 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
575 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
576 assert(N == 1 && "Invalid number of operands!");
577 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
580 void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
581 assert(N == 1 && "Invalid number of operands!");
582 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
585 void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
586 assert(N == 1 && "Invalid number of operands!");
587 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
590 void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
591 assert(N == 1 && "Invalid number of operands!");
592 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
595 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
596 assert(N == 1 && "Invalid number of operands!");
597 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
600 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
601 assert(N == 1 && "Invalid number of operands!");
602 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
605 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
606 assert(N == 1 && "Invalid number of operands!");
607 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
610 void addImmOperands(MCInst &Inst, unsigned N) const {
611 assert(N == 1 && "Invalid number of operands!");
612 if (Kind == Immediate)
613 Inst.addOperand(MCOperand::CreateImm(getImm()));
615 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
618 void addS16ImmOperands(MCInst &Inst, unsigned N) const {
619 assert(N == 1 && "Invalid number of operands!");
622 Inst.addOperand(MCOperand::CreateImm(getImm()));
624 case ContextImmediate:
625 Inst.addOperand(MCOperand::CreateImm(getImmS16Context()));
628 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
633 void addU16ImmOperands(MCInst &Inst, unsigned N) const {
634 assert(N == 1 && "Invalid number of operands!");
637 Inst.addOperand(MCOperand::CreateImm(getImm()));
639 case ContextImmediate:
640 Inst.addOperand(MCOperand::CreateImm(getImmU16Context()));
643 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
648 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
649 assert(N == 1 && "Invalid number of operands!");
650 if (Kind == Immediate)
651 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
653 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
656 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
657 assert(N == 1 && "Invalid number of operands!");
658 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
661 StringRef getToken() const {
662 assert(Kind == Token && "Invalid access!");
663 return StringRef(Tok.Data, Tok.Length);
666 void print(raw_ostream &OS) const override;
668 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
670 auto Op = make_unique<PPCOperand>(Token);
671 Op->Tok.Data = Str.data();
672 Op->Tok.Length = Str.size();
675 Op->IsPPC64 = IsPPC64;
679 static std::unique_ptr<PPCOperand>
680 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
681 // Allocate extra memory for the string and copy it.
682 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
683 // deleter which will destroy them by simply using "delete", not correctly
684 // calling operator delete on this extra memory after calling the dtor
686 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
687 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
688 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
689 Op->Tok.Length = Str.size();
690 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
693 Op->IsPPC64 = IsPPC64;
697 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
699 auto Op = make_unique<PPCOperand>(Immediate);
703 Op->IsPPC64 = IsPPC64;
707 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
708 SMLoc E, bool IsPPC64) {
709 auto Op = make_unique<PPCOperand>(Expression);
711 Op->Expr.CRVal = EvaluateCRExpr(Val);
714 Op->IsPPC64 = IsPPC64;
718 static std::unique_ptr<PPCOperand>
719 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
720 auto Op = make_unique<PPCOperand>(TLSRegister);
721 Op->TLSReg.Sym = Sym;
724 Op->IsPPC64 = IsPPC64;
728 static std::unique_ptr<PPCOperand>
729 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
730 auto Op = make_unique<PPCOperand>(ContextImmediate);
734 Op->IsPPC64 = IsPPC64;
738 static std::unique_ptr<PPCOperand>
739 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
740 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
741 return CreateImm(CE->getValue(), S, E, IsPPC64);
743 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
744 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
745 return CreateTLSReg(SRE, S, E, IsPPC64);
747 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
749 if (TE->EvaluateAsConstant(Res))
750 return CreateContextImm(Res, S, E, IsPPC64);
753 return CreateExpr(Val, S, E, IsPPC64);
757 } // end anonymous namespace.
759 void PPCOperand::print(raw_ostream &OS) const {
762 OS << "'" << getToken() << "'";
765 case ContextImmediate:
769 getExpr()->print(OS);
772 getTLSReg()->print(OS);
778 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
780 Inst.addOperand(MCOperand::CreateImm(-Op.getImm()));
783 const MCExpr *Expr = Op.getExpr();
784 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
785 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
786 Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr()));
789 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
790 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
791 const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(),
792 BinExpr->getLHS(), Ctx);
793 Inst.addOperand(MCOperand::CreateExpr(NE));
797 Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
800 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
801 const OperandVector &Operands) {
802 int Opcode = Inst.getOpcode();
809 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
810 PPC::DCBT : PPC::DCBTST);
811 TmpInst.addOperand(MCOperand::CreateImm(
812 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
813 TmpInst.addOperand(Inst.getOperand(0));
814 TmpInst.addOperand(Inst.getOperand(1));
821 TmpInst.setOpcode(PPC::DCBT);
822 TmpInst.addOperand(Inst.getOperand(2));
823 TmpInst.addOperand(Inst.getOperand(0));
824 TmpInst.addOperand(Inst.getOperand(1));
829 case PPC::DCBTSTDS: {
831 TmpInst.setOpcode(PPC::DCBTST);
832 TmpInst.addOperand(Inst.getOperand(2));
833 TmpInst.addOperand(Inst.getOperand(0));
834 TmpInst.addOperand(Inst.getOperand(1));
840 TmpInst.setOpcode(PPC::LA);
841 TmpInst.addOperand(Inst.getOperand(0));
842 TmpInst.addOperand(Inst.getOperand(2));
843 TmpInst.addOperand(Inst.getOperand(1));
849 TmpInst.setOpcode(PPC::ADDI);
850 TmpInst.addOperand(Inst.getOperand(0));
851 TmpInst.addOperand(Inst.getOperand(1));
852 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
858 TmpInst.setOpcode(PPC::ADDIS);
859 TmpInst.addOperand(Inst.getOperand(0));
860 TmpInst.addOperand(Inst.getOperand(1));
861 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
867 TmpInst.setOpcode(PPC::ADDIC);
868 TmpInst.addOperand(Inst.getOperand(0));
869 TmpInst.addOperand(Inst.getOperand(1));
870 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
876 TmpInst.setOpcode(PPC::ADDICo);
877 TmpInst.addOperand(Inst.getOperand(0));
878 TmpInst.addOperand(Inst.getOperand(1));
879 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
886 int64_t N = Inst.getOperand(2).getImm();
887 int64_t B = Inst.getOperand(3).getImm();
888 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
889 TmpInst.addOperand(Inst.getOperand(0));
890 TmpInst.addOperand(Inst.getOperand(1));
891 TmpInst.addOperand(MCOperand::CreateImm(B));
892 TmpInst.addOperand(MCOperand::CreateImm(0));
893 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
900 int64_t N = Inst.getOperand(2).getImm();
901 int64_t B = Inst.getOperand(3).getImm();
902 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
903 TmpInst.addOperand(Inst.getOperand(0));
904 TmpInst.addOperand(Inst.getOperand(1));
905 TmpInst.addOperand(MCOperand::CreateImm(B + N));
906 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
907 TmpInst.addOperand(MCOperand::CreateImm(31));
914 int64_t N = Inst.getOperand(2).getImm();
915 int64_t B = Inst.getOperand(3).getImm();
916 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
917 TmpInst.addOperand(Inst.getOperand(0));
918 TmpInst.addOperand(Inst.getOperand(0));
919 TmpInst.addOperand(Inst.getOperand(1));
920 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
921 TmpInst.addOperand(MCOperand::CreateImm(B));
922 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
929 int64_t N = Inst.getOperand(2).getImm();
930 int64_t B = Inst.getOperand(3).getImm();
931 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
932 TmpInst.addOperand(Inst.getOperand(0));
933 TmpInst.addOperand(Inst.getOperand(0));
934 TmpInst.addOperand(Inst.getOperand(1));
935 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
936 TmpInst.addOperand(MCOperand::CreateImm(B));
937 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
944 int64_t N = Inst.getOperand(2).getImm();
945 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
946 TmpInst.addOperand(Inst.getOperand(0));
947 TmpInst.addOperand(Inst.getOperand(1));
948 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
949 TmpInst.addOperand(MCOperand::CreateImm(0));
950 TmpInst.addOperand(MCOperand::CreateImm(31));
957 int64_t N = Inst.getOperand(2).getImm();
958 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
959 TmpInst.addOperand(Inst.getOperand(0));
960 TmpInst.addOperand(Inst.getOperand(1));
961 TmpInst.addOperand(MCOperand::CreateImm(N));
962 TmpInst.addOperand(MCOperand::CreateImm(0));
963 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
970 int64_t N = Inst.getOperand(2).getImm();
971 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
972 TmpInst.addOperand(Inst.getOperand(0));
973 TmpInst.addOperand(Inst.getOperand(1));
974 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
975 TmpInst.addOperand(MCOperand::CreateImm(N));
976 TmpInst.addOperand(MCOperand::CreateImm(31));
983 int64_t N = Inst.getOperand(2).getImm();
984 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
985 TmpInst.addOperand(Inst.getOperand(0));
986 TmpInst.addOperand(Inst.getOperand(1));
987 TmpInst.addOperand(MCOperand::CreateImm(0));
988 TmpInst.addOperand(MCOperand::CreateImm(0));
989 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
994 case PPC::CLRLSLWIo: {
996 int64_t B = Inst.getOperand(2).getImm();
997 int64_t N = Inst.getOperand(3).getImm();
998 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
999 TmpInst.addOperand(Inst.getOperand(0));
1000 TmpInst.addOperand(Inst.getOperand(1));
1001 TmpInst.addOperand(MCOperand::CreateImm(N));
1002 TmpInst.addOperand(MCOperand::CreateImm(B - N));
1003 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
1008 case PPC::EXTLDIo: {
1010 int64_t N = Inst.getOperand(2).getImm();
1011 int64_t B = Inst.getOperand(3).getImm();
1012 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1013 TmpInst.addOperand(Inst.getOperand(0));
1014 TmpInst.addOperand(Inst.getOperand(1));
1015 TmpInst.addOperand(MCOperand::CreateImm(B));
1016 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
1021 case PPC::EXTRDIo: {
1023 int64_t N = Inst.getOperand(2).getImm();
1024 int64_t B = Inst.getOperand(3).getImm();
1025 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1026 TmpInst.addOperand(Inst.getOperand(0));
1027 TmpInst.addOperand(Inst.getOperand(1));
1028 TmpInst.addOperand(MCOperand::CreateImm(B + N));
1029 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1034 case PPC::INSRDIo: {
1036 int64_t N = Inst.getOperand(2).getImm();
1037 int64_t B = Inst.getOperand(3).getImm();
1038 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1039 TmpInst.addOperand(Inst.getOperand(0));
1040 TmpInst.addOperand(Inst.getOperand(0));
1041 TmpInst.addOperand(Inst.getOperand(1));
1042 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
1043 TmpInst.addOperand(MCOperand::CreateImm(B));
1048 case PPC::ROTRDIo: {
1050 int64_t N = Inst.getOperand(2).getImm();
1051 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1052 TmpInst.addOperand(Inst.getOperand(0));
1053 TmpInst.addOperand(Inst.getOperand(1));
1054 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1055 TmpInst.addOperand(MCOperand::CreateImm(0));
1062 int64_t N = Inst.getOperand(2).getImm();
1063 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1064 TmpInst.addOperand(Inst.getOperand(0));
1065 TmpInst.addOperand(Inst.getOperand(1));
1066 TmpInst.addOperand(MCOperand::CreateImm(N));
1067 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1074 int64_t N = Inst.getOperand(2).getImm();
1075 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1076 TmpInst.addOperand(Inst.getOperand(0));
1077 TmpInst.addOperand(Inst.getOperand(1));
1078 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1079 TmpInst.addOperand(MCOperand::CreateImm(N));
1084 case PPC::CLRRDIo: {
1086 int64_t N = Inst.getOperand(2).getImm();
1087 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1088 TmpInst.addOperand(Inst.getOperand(0));
1089 TmpInst.addOperand(Inst.getOperand(1));
1090 TmpInst.addOperand(MCOperand::CreateImm(0));
1091 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1096 case PPC::CLRLSLDIo: {
1098 int64_t B = Inst.getOperand(2).getImm();
1099 int64_t N = Inst.getOperand(3).getImm();
1100 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1101 TmpInst.addOperand(Inst.getOperand(0));
1102 TmpInst.addOperand(Inst.getOperand(1));
1103 TmpInst.addOperand(MCOperand::CreateImm(N));
1104 TmpInst.addOperand(MCOperand::CreateImm(B - N));
1109 case PPC::RLWINMobm: {
1111 int64_t BM = Inst.getOperand(3).getImm();
1112 if (!isRunOfOnes(BM, MB, ME))
1116 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1117 TmpInst.addOperand(Inst.getOperand(0));
1118 TmpInst.addOperand(Inst.getOperand(1));
1119 TmpInst.addOperand(Inst.getOperand(2));
1120 TmpInst.addOperand(MCOperand::CreateImm(MB));
1121 TmpInst.addOperand(MCOperand::CreateImm(ME));
1126 case PPC::RLWIMIobm: {
1128 int64_t BM = Inst.getOperand(3).getImm();
1129 if (!isRunOfOnes(BM, MB, ME))
1133 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1134 TmpInst.addOperand(Inst.getOperand(0));
1135 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1136 TmpInst.addOperand(Inst.getOperand(1));
1137 TmpInst.addOperand(Inst.getOperand(2));
1138 TmpInst.addOperand(MCOperand::CreateImm(MB));
1139 TmpInst.addOperand(MCOperand::CreateImm(ME));
1144 case PPC::RLWNMobm: {
1146 int64_t BM = Inst.getOperand(3).getImm();
1147 if (!isRunOfOnes(BM, MB, ME))
1151 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1152 TmpInst.addOperand(Inst.getOperand(0));
1153 TmpInst.addOperand(Inst.getOperand(1));
1154 TmpInst.addOperand(Inst.getOperand(2));
1155 TmpInst.addOperand(MCOperand::CreateImm(MB));
1156 TmpInst.addOperand(MCOperand::CreateImm(ME));
1163 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1164 OperandVector &Operands,
1165 MCStreamer &Out, uint64_t &ErrorInfo,
1166 bool MatchingInlineAsm) {
1169 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1171 // Post-process instructions (typically extended mnemonics)
1172 ProcessInstruction(Inst, Operands);
1174 Out.EmitInstruction(Inst, STI);
1176 case Match_MissingFeature:
1177 return Error(IDLoc, "instruction use requires an option to be enabled");
1178 case Match_MnemonicFail:
1179 return Error(IDLoc, "unrecognized instruction mnemonic");
1180 case Match_InvalidOperand: {
1181 SMLoc ErrorLoc = IDLoc;
1182 if (ErrorInfo != ~0ULL) {
1183 if (ErrorInfo >= Operands.size())
1184 return Error(IDLoc, "too few operands for instruction");
1186 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1187 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1190 return Error(ErrorLoc, "invalid operand for instruction");
1194 llvm_unreachable("Implement any new match types added!");
1198 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1199 if (Tok.is(AsmToken::Identifier)) {
1200 StringRef Name = Tok.getString();
1202 if (Name.equals_lower("lr")) {
1203 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1206 } else if (Name.equals_lower("ctr")) {
1207 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1210 } else if (Name.equals_lower("vrsave")) {
1211 RegNo = PPC::VRSAVE;
1214 } else if (Name.startswith_lower("r") &&
1215 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1216 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1218 } else if (Name.startswith_lower("f") &&
1219 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1220 RegNo = FRegs[IntVal];
1222 } else if (Name.startswith_lower("v") &&
1223 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1224 RegNo = VRegs[IntVal];
1226 } else if (Name.startswith_lower("cr") &&
1227 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1228 RegNo = CRRegs[IntVal];
1237 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1238 MCAsmParser &Parser = getParser();
1239 const AsmToken &Tok = Parser.getTok();
1240 StartLoc = Tok.getLoc();
1241 EndLoc = Tok.getEndLoc();
1245 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1246 Parser.Lex(); // Eat identifier token.
1250 return Error(StartLoc, "invalid register name");
1253 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1254 /// the expression and check for VK_PPC_LO/HI/HA
1255 /// symbol variants. If all symbols with modifier use the same
1256 /// variant, return the corresponding PPCMCExpr::VariantKind,
1257 /// and a modified expression using the default symbol variant.
1258 /// Otherwise, return NULL.
1259 const MCExpr *PPCAsmParser::
1260 ExtractModifierFromExpr(const MCExpr *E,
1261 PPCMCExpr::VariantKind &Variant) {
1262 MCContext &Context = getParser().getContext();
1263 Variant = PPCMCExpr::VK_PPC_None;
1265 switch (E->getKind()) {
1266 case MCExpr::Target:
1267 case MCExpr::Constant:
1270 case MCExpr::SymbolRef: {
1271 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1273 switch (SRE->getKind()) {
1274 case MCSymbolRefExpr::VK_PPC_LO:
1275 Variant = PPCMCExpr::VK_PPC_LO;
1277 case MCSymbolRefExpr::VK_PPC_HI:
1278 Variant = PPCMCExpr::VK_PPC_HI;
1280 case MCSymbolRefExpr::VK_PPC_HA:
1281 Variant = PPCMCExpr::VK_PPC_HA;
1283 case MCSymbolRefExpr::VK_PPC_HIGHER:
1284 Variant = PPCMCExpr::VK_PPC_HIGHER;
1286 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1287 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1289 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1290 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1292 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1293 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1299 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1302 case MCExpr::Unary: {
1303 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1304 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1307 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1310 case MCExpr::Binary: {
1311 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1312 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1313 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1314 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1319 if (!LHS) LHS = BE->getLHS();
1320 if (!RHS) RHS = BE->getRHS();
1322 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1323 Variant = RHSVariant;
1324 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1325 Variant = LHSVariant;
1326 else if (LHSVariant == RHSVariant)
1327 Variant = LHSVariant;
1331 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1335 llvm_unreachable("Invalid expression kind!");
1338 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1339 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1340 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1341 /// FIXME: This is a hack.
1342 const MCExpr *PPCAsmParser::
1343 FixupVariantKind(const MCExpr *E) {
1344 MCContext &Context = getParser().getContext();
1346 switch (E->getKind()) {
1347 case MCExpr::Target:
1348 case MCExpr::Constant:
1351 case MCExpr::SymbolRef: {
1352 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1353 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1355 switch (SRE->getKind()) {
1356 case MCSymbolRefExpr::VK_TLSGD:
1357 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1359 case MCSymbolRefExpr::VK_TLSLD:
1360 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1365 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1368 case MCExpr::Unary: {
1369 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1370 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1371 if (Sub == UE->getSubExpr())
1373 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1376 case MCExpr::Binary: {
1377 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1378 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1379 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1380 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1382 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1386 llvm_unreachable("Invalid expression kind!");
1389 /// ParseExpression. This differs from the default "parseExpression" in that
1390 /// it handles modifiers.
1392 ParseExpression(const MCExpr *&EVal) {
1395 return ParseDarwinExpression(EVal);
1398 // Handle \code @l/@ha \endcode
1399 if (getParser().parseExpression(EVal))
1402 EVal = FixupVariantKind(EVal);
1404 PPCMCExpr::VariantKind Variant;
1405 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1407 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1412 /// ParseDarwinExpression. (MachO Platforms)
1413 /// This differs from the default "parseExpression" in that it handles detection
1414 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1415 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1416 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1417 /// for this to be done at a higher level.
1419 ParseDarwinExpression(const MCExpr *&EVal) {
1420 MCAsmParser &Parser = getParser();
1421 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1422 switch (getLexer().getKind()) {
1425 case AsmToken::Identifier:
1426 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1427 // something starting with any other char should be part of the
1428 // asm syntax. If handwritten asm includes an identifier like lo16,
1429 // then all bets are off - but no-one would do that, right?
1430 StringRef poss = Parser.getTok().getString();
1431 if (poss.equals_lower("lo16")) {
1432 Variant = PPCMCExpr::VK_PPC_LO;
1433 } else if (poss.equals_lower("hi16")) {
1434 Variant = PPCMCExpr::VK_PPC_HI;
1435 } else if (poss.equals_lower("ha16")) {
1436 Variant = PPCMCExpr::VK_PPC_HA;
1438 if (Variant != PPCMCExpr::VK_PPC_None) {
1439 Parser.Lex(); // Eat the xx16
1440 if (getLexer().isNot(AsmToken::LParen))
1441 return Error(Parser.getTok().getLoc(), "expected '('");
1442 Parser.Lex(); // Eat the '('
1447 if (getParser().parseExpression(EVal))
1450 if (Variant != PPCMCExpr::VK_PPC_None) {
1451 if (getLexer().isNot(AsmToken::RParen))
1452 return Error(Parser.getTok().getLoc(), "expected ')'");
1453 Parser.Lex(); // Eat the ')'
1454 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1460 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1462 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1463 MCAsmParser &Parser = getParser();
1464 SMLoc S = Parser.getTok().getLoc();
1465 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1468 // Attempt to parse the next token as an immediate
1469 switch (getLexer().getKind()) {
1470 // Special handling for register names. These are interpreted
1471 // as immediates corresponding to the register number.
1472 case AsmToken::Percent:
1473 Parser.Lex(); // Eat the '%'.
1476 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1477 Parser.Lex(); // Eat the identifier token.
1478 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1481 return Error(S, "invalid register name");
1483 case AsmToken::Identifier:
1484 // Note that non-register-name identifiers from the compiler will begin
1485 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1486 // identifiers like r31foo - so we fall through in the event that parsing
1487 // a register name fails.
1491 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1492 Parser.Lex(); // Eat the identifier token.
1493 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1497 // Fall-through to process non-register-name identifiers as expression.
1498 // All other expressions
1499 case AsmToken::LParen:
1500 case AsmToken::Plus:
1501 case AsmToken::Minus:
1502 case AsmToken::Integer:
1504 case AsmToken::Dollar:
1505 case AsmToken::Exclaim:
1506 case AsmToken::Tilde:
1507 if (!ParseExpression(EVal))
1511 return Error(S, "unknown operand");
1514 // Push the parsed operand into the list of operands
1515 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1517 // Check whether this is a TLS call expression
1518 bool TLSCall = false;
1519 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1520 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1522 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1523 const MCExpr *TLSSym;
1525 Parser.Lex(); // Eat the '('.
1526 S = Parser.getTok().getLoc();
1527 if (ParseExpression(TLSSym))
1528 return Error(S, "invalid TLS call expression");
1529 if (getLexer().isNot(AsmToken::RParen))
1530 return Error(Parser.getTok().getLoc(), "missing ')'");
1531 E = Parser.getTok().getLoc();
1532 Parser.Lex(); // Eat the ')'.
1534 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1537 // Otherwise, check for D-form memory operands
1538 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1539 Parser.Lex(); // Eat the '('.
1540 S = Parser.getTok().getLoc();
1543 switch (getLexer().getKind()) {
1544 case AsmToken::Percent:
1545 Parser.Lex(); // Eat the '%'.
1547 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1548 return Error(S, "invalid register name");
1549 Parser.Lex(); // Eat the identifier token.
1552 case AsmToken::Integer:
1554 if (getParser().parseAbsoluteExpression(IntVal) ||
1555 IntVal < 0 || IntVal > 31)
1556 return Error(S, "invalid register number");
1558 return Error(S, "unexpected integer value");
1562 case AsmToken::Identifier:
1565 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1566 Parser.Lex(); // Eat the identifier token.
1573 return Error(S, "invalid memory operand");
1576 if (getLexer().isNot(AsmToken::RParen))
1577 return Error(Parser.getTok().getLoc(), "missing ')'");
1578 E = Parser.getTok().getLoc();
1579 Parser.Lex(); // Eat the ')'.
1581 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1587 /// Parse an instruction mnemonic followed by its operands.
1588 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1589 SMLoc NameLoc, OperandVector &Operands) {
1590 // The first operand is the token for the instruction name.
1591 // If the next character is a '+' or '-', we need to add it to the
1592 // instruction name, to match what TableGen is doing.
1593 std::string NewOpcode;
1594 if (getLexer().is(AsmToken::Plus)) {
1600 if (getLexer().is(AsmToken::Minus)) {
1606 // If the instruction ends in a '.', we need to create a separate
1607 // token for it, to match what TableGen is doing.
1608 size_t Dot = Name.find('.');
1609 StringRef Mnemonic = Name.slice(0, Dot);
1610 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1612 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1614 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1615 if (Dot != StringRef::npos) {
1616 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1617 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1618 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1620 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1622 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1625 // If there are no more operands then finish
1626 if (getLexer().is(AsmToken::EndOfStatement))
1629 // Parse the first operand
1630 if (ParseOperand(Operands))
1633 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1634 getLexer().is(AsmToken::Comma)) {
1635 // Consume the comma token
1638 // Parse the next operand
1639 if (ParseOperand(Operands))
1643 // We'll now deal with an unfortunate special case: the syntax for the dcbt
1644 // and dcbtst instructions differs for server vs. embedded cores.
1645 // The syntax for dcbt is:
1646 // dcbt ra, rb, th [server]
1647 // dcbt th, ra, rb [embedded]
1648 // where th can be omitted when it is 0. dcbtst is the same. We take the
1649 // server form to be the default, so swap the operands if we're parsing for
1650 // an embedded core (they'll be swapped again upon printing).
1651 if ((STI.getFeatureBits() & PPC::FeatureBookE) != 0 &&
1652 Operands.size() == 4 &&
1653 (Name == "dcbt" || Name == "dcbtst")) {
1654 std::swap(Operands[1], Operands[3]);
1655 std::swap(Operands[2], Operands[1]);
1661 /// ParseDirective parses the PPC specific directives
1662 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1663 StringRef IDVal = DirectiveID.getIdentifier();
1665 if (IDVal == ".word")
1666 return ParseDirectiveWord(2, DirectiveID.getLoc());
1667 if (IDVal == ".llong")
1668 return ParseDirectiveWord(8, DirectiveID.getLoc());
1670 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1671 if (IDVal == ".machine")
1672 return ParseDirectiveMachine(DirectiveID.getLoc());
1673 if (IDVal == ".abiversion")
1674 return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1675 if (IDVal == ".localentry")
1676 return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1678 if (IDVal == ".machine")
1679 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1684 /// ParseDirectiveWord
1685 /// ::= .word [ expression (, expression)* ]
1686 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1687 MCAsmParser &Parser = getParser();
1688 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1690 const MCExpr *Value;
1691 if (getParser().parseExpression(Value))
1694 getParser().getStreamer().EmitValue(Value, Size);
1696 if (getLexer().is(AsmToken::EndOfStatement))
1699 if (getLexer().isNot(AsmToken::Comma))
1700 return Error(L, "unexpected token in directive");
1709 /// ParseDirectiveTC
1710 /// ::= .tc [ symbol (, expression)* ]
1711 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1712 MCAsmParser &Parser = getParser();
1713 // Skip TC symbol, which is only used with XCOFF.
1714 while (getLexer().isNot(AsmToken::EndOfStatement)
1715 && getLexer().isNot(AsmToken::Comma))
1717 if (getLexer().isNot(AsmToken::Comma)) {
1718 Error(L, "unexpected token in directive");
1723 // Align to word size.
1724 getParser().getStreamer().EmitValueToAlignment(Size);
1726 // Emit expressions.
1727 return ParseDirectiveWord(Size, L);
1730 /// ParseDirectiveMachine (ELF platforms)
1731 /// ::= .machine [ cpu | "push" | "pop" ]
1732 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1733 MCAsmParser &Parser = getParser();
1734 if (getLexer().isNot(AsmToken::Identifier) &&
1735 getLexer().isNot(AsmToken::String)) {
1736 Error(L, "unexpected token in directive");
1740 StringRef CPU = Parser.getTok().getIdentifier();
1743 // FIXME: Right now, the parser always allows any available
1744 // instruction, so the .machine directive is not useful.
1745 // Implement ".machine any" (by doing nothing) for the benefit
1746 // of existing assembler code. Likewise, we can then implement
1747 // ".machine push" and ".machine pop" as no-op.
1748 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1749 Error(L, "unrecognized machine type");
1753 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1754 Error(L, "unexpected token in directive");
1757 PPCTargetStreamer &TStreamer =
1758 *static_cast<PPCTargetStreamer *>(
1759 getParser().getStreamer().getTargetStreamer());
1760 TStreamer.emitMachine(CPU);
1765 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1766 /// ::= .machine cpu-identifier
1767 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1768 MCAsmParser &Parser = getParser();
1769 if (getLexer().isNot(AsmToken::Identifier) &&
1770 getLexer().isNot(AsmToken::String)) {
1771 Error(L, "unexpected token in directive");
1775 StringRef CPU = Parser.getTok().getIdentifier();
1778 // FIXME: this is only the 'default' set of cpu variants.
1779 // However we don't act on this information at present, this is simply
1780 // allowing parsing to proceed with minimal sanity checking.
1781 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1782 Error(L, "unrecognized cpu type");
1786 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1787 Error(L, "wrong cpu type specified for 64bit");
1790 if (!isPPC64() && CPU == "ppc64") {
1791 Error(L, "wrong cpu type specified for 32bit");
1795 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1796 Error(L, "unexpected token in directive");
1803 /// ParseDirectiveAbiVersion
1804 /// ::= .abiversion constant-expression
1805 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1807 if (getParser().parseAbsoluteExpression(AbiVersion)){
1808 Error(L, "expected constant expression");
1811 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1812 Error(L, "unexpected token in directive");
1816 PPCTargetStreamer &TStreamer =
1817 *static_cast<PPCTargetStreamer *>(
1818 getParser().getStreamer().getTargetStreamer());
1819 TStreamer.emitAbiVersion(AbiVersion);
1824 /// ParseDirectiveLocalEntry
1825 /// ::= .localentry symbol, expression
1826 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1828 if (getParser().parseIdentifier(Name)) {
1829 Error(L, "expected identifier in directive");
1832 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1834 if (getLexer().isNot(AsmToken::Comma)) {
1835 Error(L, "unexpected token in directive");
1841 if (getParser().parseExpression(Expr)) {
1842 Error(L, "expected expression");
1846 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1847 Error(L, "unexpected token in directive");
1851 PPCTargetStreamer &TStreamer =
1852 *static_cast<PPCTargetStreamer *>(
1853 getParser().getStreamer().getTargetStreamer());
1854 TStreamer.emitLocalEntry(Sym, Expr);
1861 /// Force static initialization.
1862 extern "C" void LLVMInitializePowerPCAsmParser() {
1863 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1864 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1865 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1868 #define GET_REGISTER_MATCHER
1869 #define GET_MATCHER_IMPLEMENTATION
1870 #include "PPCGenAsmMatcher.inc"
1872 // Define this matcher function after the auto-generated include so we
1873 // have the match class enum definitions.
1874 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1876 // If the kind is a token for a literal immediate, check if our asm
1877 // operand matches. This is for InstAliases which have a fixed-value
1878 // immediate in the syntax.
1881 case MCK_0: ImmVal = 0; break;
1882 case MCK_1: ImmVal = 1; break;
1883 case MCK_2: ImmVal = 2; break;
1884 case MCK_3: ImmVal = 3; break;
1885 case MCK_4: ImmVal = 4; break;
1886 case MCK_5: ImmVal = 5; break;
1887 case MCK_6: ImmVal = 6; break;
1888 case MCK_7: ImmVal = 7; break;
1889 default: return Match_InvalidOperand;
1892 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1893 if (Op.isImm() && Op.getImm() == ImmVal)
1894 return Match_Success;
1896 return Match_InvalidOperand;
1900 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1901 MCSymbolRefExpr::VariantKind Variant,
1904 case MCSymbolRefExpr::VK_PPC_LO:
1905 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1906 case MCSymbolRefExpr::VK_PPC_HI:
1907 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1908 case MCSymbolRefExpr::VK_PPC_HA:
1909 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1910 case MCSymbolRefExpr::VK_PPC_HIGHER:
1911 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1912 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1913 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1914 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1915 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1916 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1917 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);