1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
35 static const MCPhysReg RRegs[32] = {
36 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
37 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
38 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
39 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
40 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
41 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
42 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
43 PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 static const MCPhysReg RRegsNoR0[32] = {
47 PPC::R1, PPC::R2, PPC::R3,
48 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
49 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
50 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
51 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
52 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
53 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
54 PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 static const MCPhysReg XRegs[32] = {
57 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
58 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
59 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
60 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
61 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
62 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
63 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
64 PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 static const MCPhysReg XRegsNoX0[32] = {
68 PPC::X1, PPC::X2, PPC::X3,
69 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
70 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
71 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
72 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
73 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
74 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
75 PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 static const MCPhysReg FRegs[32] = {
78 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
79 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
80 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
81 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
82 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
83 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
84 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
85 PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 static const MCPhysReg VRegs[32] = {
88 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
89 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
90 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
91 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
92 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
93 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
94 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
95 PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 static const MCPhysReg VSRegs[64] = {
98 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
99 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
100 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
101 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
102 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
103 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
104 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
105 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
108 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
109 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
110 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
111 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
112 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
113 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
114 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 static const MCPhysReg VSFRegs[64] = {
117 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
118 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
119 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
120 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
121 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
122 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
123 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
124 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
127 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
128 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
129 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
130 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
131 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
132 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
133 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 static const MCPhysReg VSSRegs[64] = {
136 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
137 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
138 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
139 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
140 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
141 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
142 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
143 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
145 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
146 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
147 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
148 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
149 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
150 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
151 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
152 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
154 static unsigned QFRegs[32] = {
155 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
156 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
157 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
158 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
159 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
160 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
161 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
162 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
164 static const MCPhysReg CRBITRegs[32] = {
165 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
166 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
167 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
168 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
169 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
170 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
171 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
172 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
174 static const MCPhysReg CRRegs[8] = {
175 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
176 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
179 // Evaluate an expression containing condition register
180 // or condition register field symbols. Returns positive
181 // value on success, or -1 on error.
183 EvaluateCRExpr(const MCExpr *E) {
184 switch (E->getKind()) {
188 case MCExpr::Constant: {
189 int64_t Res = cast<MCConstantExpr>(E)->getValue();
190 return Res < 0 ? -1 : Res;
193 case MCExpr::SymbolRef: {
194 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
195 StringRef Name = SRE->getSymbol().getName();
197 if (Name == "lt") return 0;
198 if (Name == "gt") return 1;
199 if (Name == "eq") return 2;
200 if (Name == "so") return 3;
201 if (Name == "un") return 3;
203 if (Name == "cr0") return 0;
204 if (Name == "cr1") return 1;
205 if (Name == "cr2") return 2;
206 if (Name == "cr3") return 3;
207 if (Name == "cr4") return 4;
208 if (Name == "cr5") return 5;
209 if (Name == "cr6") return 6;
210 if (Name == "cr7") return 7;
218 case MCExpr::Binary: {
219 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
220 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
221 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
224 if (LHSVal < 0 || RHSVal < 0)
227 switch (BE->getOpcode()) {
229 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
230 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
233 return Res < 0 ? -1 : Res;
237 llvm_unreachable("Invalid expression kind!");
244 class PPCAsmParser : public MCTargetAsmParser {
245 MCSubtargetInfo &STI;
246 const MCInstrInfo &MII;
250 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
251 bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
253 bool isPPC64() const { return IsPPC64; }
254 bool isDarwin() const { return IsDarwin; }
256 bool MatchRegisterName(const AsmToken &Tok,
257 unsigned &RegNo, int64_t &IntVal);
259 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
261 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
262 PPCMCExpr::VariantKind &Variant);
263 const MCExpr *FixupVariantKind(const MCExpr *E);
264 bool ParseExpression(const MCExpr *&EVal);
265 bool ParseDarwinExpression(const MCExpr *&EVal);
267 bool ParseOperand(OperandVector &Operands);
269 bool ParseDirectiveWord(unsigned Size, SMLoc L);
270 bool ParseDirectiveTC(unsigned Size, SMLoc L);
271 bool ParseDirectiveMachine(SMLoc L);
272 bool ParseDarwinDirectiveMachine(SMLoc L);
273 bool ParseDirectiveAbiVersion(SMLoc L);
274 bool ParseDirectiveLocalEntry(SMLoc L);
276 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
277 OperandVector &Operands, MCStreamer &Out,
279 bool MatchingInlineAsm) override;
281 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
283 /// @name Auto-generated Match Functions
286 #define GET_ASSEMBLER_HEADER
287 #include "PPCGenAsmMatcher.inc"
293 PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &, const MCInstrInfo &MII,
294 const MCTargetOptions &Options)
295 : MCTargetAsmParser(), STI(STI), MII(MII) {
296 // Check for 64-bit vs. 32-bit pointer mode.
297 Triple TheTriple(STI.getTargetTriple());
298 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
299 TheTriple.getArch() == Triple::ppc64le);
300 IsDarwin = TheTriple.isMacOSX();
301 // Initialize the set of available features.
302 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
305 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
306 SMLoc NameLoc, OperandVector &Operands) override;
308 bool ParseDirective(AsmToken DirectiveID) override;
310 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
311 unsigned Kind) override;
313 const MCExpr *applyModifierToExpr(const MCExpr *E,
314 MCSymbolRefExpr::VariantKind,
315 MCContext &Ctx) override;
318 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
320 struct PPCOperand : public MCParsedAsmOperand {
329 SMLoc StartLoc, EndLoc;
343 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
347 const MCSymbolRefExpr *Sym;
354 struct TLSRegOp TLSReg;
357 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
359 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
361 StartLoc = o.StartLoc;
369 case ContextImmediate:
381 /// getStartLoc - Get the location of the first token of this operand.
382 SMLoc getStartLoc() const override { return StartLoc; }
384 /// getEndLoc - Get the location of the last token of this operand.
385 SMLoc getEndLoc() const override { return EndLoc; }
387 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
388 bool isPPC64() const { return IsPPC64; }
390 int64_t getImm() const {
391 assert(Kind == Immediate && "Invalid access!");
394 int64_t getImmS16Context() const {
395 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
396 if (Kind == Immediate)
398 return static_cast<int16_t>(Imm.Val);
400 int64_t getImmU16Context() const {
401 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
405 const MCExpr *getExpr() const {
406 assert(Kind == Expression && "Invalid access!");
410 int64_t getExprCRVal() const {
411 assert(Kind == Expression && "Invalid access!");
415 const MCExpr *getTLSReg() const {
416 assert(Kind == TLSRegister && "Invalid access!");
420 unsigned getReg() const override {
421 assert(isRegNumber() && "Invalid access!");
422 return (unsigned) Imm.Val;
425 unsigned getVSReg() const {
426 assert(isVSRegNumber() && "Invalid access!");
427 return (unsigned) Imm.Val;
430 unsigned getCCReg() const {
431 assert(isCCRegNumber() && "Invalid access!");
432 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
435 unsigned getCRBit() const {
436 assert(isCRBitNumber() && "Invalid access!");
437 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
440 unsigned getCRBitMask() const {
441 assert(isCRBitMask() && "Invalid access!");
442 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
445 bool isToken() const override { return Kind == Token; }
446 bool isImm() const override { return Kind == Immediate || Kind == Expression; }
447 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
448 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
449 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
450 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
451 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
452 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
453 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
454 bool isU6ImmX2() const { return Kind == Immediate &&
455 isUInt<6>(getImm()) &&
456 (getImm() & 1) == 0; }
457 bool isU7ImmX4() const { return Kind == Immediate &&
458 isUInt<7>(getImm()) &&
459 (getImm() & 3) == 0; }
460 bool isU8ImmX8() const { return Kind == Immediate &&
461 isUInt<8>(getImm()) &&
462 (getImm() & 7) == 0; }
463 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
464 bool isU16Imm() const {
469 case ContextImmediate:
470 return isUInt<16>(getImmU16Context());
475 bool isS16Imm() const {
480 case ContextImmediate:
481 return isInt<16>(getImmS16Context());
486 bool isS16ImmX4() const { return Kind == Expression ||
487 (Kind == Immediate && isInt<16>(getImm()) &&
488 (getImm() & 3) == 0); }
489 bool isS17Imm() const {
494 case ContextImmediate:
495 return isInt<17>(getImmS16Context());
500 bool isTLSReg() const { return Kind == TLSRegister; }
501 bool isDirectBr() const {
502 if (Kind == Expression)
504 if (Kind != Immediate)
506 // Operand must be 64-bit aligned, signed 27-bit immediate.
507 if ((getImm() & 3) != 0)
509 if (isInt<26>(getImm()))
512 // In 32-bit mode, large 32-bit quantities wrap around.
513 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
518 bool isCondBr() const { return Kind == Expression ||
519 (Kind == Immediate && isInt<16>(getImm()) &&
520 (getImm() & 3) == 0); }
521 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
522 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
523 bool isCCRegNumber() const { return (Kind == Expression
524 && isUInt<3>(getExprCRVal())) ||
526 && isUInt<3>(getImm())); }
527 bool isCRBitNumber() const { return (Kind == Expression
528 && isUInt<5>(getExprCRVal())) ||
530 && isUInt<5>(getImm())); }
531 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
532 isPowerOf2_32(getImm()); }
533 bool isMem() const override { return false; }
534 bool isReg() const override { return false; }
536 void addRegOperands(MCInst &Inst, unsigned N) const {
537 llvm_unreachable("addRegOperands");
540 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
541 assert(N == 1 && "Invalid number of operands!");
542 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
545 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
546 assert(N == 1 && "Invalid number of operands!");
547 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
550 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
551 assert(N == 1 && "Invalid number of operands!");
552 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
555 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
556 assert(N == 1 && "Invalid number of operands!");
557 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
560 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
562 addRegG8RCOperands(Inst, N);
564 addRegGPRCOperands(Inst, N);
567 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
569 addRegG8RCNoX0Operands(Inst, N);
571 addRegGPRCNoR0Operands(Inst, N);
574 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
575 assert(N == 1 && "Invalid number of operands!");
576 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
579 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
580 assert(N == 1 && "Invalid number of operands!");
581 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
584 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
585 assert(N == 1 && "Invalid number of operands!");
586 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
589 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
590 assert(N == 1 && "Invalid number of operands!");
591 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
594 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
595 assert(N == 1 && "Invalid number of operands!");
596 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
599 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
600 assert(N == 1 && "Invalid number of operands!");
601 Inst.addOperand(MCOperand::CreateReg(VSSRegs[getVSReg()]));
604 void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
605 assert(N == 1 && "Invalid number of operands!");
606 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
609 void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
610 assert(N == 1 && "Invalid number of operands!");
611 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
614 void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
615 assert(N == 1 && "Invalid number of operands!");
616 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
619 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
620 assert(N == 1 && "Invalid number of operands!");
621 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
624 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
625 assert(N == 1 && "Invalid number of operands!");
626 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
629 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
630 assert(N == 1 && "Invalid number of operands!");
631 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
634 void addImmOperands(MCInst &Inst, unsigned N) const {
635 assert(N == 1 && "Invalid number of operands!");
636 if (Kind == Immediate)
637 Inst.addOperand(MCOperand::CreateImm(getImm()));
639 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
642 void addS16ImmOperands(MCInst &Inst, unsigned N) const {
643 assert(N == 1 && "Invalid number of operands!");
646 Inst.addOperand(MCOperand::CreateImm(getImm()));
648 case ContextImmediate:
649 Inst.addOperand(MCOperand::CreateImm(getImmS16Context()));
652 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
657 void addU16ImmOperands(MCInst &Inst, unsigned N) const {
658 assert(N == 1 && "Invalid number of operands!");
661 Inst.addOperand(MCOperand::CreateImm(getImm()));
663 case ContextImmediate:
664 Inst.addOperand(MCOperand::CreateImm(getImmU16Context()));
667 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
672 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
673 assert(N == 1 && "Invalid number of operands!");
674 if (Kind == Immediate)
675 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
677 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
680 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
681 assert(N == 1 && "Invalid number of operands!");
682 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
685 StringRef getToken() const {
686 assert(Kind == Token && "Invalid access!");
687 return StringRef(Tok.Data, Tok.Length);
690 void print(raw_ostream &OS) const override;
692 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
694 auto Op = make_unique<PPCOperand>(Token);
695 Op->Tok.Data = Str.data();
696 Op->Tok.Length = Str.size();
699 Op->IsPPC64 = IsPPC64;
703 static std::unique_ptr<PPCOperand>
704 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
705 // Allocate extra memory for the string and copy it.
706 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
707 // deleter which will destroy them by simply using "delete", not correctly
708 // calling operator delete on this extra memory after calling the dtor
710 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
711 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
712 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
713 Op->Tok.Length = Str.size();
714 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
717 Op->IsPPC64 = IsPPC64;
721 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
723 auto Op = make_unique<PPCOperand>(Immediate);
727 Op->IsPPC64 = IsPPC64;
731 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
732 SMLoc E, bool IsPPC64) {
733 auto Op = make_unique<PPCOperand>(Expression);
735 Op->Expr.CRVal = EvaluateCRExpr(Val);
738 Op->IsPPC64 = IsPPC64;
742 static std::unique_ptr<PPCOperand>
743 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
744 auto Op = make_unique<PPCOperand>(TLSRegister);
745 Op->TLSReg.Sym = Sym;
748 Op->IsPPC64 = IsPPC64;
752 static std::unique_ptr<PPCOperand>
753 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
754 auto Op = make_unique<PPCOperand>(ContextImmediate);
758 Op->IsPPC64 = IsPPC64;
762 static std::unique_ptr<PPCOperand>
763 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
764 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
765 return CreateImm(CE->getValue(), S, E, IsPPC64);
767 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
768 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
769 return CreateTLSReg(SRE, S, E, IsPPC64);
771 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
773 if (TE->EvaluateAsConstant(Res))
774 return CreateContextImm(Res, S, E, IsPPC64);
777 return CreateExpr(Val, S, E, IsPPC64);
781 } // end anonymous namespace.
783 void PPCOperand::print(raw_ostream &OS) const {
786 OS << "'" << getToken() << "'";
789 case ContextImmediate:
793 getExpr()->print(OS);
796 getTLSReg()->print(OS);
802 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
804 Inst.addOperand(MCOperand::CreateImm(-Op.getImm()));
807 const MCExpr *Expr = Op.getExpr();
808 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
809 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
810 Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr()));
813 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
814 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
815 const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(),
816 BinExpr->getLHS(), Ctx);
817 Inst.addOperand(MCOperand::CreateExpr(NE));
821 Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
824 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
825 const OperandVector &Operands) {
826 int Opcode = Inst.getOpcode();
833 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
834 PPC::DCBT : PPC::DCBTST);
835 TmpInst.addOperand(MCOperand::CreateImm(
836 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
837 TmpInst.addOperand(Inst.getOperand(0));
838 TmpInst.addOperand(Inst.getOperand(1));
845 TmpInst.setOpcode(PPC::DCBT);
846 TmpInst.addOperand(Inst.getOperand(2));
847 TmpInst.addOperand(Inst.getOperand(0));
848 TmpInst.addOperand(Inst.getOperand(1));
853 case PPC::DCBTSTDS: {
855 TmpInst.setOpcode(PPC::DCBTST);
856 TmpInst.addOperand(Inst.getOperand(2));
857 TmpInst.addOperand(Inst.getOperand(0));
858 TmpInst.addOperand(Inst.getOperand(1));
864 TmpInst.setOpcode(PPC::LA);
865 TmpInst.addOperand(Inst.getOperand(0));
866 TmpInst.addOperand(Inst.getOperand(2));
867 TmpInst.addOperand(Inst.getOperand(1));
873 TmpInst.setOpcode(PPC::ADDI);
874 TmpInst.addOperand(Inst.getOperand(0));
875 TmpInst.addOperand(Inst.getOperand(1));
876 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
882 TmpInst.setOpcode(PPC::ADDIS);
883 TmpInst.addOperand(Inst.getOperand(0));
884 TmpInst.addOperand(Inst.getOperand(1));
885 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
891 TmpInst.setOpcode(PPC::ADDIC);
892 TmpInst.addOperand(Inst.getOperand(0));
893 TmpInst.addOperand(Inst.getOperand(1));
894 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
900 TmpInst.setOpcode(PPC::ADDICo);
901 TmpInst.addOperand(Inst.getOperand(0));
902 TmpInst.addOperand(Inst.getOperand(1));
903 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
910 int64_t N = Inst.getOperand(2).getImm();
911 int64_t B = Inst.getOperand(3).getImm();
912 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
913 TmpInst.addOperand(Inst.getOperand(0));
914 TmpInst.addOperand(Inst.getOperand(1));
915 TmpInst.addOperand(MCOperand::CreateImm(B));
916 TmpInst.addOperand(MCOperand::CreateImm(0));
917 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
924 int64_t N = Inst.getOperand(2).getImm();
925 int64_t B = Inst.getOperand(3).getImm();
926 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
927 TmpInst.addOperand(Inst.getOperand(0));
928 TmpInst.addOperand(Inst.getOperand(1));
929 TmpInst.addOperand(MCOperand::CreateImm(B + N));
930 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
931 TmpInst.addOperand(MCOperand::CreateImm(31));
938 int64_t N = Inst.getOperand(2).getImm();
939 int64_t B = Inst.getOperand(3).getImm();
940 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
941 TmpInst.addOperand(Inst.getOperand(0));
942 TmpInst.addOperand(Inst.getOperand(0));
943 TmpInst.addOperand(Inst.getOperand(1));
944 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
945 TmpInst.addOperand(MCOperand::CreateImm(B));
946 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
953 int64_t N = Inst.getOperand(2).getImm();
954 int64_t B = Inst.getOperand(3).getImm();
955 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
956 TmpInst.addOperand(Inst.getOperand(0));
957 TmpInst.addOperand(Inst.getOperand(0));
958 TmpInst.addOperand(Inst.getOperand(1));
959 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
960 TmpInst.addOperand(MCOperand::CreateImm(B));
961 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
968 int64_t N = Inst.getOperand(2).getImm();
969 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
970 TmpInst.addOperand(Inst.getOperand(0));
971 TmpInst.addOperand(Inst.getOperand(1));
972 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
973 TmpInst.addOperand(MCOperand::CreateImm(0));
974 TmpInst.addOperand(MCOperand::CreateImm(31));
981 int64_t N = Inst.getOperand(2).getImm();
982 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
983 TmpInst.addOperand(Inst.getOperand(0));
984 TmpInst.addOperand(Inst.getOperand(1));
985 TmpInst.addOperand(MCOperand::CreateImm(N));
986 TmpInst.addOperand(MCOperand::CreateImm(0));
987 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
994 int64_t N = Inst.getOperand(2).getImm();
995 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
996 TmpInst.addOperand(Inst.getOperand(0));
997 TmpInst.addOperand(Inst.getOperand(1));
998 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
999 TmpInst.addOperand(MCOperand::CreateImm(N));
1000 TmpInst.addOperand(MCOperand::CreateImm(31));
1005 case PPC::CLRRWIo: {
1007 int64_t N = Inst.getOperand(2).getImm();
1008 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1009 TmpInst.addOperand(Inst.getOperand(0));
1010 TmpInst.addOperand(Inst.getOperand(1));
1011 TmpInst.addOperand(MCOperand::CreateImm(0));
1012 TmpInst.addOperand(MCOperand::CreateImm(0));
1013 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
1018 case PPC::CLRLSLWIo: {
1020 int64_t B = Inst.getOperand(2).getImm();
1021 int64_t N = Inst.getOperand(3).getImm();
1022 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1023 TmpInst.addOperand(Inst.getOperand(0));
1024 TmpInst.addOperand(Inst.getOperand(1));
1025 TmpInst.addOperand(MCOperand::CreateImm(N));
1026 TmpInst.addOperand(MCOperand::CreateImm(B - N));
1027 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
1032 case PPC::EXTLDIo: {
1034 int64_t N = Inst.getOperand(2).getImm();
1035 int64_t B = Inst.getOperand(3).getImm();
1036 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1037 TmpInst.addOperand(Inst.getOperand(0));
1038 TmpInst.addOperand(Inst.getOperand(1));
1039 TmpInst.addOperand(MCOperand::CreateImm(B));
1040 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
1045 case PPC::EXTRDIo: {
1047 int64_t N = Inst.getOperand(2).getImm();
1048 int64_t B = Inst.getOperand(3).getImm();
1049 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1050 TmpInst.addOperand(Inst.getOperand(0));
1051 TmpInst.addOperand(Inst.getOperand(1));
1052 TmpInst.addOperand(MCOperand::CreateImm(B + N));
1053 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1058 case PPC::INSRDIo: {
1060 int64_t N = Inst.getOperand(2).getImm();
1061 int64_t B = Inst.getOperand(3).getImm();
1062 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1063 TmpInst.addOperand(Inst.getOperand(0));
1064 TmpInst.addOperand(Inst.getOperand(0));
1065 TmpInst.addOperand(Inst.getOperand(1));
1066 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
1067 TmpInst.addOperand(MCOperand::CreateImm(B));
1072 case PPC::ROTRDIo: {
1074 int64_t N = Inst.getOperand(2).getImm();
1075 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1076 TmpInst.addOperand(Inst.getOperand(0));
1077 TmpInst.addOperand(Inst.getOperand(1));
1078 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1079 TmpInst.addOperand(MCOperand::CreateImm(0));
1086 int64_t N = Inst.getOperand(2).getImm();
1087 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1088 TmpInst.addOperand(Inst.getOperand(0));
1089 TmpInst.addOperand(Inst.getOperand(1));
1090 TmpInst.addOperand(MCOperand::CreateImm(N));
1091 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1098 int64_t N = Inst.getOperand(2).getImm();
1099 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1100 TmpInst.addOperand(Inst.getOperand(0));
1101 TmpInst.addOperand(Inst.getOperand(1));
1102 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1103 TmpInst.addOperand(MCOperand::CreateImm(N));
1108 case PPC::CLRRDIo: {
1110 int64_t N = Inst.getOperand(2).getImm();
1111 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1112 TmpInst.addOperand(Inst.getOperand(0));
1113 TmpInst.addOperand(Inst.getOperand(1));
1114 TmpInst.addOperand(MCOperand::CreateImm(0));
1115 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1120 case PPC::CLRLSLDIo: {
1122 int64_t B = Inst.getOperand(2).getImm();
1123 int64_t N = Inst.getOperand(3).getImm();
1124 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1125 TmpInst.addOperand(Inst.getOperand(0));
1126 TmpInst.addOperand(Inst.getOperand(1));
1127 TmpInst.addOperand(MCOperand::CreateImm(N));
1128 TmpInst.addOperand(MCOperand::CreateImm(B - N));
1133 case PPC::RLWINMobm: {
1135 int64_t BM = Inst.getOperand(3).getImm();
1136 if (!isRunOfOnes(BM, MB, ME))
1140 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1141 TmpInst.addOperand(Inst.getOperand(0));
1142 TmpInst.addOperand(Inst.getOperand(1));
1143 TmpInst.addOperand(Inst.getOperand(2));
1144 TmpInst.addOperand(MCOperand::CreateImm(MB));
1145 TmpInst.addOperand(MCOperand::CreateImm(ME));
1150 case PPC::RLWIMIobm: {
1152 int64_t BM = Inst.getOperand(3).getImm();
1153 if (!isRunOfOnes(BM, MB, ME))
1157 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1158 TmpInst.addOperand(Inst.getOperand(0));
1159 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1160 TmpInst.addOperand(Inst.getOperand(1));
1161 TmpInst.addOperand(Inst.getOperand(2));
1162 TmpInst.addOperand(MCOperand::CreateImm(MB));
1163 TmpInst.addOperand(MCOperand::CreateImm(ME));
1168 case PPC::RLWNMobm: {
1170 int64_t BM = Inst.getOperand(3).getImm();
1171 if (!isRunOfOnes(BM, MB, ME))
1175 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1176 TmpInst.addOperand(Inst.getOperand(0));
1177 TmpInst.addOperand(Inst.getOperand(1));
1178 TmpInst.addOperand(Inst.getOperand(2));
1179 TmpInst.addOperand(MCOperand::CreateImm(MB));
1180 TmpInst.addOperand(MCOperand::CreateImm(ME));
1187 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1188 OperandVector &Operands,
1189 MCStreamer &Out, uint64_t &ErrorInfo,
1190 bool MatchingInlineAsm) {
1193 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1195 // Post-process instructions (typically extended mnemonics)
1196 ProcessInstruction(Inst, Operands);
1198 Out.EmitInstruction(Inst, STI);
1200 case Match_MissingFeature:
1201 return Error(IDLoc, "instruction use requires an option to be enabled");
1202 case Match_MnemonicFail:
1203 return Error(IDLoc, "unrecognized instruction mnemonic");
1204 case Match_InvalidOperand: {
1205 SMLoc ErrorLoc = IDLoc;
1206 if (ErrorInfo != ~0ULL) {
1207 if (ErrorInfo >= Operands.size())
1208 return Error(IDLoc, "too few operands for instruction");
1210 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1211 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1214 return Error(ErrorLoc, "invalid operand for instruction");
1218 llvm_unreachable("Implement any new match types added!");
1222 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1223 if (Tok.is(AsmToken::Identifier)) {
1224 StringRef Name = Tok.getString();
1226 if (Name.equals_lower("lr")) {
1227 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1230 } else if (Name.equals_lower("ctr")) {
1231 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1234 } else if (Name.equals_lower("vrsave")) {
1235 RegNo = PPC::VRSAVE;
1238 } else if (Name.startswith_lower("r") &&
1239 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1240 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1242 } else if (Name.startswith_lower("f") &&
1243 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1244 RegNo = FRegs[IntVal];
1246 } else if (Name.startswith_lower("vs") &&
1247 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1248 RegNo = VSRegs[IntVal];
1250 } else if (Name.startswith_lower("v") &&
1251 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1252 RegNo = VRegs[IntVal];
1254 } else if (Name.startswith_lower("q") &&
1255 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1256 RegNo = QFRegs[IntVal];
1258 } else if (Name.startswith_lower("cr") &&
1259 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1260 RegNo = CRRegs[IntVal];
1269 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1270 MCAsmParser &Parser = getParser();
1271 const AsmToken &Tok = Parser.getTok();
1272 StartLoc = Tok.getLoc();
1273 EndLoc = Tok.getEndLoc();
1277 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1278 Parser.Lex(); // Eat identifier token.
1282 return Error(StartLoc, "invalid register name");
1285 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1286 /// the expression and check for VK_PPC_LO/HI/HA
1287 /// symbol variants. If all symbols with modifier use the same
1288 /// variant, return the corresponding PPCMCExpr::VariantKind,
1289 /// and a modified expression using the default symbol variant.
1290 /// Otherwise, return NULL.
1291 const MCExpr *PPCAsmParser::
1292 ExtractModifierFromExpr(const MCExpr *E,
1293 PPCMCExpr::VariantKind &Variant) {
1294 MCContext &Context = getParser().getContext();
1295 Variant = PPCMCExpr::VK_PPC_None;
1297 switch (E->getKind()) {
1298 case MCExpr::Target:
1299 case MCExpr::Constant:
1302 case MCExpr::SymbolRef: {
1303 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1305 switch (SRE->getKind()) {
1306 case MCSymbolRefExpr::VK_PPC_LO:
1307 Variant = PPCMCExpr::VK_PPC_LO;
1309 case MCSymbolRefExpr::VK_PPC_HI:
1310 Variant = PPCMCExpr::VK_PPC_HI;
1312 case MCSymbolRefExpr::VK_PPC_HA:
1313 Variant = PPCMCExpr::VK_PPC_HA;
1315 case MCSymbolRefExpr::VK_PPC_HIGHER:
1316 Variant = PPCMCExpr::VK_PPC_HIGHER;
1318 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1319 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1321 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1322 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1324 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1325 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1331 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1334 case MCExpr::Unary: {
1335 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1336 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1339 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1342 case MCExpr::Binary: {
1343 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1344 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1345 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1346 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1351 if (!LHS) LHS = BE->getLHS();
1352 if (!RHS) RHS = BE->getRHS();
1354 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1355 Variant = RHSVariant;
1356 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1357 Variant = LHSVariant;
1358 else if (LHSVariant == RHSVariant)
1359 Variant = LHSVariant;
1363 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1367 llvm_unreachable("Invalid expression kind!");
1370 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1371 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1372 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1373 /// FIXME: This is a hack.
1374 const MCExpr *PPCAsmParser::
1375 FixupVariantKind(const MCExpr *E) {
1376 MCContext &Context = getParser().getContext();
1378 switch (E->getKind()) {
1379 case MCExpr::Target:
1380 case MCExpr::Constant:
1383 case MCExpr::SymbolRef: {
1384 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1385 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1387 switch (SRE->getKind()) {
1388 case MCSymbolRefExpr::VK_TLSGD:
1389 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1391 case MCSymbolRefExpr::VK_TLSLD:
1392 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1397 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1400 case MCExpr::Unary: {
1401 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1402 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1403 if (Sub == UE->getSubExpr())
1405 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1408 case MCExpr::Binary: {
1409 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1410 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1411 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1412 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1414 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1418 llvm_unreachable("Invalid expression kind!");
1421 /// ParseExpression. This differs from the default "parseExpression" in that
1422 /// it handles modifiers.
1424 ParseExpression(const MCExpr *&EVal) {
1427 return ParseDarwinExpression(EVal);
1430 // Handle \code @l/@ha \endcode
1431 if (getParser().parseExpression(EVal))
1434 EVal = FixupVariantKind(EVal);
1436 PPCMCExpr::VariantKind Variant;
1437 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1439 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1444 /// ParseDarwinExpression. (MachO Platforms)
1445 /// This differs from the default "parseExpression" in that it handles detection
1446 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1447 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1448 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1449 /// for this to be done at a higher level.
1451 ParseDarwinExpression(const MCExpr *&EVal) {
1452 MCAsmParser &Parser = getParser();
1453 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1454 switch (getLexer().getKind()) {
1457 case AsmToken::Identifier:
1458 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1459 // something starting with any other char should be part of the
1460 // asm syntax. If handwritten asm includes an identifier like lo16,
1461 // then all bets are off - but no-one would do that, right?
1462 StringRef poss = Parser.getTok().getString();
1463 if (poss.equals_lower("lo16")) {
1464 Variant = PPCMCExpr::VK_PPC_LO;
1465 } else if (poss.equals_lower("hi16")) {
1466 Variant = PPCMCExpr::VK_PPC_HI;
1467 } else if (poss.equals_lower("ha16")) {
1468 Variant = PPCMCExpr::VK_PPC_HA;
1470 if (Variant != PPCMCExpr::VK_PPC_None) {
1471 Parser.Lex(); // Eat the xx16
1472 if (getLexer().isNot(AsmToken::LParen))
1473 return Error(Parser.getTok().getLoc(), "expected '('");
1474 Parser.Lex(); // Eat the '('
1479 if (getParser().parseExpression(EVal))
1482 if (Variant != PPCMCExpr::VK_PPC_None) {
1483 if (getLexer().isNot(AsmToken::RParen))
1484 return Error(Parser.getTok().getLoc(), "expected ')'");
1485 Parser.Lex(); // Eat the ')'
1486 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1492 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1494 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1495 MCAsmParser &Parser = getParser();
1496 SMLoc S = Parser.getTok().getLoc();
1497 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1500 // Attempt to parse the next token as an immediate
1501 switch (getLexer().getKind()) {
1502 // Special handling for register names. These are interpreted
1503 // as immediates corresponding to the register number.
1504 case AsmToken::Percent:
1505 Parser.Lex(); // Eat the '%'.
1508 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1509 Parser.Lex(); // Eat the identifier token.
1510 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1513 return Error(S, "invalid register name");
1515 case AsmToken::Identifier:
1516 // Note that non-register-name identifiers from the compiler will begin
1517 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1518 // identifiers like r31foo - so we fall through in the event that parsing
1519 // a register name fails.
1523 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1524 Parser.Lex(); // Eat the identifier token.
1525 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1529 // Fall-through to process non-register-name identifiers as expression.
1530 // All other expressions
1531 case AsmToken::LParen:
1532 case AsmToken::Plus:
1533 case AsmToken::Minus:
1534 case AsmToken::Integer:
1536 case AsmToken::Dollar:
1537 case AsmToken::Exclaim:
1538 case AsmToken::Tilde:
1539 if (!ParseExpression(EVal))
1543 return Error(S, "unknown operand");
1546 // Push the parsed operand into the list of operands
1547 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1549 // Check whether this is a TLS call expression
1550 bool TLSCall = false;
1551 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1552 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1554 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1555 const MCExpr *TLSSym;
1557 Parser.Lex(); // Eat the '('.
1558 S = Parser.getTok().getLoc();
1559 if (ParseExpression(TLSSym))
1560 return Error(S, "invalid TLS call expression");
1561 if (getLexer().isNot(AsmToken::RParen))
1562 return Error(Parser.getTok().getLoc(), "missing ')'");
1563 E = Parser.getTok().getLoc();
1564 Parser.Lex(); // Eat the ')'.
1566 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1569 // Otherwise, check for D-form memory operands
1570 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1571 Parser.Lex(); // Eat the '('.
1572 S = Parser.getTok().getLoc();
1575 switch (getLexer().getKind()) {
1576 case AsmToken::Percent:
1577 Parser.Lex(); // Eat the '%'.
1579 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1580 return Error(S, "invalid register name");
1581 Parser.Lex(); // Eat the identifier token.
1584 case AsmToken::Integer:
1586 if (getParser().parseAbsoluteExpression(IntVal) ||
1587 IntVal < 0 || IntVal > 31)
1588 return Error(S, "invalid register number");
1590 return Error(S, "unexpected integer value");
1594 case AsmToken::Identifier:
1597 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1598 Parser.Lex(); // Eat the identifier token.
1605 return Error(S, "invalid memory operand");
1608 if (getLexer().isNot(AsmToken::RParen))
1609 return Error(Parser.getTok().getLoc(), "missing ')'");
1610 E = Parser.getTok().getLoc();
1611 Parser.Lex(); // Eat the ')'.
1613 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1619 /// Parse an instruction mnemonic followed by its operands.
1620 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1621 SMLoc NameLoc, OperandVector &Operands) {
1622 // The first operand is the token for the instruction name.
1623 // If the next character is a '+' or '-', we need to add it to the
1624 // instruction name, to match what TableGen is doing.
1625 std::string NewOpcode;
1626 if (getLexer().is(AsmToken::Plus)) {
1632 if (getLexer().is(AsmToken::Minus)) {
1638 // If the instruction ends in a '.', we need to create a separate
1639 // token for it, to match what TableGen is doing.
1640 size_t Dot = Name.find('.');
1641 StringRef Mnemonic = Name.slice(0, Dot);
1642 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1644 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1646 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1647 if (Dot != StringRef::npos) {
1648 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1649 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1650 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1652 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1654 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1657 // If there are no more operands then finish
1658 if (getLexer().is(AsmToken::EndOfStatement))
1661 // Parse the first operand
1662 if (ParseOperand(Operands))
1665 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1666 getLexer().is(AsmToken::Comma)) {
1667 // Consume the comma token
1670 // Parse the next operand
1671 if (ParseOperand(Operands))
1675 // We'll now deal with an unfortunate special case: the syntax for the dcbt
1676 // and dcbtst instructions differs for server vs. embedded cores.
1677 // The syntax for dcbt is:
1678 // dcbt ra, rb, th [server]
1679 // dcbt th, ra, rb [embedded]
1680 // where th can be omitted when it is 0. dcbtst is the same. We take the
1681 // server form to be the default, so swap the operands if we're parsing for
1682 // an embedded core (they'll be swapped again upon printing).
1683 if ((STI.getFeatureBits() & PPC::FeatureBookE) != 0 &&
1684 Operands.size() == 4 &&
1685 (Name == "dcbt" || Name == "dcbtst")) {
1686 std::swap(Operands[1], Operands[3]);
1687 std::swap(Operands[2], Operands[1]);
1693 /// ParseDirective parses the PPC specific directives
1694 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1695 StringRef IDVal = DirectiveID.getIdentifier();
1697 if (IDVal == ".word")
1698 return ParseDirectiveWord(2, DirectiveID.getLoc());
1699 if (IDVal == ".llong")
1700 return ParseDirectiveWord(8, DirectiveID.getLoc());
1702 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1703 if (IDVal == ".machine")
1704 return ParseDirectiveMachine(DirectiveID.getLoc());
1705 if (IDVal == ".abiversion")
1706 return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1707 if (IDVal == ".localentry")
1708 return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1710 if (IDVal == ".machine")
1711 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1716 /// ParseDirectiveWord
1717 /// ::= .word [ expression (, expression)* ]
1718 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1719 MCAsmParser &Parser = getParser();
1720 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1722 const MCExpr *Value;
1723 if (getParser().parseExpression(Value))
1726 getParser().getStreamer().EmitValue(Value, Size);
1728 if (getLexer().is(AsmToken::EndOfStatement))
1731 if (getLexer().isNot(AsmToken::Comma))
1732 return Error(L, "unexpected token in directive");
1741 /// ParseDirectiveTC
1742 /// ::= .tc [ symbol (, expression)* ]
1743 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1744 MCAsmParser &Parser = getParser();
1745 // Skip TC symbol, which is only used with XCOFF.
1746 while (getLexer().isNot(AsmToken::EndOfStatement)
1747 && getLexer().isNot(AsmToken::Comma))
1749 if (getLexer().isNot(AsmToken::Comma)) {
1750 Error(L, "unexpected token in directive");
1755 // Align to word size.
1756 getParser().getStreamer().EmitValueToAlignment(Size);
1758 // Emit expressions.
1759 return ParseDirectiveWord(Size, L);
1762 /// ParseDirectiveMachine (ELF platforms)
1763 /// ::= .machine [ cpu | "push" | "pop" ]
1764 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1765 MCAsmParser &Parser = getParser();
1766 if (getLexer().isNot(AsmToken::Identifier) &&
1767 getLexer().isNot(AsmToken::String)) {
1768 Error(L, "unexpected token in directive");
1772 StringRef CPU = Parser.getTok().getIdentifier();
1775 // FIXME: Right now, the parser always allows any available
1776 // instruction, so the .machine directive is not useful.
1777 // Implement ".machine any" (by doing nothing) for the benefit
1778 // of existing assembler code. Likewise, we can then implement
1779 // ".machine push" and ".machine pop" as no-op.
1780 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1781 Error(L, "unrecognized machine type");
1785 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1786 Error(L, "unexpected token in directive");
1789 PPCTargetStreamer &TStreamer =
1790 *static_cast<PPCTargetStreamer *>(
1791 getParser().getStreamer().getTargetStreamer());
1792 TStreamer.emitMachine(CPU);
1797 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1798 /// ::= .machine cpu-identifier
1799 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1800 MCAsmParser &Parser = getParser();
1801 if (getLexer().isNot(AsmToken::Identifier) &&
1802 getLexer().isNot(AsmToken::String)) {
1803 Error(L, "unexpected token in directive");
1807 StringRef CPU = Parser.getTok().getIdentifier();
1810 // FIXME: this is only the 'default' set of cpu variants.
1811 // However we don't act on this information at present, this is simply
1812 // allowing parsing to proceed with minimal sanity checking.
1813 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1814 Error(L, "unrecognized cpu type");
1818 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1819 Error(L, "wrong cpu type specified for 64bit");
1822 if (!isPPC64() && CPU == "ppc64") {
1823 Error(L, "wrong cpu type specified for 32bit");
1827 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1828 Error(L, "unexpected token in directive");
1835 /// ParseDirectiveAbiVersion
1836 /// ::= .abiversion constant-expression
1837 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1839 if (getParser().parseAbsoluteExpression(AbiVersion)){
1840 Error(L, "expected constant expression");
1843 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1844 Error(L, "unexpected token in directive");
1848 PPCTargetStreamer &TStreamer =
1849 *static_cast<PPCTargetStreamer *>(
1850 getParser().getStreamer().getTargetStreamer());
1851 TStreamer.emitAbiVersion(AbiVersion);
1856 /// ParseDirectiveLocalEntry
1857 /// ::= .localentry symbol, expression
1858 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1860 if (getParser().parseIdentifier(Name)) {
1861 Error(L, "expected identifier in directive");
1864 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1866 if (getLexer().isNot(AsmToken::Comma)) {
1867 Error(L, "unexpected token in directive");
1873 if (getParser().parseExpression(Expr)) {
1874 Error(L, "expected expression");
1878 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1879 Error(L, "unexpected token in directive");
1883 PPCTargetStreamer &TStreamer =
1884 *static_cast<PPCTargetStreamer *>(
1885 getParser().getStreamer().getTargetStreamer());
1886 TStreamer.emitLocalEntry(Sym, Expr);
1893 /// Force static initialization.
1894 extern "C" void LLVMInitializePowerPCAsmParser() {
1895 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1896 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1897 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1900 #define GET_REGISTER_MATCHER
1901 #define GET_MATCHER_IMPLEMENTATION
1902 #include "PPCGenAsmMatcher.inc"
1904 // Define this matcher function after the auto-generated include so we
1905 // have the match class enum definitions.
1906 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1908 // If the kind is a token for a literal immediate, check if our asm
1909 // operand matches. This is for InstAliases which have a fixed-value
1910 // immediate in the syntax.
1913 case MCK_0: ImmVal = 0; break;
1914 case MCK_1: ImmVal = 1; break;
1915 case MCK_2: ImmVal = 2; break;
1916 case MCK_3: ImmVal = 3; break;
1917 case MCK_4: ImmVal = 4; break;
1918 case MCK_5: ImmVal = 5; break;
1919 case MCK_6: ImmVal = 6; break;
1920 case MCK_7: ImmVal = 7; break;
1921 default: return Match_InvalidOperand;
1924 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1925 if (Op.isImm() && Op.getImm() == ImmVal)
1926 return Match_Success;
1928 return Match_InvalidOperand;
1932 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1933 MCSymbolRefExpr::VariantKind Variant,
1936 case MCSymbolRefExpr::VK_PPC_LO:
1937 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1938 case MCSymbolRefExpr::VK_PPC_HI:
1939 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1940 case MCSymbolRefExpr::VK_PPC_HA:
1941 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1942 case MCSymbolRefExpr::VK_PPC_HIGHER:
1943 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1944 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1945 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1946 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1947 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1948 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1949 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);