2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pic16-lower"
15 #include "PIC16ISelLowering.h"
16 #include "PIC16TargetObjectFile.h"
17 #include "PIC16TargetMachine.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/GlobalValue.h"
20 #include "llvm/Function.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
31 static const char *getIntrinsicName(unsigned opcode) {
34 default: assert (0 && "do not know intrinsic name");
35 // Arithmetic Right shift for integer types.
36 case PIC16ISD::SRA_I8: Basename = "sra.i8"; break;
37 case RTLIB::SRA_I16: Basename = "sra.i16"; break;
38 case RTLIB::SRA_I32: Basename = "sra.i32"; break;
40 // Left shift for integer types.
41 case PIC16ISD::SLL_I8: Basename = "sll.i8"; break;
42 case RTLIB::SHL_I16: Basename = "sll.i16"; break;
43 case RTLIB::SHL_I32: Basename = "sll.i32"; break;
45 // Logical Right Shift for integer types.
46 case PIC16ISD::SRL_I8: Basename = "srl.i8"; break;
47 case RTLIB::SRL_I16: Basename = "srl.i16"; break;
48 case RTLIB::SRL_I32: Basename = "srl.i32"; break;
50 // Multiply for integer types.
51 case PIC16ISD::MUL_I8: Basename = "mul.i8"; break;
52 case RTLIB::MUL_I16: Basename = "mul.i16"; break;
53 case RTLIB::MUL_I32: Basename = "mul.i32"; break;
55 // Signed division for integers.
56 case RTLIB::SDIV_I16: Basename = "sdiv.i16"; break;
57 case RTLIB::SDIV_I32: Basename = "sdiv.i32"; break;
59 // Unsigned division for integers.
60 case RTLIB::UDIV_I16: Basename = "udiv.i16"; break;
61 case RTLIB::UDIV_I32: Basename = "udiv.i32"; break;
63 // Signed Modulas for integers.
64 case RTLIB::SREM_I16: Basename = "srem.i16"; break;
65 case RTLIB::SREM_I32: Basename = "srem.i32"; break;
67 // Unsigned Modulas for integers.
68 case RTLIB::UREM_I16: Basename = "urem.i16"; break;
69 case RTLIB::UREM_I32: Basename = "urem.i32"; break;
71 //////////////////////
72 // LIBCALLS FOR FLOATS
73 //////////////////////
75 // Float to signed integrals
76 case RTLIB::FPTOSINT_F32_I8: Basename = "f32_to_si32"; break;
77 case RTLIB::FPTOSINT_F32_I16: Basename = "f32_to_si32"; break;
78 case RTLIB::FPTOSINT_F32_I32: Basename = "f32_to_si32"; break;
80 // Signed integrals to float. char and int are first sign extended to i32
81 // before being converted to float, so an I8_F32 or I16_F32 isn't required.
82 case RTLIB::SINTTOFP_I32_F32: Basename = "si32_to_f32"; break;
84 // Float to Unsigned conversions.
85 // Signed conversion can be used for unsigned conversion as well.
86 // In signed and unsigned versions only the interpretation of the
87 // MSB is different. Bit representation remains the same.
88 case RTLIB::FPTOUINT_F32_I8: Basename = "f32_to_si32"; break;
89 case RTLIB::FPTOUINT_F32_I16: Basename = "f32_to_si32"; break;
90 case RTLIB::FPTOUINT_F32_I32: Basename = "f32_to_si32"; break;
92 // Unsigned to Float conversions. char and int are first zero extended
93 // before being converted to float.
94 case RTLIB::UINTTOFP_I32_F32: Basename = "ui32_to_f32"; break;
96 // Floating point add, sub, mul, div.
97 case RTLIB::ADD_F32: Basename = "add.f32"; break;
98 case RTLIB::SUB_F32: Basename = "sub.f32"; break;
99 case RTLIB::MUL_F32: Basename = "mul.f32"; break;
100 case RTLIB::DIV_F32: Basename = "div.f32"; break;
102 // Floating point comparison
103 case RTLIB::O_F32: Basename = "unordered.f32"; break;
104 case RTLIB::UO_F32: Basename = "unordered.f32"; break;
105 case RTLIB::OLE_F32: Basename = "le.f32"; break;
106 case RTLIB::OGE_F32: Basename = "ge.f32"; break;
107 case RTLIB::OLT_F32: Basename = "lt.f32"; break;
108 case RTLIB::OGT_F32: Basename = "gt.f32"; break;
109 case RTLIB::OEQ_F32: Basename = "eq.f32"; break;
110 case RTLIB::UNE_F32: Basename = "neq.f32"; break;
113 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
114 std::string tagname = PAN::getTagName(PAN::LIBCALL);
115 std::string Fullname = prefix + tagname + Basename;
117 // The name has to live through program life.
118 char *tmp = new char[Fullname.size() + 1];
119 strcpy (tmp, Fullname.c_str());
124 // PIC16TargetLowering Constructor.
125 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
126 : TargetLowering(TM, new PIC16TargetObjectFile(TM)), TmpSize(0) {
128 Subtarget = &TM.getSubtarget<PIC16Subtarget>();
130 addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
132 setShiftAmountType(MVT::i8);
134 // SRA library call names
135 setPIC16LibcallName(PIC16ISD::SRA_I8, getIntrinsicName(PIC16ISD::SRA_I8));
136 setLibcallName(RTLIB::SRA_I16, getIntrinsicName(RTLIB::SRA_I16));
137 setLibcallName(RTLIB::SRA_I32, getIntrinsicName(RTLIB::SRA_I32));
139 // SHL library call names
140 setPIC16LibcallName(PIC16ISD::SLL_I8, getIntrinsicName(PIC16ISD::SLL_I8));
141 setLibcallName(RTLIB::SHL_I16, getIntrinsicName(RTLIB::SHL_I16));
142 setLibcallName(RTLIB::SHL_I32, getIntrinsicName(RTLIB::SHL_I32));
144 // SRL library call names
145 setPIC16LibcallName(PIC16ISD::SRL_I8, getIntrinsicName(PIC16ISD::SRL_I8));
146 setLibcallName(RTLIB::SRL_I16, getIntrinsicName(RTLIB::SRL_I16));
147 setLibcallName(RTLIB::SRL_I32, getIntrinsicName(RTLIB::SRL_I32));
149 // MUL Library call names
150 setPIC16LibcallName(PIC16ISD::MUL_I8, getIntrinsicName(PIC16ISD::MUL_I8));
151 setLibcallName(RTLIB::MUL_I16, getIntrinsicName(RTLIB::MUL_I16));
152 setLibcallName(RTLIB::MUL_I32, getIntrinsicName(RTLIB::MUL_I32));
154 // Signed division lib call names
155 setLibcallName(RTLIB::SDIV_I16, getIntrinsicName(RTLIB::SDIV_I16));
156 setLibcallName(RTLIB::SDIV_I32, getIntrinsicName(RTLIB::SDIV_I32));
158 // Unsigned division lib call names
159 setLibcallName(RTLIB::UDIV_I16, getIntrinsicName(RTLIB::UDIV_I16));
160 setLibcallName(RTLIB::UDIV_I32, getIntrinsicName(RTLIB::UDIV_I32));
162 // Signed remainder lib call names
163 setLibcallName(RTLIB::SREM_I16, getIntrinsicName(RTLIB::SREM_I16));
164 setLibcallName(RTLIB::SREM_I32, getIntrinsicName(RTLIB::SREM_I32));
166 // Unsigned remainder lib call names
167 setLibcallName(RTLIB::UREM_I16, getIntrinsicName(RTLIB::UREM_I16));
168 setLibcallName(RTLIB::UREM_I32, getIntrinsicName(RTLIB::UREM_I32));
170 // Floating point to signed int conversions.
171 setLibcallName(RTLIB::FPTOSINT_F32_I8,
172 getIntrinsicName(RTLIB::FPTOSINT_F32_I8));
173 setLibcallName(RTLIB::FPTOSINT_F32_I16,
174 getIntrinsicName(RTLIB::FPTOSINT_F32_I16));
175 setLibcallName(RTLIB::FPTOSINT_F32_I32,
176 getIntrinsicName(RTLIB::FPTOSINT_F32_I32));
178 // Signed int to floats.
179 setLibcallName(RTLIB::SINTTOFP_I32_F32,
180 getIntrinsicName(RTLIB::SINTTOFP_I32_F32));
182 // Floating points to unsigned ints.
183 setLibcallName(RTLIB::FPTOUINT_F32_I8,
184 getIntrinsicName(RTLIB::FPTOUINT_F32_I8));
185 setLibcallName(RTLIB::FPTOUINT_F32_I16,
186 getIntrinsicName(RTLIB::FPTOUINT_F32_I16));
187 setLibcallName(RTLIB::FPTOUINT_F32_I32,
188 getIntrinsicName(RTLIB::FPTOUINT_F32_I32));
190 // Unsigned int to floats.
191 setLibcallName(RTLIB::UINTTOFP_I32_F32,
192 getIntrinsicName(RTLIB::UINTTOFP_I32_F32));
194 // Floating point add, sub, mul ,div.
195 setLibcallName(RTLIB::ADD_F32, getIntrinsicName(RTLIB::ADD_F32));
196 setLibcallName(RTLIB::SUB_F32, getIntrinsicName(RTLIB::SUB_F32));
197 setLibcallName(RTLIB::MUL_F32, getIntrinsicName(RTLIB::MUL_F32));
198 setLibcallName(RTLIB::DIV_F32, getIntrinsicName(RTLIB::DIV_F32));
200 // Floationg point comparison
201 setLibcallName(RTLIB::UO_F32, getIntrinsicName(RTLIB::UO_F32));
202 setLibcallName(RTLIB::OLE_F32, getIntrinsicName(RTLIB::OLE_F32));
203 setLibcallName(RTLIB::OGE_F32, getIntrinsicName(RTLIB::OGE_F32));
204 setLibcallName(RTLIB::OLT_F32, getIntrinsicName(RTLIB::OLT_F32));
205 setLibcallName(RTLIB::OGT_F32, getIntrinsicName(RTLIB::OGT_F32));
206 setLibcallName(RTLIB::OEQ_F32, getIntrinsicName(RTLIB::OEQ_F32));
207 setLibcallName(RTLIB::UNE_F32, getIntrinsicName(RTLIB::UNE_F32));
209 // Return value comparisons of floating point calls.
210 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
219 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
220 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
222 setOperationAction(ISD::LOAD, MVT::i8, Legal);
223 setOperationAction(ISD::LOAD, MVT::i16, Custom);
224 setOperationAction(ISD::LOAD, MVT::i32, Custom);
226 setOperationAction(ISD::STORE, MVT::i8, Legal);
227 setOperationAction(ISD::STORE, MVT::i16, Custom);
228 setOperationAction(ISD::STORE, MVT::i32, Custom);
230 setOperationAction(ISD::ADDE, MVT::i8, Custom);
231 setOperationAction(ISD::ADDC, MVT::i8, Custom);
232 setOperationAction(ISD::SUBE, MVT::i8, Custom);
233 setOperationAction(ISD::SUBC, MVT::i8, Custom);
234 setOperationAction(ISD::SUB, MVT::i8, Custom);
235 setOperationAction(ISD::ADD, MVT::i8, Custom);
236 setOperationAction(ISD::ADD, MVT::i16, Custom);
238 setOperationAction(ISD::OR, MVT::i8, Custom);
239 setOperationAction(ISD::AND, MVT::i8, Custom);
240 setOperationAction(ISD::XOR, MVT::i8, Custom);
242 setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
243 setOperationAction(ISD::CALL, MVT::i16, Custom);
244 setOperationAction(ISD::RET, MVT::Other, Custom);
246 setOperationAction(ISD::MUL, MVT::i8, Custom);
248 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
249 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
250 setOperationAction(ISD::MULHU, MVT::i8, Expand);
251 setOperationAction(ISD::MULHS, MVT::i8, Expand);
253 setOperationAction(ISD::SRA, MVT::i8, Custom);
254 setOperationAction(ISD::SHL, MVT::i8, Custom);
255 setOperationAction(ISD::SRL, MVT::i8, Custom);
257 setOperationAction(ISD::ROTL, MVT::i8, Expand);
258 setOperationAction(ISD::ROTR, MVT::i8, Expand);
260 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
262 // PIC16 does not support shift parts
263 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
264 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
265 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
268 // PIC16 does not have a SETCC, expand it to SELECT_CC.
269 setOperationAction(ISD::SETCC, MVT::i8, Expand);
270 setOperationAction(ISD::SELECT, MVT::i8, Expand);
271 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
272 setOperationAction(ISD::BRIND, MVT::Other, Expand);
274 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
275 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
277 //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
278 setTruncStoreAction(MVT::i16, MVT::i8, Custom);
280 // Now deduce the information based on the above mentioned
282 computeRegisterProperties();
285 // getOutFlag - Extract the flag result if the Op has it.
286 static SDValue getOutFlag(SDValue &Op) {
287 // Flag is the last value of the node.
288 SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
290 assert (Flag.getValueType() == MVT::Flag
291 && "Node does not have an out Flag");
295 // Get the TmpOffset for FrameIndex
296 unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size) {
297 std::map<unsigned, unsigned>::iterator
298 MapIt = FiTmpOffsetMap.find(FI);
299 if (MapIt != FiTmpOffsetMap.end())
300 return MapIt->second;
302 // This FI (FrameIndex) is not yet mapped, so map it
303 FiTmpOffsetMap[FI] = TmpSize;
305 return FiTmpOffsetMap[FI];
308 // To extract chain value from the SDValue Nodes
309 // This function will help to maintain the chain extracting
310 // code at one place. In case of any change in future it will
311 // help maintain the code.
312 static SDValue getChain(SDValue &Op) {
313 SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
315 // If the last value returned in Flag then the chain is
316 // second last value returned.
317 if (Chain.getValueType() == MVT::Flag)
318 Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
320 // All nodes may not produce a chain. Therefore following assert
321 // verifies that the node is returning a chain only.
322 assert (Chain.getValueType() == MVT::Other
323 && "Node does not have a chain");
328 /// PopulateResults - Helper function to LowerOperation.
329 /// If a node wants to return multiple results after lowering,
330 /// it stuffs them into an array of SDValue called Results.
332 static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) {
333 if (N.getOpcode() == ISD::MERGE_VALUES) {
334 int NumResults = N.getNumOperands();
335 for( int i = 0; i < NumResults; i++)
336 Results.push_back(N.getOperand(i));
339 Results.push_back(N);
342 MVT PIC16TargetLowering::getSetCCResultType(MVT ValType) const {
346 /// The type legalizer framework of generating legalizer can generate libcalls
347 /// only when the operand/result types are illegal.
348 /// PIC16 needs to generate libcalls even for the legal types (i8) for some ops.
349 /// For example an arithmetic right shift. These functions are used to lower
350 /// such operations that generate libcall for legal types.
353 PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
355 PIC16LibcallNames[Call] = Name;
359 PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) {
360 return PIC16LibcallNames[Call];
364 PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
365 MVT RetVT, const SDValue *Ops,
366 unsigned NumOps, bool isSigned,
367 SelectionDAG &DAG, DebugLoc dl) {
369 TargetLowering::ArgListTy Args;
370 Args.reserve(NumOps);
372 TargetLowering::ArgListEntry Entry;
373 for (unsigned i = 0; i != NumOps; ++i) {
375 Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
376 Entry.isSExt = isSigned;
377 Entry.isZExt = !isSigned;
378 Args.push_back(Entry);
380 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i8);
382 const Type *RetTy = RetVT.getTypeForMVT();
383 std::pair<SDValue,SDValue> CallInfo =
384 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
385 false, 0, CallingConv::C, false, Callee, Args, DAG, dl);
387 return CallInfo.first;
390 const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
392 default: return NULL;
393 case PIC16ISD::Lo: return "PIC16ISD::Lo";
394 case PIC16ISD::Hi: return "PIC16ISD::Hi";
395 case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
396 case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
397 case PIC16ISD::MTPCLATH: return "PIC16ISD::MTPCLATH";
398 case PIC16ISD::PIC16Connect: return "PIC16ISD::PIC16Connect";
399 case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
400 case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
401 case PIC16ISD::PIC16LdArg: return "PIC16ISD::PIC16LdArg";
402 case PIC16ISD::PIC16LdWF: return "PIC16ISD::PIC16LdWF";
403 case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
404 case PIC16ISD::PIC16StWF: return "PIC16ISD::PIC16StWF";
405 case PIC16ISD::BCF: return "PIC16ISD::BCF";
406 case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
407 case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
408 case PIC16ISD::RLF: return "PIC16ISD::RLF";
409 case PIC16ISD::RRF: return "PIC16ISD::RRF";
410 case PIC16ISD::CALL: return "PIC16ISD::CALL";
411 case PIC16ISD::CALLW: return "PIC16ISD::CALLW";
412 case PIC16ISD::SUBCC: return "PIC16ISD::SUBCC";
413 case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
414 case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
415 case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
419 void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
420 SmallVectorImpl<SDValue>&Results,
423 switch (N->getOpcode()) {
424 case ISD::GlobalAddress:
425 Results.push_back(ExpandGlobalAddress(N, DAG));
427 case ISD::ExternalSymbol:
428 Results.push_back(ExpandExternalSymbol(N, DAG));
431 Results.push_back(ExpandStore(N, DAG));
434 PopulateResults(ExpandLoad(N, DAG), Results);
437 // Results.push_back(ExpandAdd(N, DAG));
439 case ISD::FrameIndex:
440 Results.push_back(ExpandFrameIndex(N, DAG));
443 assert (0 && "not implemented");
448 SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
450 // Currently handling FrameIndex of size MVT::i16 only
451 // One example of this scenario is when return value is written on
454 if (N->getValueType(0) != MVT::i16)
457 // Expand the FrameIndex into ExternalSymbol and a Constant node
458 // The constant will represent the frame index number
459 // Get the current function frame
460 MachineFunction &MF = DAG.getMachineFunction();
461 const Function *Func = MF.getFunction();
462 const std::string Name = Func->getName();
464 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
465 // FIXME there isn't really debug info here
466 DebugLoc dl = FR->getDebugLoc();
468 // Expand FrameIndex like GlobalAddress and ExternalSymbol
469 // Also use Offset field for lo and hi parts. The default
474 SDValue FI = SDValue(N,0);
475 LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
476 SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
477 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
478 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
479 return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
483 SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
484 StoreSDNode *St = cast<StoreSDNode>(N);
485 SDValue Chain = St->getChain();
486 SDValue Src = St->getValue();
487 SDValue Ptr = St->getBasePtr();
488 MVT ValueType = Src.getValueType();
489 unsigned StoreOffset = 0;
490 DebugLoc dl = N->getDebugLoc();
492 SDValue PtrLo, PtrHi;
493 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
495 if (ValueType == MVT::i8) {
496 return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
498 DAG.getConstant (0 + StoreOffset, MVT::i8));
500 else if (ValueType == MVT::i16) {
501 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
502 SDValue SrcLo, SrcHi;
503 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
504 SDValue ChainLo = Chain, ChainHi = Chain;
505 if (Chain.getOpcode() == ISD::TokenFactor) {
506 ChainLo = Chain.getOperand(0);
507 ChainHi = Chain.getOperand(1);
509 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
512 DAG.getConstant (0 + StoreOffset, MVT::i8));
514 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
516 DAG.getConstant (1 + StoreOffset, MVT::i8));
518 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
521 else if (ValueType == MVT::i32) {
522 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
523 SDValue SrcLo, SrcHi;
524 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
526 // Get the expanded parts of each of SrcLo and SrcHi.
527 SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
528 GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
529 GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
531 SDValue ChainLo = Chain, ChainHi = Chain;
532 if (Chain.getOpcode() == ISD::TokenFactor) {
533 ChainLo = Chain.getOperand(0);
534 ChainHi = Chain.getOperand(1);
536 SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
538 if (ChainLo.getOpcode() == ISD::TokenFactor) {
539 ChainLo1 = ChainLo.getOperand(0);
540 ChainLo2 = ChainLo.getOperand(1);
542 if (ChainHi.getOpcode() == ISD::TokenFactor) {
543 ChainHi1 = ChainHi.getOperand(0);
544 ChainHi2 = ChainHi.getOperand(1);
546 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
548 SrcLo1, PtrLo, PtrHi,
549 DAG.getConstant (0 + StoreOffset, MVT::i8));
551 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
552 SrcLo2, PtrLo, PtrHi,
553 DAG.getConstant (1 + StoreOffset, MVT::i8));
555 SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
556 SrcHi1, PtrLo, PtrHi,
557 DAG.getConstant (2 + StoreOffset, MVT::i8));
559 SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
560 SrcHi2, PtrLo, PtrHi,
561 DAG.getConstant (3 + StoreOffset, MVT::i8));
563 SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
564 getChain(Store1), getChain(Store2));
565 SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
566 getChain(Store3), getChain(Store4));
567 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
571 assert (0 && "value type not supported");
576 SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
578 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
579 // FIXME there isn't really debug info here
580 DebugLoc dl = ES->getDebugLoc();
582 SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
583 SDValue Offset = DAG.getConstant(0, MVT::i8);
584 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset);
585 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset);
587 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
590 // ExpandGlobalAddress -
591 SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
592 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
593 // FIXME there isn't really debug info here
594 DebugLoc dl = G->getDebugLoc();
596 SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
599 SDValue Offset = DAG.getConstant(0, MVT::i8);
600 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset);
601 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset);
603 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
606 bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
607 assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
609 if (Op.getOpcode() == ISD::BUILD_PAIR) {
610 if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
616 // Return true if DirectAddress is in ROM_SPACE
617 bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
619 // RomAddress is a GlobalAddress in ROM_SPACE_
620 // If the Op is not a GlobalAddress return NULL without checking
622 if (!isDirectAddress(Op))
625 // Its a GlobalAddress.
626 // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
627 SDValue TGA = Op.getOperand(0).getOperand(0);
628 GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
630 if (GSDN->getAddressSpace() == PIC16ISD::ROM_SPACE)
633 // Any other address space return it false
638 // GetExpandedParts - This function is on the similiar lines as
639 // the GetExpandedInteger in type legalizer is. This returns expanded
640 // parts of Op in Lo and Hi.
642 void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
643 SDValue &Lo, SDValue &Hi) {
644 SDNode *N = Op.getNode();
645 DebugLoc dl = N->getDebugLoc();
646 MVT NewVT = getTypeToTransformTo(N->getValueType(0));
648 // Extract the lo component.
649 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
650 DAG.getConstant(0, MVT::i8));
652 // extract the hi component
653 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
654 DAG.getConstant(1, MVT::i8));
657 // Legalize FrameIndex into ExternalSymbol and offset.
659 PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
660 SDValue &ES, int &Offset) {
662 MachineFunction &MF = DAG.getMachineFunction();
663 const Function *Func = MF.getFunction();
664 MachineFrameInfo *MFI = MF.getFrameInfo();
665 const std::string Name = Func->getName();
667 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(Op);
669 // FrameIndices are not stack offsets. But they represent the request
670 // for space on stack. That space requested may be more than one byte.
671 // Therefore, to calculate the stack offset that a FrameIndex aligns
672 // with, we need to traverse all the FrameIndices available earlier in
673 // the list and add their requested size.
674 unsigned FIndex = FR->getIndex();
676 if (FIndex < ReservedFrameCount) {
677 tmpName = createESName(PAN::getFrameLabel(Name));
678 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
680 for (unsigned i=0; i<FIndex ; ++i) {
681 Offset += MFI->getObjectSize(i);
684 // FrameIndex has been made for some temporary storage
685 tmpName = createESName(PAN::getTempdataLabel(Name));
686 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
687 Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex));
693 // This function legalizes the PIC16 Addresses. If the Pointer is
694 // -- Direct address variable residing
695 // --> then a Banksel for that variable will be created.
697 // --> then it will be treated as an indirect address.
698 // -- Indirect address
699 // --> then the address will be loaded into FSR
700 // -- ADD with constant operand
701 // --> then constant operand of ADD will be returned as Offset
702 // and non-constant operand of ADD will be treated as pointer.
703 // Returns the high and lo part of the address, and the offset(in case of ADD).
705 void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
706 SDValue &Lo, SDValue &Hi,
707 unsigned &Offset, DebugLoc dl) {
709 // Offset, by default, should be 0
712 // If the pointer is ADD with constant,
713 // return the constant value as the offset
714 if (Ptr.getOpcode() == ISD::ADD) {
715 SDValue OperLeft = Ptr.getOperand(0);
716 SDValue OperRight = Ptr.getOperand(1);
717 if ((OperLeft.getOpcode() == ISD::Constant) &&
718 (dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue() < 32 )) {
719 Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
721 } else if ((OperRight.getOpcode() == ISD::Constant) &&
722 (dyn_cast<ConstantSDNode>(OperRight)->getZExtValue() < 32 )){
723 Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
728 // If the pointer is Type i8 and an external symbol
729 // then treat it as direct address.
730 // One example for such case is storing and loading
731 // from function frame during a call
732 if (Ptr.getValueType() == MVT::i8) {
733 switch (Ptr.getOpcode()) {
734 case ISD::TargetExternalSymbol:
736 Hi = DAG.getConstant(1, MVT::i8);
741 // Expansion of FrameIndex has Lo/Hi parts
742 if (isDirectAddress(Ptr)) {
743 SDValue TFI = Ptr.getOperand(0).getOperand(0);
745 if (TFI.getOpcode() == ISD::TargetFrameIndex) {
746 LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
747 Hi = DAG.getConstant(1, MVT::i8);
748 Offset += FrameOffset;
750 } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
751 // FrameIndex has already been expanded.
752 // Now just make use of its expansion
754 Hi = DAG.getConstant(1, MVT::i8);
755 SDValue FOffset = Ptr.getOperand(0).getOperand(1);
756 assert (FOffset.getOpcode() == ISD::Constant &&
757 "Invalid operand of PIC16ISD::Lo");
758 Offset += dyn_cast<ConstantSDNode>(FOffset)->getZExtValue();
763 if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
764 // Direct addressing case for RAM variables. The Hi part is constant
765 // and the Lo part is the TGA itself.
766 Lo = Ptr.getOperand(0).getOperand(0);
768 // For direct addresses Hi is a constant. Value 1 for the constant
769 // signifies that banksel needs to generated for it. Value 0 for
770 // the constant signifies that banksel does not need to be generated
771 // for it. Mark it as 1 now and optimize later.
772 Hi = DAG.getConstant(1, MVT::i8);
776 // Indirect addresses. Get the hi and lo parts of ptr.
777 GetExpandedParts(Ptr, DAG, Lo, Hi);
779 // Put the hi and lo parts into FSR.
780 Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
781 Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
786 SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
787 LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
788 SDValue Chain = LD->getChain();
789 SDValue Ptr = LD->getBasePtr();
790 DebugLoc dl = LD->getDebugLoc();
792 SDValue Load, Offset;
795 SDValue PtrLo, PtrHi;
798 // Legalize direct/indirect addresses. This will give the lo and hi parts
799 // of the address and the offset.
800 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
802 // Load from the pointer (direct address or FSR)
803 VT = N->getValueType(0);
804 unsigned NumLoads = VT.getSizeInBits() / 8;
805 std::vector<SDValue> PICLoads;
807 MVT MemVT = LD->getMemoryVT();
808 if(ISD::isNON_EXTLoad(N)) {
809 for (iter=0; iter<NumLoads ; ++iter) {
810 // Add the pointer offset if any
811 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
812 Tys = DAG.getVTList(MVT::i8, MVT::Other);
813 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
815 PICLoads.push_back(Load);
818 // If it is extended load then use PIC16Load for Memory Bytes
819 // and for all extended bytes perform action based on type of
820 // extention - i.e. SignExtendedLoad or ZeroExtendedLoad
823 // For extended loads this is the memory value type
824 // i.e. without any extension
825 MVT MemVT = LD->getMemoryVT();
826 unsigned MemBytes = MemVT.getSizeInBits() / 8;
827 // if MVT::i1 is extended to MVT::i8 then MemBytes will be zero
829 if (MemBytes == 0) MemBytes = 1;
831 unsigned ExtdBytes = VT.getSizeInBits() / 8;
832 Offset = DAG.getConstant(LoadOffset, MVT::i8);
834 Tys = DAG.getVTList(MVT::i8, MVT::Other);
835 // For MemBytes generate PIC16Load with proper offset
836 for (iter=0; iter < MemBytes; ++iter) {
837 // Add the pointer offset if any
838 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
839 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
841 PICLoads.push_back(Load);
844 // For SignExtendedLoad
845 if (ISD::isSEXTLoad(N)) {
846 // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
848 SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
849 DAG.getConstant(7, MVT::i8));
850 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
851 PICLoads.push_back(SRA);
853 } else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
854 //} else if (ISD::isZEXTLoad(N)) {
855 // ZeroExtendedLoad -- For all ExtdBytes use constant 0
856 SDValue ConstZero = DAG.getConstant(0, MVT::i8);
857 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
858 PICLoads.push_back(ConstZero);
865 // Operand of Load is illegal -- Load itself is legal
868 else if (VT == MVT::i16) {
869 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
870 if (MemVT == MVT::i8)
871 Chain = getChain(PICLoads[0]);
873 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
874 getChain(PICLoads[0]), getChain(PICLoads[1]));
875 } else if (VT == MVT::i32) {
877 BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
878 PICLoads[0], PICLoads[1]);
879 BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
880 PICLoads[2], PICLoads[3]);
881 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
882 if (MemVT == MVT::i8)
883 Chain = getChain(PICLoads[0]);
884 else if (MemVT == MVT::i16)
885 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
886 getChain(PICLoads[0]), getChain(PICLoads[1]));
889 Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
890 getChain(PICLoads[0]), getChain(PICLoads[1]));
891 Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
892 getChain(PICLoads[2]), getChain(PICLoads[3]));
893 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
894 Chains[0], Chains[1]);
897 Tys = DAG.getVTList(VT, MVT::Other);
898 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
901 SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
902 // We should have handled larger operands in type legalizer itself.
903 assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
905 SDNode *N = Op.getNode();
906 SDValue Value = N->getOperand(0);
907 SDValue Amt = N->getOperand(1);
908 PIC16ISD::PIC16Libcall CallCode;
909 switch (N->getOpcode()) {
911 CallCode = PIC16ISD::SRA_I8;
914 CallCode = PIC16ISD::SLL_I8;
917 CallCode = PIC16ISD::SRL_I8;
920 assert ( 0 && "This shift is not implemented yet.");
923 SmallVector<SDValue, 2> Ops(2);
926 SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
927 true, DAG, N->getDebugLoc());
931 SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
932 // We should have handled larger operands in type legalizer itself.
933 assert (Op.getValueType() == MVT::i8 && "illegal multiply to lower");
935 SDNode *N = Op.getNode();
936 SmallVector<SDValue, 2> Ops(2);
937 Ops[0] = N->getOperand(0);
938 Ops[1] = N->getOperand(1);
939 SDValue Call = MakePIC16Libcall(PIC16ISD::MUL_I8, N->getValueType(0),
940 &Ops[0], 2, true, DAG, N->getDebugLoc());
945 PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
946 SmallVectorImpl<SDValue>&Results,
948 SDValue Op = SDValue(N, 0);
951 switch (Op.getOpcode()) {
952 case ISD::FORMAL_ARGUMENTS:
953 Res = LowerFORMAL_ARGUMENTS(Op, DAG); break;
955 Res = ExpandLoad(Op.getNode(), DAG); break;
957 Res = LowerCALL(Op, DAG); break;
959 // All other operations are handled in LowerOperation.
960 Res = LowerOperation(Op, DAG);
962 Results.push_back(Res);
969 unsigned NumValues = N->getNumValues();
970 for (i = 0; i < NumValues ; i++) {
971 Results.push_back(SDValue(N, i));
975 SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
976 switch (Op.getOpcode()) {
977 case ISD::FORMAL_ARGUMENTS:
978 return LowerFORMAL_ARGUMENTS(Op, DAG);
982 return LowerADD(Op, DAG);
986 return LowerSUB(Op, DAG);
988 return ExpandLoad(Op.getNode(), DAG);
990 return ExpandStore(Op.getNode(), DAG);
992 return LowerMUL(Op, DAG);
996 return LowerShift(Op, DAG);
1000 return LowerBinOp(Op, DAG);
1002 return LowerCALL(Op, DAG);
1004 return LowerRET(Op, DAG);
1006 return LowerBR_CC(Op, DAG);
1007 case ISD::SELECT_CC:
1008 return LowerSELECT_CC(Op, DAG);
1013 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
1016 assert (Op.getValueType() == MVT::i8
1017 && "illegal value type to store on stack.");
1019 MachineFunction &MF = DAG.getMachineFunction();
1020 const Function *Func = MF.getFunction();
1021 const std::string FuncName = Func->getName();
1024 // Put the value on stack.
1025 // Get a stack slot index and convert to es.
1026 int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
1027 const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
1028 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1030 // Store the value to ES.
1031 SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
1034 DAG.getConstant (1, MVT::i8), // Banksel.
1035 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1038 // Load the value from ES.
1039 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
1040 SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
1041 ES, DAG.getConstant (1, MVT::i8),
1042 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1045 return Load.getValue(0);
1048 SDValue PIC16TargetLowering::
1049 LowerIndirectCallArguments(SDValue Op, SDValue Chain, SDValue InFlag,
1050 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1051 SelectionDAG &DAG) {
1052 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1053 unsigned NumOps = TheCall->getNumArgs();
1054 DebugLoc dl = TheCall->getDebugLoc();
1056 // If call has no arguments then do nothing and return.
1060 std::vector<SDValue> Ops;
1061 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1062 SDValue Arg, StoreRet;
1064 // For PIC16 ABI the arguments come after the return value.
1065 unsigned RetVals = TheCall->getNumRetVals();
1066 for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
1067 // Get the arguments
1068 Arg = TheCall->getArg(i);
1071 Ops.push_back(Chain);
1073 Ops.push_back(DataAddr_Lo);
1074 Ops.push_back(DataAddr_Hi);
1075 Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
1076 Ops.push_back(InFlag);
1078 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1080 Chain = getChain(StoreRet);
1081 InFlag = getOutFlag(StoreRet);
1087 SDValue PIC16TargetLowering::
1088 LowerDirectCallArguments(SDValue Op, SDValue Chain, SDValue ArgLabel,
1089 SDValue InFlag, SelectionDAG &DAG) {
1090 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1091 unsigned NumOps = TheCall->getNumArgs();
1092 DebugLoc dl = TheCall->getDebugLoc();
1094 SDValue Arg, StoreAt;
1097 unsigned ArgCount=0;
1099 // If call has no arguments then do nothing and return.
1103 // FIXME: This portion of code currently assumes only
1104 // primitive types being passed as arguments.
1106 // Legalize the address before use
1107 SDValue PtrLo, PtrHi;
1108 unsigned AddressOffset;
1109 int StoreOffset = 0;
1110 LegalizeAddress(ArgLabel, DAG, PtrLo, PtrHi, AddressOffset, dl);
1113 std::vector<SDValue> Ops;
1114 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1115 for (unsigned i=ArgCount, Offset = 0; i<NumOps; i++) {
1117 Arg = TheCall->getArg(i);
1118 StoreOffset = (Offset + AddressOffset);
1120 // Store the argument on frame
1123 Ops.push_back(Chain);
1125 Ops.push_back(PtrLo);
1126 Ops.push_back(PtrHi);
1127 Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
1128 Ops.push_back(InFlag);
1130 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1132 Chain = getChain(StoreRet);
1133 InFlag = getOutFlag(StoreRet);
1135 // Update the frame offset to be used for next argument
1136 ArgVT = Arg.getValueType();
1137 Size = ArgVT.getSizeInBits();
1138 Size = Size/8; // Calculate size in bytes
1139 Offset += Size; // Increase the frame offset
1144 SDValue PIC16TargetLowering::
1145 LowerIndirectCallReturn (SDValue Op, SDValue Chain, SDValue InFlag,
1146 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1147 SelectionDAG &DAG) {
1148 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1149 DebugLoc dl = TheCall->getDebugLoc();
1150 unsigned RetVals = TheCall->getNumRetVals();
1152 // If call does not have anything to return
1153 // then do nothing and go back.
1157 // Call has something to return
1158 std::vector<SDValue> ResultVals;
1161 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1162 for(unsigned i=0;i<RetVals;i++) {
1163 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
1164 DataAddr_Hi, DAG.getConstant(i, MVT::i8),
1166 InFlag = getOutFlag(LoadRet);
1167 Chain = getChain(LoadRet);
1168 ResultVals.push_back(LoadRet);
1170 ResultVals.push_back(Chain);
1171 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1175 SDValue PIC16TargetLowering::
1176 LowerDirectCallReturn(SDValue Op, SDValue Chain, SDValue RetLabel,
1177 SDValue InFlag, SelectionDAG &DAG) {
1178 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1179 DebugLoc dl = TheCall->getDebugLoc();
1180 // Currently handling primitive types only. They will come in
1182 unsigned RetVals = TheCall->getNumRetVals();
1184 std::vector<SDValue> ResultVals;
1186 // Return immediately if the return type is void
1190 // Call has something to return
1192 // Legalize the address before use
1195 LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl);
1197 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1200 for(unsigned i=0, Offset=0;i<RetVals;i++) {
1202 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
1203 DAG.getConstant(LdOffset + Offset, MVT::i8),
1206 InFlag = getOutFlag(LoadRet);
1208 Chain = getChain(LoadRet);
1210 ResultVals.push_back(LoadRet);
1213 // To return use MERGE_VALUES
1214 ResultVals.push_back(Chain);
1215 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1219 SDValue PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1220 SDValue Chain = Op.getOperand(0);
1221 DebugLoc dl = Op.getDebugLoc();
1223 if (Op.getNumOperands() == 1) // return void
1226 // return should have odd number of operands
1227 if ((Op.getNumOperands() % 2) == 0 ) {
1228 llvm_unreachable("Do not know how to return this many arguments!");
1231 // Number of values to return
1232 unsigned NumRet = (Op.getNumOperands() / 2);
1234 // Function returns value always on stack with the offset starting
1236 MachineFunction &MF = DAG.getMachineFunction();
1237 const Function *F = MF.getFunction();
1238 std::string FuncName = F->getName();
1240 const char *tmpName = createESName(PAN::getFrameLabel(FuncName));
1241 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1242 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1243 SDValue BS = DAG.getConstant(1, MVT::i8);
1245 for(unsigned i=0;i<NumRet; ++i) {
1246 RetVal = Op.getNode()->getOperand(2*i + 1);
1247 Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
1249 DAG.getConstant (i, MVT::i8));
1252 return DAG.getNode(ISD::RET, dl, MVT::Other, Chain);
1255 // CALL node may have some operands non-legal to PIC16. Generate new CALL
1256 // node with all the operands legal.
1257 // Currently only Callee operand of the CALL node is non-legal. This function
1258 // legalizes the Callee operand and uses all other operands as are to generate
1261 SDValue PIC16TargetLowering::LegalizeCALL(SDValue Op, SelectionDAG &DAG) {
1262 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1263 SDValue Chain = TheCall->getChain();
1264 SDValue Callee = TheCall->getCallee();
1265 DebugLoc dl = TheCall->getDebugLoc();
1268 assert(Callee.getValueType() == MVT::i16 &&
1269 "Don't know how to legalize this call node!!!");
1270 assert(Callee.getOpcode() == ISD::BUILD_PAIR &&
1271 "Don't know how to legalize this call node!!!");
1273 if (isDirectAddress(Callee)) {
1274 // Come here for direct calls
1275 Callee = Callee.getOperand(0).getOperand(0);
1277 // Come here for indirect calls
1279 // Indirect addresses. Get the hi and lo parts of ptr.
1280 GetExpandedParts(Callee, DAG, Lo, Hi);
1281 // Connect Lo and Hi parts of the callee with the PIC16Connect
1282 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1284 std::vector<SDValue> Ops;
1285 Ops.push_back(Chain);
1286 Ops.push_back(Callee);
1288 // Add the call arguments and their flags
1289 unsigned NumArgs = TheCall->getNumArgs();
1290 for(i=0;i<NumArgs;i++) {
1291 Ops.push_back(TheCall->getArg(i));
1292 Ops.push_back(TheCall->getArgFlagsVal(i));
1294 std::vector<MVT> NodeTys;
1295 unsigned NumRets = TheCall->getNumRetVals();
1296 for(i=0;i<NumRets;i++)
1297 NodeTys.push_back(TheCall->getRetValType(i));
1299 // Return a Chain as well
1300 NodeTys.push_back(MVT::Other);
1302 SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size());
1303 // Generate new call with all the operands legal
1304 return DAG.getCall(TheCall->getCallingConv(), dl,
1305 TheCall->isVarArg(), TheCall->isTailCall(),
1306 TheCall->isInreg(), VTs, &Ops[0], Ops.size(),
1307 TheCall->getNumFixedArgs());
1310 void PIC16TargetLowering::
1311 GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
1312 SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
1313 SelectionDAG &DAG) {
1314 assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
1315 && "Don't know what to do of such callee!!");
1316 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1317 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1318 Chain = getChain(SeqStart);
1319 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1321 // Get the Lo and Hi part of code address
1322 SDValue Lo = Callee.getOperand(0);
1323 SDValue Hi = Callee.getOperand(1);
1325 SDValue Data_Lo, Data_Hi;
1326 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1327 // Subtract 2 from Address to get the Lower part of DataAddress.
1328 SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
1329 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1330 DAG.getConstant(2, MVT::i8));
1331 SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1332 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3);
1333 SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1334 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1335 SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
1337 Chain = getChain(Call);
1338 OperFlag = getOutFlag(Call);
1339 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1341 Chain = getChain(SeqEnd);
1342 OperFlag = getOutFlag(SeqEnd);
1344 // Low part of Data Address
1345 DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
1347 // Make the second call.
1348 SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1349 Chain = getChain(SeqStart);
1350 OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1352 // Subtract 1 from Address to get high part of data address.
1353 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1354 DAG.getConstant(1, MVT::i8));
1355 SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1356 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1357 PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1359 // Use new Lo to make another CALLW
1360 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1361 Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
1362 Chain = getChain(Call);
1363 OperFlag = getOutFlag(Call);
1364 SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1366 Chain = getChain(SeqEnd);
1367 OperFlag = getOutFlag(SeqEnd);
1368 // Hi part of Data Address
1369 DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
1373 SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1374 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1375 SDValue Chain = TheCall->getChain();
1376 SDValue Callee = TheCall->getCallee();
1377 DebugLoc dl = TheCall->getDebugLoc();
1378 if (Callee.getValueType() == MVT::i16 &&
1379 Callee.getOpcode() == ISD::BUILD_PAIR) {
1380 // Control should come here only from TypeLegalizer for lowering
1382 // Legalize the non-legal arguments of call and return the
1383 // new call with legal arguments.
1384 return LegalizeCALL(Op, DAG);
1386 // Control should come here from Legalize DAG.
1387 // Here all the operands of CALL node should be legal.
1389 // If this is an indirect call then to pass the arguments
1390 // and read the return value back, we need the data address
1391 // of the function being called.
1392 // To get the data address two more calls need to be made.
1394 // The flag to track if this is a direct or indirect call.
1395 bool IsDirectCall = true;
1396 unsigned RetVals = TheCall->getNumRetVals();
1397 unsigned NumArgs = TheCall->getNumArgs();
1399 SDValue DataAddr_Lo, DataAddr_Hi;
1400 if (Callee.getOpcode() == PIC16ISD::PIC16Connect) {
1401 IsDirectCall = false; // This is indirect call
1402 // Read DataAddress only if we have to pass arguments or
1403 // read return value.
1404 if ((RetVals > 0) || (NumArgs > 0))
1405 GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
1408 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1410 // Start the call sequence.
1411 // Carring the Constant 0 along the CALLSEQSTART
1412 // because there is nothing else to carry.
1413 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1414 Chain = getChain(SeqStart);
1415 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1418 // For any direct call - callee will be GlobalAddressNode or
1420 SDValue ArgLabel, RetLabel;
1422 // Considering the GlobalAddressNode case here.
1423 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1424 GlobalValue *GV = G->getGlobal();
1425 Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
1426 Name = G->getGlobal()->getName();
1427 } else {// Considering the ExternalSymbol case here
1428 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
1429 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
1430 Name = ES->getSymbol();
1433 // Label for argument passing
1434 const char *argFrame = createESName(PAN::getArgsLabel(Name));
1435 ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
1437 // Label for reading return value
1438 const char *retName = createESName(PAN::getRetvalLabel(Name));
1439 RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
1442 SDValue CodeAddr_Lo = Callee.getOperand(0);
1443 SDValue CodeAddr_Hi = Callee.getOperand(1);
1445 /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
1446 DAG.getConstant(2, MVT::i8));*/
1448 // move Hi part in PCLATH
1449 CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
1450 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
1454 // Pass the argument to function before making the call.
1457 CallArgs = LowerDirectCallArguments(Op, Chain, ArgLabel, OperFlag, DAG);
1458 Chain = getChain(CallArgs);
1459 OperFlag = getOutFlag(CallArgs);
1461 CallArgs = LowerIndirectCallArguments(Op, Chain, OperFlag, DataAddr_Lo,
1463 Chain = getChain(CallArgs);
1464 OperFlag = getOutFlag(CallArgs);
1467 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1468 SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
1470 Chain = getChain(PICCall);
1471 OperFlag = getOutFlag(PICCall);
1474 // Carrying the Constant 0 along the CALLSEQSTART
1475 // because there is nothing else to carry.
1476 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1478 Chain = getChain(SeqEnd);
1479 OperFlag = getOutFlag(SeqEnd);
1481 // Lower the return value reading after the call.
1483 return LowerDirectCallReturn(Op, Chain, RetLabel, OperFlag, DAG);
1485 return LowerIndirectCallReturn(Op, Chain, OperFlag, DataAddr_Lo,
1489 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
1490 if (Op.getOpcode() == PIC16ISD::PIC16Load)
1491 if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
1492 || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
1497 // NeedToConvertToMemOp - Returns true if one of the operands of the
1498 // operation 'Op' needs to be put into memory. Also returns the
1499 // operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
1500 // no instruction that can operation on two registers. Most insns take
1501 // one register and one memory operand (addwf) / Constant (addlw).
1502 bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
1503 // If one of the operand is a constant, return false.
1504 if (Op.getOperand(0).getOpcode() == ISD::Constant ||
1505 Op.getOperand(1).getOpcode() == ISD::Constant)
1508 // Return false if one of the operands is already a direct
1509 // load and that operand has only one use.
1510 if (isDirectLoad(Op.getOperand(0))) {
1511 if (Op.getOperand(0).hasOneUse())
1516 if (isDirectLoad(Op.getOperand(1))) {
1517 if (Op.getOperand(1).hasOneUse())
1525 // LowerBinOp - Lower a commutative binary operation that does not
1526 // affect status flag carry.
1527 SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) {
1528 DebugLoc dl = Op.getDebugLoc();
1530 // We should have handled larger operands in type legalizer itself.
1531 assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
1534 if (NeedToConvertToMemOp(Op, MemOp)) {
1535 // Put one value on stack.
1536 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1538 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1546 // LowerADD - Lower all types of ADD operations including the ones
1547 // that affects carry.
1548 SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
1549 // We should have handled larger operands in type legalizer itself.
1550 assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
1551 DebugLoc dl = Op.getDebugLoc();
1553 if (NeedToConvertToMemOp(Op, MemOp)) {
1554 // Put one value on stack.
1555 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1557 // ADDC and ADDE produce two results.
1558 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1560 // ADDE has three operands, the last one is the carry bit.
1561 if (Op.getOpcode() == ISD::ADDE)
1562 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1563 NewVal, Op.getOperand(2));
1564 // ADDC has two operands.
1565 else if (Op.getOpcode() == ISD::ADDC)
1566 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1568 // ADD it is. It produces only one result.
1570 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1577 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
1578 DebugLoc dl = Op.getDebugLoc();
1579 // We should have handled larger operands in type legalizer itself.
1580 assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
1582 // Nothing to do if the first operand is already a direct load and it has
1584 if (isDirectLoad(Op.getOperand(0)) && Op.getOperand(0).hasOneUse())
1587 // Put first operand on stack.
1588 SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
1590 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1591 switch (Op.getOpcode()) {
1593 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
1597 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
1600 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, NewVal, Op.getOperand(1));
1603 assert (0 && "Opcode unknown.");
1607 void PIC16TargetLowering::InitReservedFrameCount(const Function *F) {
1608 unsigned NumArgs = F->arg_size();
1610 bool isVoidFunc = (F->getReturnType()->getTypeID() == Type::VoidTyID);
1613 ReservedFrameCount = NumArgs;
1615 ReservedFrameCount = NumArgs + 1;
1618 // LowerFORMAL_ARGUMENTS - Argument values are loaded from the
1619 // <fname>.args + offset. All arguments are already broken to leaglized
1620 // types, so the offset just runs from 0 to NumArgVals - 1.
1622 SDValue PIC16TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1623 SelectionDAG &DAG) {
1624 SmallVector<SDValue, 8> ArgValues;
1625 unsigned NumArgVals = Op.getNode()->getNumValues() - 1;
1626 DebugLoc dl = Op.getDebugLoc();
1627 SDValue Chain = Op.getOperand(0); // Formal arguments' chain
1630 // Get the callee's name to create the <fname>.args label to pass args.
1631 MachineFunction &MF = DAG.getMachineFunction();
1632 const Function *F = MF.getFunction();
1633 std::string FuncName = F->getName();
1635 // Reset the map of FI and TmpOffset
1636 ResetTmpOffsetMap();
1637 // Initialize the ReserveFrameCount
1638 InitReservedFrameCount(F);
1640 // Create the <fname>.args external symbol.
1641 const char *tmpName = createESName(PAN::getArgsLabel(FuncName));
1642 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1644 // Load arg values from the label + offset.
1645 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1646 SDValue BS = DAG.getConstant(1, MVT::i8);
1647 for (unsigned i = 0; i < NumArgVals ; ++i) {
1648 SDValue Offset = DAG.getConstant(i, MVT::i8);
1649 SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
1651 Chain = getChain(PICLoad);
1652 ArgValues.push_back(PICLoad);
1655 // Return a MERGE_VALUE node.
1656 ArgValues.push_back(Op.getOperand(0));
1657 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1658 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1661 // Perform DAGCombine of PIC16Load.
1662 // FIXME - Need a more elaborate comment here.
1663 SDValue PIC16TargetLowering::
1664 PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1665 SelectionDAG &DAG = DCI.DAG;
1666 SDValue Chain = N->getOperand(0);
1667 if (N->hasNUsesOfValue(0, 0)) {
1668 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
1673 // For all the functions with arguments some STORE nodes are generated
1674 // that store the argument on the frameindex. However in PIC16 the arguments
1675 // are passed on stack only. Therefore these STORE nodes are redundant.
1676 // To remove these STORE nodes will be removed in PerformStoreCombine
1678 // Currently this function is doint nothing and will be updated for removing
1679 // unwanted store operations
1680 SDValue PIC16TargetLowering::
1681 PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1682 return SDValue(N, 0);
1684 // Storing an undef value is of no use, so remove it
1685 if (isStoringUndef(N, Chain, DAG)) {
1686 return Chain; // remove the store and return the chain
1688 //else everything is ok.
1689 return SDValue(N, 0);
1693 SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
1694 DAGCombinerInfo &DCI) const {
1695 switch (N->getOpcode()) {
1697 return PerformStoreCombine(N, DCI);
1698 case PIC16ISD::PIC16Load:
1699 return PerformPIC16LoadCombine(N, DCI);
1704 static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
1706 default: llvm_unreachable("Unknown condition code!");
1707 case ISD::SETNE: return PIC16CC::NE;
1708 case ISD::SETEQ: return PIC16CC::EQ;
1709 case ISD::SETGT: return PIC16CC::GT;
1710 case ISD::SETGE: return PIC16CC::GE;
1711 case ISD::SETLT: return PIC16CC::LT;
1712 case ISD::SETLE: return PIC16CC::LE;
1713 case ISD::SETULT: return PIC16CC::ULT;
1714 case ISD::SETULE: return PIC16CC::ULE;
1715 case ISD::SETUGE: return PIC16CC::UGE;
1716 case ISD::SETUGT: return PIC16CC::UGT;
1720 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1721 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1722 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1723 ISD::CondCode CC, unsigned &SPCC) {
1724 if (isa<ConstantSDNode>(RHS) &&
1725 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1727 (LHS.getOpcode() == PIC16ISD::SELECT_ICC &&
1728 LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) &&
1729 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1730 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1731 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
1732 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
1733 SDValue CMPCC = LHS.getOperand(3);
1734 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1735 LHS = CMPCC.getOperand(0);
1736 RHS = CMPCC.getOperand(1);
1740 // Returns appropriate CMP insn and corresponding condition code in PIC16CC
1741 SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
1742 unsigned CC, SDValue &PIC16CC,
1743 SelectionDAG &DAG, DebugLoc dl) {
1744 PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
1746 // PIC16 sub is literal - W. So Swap the operands and condition if needed.
1747 // i.e. a < 12 can be rewritten as 12 > a.
1748 if (RHS.getOpcode() == ISD::Constant) {
1757 CondCode = PIC16CC::GT;
1760 CondCode = PIC16CC::LT;
1763 CondCode = PIC16CC::UGT;
1766 CondCode = PIC16CC::ULT;
1769 CondCode = PIC16CC::LE;
1772 CondCode = PIC16CC::GE;
1775 CondCode = PIC16CC::UGE;
1778 CondCode = PIC16CC::ULE;
1783 PIC16CC = DAG.getConstant(CondCode, MVT::i8);
1785 // These are signed comparisons.
1786 SDValue Mask = DAG.getConstant(128, MVT::i8);
1787 if (isSignedComparison(CondCode)) {
1788 LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
1789 RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
1792 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
1793 // We can use a subtract operation to set the condition codes. But
1794 // we need to put one operand in memory if required.
1795 // Nothing to do if the first operand is already a valid type (direct load
1796 // for subwf and literal for sublw) and it is used by this operation only.
1797 if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
1799 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1801 // else convert the first operand to mem.
1802 LHS = ConvertToMemOperand (LHS, DAG, dl);
1803 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1807 SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1808 SDValue LHS = Op.getOperand(0);
1809 SDValue RHS = Op.getOperand(1);
1810 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1811 SDValue TrueVal = Op.getOperand(2);
1812 SDValue FalseVal = Op.getOperand(3);
1813 unsigned ORIGCC = ~0;
1814 DebugLoc dl = Op.getDebugLoc();
1816 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1817 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1819 // A setcc: lhs, rhs, cc is expanded by llvm to
1820 // select_cc: result of setcc, 0, 1, 0, setne
1821 // We can think of it as:
1822 // select_cc: lhs, rhs, 1, 0, cc
1823 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1824 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1827 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1829 return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
1830 FalseVal, PIC16CC, Cmp.getValue(1));
1834 PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1835 MachineBasicBlock *BB) const {
1836 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1837 unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
1838 DebugLoc dl = MI->getDebugLoc();
1840 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1841 // control-flow pattern. The incoming instruction knows the destination vreg
1842 // to set, the condition code register to branch on, the true/false values to
1843 // select between, and a branch opcode to use.
1844 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1845 MachineFunction::iterator It = BB;
1852 // fallthrough --> copy0MBB
1853 MachineBasicBlock *thisMBB = BB;
1854 MachineFunction *F = BB->getParent();
1855 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1856 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1857 BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
1858 F->insert(It, copy0MBB);
1859 F->insert(It, sinkMBB);
1861 // Update machine-CFG edges by transferring all successors of the current
1862 // block to the new block which will contain the Phi node for the select.
1863 sinkMBB->transferSuccessors(BB);
1864 // Next, add the true and fallthrough blocks as its successors.
1865 BB->addSuccessor(copy0MBB);
1866 BB->addSuccessor(sinkMBB);
1869 // %FalseValue = ...
1870 // # fallthrough to sinkMBB
1873 // Update machine-CFG edges
1874 BB->addSuccessor(sinkMBB);
1877 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1880 BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
1881 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1882 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1884 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1889 SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1890 SDValue Chain = Op.getOperand(0);
1891 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1892 SDValue LHS = Op.getOperand(2); // LHS of the condition.
1893 SDValue RHS = Op.getOperand(3); // RHS of the condition.
1894 SDValue Dest = Op.getOperand(4); // BB to jump to
1895 unsigned ORIGCC = ~0;
1896 DebugLoc dl = Op.getDebugLoc();
1898 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1899 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1900 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1901 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1903 // Get the Compare insn and condition code.
1905 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1907 return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,