1 //===- NVPTXInstrInfo.td - NVPTX Instruction defs -------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "NVPTXInstrFormats.td"
17 def NOP : NVPTXInst<(outs), (ins), "", []>;
19 // List of vector specific properties
20 def isVecLD : VecInstTypeEnum<1>;
21 def isVecST : VecInstTypeEnum<2>;
22 def isVecBuild : VecInstTypeEnum<3>;
23 def isVecShuffle : VecInstTypeEnum<4>;
24 def isVecExtract : VecInstTypeEnum<5>;
25 def isVecInsert : VecInstTypeEnum<6>;
26 def isVecDest : VecInstTypeEnum<7>;
27 def isVecOther : VecInstTypeEnum<15>;
29 //===----------------------------------------------------------------------===//
30 // NVPTX Operand Definitions.
31 //===----------------------------------------------------------------------===//
33 def brtarget : Operand<OtherVT>;
35 // CVT conversion modes
36 // These must match the enum in NVPTX.h
37 def CvtNONE : PatLeaf<(i32 0x0)>;
38 def CvtRNI : PatLeaf<(i32 0x1)>;
39 def CvtRZI : PatLeaf<(i32 0x2)>;
40 def CvtRMI : PatLeaf<(i32 0x3)>;
41 def CvtRPI : PatLeaf<(i32 0x4)>;
42 def CvtRN : PatLeaf<(i32 0x5)>;
43 def CvtRZ : PatLeaf<(i32 0x6)>;
44 def CvtRM : PatLeaf<(i32 0x7)>;
45 def CvtRP : PatLeaf<(i32 0x8)>;
47 def CvtNONE_FTZ : PatLeaf<(i32 0x10)>;
48 def CvtRNI_FTZ : PatLeaf<(i32 0x11)>;
49 def CvtRZI_FTZ : PatLeaf<(i32 0x12)>;
50 def CvtRMI_FTZ : PatLeaf<(i32 0x13)>;
51 def CvtRPI_FTZ : PatLeaf<(i32 0x14)>;
52 def CvtRN_FTZ : PatLeaf<(i32 0x15)>;
53 def CvtRZ_FTZ : PatLeaf<(i32 0x16)>;
54 def CvtRM_FTZ : PatLeaf<(i32 0x17)>;
55 def CvtRP_FTZ : PatLeaf<(i32 0x18)>;
57 def CvtSAT : PatLeaf<(i32 0x20)>;
58 def CvtSAT_FTZ : PatLeaf<(i32 0x30)>;
60 def CvtMode : Operand<i32> {
61 let PrintMethod = "printCvtMode";
65 // These must match the enum in NVPTX.h
66 def CmpEQ : PatLeaf<(i32 0)>;
67 def CmpNE : PatLeaf<(i32 1)>;
68 def CmpLT : PatLeaf<(i32 2)>;
69 def CmpLE : PatLeaf<(i32 3)>;
70 def CmpGT : PatLeaf<(i32 4)>;
71 def CmpGE : PatLeaf<(i32 5)>;
72 def CmpLO : PatLeaf<(i32 6)>;
73 def CmpLS : PatLeaf<(i32 7)>;
74 def CmpHI : PatLeaf<(i32 8)>;
75 def CmpHS : PatLeaf<(i32 9)>;
76 def CmpEQU : PatLeaf<(i32 10)>;
77 def CmpNEU : PatLeaf<(i32 11)>;
78 def CmpLTU : PatLeaf<(i32 12)>;
79 def CmpLEU : PatLeaf<(i32 13)>;
80 def CmpGTU : PatLeaf<(i32 14)>;
81 def CmpGEU : PatLeaf<(i32 15)>;
82 def CmpNUM : PatLeaf<(i32 16)>;
83 def CmpNAN : PatLeaf<(i32 17)>;
85 def CmpEQ_FTZ : PatLeaf<(i32 0x100)>;
86 def CmpNE_FTZ : PatLeaf<(i32 0x101)>;
87 def CmpLT_FTZ : PatLeaf<(i32 0x102)>;
88 def CmpLE_FTZ : PatLeaf<(i32 0x103)>;
89 def CmpGT_FTZ : PatLeaf<(i32 0x104)>;
90 def CmpGE_FTZ : PatLeaf<(i32 0x105)>;
91 def CmpLO_FTZ : PatLeaf<(i32 0x106)>;
92 def CmpLS_FTZ : PatLeaf<(i32 0x107)>;
93 def CmpHI_FTZ : PatLeaf<(i32 0x108)>;
94 def CmpHS_FTZ : PatLeaf<(i32 0x109)>;
95 def CmpEQU_FTZ : PatLeaf<(i32 0x10A)>;
96 def CmpNEU_FTZ : PatLeaf<(i32 0x10B)>;
97 def CmpLTU_FTZ : PatLeaf<(i32 0x10C)>;
98 def CmpLEU_FTZ : PatLeaf<(i32 0x10D)>;
99 def CmpGTU_FTZ : PatLeaf<(i32 0x10E)>;
100 def CmpGEU_FTZ : PatLeaf<(i32 0x10F)>;
101 def CmpNUM_FTZ : PatLeaf<(i32 0x110)>;
102 def CmpNAN_FTZ : PatLeaf<(i32 0x111)>;
104 def CmpMode : Operand<i32> {
105 let PrintMethod = "printCmpMode";
108 def F32ConstZero : Operand<f32>, PatLeaf<(f32 fpimm)>, SDNodeXForm<fpimm, [{
109 return CurDAG->getTargetConstantFP(0.0, MVT::f32);
111 def F32ConstOne : Operand<f32>, PatLeaf<(f32 fpimm)>, SDNodeXForm<fpimm, [{
112 return CurDAG->getTargetConstantFP(1.0, MVT::f32);
115 //===----------------------------------------------------------------------===//
116 // NVPTX Instruction Predicate Definitions
117 //===----------------------------------------------------------------------===//
120 def hasAtomRedG32 : Predicate<"Subtarget.hasAtomRedG32()">;
121 def hasAtomRedS32 : Predicate<"Subtarget.hasAtomRedS32()">;
122 def hasAtomRedGen32 : Predicate<"Subtarget.hasAtomRedGen32()">;
123 def useAtomRedG32forGen32 :
124 Predicate<"!Subtarget.hasAtomRedGen32() && Subtarget.hasAtomRedG32()">;
125 def hasBrkPt : Predicate<"Subtarget.hasBrkPt()">;
126 def hasAtomRedG64 : Predicate<"Subtarget.hasAtomRedG64()">;
127 def hasAtomRedS64 : Predicate<"Subtarget.hasAtomRedS64()">;
128 def hasAtomRedGen64 : Predicate<"Subtarget.hasAtomRedGen64()">;
129 def useAtomRedG64forGen64 :
130 Predicate<"!Subtarget.hasAtomRedGen64() && Subtarget.hasAtomRedG64()">;
131 def hasAtomAddF32 : Predicate<"Subtarget.hasAtomAddF32()">;
132 def hasVote : Predicate<"Subtarget.hasVote()">;
133 def hasDouble : Predicate<"Subtarget.hasDouble()">;
134 def reqPTX20 : Predicate<"Subtarget.reqPTX20()">;
135 def hasLDG : Predicate<"Subtarget.hasLDG()">;
136 def hasLDU : Predicate<"Subtarget.hasLDU()">;
137 def hasGenericLdSt : Predicate<"Subtarget.hasGenericLdSt()">;
139 def doF32FTZ : Predicate<"UseF32FTZ==1">;
140 def doNoF32FTZ : Predicate<"UseF32FTZ==0">;
142 def doFMAF32 : Predicate<"doFMAF32">;
143 def doFMAF32_ftz : Predicate<"(doFMAF32 && UseF32FTZ)">;
144 def doFMAF32AGG : Predicate<"doFMAF32AGG">;
145 def doFMAF32AGG_ftz : Predicate<"(doFMAF32AGG && UseF32FTZ)">;
146 def doFMAF64 : Predicate<"doFMAF64">;
147 def doFMAF64AGG : Predicate<"doFMAF64AGG">;
148 def doFMADF32 : Predicate<"doFMADF32">;
149 def doFMADF32_ftz : Predicate<"(doFMADF32 && UseF32FTZ)">;
151 def doMulWide : Predicate<"doMulWide">;
153 def allowFMA : Predicate<"allowFMA">;
154 def allowFMA_ftz : Predicate<"(allowFMA && UseF32FTZ)">;
156 def do_DIVF32_APPROX : Predicate<"do_DIVF32_PREC==0">;
157 def do_DIVF32_FULL : Predicate<"do_DIVF32_PREC==1">;
159 def do_SQRTF32_APPROX : Predicate<"do_SQRTF32_PREC==0">;
160 def do_SQRTF32_RN : Predicate<"do_SQRTF32_PREC==1">;
162 def hasHWROT32 : Predicate<"Subtarget.hasHWROT32()">;
164 def true : Predicate<"1">;
167 //===----------------------------------------------------------------------===//
168 // Some Common Instruction Class Templates
169 //===----------------------------------------------------------------------===//
171 multiclass I3<string OpcStr, SDNode OpNode> {
172 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
173 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
174 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
176 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
177 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
178 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
179 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
180 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
181 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
183 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
184 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
185 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
186 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
187 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
188 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
190 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
191 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
192 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
195 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
196 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
198 !strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
199 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
201 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
202 !strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
203 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
206 multiclass F3<string OpcStr, SDNode OpNode> {
207 def f64rr : NVPTXInst<(outs Float64Regs:$dst),
208 (ins Float64Regs:$a, Float64Regs:$b),
209 !strconcat(OpcStr, ".f64 \t$dst, $a, $b;"),
210 [(set Float64Regs:$dst,
211 (OpNode Float64Regs:$a, Float64Regs:$b))]>,
212 Requires<[allowFMA]>;
213 def f64ri : NVPTXInst<(outs Float64Regs:$dst),
214 (ins Float64Regs:$a, f64imm:$b),
215 !strconcat(OpcStr, ".f64 \t$dst, $a, $b;"),
216 [(set Float64Regs:$dst,
217 (OpNode Float64Regs:$a, fpimm:$b))]>,
218 Requires<[allowFMA]>;
219 def f32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
220 (ins Float32Regs:$a, Float32Regs:$b),
221 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a, $b;"),
222 [(set Float32Regs:$dst,
223 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
224 Requires<[allowFMA_ftz]>;
225 def f32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
226 (ins Float32Regs:$a, f32imm:$b),
227 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a, $b;"),
228 [(set Float32Regs:$dst,
229 (OpNode Float32Regs:$a, fpimm:$b))]>,
230 Requires<[allowFMA_ftz]>;
231 def f32rr : NVPTXInst<(outs Float32Regs:$dst),
232 (ins Float32Regs:$a, Float32Regs:$b),
233 !strconcat(OpcStr, ".f32 \t$dst, $a, $b;"),
234 [(set Float32Regs:$dst,
235 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
236 Requires<[allowFMA]>;
237 def f32ri : NVPTXInst<(outs Float32Regs:$dst),
238 (ins Float32Regs:$a, f32imm:$b),
239 !strconcat(OpcStr, ".f32 \t$dst, $a, $b;"),
240 [(set Float32Regs:$dst,
241 (OpNode Float32Regs:$a, fpimm:$b))]>,
242 Requires<[allowFMA]>;
245 multiclass F3_rn<string OpcStr, SDNode OpNode> {
246 def f64rr : NVPTXInst<(outs Float64Regs:$dst),
247 (ins Float64Regs:$a, Float64Regs:$b),
248 !strconcat(OpcStr, ".rn.f64 \t$dst, $a, $b;"),
249 [(set Float64Regs:$dst,
250 (OpNode Float64Regs:$a, Float64Regs:$b))]>;
251 def f64ri : NVPTXInst<(outs Float64Regs:$dst),
252 (ins Float64Regs:$a, f64imm:$b),
253 !strconcat(OpcStr, ".rn.f64 \t$dst, $a, $b;"),
254 [(set Float64Regs:$dst,
255 (OpNode Float64Regs:$a, fpimm:$b))]>;
256 def f32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
257 (ins Float32Regs:$a, Float32Regs:$b),
258 !strconcat(OpcStr, ".rn.ftz.f32 \t$dst, $a, $b;"),
259 [(set Float32Regs:$dst,
260 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
261 Requires<[doF32FTZ]>;
262 def f32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
263 (ins Float32Regs:$a, f32imm:$b),
264 !strconcat(OpcStr, ".rn.ftz.f32 \t$dst, $a, $b;"),
265 [(set Float32Regs:$dst,
266 (OpNode Float32Regs:$a, fpimm:$b))]>,
267 Requires<[doF32FTZ]>;
268 def f32rr : NVPTXInst<(outs Float32Regs:$dst),
269 (ins Float32Regs:$a, Float32Regs:$b),
270 !strconcat(OpcStr, ".rn.f32 \t$dst, $a, $b;"),
271 [(set Float32Regs:$dst,
272 (OpNode Float32Regs:$a, Float32Regs:$b))]>;
273 def f32ri : NVPTXInst<(outs Float32Regs:$dst),
274 (ins Float32Regs:$a, f32imm:$b),
275 !strconcat(OpcStr, ".rn.f32 \t$dst, $a, $b;"),
276 [(set Float32Regs:$dst,
277 (OpNode Float32Regs:$a, fpimm:$b))]>;
280 multiclass F2<string OpcStr, SDNode OpNode> {
281 def f64 : NVPTXInst<(outs Float64Regs:$dst), (ins Float64Regs:$a),
282 !strconcat(OpcStr, ".f64 \t$dst, $a;"),
283 [(set Float64Regs:$dst, (OpNode Float64Regs:$a))]>;
284 def f32_ftz : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$a),
285 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a;"),
286 [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>,
287 Requires<[doF32FTZ]>;
288 def f32 : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$a),
289 !strconcat(OpcStr, ".f32 \t$dst, $a;"),
290 [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>;
293 //===----------------------------------------------------------------------===//
294 // NVPTX Instructions.
295 //===----------------------------------------------------------------------===//
297 //-----------------------------------
298 // General Type Conversion
299 //-----------------------------------
301 // Generate a cvt to the given type from all possible types.
302 // Each instance takes a CvtMode immediate that defines the conversion mode to
303 // use. It can be CvtNONE to omit a conversion mode.
304 multiclass CVT_FROM_ALL<string FromName, RegisterClass RC> {
305 def _s16 : NVPTXInst<(outs RC:$dst),
306 (ins Int16Regs:$src, CvtMode:$mode),
307 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
308 FromName, ".s16\t$dst, $src;"),
310 def _u16 : NVPTXInst<(outs RC:$dst),
311 (ins Int16Regs:$src, CvtMode:$mode),
312 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
313 FromName, ".u16\t$dst, $src;"),
315 def _f16 : NVPTXInst<(outs RC:$dst),
316 (ins Int16Regs:$src, CvtMode:$mode),
317 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
318 FromName, ".f16\t$dst, $src;"),
320 def _s32 : NVPTXInst<(outs RC:$dst),
321 (ins Int32Regs:$src, CvtMode:$mode),
322 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
323 FromName, ".s32\t$dst, $src;"),
325 def _u32 : NVPTXInst<(outs RC:$dst),
326 (ins Int32Regs:$src, CvtMode:$mode),
327 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
328 FromName, ".u32\t$dst, $src;"),
330 def _s64 : NVPTXInst<(outs RC:$dst),
331 (ins Int64Regs:$src, CvtMode:$mode),
332 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
333 FromName, ".s64\t$dst, $src;"),
335 def _u64 : NVPTXInst<(outs RC:$dst),
336 (ins Int64Regs:$src, CvtMode:$mode),
337 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
338 FromName, ".u64\t$dst, $src;"),
340 def _f32 : NVPTXInst<(outs RC:$dst),
341 (ins Float32Regs:$src, CvtMode:$mode),
342 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
343 FromName, ".f32\t$dst, $src;"),
345 def _f64 : NVPTXInst<(outs RC:$dst),
346 (ins Float64Regs:$src, CvtMode:$mode),
347 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
348 FromName, ".f64\t$dst, $src;"),
352 // Generate a cvt to all possible types.
353 defm CVT_s16 : CVT_FROM_ALL<"s16", Int16Regs>;
354 defm CVT_u16 : CVT_FROM_ALL<"u16", Int16Regs>;
355 defm CVT_f16 : CVT_FROM_ALL<"f16", Int16Regs>;
356 defm CVT_s32 : CVT_FROM_ALL<"s32", Int32Regs>;
357 defm CVT_u32 : CVT_FROM_ALL<"u32", Int32Regs>;
358 defm CVT_s64 : CVT_FROM_ALL<"s64", Int64Regs>;
359 defm CVT_u64 : CVT_FROM_ALL<"u64", Int64Regs>;
360 defm CVT_f32 : CVT_FROM_ALL<"f32", Float32Regs>;
361 defm CVT_f64 : CVT_FROM_ALL<"f64", Float64Regs>;
363 //-----------------------------------
364 // Integer Arithmetic
365 //-----------------------------------
367 multiclass ADD_SUB_i1<SDNode OpNode> {
368 def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
369 "xor.pred \t$dst, $a, $b;",
370 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
371 def _ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
372 "xor.pred \t$dst, $a, $b;",
373 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, (imm):$b))]>;
376 defm ADD_i1 : ADD_SUB_i1<add>;
377 defm SUB_i1 : ADD_SUB_i1<sub>;
380 defm ADD : I3<"add.s", add>;
381 defm SUB : I3<"sub.s", sub>;
383 defm ADDCC : ADD_SUB_INT_32<"add.cc", addc>;
384 defm SUBCC : ADD_SUB_INT_32<"sub.cc", subc>;
386 defm ADDCCC : ADD_SUB_INT_32<"addc.cc", adde>;
387 defm SUBCCC : ADD_SUB_INT_32<"subc.cc", sube>;
389 //mul.wide PTX instruction
390 def SInt32Const : PatLeaf<(imm), [{
391 const APInt &v = N->getAPIntValue();
392 if (v.isSignedIntN(32))
397 def UInt32Const : PatLeaf<(imm), [{
398 const APInt &v = N->getAPIntValue();
404 def SInt16Const : PatLeaf<(imm), [{
405 const APInt &v = N->getAPIntValue();
406 if (v.isSignedIntN(16))
411 def UInt16Const : PatLeaf<(imm), [{
412 const APInt &v = N->getAPIntValue();
418 def Int5Const : PatLeaf<(imm), [{
419 const APInt &v = N->getAPIntValue();
420 // Check if 0 <= v < 32
421 // Only then the result from (x << v) will be i32
422 if (v.sge(0) && v.slt(32))
427 def Int4Const : PatLeaf<(imm), [{
428 const APInt &v = N->getAPIntValue();
429 // Check if 0 <= v < 16
430 // Only then the result from (x << v) will be i16
431 if (v.sge(0) && v.slt(16))
436 def SHL2MUL32 : SDNodeXForm<imm, [{
437 const APInt &v = N->getAPIntValue();
439 return CurDAG->getTargetConstant(temp.shl(v), MVT::i32);
442 def SHL2MUL16 : SDNodeXForm<imm, [{
443 const APInt &v = N->getAPIntValue();
445 return CurDAG->getTargetConstant(temp.shl(v), MVT::i16);
448 def MULWIDES64 : NVPTXInst<(outs Int64Regs:$dst),
449 (ins Int32Regs:$a, Int32Regs:$b),
450 "mul.wide.s32 \t$dst, $a, $b;", []>;
451 def MULWIDES64Imm : NVPTXInst<(outs Int64Regs:$dst),
452 (ins Int32Regs:$a, i64imm:$b),
453 "mul.wide.s32 \t$dst, $a, $b;", []>;
455 def MULWIDEU64 : NVPTXInst<(outs Int64Regs:$dst),
456 (ins Int32Regs:$a, Int32Regs:$b),
457 "mul.wide.u32 \t$dst, $a, $b;", []>;
458 def MULWIDEU64Imm : NVPTXInst<(outs Int64Regs:$dst),
459 (ins Int32Regs:$a, i64imm:$b),
460 "mul.wide.u32 \t$dst, $a, $b;", []>;
462 def MULWIDES32 : NVPTXInst<(outs Int32Regs:$dst),
463 (ins Int16Regs:$a, Int16Regs:$b),
464 "mul.wide.s16 \t$dst, $a, $b;", []>;
465 def MULWIDES32Imm : NVPTXInst<(outs Int32Regs:$dst),
466 (ins Int16Regs:$a, i32imm:$b),
467 "mul.wide.s16 \t$dst, $a, $b;", []>;
469 def MULWIDEU32 : NVPTXInst<(outs Int32Regs:$dst),
470 (ins Int16Regs:$a, Int16Regs:$b),
471 "mul.wide.u16 \t$dst, $a, $b;", []>;
472 def MULWIDEU32Imm : NVPTXInst<(outs Int32Regs:$dst),
473 (ins Int16Regs:$a, i32imm:$b),
474 "mul.wide.u16 \t$dst, $a, $b;", []>;
476 def : Pat<(shl (sext Int32Regs:$a), (i32 Int5Const:$b)),
477 (MULWIDES64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
478 Requires<[doMulWide]>;
479 def : Pat<(shl (zext Int32Regs:$a), (i32 Int5Const:$b)),
480 (MULWIDEU64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
481 Requires<[doMulWide]>;
483 def : Pat<(shl (sext Int16Regs:$a), (i16 Int4Const:$b)),
484 (MULWIDES32Imm Int16Regs:$a, (SHL2MUL16 node:$b))>,
485 Requires<[doMulWide]>;
486 def : Pat<(shl (zext Int16Regs:$a), (i16 Int4Const:$b)),
487 (MULWIDEU32Imm Int16Regs:$a, (SHL2MUL16 node:$b))>,
488 Requires<[doMulWide]>;
490 def : Pat<(mul (sext Int32Regs:$a), (sext Int32Regs:$b)),
491 (MULWIDES64 Int32Regs:$a, Int32Regs:$b)>,
492 Requires<[doMulWide]>;
493 def : Pat<(mul (sext Int32Regs:$a), (i64 SInt32Const:$b)),
494 (MULWIDES64Imm Int32Regs:$a, (i64 SInt32Const:$b))>,
495 Requires<[doMulWide]>;
497 def : Pat<(mul (zext Int32Regs:$a), (zext Int32Regs:$b)),
498 (MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>, Requires<[doMulWide]>;
499 def : Pat<(mul (zext Int32Regs:$a), (i64 UInt32Const:$b)),
500 (MULWIDEU64Imm Int32Regs:$a, (i64 UInt32Const:$b))>,
501 Requires<[doMulWide]>;
503 def : Pat<(mul (sext Int16Regs:$a), (sext Int16Regs:$b)),
504 (MULWIDES32 Int16Regs:$a, Int16Regs:$b)>, Requires<[doMulWide]>;
505 def : Pat<(mul (sext Int16Regs:$a), (i32 SInt16Const:$b)),
506 (MULWIDES32Imm Int16Regs:$a, (i32 SInt16Const:$b))>,
507 Requires<[doMulWide]>;
509 def : Pat<(mul (zext Int16Regs:$a), (zext Int16Regs:$b)),
510 (MULWIDEU32 Int16Regs:$a, Int16Regs:$b)>, Requires<[doMulWide]>;
511 def : Pat<(mul (zext Int16Regs:$a), (i32 UInt16Const:$b)),
512 (MULWIDEU32Imm Int16Regs:$a, (i32 UInt16Const:$b))>,
513 Requires<[doMulWide]>;
515 defm MULT : I3<"mul.lo.s", mul>;
517 defm MULTHS : I3<"mul.hi.s", mulhs>;
518 defm MULTHU : I3<"mul.hi.u", mulhu>;
520 defm SDIV : I3<"div.s", sdiv>;
521 defm UDIV : I3<"div.u", udiv>;
523 defm SREM : I3<"rem.s", srem>;
524 // The ri version will not be selected as DAGCombiner::visitSREM will lower it.
525 defm UREM : I3<"rem.u", urem>;
526 // The ri version will not be selected as DAGCombiner::visitUREM will lower it.
528 def MAD16rrr : NVPTXInst<(outs Int16Regs:$dst),
529 (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
530 "mad.lo.s16 \t$dst, $a, $b, $c;",
531 [(set Int16Regs:$dst, (add
532 (mul Int16Regs:$a, Int16Regs:$b), Int16Regs:$c))]>;
533 def MAD16rri : NVPTXInst<(outs Int16Regs:$dst),
534 (ins Int16Regs:$a, Int16Regs:$b, i16imm:$c),
535 "mad.lo.s16 \t$dst, $a, $b, $c;",
536 [(set Int16Regs:$dst, (add
537 (mul Int16Regs:$a, Int16Regs:$b), imm:$c))]>;
538 def MAD16rir : NVPTXInst<(outs Int16Regs:$dst),
539 (ins Int16Regs:$a, i16imm:$b, Int16Regs:$c),
540 "mad.lo.s16 \t$dst, $a, $b, $c;",
541 [(set Int16Regs:$dst, (add
542 (mul Int16Regs:$a, imm:$b), Int16Regs:$c))]>;
543 def MAD16rii : NVPTXInst<(outs Int16Regs:$dst),
544 (ins Int16Regs:$a, i16imm:$b, i16imm:$c),
545 "mad.lo.s16 \t$dst, $a, $b, $c;",
546 [(set Int16Regs:$dst, (add (mul Int16Regs:$a, imm:$b),
549 def MAD32rrr : NVPTXInst<(outs Int32Regs:$dst),
550 (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
551 "mad.lo.s32 \t$dst, $a, $b, $c;",
552 [(set Int32Regs:$dst, (add
553 (mul Int32Regs:$a, Int32Regs:$b), Int32Regs:$c))]>;
554 def MAD32rri : NVPTXInst<(outs Int32Regs:$dst),
555 (ins Int32Regs:$a, Int32Regs:$b, i32imm:$c),
556 "mad.lo.s32 \t$dst, $a, $b, $c;",
557 [(set Int32Regs:$dst, (add
558 (mul Int32Regs:$a, Int32Regs:$b), imm:$c))]>;
559 def MAD32rir : NVPTXInst<(outs Int32Regs:$dst),
560 (ins Int32Regs:$a, i32imm:$b, Int32Regs:$c),
561 "mad.lo.s32 \t$dst, $a, $b, $c;",
562 [(set Int32Regs:$dst, (add
563 (mul Int32Regs:$a, imm:$b), Int32Regs:$c))]>;
564 def MAD32rii : NVPTXInst<(outs Int32Regs:$dst),
565 (ins Int32Regs:$a, i32imm:$b, i32imm:$c),
566 "mad.lo.s32 \t$dst, $a, $b, $c;",
567 [(set Int32Regs:$dst, (add
568 (mul Int32Regs:$a, imm:$b), imm:$c))]>;
570 def MAD64rrr : NVPTXInst<(outs Int64Regs:$dst),
571 (ins Int64Regs:$a, Int64Regs:$b, Int64Regs:$c),
572 "mad.lo.s64 \t$dst, $a, $b, $c;",
573 [(set Int64Regs:$dst, (add
574 (mul Int64Regs:$a, Int64Regs:$b), Int64Regs:$c))]>;
575 def MAD64rri : NVPTXInst<(outs Int64Regs:$dst),
576 (ins Int64Regs:$a, Int64Regs:$b, i64imm:$c),
577 "mad.lo.s64 \t$dst, $a, $b, $c;",
578 [(set Int64Regs:$dst, (add
579 (mul Int64Regs:$a, Int64Regs:$b), imm:$c))]>;
580 def MAD64rir : NVPTXInst<(outs Int64Regs:$dst),
581 (ins Int64Regs:$a, i64imm:$b, Int64Regs:$c),
582 "mad.lo.s64 \t$dst, $a, $b, $c;",
583 [(set Int64Regs:$dst, (add
584 (mul Int64Regs:$a, imm:$b), Int64Regs:$c))]>;
585 def MAD64rii : NVPTXInst<(outs Int64Regs:$dst),
586 (ins Int64Regs:$a, i64imm:$b, i64imm:$c),
587 "mad.lo.s64 \t$dst, $a, $b, $c;",
588 [(set Int64Regs:$dst, (add
589 (mul Int64Regs:$a, imm:$b), imm:$c))]>;
592 def INEG16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
593 "neg.s16 \t$dst, $src;",
594 [(set Int16Regs:$dst, (ineg Int16Regs:$src))]>;
595 def INEG32 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
596 "neg.s32 \t$dst, $src;",
597 [(set Int32Regs:$dst, (ineg Int32Regs:$src))]>;
598 def INEG64 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
599 "neg.s64 \t$dst, $src;",
600 [(set Int64Regs:$dst, (ineg Int64Regs:$src))]>;
602 //-----------------------------------
603 // Floating Point Arithmetic
604 //-----------------------------------
607 def FloatConst1 : PatLeaf<(fpimm), [{
608 if (&(N->getValueAPF().getSemantics()) != &llvm::APFloat::IEEEsingle)
610 float f = (float)N->getValueAPF().convertToFloat();
613 // Constand (double)1.0
614 def DoubleConst1 : PatLeaf<(fpimm), [{
615 if (&(N->getValueAPF().getSemantics()) != &llvm::APFloat::IEEEdouble)
617 double d = (double)N->getValueAPF().convertToDouble();
621 defm FADD : F3<"add", fadd>;
622 defm FSUB : F3<"sub", fsub>;
623 defm FMUL : F3<"mul", fmul>;
625 defm FADD_rn : F3_rn<"add", fadd>;
626 defm FSUB_rn : F3_rn<"sub", fsub>;
627 defm FMUL_rn : F3_rn<"mul", fmul>;
629 defm FABS : F2<"abs", fabs>;
630 defm FNEG : F2<"neg", fneg>;
631 defm FSQRT : F2<"sqrt.rn", fsqrt>;
636 def FDIV641r : NVPTXInst<(outs Float64Regs:$dst),
637 (ins f64imm:$a, Float64Regs:$b),
638 "rcp.rn.f64 \t$dst, $b;",
639 [(set Float64Regs:$dst,
640 (fdiv DoubleConst1:$a, Float64Regs:$b))]>;
641 def FDIV64rr : NVPTXInst<(outs Float64Regs:$dst),
642 (ins Float64Regs:$a, Float64Regs:$b),
643 "div.rn.f64 \t$dst, $a, $b;",
644 [(set Float64Regs:$dst,
645 (fdiv Float64Regs:$a, Float64Regs:$b))]>;
646 def FDIV64ri : NVPTXInst<(outs Float64Regs:$dst),
647 (ins Float64Regs:$a, f64imm:$b),
648 "div.rn.f64 \t$dst, $a, $b;",
649 [(set Float64Regs:$dst,
650 (fdiv Float64Regs:$a, fpimm:$b))]>;
653 // F32 Approximate reciprocal
655 def FDIV321r_ftz : NVPTXInst<(outs Float32Regs:$dst),
656 (ins f32imm:$a, Float32Regs:$b),
657 "rcp.approx.ftz.f32 \t$dst, $b;",
658 [(set Float32Regs:$dst,
659 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
660 Requires<[do_DIVF32_APPROX, doF32FTZ]>;
661 def FDIV321r : NVPTXInst<(outs Float32Regs:$dst),
662 (ins f32imm:$a, Float32Regs:$b),
663 "rcp.approx.f32 \t$dst, $b;",
664 [(set Float32Regs:$dst,
665 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
666 Requires<[do_DIVF32_APPROX]>;
668 // F32 Approximate division
670 def FDIV32approxrr_ftz : NVPTXInst<(outs Float32Regs:$dst),
671 (ins Float32Regs:$a, Float32Regs:$b),
672 "div.approx.ftz.f32 \t$dst, $a, $b;",
673 [(set Float32Regs:$dst,
674 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
675 Requires<[do_DIVF32_APPROX, doF32FTZ]>;
676 def FDIV32approxrr : NVPTXInst<(outs Float32Regs:$dst),
677 (ins Float32Regs:$a, Float32Regs:$b),
678 "div.approx.f32 \t$dst, $a, $b;",
679 [(set Float32Regs:$dst,
680 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
681 Requires<[do_DIVF32_APPROX]>;
683 // F32 Semi-accurate reciprocal
685 // rcp.approx gives the same result as div.full(1.0f, a) and is faster.
687 def FDIV321r_approx_ftz : NVPTXInst<(outs Float32Regs:$dst),
688 (ins f32imm:$a, Float32Regs:$b),
689 "rcp.approx.ftz.f32 \t$dst, $b;",
690 [(set Float32Regs:$dst,
691 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
692 Requires<[do_DIVF32_FULL, doF32FTZ]>;
693 def FDIV321r_approx : NVPTXInst<(outs Float32Regs:$dst),
694 (ins f32imm:$a, Float32Regs:$b),
695 "rcp.approx.f32 \t$dst, $b;",
696 [(set Float32Regs:$dst,
697 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
698 Requires<[do_DIVF32_FULL]>;
700 // F32 Semi-accurate division
702 def FDIV32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
703 (ins Float32Regs:$a, Float32Regs:$b),
704 "div.full.ftz.f32 \t$dst, $a, $b;",
705 [(set Float32Regs:$dst,
706 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
707 Requires<[do_DIVF32_FULL, doF32FTZ]>;
708 def FDIV32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
709 (ins Float32Regs:$a, f32imm:$b),
710 "div.full.ftz.f32 \t$dst, $a, $b;",
711 [(set Float32Regs:$dst,
712 (fdiv Float32Regs:$a, fpimm:$b))]>,
713 Requires<[do_DIVF32_FULL, doF32FTZ]>;
714 def FDIV32rr : NVPTXInst<(outs Float32Regs:$dst),
715 (ins Float32Regs:$a, Float32Regs:$b),
716 "div.full.f32 \t$dst, $a, $b;",
717 [(set Float32Regs:$dst,
718 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
719 Requires<[do_DIVF32_FULL]>;
720 def FDIV32ri : NVPTXInst<(outs Float32Regs:$dst),
721 (ins Float32Regs:$a, f32imm:$b),
722 "div.full.f32 \t$dst, $a, $b;",
723 [(set Float32Regs:$dst,
724 (fdiv Float32Regs:$a, fpimm:$b))]>,
725 Requires<[do_DIVF32_FULL]>;
727 // F32 Accurate reciprocal
729 def FDIV321r_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
730 (ins f32imm:$a, Float32Regs:$b),
731 "rcp.rn.ftz.f32 \t$dst, $b;",
732 [(set Float32Regs:$dst,
733 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
734 Requires<[reqPTX20, doF32FTZ]>;
735 def FDIV321r_prec : NVPTXInst<(outs Float32Regs:$dst),
736 (ins f32imm:$a, Float32Regs:$b),
737 "rcp.rn.f32 \t$dst, $b;",
738 [(set Float32Regs:$dst,
739 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
740 Requires<[reqPTX20]>;
742 // F32 Accurate division
744 def FDIV32rr_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
745 (ins Float32Regs:$a, Float32Regs:$b),
746 "div.rn.ftz.f32 \t$dst, $a, $b;",
747 [(set Float32Regs:$dst,
748 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
749 Requires<[doF32FTZ, reqPTX20]>;
750 def FDIV32ri_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
751 (ins Float32Regs:$a, f32imm:$b),
752 "div.rn.ftz.f32 \t$dst, $a, $b;",
753 [(set Float32Regs:$dst,
754 (fdiv Float32Regs:$a, fpimm:$b))]>,
755 Requires<[doF32FTZ, reqPTX20]>;
756 def FDIV32rr_prec : NVPTXInst<(outs Float32Regs:$dst),
757 (ins Float32Regs:$a, Float32Regs:$b),
758 "div.rn.f32 \t$dst, $a, $b;",
759 [(set Float32Regs:$dst,
760 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
761 Requires<[reqPTX20]>;
762 def FDIV32ri_prec : NVPTXInst<(outs Float32Regs:$dst),
763 (ins Float32Regs:$a, f32imm:$b),
764 "div.rn.f32 \t$dst, $a, $b;",
765 [(set Float32Regs:$dst,
766 (fdiv Float32Regs:$a, fpimm:$b))]>,
767 Requires<[reqPTX20]>;
773 def RSQRTF32approx1r : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$b),
774 "rsqrt.approx.f32 \t$dst, $b;", []>;
776 def: Pat<(fdiv FloatConst1, (int_nvvm_sqrt_f Float32Regs:$b)),
777 (RSQRTF32approx1r Float32Regs:$b)>,
778 Requires<[do_DIVF32_FULL, do_SQRTF32_APPROX, doNoF32FTZ]>;
780 multiclass FPCONTRACT32<string OpcStr, Predicate Pred> {
781 def rrr : NVPTXInst<(outs Float32Regs:$dst),
782 (ins Float32Regs:$a, Float32Regs:$b, Float32Regs:$c),
783 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
784 [(set Float32Regs:$dst, (fadd
785 (fmul Float32Regs:$a, Float32Regs:$b),
786 Float32Regs:$c))]>, Requires<[Pred]>;
787 // This is to WAR a weird bug in Tablegen that does not automatically
788 // generate the following permutated rule rrr2 from the above rrr.
789 // So we explicitly add it here. This happens to FMA32 only.
790 // See the comments at FMAD32 and FMA32 for more information.
791 def rrr2 : NVPTXInst<(outs Float32Regs:$dst),
792 (ins Float32Regs:$a, Float32Regs:$b, Float32Regs:$c),
793 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
794 [(set Float32Regs:$dst, (fadd Float32Regs:$c,
795 (fmul Float32Regs:$a, Float32Regs:$b)))]>,
797 def rri : NVPTXInst<(outs Float32Regs:$dst),
798 (ins Float32Regs:$a, Float32Regs:$b, f32imm:$c),
799 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
800 [(set Float32Regs:$dst, (fadd
801 (fmul Float32Regs:$a, Float32Regs:$b), fpimm:$c))]>,
803 def rir : NVPTXInst<(outs Float32Regs:$dst),
804 (ins Float32Regs:$a, f32imm:$b, Float32Regs:$c),
805 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
806 [(set Float32Regs:$dst, (fadd
807 (fmul Float32Regs:$a, fpimm:$b), Float32Regs:$c))]>,
809 def rii : NVPTXInst<(outs Float32Regs:$dst),
810 (ins Float32Regs:$a, f32imm:$b, f32imm:$c),
811 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
812 [(set Float32Regs:$dst, (fadd
813 (fmul Float32Regs:$a, fpimm:$b), fpimm:$c))]>,
817 multiclass FPCONTRACT64<string OpcStr, Predicate Pred> {
818 def rrr : NVPTXInst<(outs Float64Regs:$dst),
819 (ins Float64Regs:$a, Float64Regs:$b, Float64Regs:$c),
820 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
821 [(set Float64Regs:$dst, (fadd
822 (fmul Float64Regs:$a, Float64Regs:$b),
823 Float64Regs:$c))]>, Requires<[Pred]>;
824 def rri : NVPTXInst<(outs Float64Regs:$dst),
825 (ins Float64Regs:$a, Float64Regs:$b, f64imm:$c),
826 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
827 [(set Float64Regs:$dst, (fadd (fmul Float64Regs:$a,
828 Float64Regs:$b), fpimm:$c))]>, Requires<[Pred]>;
829 def rir : NVPTXInst<(outs Float64Regs:$dst),
830 (ins Float64Regs:$a, f64imm:$b, Float64Regs:$c),
831 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
832 [(set Float64Regs:$dst, (fadd
833 (fmul Float64Regs:$a, fpimm:$b), Float64Regs:$c))]>,
835 def rii : NVPTXInst<(outs Float64Regs:$dst),
836 (ins Float64Regs:$a, f64imm:$b, f64imm:$c),
837 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
838 [(set Float64Regs:$dst, (fadd
839 (fmul Float64Regs:$a, fpimm:$b), fpimm:$c))]>,
843 // Due to a unknown reason (most likely a bug in tablegen), tablegen does not
844 // automatically generate the rrr2 rule from
845 // the rrr rule (see FPCONTRACT32) for FMA32, though it does for FMAD32.
846 // If we reverse the order of the following two lines, then rrr2 rule will be
847 // generated for FMA32, but not for rrr.
848 // Therefore, we manually write the rrr2 rule in FPCONTRACT32.
849 defm FMAD32_ftz : FPCONTRACT32<"mad.ftz.f32", doFMADF32_ftz>;
850 defm FMAD32 : FPCONTRACT32<"mad.f32", doFMADF32>;
851 defm FMA32_ftz : FPCONTRACT32<"fma.rn.ftz.f32", doFMAF32_ftz>;
852 defm FMA32 : FPCONTRACT32<"fma.rn.f32", doFMAF32>;
853 defm FMA64 : FPCONTRACT64<"fma.rn.f64", doFMAF64>;
855 // b*c-a => fmad(b, c, -a)
856 multiclass FPCONTRACT32_SUB_PAT_MAD<NVPTXInst Inst, Predicate Pred> {
857 def : Pat<(fsub (fmul Float32Regs:$b, Float32Regs:$c), Float32Regs:$a),
858 (Inst Float32Regs:$b, Float32Regs:$c, (FNEGf32 Float32Regs:$a))>,
862 // a-b*c => fmad(-b,c, a)
863 // - legal because a-b*c <=> a+(-b*c) <=> a+(-b)*c
864 // b*c-a => fmad(b, c, -a)
865 // - legal because b*c-a <=> b*c+(-a)
866 multiclass FPCONTRACT32_SUB_PAT<NVPTXInst Inst, Predicate Pred> {
867 def : Pat<(fsub Float32Regs:$a, (fmul Float32Regs:$b, Float32Regs:$c)),
868 (Inst (FNEGf32 Float32Regs:$b), Float32Regs:$c, Float32Regs:$a)>,
870 def : Pat<(fsub (fmul Float32Regs:$b, Float32Regs:$c), Float32Regs:$a),
871 (Inst Float32Regs:$b, Float32Regs:$c, (FNEGf32 Float32Regs:$a))>,
875 // a-b*c => fmad(-b,c, a)
876 // b*c-a => fmad(b, c, -a)
877 multiclass FPCONTRACT64_SUB_PAT<NVPTXInst Inst, Predicate Pred> {
878 def : Pat<(fsub Float64Regs:$a, (fmul Float64Regs:$b, Float64Regs:$c)),
879 (Inst (FNEGf64 Float64Regs:$b), Float64Regs:$c, Float64Regs:$a)>,
882 def : Pat<(fsub (fmul Float64Regs:$b, Float64Regs:$c), Float64Regs:$a),
883 (Inst Float64Regs:$b, Float64Regs:$c, (FNEGf64 Float64Regs:$a))>,
887 defm FMAF32ext_ftz : FPCONTRACT32_SUB_PAT<FMA32_ftzrrr, doFMAF32AGG_ftz>;
888 defm FMAF32ext : FPCONTRACT32_SUB_PAT<FMA32rrr, doFMAF32AGG>;
889 defm FMADF32ext_ftz : FPCONTRACT32_SUB_PAT_MAD<FMAD32_ftzrrr, doFMADF32_ftz>;
890 defm FMADF32ext : FPCONTRACT32_SUB_PAT_MAD<FMAD32rrr, doFMADF32>;
891 defm FMAF64ext : FPCONTRACT64_SUB_PAT<FMA64rrr, doFMAF64AGG>;
893 def SINF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
894 "sin.approx.f32 \t$dst, $src;",
895 [(set Float32Regs:$dst, (fsin Float32Regs:$src))]>;
896 def COSF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
897 "cos.approx.f32 \t$dst, $src;",
898 [(set Float32Regs:$dst, (fcos Float32Regs:$src))]>;
900 // Lower (frem x, y) into (sub x, (mul (floor (div x, y)) y))
901 // e.g. "poor man's fmod()"
904 def : Pat<(frem Float32Regs:$x, Float32Regs:$y),
905 (FSUBf32rr_ftz Float32Regs:$x, (FMULf32rr_ftz (CVT_f32_f32
906 (FDIV32rr_prec_ftz Float32Regs:$x, Float32Regs:$y), CvtRMI_FTZ),
908 Requires<[doF32FTZ]>;
909 def : Pat<(frem Float32Regs:$x, fpimm:$y),
910 (FSUBf32rr_ftz Float32Regs:$x, (FMULf32ri_ftz (CVT_f32_f32
911 (FDIV32ri_prec_ftz Float32Regs:$x, fpimm:$y), CvtRMI_FTZ),
913 Requires<[doF32FTZ]>;
916 def : Pat<(frem Float32Regs:$x, Float32Regs:$y),
917 (FSUBf32rr Float32Regs:$x, (FMULf32rr (CVT_f32_f32
918 (FDIV32rr_prec Float32Regs:$x, Float32Regs:$y), CvtRMI),
920 def : Pat<(frem Float32Regs:$x, fpimm:$y),
921 (FSUBf32rr Float32Regs:$x, (FMULf32ri (CVT_f32_f32
922 (FDIV32ri_prec Float32Regs:$x, fpimm:$y), CvtRMI),
926 def : Pat<(frem Float64Regs:$x, Float64Regs:$y),
927 (FSUBf64rr Float64Regs:$x, (FMULf64rr (CVT_f64_f64
928 (FDIV64rr Float64Regs:$x, Float64Regs:$y), CvtRMI),
930 def : Pat<(frem Float64Regs:$x, fpimm:$y),
931 (FSUBf64rr Float64Regs:$x, (FMULf64ri (CVT_f64_f64
932 (FDIV64ri Float64Regs:$x, fpimm:$y), CvtRMI),
935 //-----------------------------------
936 // Logical Arithmetic
937 //-----------------------------------
939 multiclass LOG_FORMAT<string OpcStr, SDNode OpNode> {
940 def b1rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
941 !strconcat(OpcStr, ".pred \t$dst, $a, $b;"),
942 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
943 def b1ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
944 !strconcat(OpcStr, ".pred \t$dst, $a, $b;"),
945 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, imm:$b))]>;
946 def b16rr: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
947 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
948 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
950 def b16ri: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
951 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
952 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, imm:$b))]>;
953 def b32rr: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
954 !strconcat(OpcStr, ".b32 \t$dst, $a, $b;"),
955 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
957 def b32ri: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
958 !strconcat(OpcStr, ".b32 \t$dst, $a, $b;"),
959 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
960 def b64rr: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
961 !strconcat(OpcStr, ".b64 \t$dst, $a, $b;"),
962 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
964 def b64ri: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
965 !strconcat(OpcStr, ".b64 \t$dst, $a, $b;"),
966 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
969 defm OR : LOG_FORMAT<"or", or>;
970 defm AND : LOG_FORMAT<"and", and>;
971 defm XOR : LOG_FORMAT<"xor", xor>;
973 def NOT1: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$src),
974 "not.pred \t$dst, $src;",
975 [(set Int1Regs:$dst, (not Int1Regs:$src))]>;
976 def NOT16: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
977 "not.b16 \t$dst, $src;",
978 [(set Int16Regs:$dst, (not Int16Regs:$src))]>;
979 def NOT32: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
980 "not.b32 \t$dst, $src;",
981 [(set Int32Regs:$dst, (not Int32Regs:$src))]>;
982 def NOT64: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
983 "not.b64 \t$dst, $src;",
984 [(set Int64Regs:$dst, (not Int64Regs:$src))]>;
986 // For shifts, the second src operand must be 32-bit value
987 multiclass LSHIFT_FORMAT<string OpcStr, SDNode OpNode> {
988 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a,
990 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
991 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
993 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
994 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
995 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
997 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
999 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1000 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1002 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
1003 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1004 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1006 def i32ii : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
1007 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1008 [(set Int32Regs:$dst, (OpNode (i32 imm:$a),
1010 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a,
1012 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1013 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1015 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
1016 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1017 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1021 defm SHL : LSHIFT_FORMAT<"shl.b", shl>;
1023 // For shifts, the second src operand must be 32-bit value
1024 // Need to add cvt for the 8-bits.
1025 multiclass RSHIFT_FORMAT<string OpcStr, SDNode OpNode> {
1026 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a,
1028 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1029 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1031 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
1032 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1033 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1035 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
1037 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1038 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1040 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
1041 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1042 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1044 def i32ii : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
1045 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1046 [(set Int32Regs:$dst, (OpNode (i32 imm:$a),
1048 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a,
1050 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1051 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1053 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
1054 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1055 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1059 defm SRA : RSHIFT_FORMAT<"shr.s", sra>;
1060 defm SRL : RSHIFT_FORMAT<"shr.u", srl>;
1063 def ROT32imm_sw : NVPTXInst<(outs Int32Regs:$dst),
1064 (ins Int32Regs:$src, i32imm:$amt1, i32imm:$amt2),
1065 !strconcat("{{\n\t",
1066 !strconcat(".reg .b32 %lhs;\n\t",
1067 !strconcat(".reg .b32 %rhs;\n\t",
1068 !strconcat("shl.b32 \t%lhs, $src, $amt1;\n\t",
1069 !strconcat("shr.b32 \t%rhs, $src, $amt2;\n\t",
1070 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1071 !strconcat("}}", ""))))))),
1074 def SUB_FRM_32 : SDNodeXForm<imm, [{
1075 return CurDAG->getTargetConstant(32-N->getZExtValue(), MVT::i32);
1078 def : Pat<(rotl Int32Regs:$src, (i32 imm:$amt)),
1079 (ROT32imm_sw Int32Regs:$src, imm:$amt, (SUB_FRM_32 node:$amt))>;
1080 def : Pat<(rotr Int32Regs:$src, (i32 imm:$amt)),
1081 (ROT32imm_sw Int32Regs:$src, (SUB_FRM_32 node:$amt), imm:$amt)>;
1083 def ROTL32reg_sw : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src,
1085 !strconcat("{{\n\t",
1086 !strconcat(".reg .b32 %lhs;\n\t",
1087 !strconcat(".reg .b32 %rhs;\n\t",
1088 !strconcat(".reg .b32 %amt2;\n\t",
1089 !strconcat("shl.b32 \t%lhs, $src, $amt;\n\t",
1090 !strconcat("sub.s32 \t%amt2, 32, $amt;\n\t",
1091 !strconcat("shr.b32 \t%rhs, $src, %amt2;\n\t",
1092 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1093 !strconcat("}}", ""))))))))),
1094 [(set Int32Regs:$dst, (rotl Int32Regs:$src, Int32Regs:$amt))]>;
1096 def ROTR32reg_sw : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src,
1098 !strconcat("{{\n\t",
1099 !strconcat(".reg .b32 %lhs;\n\t",
1100 !strconcat(".reg .b32 %rhs;\n\t",
1101 !strconcat(".reg .b32 %amt2;\n\t",
1102 !strconcat("shr.b32 \t%lhs, $src, $amt;\n\t",
1103 !strconcat("sub.s32 \t%amt2, 32, $amt;\n\t",
1104 !strconcat("shl.b32 \t%rhs, $src, %amt2;\n\t",
1105 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1106 !strconcat("}}", ""))))))))),
1107 [(set Int32Regs:$dst, (rotr Int32Regs:$src, Int32Regs:$amt))]>;
1110 def ROT64imm_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1111 i32imm:$amt1, i32imm:$amt2),
1112 !strconcat("{{\n\t",
1113 !strconcat(".reg .b64 %lhs;\n\t",
1114 !strconcat(".reg .b64 %rhs;\n\t",
1115 !strconcat("shl.b64 \t%lhs, $src, $amt1;\n\t",
1116 !strconcat("shr.b64 \t%rhs, $src, $amt2;\n\t",
1117 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1118 !strconcat("}}", ""))))))),
1121 def SUB_FRM_64 : SDNodeXForm<imm, [{
1122 return CurDAG->getTargetConstant(64-N->getZExtValue(), MVT::i32);
1125 def : Pat<(rotl Int64Regs:$src, (i32 imm:$amt)),
1126 (ROT64imm_sw Int64Regs:$src, imm:$amt, (SUB_FRM_64 node:$amt))>;
1127 def : Pat<(rotr Int64Regs:$src, (i32 imm:$amt)),
1128 (ROT64imm_sw Int64Regs:$src, (SUB_FRM_64 node:$amt), imm:$amt)>;
1130 def ROTL64reg_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1132 !strconcat("{{\n\t",
1133 !strconcat(".reg .b64 %lhs;\n\t",
1134 !strconcat(".reg .b64 %rhs;\n\t",
1135 !strconcat(".reg .u32 %amt2;\n\t",
1136 !strconcat("shl.b64 \t%lhs, $src, $amt;\n\t",
1137 !strconcat("sub.u32 \t%amt2, 64, $amt;\n\t",
1138 !strconcat("shr.b64 \t%rhs, $src, %amt2;\n\t",
1139 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1140 !strconcat("}}", ""))))))))),
1141 [(set Int64Regs:$dst, (rotl Int64Regs:$src, Int32Regs:$amt))]>;
1143 def ROTR64reg_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1145 !strconcat("{{\n\t",
1146 !strconcat(".reg .b64 %lhs;\n\t",
1147 !strconcat(".reg .b64 %rhs;\n\t",
1148 !strconcat(".reg .u32 %amt2;\n\t",
1149 !strconcat("shr.b64 \t%lhs, $src, $amt;\n\t",
1150 !strconcat("sub.u32 \t%amt2, 64, $amt;\n\t",
1151 !strconcat("shl.b64 \t%rhs, $src, %amt2;\n\t",
1152 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1153 !strconcat("}}", ""))))))))),
1154 [(set Int64Regs:$dst, (rotr Int64Regs:$src, Int32Regs:$amt))]>;
1157 //-----------------------------------
1158 // General Comparison
1159 //-----------------------------------
1161 // General setp instructions
1162 multiclass SETP<string TypeStr, RegisterClass RC, Operand ImmCls> {
1163 def rr : NVPTXInst<(outs Int1Regs:$dst),
1164 (ins RC:$a, RC:$b, CmpMode:$cmp),
1165 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1167 def ri : NVPTXInst<(outs Int1Regs:$dst),
1168 (ins RC:$a, ImmCls:$b, CmpMode:$cmp),
1169 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1171 def ir : NVPTXInst<(outs Int1Regs:$dst),
1172 (ins ImmCls:$a, RC:$b, CmpMode:$cmp),
1173 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1177 defm SETP_b16 : SETP<"b16", Int16Regs, i16imm>;
1178 defm SETP_s16 : SETP<"s16", Int16Regs, i16imm>;
1179 defm SETP_u16 : SETP<"u16", Int16Regs, i16imm>;
1180 defm SETP_b32 : SETP<"b32", Int32Regs, i32imm>;
1181 defm SETP_s32 : SETP<"s32", Int32Regs, i32imm>;
1182 defm SETP_u32 : SETP<"u32", Int32Regs, i32imm>;
1183 defm SETP_b64 : SETP<"b64", Int64Regs, i64imm>;
1184 defm SETP_s64 : SETP<"s64", Int64Regs, i64imm>;
1185 defm SETP_u64 : SETP<"u64", Int64Regs, i64imm>;
1186 defm SETP_f32 : SETP<"f32", Float32Regs, f32imm>;
1187 defm SETP_f64 : SETP<"f64", Float64Regs, f64imm>;
1189 // General set instructions
1190 multiclass SET<string TypeStr, RegisterClass RC, Operand ImmCls> {
1191 def rr : NVPTXInst<(outs Int32Regs:$dst),
1192 (ins RC:$a, RC:$b, CmpMode:$cmp),
1193 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1194 def ri : NVPTXInst<(outs Int32Regs:$dst),
1195 (ins RC:$a, ImmCls:$b, CmpMode:$cmp),
1196 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1197 def ir : NVPTXInst<(outs Int32Regs:$dst),
1198 (ins ImmCls:$a, RC:$b, CmpMode:$cmp),
1199 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1202 defm SET_b16 : SET<"b16", Int16Regs, i16imm>;
1203 defm SET_s16 : SET<"s16", Int16Regs, i16imm>;
1204 defm SET_u16 : SET<"u16", Int16Regs, i16imm>;
1205 defm SET_b32 : SET<"b32", Int32Regs, i32imm>;
1206 defm SET_s32 : SET<"s32", Int32Regs, i32imm>;
1207 defm SET_u32 : SET<"u32", Int32Regs, i32imm>;
1208 defm SET_b64 : SET<"b64", Int64Regs, i64imm>;
1209 defm SET_s64 : SET<"s64", Int64Regs, i64imm>;
1210 defm SET_u64 : SET<"u64", Int64Regs, i64imm>;
1211 defm SET_f32 : SET<"f32", Float32Regs, f32imm>;
1212 defm SET_f64 : SET<"f64", Float64Regs, f64imm>;
1214 //-----------------------------------
1215 // General Selection
1216 //-----------------------------------
1218 // General selp instructions
1219 multiclass SELP<string TypeStr, RegisterClass RC, Operand ImmCls> {
1220 def rr : NVPTXInst<(outs RC:$dst),
1221 (ins RC:$a, RC:$b, Int1Regs:$p),
1222 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1223 def ri : NVPTXInst<(outs RC:$dst),
1224 (ins RC:$a, ImmCls:$b, Int1Regs:$p),
1225 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1226 def ir : NVPTXInst<(outs RC:$dst),
1227 (ins ImmCls:$a, RC:$b, Int1Regs:$p),
1228 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1229 def ii : NVPTXInst<(outs RC:$dst),
1230 (ins ImmCls:$a, ImmCls:$b, Int1Regs:$p),
1231 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1234 multiclass SELP_PATTERN<string TypeStr, RegisterClass RC, Operand ImmCls,
1236 def rr : NVPTXInst<(outs RC:$dst),
1237 (ins RC:$a, RC:$b, Int1Regs:$p),
1238 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1239 [(set RC:$dst, (select Int1Regs:$p, RC:$a, RC:$b))]>;
1240 def ri : NVPTXInst<(outs RC:$dst),
1241 (ins RC:$a, ImmCls:$b, Int1Regs:$p),
1242 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1243 [(set RC:$dst, (select Int1Regs:$p, RC:$a, ImmNode:$b))]>;
1244 def ir : NVPTXInst<(outs RC:$dst),
1245 (ins ImmCls:$a, RC:$b, Int1Regs:$p),
1246 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1247 [(set RC:$dst, (select Int1Regs:$p, ImmNode:$a, RC:$b))]>;
1248 def ii : NVPTXInst<(outs RC:$dst),
1249 (ins ImmCls:$a, ImmCls:$b, Int1Regs:$p),
1250 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1251 [(set RC:$dst, (select Int1Regs:$p, ImmNode:$a, ImmNode:$b))]>;
1254 defm SELP_b16 : SELP_PATTERN<"b16", Int16Regs, i16imm, imm>;
1255 defm SELP_s16 : SELP<"s16", Int16Regs, i16imm>;
1256 defm SELP_u16 : SELP<"u16", Int16Regs, i16imm>;
1257 defm SELP_b32 : SELP_PATTERN<"b32", Int32Regs, i32imm, imm>;
1258 defm SELP_s32 : SELP<"s32", Int32Regs, i32imm>;
1259 defm SELP_u32 : SELP<"u32", Int32Regs, i32imm>;
1260 defm SELP_b64 : SELP_PATTERN<"b64", Int64Regs, i64imm, imm>;
1261 defm SELP_s64 : SELP<"s64", Int64Regs, i64imm>;
1262 defm SELP_u64 : SELP<"u64", Int64Regs, i64imm>;
1263 defm SELP_f32 : SELP_PATTERN<"f32", Float32Regs, f32imm, fpimm>;
1264 defm SELP_f64 : SELP_PATTERN<"f64", Float64Regs, f64imm, fpimm>;
1266 // Special select for predicate operands
1267 def : Pat<(i1 (select Int1Regs:$p, Int1Regs:$a, Int1Regs:$b)),
1268 (ORb1rr (ANDb1rr Int1Regs:$p, Int1Regs:$a),
1269 (ANDb1rr (NOT1 Int1Regs:$p), Int1Regs:$b))>;
1271 //-----------------------------------
1272 // Data Movement (Load / Store, Move)
1273 //-----------------------------------
1275 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex],
1277 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri64", [frameindex],
1280 def MEMri : Operand<i32> {
1281 let PrintMethod = "printMemOperand";
1282 let MIOperandInfo = (ops Int32Regs, i32imm);
1284 def MEMri64 : Operand<i64> {
1285 let PrintMethod = "printMemOperand";
1286 let MIOperandInfo = (ops Int64Regs, i64imm);
1289 def imem : Operand<iPTR> {
1290 let PrintMethod = "printOperand";
1293 def imemAny : Operand<iPTRAny> {
1294 let PrintMethod = "printOperand";
1297 def LdStCode : Operand<i32> {
1298 let PrintMethod = "printLdStCode";
1301 def SDTWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
1302 def Wrapper : SDNode<"NVPTXISD::Wrapper", SDTWrapper>;
1304 def MOV_ADDR : NVPTXInst<(outs Int32Regs:$dst), (ins imem:$a),
1305 "mov.u32 \t$dst, $a;",
1306 [(set Int32Regs:$dst, (Wrapper tglobaladdr:$a))]>;
1308 def MOV_ADDR64 : NVPTXInst<(outs Int64Regs:$dst), (ins imem:$a),
1309 "mov.u64 \t$dst, $a;",
1310 [(set Int64Regs:$dst, (Wrapper tglobaladdr:$a))]>;
1312 // copyPhysreg is hard-coded in NVPTXInstrInfo.cpp
1313 let IsSimpleMove=1 in {
1314 def IMOV1rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$sss),
1315 "mov.pred \t$dst, $sss;", []>;
1316 def IMOV16rr: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$sss),
1317 "mov.u16 \t$dst, $sss;", []>;
1318 def IMOV32rr: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$sss),
1319 "mov.u32 \t$dst, $sss;", []>;
1320 def IMOV64rr: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$sss),
1321 "mov.u64 \t$dst, $sss;", []>;
1323 def FMOV32rr: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
1324 "mov.f32 \t$dst, $src;", []>;
1325 def FMOV64rr: NVPTXInst<(outs Float64Regs:$dst), (ins Float64Regs:$src),
1326 "mov.f64 \t$dst, $src;", []>;
1328 def IMOV1ri: NVPTXInst<(outs Int1Regs:$dst), (ins i1imm:$src),
1329 "mov.pred \t$dst, $src;",
1330 [(set Int1Regs:$dst, imm:$src)]>;
1331 def IMOV16ri: NVPTXInst<(outs Int16Regs:$dst), (ins i16imm:$src),
1332 "mov.u16 \t$dst, $src;",
1333 [(set Int16Regs:$dst, imm:$src)]>;
1334 def IMOV32ri: NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$src),
1335 "mov.u32 \t$dst, $src;",
1336 [(set Int32Regs:$dst, imm:$src)]>;
1337 def IMOV64i: NVPTXInst<(outs Int64Regs:$dst), (ins i64imm:$src),
1338 "mov.u64 \t$dst, $src;",
1339 [(set Int64Regs:$dst, imm:$src)]>;
1341 def FMOV32ri: NVPTXInst<(outs Float32Regs:$dst), (ins f32imm:$src),
1342 "mov.f32 \t$dst, $src;",
1343 [(set Float32Regs:$dst, fpimm:$src)]>;
1344 def FMOV64ri: NVPTXInst<(outs Float64Regs:$dst), (ins f64imm:$src),
1345 "mov.f64 \t$dst, $src;",
1346 [(set Float64Regs:$dst, fpimm:$src)]>;
1348 def : Pat<(i32 (Wrapper texternalsym:$dst)), (IMOV32ri texternalsym:$dst)>;
1350 //---- Copy Frame Index ----
1351 def LEA_ADDRi : NVPTXInst<(outs Int32Regs:$dst), (ins MEMri:$addr),
1352 "add.u32 \t$dst, ${addr:add};",
1353 [(set Int32Regs:$dst, ADDRri:$addr)]>;
1354 def LEA_ADDRi64 : NVPTXInst<(outs Int64Regs:$dst), (ins MEMri64:$addr),
1355 "add.u64 \t$dst, ${addr:add};",
1356 [(set Int64Regs:$dst, ADDRri64:$addr)]>;
1358 //-----------------------------------
1359 // Comparison and Selection
1360 //-----------------------------------
1362 multiclass ISET_FORMAT<PatFrag OpNode, PatLeaf Mode,
1363 Instruction setp_16rr,
1364 Instruction setp_16ri,
1365 Instruction setp_16ir,
1366 Instruction setp_32rr,
1367 Instruction setp_32ri,
1368 Instruction setp_32ir,
1369 Instruction setp_64rr,
1370 Instruction setp_64ri,
1371 Instruction setp_64ir,
1372 Instruction set_16rr,
1373 Instruction set_16ri,
1374 Instruction set_16ir,
1375 Instruction set_32rr,
1376 Instruction set_32ri,
1377 Instruction set_32ir,
1378 Instruction set_64rr,
1379 Instruction set_64ri,
1380 Instruction set_64ir> {
1382 def : Pat<(i1 (OpNode Int16Regs:$a, Int16Regs:$b)),
1383 (setp_16rr Int16Regs:$a, Int16Regs:$b, Mode)>;
1384 def : Pat<(i1 (OpNode Int16Regs:$a, imm:$b)),
1385 (setp_16ri Int16Regs:$a, imm:$b, Mode)>;
1386 def : Pat<(i1 (OpNode imm:$a, Int16Regs:$b)),
1387 (setp_16ir imm:$a, Int16Regs:$b, Mode)>;
1389 def : Pat<(i1 (OpNode Int32Regs:$a, Int32Regs:$b)),
1390 (setp_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
1391 def : Pat<(i1 (OpNode Int32Regs:$a, imm:$b)),
1392 (setp_32ri Int32Regs:$a, imm:$b, Mode)>;
1393 def : Pat<(i1 (OpNode imm:$a, Int32Regs:$b)),
1394 (setp_32ir imm:$a, Int32Regs:$b, Mode)>;
1396 def : Pat<(i1 (OpNode Int64Regs:$a, Int64Regs:$b)),
1397 (setp_64rr Int64Regs:$a, Int64Regs:$b, Mode)>;
1398 def : Pat<(i1 (OpNode Int64Regs:$a, imm:$b)),
1399 (setp_64ri Int64Regs:$a, imm:$b, Mode)>;
1400 def : Pat<(i1 (OpNode imm:$a, Int64Regs:$b)),
1401 (setp_64ir imm:$a, Int64Regs:$b, Mode)>;
1404 def : Pat<(i32 (OpNode Int16Regs:$a, Int16Regs:$b)),
1405 (set_16rr Int16Regs:$a, Int16Regs:$b, Mode)>;
1406 def : Pat<(i32 (OpNode Int16Regs:$a, imm:$b)),
1407 (set_16ri Int16Regs:$a, imm:$b, Mode)>;
1408 def : Pat<(i32 (OpNode imm:$a, Int16Regs:$b)),
1409 (set_16ir imm:$a, Int16Regs:$b, Mode)>;
1411 def : Pat<(i32 (OpNode Int32Regs:$a, Int32Regs:$b)),
1412 (set_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
1413 def : Pat<(i32 (OpNode Int32Regs:$a, imm:$b)),
1414 (set_32ri Int32Regs:$a, imm:$b, Mode)>;
1415 def : Pat<(i32 (OpNode imm:$a, Int32Regs:$b)),
1416 (set_32ir imm:$a, Int32Regs:$b, Mode)>;
1418 def : Pat<(i32 (OpNode Int64Regs:$a, Int64Regs:$b)),
1419 (set_64rr Int64Regs:$a, Int64Regs:$b, Mode)>;
1420 def : Pat<(i32 (OpNode Int64Regs:$a, imm:$b)),
1421 (set_64ri Int64Regs:$a, imm:$b, Mode)>;
1422 def : Pat<(i32 (OpNode imm:$a, Int64Regs:$b)),
1423 (set_64ir imm:$a, Int64Regs:$b, Mode)>;
1426 multiclass ISET_FORMAT_SIGNED<PatFrag OpNode, PatLeaf Mode>
1427 : ISET_FORMAT<OpNode, Mode,
1428 SETP_s16rr, SETP_s16ri, SETP_s16ir,
1429 SETP_s32rr, SETP_s32ri, SETP_s32ir,
1430 SETP_s64rr, SETP_s64ri, SETP_s64ir,
1431 SET_s16rr, SET_s16ri, SET_s16ir,
1432 SET_s32rr, SET_s32ri, SET_s32ir,
1433 SET_s64rr, SET_s64ri, SET_s64ir> {
1434 // TableGen doesn't like empty multiclasses
1435 def : PatLeaf<(i32 0)>;
1438 multiclass ISET_FORMAT_UNSIGNED<PatFrag OpNode, PatLeaf Mode>
1439 : ISET_FORMAT<OpNode, Mode,
1440 SETP_u16rr, SETP_u16ri, SETP_u16ir,
1441 SETP_u32rr, SETP_u32ri, SETP_u32ir,
1442 SETP_u64rr, SETP_u64ri, SETP_u64ir,
1443 SET_u16rr, SET_u16ri, SET_u16ir,
1444 SET_u32rr, SET_u32ri, SET_u32ir,
1445 SET_u64rr, SET_u64ri, SET_u64ir> {
1446 // TableGen doesn't like empty multiclasses
1447 def : PatLeaf<(i32 0)>;
1450 defm : ISET_FORMAT_SIGNED<setgt, CmpGT>;
1451 defm : ISET_FORMAT_UNSIGNED<setugt, CmpGT>;
1452 defm : ISET_FORMAT_SIGNED<setlt, CmpLT>;
1453 defm : ISET_FORMAT_UNSIGNED<setult, CmpLT>;
1454 defm : ISET_FORMAT_SIGNED<setge, CmpGE>;
1455 defm : ISET_FORMAT_UNSIGNED<setuge, CmpGE>;
1456 defm : ISET_FORMAT_SIGNED<setle, CmpLE>;
1457 defm : ISET_FORMAT_UNSIGNED<setule, CmpLE>;
1458 defm : ISET_FORMAT_SIGNED<seteq, CmpEQ>;
1459 defm : ISET_FORMAT_UNSIGNED<setueq, CmpEQ>;
1460 defm : ISET_FORMAT_SIGNED<setne, CmpNE>;
1461 defm : ISET_FORMAT_UNSIGNED<setune, CmpNE>;
1464 def : Pat<(setne Int1Regs:$a, Int1Regs:$b),
1465 (XORb1rr Int1Regs:$a, Int1Regs:$b)>;
1466 def : Pat<(setune Int1Regs:$a, Int1Regs:$b),
1467 (XORb1rr Int1Regs:$a, Int1Regs:$b)>;
1469 def : Pat<(seteq Int1Regs:$a, Int1Regs:$b),
1470 (NOT1 (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1471 def : Pat<(setueq Int1Regs:$a, Int1Regs:$b),
1472 (NOT1 (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1474 // i1 compare -> i32
1475 def : Pat<(i32 (setne Int1Regs:$a, Int1Regs:$b)),
1476 (SELP_u32ii -1, 0, (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1477 def : Pat<(i32 (setne Int1Regs:$a, Int1Regs:$b)),
1478 (SELP_u32ii 0, -1, (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1482 multiclass FSET_FORMAT<PatFrag OpNode, PatLeaf Mode, PatLeaf ModeFTZ> {
1484 def : Pat<(i1 (OpNode Float32Regs:$a, Float32Regs:$b)),
1485 (SETP_f32rr Float32Regs:$a, Float32Regs:$b, ModeFTZ)>,
1486 Requires<[doF32FTZ]>;
1487 def : Pat<(i1 (OpNode Float32Regs:$a, Float32Regs:$b)),
1488 (SETP_f32rr Float32Regs:$a, Float32Regs:$b, Mode)>;
1489 def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
1490 (SETP_f32ri Float32Regs:$a, fpimm:$b, ModeFTZ)>,
1491 Requires<[doF32FTZ]>;
1492 def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
1493 (SETP_f32ri Float32Regs:$a, fpimm:$b, Mode)>;
1494 def : Pat<(i1 (OpNode fpimm:$a, Float32Regs:$b)),
1495 (SETP_f32ir fpimm:$a, Float32Regs:$b, ModeFTZ)>,
1496 Requires<[doF32FTZ]>;
1497 def : Pat<(i1 (OpNode fpimm:$a, Float32Regs:$b)),
1498 (SETP_f32ir fpimm:$a, Float32Regs:$b, Mode)>;
1501 def : Pat<(i1 (OpNode Float64Regs:$a, Float64Regs:$b)),
1502 (SETP_f64rr Float64Regs:$a, Float64Regs:$b, Mode)>;
1503 def : Pat<(i1 (OpNode Float64Regs:$a, fpimm:$b)),
1504 (SETP_f64ri Float64Regs:$a, fpimm:$b, Mode)>;
1505 def : Pat<(i1 (OpNode fpimm:$a, Float64Regs:$b)),
1506 (SETP_f64ir fpimm:$a, Float64Regs:$b, Mode)>;
1509 def : Pat<(i32 (OpNode Float32Regs:$a, Float32Regs:$b)),
1510 (SET_f32rr Float32Regs:$a, Float32Regs:$b, ModeFTZ)>,
1511 Requires<[doF32FTZ]>;
1512 def : Pat<(i32 (OpNode Float32Regs:$a, Float32Regs:$b)),
1513 (SET_f32rr Float32Regs:$a, Float32Regs:$b, Mode)>;
1514 def : Pat<(i32 (OpNode Float32Regs:$a, fpimm:$b)),
1515 (SET_f32ri Float32Regs:$a, fpimm:$b, ModeFTZ)>,
1516 Requires<[doF32FTZ]>;
1517 def : Pat<(i32 (OpNode Float32Regs:$a, fpimm:$b)),
1518 (SET_f32ri Float32Regs:$a, fpimm:$b, Mode)>;
1519 def : Pat<(i32 (OpNode fpimm:$a, Float32Regs:$b)),
1520 (SET_f32ir fpimm:$a, Float32Regs:$b, ModeFTZ)>,
1521 Requires<[doF32FTZ]>;
1522 def : Pat<(i32 (OpNode fpimm:$a, Float32Regs:$b)),
1523 (SET_f32ir fpimm:$a, Float32Regs:$b, Mode)>;
1526 def : Pat<(i32 (OpNode Float64Regs:$a, Float64Regs:$b)),
1527 (SET_f64rr Float64Regs:$a, Float64Regs:$b, Mode)>;
1528 def : Pat<(i32 (OpNode Float64Regs:$a, fpimm:$b)),
1529 (SET_f64ri Float64Regs:$a, fpimm:$b, Mode)>;
1530 def : Pat<(i32 (OpNode fpimm:$a, Float64Regs:$b)),
1531 (SET_f64ir fpimm:$a, Float64Regs:$b, Mode)>;
1534 defm FSetGT : FSET_FORMAT<setogt, CmpGT, CmpGT_FTZ>;
1535 defm FSetLT : FSET_FORMAT<setolt, CmpLT, CmpLT_FTZ>;
1536 defm FSetGE : FSET_FORMAT<setoge, CmpGE, CmpGE_FTZ>;
1537 defm FSetLE : FSET_FORMAT<setole, CmpLE, CmpLE_FTZ>;
1538 defm FSetEQ : FSET_FORMAT<setoeq, CmpEQ, CmpEQ_FTZ>;
1539 defm FSetNE : FSET_FORMAT<setone, CmpNE, CmpNE_FTZ>;
1541 defm FSetUGT : FSET_FORMAT<setugt, CmpGTU, CmpGTU_FTZ>;
1542 defm FSetULT : FSET_FORMAT<setult, CmpLTU, CmpLTU_FTZ>;
1543 defm FSetUGE : FSET_FORMAT<setuge, CmpGEU, CmpGEU_FTZ>;
1544 defm FSetULE : FSET_FORMAT<setule, CmpLEU, CmpLEU_FTZ>;
1545 defm FSetUEQ : FSET_FORMAT<setueq, CmpEQU, CmpEQU_FTZ>;
1546 defm FSetUNE : FSET_FORMAT<setune, CmpNEU, CmpNEU_FTZ>;
1548 defm FSetNUM : FSET_FORMAT<seto, CmpNUM, CmpNUM_FTZ>;
1549 defm FSetNAN : FSET_FORMAT<setuo, CmpNAN, CmpNAN_FTZ>;
1551 //def ld_param : SDNode<"NVPTXISD::LOAD_PARAM", SDTLoad,
1552 // [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1554 def SDTDeclareParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
1556 def SDTDeclareScalarParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>,
1557 SDTCisInt<1>, SDTCisInt<2>]>;
1558 def SDTLoadParamProfile : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
1559 def SDTLoadParamV2Profile : SDTypeProfile<2, 2, [SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisInt<3>]>;
1560 def SDTLoadParamV4Profile : SDTypeProfile<4, 2, [SDTCisInt<4>, SDTCisInt<5>]>;
1561 def SDTPrintCallProfile : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
1562 def SDTPrintCallUniProfile : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
1563 def SDTStoreParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>]>;
1564 def SDTStoreParamV2Profile : SDTypeProfile<0, 4, [SDTCisInt<0>, SDTCisInt<1>]>;
1565 def SDTStoreParamV4Profile : SDTypeProfile<0, 6, [SDTCisInt<0>, SDTCisInt<1>]>;
1566 def SDTStoreParam32Profile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>]>;
1567 def SDTCallArgProfile : SDTypeProfile<0, 2, [SDTCisInt<0>]>;
1568 def SDTCallArgMarkProfile : SDTypeProfile<0, 0, []>;
1569 def SDTCallVoidProfile : SDTypeProfile<0, 1, []>;
1570 def SDTCallValProfile : SDTypeProfile<1, 0, []>;
1571 def SDTMoveParamProfile : SDTypeProfile<1, 1, []>;
1572 def SDTStoreRetvalProfile : SDTypeProfile<0, 2, [SDTCisInt<0>]>;
1573 def SDTStoreRetvalV2Profile : SDTypeProfile<0, 3, [SDTCisInt<0>]>;
1574 def SDTStoreRetvalV4Profile : SDTypeProfile<0, 5, [SDTCisInt<0>]>;
1575 def SDTPseudoUseParamProfile : SDTypeProfile<0, 1, []>;
1577 def DeclareParam : SDNode<"NVPTXISD::DeclareParam", SDTDeclareParamProfile,
1578 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1579 def DeclareScalarParam : SDNode<"NVPTXISD::DeclareScalarParam",
1580 SDTDeclareScalarParamProfile,
1581 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1582 def DeclareRetParam : SDNode<"NVPTXISD::DeclareRetParam",
1583 SDTDeclareParamProfile,
1584 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1585 def DeclareRet : SDNode<"NVPTXISD::DeclareRet", SDTDeclareScalarParamProfile,
1586 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1587 def LoadParam : SDNode<"NVPTXISD::LoadParam", SDTLoadParamProfile,
1588 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1589 def LoadParamV2 : SDNode<"NVPTXISD::LoadParamV2", SDTLoadParamV2Profile,
1590 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1591 def LoadParamV4 : SDNode<"NVPTXISD::LoadParamV4", SDTLoadParamV4Profile,
1592 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1593 def PrintCall : SDNode<"NVPTXISD::PrintCall", SDTPrintCallProfile,
1594 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1595 def PrintCallUni : SDNode<"NVPTXISD::PrintCallUni", SDTPrintCallUniProfile,
1596 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1597 def StoreParam : SDNode<"NVPTXISD::StoreParam", SDTStoreParamProfile,
1598 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1599 def StoreParamV2 : SDNode<"NVPTXISD::StoreParamV2", SDTStoreParamV2Profile,
1600 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1601 def StoreParamV4 : SDNode<"NVPTXISD::StoreParamV4", SDTStoreParamV4Profile,
1602 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1603 def StoreParamU32 : SDNode<"NVPTXISD::StoreParamU32", SDTStoreParam32Profile,
1604 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1605 def StoreParamS32 : SDNode<"NVPTXISD::StoreParamS32", SDTStoreParam32Profile,
1606 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1607 def CallArgBegin : SDNode<"NVPTXISD::CallArgBegin", SDTCallArgMarkProfile,
1608 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1609 def CallArg : SDNode<"NVPTXISD::CallArg", SDTCallArgProfile,
1610 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1611 def LastCallArg : SDNode<"NVPTXISD::LastCallArg", SDTCallArgProfile,
1612 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1613 def CallArgEnd : SDNode<"NVPTXISD::CallArgEnd", SDTCallVoidProfile,
1614 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1615 def CallVoid : SDNode<"NVPTXISD::CallVoid", SDTCallVoidProfile,
1616 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1617 def Prototype : SDNode<"NVPTXISD::Prototype", SDTCallVoidProfile,
1618 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1619 def CallVal : SDNode<"NVPTXISD::CallVal", SDTCallValProfile,
1620 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1621 def MoveParam : SDNode<"NVPTXISD::MoveParam", SDTMoveParamProfile,
1623 def StoreRetval : SDNode<"NVPTXISD::StoreRetval", SDTStoreRetvalProfile,
1624 [SDNPHasChain, SDNPSideEffect]>;
1625 def StoreRetvalV2 : SDNode<"NVPTXISD::StoreRetvalV2", SDTStoreRetvalV2Profile,
1626 [SDNPHasChain, SDNPSideEffect]>;
1627 def StoreRetvalV4 : SDNode<"NVPTXISD::StoreRetvalV4", SDTStoreRetvalV4Profile,
1628 [SDNPHasChain, SDNPSideEffect]>;
1629 def PseudoUseParam : SDNode<"NVPTXISD::PseudoUseParam",
1630 SDTPseudoUseParamProfile,
1631 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1632 def RETURNNode : SDNode<"NVPTXISD::RETURN", SDTCallArgMarkProfile,
1633 [SDNPHasChain, SDNPSideEffect]>;
1635 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1636 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1637 !strconcat(!strconcat("ld.param", opstr),
1638 "\t$dst, [retval0+$b];"),
1641 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1642 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1643 !strconcat(!strconcat("mov", opstr),
1644 "\t$dst, retval$b;"),
1645 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
1647 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1648 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1649 !strconcat(!strconcat("ld.param.v2", opstr),
1650 "\t{{$dst, $dst2}}, [retval0+$b];"), []>;
1652 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1653 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1656 !strconcat(!strconcat("ld.param.v4", opstr),
1657 "\t{{$dst, $dst2, $dst3, $dst4}}, [retval0+$b];"), []>;
1659 class StoreParamInst<NVPTXRegClass regclass, string opstr> :
1660 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a, i32imm:$b),
1661 !strconcat(!strconcat("st.param", opstr),
1662 "\t[param$a+$b], $val;"),
1665 class StoreParamV2Inst<NVPTXRegClass regclass, string opstr> :
1666 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2,
1667 i32imm:$a, i32imm:$b),
1668 !strconcat(!strconcat("st.param.v2", opstr),
1669 "\t[param$a+$b], {{$val, $val2}};"),
1672 class StoreParamV4Inst<NVPTXRegClass regclass, string opstr> :
1673 NVPTXInst<(outs), (ins regclass:$val, regclass:$val1, regclass:$val2,
1674 regclass:$val3, i32imm:$a, i32imm:$b),
1675 !strconcat(!strconcat("st.param.v4", opstr),
1676 "\t[param$a+$b], {{$val, $val2, $val3, $val4}};"),
1679 class StoreRetvalInst<NVPTXRegClass regclass, string opstr> :
1680 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a),
1681 !strconcat(!strconcat("st.param", opstr),
1682 "\t[func_retval0+$a], $val;"),
1685 class StoreRetvalV2Inst<NVPTXRegClass regclass, string opstr> :
1686 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2, i32imm:$a),
1687 !strconcat(!strconcat("st.param.v2", opstr),
1688 "\t[func_retval0+$a], {{$val, $val2}};"),
1691 class StoreRetvalV4Inst<NVPTXRegClass regclass, string opstr> :
1693 (ins regclass:$val, regclass:$val2, regclass:$val3,
1694 regclass:$val4, i32imm:$a),
1695 !strconcat(!strconcat("st.param.v4", opstr),
1696 "\t[func_retval0+$a], {{$val, $val2, $val3, $val4}};"),
1699 def PrintCallRetInst1 : NVPTXInst<(outs), (ins),
1701 [(PrintCall (i32 1))]>;
1702 def PrintCallRetInst2 : NVPTXInst<(outs), (ins),
1703 "call (retval0, retval1), ",
1704 [(PrintCall (i32 2))]>;
1705 def PrintCallRetInst3 : NVPTXInst<(outs), (ins),
1706 "call (retval0, retval1, retval2), ",
1707 [(PrintCall (i32 3))]>;
1708 def PrintCallRetInst4 : NVPTXInst<(outs), (ins),
1709 "call (retval0, retval1, retval2, retval3), ",
1710 [(PrintCall (i32 4))]>;
1711 def PrintCallRetInst5 : NVPTXInst<(outs), (ins),
1712 "call (retval0, retval1, retval2, retval3, retval4), ",
1713 [(PrintCall (i32 5))]>;
1714 def PrintCallRetInst6 : NVPTXInst<(outs), (ins),
1715 "call (retval0, retval1, retval2, retval3, retval4, retval5), ",
1716 [(PrintCall (i32 6))]>;
1717 def PrintCallRetInst7 : NVPTXInst<(outs), (ins),
1718 "call (retval0, retval1, retval2, retval3, retval4, retval5, retval6), ",
1719 [(PrintCall (i32 7))]>;
1720 def PrintCallRetInst8 : NVPTXInst<(outs), (ins),
1721 !strconcat("call (retval0, retval1, retval2, retval3, retval4",
1722 ", retval5, retval6, retval7), "),
1723 [(PrintCall (i32 8))]>;
1725 def PrintCallNoRetInst : NVPTXInst<(outs), (ins), "call ",
1726 [(PrintCall (i32 0))]>;
1728 def PrintCallUniRetInst1 : NVPTXInst<(outs), (ins),
1729 "call.uni (retval0), ",
1730 [(PrintCallUni (i32 1))]>;
1731 def PrintCallUniRetInst2 : NVPTXInst<(outs), (ins),
1732 "call.uni (retval0, retval1), ",
1733 [(PrintCallUni (i32 2))]>;
1734 def PrintCallUniRetInst3 : NVPTXInst<(outs), (ins),
1735 "call.uni (retval0, retval1, retval2), ",
1736 [(PrintCallUni (i32 3))]>;
1737 def PrintCallUniRetInst4 : NVPTXInst<(outs), (ins),
1738 "call.uni (retval0, retval1, retval2, retval3), ",
1739 [(PrintCallUni (i32 4))]>;
1740 def PrintCallUniRetInst5 : NVPTXInst<(outs), (ins),
1741 "call.uni (retval0, retval1, retval2, retval3, retval4), ",
1742 [(PrintCallUni (i32 5))]>;
1743 def PrintCallUniRetInst6 : NVPTXInst<(outs), (ins),
1744 "call.uni (retval0, retval1, retval2, retval3, retval4, retval5), ",
1745 [(PrintCallUni (i32 6))]>;
1746 def PrintCallUniRetInst7 : NVPTXInst<(outs), (ins),
1747 "call.uni (retval0, retval1, retval2, retval3, retval4, retval5, retval6), ",
1748 [(PrintCallUni (i32 7))]>;
1749 def PrintCallUniRetInst8 : NVPTXInst<(outs), (ins),
1750 !strconcat("call.uni (retval0, retval1, retval2, retval3, retval4",
1751 ", retval5, retval6, retval7), "),
1752 [(PrintCallUni (i32 8))]>;
1754 def PrintCallUniNoRetInst : NVPTXInst<(outs), (ins), "call.uni ",
1755 [(PrintCallUni (i32 0))]>;
1757 def LoadParamMemI64 : LoadParamMemInst<Int64Regs, ".b64">;
1758 def LoadParamMemI32 : LoadParamMemInst<Int32Regs, ".b32">;
1759 def LoadParamMemI16 : LoadParamMemInst<Int16Regs, ".b16">;
1760 def LoadParamMemI8 : LoadParamMemInst<Int16Regs, ".b8">;
1761 def LoadParamMemV2I64 : LoadParamV2MemInst<Int64Regs, ".b64">;
1762 def LoadParamMemV2I32 : LoadParamV2MemInst<Int32Regs, ".b32">;
1763 def LoadParamMemV2I16 : LoadParamV2MemInst<Int16Regs, ".b16">;
1764 def LoadParamMemV2I8 : LoadParamV2MemInst<Int16Regs, ".b8">;
1765 def LoadParamMemV4I32 : LoadParamV4MemInst<Int32Regs, ".b32">;
1766 def LoadParamMemV4I16 : LoadParamV4MemInst<Int16Regs, ".b16">;
1767 def LoadParamMemV4I8 : LoadParamV4MemInst<Int16Regs, ".b8">;
1768 def LoadParamMemF32 : LoadParamMemInst<Float32Regs, ".f32">;
1769 def LoadParamMemF64 : LoadParamMemInst<Float64Regs, ".f64">;
1770 def LoadParamMemV2F32 : LoadParamV2MemInst<Float32Regs, ".f32">;
1771 def LoadParamMemV2F64 : LoadParamV2MemInst<Float64Regs, ".f64">;
1772 def LoadParamMemV4F32 : LoadParamV4MemInst<Float32Regs, ".f32">;
1774 def StoreParamI64 : StoreParamInst<Int64Regs, ".b64">;
1775 def StoreParamI32 : StoreParamInst<Int32Regs, ".b32">;
1777 def StoreParamI16 : StoreParamInst<Int16Regs, ".b16">;
1778 def StoreParamI8 : StoreParamInst<Int16Regs, ".b8">;
1779 def StoreParamV2I64 : StoreParamV2Inst<Int64Regs, ".b64">;
1780 def StoreParamV2I32 : StoreParamV2Inst<Int32Regs, ".b32">;
1781 def StoreParamV2I16 : StoreParamV2Inst<Int16Regs, ".b16">;
1782 def StoreParamV2I8 : StoreParamV2Inst<Int16Regs, ".b8">;
1784 // FIXME: StoreParamV4Inst crashes llvm-tblgen :(
1785 //def StoreParamV4I32 : StoreParamV4Inst<Int32Regs, ".b32">;
1786 def StoreParamV4I32 : NVPTXInst<(outs), (ins Int32Regs:$val, Int32Regs:$val2,
1787 Int32Regs:$val3, Int32Regs:$val4,
1788 i32imm:$a, i32imm:$b),
1789 "st.param.b32\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1792 def StoreParamV4I16 : NVPTXInst<(outs), (ins Int16Regs:$val, Int16Regs:$val2,
1793 Int16Regs:$val3, Int16Regs:$val4,
1794 i32imm:$a, i32imm:$b),
1795 "st.param.v4.b16\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1798 def StoreParamV4I8 : NVPTXInst<(outs), (ins Int16Regs:$val, Int16Regs:$val2,
1799 Int16Regs:$val3, Int16Regs:$val4,
1800 i32imm:$a, i32imm:$b),
1801 "st.param.v4.b8\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1804 def StoreParamF32 : StoreParamInst<Float32Regs, ".f32">;
1805 def StoreParamF64 : StoreParamInst<Float64Regs, ".f64">;
1806 def StoreParamV2F32 : StoreParamV2Inst<Float32Regs, ".f32">;
1807 def StoreParamV2F64 : StoreParamV2Inst<Float64Regs, ".f64">;
1808 // FIXME: StoreParamV4Inst crashes llvm-tblgen :(
1809 //def StoreParamV4F32 : StoreParamV4Inst<Float32Regs, ".f32">;
1810 def StoreParamV4F32 : NVPTXInst<(outs),
1811 (ins Float32Regs:$val, Float32Regs:$val2,
1812 Float32Regs:$val3, Float32Regs:$val4,
1813 i32imm:$a, i32imm:$b),
1814 "st.param.v4.f32\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1818 def StoreRetvalI64 : StoreRetvalInst<Int64Regs, ".b64">;
1819 def StoreRetvalI32 : StoreRetvalInst<Int32Regs, ".b32">;
1820 def StoreRetvalI16 : StoreRetvalInst<Int16Regs, ".b16">;
1821 def StoreRetvalI8 : StoreRetvalInst<Int16Regs, ".b8">;
1822 def StoreRetvalV2I64 : StoreRetvalV2Inst<Int64Regs, ".b64">;
1823 def StoreRetvalV2I32 : StoreRetvalV2Inst<Int32Regs, ".b32">;
1824 def StoreRetvalV2I16 : StoreRetvalV2Inst<Int16Regs, ".b16">;
1825 def StoreRetvalV2I8 : StoreRetvalV2Inst<Int16Regs, ".b8">;
1826 def StoreRetvalV4I32 : StoreRetvalV4Inst<Int32Regs, ".b32">;
1827 def StoreRetvalV4I16 : StoreRetvalV4Inst<Int16Regs, ".b16">;
1828 def StoreRetvalV4I8 : StoreRetvalV4Inst<Int16Regs, ".b8">;
1830 def StoreRetvalF64 : StoreRetvalInst<Float64Regs, ".f64">;
1831 def StoreRetvalF32 : StoreRetvalInst<Float32Regs, ".f32">;
1832 def StoreRetvalV2F64 : StoreRetvalV2Inst<Float64Regs, ".f64">;
1833 def StoreRetvalV2F32 : StoreRetvalV2Inst<Float32Regs, ".f32">;
1834 def StoreRetvalV4F32 : StoreRetvalV4Inst<Float32Regs, ".f32">;
1836 def CallArgBeginInst : NVPTXInst<(outs), (ins), "(", [(CallArgBegin)]>;
1837 def CallArgEndInst1 : NVPTXInst<(outs), (ins), ");", [(CallArgEnd (i32 1))]>;
1838 def CallArgEndInst0 : NVPTXInst<(outs), (ins), ")", [(CallArgEnd (i32 0))]>;
1839 def RETURNInst : NVPTXInst<(outs), (ins), "ret;", [(RETURNNode)]>;
1841 class CallArgInst<NVPTXRegClass regclass> :
1842 NVPTXInst<(outs), (ins regclass:$a), "$a, ",
1843 [(CallArg (i32 0), regclass:$a)]>;
1845 class LastCallArgInst<NVPTXRegClass regclass> :
1846 NVPTXInst<(outs), (ins regclass:$a), "$a",
1847 [(LastCallArg (i32 0), regclass:$a)]>;
1849 def CallArgI64 : CallArgInst<Int64Regs>;
1850 def CallArgI32 : CallArgInst<Int32Regs>;
1851 def CallArgI16 : CallArgInst<Int16Regs>;
1853 def CallArgF64 : CallArgInst<Float64Regs>;
1854 def CallArgF32 : CallArgInst<Float32Regs>;
1856 def LastCallArgI64 : LastCallArgInst<Int64Regs>;
1857 def LastCallArgI32 : LastCallArgInst<Int32Regs>;
1858 def LastCallArgI16 : LastCallArgInst<Int16Regs>;
1860 def LastCallArgF64 : LastCallArgInst<Float64Regs>;
1861 def LastCallArgF32 : LastCallArgInst<Float32Regs>;
1863 def CallArgI32imm : NVPTXInst<(outs), (ins i32imm:$a), "$a, ",
1864 [(CallArg (i32 0), (i32 imm:$a))]>;
1865 def LastCallArgI32imm : NVPTXInst<(outs), (ins i32imm:$a), "$a",
1866 [(LastCallArg (i32 0), (i32 imm:$a))]>;
1868 def CallArgParam : NVPTXInst<(outs), (ins i32imm:$a), "param$a, ",
1869 [(CallArg (i32 1), (i32 imm:$a))]>;
1870 def LastCallArgParam : NVPTXInst<(outs), (ins i32imm:$a), "param$a",
1871 [(LastCallArg (i32 1), (i32 imm:$a))]>;
1873 def CallVoidInst : NVPTXInst<(outs), (ins imem:$addr),
1875 [(CallVoid (Wrapper tglobaladdr:$addr))]>;
1876 def CallVoidInstReg : NVPTXInst<(outs), (ins Int32Regs:$addr),
1878 [(CallVoid Int32Regs:$addr)]>;
1879 def CallVoidInstReg64 : NVPTXInst<(outs), (ins Int64Regs:$addr),
1881 [(CallVoid Int64Regs:$addr)]>;
1882 def PrototypeInst : NVPTXInst<(outs), (ins i32imm:$val),
1883 ", prototype_$val;",
1884 [(Prototype (i32 imm:$val))]>;
1886 def DeclareRetMemInst : NVPTXInst<(outs),
1887 (ins i32imm:$align, i32imm:$size, i32imm:$num),
1888 ".param .align $align .b8 retval$num[$size];",
1889 [(DeclareRetParam (i32 imm:$align), (i32 imm:$size), (i32 imm:$num))]>;
1890 def DeclareRetScalarInst : NVPTXInst<(outs), (ins i32imm:$size, i32imm:$num),
1891 ".param .b$size retval$num;",
1892 [(DeclareRet (i32 1), (i32 imm:$size), (i32 imm:$num))]>;
1893 def DeclareRetRegInst : NVPTXInst<(outs), (ins i32imm:$size, i32imm:$num),
1894 ".reg .b$size retval$num;",
1895 [(DeclareRet (i32 2), (i32 imm:$size), (i32 imm:$num))]>;
1897 def DeclareParamInst : NVPTXInst<(outs),
1898 (ins i32imm:$align, i32imm:$a, i32imm:$size),
1899 ".param .align $align .b8 param$a[$size];",
1900 [(DeclareParam (i32 imm:$align), (i32 imm:$a), (i32 imm:$size))]>;
1901 def DeclareScalarParamInst : NVPTXInst<(outs), (ins i32imm:$a, i32imm:$size),
1902 ".param .b$size param$a;",
1903 [(DeclareScalarParam (i32 imm:$a), (i32 imm:$size), (i32 0))]>;
1904 def DeclareScalarRegInst : NVPTXInst<(outs), (ins i32imm:$a, i32imm:$size),
1905 ".reg .b$size param$a;",
1906 [(DeclareScalarParam (i32 imm:$a), (i32 imm:$size), (i32 1))]>;
1908 class MoveParamInst<NVPTXRegClass regclass, string asmstr> :
1909 NVPTXInst<(outs regclass:$dst), (ins regclass:$src),
1910 !strconcat(!strconcat("mov", asmstr), "\t$dst, $src;"),
1911 [(set regclass:$dst, (MoveParam regclass:$src))]>;
1913 def MoveParamI64 : MoveParamInst<Int64Regs, ".b64">;
1914 def MoveParamI32 : MoveParamInst<Int32Regs, ".b32">;
1915 def MoveParamI16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
1916 "cvt.u16.u32\t$dst, $src;",
1917 [(set Int16Regs:$dst, (MoveParam Int16Regs:$src))]>;
1918 def MoveParamF64 : MoveParamInst<Float64Regs, ".f64">;
1919 def MoveParamF32 : MoveParamInst<Float32Regs, ".f32">;
1921 class PseudoUseParamInst<NVPTXRegClass regclass> :
1922 NVPTXInst<(outs), (ins regclass:$src),
1923 "// Pseudo use of $src",
1924 [(PseudoUseParam regclass:$src)]>;
1926 def PseudoUseParamI64 : PseudoUseParamInst<Int64Regs>;
1927 def PseudoUseParamI32 : PseudoUseParamInst<Int32Regs>;
1928 def PseudoUseParamI16 : PseudoUseParamInst<Int16Regs>;
1929 def PseudoUseParamF64 : PseudoUseParamInst<Float64Regs>;
1930 def PseudoUseParamF32 : PseudoUseParamInst<Float32Regs>;
1934 // Load / Store Handling
1936 multiclass LD<NVPTXRegClass regclass> {
1937 def _avar : NVPTXInst<(outs regclass:$dst),
1938 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1939 i32imm:$fromWidth, imem:$addr),
1940 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1941 "$fromWidth \t$dst, [$addr];"), []>;
1942 def _areg : NVPTXInst<(outs regclass:$dst),
1943 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1944 i32imm:$fromWidth, Int32Regs:$addr),
1945 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1946 "$fromWidth \t$dst, [$addr];"), []>;
1947 def _areg_64 : NVPTXInst<(outs regclass:$dst),
1948 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1949 i32imm:$fromWidth, Int64Regs:$addr),
1950 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$fromWidth",
1951 " \t$dst, [$addr];"), []>;
1952 def _ari : NVPTXInst<(outs regclass:$dst),
1953 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1954 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
1955 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1956 "$fromWidth \t$dst, [$addr+$offset];"), []>;
1957 def _ari_64 : NVPTXInst<(outs regclass:$dst),
1958 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1959 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
1960 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$fromWidth",
1961 " \t$dst, [$addr+$offset];"), []>;
1962 def _asi : NVPTXInst<(outs regclass:$dst),
1963 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1964 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
1965 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1966 "$fromWidth \t$dst, [$addr+$offset];"), []>;
1969 let mayLoad=1, neverHasSideEffects=1 in {
1970 defm LD_i8 : LD<Int16Regs>;
1971 defm LD_i16 : LD<Int16Regs>;
1972 defm LD_i32 : LD<Int32Regs>;
1973 defm LD_i64 : LD<Int64Regs>;
1974 defm LD_f32 : LD<Float32Regs>;
1975 defm LD_f64 : LD<Float64Regs>;
1978 multiclass ST<NVPTXRegClass regclass> {
1979 def _avar : NVPTXInst<(outs),
1980 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1981 LdStCode:$Sign, i32imm:$toWidth, imem:$addr),
1982 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
1983 " \t[$addr], $src;"), []>;
1984 def _areg : NVPTXInst<(outs),
1985 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1986 LdStCode:$Sign, i32imm:$toWidth, Int32Regs:$addr),
1987 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
1988 " \t[$addr], $src;"), []>;
1989 def _areg_64 : NVPTXInst<(outs),
1990 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1991 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr),
1992 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth ",
1993 "\t[$addr], $src;"), []>;
1994 def _ari : NVPTXInst<(outs),
1995 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1996 LdStCode:$Sign, i32imm:$toWidth, Int32Regs:$addr, i32imm:$offset),
1997 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
1998 " \t[$addr+$offset], $src;"), []>;
1999 def _ari_64 : NVPTXInst<(outs),
2000 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2001 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr, i32imm:$offset),
2002 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth ",
2003 "\t[$addr+$offset], $src;"), []>;
2004 def _asi : NVPTXInst<(outs),
2005 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2006 LdStCode:$Sign, i32imm:$toWidth, imem:$addr, i32imm:$offset),
2007 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2008 " \t[$addr+$offset], $src;"), []>;
2011 let mayStore=1, neverHasSideEffects=1 in {
2012 defm ST_i8 : ST<Int16Regs>;
2013 defm ST_i16 : ST<Int16Regs>;
2014 defm ST_i32 : ST<Int32Regs>;
2015 defm ST_i64 : ST<Int64Regs>;
2016 defm ST_f32 : ST<Float32Regs>;
2017 defm ST_f64 : ST<Float64Regs>;
2020 // The following is used only in and after vector elementizations.
2021 // Vector elementization happens at the machine instruction level, so the
2022 // following instruction
2023 // never appears in the DAG.
2024 multiclass LD_VEC<NVPTXRegClass regclass> {
2025 def _v2_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2026 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2027 i32imm:$fromWidth, imem:$addr),
2028 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2029 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2030 def _v2_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2031 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2032 i32imm:$fromWidth, Int32Regs:$addr),
2033 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2034 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2035 def _v2_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2036 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2037 i32imm:$fromWidth, Int64Regs:$addr),
2038 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2039 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2040 def _v2_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2041 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2042 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2043 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2044 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2045 def _v2_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2046 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2047 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2048 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2049 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2050 def _v2_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2051 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2052 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2053 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2054 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2055 def _v4_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2056 regclass:$dst3, regclass:$dst4),
2057 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2058 i32imm:$fromWidth, imem:$addr),
2059 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2060 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2061 def _v4_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2063 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2064 i32imm:$fromWidth, Int32Regs:$addr),
2065 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2066 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2067 def _v4_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2068 regclass:$dst3, regclass:$dst4),
2069 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2070 i32imm:$fromWidth, Int64Regs:$addr),
2071 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2072 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2073 def _v4_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2075 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2076 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2077 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2078 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2080 def _v4_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2081 regclass:$dst3, regclass:$dst4),
2082 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2083 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2084 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2085 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2087 def _v4_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2089 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2090 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2091 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2092 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2095 let mayLoad=1, neverHasSideEffects=1 in {
2096 defm LDV_i8 : LD_VEC<Int16Regs>;
2097 defm LDV_i16 : LD_VEC<Int16Regs>;
2098 defm LDV_i32 : LD_VEC<Int32Regs>;
2099 defm LDV_i64 : LD_VEC<Int64Regs>;
2100 defm LDV_f32 : LD_VEC<Float32Regs>;
2101 defm LDV_f64 : LD_VEC<Float64Regs>;
2104 multiclass ST_VEC<NVPTXRegClass regclass> {
2105 def _v2_avar : NVPTXInst<(outs),
2106 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2107 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, imem:$addr),
2108 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2109 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2110 def _v2_areg : NVPTXInst<(outs),
2111 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2112 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int32Regs:$addr),
2113 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2114 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2115 def _v2_areg_64 : NVPTXInst<(outs),
2116 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2117 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int64Regs:$addr),
2118 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2119 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2120 def _v2_ari : NVPTXInst<(outs),
2121 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2122 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int32Regs:$addr,
2124 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2125 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2126 def _v2_ari_64 : NVPTXInst<(outs),
2127 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2128 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int64Regs:$addr,
2130 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2131 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2132 def _v2_asi : NVPTXInst<(outs),
2133 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2134 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, imem:$addr,
2136 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2137 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2138 def _v4_avar : NVPTXInst<(outs),
2139 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2140 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2141 i32imm:$fromWidth, imem:$addr),
2142 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2143 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2144 def _v4_areg : NVPTXInst<(outs),
2145 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2146 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2147 i32imm:$fromWidth, Int32Regs:$addr),
2148 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2149 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2150 def _v4_areg_64 : NVPTXInst<(outs),
2151 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2152 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2153 i32imm:$fromWidth, Int64Regs:$addr),
2154 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2155 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2156 def _v4_ari : NVPTXInst<(outs),
2157 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2158 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2159 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2160 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2161 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2163 def _v4_ari_64 : NVPTXInst<(outs),
2164 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2165 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2166 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2167 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2168 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2170 def _v4_asi : NVPTXInst<(outs),
2171 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2172 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2173 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2174 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2175 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2178 let mayStore=1, neverHasSideEffects=1 in {
2179 defm STV_i8 : ST_VEC<Int16Regs>;
2180 defm STV_i16 : ST_VEC<Int16Regs>;
2181 defm STV_i32 : ST_VEC<Int32Regs>;
2182 defm STV_i64 : ST_VEC<Int64Regs>;
2183 defm STV_f32 : ST_VEC<Float32Regs>;
2184 defm STV_f64 : ST_VEC<Float64Regs>;
2188 //---- Conversion ----
2190 // NOTE: pred->fp are currently sub-optimal due to an issue in TableGen where
2191 // we cannot specify floating-point literals in isel patterns. Therefore, we
2192 // use an integer selp to select either 1 or 0 and then cvt to floating-point.
2195 def : Pat<(f32 (sint_to_fp Int1Regs:$a)),
2196 (CVT_f32_s32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2197 def : Pat<(f32 (sint_to_fp Int16Regs:$a)),
2198 (CVT_f32_s16 Int16Regs:$a, CvtRN)>;
2199 def : Pat<(f32 (sint_to_fp Int32Regs:$a)),
2200 (CVT_f32_s32 Int32Regs:$a, CvtRN)>;
2201 def : Pat<(f32 (sint_to_fp Int64Regs:$a)),
2202 (CVT_f32_s64 Int64Regs:$a, CvtRN)>;
2205 def : Pat<(f32 (uint_to_fp Int1Regs:$a)),
2206 (CVT_f32_u32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2207 def : Pat<(f32 (uint_to_fp Int16Regs:$a)),
2208 (CVT_f32_u16 Int16Regs:$a, CvtRN)>;
2209 def : Pat<(f32 (uint_to_fp Int32Regs:$a)),
2210 (CVT_f32_u32 Int32Regs:$a, CvtRN)>;
2211 def : Pat<(f32 (uint_to_fp Int64Regs:$a)),
2212 (CVT_f32_u64 Int64Regs:$a, CvtRN)>;
2215 def : Pat<(f64 (sint_to_fp Int1Regs:$a)),
2216 (CVT_f64_s32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2217 def : Pat<(f64 (sint_to_fp Int16Regs:$a)),
2218 (CVT_f64_s16 Int16Regs:$a, CvtRN)>;
2219 def : Pat<(f64 (sint_to_fp Int32Regs:$a)),
2220 (CVT_f64_s32 Int32Regs:$a, CvtRN)>;
2221 def : Pat<(f64 (sint_to_fp Int64Regs:$a)),
2222 (CVT_f64_s64 Int64Regs:$a, CvtRN)>;
2225 def : Pat<(f64 (uint_to_fp Int1Regs:$a)),
2226 (CVT_f64_u32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2227 def : Pat<(f64 (uint_to_fp Int16Regs:$a)),
2228 (CVT_f64_u16 Int16Regs:$a, CvtRN)>;
2229 def : Pat<(f64 (uint_to_fp Int32Regs:$a)),
2230 (CVT_f64_u32 Int32Regs:$a, CvtRN)>;
2231 def : Pat<(f64 (uint_to_fp Int64Regs:$a)),
2232 (CVT_f64_u64 Int64Regs:$a, CvtRN)>;
2236 def : Pat<(i16 (fp_to_sint Float32Regs:$a)),
2237 (CVT_s16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2238 def : Pat<(i16 (fp_to_sint Float32Regs:$a)),
2239 (CVT_s16_f32 Float32Regs:$a, CvtRZI)>;
2240 def : Pat<(i32 (fp_to_sint Float32Regs:$a)),
2241 (CVT_s32_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2242 def : Pat<(i32 (fp_to_sint Float32Regs:$a)),
2243 (CVT_s32_f32 Float32Regs:$a, CvtRZI)>;
2244 def : Pat<(i64 (fp_to_sint Float32Regs:$a)),
2245 (CVT_s64_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2246 def : Pat<(i64 (fp_to_sint Float32Regs:$a)),
2247 (CVT_s64_f32 Float32Regs:$a, CvtRZI)>;
2250 def : Pat<(i16 (fp_to_uint Float32Regs:$a)),
2251 (CVT_u16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2252 def : Pat<(i16 (fp_to_uint Float32Regs:$a)),
2253 (CVT_u16_f32 Float32Regs:$a, CvtRZI)>;
2254 def : Pat<(i32 (fp_to_uint Float32Regs:$a)),
2255 (CVT_u32_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2256 def : Pat<(i32 (fp_to_uint Float32Regs:$a)),
2257 (CVT_u32_f32 Float32Regs:$a, CvtRZI)>;
2258 def : Pat<(i64 (fp_to_uint Float32Regs:$a)),
2259 (CVT_u64_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2260 def : Pat<(i64 (fp_to_uint Float32Regs:$a)),
2261 (CVT_u64_f32 Float32Regs:$a, CvtRZI)>;
2264 def : Pat<(i16 (fp_to_sint Float64Regs:$a)),
2265 (CVT_s16_f64 Float64Regs:$a, CvtRZI)>;
2266 def : Pat<(i32 (fp_to_sint Float64Regs:$a)),
2267 (CVT_s32_f64 Float64Regs:$a, CvtRZI)>;
2268 def : Pat<(i64 (fp_to_sint Float64Regs:$a)),
2269 (CVT_s64_f64 Float64Regs:$a, CvtRZI)>;
2272 def : Pat<(i16 (fp_to_uint Float64Regs:$a)),
2273 (CVT_u16_f64 Float64Regs:$a, CvtRZI)>;
2274 def : Pat<(i32 (fp_to_uint Float64Regs:$a)),
2275 (CVT_u32_f64 Float64Regs:$a, CvtRZI)>;
2276 def : Pat<(i64 (fp_to_uint Float64Regs:$a)),
2277 (CVT_u64_f64 Float64Regs:$a, CvtRZI)>;
2280 def : Pat<(i16 (sext Int1Regs:$a)),
2281 (SELP_s16ii -1, 0, Int1Regs:$a)>;
2282 def : Pat<(i32 (sext Int1Regs:$a)),
2283 (SELP_s32ii -1, 0, Int1Regs:$a)>;
2284 def : Pat<(i64 (sext Int1Regs:$a)),
2285 (SELP_s64ii -1, 0, Int1Regs:$a)>;
2288 def : Pat<(i16 (zext Int1Regs:$a)),
2289 (SELP_u16ii 1, 0, Int1Regs:$a)>;
2290 def : Pat<(i32 (zext Int1Regs:$a)),
2291 (SELP_u32ii 1, 0, Int1Regs:$a)>;
2292 def : Pat<(i64 (zext Int1Regs:$a)),
2293 (SELP_u64ii 1, 0, Int1Regs:$a)>;
2296 def : Pat<(i16 (anyext Int1Regs:$a)),
2297 (SELP_u16ii 1, 0, Int1Regs:$a)>;
2298 def : Pat<(i32 (anyext Int1Regs:$a)),
2299 (SELP_u32ii 1, 0, Int1Regs:$a)>;
2300 def : Pat<(i64 (anyext Int1Regs:$a)),
2301 (SELP_u64ii 1, 0, Int1Regs:$a)>;
2304 def : Pat<(i32 (sext Int16Regs:$a)),
2305 (CVT_s32_s16 Int16Regs:$a, CvtNONE)>;
2306 def : Pat<(i64 (sext Int16Regs:$a)),
2307 (CVT_s64_s16 Int16Regs:$a, CvtNONE)>;
2310 def : Pat<(i32 (zext Int16Regs:$a)),
2311 (CVT_u32_u16 Int16Regs:$a, CvtNONE)>;
2312 def : Pat<(i64 (zext Int16Regs:$a)),
2313 (CVT_u64_u16 Int16Regs:$a, CvtNONE)>;
2316 def : Pat<(i32 (anyext Int16Regs:$a)),
2317 (CVT_u32_u16 Int16Regs:$a, CvtNONE)>;
2318 def : Pat<(i64 (anyext Int16Regs:$a)),
2319 (CVT_u64_u16 Int16Regs:$a, CvtNONE)>;
2322 def : Pat<(i64 (sext Int32Regs:$a)),
2323 (CVT_s64_s32 Int32Regs:$a, CvtNONE)>;
2326 def : Pat<(i64 (zext Int32Regs:$a)),
2327 (CVT_u64_u32 Int32Regs:$a, CvtNONE)>;
2330 def : Pat<(i64 (anyext Int32Regs:$a)),
2331 (CVT_u64_u32 Int32Regs:$a, CvtNONE)>;
2335 def : Pat<(i32 (trunc Int64Regs:$a)),
2336 (CVT_u32_u64 Int64Regs:$a, CvtNONE)>;
2337 def : Pat<(i16 (trunc Int64Regs:$a)),
2338 (CVT_u16_u64 Int64Regs:$a, CvtNONE)>;
2339 def : Pat<(i1 (trunc Int64Regs:$a)),
2340 (SETP_b64ri (ANDb64ri Int64Regs:$a, 1), 1, CmpEQ)>;
2343 def : Pat<(i16 (trunc Int32Regs:$a)),
2344 (CVT_u16_u32 Int32Regs:$a, CvtNONE)>;
2345 def : Pat<(i1 (trunc Int32Regs:$a)),
2346 (SETP_b32ri (ANDb32ri Int32Regs:$a, 1), 1, CmpEQ)>;
2349 def : Pat<(i1 (trunc Int16Regs:$a)),
2350 (SETP_b16ri (ANDb16ri Int16Regs:$a, 1), 1, CmpEQ)>;
2353 // Select instructions with 32-bit predicates
2354 def : Pat<(select Int32Regs:$pred, Int16Regs:$a, Int16Regs:$b),
2355 (SELP_b16rr Int16Regs:$a, Int16Regs:$b,
2356 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2357 def : Pat<(select Int32Regs:$pred, Int32Regs:$a, Int32Regs:$b),
2358 (SELP_b32rr Int32Regs:$a, Int32Regs:$b,
2359 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2360 def : Pat<(select Int32Regs:$pred, Int64Regs:$a, Int64Regs:$b),
2361 (SELP_b64rr Int64Regs:$a, Int64Regs:$b,
2362 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2363 def : Pat<(select Int32Regs:$pred, Float32Regs:$a, Float32Regs:$b),
2364 (SELP_f32rr Float32Regs:$a, Float32Regs:$b,
2365 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2366 def : Pat<(select Int32Regs:$pred, Float64Regs:$a, Float64Regs:$b),
2367 (SELP_f64rr Float64Regs:$a, Float64Regs:$b,
2368 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2371 class F_BITCONVERT<string SzStr, NVPTXRegClass regclassIn,
2372 NVPTXRegClass regclassOut> :
2373 NVPTXInst<(outs regclassOut:$d), (ins regclassIn:$a),
2374 !strconcat("mov.b", !strconcat(SzStr, " \t $d, $a;")),
2375 [(set regclassOut:$d, (bitconvert regclassIn:$a))]>;
2377 def BITCONVERT_32_I2F : F_BITCONVERT<"32", Int32Regs, Float32Regs>;
2378 def BITCONVERT_32_F2I : F_BITCONVERT<"32", Float32Regs, Int32Regs>;
2379 def BITCONVERT_64_I2F : F_BITCONVERT<"64", Int64Regs, Float64Regs>;
2380 def BITCONVERT_64_F2I : F_BITCONVERT<"64", Float64Regs, Int64Regs>;
2382 // pack a set of smaller int registers to a larger int register
2383 def V4I16toI64 : NVPTXInst<(outs Int64Regs:$d),
2384 (ins Int16Regs:$s1, Int16Regs:$s2,
2385 Int16Regs:$s3, Int16Regs:$s4),
2386 "mov.b64\t$d, {{$s1, $s2, $s3, $s4}};",
2388 def V2I16toI32 : NVPTXInst<(outs Int32Regs:$d),
2389 (ins Int16Regs:$s1, Int16Regs:$s2),
2390 "mov.b32\t$d, {{$s1, $s2}};",
2392 def V2I32toI64 : NVPTXInst<(outs Int64Regs:$d),
2393 (ins Int32Regs:$s1, Int32Regs:$s2),
2394 "mov.b64\t$d, {{$s1, $s2}};",
2396 def V2F32toF64 : NVPTXInst<(outs Float64Regs:$d),
2397 (ins Float32Regs:$s1, Float32Regs:$s2),
2398 "mov.b64\t$d, {{$s1, $s2}};",
2401 // unpack a larger int register to a set of smaller int registers
2402 def I64toV4I16 : NVPTXInst<(outs Int16Regs:$d1, Int16Regs:$d2,
2403 Int16Regs:$d3, Int16Regs:$d4),
2405 "mov.b64\t{{$d1, $d2, $d3, $d4}}, $s;",
2407 def I32toV2I16 : NVPTXInst<(outs Int16Regs:$d1, Int16Regs:$d2),
2409 "mov.b32\t{{$d1, $d2}}, $s;",
2411 def I64toV2I32 : NVPTXInst<(outs Int32Regs:$d1, Int32Regs:$d2),
2413 "mov.b64\t{{$d1, $d2}}, $s;",
2415 def F64toV2F32 : NVPTXInst<(outs Float32Regs:$d1, Float32Regs:$d2),
2416 (ins Float64Regs:$s),
2417 "mov.b64\t{{$d1, $d2}}, $s;",
2420 // Count leading zeros
2421 def CLZr32 : NVPTXInst<(outs Int32Regs:$d), (ins Int32Regs:$a),
2424 def CLZr64 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2428 // 32-bit has a direct PTX instruction
2429 def : Pat<(ctlz Int32Regs:$a),
2430 (CLZr32 Int32Regs:$a)>;
2431 def : Pat<(ctlz_zero_undef Int32Regs:$a),
2432 (CLZr32 Int32Regs:$a)>;
2434 // For 64-bit, the result in PTX is actually 32-bit so we zero-extend
2435 // to 64-bit to match the LLVM semantics
2436 def : Pat<(ctlz Int64Regs:$a),
2437 (CVT_u64_u32 (CLZr64 Int64Regs:$a), CvtNONE)>;
2438 def : Pat<(ctlz_zero_undef Int64Regs:$a),
2439 (CVT_u64_u32 (CLZr64 Int64Regs:$a), CvtNONE)>;
2441 // For 16-bit, we zero-extend to 32-bit, then trunc the result back
2442 // to 16-bits (ctlz of a 16-bit value is guaranteed to require less
2443 // than 16 bits to store). We also need to subtract 16 because the
2444 // high-order 16 zeros were counted.
2445 def : Pat<(ctlz Int16Regs:$a),
2446 (SUBi16ri (CVT_u16_u32 (CLZr32
2447 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2449 def : Pat<(ctlz_zero_undef Int16Regs:$a),
2450 (SUBi16ri (CVT_u16_u32 (CLZr32
2451 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2455 def POPCr32 : NVPTXInst<(outs Int32Regs:$d), (ins Int32Regs:$a),
2456 "popc.b32\t$d, $a;",
2458 def POPCr64 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2459 "popc.b64\t$d, $a;",
2462 // 32-bit has a direct PTX instruction
2463 def : Pat<(ctpop Int32Regs:$a),
2464 (POPCr32 Int32Regs:$a)>;
2466 // For 64-bit, the result in PTX is actually 32-bit so we zero-extend
2467 // to 64-bit to match the LLVM semantics
2468 def : Pat<(ctpop Int64Regs:$a),
2469 (CVT_u64_u32 (POPCr64 Int64Regs:$a), CvtNONE)>;
2471 // For 16-bit, we zero-extend to 32-bit, then trunc the result back
2472 // to 16-bits (ctpop of a 16-bit value is guaranteed to require less
2473 // than 16 bits to store)
2474 def : Pat<(ctpop Int16Regs:$a),
2475 (CVT_u16_u32 (POPCr32 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2478 // fround f64 -> f32
2479 def : Pat<(f32 (fround Float64Regs:$a)),
2480 (CVT_f32_f64 Float64Regs:$a, CvtRN_FTZ)>, Requires<[doF32FTZ]>;
2481 def : Pat<(f32 (fround Float64Regs:$a)),
2482 (CVT_f32_f64 Float64Regs:$a, CvtRN)>;
2484 // fextend f32 -> f64
2485 def : Pat<(f64 (fextend Float32Regs:$a)),
2486 (CVT_f64_f32 Float32Regs:$a, CvtNONE_FTZ)>, Requires<[doF32FTZ]>;
2487 def : Pat<(f64 (fextend Float32Regs:$a)),
2488 (CVT_f64_f32 Float32Regs:$a, CvtNONE)>;
2490 def retflag : SDNode<"NVPTXISD::RET_FLAG", SDTNone,
2491 [SDNPHasChain, SDNPOptInGlue]>;
2493 //-----------------------------------
2495 //-----------------------------------
2497 let isTerminator=1 in {
2498 let isReturn=1, isBarrier=1 in
2499 def Return : NVPTXInst<(outs), (ins), "ret;", [(retflag)]>;
2502 def CBranch : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2503 "@$a bra \t$target;",
2504 [(brcond Int1Regs:$a, bb:$target)]>;
2506 def CBranchOther : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2507 "@!$a bra \t$target;",
2510 let isBranch=1, isBarrier=1 in
2511 def GOTO : NVPTXInst<(outs), (ins brtarget:$target),
2512 "bra.uni \t$target;",
2516 def : Pat<(brcond Int32Regs:$a, bb:$target),
2517 (CBranch (SETP_u32ri Int32Regs:$a, 0, CmpNE), bb:$target)>;
2519 // SelectionDAGBuilder::visitSWitchCase() will invert the condition of a
2520 // conditional branch if
2521 // the target block is the next block so that the code can fall through to the
2523 // The invertion is done by 'xor condition, 1', which will be translated to
2524 // (setne condition, -1).
2525 // Since ptx supports '@!pred bra target', we should use it.
2526 def : Pat<(brcond (i1 (setne Int1Regs:$a, -1)), bb:$target),
2527 (CBranchOther Int1Regs:$a, bb:$target)>;
2530 def SDT_NVPTXCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2531 def SDT_NVPTXCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2532 SDTCisVT<1, i32> ]>;
2534 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_NVPTXCallSeqStart,
2535 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
2536 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_NVPTXCallSeqEnd,
2537 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
2540 def SDT_NVPTXCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2541 def call : SDNode<"NVPTXISD::CALL", SDT_NVPTXCall,
2542 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2543 def calltarget : Operand<i32>;
2545 def CALL : NVPTXInst<(outs), (ins calltarget:$dst),
2546 "call \t$dst, (1);", []>;
2549 def : Pat<(call tglobaladdr:$dst),
2550 (CALL tglobaladdr:$dst)>;
2551 def : Pat<(call texternalsym:$dst),
2552 (CALL texternalsym:$dst)>;
2554 // Pseudo instructions.
2555 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
2556 : NVPTXInst<outs, ins, asmstr, pattern>;
2558 // @TODO: We use some tricks here to emit curly braces. Can we clean this up
2559 // a bit without TableGen modifications?
2560 def Callseq_Start : NVPTXInst<(outs), (ins i32imm:$amt),
2561 "// Callseq Start $amt\n\t{{\n\t.reg .b32 temp_param_reg;\n\t// <end>}}",
2562 [(callseq_start timm:$amt)]>;
2563 def Callseq_End : NVPTXInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2564 "\n\t//{{\n\t}}// Callseq End $amt1",
2565 [(callseq_end timm:$amt1, timm:$amt2)]>;
2569 def trapinst : NVPTXInst<(outs), (ins),
2573 include "NVPTXIntrinsics.td"
2576 //-----------------------------------
2578 //-----------------------------------
2579 // BSWAP is currently expanded. The following is a more efficient
2580 // - for < sm_20, use vector scalar mov, as tesla support native 16-bit register
2581 // - for sm_20, use pmpt (use vector scalar mov to get the pack and
2582 // unpack). sm_20 supports native 32-bit register, but not native 16-bit