1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
16 #include "Mips16FrameLowering.h"
17 #include "Mips16HardFloat.h"
18 #include "Mips16ISelDAGToDAG.h"
19 #include "Mips16ISelLowering.h"
20 #include "Mips16InstrInfo.h"
21 #include "MipsFrameLowering.h"
22 #include "MipsInstrInfo.h"
23 #include "MipsModuleISelDAGToDAG.h"
25 #include "MipsSEFrameLowering.h"
26 #include "MipsSEISelDAGToDAG.h"
27 #include "MipsSEISelLowering.h"
28 #include "MipsSEInstrInfo.h"
29 #include "llvm/Analysis/TargetTransformInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/PassManager.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Transforms/Scalar.h"
38 #define DEBUG_TYPE "mips"
40 extern "C" void LLVMInitializeMipsTarget() {
41 // Register the target.
42 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
43 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
44 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
45 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
48 // On function prologue, the stack is created by decrementing
49 // its pointer. Once decremented, all references are done with positive
50 // offset from the stack/frame pointer, using StackGrowsUp enables
51 // an easier handling.
52 // Using CodeModel::Large enables different CALL behavior.
53 MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
54 StringRef CPU, StringRef FS,
55 const TargetOptions &Options,
56 Reloc::Model RM, CodeModel::Model CM,
57 CodeGenOpt::Level OL, bool isLittle)
58 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59 isLittle(isLittle), Subtarget(nullptr),
60 DefaultSubtarget(TT, CPU, FS, isLittle, this),
61 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
63 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
65 Subtarget = &DefaultSubtarget;
69 void MipsebTargetMachine::anchor() { }
72 MipsebTargetMachine(const Target &T, StringRef TT,
73 StringRef CPU, StringRef FS, const TargetOptions &Options,
74 Reloc::Model RM, CodeModel::Model CM,
76 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
78 void MipselTargetMachine::anchor() { }
81 MipselTargetMachine(const Target &T, StringRef TT,
82 StringRef CPU, StringRef FS, const TargetOptions &Options,
83 Reloc::Model RM, CodeModel::Model CM,
85 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
88 MipsTargetMachine::getSubtargetImpl(const Function &F) const override {
89 AttributeSet FnAttrs = F.getAttributes();
91 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
93 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
95 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
96 ? CPUAttr.getValueAsString().str()
98 std::string FS = !FSAttr.hasAttribute(Attribute::None)
99 ? FSAttr.getValueAsString().str()
102 !FnAttrs.getAttribute(AttributeSet::FunctionIndex, "mips16")
103 .hasAttribute(Attribute::None);
104 bool hasNoMips16Attr =
105 !FnAttrs.getAttribute(AttributeSet::FunctionIndex, "nomips16")
106 .hasAttribute(Attribute::None);
109 FS += FS.empty() ? "+mips16" : ",+mips16";
110 else if (hasNoMips16Attr)
111 FS += FS.empty() ? "-mips16" : ",-mips16";
113 auto &I = SubtargetMap[CPU + FS];
115 // This needs to be done before we create a new subtarget since any
116 // creation will depend on the TM and the code generation flags on the
117 // function that reside in TargetOptions.
118 resetTargetOptions(F);
119 I = make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, this);
124 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
125 DEBUG(dbgs() << "resetSubtarget\n");
127 Subtarget = const_cast<MipsSubtarget*>(getSubtargetImpl(MF->getFunction()));
128 MF->setSubtarget(Subtarget);
133 /// Mips Code Generator Pass Configuration Options.
134 class MipsPassConfig : public TargetPassConfig {
136 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
137 : TargetPassConfig(TM, PM) {
138 // The current implementation of long branch pass requires a scratch
139 // register ($at) to be available before branch instructions. Tail merging
140 // can break this requirement, so disable it when long branch pass is
142 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
145 MipsTargetMachine &getMipsTargetMachine() const {
146 return getTM<MipsTargetMachine>();
149 const MipsSubtarget &getMipsSubtarget() const {
150 return *getMipsTargetMachine().getSubtargetImpl();
153 void addIRPasses() override;
154 bool addInstSelector() override;
155 void addMachineSSAOptimization() override;
156 bool addPreEmitPass() override;
158 bool addPreRegAlloc() override;
163 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
164 return new MipsPassConfig(this, PM);
167 void MipsPassConfig::addIRPasses() {
168 TargetPassConfig::addIRPasses();
169 if (getMipsSubtarget().os16())
170 addPass(createMipsOs16(getMipsTargetMachine()));
171 if (getMipsSubtarget().inMips16HardFloat())
172 addPass(createMips16HardFloat(getMipsTargetMachine()));
174 // Install an instruction selector pass using
175 // the ISelDag to gen Mips code.
176 bool MipsPassConfig::addInstSelector() {
177 addPass(createMipsModuleISelDag(getMipsTargetMachine()));
178 addPass(createMips16ISelDag(getMipsTargetMachine()));
179 addPass(createMipsSEISelDag(getMipsTargetMachine()));
183 void MipsPassConfig::addMachineSSAOptimization() {
184 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
185 TargetPassConfig::addMachineSSAOptimization();
188 bool MipsPassConfig::addPreRegAlloc() {
189 if (getOptLevel() == CodeGenOpt::None) {
190 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
197 void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
198 if (Subtarget->allowMixed16_32()) {
199 DEBUG(errs() << "No ");
200 //FIXME: The Basic Target Transform Info
201 // pass needs to become a function pass instead of
202 // being an immutable pass and then this method as it exists now
203 // would be unnecessary.
204 PM.add(createNoTargetTransformInfoPass());
206 LLVMTargetMachine::addAnalysisPasses(PM);
207 DEBUG(errs() << "Target Transform Info Pass Added\n");
210 // Implemented by targets that want to run passes immediately before
211 // machine code is emitted. return true if -print-machineinstrs should
212 // print out the code after the passes.
213 bool MipsPassConfig::addPreEmitPass() {
214 MipsTargetMachine &TM = getMipsTargetMachine();
215 addPass(createMipsDelaySlotFillerPass(TM));
216 addPass(createMipsLongBranchPass(TM));
217 addPass(createMipsConstantIslandPass(TM));