1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "MipsFrameLowering.h"
18 #include "MipsISelLowering.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsJITInfo.h"
21 #include "MipsSelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
34 class MipsTargetMachine;
36 class MipsSubtarget : public MipsGenSubtargetInfo {
37 virtual void anchor();
40 // NOTE: O64 will not be supported.
42 UnknownABI, O32, N32, N64, EABI
47 Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
51 // Mips architecture version
52 MipsArchEnum MipsArchVersion;
54 // Mips supported ABIs
57 // IsLittle - The target is Little Endian
60 // IsSingleFloat - The target only supports single precision float
61 // point operations. This enable the target to use all 32 32-bit
62 // floating point registers instead of only using even ones.
65 // IsFP64bit - The target processor has 64-bit floating point registers.
68 // IsNan2008 - IEEE 754-2008 NaN encoding.
71 // IsFP64bit - General-purpose registers are 64 bits wide
74 // HasVFPU - Processor has a vector floating point unit.
77 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
80 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
83 // UseSmallSection - Small section is used.
86 /// Features related to the presence of specific instructions.
88 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
91 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
94 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
97 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
100 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
103 // InMips16 -- can process Mips16 instructions
107 bool InMips16HardFloat;
109 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
110 bool PreviousInMips16Mode;
112 // InMicroMips -- can process MicroMips instructions
113 bool InMicroMipsMode;
115 // HasDSP, HasDSPR2 -- supports DSP ASE.
116 bool HasDSP, HasDSPR2;
118 // Allow mixed Mips16 and Mips32 in one source file
119 bool AllowMixed16_32;
121 // Optimize for space by compiling all functions as Mips 16 unless
122 // it needs floating point. Functions needing floating point are
123 // compiled as Mips32
126 // HasMSA -- supports MSA ASE.
129 InstrItineraryData InstrItins;
134 // We can override the determination of whether we are in mips16 mode
135 // as from the command line
136 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
138 MipsTargetMachine *TM;
142 const DataLayout DL; // Calculates type size & alignment
143 const MipsSelectionDAGInfo TSInfo;
145 std::unique_ptr<const MipsInstrInfo> InstrInfo;
146 std::unique_ptr<const MipsFrameLowering> FrameLowering;
147 std::unique_ptr<const MipsTargetLowering> TLInfo;
148 std::unique_ptr<const MipsInstrInfo> InstrInfo16;
149 std::unique_ptr<const MipsFrameLowering> FrameLowering16;
150 std::unique_ptr<const MipsTargetLowering> TLInfo16;
151 std::unique_ptr<const MipsInstrInfo> InstrInfoSE;
152 std::unique_ptr<const MipsFrameLowering> FrameLoweringSE;
153 std::unique_ptr<const MipsTargetLowering> TLInfoSE;
156 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
157 AntiDepBreakMode& Mode,
158 RegClassVector& CriticalPathRCs) const override;
160 /// Only O32 and EABI supported right now.
161 bool isABI_EABI() const { return MipsABI == EABI; }
162 bool isABI_N64() const { return MipsABI == N64; }
163 bool isABI_N32() const { return MipsABI == N32; }
164 bool isABI_O32() const { return MipsABI == O32; }
165 unsigned getTargetABI() const { return MipsABI; }
167 /// This constructor initializes the data members to match that
168 /// of the specified triple.
169 MipsSubtarget(const std::string &TT, const std::string &CPU,
170 const std::string &FS, bool little, Reloc::Model RM,
171 MipsTargetMachine *TM);
173 /// ParseSubtargetFeatures - Parses features string setting specified
174 /// subtarget options. Definition of function is auto generated by tblgen.
175 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
177 bool hasMips2() const { return MipsArchVersion >= Mips2; }
178 bool hasMips3() const { return MipsArchVersion >= Mips3; }
179 bool hasMips4_32() const { return HasMips4_32; }
180 bool hasMips4_32r2() const { return HasMips4_32r2; }
181 bool hasMips32() const {
182 return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
183 MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
185 bool hasMips32r2() const {
186 return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
187 MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
189 bool hasMips32r6() const {
190 return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
192 bool hasMips64() const { return MipsArchVersion >= Mips64; }
193 bool hasMips64r2() const {
194 return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
196 bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
198 bool hasCnMips() const { return HasCnMips; }
200 bool isLittle() const { return IsLittle; }
201 bool isFP64bit() const { return IsFP64bit; }
202 bool isNaN2008() const { return IsNaN2008bit; }
203 bool isNotFP64bit() const { return !IsFP64bit; }
204 bool isGP64bit() const { return IsGP64bit; }
205 bool isGP32bit() const { return !IsGP64bit; }
206 bool isSingleFloat() const { return IsSingleFloat; }
207 bool isNotSingleFloat() const { return !IsSingleFloat; }
208 bool hasVFPU() const { return HasVFPU; }
209 bool inMips16Mode() const {
210 switch (OverrideMode) {
215 case NoMips16Override:
218 llvm_unreachable("Unexpected mode");
220 bool inMips16ModeDefault() const {
223 bool inMips16HardFloat() const {
224 return inMips16Mode() && InMips16HardFloat;
226 bool inMicroMipsMode() const { return InMicroMipsMode; }
227 bool hasDSP() const { return HasDSP; }
228 bool hasDSPR2() const { return HasDSPR2; }
229 bool hasMSA() const { return HasMSA; }
230 bool isLinux() const { return IsLinux; }
231 bool useSmallSection() const { return UseSmallSection; }
233 bool hasStandardEncoding() const { return !inMips16Mode(); }
235 bool mipsSEUsesSoftFloat() const;
237 bool enableLongBranchPass() const {
238 return hasStandardEncoding() || allowMixed16_32();
241 /// Features related to the presence of specific instructions.
242 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
244 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
245 bool allowMixed16_32() const { return inMips16ModeDefault() |
248 bool os16() const { return Os16;};
250 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
251 bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
253 // for now constant islands are on for the whole compilation unit but we only
254 // really use them if in addition we are in mips16 mode
255 static bool useConstantIslands();
257 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
259 // Grab relocation model
260 Reloc::Model getRelocationModel() const {return RM;}
262 /// \brief Reset the subtarget for the Mips target.
263 void resetSubtarget(MachineFunction *MF);
265 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
266 const TargetMachine *TM);
268 /// Does the system support unaligned memory access.
270 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
271 /// specify which component of the system provides it. Hardware, software, and
272 /// hybrid implementations are all valid.
273 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
275 // Set helper classes
276 void setHelperClassesMips16();
277 void setHelperClassesMipsSE();
279 MipsJITInfo *getJITInfo() { return &JITInfo; }
280 const MipsSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
281 const DataLayout *getDataLayout() const { return &DL; }
282 const MipsInstrInfo *getInstrInfo() const { return InstrInfo.get(); }
283 const TargetFrameLowering *getFrameLowering() const {
284 return FrameLowering.get();
286 const MipsRegisterInfo *getRegisterInfo() const {
287 return &InstrInfo->getRegisterInfo();
289 const MipsTargetLowering *getTargetLowering() const { return TLInfo.get(); }
291 } // End llvm namespace