1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "MCTargetDesc/MipsReginfo.h"
18 #include "llvm/MC/MCInstrItineraries.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
24 #define GET_SUBTARGETINFO_HEADER
25 #include "MipsGenSubtargetInfo.inc"
30 class MipsTargetMachine;
32 class MipsSubtarget : public MipsGenSubtargetInfo {
33 virtual void anchor();
36 // NOTE: O64 will not be supported.
38 UnknownABI, O32, N32, N64, EABI
44 Mips32, Mips32r2, Mips64, Mips64r2
47 // Mips architecture version
48 MipsArchEnum MipsArchVersion;
50 // Mips supported ABIs
53 // IsLittle - The target is Little Endian
56 // IsSingleFloat - The target only supports single precision float
57 // point operations. This enable the target to use all 32 32-bit
58 // floating point registers instead of only using even ones.
61 // IsFP64bit - The target processor has 64-bit floating point registers.
64 // IsFP64bit - General-purpose registers are 64 bits wide
67 // HasVFPU - Processor has a vector floating point unit.
70 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
73 // UseSmallSection - Small section is used.
76 /// Features related to the presence of specific instructions.
78 // HasSEInReg - SEB and SEH (signext in register) instructions.
81 // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
84 // HasSwap - Byte and half swap instructions.
87 // HasBitCount - Count leading '1' and '0' bits.
90 // HasFPIdx -- Floating point indexed load/store instructions.
93 // InMips16 -- can process Mips16 instructions
97 bool InMips16HardFloat;
99 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
100 bool PreviousInMips16Mode;
102 // InMicroMips -- can process MicroMips instructions
103 bool InMicroMipsMode;
105 // HasDSP, HasDSPR2 -- supports DSP ASE.
106 bool HasDSP, HasDSPR2;
108 // Allow mixed Mips16 and Mips32 in one source file
109 bool AllowMixed16_32;
111 // Optimize for space by compiling all functions as Mips 16 unless
112 // it needs floating point. Functions needing floating point are
113 // compiled as Mips32
116 InstrItineraryData InstrItins;
118 // The instance to the register info section object
124 // We can override the determination of whether we are in mips16 mode
125 // as from the command line
126 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
128 MipsTargetMachine *TM;
131 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
132 AntiDepBreakMode& Mode,
133 RegClassVector& CriticalPathRCs) const;
135 /// Only O32 and EABI supported right now.
136 bool isABI_EABI() const { return MipsABI == EABI; }
137 bool isABI_N64() const { return MipsABI == N64; }
138 bool isABI_N32() const { return MipsABI == N32; }
139 bool isABI_O32() const { return MipsABI == O32; }
140 unsigned getTargetABI() const { return MipsABI; }
142 /// This constructor initializes the data members to match that
143 /// of the specified triple.
144 MipsSubtarget(const std::string &TT, const std::string &CPU,
145 const std::string &FS, bool little, Reloc::Model RM,
146 MipsTargetMachine *TM);
148 /// ParseSubtargetFeatures - Parses features string setting specified
149 /// subtarget options. Definition of function is auto generated by tblgen.
150 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
152 bool hasMips32() const { return MipsArchVersion >= Mips32; }
153 bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
154 MipsArchVersion == Mips64r2; }
155 bool hasMips64() const { return MipsArchVersion >= Mips64; }
156 bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
158 bool isLittle() const { return IsLittle; }
159 bool isFP64bit() const { return IsFP64bit; }
160 bool isGP64bit() const { return IsGP64bit; }
161 bool isGP32bit() const { return !IsGP64bit; }
162 bool isSingleFloat() const { return IsSingleFloat; }
163 bool isNotSingleFloat() const { return !IsSingleFloat; }
164 bool hasVFPU() const { return HasVFPU; }
165 bool inMips16Mode() const {
166 switch (OverrideMode) {
171 case NoMips16Override:
174 llvm_unreachable("Unexpected mode");
176 bool inMips16ModeDefault() const {
179 bool inMips16HardFloat() const {
180 return inMips16Mode() && InMips16HardFloat;
182 bool inMicroMipsMode() const { return InMicroMipsMode; }
183 bool hasDSP() const { return HasDSP; }
184 bool hasDSPR2() const { return HasDSPR2; }
185 bool isLinux() const { return IsLinux; }
186 bool useSmallSection() const { return UseSmallSection; }
188 bool hasStandardEncoding() const { return !inMips16Mode(); }
190 /// Features related to the presence of specific instructions.
191 bool hasSEInReg() const { return HasSEInReg; }
192 bool hasCondMov() const { return HasCondMov; }
193 bool hasSwap() const { return HasSwap; }
194 bool hasBitCount() const { return HasBitCount; }
195 bool hasFPIdx() const { return HasFPIdx; }
197 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
198 bool allowMixed16_32() const { return inMips16ModeDefault() |
201 bool os16() const { return Os16;};
203 // Grab MipsRegInfo object
204 const MipsReginfo &getMReginfo() const { return MRI; }
206 // Grab relocation model
207 Reloc::Model getRelocationModel() const {return RM;}
209 /// \brief Reset the subtarget for the Mips target.
210 void resetSubtarget(MachineFunction *MF);
214 } // End llvm namespace