1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
17 #include "MipsFrameLowering.h"
18 #include "MipsISelLowering.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsJITInfo.h"
21 #include "MipsSelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
34 class MipsTargetMachine;
36 class MipsSubtarget : public MipsGenSubtargetInfo {
37 virtual void anchor();
40 // NOTE: O64 will not be supported.
42 UnknownABI, O32, N32, N64, EABI
47 Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
51 // Mips architecture version
52 MipsArchEnum MipsArchVersion;
54 // Mips supported ABIs
57 // IsLittle - The target is Little Endian
60 // IsSingleFloat - The target only supports single precision float
61 // point operations. This enable the target to use all 32 32-bit
62 // floating point registers instead of only using even ones.
65 // IsFPXX - MIPS O32 modeless ABI.
68 // NoABICalls - Disable SVR4-style position-independent code.
71 // IsFP64bit - The target processor has 64-bit floating point registers.
74 /// Are odd single-precision registers permitted?
75 /// This corresponds to -modd-spreg and -mno-odd-spreg
78 // IsNan2008 - IEEE 754-2008 NaN encoding.
81 // IsFP64bit - General-purpose registers are 64 bits wide
84 // HasVFPU - Processor has a vector floating point unit.
87 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
90 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
93 // UseSmallSection - Small section is used.
96 /// Features related to the presence of specific instructions.
98 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
101 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
104 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
107 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
110 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
113 // InMips16 -- can process Mips16 instructions
117 bool InMips16HardFloat;
119 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
120 bool PreviousInMips16Mode;
122 // InMicroMips -- can process MicroMips instructions
123 bool InMicroMipsMode;
125 // HasDSP, HasDSPR2 -- supports DSP ASE.
126 bool HasDSP, HasDSPR2;
128 // Allow mixed Mips16 and Mips32 in one source file
129 bool AllowMixed16_32;
131 // Optimize for space by compiling all functions as Mips 16 unless
132 // it needs floating point. Functions needing floating point are
133 // compiled as Mips32
136 // HasMSA -- supports MSA ASE.
139 InstrItineraryData InstrItins;
141 // We can override the determination of whether we are in mips16 mode
142 // as from the command line
143 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
145 MipsTargetMachine *TM;
149 const DataLayout DL; // Calculates type size & alignment
150 const MipsSelectionDAGInfo TSInfo;
152 std::unique_ptr<const MipsInstrInfo> InstrInfo;
153 std::unique_ptr<const MipsFrameLowering> FrameLowering;
154 std::unique_ptr<const MipsTargetLowering> TLInfo;
157 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
158 bool enablePostMachineScheduler() const override;
159 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
160 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
162 /// Only O32 and EABI supported right now.
163 bool isABI_EABI() const { return MipsABI == EABI; }
164 bool isABI_N64() const { return MipsABI == N64; }
165 bool isABI_N32() const { return MipsABI == N32; }
166 bool isABI_O32() const { return MipsABI == O32; }
167 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
168 unsigned getTargetABI() const { return MipsABI; }
170 /// This constructor initializes the data members to match that
171 /// of the specified triple.
172 MipsSubtarget(const std::string &TT, const std::string &CPU,
173 const std::string &FS, bool little, MipsTargetMachine *TM);
175 /// ParseSubtargetFeatures - Parses features string setting specified
176 /// subtarget options. Definition of function is auto generated by tblgen.
177 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
179 bool hasMips1() const { return MipsArchVersion >= Mips1; }
180 bool hasMips2() const { return MipsArchVersion >= Mips2; }
181 bool hasMips3() const { return MipsArchVersion >= Mips3; }
182 bool hasMips4() const { return MipsArchVersion >= Mips4; }
183 bool hasMips5() const { return MipsArchVersion >= Mips5; }
184 bool hasMips4_32() const { return HasMips4_32; }
185 bool hasMips4_32r2() const { return HasMips4_32r2; }
186 bool hasMips32() const {
187 return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
188 MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
190 bool hasMips32r2() const {
191 return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
192 MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
194 bool hasMips32r6() const {
195 return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
197 bool hasMips64() const { return MipsArchVersion >= Mips64; }
198 bool hasMips64r2() const {
199 return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
201 bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
203 bool hasCnMips() const { return HasCnMips; }
205 bool isLittle() const { return IsLittle; }
206 bool isABICalls() const { return !NoABICalls; }
207 bool isFPXX() const { return IsFPXX; }
208 bool isFP64bit() const { return IsFP64bit; }
209 bool useOddSPReg() const { return UseOddSPReg; }
210 bool noOddSPReg() const { return !UseOddSPReg; }
211 bool isNaN2008() const { return IsNaN2008bit; }
212 bool isNotFP64bit() const { return !IsFP64bit; }
213 bool isGP64bit() const { return IsGP64bit; }
214 bool isGP32bit() const { return !IsGP64bit; }
215 bool isSingleFloat() const { return IsSingleFloat; }
216 bool isNotSingleFloat() const { return !IsSingleFloat; }
217 bool hasVFPU() const { return HasVFPU; }
218 bool inMips16Mode() const { return InMips16Mode; }
219 bool inMips16ModeDefault() const {
222 // Hard float for mips16 means essentially to compile as soft float
223 // but to use a runtime library for soft float that is written with
224 // native mips32 floating point instructions (those runtime routines
225 // run in mips32 hard float mode).
226 bool inMips16HardFloat() const {
227 return inMips16Mode() && InMips16HardFloat;
229 bool inMicroMipsMode() const { return InMicroMipsMode; }
230 bool hasDSP() const { return HasDSP; }
231 bool hasDSPR2() const { return HasDSPR2; }
232 bool hasMSA() const { return HasMSA; }
233 bool isLinux() const { return IsLinux; }
234 bool useSmallSection() const { return UseSmallSection; }
236 bool hasStandardEncoding() const { return !inMips16Mode(); }
238 bool abiUsesSoftFloat() const;
240 bool enableLongBranchPass() const {
241 return hasStandardEncoding() || allowMixed16_32();
244 /// Features related to the presence of specific instructions.
245 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
246 bool hasMTHC1() const { return hasMips32r2(); }
248 bool allowMixed16_32() const { return inMips16ModeDefault() |
251 bool os16() const { return Os16;};
253 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
254 bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
256 // for now constant islands are on for the whole compilation unit but we only
257 // really use them if in addition we are in mips16 mode
258 static bool useConstantIslands();
260 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
262 // Grab relocation model
263 Reloc::Model getRelocationModel() const;
265 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
266 const TargetMachine *TM);
268 /// Does the system support unaligned memory access.
270 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
271 /// specify which component of the system provides it. Hardware, software, and
272 /// hybrid implementations are all valid.
273 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
275 // Set helper classes
276 void setHelperClassesMips16();
277 void setHelperClassesMipsSE();
279 MipsJITInfo *getJITInfo() override { return &JITInfo; }
280 const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
283 const DataLayout *getDataLayout() const override { return &DL; }
284 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
285 const TargetFrameLowering *getFrameLowering() const override {
286 return FrameLowering.get();
288 const MipsRegisterInfo *getRegisterInfo() const override {
289 return &InstrInfo->getRegisterInfo();
291 const MipsTargetLowering *getTargetLowering() const override {
294 const InstrItineraryData *getInstrItineraryData() const override {
298 } // End llvm namespace