1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "MipsGenSubtargetInfo.inc"
28 class MipsTargetMachine;
30 class MipsSubtarget : public MipsGenSubtargetInfo {
31 virtual void anchor();
34 // NOTE: O64 will not be supported.
36 UnknownABI, O32, N32, N64, EABI
41 Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
45 // Mips architecture version
46 MipsArchEnum MipsArchVersion;
48 // Mips supported ABIs
51 // IsLittle - The target is Little Endian
54 // IsSingleFloat - The target only supports single precision float
55 // point operations. This enable the target to use all 32 32-bit
56 // floating point registers instead of only using even ones.
59 // IsFP64bit - The target processor has 64-bit floating point registers.
62 // IsNan2008 - IEEE 754-2008 NaN encoding.
65 // IsFP64bit - General-purpose registers are 64 bits wide
68 // HasVFPU - Processor has a vector floating point unit.
71 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
74 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
77 // UseSmallSection - Small section is used.
80 /// Features related to the presence of specific instructions.
82 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
85 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
88 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
91 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
94 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
97 // InMips16 -- can process Mips16 instructions
101 bool InMips16HardFloat;
103 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
104 bool PreviousInMips16Mode;
106 // InMicroMips -- can process MicroMips instructions
107 bool InMicroMipsMode;
109 // HasDSP, HasDSPR2 -- supports DSP ASE.
110 bool HasDSP, HasDSPR2;
112 // Allow mixed Mips16 and Mips32 in one source file
113 bool AllowMixed16_32;
115 // Optimize for space by compiling all functions as Mips 16 unless
116 // it needs floating point. Functions needing floating point are
117 // compiled as Mips32
120 // HasMSA -- supports MSA ASE.
123 InstrItineraryData InstrItins;
128 // We can override the determination of whether we are in mips16 mode
129 // as from the command line
130 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
132 MipsTargetMachine *TM;
136 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
137 AntiDepBreakMode& Mode,
138 RegClassVector& CriticalPathRCs) const override;
140 /// Only O32 and EABI supported right now.
141 bool isABI_EABI() const { return MipsABI == EABI; }
142 bool isABI_N64() const { return MipsABI == N64; }
143 bool isABI_N32() const { return MipsABI == N32; }
144 bool isABI_O32() const { return MipsABI == O32; }
145 unsigned getTargetABI() const { return MipsABI; }
147 /// This constructor initializes the data members to match that
148 /// of the specified triple.
149 MipsSubtarget(const std::string &TT, const std::string &CPU,
150 const std::string &FS, bool little, Reloc::Model RM,
151 MipsTargetMachine *TM);
153 /// ParseSubtargetFeatures - Parses features string setting specified
154 /// subtarget options. Definition of function is auto generated by tblgen.
155 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
157 bool hasMips2() const { return MipsArchVersion >= Mips2; }
158 bool hasMips3() const { return MipsArchVersion >= Mips3; }
159 bool hasMips4_32() const { return HasMips4_32; }
160 bool hasMips4_32r2() const { return HasMips4_32r2; }
161 bool hasMips32() const { return MipsArchVersion >= Mips32; }
162 bool hasMips32r2() const {
163 return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
164 MipsArchVersion == Mips64r2;
166 bool hasMips32r6() const {
167 return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
169 bool hasMips64() const { return MipsArchVersion >= Mips64; }
170 bool hasMips64r2() const {
171 return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
173 bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
175 bool hasCnMips() const { return HasCnMips; }
177 bool isLittle() const { return IsLittle; }
178 bool isFP64bit() const { return IsFP64bit; }
179 bool isNaN2008() const { return IsNaN2008bit; }
180 bool isNotFP64bit() const { return !IsFP64bit; }
181 bool isGP64bit() const { return IsGP64bit; }
182 bool isGP32bit() const { return !IsGP64bit; }
183 bool isSingleFloat() const { return IsSingleFloat; }
184 bool isNotSingleFloat() const { return !IsSingleFloat; }
185 bool hasVFPU() const { return HasVFPU; }
186 bool inMips16Mode() const {
187 switch (OverrideMode) {
192 case NoMips16Override:
195 llvm_unreachable("Unexpected mode");
197 bool inMips16ModeDefault() const {
200 bool inMips16HardFloat() const {
201 return inMips16Mode() && InMips16HardFloat;
203 bool inMicroMipsMode() const { return InMicroMipsMode; }
204 bool hasDSP() const { return HasDSP; }
205 bool hasDSPR2() const { return HasDSPR2; }
206 bool hasMSA() const { return HasMSA; }
207 bool isLinux() const { return IsLinux; }
208 bool useSmallSection() const { return UseSmallSection; }
210 bool hasStandardEncoding() const { return !inMips16Mode(); }
212 bool mipsSEUsesSoftFloat() const;
214 bool enableLongBranchPass() const {
215 return hasStandardEncoding() || allowMixed16_32();
218 /// Features related to the presence of specific instructions.
219 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
221 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
222 bool allowMixed16_32() const { return inMips16ModeDefault() |
225 bool os16() const { return Os16;};
227 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
228 bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
230 // for now constant islands are on for the whole compilation unit but we only
231 // really use them if in addition we are in mips16 mode
232 static bool useConstantIslands();
234 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
236 // Grab relocation model
237 Reloc::Model getRelocationModel() const {return RM;}
239 /// \brief Reset the subtarget for the Mips target.
240 void resetSubtarget(MachineFunction *MF);
242 /// Does the system support unaligned memory access.
244 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
245 /// specify which component of the system provides it. Hardware, software, and
246 /// hybrid implementations are all valid.
247 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
249 } // End llvm namespace