1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "MipsGenSubtargetInfo.inc"
28 class MipsTargetMachine;
30 class MipsSubtarget : public MipsGenSubtargetInfo {
31 virtual void anchor();
34 // NOTE: O64 will not be supported.
36 UnknownABI, O32, N32, N64, EABI
40 enum MipsArchEnum { Mips1, Mips2, Mips32, Mips32r2, Mips3, Mips4, Mips5,
43 // Mips architecture version
44 MipsArchEnum MipsArchVersion;
46 // Mips supported ABIs
49 // IsLittle - The target is Little Endian
52 // IsSingleFloat - The target only supports single precision float
53 // point operations. This enable the target to use all 32 32-bit
54 // floating point registers instead of only using even ones.
57 // IsFP64bit - The target processor has 64-bit floating point registers.
60 // IsNan2008 - IEEE 754-2008 NaN encoding.
63 // IsFP64bit - General-purpose registers are 64 bits wide
66 // HasVFPU - Processor has a vector floating point unit.
69 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
72 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
75 // UseSmallSection - Small section is used.
78 /// Features related to the presence of specific instructions.
80 // HasSEInReg - SEB and SEH (signext in register) instructions.
83 // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
86 // HasSwap - Byte and half swap instructions.
89 // HasBitCount - Count leading '1' and '0' bits.
92 // HasFPIdx -- Floating point indexed load/store instructions.
95 // InMips16 -- can process Mips16 instructions
99 bool InMips16HardFloat;
101 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
102 bool PreviousInMips16Mode;
104 // InMicroMips -- can process MicroMips instructions
105 bool InMicroMipsMode;
107 // HasDSP, HasDSPR2 -- supports DSP ASE.
108 bool HasDSP, HasDSPR2;
110 // Allow mixed Mips16 and Mips32 in one source file
111 bool AllowMixed16_32;
113 // Optimize for space by compiling all functions as Mips 16 unless
114 // it needs floating point. Functions needing floating point are
115 // compiled as Mips32
118 // HasMSA -- supports MSA ASE.
121 InstrItineraryData InstrItins;
126 // We can override the determination of whether we are in mips16 mode
127 // as from the command line
128 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
130 MipsTargetMachine *TM;
134 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
135 AntiDepBreakMode& Mode,
136 RegClassVector& CriticalPathRCs) const override;
138 /// Only O32 and EABI supported right now.
139 bool isABI_EABI() const { return MipsABI == EABI; }
140 bool isABI_N64() const { return MipsABI == N64; }
141 bool isABI_N32() const { return MipsABI == N32; }
142 bool isABI_O32() const { return MipsABI == O32; }
143 unsigned getTargetABI() const { return MipsABI; }
145 /// This constructor initializes the data members to match that
146 /// of the specified triple.
147 MipsSubtarget(const std::string &TT, const std::string &CPU,
148 const std::string &FS, bool little, Reloc::Model RM,
149 MipsTargetMachine *TM);
151 /// ParseSubtargetFeatures - Parses features string setting specified
152 /// subtarget options. Definition of function is auto generated by tblgen.
153 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
155 bool hasMips32() const { return MipsArchVersion >= Mips32; }
156 bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
157 MipsArchVersion == Mips64r2; }
158 bool hasMips64() const { return MipsArchVersion >= Mips64; }
159 bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
161 bool hasCnMips() const { return HasCnMips; }
163 bool isLittle() const { return IsLittle; }
164 bool isFP64bit() const { return IsFP64bit; }
165 bool isNaN2008() const { return IsNaN2008bit; }
166 bool isNotFP64bit() const { return !IsFP64bit; }
167 bool isGP64bit() const { return IsGP64bit; }
168 bool isGP32bit() const { return !IsGP64bit; }
169 bool isSingleFloat() const { return IsSingleFloat; }
170 bool isNotSingleFloat() const { return !IsSingleFloat; }
171 bool hasVFPU() const { return HasVFPU; }
172 bool inMips16Mode() const {
173 switch (OverrideMode) {
178 case NoMips16Override:
181 llvm_unreachable("Unexpected mode");
183 bool inMips16ModeDefault() const {
186 bool inMips16HardFloat() const {
187 return inMips16Mode() && InMips16HardFloat;
189 bool inMicroMipsMode() const { return InMicroMipsMode; }
190 bool hasDSP() const { return HasDSP; }
191 bool hasDSPR2() const { return HasDSPR2; }
192 bool hasMSA() const { return HasMSA; }
193 bool isLinux() const { return IsLinux; }
194 bool useSmallSection() const { return UseSmallSection; }
196 bool hasStandardEncoding() const { return !inMips16Mode(); }
198 bool mipsSEUsesSoftFloat() const;
200 bool enableLongBranchPass() const {
201 return hasStandardEncoding() || allowMixed16_32();
204 /// Features related to the presence of specific instructions.
205 bool hasSEInReg() const { return HasSEInReg; }
206 bool hasCondMov() const { return HasCondMov; }
207 bool hasSwap() const { return HasSwap; }
208 bool hasBitCount() const { return HasBitCount; }
209 bool hasFPIdx() const { return HasFPIdx; }
210 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
212 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
213 bool allowMixed16_32() const { return inMips16ModeDefault() |
216 bool os16() const { return Os16;};
218 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
219 bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
221 // for now constant islands are on for the whole compilation unit but we only
222 // really use them if in addition we are in mips16 mode
223 static bool useConstantIslands();
225 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
227 // Grab relocation model
228 Reloc::Model getRelocationModel() const {return RM;}
230 /// \brief Reset the subtarget for the Mips target.
231 void resetSubtarget(MachineFunction *MF);
235 } // End llvm namespace