1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "MCTargetDesc/MipsReginfo.h"
18 #include "llvm/MC/MCInstrItineraries.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
24 #define GET_SUBTARGETINFO_HEADER
25 #include "MipsGenSubtargetInfo.inc"
30 class MipsTargetMachine;
32 class MipsSubtarget : public MipsGenSubtargetInfo {
33 virtual void anchor();
36 // NOTE: O64 will not be supported.
38 UnknownABI, O32, N32, N64, EABI
44 Mips32, Mips32r2, Mips64, Mips64r2
47 // Mips architecture version
48 MipsArchEnum MipsArchVersion;
50 // Mips supported ABIs
53 // IsLittle - The target is Little Endian
56 // IsSingleFloat - The target only supports single precision float
57 // point operations. This enable the target to use all 32 32-bit
58 // floating point registers instead of only using even ones.
61 // IsFP64bit - The target processor has 64-bit floating point registers.
64 // IsFP64bit - General-purpose registers are 64 bits wide
67 // HasVFPU - Processor has a vector floating point unit.
70 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
73 // UseSmallSection - Small section is used.
76 /// Features related to the presence of specific instructions.
78 // HasSEInReg - SEB and SEH (signext in register) instructions.
81 // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
84 // HasSwap - Byte and half swap instructions.
87 // HasBitCount - Count leading '1' and '0' bits.
90 // HasFPIdx -- Floating point indexed load/store instructions.
93 // InMips16 -- can process Mips16 instructions
96 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
97 bool PreviousInMips16Mode;
99 // InMicroMips -- can process MicroMips instructions
100 bool InMicroMipsMode;
102 // HasDSP, HasDSPR2 -- supports DSP ASE.
103 bool HasDSP, HasDSPR2;
105 // Allow mixed Mips16 and Mips32 in one source file
106 bool AllowMixed16_32;
108 InstrItineraryData InstrItins;
110 // The instance to the register info section object
116 // We can override the determination of whether we are in mips16 mode
117 // as from the command line
118 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
120 MipsTargetMachine *TM;
123 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
124 AntiDepBreakMode& Mode,
125 RegClassVector& CriticalPathRCs) const;
127 /// Only O32 and EABI supported right now.
128 bool isABI_EABI() const { return MipsABI == EABI; }
129 bool isABI_N64() const { return MipsABI == N64; }
130 bool isABI_N32() const { return MipsABI == N32; }
131 bool isABI_O32() const { return MipsABI == O32; }
132 unsigned getTargetABI() const { return MipsABI; }
134 /// This constructor initializes the data members to match that
135 /// of the specified triple.
136 MipsSubtarget(const std::string &TT, const std::string &CPU,
137 const std::string &FS, bool little, Reloc::Model RM,
138 MipsTargetMachine *TM);
140 /// ParseSubtargetFeatures - Parses features string setting specified
141 /// subtarget options. Definition of function is auto generated by tblgen.
142 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
144 bool hasMips32() const { return MipsArchVersion >= Mips32; }
145 bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
146 MipsArchVersion == Mips64r2; }
147 bool hasMips64() const { return MipsArchVersion >= Mips64; }
148 bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
150 bool isLittle() const { return IsLittle; }
151 bool isFP64bit() const { return IsFP64bit; }
152 bool isGP64bit() const { return IsGP64bit; }
153 bool isGP32bit() const { return !IsGP64bit; }
154 bool isSingleFloat() const { return IsSingleFloat; }
155 bool isNotSingleFloat() const { return !IsSingleFloat; }
156 bool hasVFPU() const { return HasVFPU; }
157 bool inMips16Mode() const {
158 switch (OverrideMode) {
163 case NoMips16Override:
166 llvm_unreachable("Unexpected mode");
168 bool inMips16ModeDefault() {
171 bool inMicroMipsMode() const { return InMicroMipsMode; }
172 bool hasDSP() const { return HasDSP; }
173 bool hasDSPR2() const { return HasDSPR2; }
174 bool isLinux() const { return IsLinux; }
175 bool useSmallSection() const { return UseSmallSection; }
177 bool hasStandardEncoding() const { return !inMips16Mode(); }
179 /// Features related to the presence of specific instructions.
180 bool hasSEInReg() const { return HasSEInReg; }
181 bool hasCondMov() const { return HasCondMov; }
182 bool hasSwap() const { return HasSwap; }
183 bool hasBitCount() const { return HasBitCount; }
184 bool hasFPIdx() const { return HasFPIdx; }
186 bool allowMixed16_32() const { return AllowMixed16_32;};
188 // Grab MipsRegInfo object
189 const MipsReginfo &getMReginfo() const { return MRI; }
191 // Grab relocation model
192 Reloc::Model getRelocationModel() const {return RM;}
194 /// \brief Reset the subtarget for the Mips target.
195 void resetSubtarget(MachineFunction *MF);
199 } // End llvm namespace