1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mips-subtarget"
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
34 // FIXME: Maybe this should be on by default when Mips16 is specified
36 static cl::opt<bool> Mixed16_32(
39 cl::desc("Allow for a mixture of Mips16 "
40 "and Mips32 code in a single source file"),
43 static cl::opt<bool> Mips_Os16(
46 cl::desc("Compile all functions that don' use "
47 "floating point as Mips 16"),
51 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
52 cl::desc("MIPS: mips16 hard float enable."),
56 Mips16ConstantIslands(
57 "mips16-constant-islands", cl::NotHidden,
58 cl::desc("MIPS: mips16 constant islands enable."),
61 /// Select the Mips CPU for the given triple and cpu name.
62 /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
63 static StringRef selectMipsCPU(Triple TT, StringRef CPU) {
64 if (CPU.empty() || CPU == "generic") {
65 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
73 void MipsSubtarget::anchor() { }
75 static std::string computeDataLayout(const MipsSubtarget &ST) {
78 // There are both little and big endian mips.
86 // Pointers are 32 bit on some ABIs.
90 // 8 and 16 bit integers only need no have natural alignment, but try to
91 // align them to 32 bits. 64 bit integers have natural alignment.
92 Ret += "-i8:8:32-i16:16:32-i64:64";
94 // 32 bit registers are always available and the stack is at least 64 bit
95 // aligned. On N64 64 bit registers are also available and the stack is
97 if (ST.isABI_N64() || ST.isABI_N32())
98 Ret += "-n32:64-S128";
105 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
106 const std::string &FS, bool little,
107 Reloc::Model _RM, MipsTargetMachine *_TM)
108 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
109 MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
110 IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
111 HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips3_32r2(false),
112 HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
113 InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
114 InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
115 AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
116 RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT),
117 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
118 TSInfo(DL), JITInfo() {
120 if (InMips16Mode && !TM->Options.UseSoftFloat) {
121 // Hard float for mips16 means essentially to compile as soft float
122 // but to use a runtime library for soft float that is written with
123 // native mips32 floating point instructions (those runtime routines
124 // run in mips32 hard float mode).
125 TM->Options.UseSoftFloat = true;
126 TM->Options.FloatABIType = FloatABI::Soft;
127 InMips16HardFloat = true;
130 PreviousInMips16Mode = InMips16Mode;
132 // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
133 // MIPS-V. They have not been tested and currently exist for the integrated
135 if (MipsArchVersion == Mips1)
136 report_fatal_error("Code generation for MIPS-I is not implemented", false);
137 if (MipsArchVersion == Mips2)
138 report_fatal_error("Code generation for MIPS-II is not implemented", false);
139 if (MipsArchVersion == Mips3)
140 report_fatal_error("Code generation for MIPS-III is not implemented",
142 if (MipsArchVersion == Mips5)
143 report_fatal_error("Code generation for MIPS-V is not implemented", false);
145 // Assert exactly one ABI was chosen.
146 assert(MipsABI != UnknownABI);
147 assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
148 ((getFeatureBits() & Mips::FeatureEABI) != 0) +
149 ((getFeatureBits() & Mips::FeatureN32) != 0) +
150 ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
152 // Check if Architecture and ABI are compatible.
153 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
154 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
155 "Invalid Arch & ABI pair.");
157 if (hasMSA() && !isFP64bit())
158 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
163 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
168 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
171 // Is the target system Linux ?
172 if (TT.find("linux") == std::string::npos)
175 // Set UseSmallSection.
176 // TODO: Investigate the IsLinux check. I suspect it's really checking for
178 UseSmallSection = !IsLinux && (RM == Reloc::Static);
182 MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
183 TargetSubtargetInfo::AntiDepBreakMode &Mode,
184 RegClassVector &CriticalPathRCs) const {
185 Mode = TargetSubtargetInfo::ANTIDEP_NONE;
186 CriticalPathRCs.clear();
187 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
188 : &Mips::GPR32RegClass);
189 return OptLevel >= CodeGenOpt::Aggressive;
192 MipsSubtarget &MipsSubtarget::initializeSubtargetDependencies(StringRef CPU,
194 std::string CPUName = selectMipsCPU(TargetTriple, CPU);
196 // Parse features string.
197 ParseSubtargetFeatures(CPUName, FS);
198 // Initialize scheduling itinerary for the specified CPU.
199 InstrItins = getInstrItineraryForCPU(CPUName);
203 //FIXME: This logic for reseting the subtarget along with
204 // the helper classes can probably be simplified but there are a lot of
205 // cases so we will defer rewriting this to later.
207 void MipsSubtarget::resetSubtarget(MachineFunction *MF) {
208 bool ChangeToMips16 = false, ChangeToNoMips16 = false;
209 DEBUG(dbgs() << "resetSubtargetFeatures" << "\n");
210 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
211 ChangeToMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
213 ChangeToNoMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
215 assert (!(ChangeToMips16 & ChangeToNoMips16) &&
216 "mips16 and nomips16 specified on the same function");
217 if (ChangeToMips16) {
218 if (PreviousInMips16Mode)
220 OverrideMode = Mips16Override;
221 PreviousInMips16Mode = true;
222 TM->setHelperClassesMips16();
224 } else if (ChangeToNoMips16) {
225 if (!PreviousInMips16Mode)
227 OverrideMode = NoMips16Override;
228 PreviousInMips16Mode = false;
229 TM->setHelperClassesMipsSE();
232 if (OverrideMode == NoOverride)
234 OverrideMode = NoOverride;
235 DEBUG(dbgs() << "back to default" << "\n");
236 if (inMips16Mode() && !PreviousInMips16Mode) {
237 TM->setHelperClassesMips16();
238 PreviousInMips16Mode = true;
239 } else if (!inMips16Mode() && PreviousInMips16Mode) {
240 TM->setHelperClassesMipsSE();
241 PreviousInMips16Mode = false;
247 bool MipsSubtarget::mipsSEUsesSoftFloat() const {
248 return TM->Options.UseSoftFloat && !InMips16HardFloat;
251 bool MipsSubtarget::useConstantIslands() {
252 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
253 return Mips16ConstantIslands;