1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsRegisterInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26 cl::desc("MIPS: Enable tail calls."), cl::init(false));
28 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29 cl::desc("Expand double precision loads and "
30 "stores to their single precision "
33 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34 : MipsTargetLowering(TM) {
35 // Set up the register classes
37 clearRegisterClasses();
39 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
42 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
44 if (Subtarget->hasDSP()) {
45 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
47 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
48 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
50 // Expand all builtin opcodes.
51 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
52 setOperationAction(Opc, VecTys[i], Expand);
54 setOperationAction(ISD::ADD, VecTys[i], Legal);
55 setOperationAction(ISD::SUB, VecTys[i], Legal);
56 setOperationAction(ISD::LOAD, VecTys[i], Legal);
57 setOperationAction(ISD::STORE, VecTys[i], Legal);
58 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
61 // Expand all truncating stores and extending loads.
62 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
63 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
65 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
66 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
67 setTruncStoreAction((MVT::SimpleValueType)VT0,
68 (MVT::SimpleValueType)VT1, Expand);
70 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
71 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
72 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
75 setTargetDAGCombine(ISD::SHL);
76 setTargetDAGCombine(ISD::SRA);
77 setTargetDAGCombine(ISD::SRL);
78 setTargetDAGCombine(ISD::SETCC);
79 setTargetDAGCombine(ISD::VSELECT);
82 if (Subtarget->hasDSPR2())
83 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
85 if (Subtarget->hasMSA()) {
86 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
87 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
88 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
89 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
90 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
91 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
92 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
94 setTargetDAGCombine(ISD::AND);
95 setTargetDAGCombine(ISD::SRA);
96 setTargetDAGCombine(ISD::XOR);
99 if (!Subtarget->mipsSEUsesSoftFloat()) {
100 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
102 // When dealing with single precision only, use libcalls
103 if (!Subtarget->isSingleFloat()) {
104 if (Subtarget->isFP64bit())
105 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
107 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
112 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
113 setOperationAction(ISD::MULHS, MVT::i32, Custom);
114 setOperationAction(ISD::MULHU, MVT::i32, Custom);
117 setOperationAction(ISD::MULHS, MVT::i64, Custom);
118 setOperationAction(ISD::MULHU, MVT::i64, Custom);
119 setOperationAction(ISD::MUL, MVT::i64, Custom);
122 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
123 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
125 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
126 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
127 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
128 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
129 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
130 setOperationAction(ISD::LOAD, MVT::i32, Custom);
131 setOperationAction(ISD::STORE, MVT::i32, Custom);
133 setTargetDAGCombine(ISD::ADDE);
134 setTargetDAGCombine(ISD::SUBE);
135 setTargetDAGCombine(ISD::MUL);
137 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
138 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
139 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
142 setOperationAction(ISD::LOAD, MVT::f64, Custom);
143 setOperationAction(ISD::STORE, MVT::f64, Custom);
146 computeRegisterProperties();
149 const MipsTargetLowering *
150 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
151 return new MipsSETargetLowering(TM);
154 // Enable MSA support for the given integer type and Register class.
155 void MipsSETargetLowering::
156 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
157 addRegisterClass(Ty, RC);
159 // Expand all builtin opcodes.
160 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
161 setOperationAction(Opc, Ty, Expand);
163 setOperationAction(ISD::BITCAST, Ty, Legal);
164 setOperationAction(ISD::LOAD, Ty, Legal);
165 setOperationAction(ISD::STORE, Ty, Legal);
166 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
167 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
168 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
170 setOperationAction(ISD::ADD, Ty, Legal);
171 setOperationAction(ISD::AND, Ty, Legal);
172 setOperationAction(ISD::CTLZ, Ty, Legal);
173 setOperationAction(ISD::CTPOP, Ty, Legal);
174 setOperationAction(ISD::MUL, Ty, Legal);
175 setOperationAction(ISD::OR, Ty, Legal);
176 setOperationAction(ISD::SDIV, Ty, Legal);
177 setOperationAction(ISD::SHL, Ty, Legal);
178 setOperationAction(ISD::SRA, Ty, Legal);
179 setOperationAction(ISD::SRL, Ty, Legal);
180 setOperationAction(ISD::SUB, Ty, Legal);
181 setOperationAction(ISD::UDIV, Ty, Legal);
182 setOperationAction(ISD::XOR, Ty, Legal);
185 // Enable MSA support for the given floating-point type and Register class.
186 void MipsSETargetLowering::
187 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
188 addRegisterClass(Ty, RC);
190 // Expand all builtin opcodes.
191 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
192 setOperationAction(Opc, Ty, Expand);
194 setOperationAction(ISD::LOAD, Ty, Legal);
195 setOperationAction(ISD::STORE, Ty, Legal);
196 setOperationAction(ISD::BITCAST, Ty, Legal);
197 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
199 if (Ty != MVT::v8f16) {
200 setOperationAction(ISD::FADD, Ty, Legal);
201 setOperationAction(ISD::FDIV, Ty, Legal);
202 setOperationAction(ISD::FLOG2, Ty, Legal);
203 setOperationAction(ISD::FMUL, Ty, Legal);
204 setOperationAction(ISD::FRINT, Ty, Legal);
205 setOperationAction(ISD::FSQRT, Ty, Legal);
206 setOperationAction(ISD::FSUB, Ty, Legal);
211 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
212 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
225 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
226 SelectionDAG &DAG) const {
227 switch(Op.getOpcode()) {
228 case ISD::LOAD: return lowerLOAD(Op, DAG);
229 case ISD::STORE: return lowerSTORE(Op, DAG);
230 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
231 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
232 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
233 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
234 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
235 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
236 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
238 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
239 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
240 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
241 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
242 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
245 return MipsTargetLowering::LowerOperation(Op, DAG);
249 // Transforms a subgraph in CurDAG if the following pattern is found:
250 // (addc multLo, Lo0), (adde multHi, Hi0),
252 // multHi/Lo: product of multiplication
253 // Lo0: initial value of Lo register
254 // Hi0: initial value of Hi register
255 // Return true if pattern matching was successful.
256 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
257 // ADDENode's second operand must be a flag output of an ADDC node in order
258 // for the matching to be successful.
259 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
261 if (ADDCNode->getOpcode() != ISD::ADDC)
264 SDValue MultHi = ADDENode->getOperand(0);
265 SDValue MultLo = ADDCNode->getOperand(0);
266 SDNode *MultNode = MultHi.getNode();
267 unsigned MultOpc = MultHi.getOpcode();
269 // MultHi and MultLo must be generated by the same node,
270 if (MultLo.getNode() != MultNode)
273 // and it must be a multiplication.
274 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
277 // MultLo amd MultHi must be the first and second output of MultNode
279 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
282 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
283 // of the values of MultNode, in which case MultNode will be removed in later
285 // If there exist users other than ADDENode or ADDCNode, this function returns
286 // here, which will result in MultNode being mapped to a single MULT
287 // instruction node rather than a pair of MULT and MADD instructions being
289 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
294 // Initialize accumulator.
295 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
296 ADDCNode->getOperand(1),
297 ADDENode->getOperand(1));
299 // create MipsMAdd(u) node
300 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
302 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
303 MultNode->getOperand(0),// Factor 0
304 MultNode->getOperand(1),// Factor 1
307 // replace uses of adde and addc here
308 if (!SDValue(ADDCNode, 0).use_empty()) {
309 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
310 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
312 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
314 if (!SDValue(ADDENode, 0).use_empty()) {
315 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
316 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
318 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
325 // Transforms a subgraph in CurDAG if the following pattern is found:
326 // (addc Lo0, multLo), (sube Hi0, multHi),
328 // multHi/Lo: product of multiplication
329 // Lo0: initial value of Lo register
330 // Hi0: initial value of Hi register
331 // Return true if pattern matching was successful.
332 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
333 // SUBENode's second operand must be a flag output of an SUBC node in order
334 // for the matching to be successful.
335 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
337 if (SUBCNode->getOpcode() != ISD::SUBC)
340 SDValue MultHi = SUBENode->getOperand(1);
341 SDValue MultLo = SUBCNode->getOperand(1);
342 SDNode *MultNode = MultHi.getNode();
343 unsigned MultOpc = MultHi.getOpcode();
345 // MultHi and MultLo must be generated by the same node,
346 if (MultLo.getNode() != MultNode)
349 // and it must be a multiplication.
350 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
353 // MultLo amd MultHi must be the first and second output of MultNode
355 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
358 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
359 // of the values of MultNode, in which case MultNode will be removed in later
361 // If there exist users other than SUBENode or SUBCNode, this function returns
362 // here, which will result in MultNode being mapped to a single MULT
363 // instruction node rather than a pair of MULT and MSUB instructions being
365 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
370 // Initialize accumulator.
371 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
372 SUBCNode->getOperand(0),
373 SUBENode->getOperand(0));
375 // create MipsSub(u) node
376 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
378 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
379 MultNode->getOperand(0),// Factor 0
380 MultNode->getOperand(1),// Factor 1
383 // replace uses of sube and subc here
384 if (!SDValue(SUBCNode, 0).use_empty()) {
385 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
386 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
388 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
390 if (!SDValue(SUBENode, 0).use_empty()) {
391 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
392 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
394 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
400 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
401 TargetLowering::DAGCombinerInfo &DCI,
402 const MipsSubtarget *Subtarget) {
403 if (DCI.isBeforeLegalize())
406 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
408 return SDValue(N, 0);
413 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
415 // Performs the following transformations:
416 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
417 // sign/zero-extension is completely overwritten by the new one performed by
419 // - Removes redundant zero extensions performed by an ISD::AND.
420 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
421 TargetLowering::DAGCombinerInfo &DCI,
422 const MipsSubtarget *Subtarget) {
423 if (!Subtarget->hasMSA())
426 SDValue Op0 = N->getOperand(0);
427 SDValue Op1 = N->getOperand(1);
428 unsigned Op0Opcode = Op0->getOpcode();
430 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
431 // where $d + 1 == 2^n and n == 32
432 // or $d + 1 == 2^n and n <= 32 and ZExt
433 // -> (MipsVExtractZExt $a, $b, $c)
434 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
435 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
436 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
441 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
443 if (Log2IfPositive <= 0)
444 return SDValue(); // Mask+1 is not a power of 2
446 SDValue Op0Op2 = Op0->getOperand(2);
447 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
448 unsigned ExtendTySize = ExtendTy.getSizeInBits();
449 unsigned Log2 = Log2IfPositive;
451 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
452 Log2 == ExtendTySize) {
453 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
454 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
455 Op0->getVTList(), Ops, Op0->getNumOperands());
463 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
464 TargetLowering::DAGCombinerInfo &DCI,
465 const MipsSubtarget *Subtarget) {
466 if (DCI.isBeforeLegalize())
469 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
471 return SDValue(N, 0);
476 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
477 EVT ShiftTy, SelectionDAG &DAG) {
478 // Clear the upper (64 - VT.sizeInBits) bits.
479 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
483 return DAG.getConstant(0, VT);
489 // If c is power of 2, return (shl x, log2(c)).
490 if (isPowerOf2_64(C))
491 return DAG.getNode(ISD::SHL, DL, VT, X,
492 DAG.getConstant(Log2_64(C), ShiftTy));
494 unsigned Log2Ceil = Log2_64_Ceil(C);
495 uint64_t Floor = 1LL << Log2_64(C);
496 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
498 // If |c - floor_c| <= |c - ceil_c|,
499 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
500 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
501 if (C - Floor <= Ceil - C) {
502 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
503 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
504 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
507 // If |c - floor_c| > |c - ceil_c|,
508 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
509 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
510 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
511 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
514 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
515 const TargetLowering::DAGCombinerInfo &DCI,
516 const MipsSETargetLowering *TL) {
517 EVT VT = N->getValueType(0);
519 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
521 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
522 VT, TL->getScalarShiftAmountTy(VT), DAG);
524 return SDValue(N, 0);
527 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
529 const MipsSubtarget *Subtarget) {
530 // See if this is a vector splat immediate node.
531 APInt SplatValue, SplatUndef;
532 unsigned SplatBitSize;
534 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
535 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
538 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
539 EltSize, !Subtarget->isLittle()) ||
540 (SplatBitSize != EltSize) ||
541 (SplatValue.getZExtValue() >= EltSize))
544 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
545 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
548 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
549 TargetLowering::DAGCombinerInfo &DCI,
550 const MipsSubtarget *Subtarget) {
551 EVT Ty = N->getValueType(0);
553 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
556 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
559 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
560 // constant splats into MipsISD::SHRA_DSP for DSPr2.
562 // Performs the following transformations:
563 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
564 // sign/zero-extension is completely overwritten by the new one performed by
565 // the ISD::SRA and ISD::SHL nodes.
566 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
569 // See performDSPShiftCombine for more information about the transformation
571 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
572 TargetLowering::DAGCombinerInfo &DCI,
573 const MipsSubtarget *Subtarget) {
574 EVT Ty = N->getValueType(0);
576 if (Subtarget->hasMSA()) {
577 SDValue Op0 = N->getOperand(0);
578 SDValue Op1 = N->getOperand(1);
580 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
581 // where $d + sizeof($c) == 32
582 // or $d + sizeof($c) <= 32 and SExt
583 // -> (MipsVExtractSExt $a, $b, $c)
584 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
585 SDValue Op0Op0 = Op0->getOperand(0);
586 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
591 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
592 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
594 if (TotalBits == 32 ||
595 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
597 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
598 Op0Op0->getOperand(2) };
599 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
600 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
606 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
609 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
613 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
614 TargetLowering::DAGCombinerInfo &DCI,
615 const MipsSubtarget *Subtarget) {
616 EVT Ty = N->getValueType(0);
618 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
621 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
624 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
625 bool IsV216 = (Ty == MVT::v2i16);
629 case ISD::SETNE: return true;
633 case ISD::SETGE: return IsV216;
637 case ISD::SETUGE: return !IsV216;
638 default: return false;
642 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
643 EVT Ty = N->getValueType(0);
645 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
648 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
651 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
652 N->getOperand(1), N->getOperand(2));
655 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
656 EVT Ty = N->getValueType(0);
658 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
661 SDValue SetCC = N->getOperand(0);
663 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
666 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
667 SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
668 N->getOperand(2), SetCC.getOperand(2));
671 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
672 const MipsSubtarget *Subtarget) {
673 EVT Ty = N->getValueType(0);
675 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
676 // Try the following combines:
677 // (xor (or $a, $b), (build_vector allones))
678 // (xor (or $a, $b), (bitcast (build_vector allones)))
679 SDValue Op0 = N->getOperand(0);
680 SDValue Op1 = N->getOperand(1);
682 ConstantSDNode *Const;
684 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
686 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
688 else if ((Op0->getOpcode() == MipsISD::VSPLAT ||
689 Op0->getOpcode() == MipsISD::VSPLATD) &&
690 (Const = dyn_cast<ConstantSDNode>(Op0->getOperand(0))) &&
691 Const->isAllOnesValue())
693 else if ((Op1->getOpcode() == MipsISD::VSPLAT ||
694 Op1->getOpcode() == MipsISD::VSPLATD) &&
695 (Const = dyn_cast<ConstantSDNode>(Op1->getOperand(0))) &&
696 Const->isAllOnesValue())
701 if (NotOp->getOpcode() == ISD::OR)
702 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
703 NotOp->getOperand(1));
710 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
711 SelectionDAG &DAG = DCI.DAG;
714 switch (N->getOpcode()) {
716 return performADDECombine(N, DAG, DCI, Subtarget);
718 Val = performANDCombine(N, DAG, DCI, Subtarget);
721 return performSUBECombine(N, DAG, DCI, Subtarget);
723 return performMULCombine(N, DAG, DCI, this);
725 return performSHLCombine(N, DAG, DCI, Subtarget);
727 return performSRACombine(N, DAG, DCI, Subtarget);
729 return performSRLCombine(N, DAG, DCI, Subtarget);
731 return performVSELECTCombine(N, DAG);
733 Val = performXORCombine(N, DAG, Subtarget);
736 Val = performSETCCCombine(N, DAG);
743 return MipsTargetLowering::PerformDAGCombine(N, DCI);
747 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
748 MachineBasicBlock *BB) const {
749 switch (MI->getOpcode()) {
751 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
752 case Mips::BPOSGE32_PSEUDO:
753 return emitBPOSGE32(MI, BB);
754 case Mips::SNZ_B_PSEUDO:
755 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
756 case Mips::SNZ_H_PSEUDO:
757 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
758 case Mips::SNZ_W_PSEUDO:
759 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
760 case Mips::SNZ_D_PSEUDO:
761 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
762 case Mips::SNZ_V_PSEUDO:
763 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
764 case Mips::SZ_B_PSEUDO:
765 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
766 case Mips::SZ_H_PSEUDO:
767 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
768 case Mips::SZ_W_PSEUDO:
769 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
770 case Mips::SZ_D_PSEUDO:
771 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
772 case Mips::SZ_V_PSEUDO:
773 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
777 bool MipsSETargetLowering::
778 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
779 unsigned NextStackOffset,
780 const MipsFunctionInfo& FI) const {
781 if (!EnableMipsTailCalls)
784 // Return false if either the callee or caller has a byval argument.
785 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
788 // Return true if the callee's argument area is no larger than the
790 return NextStackOffset <= FI.getIncomingArgSize();
793 void MipsSETargetLowering::
794 getOpndList(SmallVectorImpl<SDValue> &Ops,
795 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
796 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
797 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
798 // T9 should contain the address of the callee function if
799 // -reloction-model=pic or it is an indirect call.
800 if (IsPICCall || !GlobalOrExternal) {
801 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
802 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
804 Ops.push_back(Callee);
806 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
807 InternalLinkage, CLI, Callee, Chain);
810 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
811 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
813 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
814 return MipsTargetLowering::lowerLOAD(Op, DAG);
816 // Replace a double precision load with two i32 loads and a buildpair64.
818 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
819 EVT PtrVT = Ptr.getValueType();
821 // i32 load from lower address.
822 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
823 MachinePointerInfo(), Nd.isVolatile(),
824 Nd.isNonTemporal(), Nd.isInvariant(),
827 // i32 load from higher address.
828 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
829 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
830 MachinePointerInfo(), Nd.isVolatile(),
831 Nd.isNonTemporal(), Nd.isInvariant(),
832 std::min(Nd.getAlignment(), 4U));
834 if (!Subtarget->isLittle())
837 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
838 SDValue Ops[2] = {BP, Hi.getValue(1)};
839 return DAG.getMergeValues(Ops, 2, DL);
842 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
843 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
845 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
846 return MipsTargetLowering::lowerSTORE(Op, DAG);
848 // Replace a double precision store with two extractelement64s and i32 stores.
850 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
851 EVT PtrVT = Ptr.getValueType();
852 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
853 Val, DAG.getConstant(0, MVT::i32));
854 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
855 Val, DAG.getConstant(1, MVT::i32));
857 if (!Subtarget->isLittle())
860 // i32 store to lower address.
861 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
862 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
865 // i32 store to higher address.
866 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
867 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
868 Nd.isVolatile(), Nd.isNonTemporal(),
869 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
872 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
873 bool HasLo, bool HasHi,
874 SelectionDAG &DAG) const {
875 EVT Ty = Op.getOperand(0).getValueType();
877 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
878 Op.getOperand(0), Op.getOperand(1));
882 Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
883 DAG.getConstant(Mips::sub_lo, MVT::i32));
885 Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
886 DAG.getConstant(Mips::sub_hi, MVT::i32));
888 if (!HasLo || !HasHi)
889 return HasLo ? Lo : Hi;
891 SDValue Vals[] = { Lo, Hi };
892 return DAG.getMergeValues(Vals, 2, DL);
896 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
897 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
898 DAG.getConstant(0, MVT::i32));
899 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
900 DAG.getConstant(1, MVT::i32));
901 return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
904 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
905 SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
906 DAG.getConstant(Mips::sub_lo, MVT::i32));
907 SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
908 DAG.getConstant(Mips::sub_hi, MVT::i32));
909 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
912 // This function expands mips intrinsic nodes which have 64-bit input operands
915 // out64 = intrinsic-node in64
917 // lo = copy (extract-element (in64, 0))
918 // hi = copy (extract-element (in64, 1))
919 // mips-specific-node
922 // out64 = merge-values (v0, v1)
924 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
926 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
927 SmallVector<SDValue, 3> Ops;
930 // See if Op has a chain input.
932 Ops.push_back(Op->getOperand(OpNo++));
934 // The next operand is the intrinsic opcode.
935 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
937 // See if the next operand has type i64.
938 SDValue Opnd = Op->getOperand(++OpNo), In64;
940 if (Opnd.getValueType() == MVT::i64)
941 In64 = initAccumulator(Opnd, DL, DAG);
945 // Push the remaining operands.
946 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
947 Ops.push_back(Op->getOperand(OpNo));
949 // Add In64 to the end of the list.
954 SmallVector<EVT, 2> ResTys;
956 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
958 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
961 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
962 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
967 assert(Val->getValueType(1) == MVT::Other);
968 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
969 return DAG.getMergeValues(Vals, 2, DL);
972 static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
974 SDValue LHS = Op->getOperand(1);
975 SDValue RHS = Op->getOperand(2);
976 EVT ResTy = Op->getValueType(0);
978 SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS);
983 static SDValue lowerMSABinaryImmIntr(SDValue Op, SelectionDAG &DAG,
984 unsigned Opc, SDValue RHS) {
985 SDValue LHS = Op->getOperand(1);
986 EVT ResTy = Op->getValueType(0);
988 return DAG.getNode(Opc, SDLoc(Op), ResTy, LHS, RHS);
991 static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
993 SDValue Value = Op->getOperand(1);
994 EVT ResTy = Op->getValueType(0);
996 SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
1001 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1002 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1004 SDValue Vec = Op->getOperand(1);
1005 SDValue Idx = Op->getOperand(2);
1006 EVT ResTy = Op->getValueType(0);
1007 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1009 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1010 DAG.getValueType(EltTy));
1015 // Lower an MSA insert intrinsic into the specified SelectionDAG node
1016 static SDValue lowerMSAInsertIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1018 SDValue Op0 = Op->getOperand(1);
1019 SDValue Op1 = Op->getOperand(2);
1020 SDValue Op2 = Op->getOperand(3);
1021 EVT ResTy = Op->getValueType(0);
1023 SDValue Result = DAG.getNode(Opc, DL, ResTy, Op0, Op2, Op1);
1028 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1029 EVT ResTy = Op->getValueType(0);
1031 unsigned SplatOp = MipsISD::VSPLAT;
1032 if (ResTy == MVT::v2i64)
1033 SplatOp = MipsISD::VSPLATD;
1035 return DAG.getNode(SplatOp, SDLoc(Op), ResTy, Op->getOperand(ImmOp));
1038 static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1040 SDValue Value = Op->getOperand(1);
1041 EVT ResTy = Op->getValueType(0);
1043 SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
1048 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1049 SelectionDAG &DAG) const {
1050 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1053 case Intrinsic::mips_shilo:
1054 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1055 case Intrinsic::mips_dpau_h_qbl:
1056 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1057 case Intrinsic::mips_dpau_h_qbr:
1058 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1059 case Intrinsic::mips_dpsu_h_qbl:
1060 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1061 case Intrinsic::mips_dpsu_h_qbr:
1062 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1063 case Intrinsic::mips_dpa_w_ph:
1064 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1065 case Intrinsic::mips_dps_w_ph:
1066 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1067 case Intrinsic::mips_dpax_w_ph:
1068 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1069 case Intrinsic::mips_dpsx_w_ph:
1070 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1071 case Intrinsic::mips_mulsa_w_ph:
1072 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1073 case Intrinsic::mips_mult:
1074 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1075 case Intrinsic::mips_multu:
1076 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1077 case Intrinsic::mips_madd:
1078 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1079 case Intrinsic::mips_maddu:
1080 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1081 case Intrinsic::mips_msub:
1082 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1083 case Intrinsic::mips_msubu:
1084 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1085 case Intrinsic::mips_addv_b:
1086 case Intrinsic::mips_addv_h:
1087 case Intrinsic::mips_addv_w:
1088 case Intrinsic::mips_addv_d:
1089 return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
1090 case Intrinsic::mips_addvi_b:
1091 case Intrinsic::mips_addvi_h:
1092 case Intrinsic::mips_addvi_w:
1093 case Intrinsic::mips_addvi_d:
1094 return lowerMSABinaryImmIntr(Op, DAG, ISD::ADD,
1095 lowerMSASplatImm(Op, 2, DAG));
1096 case Intrinsic::mips_and_v:
1097 return lowerMSABinaryIntr(Op, DAG, ISD::AND);
1098 case Intrinsic::mips_bnz_b:
1099 case Intrinsic::mips_bnz_h:
1100 case Intrinsic::mips_bnz_w:
1101 case Intrinsic::mips_bnz_d:
1102 return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
1103 case Intrinsic::mips_bnz_v:
1104 return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
1105 case Intrinsic::mips_bz_b:
1106 case Intrinsic::mips_bz_h:
1107 case Intrinsic::mips_bz_w:
1108 case Intrinsic::mips_bz_d:
1109 return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
1110 case Intrinsic::mips_bz_v:
1111 return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
1112 case Intrinsic::mips_copy_s_b:
1113 case Intrinsic::mips_copy_s_h:
1114 case Intrinsic::mips_copy_s_w:
1115 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1116 case Intrinsic::mips_copy_u_b:
1117 case Intrinsic::mips_copy_u_h:
1118 case Intrinsic::mips_copy_u_w:
1119 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1120 case Intrinsic::mips_div_s_b:
1121 case Intrinsic::mips_div_s_h:
1122 case Intrinsic::mips_div_s_w:
1123 case Intrinsic::mips_div_s_d:
1124 return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
1125 case Intrinsic::mips_div_u_b:
1126 case Intrinsic::mips_div_u_h:
1127 case Intrinsic::mips_div_u_w:
1128 case Intrinsic::mips_div_u_d:
1129 return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
1130 case Intrinsic::mips_fadd_w:
1131 case Intrinsic::mips_fadd_d:
1132 return lowerMSABinaryIntr(Op, DAG, ISD::FADD);
1133 case Intrinsic::mips_fdiv_w:
1134 case Intrinsic::mips_fdiv_d:
1135 return lowerMSABinaryIntr(Op, DAG, ISD::FDIV);
1136 case Intrinsic::mips_fill_b:
1137 case Intrinsic::mips_fill_h:
1138 case Intrinsic::mips_fill_w:
1139 return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
1140 case Intrinsic::mips_flog2_w:
1141 case Intrinsic::mips_flog2_d:
1142 return lowerMSAUnaryIntr(Op, DAG, ISD::FLOG2);
1143 case Intrinsic::mips_fmul_w:
1144 case Intrinsic::mips_fmul_d:
1145 return lowerMSABinaryIntr(Op, DAG, ISD::FMUL);
1146 case Intrinsic::mips_frint_w:
1147 case Intrinsic::mips_frint_d:
1148 return lowerMSAUnaryIntr(Op, DAG, ISD::FRINT);
1149 case Intrinsic::mips_fsqrt_w:
1150 case Intrinsic::mips_fsqrt_d:
1151 return lowerMSAUnaryIntr(Op, DAG, ISD::FSQRT);
1152 case Intrinsic::mips_fsub_w:
1153 case Intrinsic::mips_fsub_d:
1154 return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
1155 case Intrinsic::mips_insert_b:
1156 case Intrinsic::mips_insert_h:
1157 case Intrinsic::mips_insert_w:
1158 return lowerMSAInsertIntr(Op, DAG, ISD::INSERT_VECTOR_ELT);
1159 case Intrinsic::mips_ldi_b:
1160 case Intrinsic::mips_ldi_h:
1161 case Intrinsic::mips_ldi_w:
1162 case Intrinsic::mips_ldi_d:
1163 return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
1164 case Intrinsic::mips_mulv_b:
1165 case Intrinsic::mips_mulv_h:
1166 case Intrinsic::mips_mulv_w:
1167 case Intrinsic::mips_mulv_d:
1168 return lowerMSABinaryIntr(Op, DAG, ISD::MUL);
1169 case Intrinsic::mips_nlzc_b:
1170 case Intrinsic::mips_nlzc_h:
1171 case Intrinsic::mips_nlzc_w:
1172 case Intrinsic::mips_nlzc_d:
1173 return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ);
1174 case Intrinsic::mips_nor_v: {
1175 SDValue Res = lowerMSABinaryIntr(Op, DAG, ISD::OR);
1176 return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
1178 case Intrinsic::mips_or_v:
1179 return lowerMSABinaryIntr(Op, DAG, ISD::OR);
1180 case Intrinsic::mips_pcnt_b:
1181 case Intrinsic::mips_pcnt_h:
1182 case Intrinsic::mips_pcnt_w:
1183 case Intrinsic::mips_pcnt_d:
1184 return lowerMSAUnaryIntr(Op, DAG, ISD::CTPOP);
1185 case Intrinsic::mips_sll_b:
1186 case Intrinsic::mips_sll_h:
1187 case Intrinsic::mips_sll_w:
1188 case Intrinsic::mips_sll_d:
1189 return lowerMSABinaryIntr(Op, DAG, ISD::SHL);
1190 case Intrinsic::mips_slli_b:
1191 case Intrinsic::mips_slli_h:
1192 case Intrinsic::mips_slli_w:
1193 case Intrinsic::mips_slli_d:
1194 return lowerMSABinaryImmIntr(Op, DAG, ISD::SHL,
1195 lowerMSASplatImm(Op, 2, DAG));
1196 case Intrinsic::mips_sra_b:
1197 case Intrinsic::mips_sra_h:
1198 case Intrinsic::mips_sra_w:
1199 case Intrinsic::mips_sra_d:
1200 return lowerMSABinaryIntr(Op, DAG, ISD::SRA);
1201 case Intrinsic::mips_srai_b:
1202 case Intrinsic::mips_srai_h:
1203 case Intrinsic::mips_srai_w:
1204 case Intrinsic::mips_srai_d:
1205 return lowerMSABinaryImmIntr(Op, DAG, ISD::SRA,
1206 lowerMSASplatImm(Op, 2, DAG));
1207 case Intrinsic::mips_srl_b:
1208 case Intrinsic::mips_srl_h:
1209 case Intrinsic::mips_srl_w:
1210 case Intrinsic::mips_srl_d:
1211 return lowerMSABinaryIntr(Op, DAG, ISD::SRL);
1212 case Intrinsic::mips_srli_b:
1213 case Intrinsic::mips_srli_h:
1214 case Intrinsic::mips_srli_w:
1215 case Intrinsic::mips_srli_d:
1216 return lowerMSABinaryImmIntr(Op, DAG, ISD::SRL,
1217 lowerMSASplatImm(Op, 2, DAG));
1218 case Intrinsic::mips_subv_b:
1219 case Intrinsic::mips_subv_h:
1220 case Intrinsic::mips_subv_w:
1221 case Intrinsic::mips_subv_d:
1222 return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
1223 case Intrinsic::mips_subvi_b:
1224 case Intrinsic::mips_subvi_h:
1225 case Intrinsic::mips_subvi_w:
1226 case Intrinsic::mips_subvi_d:
1227 return lowerMSABinaryImmIntr(Op, DAG, ISD::SUB,
1228 lowerMSASplatImm(Op, 2, DAG));
1229 case Intrinsic::mips_xor_v:
1230 return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
1234 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1236 SDValue ChainIn = Op->getOperand(0);
1237 SDValue Address = Op->getOperand(2);
1238 SDValue Offset = Op->getOperand(3);
1239 EVT ResTy = Op->getValueType(0);
1240 EVT PtrTy = Address->getValueType(0);
1242 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1244 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1248 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1249 SelectionDAG &DAG) const {
1250 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1254 case Intrinsic::mips_extp:
1255 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1256 case Intrinsic::mips_extpdp:
1257 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1258 case Intrinsic::mips_extr_w:
1259 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1260 case Intrinsic::mips_extr_r_w:
1261 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1262 case Intrinsic::mips_extr_rs_w:
1263 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1264 case Intrinsic::mips_extr_s_h:
1265 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1266 case Intrinsic::mips_mthlip:
1267 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1268 case Intrinsic::mips_mulsaq_s_w_ph:
1269 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1270 case Intrinsic::mips_maq_s_w_phl:
1271 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1272 case Intrinsic::mips_maq_s_w_phr:
1273 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1274 case Intrinsic::mips_maq_sa_w_phl:
1275 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1276 case Intrinsic::mips_maq_sa_w_phr:
1277 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1278 case Intrinsic::mips_dpaq_s_w_ph:
1279 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1280 case Intrinsic::mips_dpsq_s_w_ph:
1281 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1282 case Intrinsic::mips_dpaq_sa_l_w:
1283 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1284 case Intrinsic::mips_dpsq_sa_l_w:
1285 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1286 case Intrinsic::mips_dpaqx_s_w_ph:
1287 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1288 case Intrinsic::mips_dpaqx_sa_w_ph:
1289 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1290 case Intrinsic::mips_dpsqx_s_w_ph:
1291 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1292 case Intrinsic::mips_dpsqx_sa_w_ph:
1293 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1294 case Intrinsic::mips_ld_b:
1295 case Intrinsic::mips_ld_h:
1296 case Intrinsic::mips_ld_w:
1297 case Intrinsic::mips_ld_d:
1298 case Intrinsic::mips_ldx_b:
1299 case Intrinsic::mips_ldx_h:
1300 case Intrinsic::mips_ldx_w:
1301 case Intrinsic::mips_ldx_d:
1302 return lowerMSALoadIntr(Op, DAG, Intr);
1306 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1308 SDValue ChainIn = Op->getOperand(0);
1309 SDValue Value = Op->getOperand(2);
1310 SDValue Address = Op->getOperand(3);
1311 SDValue Offset = Op->getOperand(4);
1312 EVT PtrTy = Address->getValueType(0);
1314 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1316 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1320 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1321 SelectionDAG &DAG) const {
1322 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1326 case Intrinsic::mips_st_b:
1327 case Intrinsic::mips_st_h:
1328 case Intrinsic::mips_st_w:
1329 case Intrinsic::mips_st_d:
1330 case Intrinsic::mips_stx_b:
1331 case Intrinsic::mips_stx_h:
1332 case Intrinsic::mips_stx_w:
1333 case Intrinsic::mips_stx_d:
1334 return lowerMSAStoreIntr(Op, DAG, Intr);
1338 /// \brief Check if the given BuildVectorSDNode is a splat.
1339 /// This method currently relies on DAG nodes being reused when equivalent,
1340 /// so it's possible for this to return false even when isConstantSplat returns
1342 static bool isSplatVector(const BuildVectorSDNode *N) {
1343 unsigned int nOps = N->getNumOperands();
1344 assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1346 SDValue Operand0 = N->getOperand(0);
1348 for (unsigned int i = 1; i < nOps; ++i) {
1349 if (N->getOperand(i) != Operand0)
1356 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
1358 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
1359 // choose to sign-extend but we could have equally chosen zero-extend. The
1360 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
1361 // result into this node later (possibly changing it to a zero-extend in the
1363 SDValue MipsSETargetLowering::
1364 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
1366 EVT ResTy = Op->getValueType(0);
1367 SDValue Op0 = Op->getOperand(0);
1368 SDValue Op1 = Op->getOperand(1);
1369 EVT EltTy = Op0->getValueType(0).getVectorElementType();
1370 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
1371 DAG.getValueType(EltTy));
1374 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1377 // Lowers according to the following rules:
1378 // - Vectors of 128-bits may be legal subject to the other rules. Other sizes
1380 // - Non-constant splats are legal and are lowered to MipsISD::VSPLAT.
1381 // - Constant splats with an element size of 32-bits or less are legal and are
1382 // lowered to MipsISD::VSPLAT.
1383 // - Constant splats with an element size of 64-bits but whose value would fit
1384 // within a 10 bit immediate are legal and are lowered to MipsISD::VSPLATD.
1385 // - All other ISD::BUILD_VECTORS are not legal
1386 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1387 SelectionDAG &DAG) const {
1388 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1389 EVT ResTy = Op->getValueType(0);
1391 APInt SplatValue, SplatUndef;
1392 unsigned SplatBitSize;
1395 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1398 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1400 !Subtarget->isLittle())) {
1403 EVT ConstTy = MVT::i32;
1404 unsigned SplatOp = MipsISD::VSPLAT;
1406 switch (SplatBitSize) {
1410 TmpVecTy = MVT::v2i64;
1412 // i64 is an illegal type on Mips32, but if it the constant fits into a
1413 // signed 10-bit value then we can still handle it using VSPLATD and an
1417 else if (isInt<10>(SplatValue.getSExtValue())) {
1418 SplatValue = SplatValue.trunc(32);
1419 SplatOp = MipsISD::VSPLATD;
1424 TmpVecTy = MVT::v4i32;
1427 TmpVecTy = MVT::v8i16;
1428 SplatValue = SplatValue.sext(32);
1431 TmpVecTy = MVT::v16i8;
1432 SplatValue = SplatValue.sext(32);
1436 Result = DAG.getNode(SplatOp, DL, TmpVecTy,
1437 DAG.getConstant(SplatValue, ConstTy));
1438 if (ResTy != Result.getValueType())
1439 Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1443 else if (isSplatVector(Node))
1444 return DAG.getNode(MipsISD::VSPLAT, DL, ResTy, Op->getOperand(0));
1449 MachineBasicBlock * MipsSETargetLowering::
1450 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1452 // bposge32_pseudo $vr0
1462 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1464 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1465 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1466 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1467 DebugLoc DL = MI->getDebugLoc();
1468 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1469 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1470 MachineFunction *F = BB->getParent();
1471 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1472 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1473 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1476 F->insert(It, Sink);
1478 // Transfer the remainder of BB and its successor edges to Sink.
1479 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1481 Sink->transferSuccessorsAndUpdatePHIs(BB);
1484 BB->addSuccessor(FBB);
1485 BB->addSuccessor(TBB);
1486 FBB->addSuccessor(Sink);
1487 TBB->addSuccessor(Sink);
1489 // Insert the real bposge32 instruction to $BB.
1490 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1493 unsigned VR2 = RegInfo.createVirtualRegister(RC);
1494 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1495 .addReg(Mips::ZERO).addImm(0);
1496 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1499 unsigned VR1 = RegInfo.createVirtualRegister(RC);
1500 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1501 .addReg(Mips::ZERO).addImm(1);
1503 // Insert phi function to $Sink.
1504 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1505 MI->getOperand(0).getReg())
1506 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1508 MI->eraseFromParent(); // The pseudo instruction is gone now.
1512 MachineBasicBlock * MipsSETargetLowering::
1513 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
1514 unsigned BranchOp) const{
1516 // vany_nonzero $rd, $ws
1527 // $rd = phi($rd1, $fbb, $rd2, $tbb)
1529 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1530 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1531 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1532 DebugLoc DL = MI->getDebugLoc();
1533 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1534 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1535 MachineFunction *F = BB->getParent();
1536 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1537 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1538 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1541 F->insert(It, Sink);
1543 // Transfer the remainder of BB and its successor edges to Sink.
1544 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1546 Sink->transferSuccessorsAndUpdatePHIs(BB);
1549 BB->addSuccessor(FBB);
1550 BB->addSuccessor(TBB);
1551 FBB->addSuccessor(Sink);
1552 TBB->addSuccessor(Sink);
1554 // Insert the real bnz.b instruction to $BB.
1555 BuildMI(BB, DL, TII->get(BranchOp))
1556 .addReg(MI->getOperand(1).getReg())
1560 unsigned RD1 = RegInfo.createVirtualRegister(RC);
1561 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
1562 .addReg(Mips::ZERO).addImm(0);
1563 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1566 unsigned RD2 = RegInfo.createVirtualRegister(RC);
1567 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
1568 .addReg(Mips::ZERO).addImm(1);
1570 // Insert phi function to $Sink.
1571 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1572 MI->getOperand(0).getReg())
1573 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
1575 MI->eraseFromParent(); // The pseudo instruction is gone now.