1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsRegisterInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26 cl::desc("MIPS: Enable tail calls."), cl::init(false));
28 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29 cl::desc("Expand double precision loads and "
30 "stores to their single precision "
33 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34 : MipsTargetLowering(TM) {
35 // Set up the register classes
37 clearRegisterClasses();
39 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
42 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
44 if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
45 // Expand all truncating stores and extending loads.
46 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
47 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
49 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
50 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
51 setTruncStoreAction((MVT::SimpleValueType)VT0,
52 (MVT::SimpleValueType)VT1, Expand);
54 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
55 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
60 if (Subtarget->hasDSP()) {
61 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
63 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
64 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
66 // Expand all builtin opcodes.
67 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
68 setOperationAction(Opc, VecTys[i], Expand);
70 setOperationAction(ISD::ADD, VecTys[i], Legal);
71 setOperationAction(ISD::SUB, VecTys[i], Legal);
72 setOperationAction(ISD::LOAD, VecTys[i], Legal);
73 setOperationAction(ISD::STORE, VecTys[i], Legal);
74 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
77 setTargetDAGCombine(ISD::SHL);
78 setTargetDAGCombine(ISD::SRA);
79 setTargetDAGCombine(ISD::SRL);
80 setTargetDAGCombine(ISD::SETCC);
81 setTargetDAGCombine(ISD::VSELECT);
84 if (Subtarget->hasDSPR2())
85 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
87 if (Subtarget->hasMSA()) {
88 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
89 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
90 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
91 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
92 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
93 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
94 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
96 setTargetDAGCombine(ISD::AND);
97 setTargetDAGCombine(ISD::SRA);
98 setTargetDAGCombine(ISD::VSELECT);
99 setTargetDAGCombine(ISD::XOR);
102 if (!Subtarget->mipsSEUsesSoftFloat()) {
103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
105 // When dealing with single precision only, use libcalls
106 if (!Subtarget->isSingleFloat()) {
107 if (Subtarget->isFP64bit())
108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
114 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
115 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
116 setOperationAction(ISD::MULHS, MVT::i32, Custom);
117 setOperationAction(ISD::MULHU, MVT::i32, Custom);
120 setOperationAction(ISD::MULHS, MVT::i64, Custom);
121 setOperationAction(ISD::MULHU, MVT::i64, Custom);
122 setOperationAction(ISD::MUL, MVT::i64, Custom);
125 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
126 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
128 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
129 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
130 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
131 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
132 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
133 setOperationAction(ISD::LOAD, MVT::i32, Custom);
134 setOperationAction(ISD::STORE, MVT::i32, Custom);
136 setTargetDAGCombine(ISD::ADDE);
137 setTargetDAGCombine(ISD::SUBE);
138 setTargetDAGCombine(ISD::MUL);
140 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
141 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
142 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
145 setOperationAction(ISD::LOAD, MVT::f64, Custom);
146 setOperationAction(ISD::STORE, MVT::f64, Custom);
149 computeRegisterProperties();
152 const MipsTargetLowering *
153 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
154 return new MipsSETargetLowering(TM);
157 // Enable MSA support for the given integer type and Register class.
158 void MipsSETargetLowering::
159 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
160 addRegisterClass(Ty, RC);
162 // Expand all builtin opcodes.
163 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
164 setOperationAction(Opc, Ty, Expand);
166 setOperationAction(ISD::BITCAST, Ty, Legal);
167 setOperationAction(ISD::LOAD, Ty, Legal);
168 setOperationAction(ISD::STORE, Ty, Legal);
169 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
170 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
171 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
173 setOperationAction(ISD::ADD, Ty, Legal);
174 setOperationAction(ISD::AND, Ty, Legal);
175 setOperationAction(ISD::CTLZ, Ty, Legal);
176 setOperationAction(ISD::CTPOP, Ty, Legal);
177 setOperationAction(ISD::MUL, Ty, Legal);
178 setOperationAction(ISD::OR, Ty, Legal);
179 setOperationAction(ISD::SDIV, Ty, Legal);
180 setOperationAction(ISD::SREM, Ty, Legal);
181 setOperationAction(ISD::SHL, Ty, Legal);
182 setOperationAction(ISD::SRA, Ty, Legal);
183 setOperationAction(ISD::SRL, Ty, Legal);
184 setOperationAction(ISD::SUB, Ty, Legal);
185 setOperationAction(ISD::UDIV, Ty, Legal);
186 setOperationAction(ISD::UREM, Ty, Legal);
187 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
188 setOperationAction(ISD::VSELECT, Ty, Legal);
189 setOperationAction(ISD::XOR, Ty, Legal);
191 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
192 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
193 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
194 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
195 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
198 setOperationAction(ISD::SETCC, Ty, Legal);
199 setCondCodeAction(ISD::SETNE, Ty, Expand);
200 setCondCodeAction(ISD::SETGE, Ty, Expand);
201 setCondCodeAction(ISD::SETGT, Ty, Expand);
202 setCondCodeAction(ISD::SETUGE, Ty, Expand);
203 setCondCodeAction(ISD::SETUGT, Ty, Expand);
206 // Enable MSA support for the given floating-point type and Register class.
207 void MipsSETargetLowering::
208 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
209 addRegisterClass(Ty, RC);
211 // Expand all builtin opcodes.
212 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
213 setOperationAction(Opc, Ty, Expand);
215 setOperationAction(ISD::LOAD, Ty, Legal);
216 setOperationAction(ISD::STORE, Ty, Legal);
217 setOperationAction(ISD::BITCAST, Ty, Legal);
218 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
219 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
221 if (Ty != MVT::v8f16) {
222 setOperationAction(ISD::FABS, Ty, Legal);
223 setOperationAction(ISD::FADD, Ty, Legal);
224 setOperationAction(ISD::FDIV, Ty, Legal);
225 setOperationAction(ISD::FLOG2, Ty, Legal);
226 setOperationAction(ISD::FMA, Ty, Legal);
227 setOperationAction(ISD::FMUL, Ty, Legal);
228 setOperationAction(ISD::FRINT, Ty, Legal);
229 setOperationAction(ISD::FSQRT, Ty, Legal);
230 setOperationAction(ISD::FSUB, Ty, Legal);
231 setOperationAction(ISD::VSELECT, Ty, Legal);
233 setOperationAction(ISD::SETCC, Ty, Legal);
234 setCondCodeAction(ISD::SETOGE, Ty, Expand);
235 setCondCodeAction(ISD::SETOGT, Ty, Expand);
236 setCondCodeAction(ISD::SETUGE, Ty, Expand);
237 setCondCodeAction(ISD::SETUGT, Ty, Expand);
238 setCondCodeAction(ISD::SETGE, Ty, Expand);
239 setCondCodeAction(ISD::SETGT, Ty, Expand);
244 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
245 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
258 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
259 SelectionDAG &DAG) const {
260 switch(Op.getOpcode()) {
261 case ISD::LOAD: return lowerLOAD(Op, DAG);
262 case ISD::STORE: return lowerSTORE(Op, DAG);
263 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
264 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
265 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
266 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
267 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
268 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
269 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
271 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
272 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
273 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
274 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
275 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
276 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
279 return MipsTargetLowering::LowerOperation(Op, DAG);
283 // Transforms a subgraph in CurDAG if the following pattern is found:
284 // (addc multLo, Lo0), (adde multHi, Hi0),
286 // multHi/Lo: product of multiplication
287 // Lo0: initial value of Lo register
288 // Hi0: initial value of Hi register
289 // Return true if pattern matching was successful.
290 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
291 // ADDENode's second operand must be a flag output of an ADDC node in order
292 // for the matching to be successful.
293 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
295 if (ADDCNode->getOpcode() != ISD::ADDC)
298 SDValue MultHi = ADDENode->getOperand(0);
299 SDValue MultLo = ADDCNode->getOperand(0);
300 SDNode *MultNode = MultHi.getNode();
301 unsigned MultOpc = MultHi.getOpcode();
303 // MultHi and MultLo must be generated by the same node,
304 if (MultLo.getNode() != MultNode)
307 // and it must be a multiplication.
308 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
311 // MultLo amd MultHi must be the first and second output of MultNode
313 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
316 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
317 // of the values of MultNode, in which case MultNode will be removed in later
319 // If there exist users other than ADDENode or ADDCNode, this function returns
320 // here, which will result in MultNode being mapped to a single MULT
321 // instruction node rather than a pair of MULT and MADD instructions being
323 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
328 // Initialize accumulator.
329 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
330 ADDCNode->getOperand(1),
331 ADDENode->getOperand(1));
333 // create MipsMAdd(u) node
334 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
336 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
337 MultNode->getOperand(0),// Factor 0
338 MultNode->getOperand(1),// Factor 1
341 // replace uses of adde and addc here
342 if (!SDValue(ADDCNode, 0).use_empty()) {
343 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLO, DL, MVT::i32, MAdd);
344 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
346 if (!SDValue(ADDENode, 0).use_empty()) {
347 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractHI, DL, MVT::i32, MAdd);
348 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
355 // Transforms a subgraph in CurDAG if the following pattern is found:
356 // (addc Lo0, multLo), (sube Hi0, multHi),
358 // multHi/Lo: product of multiplication
359 // Lo0: initial value of Lo register
360 // Hi0: initial value of Hi register
361 // Return true if pattern matching was successful.
362 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
363 // SUBENode's second operand must be a flag output of an SUBC node in order
364 // for the matching to be successful.
365 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
367 if (SUBCNode->getOpcode() != ISD::SUBC)
370 SDValue MultHi = SUBENode->getOperand(1);
371 SDValue MultLo = SUBCNode->getOperand(1);
372 SDNode *MultNode = MultHi.getNode();
373 unsigned MultOpc = MultHi.getOpcode();
375 // MultHi and MultLo must be generated by the same node,
376 if (MultLo.getNode() != MultNode)
379 // and it must be a multiplication.
380 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
383 // MultLo amd MultHi must be the first and second output of MultNode
385 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
388 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
389 // of the values of MultNode, in which case MultNode will be removed in later
391 // If there exist users other than SUBENode or SUBCNode, this function returns
392 // here, which will result in MultNode being mapped to a single MULT
393 // instruction node rather than a pair of MULT and MSUB instructions being
395 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
400 // Initialize accumulator.
401 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
402 SUBCNode->getOperand(0),
403 SUBENode->getOperand(0));
405 // create MipsSub(u) node
406 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
408 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
409 MultNode->getOperand(0),// Factor 0
410 MultNode->getOperand(1),// Factor 1
413 // replace uses of sube and subc here
414 if (!SDValue(SUBCNode, 0).use_empty()) {
415 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLO, DL, MVT::i32, MSub);
416 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
418 if (!SDValue(SUBENode, 0).use_empty()) {
419 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractHI, DL, MVT::i32, MSub);
420 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
426 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
427 TargetLowering::DAGCombinerInfo &DCI,
428 const MipsSubtarget *Subtarget) {
429 if (DCI.isBeforeLegalize())
432 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
434 return SDValue(N, 0);
439 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
441 // Performs the following transformations:
442 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
443 // sign/zero-extension is completely overwritten by the new one performed by
445 // - Removes redundant zero extensions performed by an ISD::AND.
446 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
447 TargetLowering::DAGCombinerInfo &DCI,
448 const MipsSubtarget *Subtarget) {
449 if (!Subtarget->hasMSA())
452 SDValue Op0 = N->getOperand(0);
453 SDValue Op1 = N->getOperand(1);
454 unsigned Op0Opcode = Op0->getOpcode();
456 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
457 // where $d + 1 == 2^n and n == 32
458 // or $d + 1 == 2^n and n <= 32 and ZExt
459 // -> (MipsVExtractZExt $a, $b, $c)
460 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
461 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
462 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
467 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
469 if (Log2IfPositive <= 0)
470 return SDValue(); // Mask+1 is not a power of 2
472 SDValue Op0Op2 = Op0->getOperand(2);
473 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
474 unsigned ExtendTySize = ExtendTy.getSizeInBits();
475 unsigned Log2 = Log2IfPositive;
477 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
478 Log2 == ExtendTySize) {
479 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
480 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
481 Op0->getVTList(), Ops, Op0->getNumOperands());
489 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
490 TargetLowering::DAGCombinerInfo &DCI,
491 const MipsSubtarget *Subtarget) {
492 if (DCI.isBeforeLegalize())
495 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
497 return SDValue(N, 0);
502 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
503 EVT ShiftTy, SelectionDAG &DAG) {
504 // Clear the upper (64 - VT.sizeInBits) bits.
505 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
509 return DAG.getConstant(0, VT);
515 // If c is power of 2, return (shl x, log2(c)).
516 if (isPowerOf2_64(C))
517 return DAG.getNode(ISD::SHL, DL, VT, X,
518 DAG.getConstant(Log2_64(C), ShiftTy));
520 unsigned Log2Ceil = Log2_64_Ceil(C);
521 uint64_t Floor = 1LL << Log2_64(C);
522 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
524 // If |c - floor_c| <= |c - ceil_c|,
525 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
526 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
527 if (C - Floor <= Ceil - C) {
528 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
529 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
530 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
533 // If |c - floor_c| > |c - ceil_c|,
534 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
535 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
536 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
537 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
540 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
541 const TargetLowering::DAGCombinerInfo &DCI,
542 const MipsSETargetLowering *TL) {
543 EVT VT = N->getValueType(0);
545 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
547 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
548 VT, TL->getScalarShiftAmountTy(VT), DAG);
550 return SDValue(N, 0);
553 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
555 const MipsSubtarget *Subtarget) {
556 // See if this is a vector splat immediate node.
557 APInt SplatValue, SplatUndef;
558 unsigned SplatBitSize;
560 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
561 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
564 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
565 EltSize, !Subtarget->isLittle()) ||
566 (SplatBitSize != EltSize) ||
567 (SplatValue.getZExtValue() >= EltSize))
570 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
571 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
574 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
575 TargetLowering::DAGCombinerInfo &DCI,
576 const MipsSubtarget *Subtarget) {
577 EVT Ty = N->getValueType(0);
579 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
582 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
585 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
586 // constant splats into MipsISD::SHRA_DSP for DSPr2.
588 // Performs the following transformations:
589 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
590 // sign/zero-extension is completely overwritten by the new one performed by
591 // the ISD::SRA and ISD::SHL nodes.
592 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
595 // See performDSPShiftCombine for more information about the transformation
597 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
598 TargetLowering::DAGCombinerInfo &DCI,
599 const MipsSubtarget *Subtarget) {
600 EVT Ty = N->getValueType(0);
602 if (Subtarget->hasMSA()) {
603 SDValue Op0 = N->getOperand(0);
604 SDValue Op1 = N->getOperand(1);
606 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
607 // where $d + sizeof($c) == 32
608 // or $d + sizeof($c) <= 32 and SExt
609 // -> (MipsVExtractSExt $a, $b, $c)
610 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
611 SDValue Op0Op0 = Op0->getOperand(0);
612 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
617 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
618 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
621 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
622 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
624 if (TotalBits == 32 ||
625 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
627 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
628 Op0Op0->getOperand(2) };
629 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
630 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
636 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
639 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
643 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
644 TargetLowering::DAGCombinerInfo &DCI,
645 const MipsSubtarget *Subtarget) {
646 EVT Ty = N->getValueType(0);
648 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
651 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
654 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
655 bool IsV216 = (Ty == MVT::v2i16);
659 case ISD::SETNE: return true;
663 case ISD::SETGE: return IsV216;
667 case ISD::SETUGE: return !IsV216;
668 default: return false;
672 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
673 EVT Ty = N->getValueType(0);
675 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
678 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
681 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
682 N->getOperand(1), N->getOperand(2));
685 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
686 EVT Ty = N->getValueType(0);
688 if (Ty.is128BitVector() && Ty.isInteger()) {
689 // Try the following combines:
690 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
691 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
692 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
693 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
694 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
695 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
696 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
697 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
698 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
699 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
701 SDValue Op0 = N->getOperand(0);
703 if (Op0->getOpcode() != ISD::SETCC)
706 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
709 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
711 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
716 SDValue Op1 = N->getOperand(1);
717 SDValue Op2 = N->getOperand(2);
718 SDValue Op0Op0 = Op0->getOperand(0);
719 SDValue Op0Op1 = Op0->getOperand(1);
721 if (Op1 == Op0Op0 && Op2 == Op0Op1)
722 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
724 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
725 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
727 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
728 SDValue SetCC = N->getOperand(0);
730 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
733 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
734 SetCC.getOperand(0), SetCC.getOperand(1),
735 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
741 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
742 const MipsSubtarget *Subtarget) {
743 EVT Ty = N->getValueType(0);
745 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
746 // Try the following combines:
747 // (xor (or $a, $b), (build_vector allones))
748 // (xor (or $a, $b), (bitcast (build_vector allones)))
749 SDValue Op0 = N->getOperand(0);
750 SDValue Op1 = N->getOperand(1);
753 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
755 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
760 if (NotOp->getOpcode() == ISD::OR)
761 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
762 NotOp->getOperand(1));
769 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
770 SelectionDAG &DAG = DCI.DAG;
773 switch (N->getOpcode()) {
775 return performADDECombine(N, DAG, DCI, Subtarget);
777 Val = performANDCombine(N, DAG, DCI, Subtarget);
780 return performSUBECombine(N, DAG, DCI, Subtarget);
782 return performMULCombine(N, DAG, DCI, this);
784 return performSHLCombine(N, DAG, DCI, Subtarget);
786 return performSRACombine(N, DAG, DCI, Subtarget);
788 return performSRLCombine(N, DAG, DCI, Subtarget);
790 return performVSELECTCombine(N, DAG);
792 Val = performXORCombine(N, DAG, Subtarget);
795 Val = performSETCCCombine(N, DAG);
802 return MipsTargetLowering::PerformDAGCombine(N, DCI);
806 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
807 MachineBasicBlock *BB) const {
808 switch (MI->getOpcode()) {
810 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
811 case Mips::BPOSGE32_PSEUDO:
812 return emitBPOSGE32(MI, BB);
813 case Mips::SNZ_B_PSEUDO:
814 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
815 case Mips::SNZ_H_PSEUDO:
816 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
817 case Mips::SNZ_W_PSEUDO:
818 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
819 case Mips::SNZ_D_PSEUDO:
820 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
821 case Mips::SNZ_V_PSEUDO:
822 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
823 case Mips::SZ_B_PSEUDO:
824 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
825 case Mips::SZ_H_PSEUDO:
826 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
827 case Mips::SZ_W_PSEUDO:
828 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
829 case Mips::SZ_D_PSEUDO:
830 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
831 case Mips::SZ_V_PSEUDO:
832 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
833 case Mips::COPY_FW_PSEUDO:
834 return emitCOPY_FW(MI, BB);
835 case Mips::COPY_FD_PSEUDO:
836 return emitCOPY_FD(MI, BB);
837 case Mips::INSERT_FW_PSEUDO:
838 return emitINSERT_FW(MI, BB);
839 case Mips::INSERT_FD_PSEUDO:
840 return emitINSERT_FD(MI, BB);
844 bool MipsSETargetLowering::
845 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
846 unsigned NextStackOffset,
847 const MipsFunctionInfo& FI) const {
848 if (!EnableMipsTailCalls)
851 // Return false if either the callee or caller has a byval argument.
852 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
855 // Return true if the callee's argument area is no larger than the
857 return NextStackOffset <= FI.getIncomingArgSize();
860 void MipsSETargetLowering::
861 getOpndList(SmallVectorImpl<SDValue> &Ops,
862 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
863 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
864 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
865 // T9 should contain the address of the callee function if
866 // -reloction-model=pic or it is an indirect call.
867 if (IsPICCall || !GlobalOrExternal) {
868 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
869 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
871 Ops.push_back(Callee);
873 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
874 InternalLinkage, CLI, Callee, Chain);
877 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
878 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
880 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
881 return MipsTargetLowering::lowerLOAD(Op, DAG);
883 // Replace a double precision load with two i32 loads and a buildpair64.
885 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
886 EVT PtrVT = Ptr.getValueType();
888 // i32 load from lower address.
889 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
890 MachinePointerInfo(), Nd.isVolatile(),
891 Nd.isNonTemporal(), Nd.isInvariant(),
894 // i32 load from higher address.
895 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
896 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
897 MachinePointerInfo(), Nd.isVolatile(),
898 Nd.isNonTemporal(), Nd.isInvariant(),
899 std::min(Nd.getAlignment(), 4U));
901 if (!Subtarget->isLittle())
904 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
905 SDValue Ops[2] = {BP, Hi.getValue(1)};
906 return DAG.getMergeValues(Ops, 2, DL);
909 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
910 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
912 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
913 return MipsTargetLowering::lowerSTORE(Op, DAG);
915 // Replace a double precision store with two extractelement64s and i32 stores.
917 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
918 EVT PtrVT = Ptr.getValueType();
919 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
920 Val, DAG.getConstant(0, MVT::i32));
921 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
922 Val, DAG.getConstant(1, MVT::i32));
924 if (!Subtarget->isLittle())
927 // i32 store to lower address.
928 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
929 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
932 // i32 store to higher address.
933 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
934 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
935 Nd.isVolatile(), Nd.isNonTemporal(),
936 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
939 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
940 bool HasLo, bool HasHi,
941 SelectionDAG &DAG) const {
942 EVT Ty = Op.getOperand(0).getValueType();
944 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
945 Op.getOperand(0), Op.getOperand(1));
949 Lo = DAG.getNode(MipsISD::ExtractLO, DL, Ty, Mult);
951 Hi = DAG.getNode(MipsISD::ExtractHI, DL, Ty, Mult);
953 if (!HasLo || !HasHi)
954 return HasLo ? Lo : Hi;
956 SDValue Vals[] = { Lo, Hi };
957 return DAG.getMergeValues(Vals, 2, DL);
961 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
962 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
963 DAG.getConstant(0, MVT::i32));
964 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
965 DAG.getConstant(1, MVT::i32));
966 return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
969 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
970 SDValue Lo = DAG.getNode(MipsISD::ExtractLO, DL, MVT::i32, Op);
971 SDValue Hi = DAG.getNode(MipsISD::ExtractHI, DL, MVT::i32, Op);
972 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
975 // This function expands mips intrinsic nodes which have 64-bit input operands
978 // out64 = intrinsic-node in64
980 // lo = copy (extract-element (in64, 0))
981 // hi = copy (extract-element (in64, 1))
982 // mips-specific-node
985 // out64 = merge-values (v0, v1)
987 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
989 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
990 SmallVector<SDValue, 3> Ops;
993 // See if Op has a chain input.
995 Ops.push_back(Op->getOperand(OpNo++));
997 // The next operand is the intrinsic opcode.
998 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1000 // See if the next operand has type i64.
1001 SDValue Opnd = Op->getOperand(++OpNo), In64;
1003 if (Opnd.getValueType() == MVT::i64)
1004 In64 = initAccumulator(Opnd, DL, DAG);
1006 Ops.push_back(Opnd);
1008 // Push the remaining operands.
1009 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1010 Ops.push_back(Op->getOperand(OpNo));
1012 // Add In64 to the end of the list.
1014 Ops.push_back(In64);
1017 SmallVector<EVT, 2> ResTys;
1019 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1021 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1024 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1025 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1030 assert(Val->getValueType(1) == MVT::Other);
1031 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1032 return DAG.getMergeValues(Vals, 2, DL);
1035 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1036 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1038 SDValue Vec = Op->getOperand(1);
1039 SDValue Idx = Op->getOperand(2);
1040 EVT ResTy = Op->getValueType(0);
1041 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1043 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1044 DAG.getValueType(EltTy));
1050 lowerMSASplatImm(SDLoc DL, EVT ResTy, SDValue ImmOp, SelectionDAG &DAG) {
1051 EVT ViaVecTy = ResTy;
1052 SmallVector<SDValue, 16> Ops;
1055 if (ViaVecTy == MVT::v2i64) {
1056 ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp,
1057 DAG.getConstant(31, MVT::i32));
1058 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) {
1059 Ops.push_back(ImmHiOp);
1060 Ops.push_back(ImmOp);
1062 ViaVecTy = MVT::v4i32;
1064 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1065 Ops.push_back(ImmOp);
1068 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0],
1071 if (ResTy != ViaVecTy)
1072 Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1078 lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1079 return lowerMSASplatImm(SDLoc(Op), Op->getValueType(0),
1080 Op->getOperand(ImmOp), DAG);
1083 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1084 SelectionDAG &DAG) const {
1087 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1090 case Intrinsic::mips_shilo:
1091 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1092 case Intrinsic::mips_dpau_h_qbl:
1093 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1094 case Intrinsic::mips_dpau_h_qbr:
1095 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1096 case Intrinsic::mips_dpsu_h_qbl:
1097 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1098 case Intrinsic::mips_dpsu_h_qbr:
1099 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1100 case Intrinsic::mips_dpa_w_ph:
1101 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1102 case Intrinsic::mips_dps_w_ph:
1103 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1104 case Intrinsic::mips_dpax_w_ph:
1105 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1106 case Intrinsic::mips_dpsx_w_ph:
1107 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1108 case Intrinsic::mips_mulsa_w_ph:
1109 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1110 case Intrinsic::mips_mult:
1111 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1112 case Intrinsic::mips_multu:
1113 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1114 case Intrinsic::mips_madd:
1115 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1116 case Intrinsic::mips_maddu:
1117 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1118 case Intrinsic::mips_msub:
1119 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1120 case Intrinsic::mips_msubu:
1121 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1122 case Intrinsic::mips_addv_b:
1123 case Intrinsic::mips_addv_h:
1124 case Intrinsic::mips_addv_w:
1125 case Intrinsic::mips_addv_d:
1126 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1128 case Intrinsic::mips_addvi_b:
1129 case Intrinsic::mips_addvi_h:
1130 case Intrinsic::mips_addvi_w:
1131 case Intrinsic::mips_addvi_d:
1132 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1133 lowerMSASplatImm(Op, 2, DAG));
1134 case Intrinsic::mips_and_v:
1135 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1137 case Intrinsic::mips_andi_b:
1138 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1139 lowerMSASplatImm(Op, 2, DAG));
1140 case Intrinsic::mips_bnz_b:
1141 case Intrinsic::mips_bnz_h:
1142 case Intrinsic::mips_bnz_w:
1143 case Intrinsic::mips_bnz_d:
1144 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1146 case Intrinsic::mips_bnz_v:
1147 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1149 case Intrinsic::mips_bsel_v:
1150 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1151 Op->getOperand(1), Op->getOperand(2),
1153 case Intrinsic::mips_bseli_b:
1154 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1155 Op->getOperand(1), Op->getOperand(2),
1156 lowerMSASplatImm(Op, 3, DAG));
1157 case Intrinsic::mips_bz_b:
1158 case Intrinsic::mips_bz_h:
1159 case Intrinsic::mips_bz_w:
1160 case Intrinsic::mips_bz_d:
1161 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1163 case Intrinsic::mips_bz_v:
1164 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1166 case Intrinsic::mips_ceq_b:
1167 case Intrinsic::mips_ceq_h:
1168 case Intrinsic::mips_ceq_w:
1169 case Intrinsic::mips_ceq_d:
1170 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1171 Op->getOperand(2), ISD::SETEQ);
1172 case Intrinsic::mips_ceqi_b:
1173 case Intrinsic::mips_ceqi_h:
1174 case Intrinsic::mips_ceqi_w:
1175 case Intrinsic::mips_ceqi_d:
1176 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1177 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1178 case Intrinsic::mips_cle_s_b:
1179 case Intrinsic::mips_cle_s_h:
1180 case Intrinsic::mips_cle_s_w:
1181 case Intrinsic::mips_cle_s_d:
1182 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1183 Op->getOperand(2), ISD::SETLE);
1184 case Intrinsic::mips_clei_s_b:
1185 case Intrinsic::mips_clei_s_h:
1186 case Intrinsic::mips_clei_s_w:
1187 case Intrinsic::mips_clei_s_d:
1188 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1189 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1190 case Intrinsic::mips_cle_u_b:
1191 case Intrinsic::mips_cle_u_h:
1192 case Intrinsic::mips_cle_u_w:
1193 case Intrinsic::mips_cle_u_d:
1194 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1195 Op->getOperand(2), ISD::SETULE);
1196 case Intrinsic::mips_clei_u_b:
1197 case Intrinsic::mips_clei_u_h:
1198 case Intrinsic::mips_clei_u_w:
1199 case Intrinsic::mips_clei_u_d:
1200 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1201 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1202 case Intrinsic::mips_clt_s_b:
1203 case Intrinsic::mips_clt_s_h:
1204 case Intrinsic::mips_clt_s_w:
1205 case Intrinsic::mips_clt_s_d:
1206 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1207 Op->getOperand(2), ISD::SETLT);
1208 case Intrinsic::mips_clti_s_b:
1209 case Intrinsic::mips_clti_s_h:
1210 case Intrinsic::mips_clti_s_w:
1211 case Intrinsic::mips_clti_s_d:
1212 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1213 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1214 case Intrinsic::mips_clt_u_b:
1215 case Intrinsic::mips_clt_u_h:
1216 case Intrinsic::mips_clt_u_w:
1217 case Intrinsic::mips_clt_u_d:
1218 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1219 Op->getOperand(2), ISD::SETULT);
1220 case Intrinsic::mips_clti_u_b:
1221 case Intrinsic::mips_clti_u_h:
1222 case Intrinsic::mips_clti_u_w:
1223 case Intrinsic::mips_clti_u_d:
1224 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1225 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1226 case Intrinsic::mips_copy_s_b:
1227 case Intrinsic::mips_copy_s_h:
1228 case Intrinsic::mips_copy_s_w:
1229 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1230 case Intrinsic::mips_copy_s_d:
1231 // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal.
1232 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1233 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1234 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1235 Op->getOperand(1), Op->getOperand(2));
1236 case Intrinsic::mips_copy_u_b:
1237 case Intrinsic::mips_copy_u_h:
1238 case Intrinsic::mips_copy_u_w:
1239 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1240 case Intrinsic::mips_copy_u_d:
1241 // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal.
1242 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1243 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1245 // Note: When i64 is illegal, this results in copy_s.w instructions instead
1246 // of copy_u.w instructions. This makes no difference to the behaviour
1247 // since i64 is only illegal when the register file is 32-bit.
1248 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1249 Op->getOperand(1), Op->getOperand(2));
1250 case Intrinsic::mips_div_s_b:
1251 case Intrinsic::mips_div_s_h:
1252 case Intrinsic::mips_div_s_w:
1253 case Intrinsic::mips_div_s_d:
1254 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1256 case Intrinsic::mips_div_u_b:
1257 case Intrinsic::mips_div_u_h:
1258 case Intrinsic::mips_div_u_w:
1259 case Intrinsic::mips_div_u_d:
1260 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1262 case Intrinsic::mips_fadd_w:
1263 case Intrinsic::mips_fadd_d:
1264 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1266 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1267 case Intrinsic::mips_fceq_w:
1268 case Intrinsic::mips_fceq_d:
1269 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1270 Op->getOperand(2), ISD::SETOEQ);
1271 case Intrinsic::mips_fcle_w:
1272 case Intrinsic::mips_fcle_d:
1273 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1274 Op->getOperand(2), ISD::SETOLE);
1275 case Intrinsic::mips_fclt_w:
1276 case Intrinsic::mips_fclt_d:
1277 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1278 Op->getOperand(2), ISD::SETOLT);
1279 case Intrinsic::mips_fcne_w:
1280 case Intrinsic::mips_fcne_d:
1281 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1282 Op->getOperand(2), ISD::SETONE);
1283 case Intrinsic::mips_fcor_w:
1284 case Intrinsic::mips_fcor_d:
1285 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1286 Op->getOperand(2), ISD::SETO);
1287 case Intrinsic::mips_fcueq_w:
1288 case Intrinsic::mips_fcueq_d:
1289 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1290 Op->getOperand(2), ISD::SETUEQ);
1291 case Intrinsic::mips_fcule_w:
1292 case Intrinsic::mips_fcule_d:
1293 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1294 Op->getOperand(2), ISD::SETULE);
1295 case Intrinsic::mips_fcult_w:
1296 case Intrinsic::mips_fcult_d:
1297 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1298 Op->getOperand(2), ISD::SETULT);
1299 case Intrinsic::mips_fcun_w:
1300 case Intrinsic::mips_fcun_d:
1301 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1302 Op->getOperand(2), ISD::SETUO);
1303 case Intrinsic::mips_fcune_w:
1304 case Intrinsic::mips_fcune_d:
1305 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1306 Op->getOperand(2), ISD::SETUNE);
1307 case Intrinsic::mips_fdiv_w:
1308 case Intrinsic::mips_fdiv_d:
1309 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1311 case Intrinsic::mips_ffint_u_w:
1312 case Intrinsic::mips_ffint_u_d:
1313 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1315 case Intrinsic::mips_ffint_s_w:
1316 case Intrinsic::mips_ffint_s_d:
1317 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1319 case Intrinsic::mips_fill_b:
1320 case Intrinsic::mips_fill_h:
1321 case Intrinsic::mips_fill_w:
1322 case Intrinsic::mips_fill_d: {
1323 SmallVector<SDValue, 16> Ops;
1324 EVT ResTy = Op->getValueType(0);
1326 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1327 Ops.push_back(Op->getOperand(1));
1329 // If ResTy is v2i64 then the type legalizer will break this node down into
1330 // an equivalent v4i32.
1331 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
1333 case Intrinsic::mips_flog2_w:
1334 case Intrinsic::mips_flog2_d:
1335 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1336 case Intrinsic::mips_fmadd_w:
1337 case Intrinsic::mips_fmadd_d:
1338 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1339 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1340 case Intrinsic::mips_fmul_w:
1341 case Intrinsic::mips_fmul_d:
1342 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1344 case Intrinsic::mips_fmsub_w:
1345 case Intrinsic::mips_fmsub_d: {
1346 EVT ResTy = Op->getValueType(0);
1347 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1348 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1349 Op->getOperand(2), Op->getOperand(3)));
1351 case Intrinsic::mips_frint_w:
1352 case Intrinsic::mips_frint_d:
1353 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1354 case Intrinsic::mips_fsqrt_w:
1355 case Intrinsic::mips_fsqrt_d:
1356 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1357 case Intrinsic::mips_fsub_w:
1358 case Intrinsic::mips_fsub_d:
1359 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1361 case Intrinsic::mips_ftrunc_u_w:
1362 case Intrinsic::mips_ftrunc_u_d:
1363 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1365 case Intrinsic::mips_ftrunc_s_w:
1366 case Intrinsic::mips_ftrunc_s_d:
1367 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1369 case Intrinsic::mips_ilvev_b:
1370 case Intrinsic::mips_ilvev_h:
1371 case Intrinsic::mips_ilvev_w:
1372 case Intrinsic::mips_ilvev_d:
1373 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1374 Op->getOperand(1), Op->getOperand(2));
1375 case Intrinsic::mips_ilvl_b:
1376 case Intrinsic::mips_ilvl_h:
1377 case Intrinsic::mips_ilvl_w:
1378 case Intrinsic::mips_ilvl_d:
1379 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1380 Op->getOperand(1), Op->getOperand(2));
1381 case Intrinsic::mips_ilvod_b:
1382 case Intrinsic::mips_ilvod_h:
1383 case Intrinsic::mips_ilvod_w:
1384 case Intrinsic::mips_ilvod_d:
1385 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1386 Op->getOperand(1), Op->getOperand(2));
1387 case Intrinsic::mips_ilvr_b:
1388 case Intrinsic::mips_ilvr_h:
1389 case Intrinsic::mips_ilvr_w:
1390 case Intrinsic::mips_ilvr_d:
1391 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1392 Op->getOperand(1), Op->getOperand(2));
1393 case Intrinsic::mips_insert_b:
1394 case Intrinsic::mips_insert_h:
1395 case Intrinsic::mips_insert_w:
1396 case Intrinsic::mips_insert_d:
1397 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1398 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1399 case Intrinsic::mips_ldi_b:
1400 case Intrinsic::mips_ldi_h:
1401 case Intrinsic::mips_ldi_w:
1402 case Intrinsic::mips_ldi_d:
1403 return lowerMSASplatImm(Op, 1, DAG);
1404 case Intrinsic::mips_maddv_b:
1405 case Intrinsic::mips_maddv_h:
1406 case Intrinsic::mips_maddv_w:
1407 case Intrinsic::mips_maddv_d: {
1408 EVT ResTy = Op->getValueType(0);
1409 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1410 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1411 Op->getOperand(2), Op->getOperand(3)));
1413 case Intrinsic::mips_max_s_b:
1414 case Intrinsic::mips_max_s_h:
1415 case Intrinsic::mips_max_s_w:
1416 case Intrinsic::mips_max_s_d:
1417 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1418 Op->getOperand(1), Op->getOperand(2));
1419 case Intrinsic::mips_max_u_b:
1420 case Intrinsic::mips_max_u_h:
1421 case Intrinsic::mips_max_u_w:
1422 case Intrinsic::mips_max_u_d:
1423 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1424 Op->getOperand(1), Op->getOperand(2));
1425 case Intrinsic::mips_maxi_s_b:
1426 case Intrinsic::mips_maxi_s_h:
1427 case Intrinsic::mips_maxi_s_w:
1428 case Intrinsic::mips_maxi_s_d:
1429 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1430 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1431 case Intrinsic::mips_maxi_u_b:
1432 case Intrinsic::mips_maxi_u_h:
1433 case Intrinsic::mips_maxi_u_w:
1434 case Intrinsic::mips_maxi_u_d:
1435 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1436 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1437 case Intrinsic::mips_min_s_b:
1438 case Intrinsic::mips_min_s_h:
1439 case Intrinsic::mips_min_s_w:
1440 case Intrinsic::mips_min_s_d:
1441 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1442 Op->getOperand(1), Op->getOperand(2));
1443 case Intrinsic::mips_min_u_b:
1444 case Intrinsic::mips_min_u_h:
1445 case Intrinsic::mips_min_u_w:
1446 case Intrinsic::mips_min_u_d:
1447 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1448 Op->getOperand(1), Op->getOperand(2));
1449 case Intrinsic::mips_mini_s_b:
1450 case Intrinsic::mips_mini_s_h:
1451 case Intrinsic::mips_mini_s_w:
1452 case Intrinsic::mips_mini_s_d:
1453 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1454 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1455 case Intrinsic::mips_mini_u_b:
1456 case Intrinsic::mips_mini_u_h:
1457 case Intrinsic::mips_mini_u_w:
1458 case Intrinsic::mips_mini_u_d:
1459 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1460 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1461 case Intrinsic::mips_mod_s_b:
1462 case Intrinsic::mips_mod_s_h:
1463 case Intrinsic::mips_mod_s_w:
1464 case Intrinsic::mips_mod_s_d:
1465 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1467 case Intrinsic::mips_mod_u_b:
1468 case Intrinsic::mips_mod_u_h:
1469 case Intrinsic::mips_mod_u_w:
1470 case Intrinsic::mips_mod_u_d:
1471 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1473 case Intrinsic::mips_mulv_b:
1474 case Intrinsic::mips_mulv_h:
1475 case Intrinsic::mips_mulv_w:
1476 case Intrinsic::mips_mulv_d:
1477 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1479 case Intrinsic::mips_msubv_b:
1480 case Intrinsic::mips_msubv_h:
1481 case Intrinsic::mips_msubv_w:
1482 case Intrinsic::mips_msubv_d: {
1483 EVT ResTy = Op->getValueType(0);
1484 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1485 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1486 Op->getOperand(2), Op->getOperand(3)));
1488 case Intrinsic::mips_nlzc_b:
1489 case Intrinsic::mips_nlzc_h:
1490 case Intrinsic::mips_nlzc_w:
1491 case Intrinsic::mips_nlzc_d:
1492 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1493 case Intrinsic::mips_nor_v: {
1494 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1495 Op->getOperand(1), Op->getOperand(2));
1496 return DAG.getNOT(DL, Res, Res->getValueType(0));
1498 case Intrinsic::mips_nori_b: {
1499 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1501 lowerMSASplatImm(Op, 2, DAG));
1502 return DAG.getNOT(DL, Res, Res->getValueType(0));
1504 case Intrinsic::mips_or_v:
1505 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1507 case Intrinsic::mips_ori_b:
1508 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1509 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1510 case Intrinsic::mips_pckev_b:
1511 case Intrinsic::mips_pckev_h:
1512 case Intrinsic::mips_pckev_w:
1513 case Intrinsic::mips_pckev_d:
1514 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1515 Op->getOperand(1), Op->getOperand(2));
1516 case Intrinsic::mips_pckod_b:
1517 case Intrinsic::mips_pckod_h:
1518 case Intrinsic::mips_pckod_w:
1519 case Intrinsic::mips_pckod_d:
1520 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1521 Op->getOperand(1), Op->getOperand(2));
1522 case Intrinsic::mips_pcnt_b:
1523 case Intrinsic::mips_pcnt_h:
1524 case Intrinsic::mips_pcnt_w:
1525 case Intrinsic::mips_pcnt_d:
1526 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1527 case Intrinsic::mips_shf_b:
1528 case Intrinsic::mips_shf_h:
1529 case Intrinsic::mips_shf_w:
1530 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1531 Op->getOperand(2), Op->getOperand(1));
1532 case Intrinsic::mips_sll_b:
1533 case Intrinsic::mips_sll_h:
1534 case Intrinsic::mips_sll_w:
1535 case Intrinsic::mips_sll_d:
1536 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1538 case Intrinsic::mips_slli_b:
1539 case Intrinsic::mips_slli_h:
1540 case Intrinsic::mips_slli_w:
1541 case Intrinsic::mips_slli_d:
1542 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1543 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1544 case Intrinsic::mips_splati_b:
1545 case Intrinsic::mips_splati_h:
1546 case Intrinsic::mips_splati_w:
1547 case Intrinsic::mips_splati_d:
1548 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1549 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1551 case Intrinsic::mips_sra_b:
1552 case Intrinsic::mips_sra_h:
1553 case Intrinsic::mips_sra_w:
1554 case Intrinsic::mips_sra_d:
1555 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1557 case Intrinsic::mips_srai_b:
1558 case Intrinsic::mips_srai_h:
1559 case Intrinsic::mips_srai_w:
1560 case Intrinsic::mips_srai_d:
1561 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
1562 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1563 case Intrinsic::mips_srl_b:
1564 case Intrinsic::mips_srl_h:
1565 case Intrinsic::mips_srl_w:
1566 case Intrinsic::mips_srl_d:
1567 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
1569 case Intrinsic::mips_srli_b:
1570 case Intrinsic::mips_srli_h:
1571 case Intrinsic::mips_srli_w:
1572 case Intrinsic::mips_srli_d:
1573 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
1574 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1575 case Intrinsic::mips_subv_b:
1576 case Intrinsic::mips_subv_h:
1577 case Intrinsic::mips_subv_w:
1578 case Intrinsic::mips_subv_d:
1579 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
1581 case Intrinsic::mips_subvi_b:
1582 case Intrinsic::mips_subvi_h:
1583 case Intrinsic::mips_subvi_w:
1584 case Intrinsic::mips_subvi_d:
1585 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
1586 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1587 case Intrinsic::mips_vshf_b:
1588 case Intrinsic::mips_vshf_h:
1589 case Intrinsic::mips_vshf_w:
1590 case Intrinsic::mips_vshf_d:
1591 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1592 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1593 case Intrinsic::mips_xor_v:
1594 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
1596 case Intrinsic::mips_xori_b:
1597 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
1598 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1602 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1604 SDValue ChainIn = Op->getOperand(0);
1605 SDValue Address = Op->getOperand(2);
1606 SDValue Offset = Op->getOperand(3);
1607 EVT ResTy = Op->getValueType(0);
1608 EVT PtrTy = Address->getValueType(0);
1610 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1612 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1616 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1617 SelectionDAG &DAG) const {
1618 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1622 case Intrinsic::mips_extp:
1623 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1624 case Intrinsic::mips_extpdp:
1625 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1626 case Intrinsic::mips_extr_w:
1627 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1628 case Intrinsic::mips_extr_r_w:
1629 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1630 case Intrinsic::mips_extr_rs_w:
1631 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1632 case Intrinsic::mips_extr_s_h:
1633 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1634 case Intrinsic::mips_mthlip:
1635 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1636 case Intrinsic::mips_mulsaq_s_w_ph:
1637 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1638 case Intrinsic::mips_maq_s_w_phl:
1639 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1640 case Intrinsic::mips_maq_s_w_phr:
1641 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1642 case Intrinsic::mips_maq_sa_w_phl:
1643 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1644 case Intrinsic::mips_maq_sa_w_phr:
1645 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1646 case Intrinsic::mips_dpaq_s_w_ph:
1647 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1648 case Intrinsic::mips_dpsq_s_w_ph:
1649 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1650 case Intrinsic::mips_dpaq_sa_l_w:
1651 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1652 case Intrinsic::mips_dpsq_sa_l_w:
1653 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1654 case Intrinsic::mips_dpaqx_s_w_ph:
1655 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1656 case Intrinsic::mips_dpaqx_sa_w_ph:
1657 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1658 case Intrinsic::mips_dpsqx_s_w_ph:
1659 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1660 case Intrinsic::mips_dpsqx_sa_w_ph:
1661 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1662 case Intrinsic::mips_ld_b:
1663 case Intrinsic::mips_ld_h:
1664 case Intrinsic::mips_ld_w:
1665 case Intrinsic::mips_ld_d:
1666 case Intrinsic::mips_ldx_b:
1667 case Intrinsic::mips_ldx_h:
1668 case Intrinsic::mips_ldx_w:
1669 case Intrinsic::mips_ldx_d:
1670 return lowerMSALoadIntr(Op, DAG, Intr);
1674 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1676 SDValue ChainIn = Op->getOperand(0);
1677 SDValue Value = Op->getOperand(2);
1678 SDValue Address = Op->getOperand(3);
1679 SDValue Offset = Op->getOperand(4);
1680 EVT PtrTy = Address->getValueType(0);
1682 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1684 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1688 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1689 SelectionDAG &DAG) const {
1690 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1694 case Intrinsic::mips_st_b:
1695 case Intrinsic::mips_st_h:
1696 case Intrinsic::mips_st_w:
1697 case Intrinsic::mips_st_d:
1698 case Intrinsic::mips_stx_b:
1699 case Intrinsic::mips_stx_h:
1700 case Intrinsic::mips_stx_w:
1701 case Intrinsic::mips_stx_d:
1702 return lowerMSAStoreIntr(Op, DAG, Intr);
1706 /// \brief Check if the given BuildVectorSDNode is a splat.
1707 /// This method currently relies on DAG nodes being reused when equivalent,
1708 /// so it's possible for this to return false even when isConstantSplat returns
1710 static bool isSplatVector(const BuildVectorSDNode *N) {
1711 unsigned int nOps = N->getNumOperands();
1712 assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1714 SDValue Operand0 = N->getOperand(0);
1716 for (unsigned int i = 1; i < nOps; ++i) {
1717 if (N->getOperand(i) != Operand0)
1724 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
1726 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
1727 // choose to sign-extend but we could have equally chosen zero-extend. The
1728 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
1729 // result into this node later (possibly changing it to a zero-extend in the
1731 SDValue MipsSETargetLowering::
1732 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
1734 EVT ResTy = Op->getValueType(0);
1735 SDValue Op0 = Op->getOperand(0);
1736 EVT VecTy = Op0->getValueType(0);
1738 if (!VecTy.is128BitVector())
1741 if (ResTy.isInteger()) {
1742 SDValue Op1 = Op->getOperand(1);
1743 EVT EltTy = VecTy.getVectorElementType();
1744 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
1745 DAG.getValueType(EltTy));
1751 static bool isConstantOrUndef(const SDValue Op) {
1752 if (Op->getOpcode() == ISD::UNDEF)
1754 if (dyn_cast<ConstantSDNode>(Op))
1756 if (dyn_cast<ConstantFPSDNode>(Op))
1761 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
1762 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
1763 if (isConstantOrUndef(Op->getOperand(i)))
1768 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1771 // Lowers according to the following rules:
1772 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
1773 // 2 less than or equal to 64 and the value fits into a signed 10-bit
1775 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
1776 // is a power of 2 less than or equal to 64 and the value does not fit into a
1777 // signed 10-bit immediate
1778 // - Non-constant splats are legal as-is.
1779 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
1780 // - All others are illegal and must be expanded.
1781 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1782 SelectionDAG &DAG) const {
1783 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1784 EVT ResTy = Op->getValueType(0);
1786 APInt SplatValue, SplatUndef;
1787 unsigned SplatBitSize;
1790 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1793 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1795 !Subtarget->isLittle()) && SplatBitSize <= 64) {
1796 // We can only cope with 8, 16, 32, or 64-bit elements
1797 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
1801 // If the value fits into a simm10 then we can use ldi.[bhwd]
1802 if (SplatValue.isSignedIntN(10))
1807 switch (SplatBitSize) {
1811 ViaVecTy = MVT::v16i8;
1814 ViaVecTy = MVT::v8i16;
1817 ViaVecTy = MVT::v4i32;
1820 // There's no fill.d to fall back on for 64-bit values
1824 SmallVector<SDValue, 16> Ops;
1825 SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32);
1827 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i)
1828 Ops.push_back(Constant);
1830 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy,
1831 &Ops[0], Ops.size());
1833 if (ViaVecTy != ResTy)
1834 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
1837 } else if (isSplatVector(Node))
1839 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
1840 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
1841 // The resulting code is the same length as the expansion, but it doesn't
1842 // use memory operations
1843 EVT ResTy = Node->getValueType(0);
1845 assert(ResTy.isVector());
1847 unsigned NumElts = ResTy.getVectorNumElements();
1848 SDValue Vector = DAG.getUNDEF(ResTy);
1849 for (unsigned i = 0; i < NumElts; ++i) {
1850 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
1851 Node->getOperand(i),
1852 DAG.getConstant(i, MVT::i32));
1860 // Lower VECTOR_SHUFFLE into SHF (if possible).
1862 // SHF splits the vector into blocks of four elements, then shuffles these
1863 // elements according to a <4 x i2> constant (encoded as an integer immediate).
1865 // It is therefore possible to lower into SHF when the mask takes the form:
1866 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
1867 // When undef's appear they are treated as if they were whatever value is
1868 // necessary in order to fit the above form.
1871 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
1872 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
1873 // i32 7, i32 6, i32 5, i32 4>
1875 // (SHF_H $w0, $w1, 27)
1876 // where the 27 comes from:
1877 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
1878 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
1879 SmallVector<int, 16> Indices,
1880 SelectionDAG &DAG) {
1881 int SHFIndices[4] = { -1, -1, -1, -1 };
1883 if (Indices.size() < 4)
1886 for (unsigned i = 0; i < 4; ++i) {
1887 for (unsigned j = i; j < Indices.size(); j += 4) {
1888 int Idx = Indices[j];
1890 // Convert from vector index to 4-element subvector index
1891 // If an index refers to an element outside of the subvector then give up
1894 if (Idx < 0 || Idx >= 4)
1898 // If the mask has an undef, replace it with the current index.
1899 // Note that it might still be undef if the current index is also undef
1900 if (SHFIndices[i] == -1)
1901 SHFIndices[i] = Idx;
1903 // Check that non-undef values are the same as in the mask. If they
1904 // aren't then give up
1905 if (!(Idx == -1 || Idx == SHFIndices[i]))
1910 // Calculate the immediate. Replace any remaining undefs with zero
1912 for (int i = 3; i >= 0; --i) {
1913 int Idx = SHFIndices[i];
1922 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
1923 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
1926 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
1928 // ILVEV interleaves the even elements from each vector.
1930 // It is possible to lower into ILVEV when the mask takes the form:
1931 // <0, n, 2, n+2, 4, n+4, ...>
1932 // where n is the number of elements in the vector.
1934 // When undef's appear in the mask they are treated as if they were whatever
1935 // value is necessary in order to fit the above form.
1936 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
1937 SmallVector<int, 16> Indices,
1938 SelectionDAG &DAG) {
1939 assert ((Indices.size() % 2) == 0);
1941 int WtIdx = ResTy.getVectorNumElements();
1943 for (unsigned i = 0; i < Indices.size(); i += 2) {
1944 if (Indices[i] != -1 && Indices[i] != WsIdx)
1946 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1952 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
1956 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
1958 // ILVOD interleaves the odd elements from each vector.
1960 // It is possible to lower into ILVOD when the mask takes the form:
1961 // <1, n+1, 3, n+3, 5, n+5, ...>
1962 // where n is the number of elements in the vector.
1964 // When undef's appear in the mask they are treated as if they were whatever
1965 // value is necessary in order to fit the above form.
1966 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
1967 SmallVector<int, 16> Indices,
1968 SelectionDAG &DAG) {
1969 assert ((Indices.size() % 2) == 0);
1971 int WtIdx = ResTy.getVectorNumElements() + 1;
1973 for (unsigned i = 0; i < Indices.size(); i += 2) {
1974 if (Indices[i] != -1 && Indices[i] != WsIdx)
1976 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1982 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
1986 // Lower VECTOR_SHUFFLE into ILVL (if possible).
1988 // ILVL interleaves consecutive elements from the left half of each vector.
1990 // It is possible to lower into ILVL when the mask takes the form:
1991 // <0, n, 1, n+1, 2, n+2, ...>
1992 // where n is the number of elements in the vector.
1994 // When undef's appear in the mask they are treated as if they were whatever
1995 // value is necessary in order to fit the above form.
1996 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
1997 SmallVector<int, 16> Indices,
1998 SelectionDAG &DAG) {
1999 assert ((Indices.size() % 2) == 0);
2001 int WtIdx = ResTy.getVectorNumElements();
2003 for (unsigned i = 0; i < Indices.size(); i += 2) {
2004 if (Indices[i] != -1 && Indices[i] != WsIdx)
2006 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2012 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2016 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2018 // ILVR interleaves consecutive elements from the right half of each vector.
2020 // It is possible to lower into ILVR when the mask takes the form:
2021 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2022 // where n is the number of elements in the vector and x is half n.
2024 // When undef's appear in the mask they are treated as if they were whatever
2025 // value is necessary in order to fit the above form.
2026 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2027 SmallVector<int, 16> Indices,
2028 SelectionDAG &DAG) {
2029 assert ((Indices.size() % 2) == 0);
2030 unsigned NumElts = ResTy.getVectorNumElements();
2031 int WsIdx = NumElts / 2;
2032 int WtIdx = NumElts + NumElts / 2;
2034 for (unsigned i = 0; i < Indices.size(); i += 2) {
2035 if (Indices[i] != -1 && Indices[i] != WsIdx)
2037 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2043 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2047 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2049 // PCKEV copies the even elements of each vector into the result vector.
2051 // It is possible to lower into PCKEV when the mask takes the form:
2052 // <0, 2, 4, ..., n, n+2, n+4, ...>
2053 // where n is the number of elements in the vector.
2055 // When undef's appear in the mask they are treated as if they were whatever
2056 // value is necessary in order to fit the above form.
2057 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2058 SmallVector<int, 16> Indices,
2059 SelectionDAG &DAG) {
2060 assert ((Indices.size() % 2) == 0);
2063 for (unsigned i = 0; i < Indices.size(); ++i) {
2064 if (Indices[i] != -1 && Indices[i] != Idx)
2069 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2073 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2075 // PCKOD copies the odd elements of each vector into the result vector.
2077 // It is possible to lower into PCKOD when the mask takes the form:
2078 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2079 // where n is the number of elements in the vector.
2081 // When undef's appear in the mask they are treated as if they were whatever
2082 // value is necessary in order to fit the above form.
2083 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2084 SmallVector<int, 16> Indices,
2085 SelectionDAG &DAG) {
2086 assert ((Indices.size() % 2) == 0);
2089 for (unsigned i = 0; i < Indices.size(); ++i) {
2090 if (Indices[i] != -1 && Indices[i] != Idx)
2095 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2099 // Lower VECTOR_SHUFFLE into VSHF.
2101 // This mostly consists of converting the shuffle indices in Indices into a
2102 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2103 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2104 // if the type is v8i16 and all the indices are less than 8 then the second
2105 // operand is unused and can be replaced with anything. We choose to replace it
2106 // with the used operand since this reduces the number of instructions overall.
2107 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2108 SmallVector<int, 16> Indices,
2109 SelectionDAG &DAG) {
2110 SmallVector<SDValue, 16> Ops;
2113 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2114 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2115 bool Using1stVec = false;
2116 bool Using2ndVec = false;
2118 int ResTyNumElts = ResTy.getVectorNumElements();
2120 for (int i = 0; i < ResTyNumElts; ++i) {
2121 // Idx == -1 means UNDEF
2122 int Idx = Indices[i];
2124 if (0 <= Idx && Idx < ResTyNumElts)
2126 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2130 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2132 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2134 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
2137 if (Using1stVec && Using2ndVec) {
2138 Op0 = Op->getOperand(0);
2139 Op1 = Op->getOperand(1);
2140 } else if (Using1stVec)
2141 Op0 = Op1 = Op->getOperand(0);
2142 else if (Using2ndVec)
2143 Op0 = Op1 = Op->getOperand(1);
2145 llvm_unreachable("shuffle vector mask references neither vector operand?");
2147 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1);
2150 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2151 // indices in the shuffle.
2152 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2153 SelectionDAG &DAG) const {
2154 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2155 EVT ResTy = Op->getValueType(0);
2157 if (!ResTy.is128BitVector())
2160 int ResTyNumElts = ResTy.getVectorNumElements();
2161 SmallVector<int, 16> Indices;
2163 for (int i = 0; i < ResTyNumElts; ++i)
2164 Indices.push_back(Node->getMaskElt(i));
2166 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2167 if (Result.getNode())
2169 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2170 if (Result.getNode())
2172 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2173 if (Result.getNode())
2175 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2176 if (Result.getNode())
2178 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2179 if (Result.getNode())
2181 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2182 if (Result.getNode())
2184 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2185 if (Result.getNode())
2187 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2190 MachineBasicBlock * MipsSETargetLowering::
2191 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2193 // bposge32_pseudo $vr0
2203 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2205 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2206 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2207 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2208 DebugLoc DL = MI->getDebugLoc();
2209 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2210 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2211 MachineFunction *F = BB->getParent();
2212 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2213 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2214 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2217 F->insert(It, Sink);
2219 // Transfer the remainder of BB and its successor edges to Sink.
2220 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2222 Sink->transferSuccessorsAndUpdatePHIs(BB);
2225 BB->addSuccessor(FBB);
2226 BB->addSuccessor(TBB);
2227 FBB->addSuccessor(Sink);
2228 TBB->addSuccessor(Sink);
2230 // Insert the real bposge32 instruction to $BB.
2231 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2234 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2235 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2236 .addReg(Mips::ZERO).addImm(0);
2237 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2240 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2241 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2242 .addReg(Mips::ZERO).addImm(1);
2244 // Insert phi function to $Sink.
2245 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2246 MI->getOperand(0).getReg())
2247 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2249 MI->eraseFromParent(); // The pseudo instruction is gone now.
2253 MachineBasicBlock * MipsSETargetLowering::
2254 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2255 unsigned BranchOp) const{
2257 // vany_nonzero $rd, $ws
2268 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2270 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2271 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2272 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2273 DebugLoc DL = MI->getDebugLoc();
2274 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2275 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2276 MachineFunction *F = BB->getParent();
2277 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2278 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2279 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2282 F->insert(It, Sink);
2284 // Transfer the remainder of BB and its successor edges to Sink.
2285 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2287 Sink->transferSuccessorsAndUpdatePHIs(BB);
2290 BB->addSuccessor(FBB);
2291 BB->addSuccessor(TBB);
2292 FBB->addSuccessor(Sink);
2293 TBB->addSuccessor(Sink);
2295 // Insert the real bnz.b instruction to $BB.
2296 BuildMI(BB, DL, TII->get(BranchOp))
2297 .addReg(MI->getOperand(1).getReg())
2301 unsigned RD1 = RegInfo.createVirtualRegister(RC);
2302 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2303 .addReg(Mips::ZERO).addImm(0);
2304 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2307 unsigned RD2 = RegInfo.createVirtualRegister(RC);
2308 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2309 .addReg(Mips::ZERO).addImm(1);
2311 // Insert phi function to $Sink.
2312 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2313 MI->getOperand(0).getReg())
2314 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2316 MI->eraseFromParent(); // The pseudo instruction is gone now.
2320 // Emit the COPY_FW pseudo instruction.
2322 // copy_fw_pseudo $fd, $ws, n
2324 // copy_u_w $rt, $ws, $n
2327 // When n is zero, the equivalent operation can be performed with (potentially)
2328 // zero instructions due to register overlaps. This optimization is never valid
2329 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2330 MachineBasicBlock * MipsSETargetLowering::
2331 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2332 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2333 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2334 DebugLoc DL = MI->getDebugLoc();
2335 unsigned Fd = MI->getOperand(0).getReg();
2336 unsigned Ws = MI->getOperand(1).getReg();
2337 unsigned Lane = MI->getOperand(2).getImm();
2340 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2342 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2344 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1);
2345 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2348 MI->eraseFromParent(); // The pseudo instruction is gone now.
2352 // Emit the COPY_FD pseudo instruction.
2354 // copy_fd_pseudo $fd, $ws, n
2356 // splati.d $wt, $ws, $n
2357 // copy $fd, $wt:sub_64
2359 // When n is zero, the equivalent operation can be performed with (potentially)
2360 // zero instructions due to register overlaps. This optimization is always
2361 // valid because FR=1 mode which is the only supported mode in MSA.
2362 MachineBasicBlock * MipsSETargetLowering::
2363 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2364 assert(Subtarget->isFP64bit());
2366 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2367 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2368 unsigned Fd = MI->getOperand(0).getReg();
2369 unsigned Ws = MI->getOperand(1).getReg();
2370 unsigned Lane = MI->getOperand(2).getImm() * 2;
2371 DebugLoc DL = MI->getDebugLoc();
2374 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2376 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2378 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2379 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2382 MI->eraseFromParent(); // The pseudo instruction is gone now.
2386 // Emit the INSERT_FW pseudo instruction.
2388 // insert_fw_pseudo $wd, $wd_in, $n, $fs
2390 // subreg_to_reg $wt:sub_lo, $fs
2391 // insve_w $wd[$n], $wd_in, $wt[0]
2392 MachineBasicBlock * MipsSETargetLowering::
2393 emitINSERT_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2394 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2395 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2396 DebugLoc DL = MI->getDebugLoc();
2397 unsigned Wd = MI->getOperand(0).getReg();
2398 unsigned Wd_in = MI->getOperand(1).getReg();
2399 unsigned Lane = MI->getOperand(2).getImm();
2400 unsigned Fs = MI->getOperand(3).getReg();
2401 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2403 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2404 .addImm(0).addReg(Fs).addImm(Mips::sub_lo);
2405 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2406 .addReg(Wd_in).addImm(Lane).addReg(Wt);
2408 MI->eraseFromParent(); // The pseudo instruction is gone now.
2412 // Emit the INSERT_FD pseudo instruction.
2414 // insert_fd_pseudo $wd, $fs, n
2416 // subreg_to_reg $wt:sub_64, $fs
2417 // insve_d $wd[$n], $wd_in, $wt[0]
2418 MachineBasicBlock * MipsSETargetLowering::
2419 emitINSERT_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2420 assert(Subtarget->isFP64bit());
2422 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2423 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2424 DebugLoc DL = MI->getDebugLoc();
2425 unsigned Wd = MI->getOperand(0).getReg();
2426 unsigned Wd_in = MI->getOperand(1).getReg();
2427 unsigned Lane = MI->getOperand(2).getImm();
2428 unsigned Fs = MI->getOperand(3).getReg();
2429 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2431 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2432 .addImm(0).addReg(Fs).addImm(Mips::sub_64);
2433 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2434 .addReg(Wd_in).addImm(Lane).addReg(Wt);
2436 MI->eraseFromParent(); // The pseudo instruction is gone now.