1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
15 #include "MipsSEISelDAGToDAG.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsRegisterInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CFG.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
39 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
40 const MachineInstr& MI) {
41 unsigned DstReg = 0, ZeroReg = 0;
43 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
44 if ((MI.getOpcode() == Mips::ADDiu) &&
45 (MI.getOperand(1).getReg() == Mips::ZERO) &&
46 (MI.getOperand(2).getImm() == 0)) {
47 DstReg = MI.getOperand(0).getReg();
49 } else if ((MI.getOpcode() == Mips::DADDiu) &&
50 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
51 (MI.getOperand(2).getImm() == 0)) {
52 DstReg = MI.getOperand(0).getReg();
53 ZeroReg = Mips::ZERO_64;
59 // Replace uses with ZeroReg.
60 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
61 E = MRI->use_end(); U != E;) {
62 MachineOperand &MO = U.getOperand();
63 unsigned OpNo = U.getOperandNo();
64 MachineInstr *MI = MO.getParent();
67 // Do not replace if it is a phi's operand or is tied to def operand.
68 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
77 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
78 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
80 if (!MipsFI->globalBaseRegSet())
83 MachineBasicBlock &MBB = MF.front();
84 MachineBasicBlock::iterator I = MBB.begin();
85 MachineRegisterInfo &RegInfo = MF.getRegInfo();
86 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
87 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
88 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
89 const TargetRegisterClass *RC;
91 if (Subtarget.isABI_N64())
92 RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
94 RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass;
96 V0 = RegInfo.createVirtualRegister(RC);
97 V1 = RegInfo.createVirtualRegister(RC);
99 if (Subtarget.isABI_N64()) {
100 MF.getRegInfo().addLiveIn(Mips::T9_64);
101 MBB.addLiveIn(Mips::T9_64);
103 // lui $v0, %hi(%neg(%gp_rel(fname)))
104 // daddu $v1, $v0, $t9
105 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
106 const GlobalValue *FName = MF.getFunction();
107 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
108 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
109 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
110 .addReg(Mips::T9_64);
111 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
112 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
116 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
117 // Set global register to __gnu_local_gp.
119 // lui $v0, %hi(__gnu_local_gp)
120 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
121 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
122 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
123 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
124 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
128 MF.getRegInfo().addLiveIn(Mips::T9);
129 MBB.addLiveIn(Mips::T9);
131 if (Subtarget.isABI_N32()) {
132 // lui $v0, %hi(%neg(%gp_rel(fname)))
133 // addu $v1, $v0, $t9
134 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
135 const GlobalValue *FName = MF.getFunction();
136 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
137 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
138 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
139 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
140 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
144 assert(Subtarget.isABI_O32());
146 // For O32 ABI, the following instruction sequence is emitted to initialize
147 // the global base register:
149 // 0. lui $2, %hi(_gp_disp)
150 // 1. addiu $2, $2, %lo(_gp_disp)
151 // 2. addu $globalbasereg, $2, $t9
153 // We emit only the last instruction here.
155 // GNU linker requires that the first two instructions appear at the beginning
156 // of a function and no instructions be inserted before or between them.
157 // The two instructions are emitted during lowering to MC layer in order to
158 // avoid any reordering.
160 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
161 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
163 MF.getRegInfo().addLiveIn(Mips::V0);
164 MBB.addLiveIn(Mips::V0);
165 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
166 .addReg(Mips::V0).addReg(Mips::T9);
169 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
170 initGlobalBaseReg(MF);
172 MachineRegisterInfo *MRI = &MF.getRegInfo();
174 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
176 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
177 replaceUsesWithZeroReg(MRI, *I);
180 /// Select multiply instructions.
181 std::pair<SDNode*, SDNode*>
182 MipsSEDAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty,
183 bool HasLo, bool HasHi) {
184 SDNode *Lo = 0, *Hi = 0;
185 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
187 SDValue InFlag = SDValue(Mul, 0);
190 unsigned Opcode = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64);
191 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
192 InFlag = SDValue(Lo, 1);
195 unsigned Opcode = (Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64);
196 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
198 return std::make_pair(Lo, Hi);
201 /// ComplexPattern used on MipsInstrInfo
202 /// Used on Mips Load/Store instructions
203 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
204 SDValue &Offset) const {
205 EVT ValTy = Addr.getValueType();
207 // if Address is FI, get the TargetFrameIndex.
208 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
209 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
210 Offset = CurDAG->getTargetConstant(0, ValTy);
214 // on PIC code Load GA
215 if (Addr.getOpcode() == MipsISD::Wrapper) {
216 Base = Addr.getOperand(0);
217 Offset = Addr.getOperand(1);
221 if (TM.getRelocationModel() != Reloc::PIC_) {
222 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
223 Addr.getOpcode() == ISD::TargetGlobalAddress))
227 // Addresses of the form FI+const or FI|const
228 if (CurDAG->isBaseWithConstantOffset(Addr)) {
229 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
230 if (isInt<16>(CN->getSExtValue())) {
232 // If the first operand is a FI, get the TargetFI Node
233 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
234 (Addr.getOperand(0)))
235 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
237 Base = Addr.getOperand(0);
239 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
244 // Operand is a result from an ADD.
245 if (Addr.getOpcode() == ISD::ADD) {
246 // When loading from constant pools, load the lower address part in
247 // the instruction itself. Example, instead of:
248 // lui $2, %hi($CPI1_0)
249 // addiu $2, $2, %lo($CPI1_0)
252 // lui $2, %hi($CPI1_0)
253 // lwc1 $f0, %lo($CPI1_0)($2)
254 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
255 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
256 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
257 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
258 isa<JumpTableSDNode>(Opnd0)) {
259 Base = Addr.getOperand(0);
269 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
270 SDValue &Offset) const {
272 Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
276 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
277 SDValue &Offset) const {
278 return selectAddrRegImm(Addr, Base, Offset) ||
279 selectAddrDefault(Addr, Base, Offset);
282 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
283 unsigned Opcode = Node->getOpcode();
284 DebugLoc DL = Node->getDebugLoc();
287 // Instruction Selection not handled by the auto-generated
288 // tablegen selection should be handled here.
290 EVT NodeTy = Node->getValueType(0);
299 SDValue InFlag = Node->getOperand(2), CmpLHS;
300 unsigned Opc = InFlag.getOpcode(); (void)Opc;
301 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
302 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
303 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
306 if (Opcode == ISD::ADDE) {
307 CmpLHS = InFlag.getValue(0);
310 CmpLHS = InFlag.getOperand(0);
314 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
316 SDValue LHS = Node->getOperand(0);
317 SDValue RHS = Node->getOperand(1);
319 EVT VT = LHS.getValueType();
321 unsigned Sltu_op = Mips::SLTu;
322 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops, 2);
323 unsigned Addu_op = Mips::ADDu;
324 SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
325 SDValue(Carry,0), RHS);
327 Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
328 SDValue(AddCarry,0));
329 return std::make_pair(true, Result);
332 /// Mul with two results
334 case ISD::UMUL_LOHI: {
335 if (NodeTy == MVT::i32)
336 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
338 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
340 std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy,
343 if (!SDValue(Node, 0).use_empty())
344 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
346 if (!SDValue(Node, 1).use_empty())
347 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
349 return std::make_pair(true, (SDNode*)NULL);
354 // Mips32 has a 32-bit three operand mul instruction.
355 if (Subtarget.hasMips32() && NodeTy == MVT::i32)
357 MultOpc = NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT;
358 Result = selectMULT(Node, MultOpc, DL, NodeTy, true, false).first;
359 return std::make_pair(true, Result);
363 if (NodeTy == MVT::i32)
364 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
366 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
368 Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
369 return std::make_pair(true, Result);
372 case ISD::ConstantFP: {
373 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
374 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
375 if (Subtarget.hasMips64()) {
376 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
377 Mips::ZERO_64, MVT::i64);
378 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
380 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
381 Mips::ZERO, MVT::i32);
382 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
386 return std::make_pair(true, Result);
391 case ISD::Constant: {
392 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
393 unsigned Size = CN->getValueSizeInBits(0);
398 MipsAnalyzeImmediate AnalyzeImm;
399 int64_t Imm = CN->getSExtValue();
401 const MipsAnalyzeImmediate::InstSeq &Seq =
402 AnalyzeImm.Analyze(Imm, Size, false);
404 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
405 DebugLoc DL = CN->getDebugLoc();
407 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
410 // The first instruction can be a LUi which is different from other
411 // instructions (ADDiu, ORI and SLL) in that it does not have a register
413 if (Inst->Opc == Mips::LUi64)
414 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
417 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
418 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
421 // The remaining instructions in the sequence are handled here.
422 for (++Inst; Inst != Seq.end(); ++Inst) {
423 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
425 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
426 SDValue(RegOpnd, 0), ImmOpnd);
429 return std::make_pair(true, RegOpnd);
432 case MipsISD::ThreadPointer: {
433 EVT PtrVT = TLI.getPointerTy();
434 unsigned RdhwrOpc, SrcReg, DestReg;
436 if (PtrVT == MVT::i32) {
437 RdhwrOpc = Mips::RDHWR;
438 SrcReg = Mips::HWR29;
441 RdhwrOpc = Mips::RDHWR64;
442 SrcReg = Mips::HWR29_64;
443 DestReg = Mips::V1_64;
447 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
448 Node->getValueType(0),
449 CurDAG->getRegister(SrcReg, PtrVT));
450 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
452 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
453 ReplaceUses(SDValue(Node, 0), ResNode);
454 return std::make_pair(true, ResNode.getNode());
458 return std::make_pair(false, (SDNode*)NULL);
461 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
462 return new MipsSEDAGToDAGISel(TM);