1 //===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEFrameLowering.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSEInstrInfo.h"
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Target/TargetOptions.h"
34 typedef MachineBasicBlock::iterator Iter;
36 static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) {
37 if (Mips::ACC64RegClass.contains(Src))
38 return std::make_pair((unsigned)Mips::PseudoMFHI,
39 (unsigned)Mips::PseudoMFLO);
41 if (Mips::ACC64DSPRegClass.contains(Src))
42 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
44 if (Mips::ACC128RegClass.contains(Src))
45 return std::make_pair((unsigned)Mips::PseudoMFHI64,
46 (unsigned)Mips::PseudoMFLO64);
48 return std::make_pair(0, 0);
51 /// Helper class to expand pseudos.
54 ExpandPseudo(MachineFunction &MF);
58 bool expandInstr(MachineBasicBlock &MBB, Iter I);
59 void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
60 void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
61 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
62 void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
63 unsigned MFLoOpc, unsigned RegSize);
64 bool expandCopy(MachineBasicBlock &MBB, Iter I);
65 bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
67 bool expandBuildPairF64(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator I, bool FP64) const;
69 bool expandExtractElementF64(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator I, bool FP64) const;
73 MachineRegisterInfo &MRI;
77 ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
78 : MF(MF_), MRI(MF.getRegInfo()) {}
80 bool ExpandPseudo::expand() {
81 bool Expanded = false;
83 for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
85 for (Iter I = BB->begin(), End = BB->end(); I != End;)
86 Expanded |= expandInstr(*BB, I++);
91 bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
92 switch(I->getOpcode()) {
93 case Mips::LOAD_CCOND_DSP:
94 expandLoadCCond(MBB, I);
96 case Mips::STORE_CCOND_DSP:
97 expandStoreCCond(MBB, I);
99 case Mips::LOAD_ACC64:
100 case Mips::LOAD_ACC64DSP:
101 expandLoadACC(MBB, I, 4);
103 case Mips::LOAD_ACC128:
104 expandLoadACC(MBB, I, 8);
106 case Mips::STORE_ACC64:
107 expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
109 case Mips::STORE_ACC64DSP:
110 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
112 case Mips::STORE_ACC128:
113 expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
115 case Mips::BuildPairF64:
116 if (expandBuildPairF64(MBB, I, false))
119 case Mips::BuildPairF64_64:
120 if (expandBuildPairF64(MBB, I, true))
123 case Mips::ExtractElementF64:
124 if (expandExtractElementF64(MBB, I, false))
127 case Mips::ExtractElementF64_64:
128 if (expandExtractElementF64(MBB, I, true))
131 case TargetOpcode::COPY:
132 if (!expandCopy(MBB, I))
143 void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
147 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
149 const MipsSEInstrInfo &TII =
150 *static_cast<const MipsSEInstrInfo *>(
151 MF.getTarget().getSubtargetImpl()->getInstrInfo());
152 const MipsRegisterInfo &RegInfo =
153 *static_cast<const MipsRegisterInfo *>(
154 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
156 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
157 unsigned VR = MRI.createVirtualRegister(RC);
158 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
160 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
161 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
162 .addReg(VR, RegState::Kill);
165 void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
169 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
171 const MipsSEInstrInfo &TII =
172 *static_cast<const MipsSEInstrInfo *>(
173 MF.getTarget().getSubtargetImpl()->getInstrInfo());
174 const MipsRegisterInfo &RegInfo =
175 *static_cast<const MipsRegisterInfo *>(
176 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
178 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
179 unsigned VR = MRI.createVirtualRegister(RC);
180 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
182 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
183 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
184 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
187 void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
194 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
196 const MipsSEInstrInfo &TII =
197 *static_cast<const MipsSEInstrInfo *>(
198 MF.getTarget().getSubtargetImpl()->getInstrInfo());
199 const MipsRegisterInfo &RegInfo =
200 *static_cast<const MipsRegisterInfo *>(
201 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
203 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
204 unsigned VR0 = MRI.createVirtualRegister(RC);
205 unsigned VR1 = MRI.createVirtualRegister(RC);
206 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
207 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
208 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
209 DebugLoc DL = I->getDebugLoc();
210 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
212 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
213 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
214 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
215 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
218 void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
219 unsigned MFHiOpc, unsigned MFLoOpc,
224 // store $vr1, FI + 4
226 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
228 const MipsSEInstrInfo &TII =
229 *static_cast<const MipsSEInstrInfo *>(
230 MF.getTarget().getSubtargetImpl()->getInstrInfo());
231 const MipsRegisterInfo &RegInfo =
232 *static_cast<const MipsRegisterInfo *>(
233 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
235 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
236 unsigned VR0 = MRI.createVirtualRegister(RC);
237 unsigned VR1 = MRI.createVirtualRegister(RC);
238 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
239 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
240 DebugLoc DL = I->getDebugLoc();
242 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
243 TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
244 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
245 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
248 bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
249 unsigned Src = I->getOperand(1).getReg();
250 std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
255 return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
258 bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
259 unsigned MFHiOpc, unsigned MFLoOpc) {
265 const MipsSEInstrInfo &TII =
266 *static_cast<const MipsSEInstrInfo *>(
267 MF.getTarget().getSubtargetImpl()->getInstrInfo());
268 const MipsRegisterInfo &RegInfo =
269 *static_cast<const MipsRegisterInfo *>(
270 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
272 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
273 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
274 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
275 unsigned VR0 = MRI.createVirtualRegister(RC);
276 unsigned VR1 = MRI.createVirtualRegister(RC);
277 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
278 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
279 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
280 DebugLoc DL = I->getDebugLoc();
282 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
283 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
284 .addReg(VR0, RegState::Kill);
285 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
286 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
287 .addReg(VR1, RegState::Kill);
291 /// This method expands the same instruction that MipsSEInstrInfo::
292 /// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not
293 /// available and the case where the ABI is FP64A. It is implemented here
294 /// because frame indexes are eliminated before MipsSEInstrInfo::
295 /// expandBuildPairF64 is called.
296 bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
297 MachineBasicBlock::iterator I,
299 // For fpxx and when mthc1 is not available, use:
300 // spill + reload via ldc1
302 // The case where dmtc1 is available doesn't need to be handled here
303 // because it never creates a BuildPairF64 node.
305 // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
306 // for odd-numbered double precision values (because the lower 32-bits is
307 // transferred with mtc1 which is redirected to the upper half of the even
308 // register). Unfortunately, we have to make this decision before register
309 // allocation so for now we use a spill/reload sequence for all
310 // double-precision values in regardless of being an odd/even register.
312 const TargetMachine &TM = MF.getTarget();
313 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
314 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
315 (FP64 && !Subtarget.useOddSPReg())) {
316 const MipsSEInstrInfo &TII = *static_cast<const MipsSEInstrInfo *>(
317 TM.getSubtargetImpl()->getInstrInfo());
318 const MipsRegisterInfo &TRI = *static_cast<const MipsRegisterInfo *>(
319 TM.getSubtargetImpl()->getRegisterInfo());
321 unsigned DstReg = I->getOperand(0).getReg();
322 unsigned LoReg = I->getOperand(1).getReg();
323 unsigned HiReg = I->getOperand(2).getReg();
325 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
326 // the cases where mthc1 is not available). 64-bit architectures and
327 // MIPS32r2 or later can use FGR64 though.
328 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
329 !Subtarget.isFP64bit());
331 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
332 const TargetRegisterClass *RC2 =
333 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
335 // We re-use the same spill slot each time so that the stack frame doesn't
336 // grow too much in functions with a large number of moves.
337 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2);
338 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI,
340 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI,
342 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, 0);
349 /// This method expands the same instruction that MipsSEInstrInfo::
350 /// expandExtractElementF64 does, for the case when ABI is fpxx and mfhc1 is not
351 /// available and the case where the ABI is FP64A. It is implemented here
352 /// because frame indexes are eliminated before MipsSEInstrInfo::
353 /// expandExtractElementF64 is called.
354 bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
355 MachineBasicBlock::iterator I,
357 // For fpxx and when mfhc1 is not available, use:
358 // spill + reload via ldc1
360 // The case where dmfc1 is available doesn't need to be handled here
361 // because it never creates a ExtractElementF64 node.
363 // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
364 // for odd-numbered double precision values (because the lower 32-bits is
365 // transferred with mfc1 which is redirected to the upper half of the even
366 // register). Unfortunately, we have to make this decision before register
367 // allocation so for now we use a spill/reload sequence for all
368 // double-precision values in regardless of being an odd/even register.
370 const TargetMachine &TM = MF.getTarget();
371 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
372 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
373 (FP64 && !Subtarget.useOddSPReg())) {
374 const MipsSEInstrInfo &TII = *static_cast<const MipsSEInstrInfo *>(
375 TM.getSubtargetImpl()->getInstrInfo());
376 const MipsRegisterInfo &TRI = *static_cast<const MipsRegisterInfo *>(
377 TM.getSubtargetImpl()->getRegisterInfo());
379 unsigned DstReg = I->getOperand(0).getReg();
380 unsigned SrcReg = I->getOperand(1).getReg();
381 unsigned N = I->getOperand(2).getImm();
383 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
384 // the cases where mfhc1 is not available). 64-bit architectures and
385 // MIPS32r2 or later can use FGR64 though.
386 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
387 !Subtarget.isFP64bit());
389 const TargetRegisterClass *RC =
390 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
391 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
393 // We re-use the same spill slot each time so that the stack frame doesn't
394 // grow too much in functions with a large number of moves.
395 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
396 TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC, &TRI,
398 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, N * 4);
405 MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
406 : MipsFrameLowering(STI, STI.stackAlignment()) {}
408 unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const {
409 static const unsigned EhDataReg[] = {
410 Mips::A0, Mips::A1, Mips::A2, Mips::A3
412 static const unsigned EhDataReg64[] = {
413 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
416 return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
419 void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
420 MachineBasicBlock &MBB = MF.front();
421 MachineFrameInfo *MFI = MF.getFrameInfo();
422 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
424 const MipsSEInstrInfo &TII =
425 *static_cast<const MipsSEInstrInfo *>(
426 MF.getTarget().getSubtargetImpl()->getInstrInfo());
427 const MipsRegisterInfo &RegInfo =
428 *static_cast<const MipsRegisterInfo *>(
429 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
431 MachineBasicBlock::iterator MBBI = MBB.begin();
432 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
433 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
434 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
435 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
436 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
438 // First, compute final stack size.
439 uint64_t StackSize = MFI->getStackSize();
441 // No need to allocate space on the stack.
442 if (StackSize == 0 && !MFI->adjustsStack()) return;
444 MachineModuleInfo &MMI = MF.getMMI();
445 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
446 MachineLocation DstML, SrcML;
449 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
451 // emit ".cfi_def_cfa_offset StackSize"
452 unsigned CFIIndex = MMI.addFrameInst(
453 MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
454 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
455 .addCFIIndex(CFIIndex);
457 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
460 // Find the instruction past the last instruction that saves a callee-saved
461 // register to the stack.
462 for (unsigned i = 0; i < CSI.size(); ++i)
465 // Iterate over list of callee-saved registers and emit .cfi_offset
467 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
468 E = CSI.end(); I != E; ++I) {
469 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
470 unsigned Reg = I->getReg();
472 // If Reg is a double precision register, emit two cfa_offsets,
473 // one for each of the paired single precision registers.
474 if (Mips::AFGR64RegClass.contains(Reg)) {
476 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
478 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
481 std::swap(Reg0, Reg1);
483 unsigned CFIIndex = MMI.addFrameInst(
484 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
485 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
486 .addCFIIndex(CFIIndex);
488 CFIIndex = MMI.addFrameInst(
489 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
490 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
491 .addCFIIndex(CFIIndex);
492 } else if (Mips::FGR64RegClass.contains(Reg)) {
493 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
494 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
497 std::swap(Reg0, Reg1);
499 unsigned CFIIndex = MMI.addFrameInst(
500 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
501 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
502 .addCFIIndex(CFIIndex);
504 CFIIndex = MMI.addFrameInst(
505 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
506 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
507 .addCFIIndex(CFIIndex);
509 // Reg is either in GPR32 or FGR32.
510 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
511 nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
512 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
513 .addCFIIndex(CFIIndex);
518 if (MipsFI->callsEhReturn()) {
519 const TargetRegisterClass *RC = STI.isABI_N64() ?
520 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
522 // Insert instructions that spill eh data registers.
523 for (int I = 0; I < 4; ++I) {
524 if (!MBB.isLiveIn(ehDataReg(I)))
525 MBB.addLiveIn(ehDataReg(I));
526 TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
527 MipsFI->getEhDataRegFI(I), RC, &RegInfo);
530 // Emit .cfi_offset directives for eh data registers.
531 for (int I = 0; I < 4; ++I) {
532 int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
533 unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
534 unsigned CFIIndex = MMI.addFrameInst(
535 MCCFIInstruction::createOffset(nullptr, Reg, Offset));
536 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
537 .addCFIIndex(CFIIndex);
541 // if framepointer enabled, set it to point to the stack pointer.
543 // Insert instruction "move $fp, $sp" at this location.
544 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO)
545 .setMIFlag(MachineInstr::FrameSetup);
547 // emit ".cfi_def_cfa_register $fp"
548 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
549 nullptr, MRI->getDwarfRegNum(FP, true)));
550 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
551 .addCFIIndex(CFIIndex);
555 void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
556 MachineBasicBlock &MBB) const {
557 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
558 MachineFrameInfo *MFI = MF.getFrameInfo();
559 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
561 const MipsSEInstrInfo &TII =
562 *static_cast<const MipsSEInstrInfo *>(
563 MF.getTarget().getSubtargetImpl()->getInstrInfo());
564 const MipsRegisterInfo &RegInfo =
565 *static_cast<const MipsRegisterInfo *>(
566 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
568 DebugLoc dl = MBBI->getDebugLoc();
569 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
570 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
571 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
572 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
574 // if framepointer enabled, restore the stack pointer.
576 // Find the first instruction that restores a callee-saved register.
577 MachineBasicBlock::iterator I = MBBI;
579 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
582 // Insert instruction "move $sp, $fp" at this location.
583 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
586 if (MipsFI->callsEhReturn()) {
587 const TargetRegisterClass *RC = STI.isABI_N64() ?
588 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
590 // Find first instruction that restores a callee-saved register.
591 MachineBasicBlock::iterator I = MBBI;
592 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
595 // Insert instructions that restore eh data registers.
596 for (int J = 0; J < 4; ++J) {
597 TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
602 // Get the number of bytes from FrameInfo
603 uint64_t StackSize = MFI->getStackSize();
609 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
612 bool MipsSEFrameLowering::
613 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
614 MachineBasicBlock::iterator MI,
615 const std::vector<CalleeSavedInfo> &CSI,
616 const TargetRegisterInfo *TRI) const {
617 MachineFunction *MF = MBB.getParent();
618 MachineBasicBlock *EntryBlock = MF->begin();
619 const TargetInstrInfo &TII =
620 *MF->getTarget().getSubtargetImpl()->getInstrInfo();
622 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
623 // Add the callee-saved register as live-in. Do not add if the register is
624 // RA and return address is taken, because it has already been added in
625 // method MipsTargetLowering::LowerRETURNADDR.
626 // It's killed at the spill, unless the register is RA and return address
628 unsigned Reg = CSI[i].getReg();
629 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
630 && MF->getFrameInfo()->isReturnAddressTaken();
631 if (!IsRAAndRetAddrIsTaken)
632 EntryBlock->addLiveIn(Reg);
634 // Insert the spill to the stack frame.
635 bool IsKill = !IsRAAndRetAddrIsTaken;
636 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
637 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
638 CSI[i].getFrameIdx(), RC, TRI);
645 MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
646 const MachineFrameInfo *MFI = MF.getFrameInfo();
648 // Reserve call frame if the size of the maximum call frame fits into 16-bit
649 // immediate field and there are no variable sized objects on the stack.
650 // Make sure the second register scavenger spill slot can be accessed with one
652 return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) &&
653 !MFI->hasVarSizedObjects();
656 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
657 void MipsSEFrameLowering::
658 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
659 MachineBasicBlock::iterator I) const {
660 const MipsSEInstrInfo &TII =
661 *static_cast<const MipsSEInstrInfo *>(
662 MF.getTarget().getSubtargetImpl()->getInstrInfo());
664 if (!hasReservedCallFrame(MF)) {
665 int64_t Amount = I->getOperand(0).getImm();
667 if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
670 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
671 TII.adjustStackPtr(SP, Amount, MBB, I);
677 void MipsSEFrameLowering::
678 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
679 RegScavenger *RS) const {
680 MachineRegisterInfo &MRI = MF.getRegInfo();
681 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
682 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
684 // Mark $fp as used if function has dedicated frame pointer.
686 MRI.setPhysRegUsed(FP);
688 // Create spill slots for eh data registers if function calls eh_return.
689 if (MipsFI->callsEhReturn())
690 MipsFI->createEhDataRegsFI();
692 // Expand pseudo instructions which load, store or copy accumulators.
693 // Add an emergency spill slot if a pseudo was expanded.
694 if (ExpandPseudo(MF).expand()) {
695 // The spill slot should be half the size of the accumulator. If target is
696 // mips64, it should be 64-bit, otherwise it should be 32-bt.
697 const TargetRegisterClass *RC = STI.hasMips64() ?
698 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
699 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
700 RC->getAlignment(), false);
701 RS->addScavengingFrameIndex(FI);
704 // Set scavenging frame index if necessary.
705 uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
706 estimateStackSize(MF);
708 if (isInt<16>(MaxSPOffset))
711 const TargetRegisterClass *RC = STI.isABI_N64() ?
712 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
713 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
714 RC->getAlignment(), false);
715 RS->addScavengingFrameIndex(FI);
718 const MipsFrameLowering *
719 llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
720 return new MipsSEFrameLowering(ST);